DP83822H [TI]
具有 16kV ESD 保护、支持工作温度范围的耐用型低功耗 10/100Mbps 以太网 PHY 收发器;型号: | DP83822H |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 16kV ESD 保护、支持工作温度范围的耐用型低功耗 10/100Mbps 以太网 PHY 收发器 以太网 局域网(LAN)标准 |
文件: | 总126页 (文件大小:3464K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DP83822HF, DP83822IF, DP83822H, DP83822I
ZHCSFD6F –JULY 2016 –REVISED JUNE 2021
DP83822 低功耗耐用型10/100Mbps 以太网物理层收发器
1 特性
3 说明
• 超稳健10/100Mbs PHY
DP83822 是一款超稳健、低功耗单端口 10/100Mbps
以太网 PHY,是苛刻工业环境的理想之选。它提供通
过标准双绞线电缆发送和接收数据或者连接到外部光纤
收发器所需的所有物理层功能。此外,DP83822 还可
通过标准 MII、RMII 或 RGMII 接口灵活地连接到
MAC。
– IEC 6100-4-2 ESD:+/- 8KV 接触放电
– IEC 6100-4-4 EFT:4KV 下的A 类
– CISPR 22 传导发射:B 类
– CISPR 22 辐射发射:B 类
– 工作温度:-40C - 125C
• MAC 接口:RGMII/RMII/MII
• 符合IEEE 802.3u 标准:100BASE-FX、
100BASE-TX 和10BASE-Te
• 灵活的电源选项
为了便于使用,DP83822 提供了集成电缆诊断工具、
内置自检和环回功能。它能够凭借自身的快速下行链路
检测和强制模式下的自动 MDIX 功能支持多条工业现
场总线。
– 低功耗单电源选项
DP83822 提供了一种创新型可靠方案来降低功耗,具
体将通过EEE、WoL 和其他可编程节能模式来实现。
• 1.8V AVD < 120mW
• 3.3V AVD < 220mW
DP83822 是一个功能丰富的引脚到引脚可升级选项,
适用于 TLK105、TLK106、TLK105L 和 TLK106L
10/100 Mbps 以太网PHY。
– 可用的I/O 电压:3.3 V/2.5 V/1.8 V
• 省电功能
– 节能以太网(EEE) IEEE 802.3az
– 支持WoL(局域网唤醒),具有魔术包检测功
能
DP83822 采用 32 引脚 5.00mm × 5.00mm VQFN 封
装。
– 可编程节能模式
器件信息
封装(1)
• IEEE 1588 时间戳的帧起始监测
• 诊断工具:电缆诊断、BIST(内置自检)、环回、
快速链路断开检测
封装尺寸(标称值)
5.00mm × 5.00mm
5.00mm × 5.00mm
5.00mm × 5.00mm
5.00mm × 5.00mm
器件型号
DP83822HF
VQFN (32)
• 强制模式下自动交叉
DP83822H
DP83822IF
DP83822I
VQFN (32)
VQFN (32)
VQFN (32)
2 应用
• 电机驱动器
• 工厂自动化、机器人和运动控制
• 电网基础设施
• 楼宇自动化
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
• 工业以太网现场总线
• 实时工业以太网应用,例如ProfiNET®
100BASE-FX
MII
RMII
RGMII
DP83822
10/100 Mbps
Ethernet PHY
MAC
10BASE-Te
100BASE-TX
RJ-45
25-MHz / 50-MHz
Clock Source
Status
LEDs
Copyright © 2016, Texas Instruments Incorporated
简化版原理图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNLS505
DP83822HF, DP83822IF, DP83822H, DP83822I
ZHCSFD6F –JULY 2016 –REVISED JUNE 2021
www.ti.com.cn
Table of Contents
7.19 10BASE-Te Jabber Timing......................................15
7.20 100BASE-TX Transmit Latency Timing.................. 15
7.21 100BASE-TX Receive Latency Timing................... 15
7.22 Timing Diagrams.....................................................16
7.23 Typical Characteristics............................................22
8 Detailed Description......................................................23
8.1 Overview...................................................................23
8.2 Functional Block Diagram.........................................24
8.3 Feature Description...................................................25
8.4 Device Functional Modes..........................................28
8.5 Programming............................................................ 45
8.6 Register Maps...........................................................50
9 Application and Implementation................................101
9.1 Application Information........................................... 101
9.2 Typical Applications................................................ 101
10 Power Supply Recommendations............................107
10.1 Power Supply Characteristics...............................107
11 Layout......................................................................... 112
11.1 Layout Guidelines..................................................112
11.2 Layout Example.....................................................115
12 Device and Documentation Support........................116
12.1 Related Links........................................................ 116
12.2 接收文档更新通知................................................. 116
12.3 支持资源................................................................116
12.4 Trademarks........................................................... 116
12.5 Electrostatic Discharge Caution............................116
12.6 术语表................................................................... 116
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 9
7.1 Absolute Maximum Ratings........................................ 9
7.2 ESD Ratings............................................................... 9
7.3 Recommended Operating Conditions.........................9
7.4 Thermal Information..................................................10
7.5 Electrical Characteristics...........................................10
7.6 Timing Requirements, Power-Up Timing...................11
7.7 Timing Requirements, Power-Up With Unstable
XI Clock.......................................................................12
7.8 Timing Requirements, Reset Timing.........................12
7.9 Timing Requirements, Serial Management Timing...12
7.10 Timing Requirements, 100 Mbps MII Transmit
Timing..........................................................................12
7.11 Timing Requirements, 100 Mbps MII Receive
Timing..........................................................................12
7.12 Timing Requirements, 10 Mbps MII Transmit
Timing..........................................................................13
7.13 Timing Requirements, 10 Mbps MII Receive
Timing..........................................................................13
7.14 Timing Requirements, RMII Transmit Timing..........14
7.15 Timing Requirements, RMII Receive Timing...........14
7.16 Timing Requirements, RGMII..................................14
7.17 Normal Link Pulse Timing....................................... 15
7.18 Auto-Negotiation Fast Link Pulse (FLP) Timing......15
Information.................................................................. 117
13.1 Package Option Addendum.................................. 118
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision E (March 2019) to Revision F (June 2021)
Page
• 更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1
• 更新了“特性”部分以突出显示关键特性。....................................................................................................... 1
• 添加了商标..........................................................................................................................................................1
• Added clarification on Tx_CLK state in reset in pin function table......................................................................4
• Added clarification on TX_CLK state in reset in IO Pins State During Reset table............................................ 4
• Added 100BASE-FX output parameters ..........................................................................................................10
• Added AVO footnote......................................................................................................................................... 11
• Added timing requirement for reset after stabilization of XI clock. ...................................................................12
• Added RMII transmit latency number .............................................................................................................. 15
• Added RGMII transmit latency number ............................................................................................................15
• Added RMII receive latency number.................................................................................................................15
• Added RGMII receive latency number..............................................................................................................15
• Updated details of earlier "reserved" bits of register 0x000B and 0x003F....................................................... 50
• Updated description for register 0x0015 and 0x001C...................................................................................... 50
• Added register description of following registers:
0x101,0x0106,0x0107,0x0126,0x04D4,0x0121,0x0122,0x0124,0x010F,0x0111,0x0129,0x0130,0x0410,0x041
6,0x0418,0x0450,0x040D ,0x041F,0x0421...................................................................................................... 50
• Added further information to registers 0x0000,0x0001,0x0469,0x0703C.........................................................50
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ZHCSFD6F –JULY 2016 –REVISED JUNE 2021
• Updated default values for
registers :0x0008,0x000A,0x0010,0x0017,0x001E,0x0155,0x0215,0x0462,0x3000,0x3001,0x3014,0x3016....
50
• Changed TPI network diagram to include optional ferrite bead for EMC improvement..................................102
Changes from Revision D (March 2019) to Revision E (March 2019)
Page
• Changed to fix typos on Table 1 ........................................................................................................................ 4
Changes from Revision C (April 2018) to Revision D (March 2019)
Page
• Changed the description for LED_1 in Pin Functions table................................................................................ 4
• Changed reset pin state for RX_D[3:0] and LED_1 pins in IO Pins State During Reset.................................... 4
• Added XO and XI capacitance..........................................................................................................................10
• Added Test Conditions to PMD OUTPUT section of the Electrical Characteristics Table.................................10
• Changed Parameter descriptions and units in Reset Timing Requirements table to match device
performance......................................................................................................................................................12
• Changed NOTE for 100BASE-FX Signal Detect pin polarity from Active LOW to Active HIGH.......................39
• Changed LED_0 strap modes to remove Mode 2 and Mode 3. ...................................................................... 45
• Changed strap description for SD_EN pin from Active LOW to Active HIGH...................................................45
• Deleted LED_0 configuration table...................................................................................................................45
• Changed LED_1 Configuration table to merge LED_0 and LED_1 configuration into a single table for clarity....
45
• Changed note in 节8.5.2 section to clarify LED connections...........................................................................49
• Added registers 0x0106, 0x0107, 0x010F, 0x0114, 0x0116, 0x0126, 0x04D4, 0x04D5, and 0x04D6 ............ 50
• Added 100Base-TX MII power consumption data for -40oC and 125oC.........................................................107
Changes from Revision B (March 2018) to Revision C (April 2018)
Page
• Changed TX_D[1:0] back to TX_D[3:0]............................................................................................................ 28
• Changed RX_D[1:0] back to RX_D[3:0]........................................................................................................... 28
Changes from Revision A (August 2016) to Revision B (March 2018)
Page
• 根据最新TI 文档和翻译标准更新了数据表文本和格式....................................................................................... 1
• Updated description of pin 24 and changed pin type from: I/O, PD to: I/O ........................................................4
• Added MII: 100BASE-TX Transmit Latency Timing table ................................................................................ 15
• Added MII: 100BASE-TX Receive Latency Timing table .................................................................................15
• Device Power-Up Timing diagram modified to include start voltage limits....................................................... 16
• Added the 100BASE-TX Transmit Latency Timing graphic ............................................................................. 16
• Added the 100BASE-TX Receive Latency Timing graphic ..............................................................................16
• Changed the Functional Block Diagram .......................................................................................................... 24
• Changed TX_D[3:0] to TX_D[1:0].....................................................................................................................28
• Changed RX_D[3:0] to RX_D[1:0]....................................................................................................................28
• Added note to the 100BASE-FX Receive section and changed the SD_DIS pin to SD_EN............................39
• Changed RX_ER strap function from: AMDIX_EN (SD_DIS) to: AMDIX_EN (SD_EN)...................................45
• Added the Detailed Design Procedure section for the TPI Network Circuit typical application...................... 102
• Switched the order of the typical applications.................................................................................................103
• Added note to the Oscillator section ..............................................................................................................103
• Changed the Power Connections graphic ..................................................................................................... 107
Changes from Revision * (August 2016) to Revision A (August 2016)
Page
• 将“产品预发布”更改为“量产数据发布”....................................................................................................... 1
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DP83822HF, DP83822IF, DP83822H, DP83822I
ZHCSFD6F –JULY 2016 –REVISED JUNE 2021
www.ti.com.cn
5 Device Comparison Table
PART
NUMBER
100BASE-FX
SUPPORT
OPERATING
TEMPERATURE
DP83822HF
DP83822H
DP83822IF
DP83822I
Yes
No
-40°C to 125°C
-40°C to 125°C
-40°C to 85°C
-40°C to 85°C
Yes
No
6 Pin Configuration and Functions
24
23
22
21
20
19
18
17
RX_CLK 25
16 RBIAS
RX_DV / RX_CTRL 26
CRS / CRS_DV 27
RX_ER 28
15 NC
14 AVD
13 NC
GND
COL / GPIO2 29
RX_D0 30
12 TD_P
11 TD_M
10 RD_P
RX_D1 31
RX_D2 32
9
RD_M
1
2
3
4
5
6
7
8
图6-1. RHB Package
32-Pin VQFN
Top View
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ZHCSFD6F –JULY 2016 –REVISED JUNE 2021
表6-1. Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
MAC INTERFACE
MII Transmit Clock: MII Transmit Clock provides a 25-MHz reference
clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps
speed. Note that in MII mode, this clock has constant phase referenced to
the reference clock. Applications requiring such constant phase may use
this feature.
O, Hi-Z
Hi-Z
TX_CLK
2
Unused in RMII Mode
RGMII Transmit Clock: The clock is sourced from the MAC layer to the
PHY. When operating at 100-Mbps speed, this clock must be 25-MHz.
When operating at 10-Mbps speed, this clock must be 2.5-MHz.
Note : When in reset, TX_CLK is an output pin and low value is driven on
it. Only once device is out of reset, TX_CLK is configured as input.
I, PD
Transmit Enable: TX_EN is presented on the rising edge of the TX_CLK.
TX_EN indicates the presence of valid data inputs on TX_D[3:0] in MII
mode and on TX_D[1:0] in RMII mode. TX_EN is an active high signal.
RGMII Transmit Control: TX_CTRL combines transmit enable and
transmit error signals. TX_EN is presented on the rising edge of TX_CLK
and TX_ER on the falling edge of TX_CLK.
TX_EN / TX_CTRL
3
I, PD
I, PD
TX_D0
TX_D1
TX_D2
TX_D3
4
5
6
7
Transmit Data: In MII mode, the transmit data nibble received from the
MAC is synchronous to the rising edge of TX_CLK. In RMII mode,
TX_D[1:0] received from the MAC is synchronous to the rising edge of the
reference clock. In RGMII mode, the transmit data nibble received from
the MAC is synchronous to the rising edge of TX_CLK.
MII Receive Clock: MII Receive Clock provides a 25-MHz reference
clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps
speed, which is derived from the received data stream.
Unused in RMII Mode
RGMII Receive Clock:RGMII Receive Clock provides a 25-MHz
reference clock for 100-Mbps speed and a 2.5-MHz reference clock for
10-Mbps speed, which is derived from the receive data stream.
RX_CLK
25
26
28
O
Receive Data Valid: This pin indicates valid data is present on the
RX_D[3:0] for MII mode and on RX_D[1:0] in RMII mode, independent
from Carrier Sense.
RGMII Receive Control: RX_CTRL combines receive data valid and
receive error signals. RX_DV is presented on the rising edge of RX_CLK
and RX_ER on the falling edge of RX_CLK.
RX_DV / RX_CTRL
O, S-PD
O, S-PU
Receive Error: This pin indicates that an error symbol has been detected
within a received packet in both MII and RMII mode. In MII mode, RX_ER
is asserted high synchronously to the rising edge of RX_CLK. In RMII
mode, RX_ER is asserted high synchronously to the rising edge of the
reference clock. This pin is not required to be used by the MAC in MII or
RMII because the PHY is corrupting data on a receive error.
Unused in RGMII Mode
RX_ER
RX_D0
RX_D1
RX_D2
30
31
32
Receive Data: Symbols received on the cable are decoded and
presented on these pins synchronous to the rising edge of RX_CLK. They
contain valid data when RX_DV is asserted. A nibble RX_D[3:0] is
received in MII and RGMII modes. 2-bits RX_D[1:0] is received in RMII
Mode. PHY address pins PHY_AD[4:1] are multiplexed with RX_D[3:0],
and are pulled-down. PHY_AD[0] (LSB of the address) is multiplexed with
COL on pin 29, and is pulled up. If no external pullup or pulldown is
present, the default PHY address is 0x01.
O, S-PD
O, S-PU
RX_D3 / GPIO3
1
Carrier Sense: In MII mode this pin is asserted high when the receive or
transmit medium is non-idle.
Carrier Sense / Receive Data Valid: In RMII mode, this pin combines
the RMII Carrier and Receive Data Valid indications.
Unused in RGMII Mode
CRS / CRS_DV
27
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表6-1. Pin Functions (continued)
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
Collision Detect: For Full-Duplex mode, this pin is always LOW. In Half-
Duplex mode, this pin is asserted HIGH only when both transmit and
receive media are non-idle.
COL / GPIO2
29
I/O, S-PU
Unused in RMII Mode
SERIAL MANAGEMENT INTERFACE
Management Data Clock: Synchronous clock to the MDIO serial
management input/output data. This clock may be asynchronous to the
MAC transmit and receive clocks. The maximum clock rate is 25 MHz.
There is no minimum clock rate.
MDC
20
19
I
Management Data I/O: Bidirectional management data signal that may
be sourced by the management station or the PHY. This pin requires a
2.2-kΩpullup resistor.
MDIO
I/O
Interrupt / Power Down: Register access is required for this pin to be
configured either as power down or as an interrupt. The default function
of this pin is power down. When this pin is configured for a power down
function, an active low signal on this pin places the device in power-down
mode.
INT/PWDN
8
I/O, OD
When this pin is configured as an interrupt pin, this pin is asserted low
when an interrupt condition occurs. The pin has an open-drain output with
a weak internal pullup. Some applications may require an external pullup
resistor.
RESET: This pin is an active low reset input that initializes or re-initializes
all the internal registers of the PHY. Asserting this pin low for at least 10
µs will force a reset process to occur.
RESET
18
I, PU
CLOCK INTERFACE
Crystal / Oscillator Input
MII reference clock: Reference clock 25-MHz ±100 ppm-tolerance
crystal or oscillator input. The device supports either an external crystal
resonator connected across pins XI and XO, or an external CMOS-level
oscillator connected to pin XI only.
RMII reference clock: Reference clock 50-MHz ±100 ppm-tolerance
CMOS-level oscillator in RMII Slave mode. Reference clock 25-MHz ±100
ppm-tolerance crystal or oscillator in RMII Master mode.
RGMII reference clock:Reference clock 25-MHz ±100 ppm-tolerance
crystal or oscillator input. The device supports either an external crystal
resonator connected across pins XI and XO, or an external CMOS-level
oscillator connected to pin XI only.
XI
23
I
Crystal Output: Reference Clock output. XO pin is used for crystal only.
This pin should be left floating when a CMOS-level oscillator is connected
to XI.
XO
22
17
O
GPIO AND LED INTERFACE
Mode 1 (Default): LINK Indication, LED indicates the status of the link.
When the link is good, LED is ON. When the link is down, LED is OFF.
Mode 2: ACT Indication, LED indicates transmit and receive activity in
addition to the status of the link. The LED is ON when link is good. The
LED blinks when the transmitter or receiver is active.
LED_0
O, S-PU
Mode 1 (Default): This pin is tri-state.
Mode 2: SPEED Indication, LED indicates the speed of the link. If speed
is 100 Mbps, LED is ON. If speed is 10 Mbps, LED is OFF. External Pull
resistors are required when LED is connected to this pin.
GPIO1: This pin can be used as a GPIO when using register access.
Signal Detect: This pin acts as Signal Detect in 100BASE-FX mode and
shall be connected with Optical Transceiver. Signal Detect high level will
be the VDDIO voltage level.
LED_1 / GPIO1
24
I/O, S-PD
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表6-1. Pin Functions (continued)
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
MII Mode: COL pin can be used to drive an LED when operating in Full-
Duplex mode. Register access is required for LED configuration.
RMII Mode: This pin can be used as an LED when using register access.
RGMII Mode:This pin can be used as an LED when using register
access.
COL / GPIO2
29
I/O, S, PU
GPIO2: This pin can be used as a GPIO when using register access.
MII Mode: RX_D3 will remain as RX_D3 because it is required for MII
mode.
RMII Mode: RX_D3 pin can be configured to drive an LED. Register
access is required for LED configuration.
RX_D3 / GPIO3
1
I/O, S-PD
RGMII Mode:RX_D3 will remain as RX_D3 because it is required for
RGMII mode.
GPIO3: This pin can be used as a GPIO when using register access.
MEDIA DEPENDENT INTERFACE
TD_M
11
12
9
Differential Transmit Output (PMD): These differential outputs can be
automatically configured to either 10BASE-Te, 100BASE-TX, or
100BASE-FX signaling or forced into a specific signaling mode.
A
A
TD_P
RD_M
RD_P
Differential Receive Input (PMD): These differential inputs are
automatically configured to accept either 10BASE-Te, 100BASE-TX, or
100BASE-FX signaling or forced into a specific signaling mode.
10
POWER AND GROUND PINS
VDDIO
AVD
21
14
P
P
I/O Supply: 3.3 V, 2.5 V, or 1.8 V
Analog Supply: 3.3 V or 1.8 V
Ground
Ground
Pad
GND
P
I
Bias Resistor Connection. A 4.87-kΩ±1% resistor must be connected
from RBIAS to GND.
RBIAS
16
OTHER PINS
NC
NC
13
15
NC
NC
Leave Floating
Leave Floating
This pin can be left floating when not in used. External Pull resistors are
required when LED is connected to this pin.
LED_1 / GPIO1
24
I/O, S-PD
(1) The definitions below define the functionality of the I/O cells for each pin.
•
•
•
•
•
•
Type: I - Input
Type: O - Output
Type: I/O - Input/Output
Type OD - Open Drain
Type: PD, PU - Internal Pulldown/Pullup
Type: S-PU, S-PD - Strapping Pin (All strap pins have weak internal pullups or pulldowns. If the default strap value is needed to be
changed then an external 2.2-kΩresistor should be used)
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表6-2. IO Pins State During Reset
PIN NAME
MDIO
NO.
19
20
8
TYPE
PU/PD/HiZ
I
I
I
Hi-Z
MDC
PD
INT_N
PU
RESET_N
TX_CLK (1)
TX_EN
TX_D3
TX_D2
TX_D1
TX_D0
LED_0
LED_1
CRS
18
2
—
O
—
PD
PD
PD
PD
PD
PD
PU
PD
PU
PU
PU
PD
PD
PD
PD
PD
PD
3
I
7
I
6
I
5
I
4
I
17
24
27
29
28
26
1
Strap
Strap
Strap
Strap
Strap
Strap
Strap
Strap
Strap
Strap
O
COL
RX_ER
RX_DV
RX_D3
RX_D2
RX_D1
RX_D0
RX_CLK
32
21
30
25
(1) When in reset, TX_CLK is an output pin and low value is driven
on it. In RGMII mode, once device is out of reset, Tx_CLK is
configured as input.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
3.8
3.8
6
UNIT
AVD
–0.5
–0.5
–0.5
–0.5
–0.5
VDDIO
Input voltage
V
TD–, TD+, RD–, RD+
Other Inputs
3.8
3.8
135
150
DC output voltage
All pins
V
TJ
Operating junction temperature
Storage temperature
°C
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under 节7.3.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±3000
UNIT
All pins except pins 9, 10, 11, and 12
Pins 9, 10, 11, and 12
Human-body model (HBM), per ANSI/
ESDA/JEDEC JS-001(1)
±16000
V(ESD) Electrostatic discharge
V
Charged-device model (CDM), per
JEDEC specification JESD22-C101(2)
All pins
±1500
±8000
IEC 61000-4-2(3)
Pins 9, 10, 11, and 12
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) IEC61000-4-2; 150 pF and 330 Ω, Contact Discharge, Class B.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.71
2.375
3.15
3.15
1.71
NOM
1.8
MAX UNIT
Supply Voltage I/O (1.8-V Option)
Supply Voltage I/O (2.5-V Option)
Supply Voltage I/O (3.3-V Option)
Supply Voltage Analog (3.3-V Option)
Supply Voltage Analog (1.8-V Option)
1.89
VDDIO
AVD(1)
2.5
2.625
3.45
3.45
1.89
V
V
3.3
3.3
1.8
Supply Voltage Center Tap (3.3-V Option)
Magnetic Center Tap
3.15
1.71
3.3
1.8
3.45
1.89
Center Tap (CT)
V
(1)
Supply Voltage Analog (1.8V Option)
Magnetic Center Tap
Ambient Temperature: DP83822I and DP83822IF
Ambient Temperature: DP83822H and DP83822HF
-40
-40
85
TA
°C
125
(1) Analog supply (AVD) and magnetic center tap must be at the same potential.
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7.4 Thermal Information
DP83822
RHB (VQFN)
32 PINS
41.0
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
35.5
14.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
ψJT
14.0
ψJB
RθJC(bot)
5.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.3-V VDDIO
VOH
IOH = –4 mA
VDDIO = 3.3-V ±5%
High level output voltage
low level output voltage
2.4
V
V
IOL = 4 mA
VDDIO = 3.3-V ±5%
VOL
0.4
0.8
VIH
VIL
High level input voltage
Low level input voltage
VDDIO = 3.3-V ±5%
VDDIO = 3.3-V ±5%
1.7
V
V
2.5-V VDDIO
IOH = –4 mA
VDDIO = 2.5-V ±5%
VOH High level output voltage
VDDIO × 0.8
V
V
IOL = 4 mA
VDDIO = 2.5-V ±5%
VOL
Low level output voltage
0.4
0.7
VIH
VIL
High level input voltage
Low level input voltage
VDDIO = 2.5-V ±5%
VDDIO = 2.5-V ±5%
1.5
V
V
1.8-V VDDIO
IOH = –2 mA
VDDIO = 1.8-V ±5%
VOH High level output voltage
V
V
VDDIO –0.4
IOL = 2 mA
VDDIO = 1.8-V ±5%
VOL
Low level output voltage
0.4
0.5
VIH
VIL
High level input voltage
Low level input voltage
VDDIO = 1.8-V ±5%
VDDIO = 1.8-V ±5%
1.3
V
V
DC CHARACTERISTICS
IIH Input high current (VIN = VCC)
IIL
10
20
10
10
20
–40°C to 85°C
–10
–20
–10
–10
–20
μA
μA
μA
85°C to 125°C
Input low current (VIN = GND)
–40°C to 125°C
-40°C to 85°C
85°C to 125°C
TRI-STATE output current
IOZ
(VOUT = VCC, VOUT = GND)
CXI/XO
CIN
XO and XI capacitance(1)
Input capacitance(1)
0.8
5
pF
pF
pF
COUT
Output capacitance(1)
5
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7.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RPU-POR Integrated pullup resistance
during latch-in (RESET and
Power-Up)
Pins: RX_ER, LED_0, CRS, and
COL
kΩ
37.5
50
62.5
RPull-Up
Integrated pullup resistance
6.75
6.75
9
9
11.25
11.25
kΩ
kΩ
RPull-Down Integrated pulldown resistance
PMD OUTPUTS
VOD
MDI 10BASE-Te swing
VOD can be controlled through
表8-81
Vpeak
Vpeak
1.54
0.95
98%
0.9
1.75
1.96
1.05
102%
1.1
VOD
MDI 100BASE-TX swing
VOD can be controlled through
表8-81
1
100%
1
MDI 100BASE-TX voltage
symmetry
VODsym
VOD
MDI 100BASE-FX transmitter
swing (1)
Differential output voltage pk-
pk(2)
Vpk-pk
ns
Tr/f
MDI 100BASE-FX transmitter
rise/fall time(1)
10%-90% Rise/Fall Time
0.5
1
1.5
Tj_out
Vin
MDI 100BASE-FX transmitter
total jitter (1)
ns
1.4
MDI 100BASE-FX receiver input Input differential voltage pk-pk
swing requirement (1)
Vpk-pk
UI
0.22
1.8
Tj_in
MDI 100BASE-FX receiver input Input jitter tolerance pk-pk
jitter requirement (1)
0.45
(1) Ensured by production test, characterization or design.
(2) Configurable through register 0x0403. Output variance is in range of +/-10%
7.6 Timing Requirements, Power-Up Timing
See (1) (2)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AVD (analog supply) ramp delay post VDDIO
(digital supply) ramp.
T1
Time from start of supply ramp
100
ms
–100
AVD and VDDIO potential must not exceed 0.3
V prior to supply ramp.(3)
VDDIO ramp time
AVD ramp time
100
100
ms
ms
Post power-up stabilization time prior to MDC
preamble for register accesses.
MDC preamble coming in any time after this max serial management initialization
wait time will be valid.
MDIO is pulled high for 32-bit
T2
200
200
ms
Hardware configuration latch-in time for power
up
T3
T4
T5
ms
ns
s
Hardware configuration pins transition to output
drivers
64
Fast Link Pulse transmission delay post power
up
1.5
(1) Ensured by production test, characterization or design.
(2) See 图7-1.
(3) AVD ramping up after VDDIO ramp completion is preferred to avoid false detection of lower level of VDDIO in any corner case.
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7.7 Timing Requirements, Power-Up With Unstable XI Clock
See (1)
.
PARAMETER
Reset application after XI stabilization
Reset pulse width
MIN
1
NOM
MAX
UNIT
us
T1
T2
10
us
(1) See 图7-2
7.8 Timing Requirements, Reset Timing
See (1) (2)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
RESET pulse width
XI clock must be stable for a minimum
of 1 μs during RESET pulse low time
T1
T2
T3
T4
T5
10
μs
Post RESET stabilization time prior to MDIO is pulled high for 32-bit serial
MDC preamble for register accesses
2
ms
ns
ns
s
management initialization
Hardware configuration latch-in time
for RESET
120
64
Hardware configuration pins transition
to output drivers
Fast Link Pulse transmission delay
post RESET
1.5
(1) Ensured by production test, characterization or design.
(2) See 图7-3.
7.9 Timing Requirements, Serial Management Timing
See (1) (2)
.
PARAMETER
MDC to MDIO (Output) Delay Time
MDIO (Input) to MDC Setup Time
MDIO (Input) to MDC Hold Time
MDC Frequency
MIN
0
TYP
MAX
UNIT
T1
T2
T3
T4
10
ns
ns
10
10
ns
2.5
25
MHz
(1) Ensured by production test, characterization or design.
(2) See 图7-4.
7.10 Timing Requirements, 100 Mbps MII Transmit Timing
See (1) (2)
.
PARAMETER
TX_CLK High / Low Time
MIN
16
10
0
TYP
MAX
UNIT
ns
T1
T2
T3
20
24
TX_D[3:0], TX_EN Data Setup to TX_CLK
TX_D[3:0], TX_EN Data Hold from TX_CLK
ns
ns
(1) Ensured by production test, characterization or design.
(2) See 图7-5.
7.11 Timing Requirements, 100 Mbps MII Receive Timing
See (1) (2)
.
PARAMETER
RX_CLK High / Low Time
RX_D[3:0], RX_DV and RX_ER Delay from RX_CLK rising
MIN
16
TYP
MAX
24
UNIT
ns
T1
T2
20
10
30
ns
(1) Ensured by production test, characterization or design.
(2) See 图7-6.
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7.12 Timing Requirements, 10 Mbps MII Transmit Timing
See (1) (2)
.
PARAMETER
TX_CLK High / Low Time
MIN
190
25
TYP
MAX
UNIT
ns
T1
T2
T3
200
210
TX_D[3:0], TX_EN Data Setup to TX_CLK
TX_D[3:0], TX_EN Data Hold from TX_CLK
ns
0
ns
(1) Ensured by production test, characterization or design.
(2) See 图7-7.
7.13 Timing Requirements, 10 Mbps MII Receive Timing
See (1) (2)
.
PARAMETER
RX_CLK High / Low Time
RX_D[3:0], RX_DV and RX_ER Delay from RX_CLK rising
MIN
160
100
TYP
MAX
240
UNIT
ns
T1
T2
200
300
ns
(1) Ensured by production test, characterization or design.
(2) See 图7-8.
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7.14 Timing Requirements, RMII Transmit Timing
See (1) (2)
.
PARAMETER
MIN
TYP
MAX
UNIT
ns
T1
T2
T3
T1
XI Clock Period
20
TX_D[1:0] and TX_EN Data Setup to XI rising
1.4
2
ns
TX_D[1:0] and TX_EN Data Hold from XI rising
RMII Master Clock (RX_D3 Clock) Period
ns
20
ns
RMII Master Clock (RX_D3 Clock) Duty Cycle
35%
65%
T2
T3
TX_D[1:0] and TX_EN Data Setup to RMII Master Clock rising
TX_D[1:0] and TX_EN Data Hold from RMII Master Clock rising
4
2
ns
ns
(1) Ensured by production test, characterization or design.
(2) See 图7-9.
7.15 Timing Requirements, RMII Receive Timing
See (1) (2)
.
PARAMETER
MIN
TYP
MAX
UNIT
ns
T1
T2
T1
XI Clock Period
20
RX_D[1:0], CRS_DV, RX_DV and RX_ER Delay from XI rising
RX_CLK Clock Period
4
14
ns
20
10
20
ns
RX_D[1:0], CRS_DV, RX_DV and RX_ER Delay from RX_CLK rising
Note: While working in 'RMII Receive Clock' mode, bit[0] in register
0x000A
T2
T1
4
14
ns
ns
RMII Master Clock (RX_D3 Clock) Period
RMII Master Clock (RX_D3 Clock) Duty Cycle
35%
4
65%
14
RX_D[1:0], CRS_DV, RX_DV and RX_ER Delay from RMII Master
Clock rising
T2
10
ns
(1) Ensured by production test, characterization or design.
(2) See 图7-10.
7.16 Timing Requirements, RGMII
See (1) (5)
.
PARAMETER
MIN
–500
1
TYP
0
MAX
UNIT
ps
Data to Clock output Skew (at Transmitter)(2)
Data to Clock input Skew (at Receiver)(2)
Data to Clock output Setup (at Transmitter - integrated delay)(3)
Data to Clock output Hold (at Transmitter - integrated delay)(3)
Data to Clock input Setup (at Receiver - integrated delay)(3)
Data to Clock input Hold (at Receiver - integrated delay)(3)
Clock Cycle Duration 10 Mbps
SkewT
SkewR
SetupT
HoldT
1.8
2
ns
1.2
1.2
1
ns
2
ns
SetupR
HoldR
2
ns
1
2
ns
Tcyc_10
Tcyc_100
Duty_T
Tr / Tf
360
36
400
40
50%
440
44
ns
Clock Cycle Duration 100 Mbps
ns
Duty Cycle for 10/100 Mbps(4)
40%
60%
750
Rise / Fall Time (20-80%)
ps
(1) Ensured by production test, characterization or design.
(2) When operating without RGMII internal delay, the PCB design requires clocks to be routed such that an additional trace delay of
greater than 1.5 ns is added to the associated clock signal.
(3) Device may operate with or without internal delay.
(4) The duty cycle may be stretched or shrunk during speed changes or while transitioning to a received packet's clock domain as long as
minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between.
(5) See 图7-11 and 图7-12.
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7.17 Normal Link Pulse Timing
See (1) (2)
.
PARAMETER
MIN
TYP
16
MAX
UNIT
ms
T1
T2
Pulse Period
Pulse Width
100
ns
(1) Ensured by production test, characterization or design.
(2) See 图7-13.
7.18 Auto-Negotiation Fast Link Pulse (FLP) Timing
See (1) (2)
.
PARAMETER
Clock Pulse to Clock Pulse Period
Clock Pulse to Data Pulse Period
Clock / Data Pulse Width
MIN
TYP
125
62
MAX
UNIT
μs
μs
ns
T1
T2
T3
T4
T5
114
16
FLP Burst to FLP Burst Period
FLP Burst Width
ms
2
ms
(1) Ensured by production test, characterization or design.
(2) See 图7-14.
7.19 10BASE-Te Jabber Timing
See (1) (2)
.
PARAMETER
Jabber activation time
Jabber deactivation time
MIN
TYP
100
500
MAX
UNIT
ms
T1
T2
ms
(1) Ensured by production test, characterization or design.
(2) See 图7-15.
7.20 100BASE-TX Transmit Latency Timing
See 图7-16.
PARAMETER
MIN
TYP
MAX
UNIT
TX_CLK rising edge with TX_EN asserted to MDI start
of /J/ symbol
T1
MII
48
56
ns
RMII(1)
102
170
ns
ns
RGMII(2)
(1) With FAST_RXDV enabled. Register<0x0009>=0x0002.
(2) With FAST_RXDV enabled. Register<0x0009>=0x0002. and Register<0x0457>=0x0410
7.21 100BASE-TX Receive Latency Timing
See 图7-17.
PARAMETER
MIN
TYP
MAX
UNIT
MDI start of /J/ symbol to RX_CLK rising edge with
RX_DV asserted
T2
MII(1)
194
218
ns
RMII(1)
272
159
ns
ns
RGMII(2)
(1) With FAST_RXDV enabled. Register<0x0009>=0x0002.
(2) With FAST_RXDV enabled. Register<0x0009>=0x0002. and Register<0x0457>=0x0410
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7.22 Timing Diagrams
tT1t
VVDDIO
t0.3 Vt
-0.3 Vt
VAVD/CT
t0.3 Vt
-0.3 Vt
XI
Hardware
RESET_N
32 Clocks
tT2t
MDC
tT3t
Latch-in
tT4
Active
I/O Pins
tT5t
FLP Burst
图7-1. Power-Up Timing
VVDD
XI
T1
T2
RESETN
图7-2. Power-Up With Unstable XI Input
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VVDD
XI
tT1
Hardware
RESET_N
32 Clocks
tT2
tT3
MDC
Latch-in
tT4
Active
I/O Pins
tT5t
FLP Burst
图7-3. Reset Timing
MDC
tT4t
tT1t
MDIO
(output)
MDC
tT2t
tT3t
MDIO
(input)
Valid Data
图7-4. Serial Management Timing
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tT1t
tT1t
tT1t
tT1t
tT1t
TX_CLK
tT2t
tT3t
TX_D [3:0]
TX_EN
Valid Data
图7-5. 100-Mbps Transmit Timing
tT1t
RX_CLK
tT2t
RX_D [3:0]
RX_DV
RX_ER
Valid Data
图7-6. 100-Mbps Receive Timing
tT1t
TX_CLK
tT2t
tT3t
TX_D [3:0]
TX_EN
Valid Data
图7-7. 10-Mbps Transmit Timing
tT1t
RX_CLK
tT2t
RX_D [3:0]
RX_DV
RX_ER
Valid Data
图7-8. 10-Mbps Receive Timing
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tT1t
XI
Master Clock
tT2t
tT3t
TX_D[1:0]
TX_EN
Valid Data
图7-9. RMII Transmit Timing
tT1t
XI
RX_CLK
Master Clock
tT2t
RX_D[1:0]
CRS_DV
RX_DV
Valid Data
RX_ER
图7-10. RMII Receive Timing
tTcyct
TX_CLK
(at transmitter)
SkewT
TX_D[3:0]
Valid Data
TX_CTRL
TX_EN
TX_ER
TX_EN
SkewR
TX_CLK
(at receiver)
图7-11. RGMII Transmit Timing
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tTcyct
Internal
Delay
Added
RX_CLK
(at transmitter)
SetupT
RX_D[3:0]
Valid Data
tHoldTt
RX_CTRL
RX_DV
SetupR
RX_ER
RX_DV
HoldR
RX_CLK
(at receiver)
图7-12. RGMII Receive Timing
tT1t
T2
Normal Link
Pulse(s)
图7-13. Normal Link Pulse(s) Timing
tT1t
tT2t
T3
T3
Fast Link
Pulse(s)
Clock
Pulse
Data
Pulse
Clock
Pulse
Data
Pulse
tT4t
tT5t
FLP Bursts
FLP Burst
图7-14. Fast Link Pulse Timing
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TX_EN
tT2t
tT1t
PMD Output
Pair
COL
图7-15. 10BASE-Te Jabber Timing
TX_CLK
TX_EN
TX_D[*:0]
T1
PMD Output
J/K
DATA
IDLE
图7-16. 100BASE-TX Transmit Latency Timing
PMD Input Pair
IDLE
(J/K)
DATA
T2
RX_DV
RX_CLK
图7-17. 100BASE-TX Receive Latency Timing
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7.23 Typical Characteristics
mV per Div
nS per Div
20 ns
mV per Div
nS per Div
80 ns
500 mV
500 mV
图7-18. 100BASE-TX PMD Eye Waveform
图7-19. 10BASE-Te Link Pulse Waveform
mV per Div
nS per Div
mV per Div
μS per Div
400 μs
500 mV
10 ns
500 mV
图7-20. 100BASE-FX Waveform
图7-21. Auto-Negotiation Fast Link Pulses
Waveform
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8 Detailed Description
8.1 Overview
The DP83822 is a fully-featured, single-port Physical Layer transceiver for 10BASE-Te, 100BASE-TX and
100BASE-FX signaling. The device supports the standard Media Independent Interface (MII), Reduced Media
Independent Interface (RMII), and Reduced Gigabit Media Independent Interface (RGMII) for direct connection
to a Media Access Controller (MAC).
The device is designed for power supply flexibility by allowing for a range of I/O voltage interfaces (3.3 V, 2.5 V,
or 1.8 V) and options for analog voltage (1.8 V or 3.3 V) to reduce power consumption. Automatic supply
configuration within the DP83822 allows for any combination of VDDIO supply and AVD supply without the need
for additional configuration settings. The DP83822 uses mixed-signal processing to perform equalization, data
recovery, and error correction to achieve robust operation over CAT5 twisted-pair cable. The DP83822 not only
meets the requirements of IEEE 802.3u, but maintains high margins in terms of crosstalk and alien noise.
The DP83822 is also a pin-to-pin upgradeable option for the TLK105, TLK106, TLK105L, and TLK106L 10/100
Mbps Ethernet PHYs.
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8.2 Functional Block Diagram
MII / RGMII Option
RMII Option
Serial
Management
Serial
Management
MII / RGMII / RMII Interface
TX
RX
Data
TX_CLK
Data
RX_CLK
MII
Registers
10BASE-Te
and
10BASE-Te
and
100BASE-TX/FX
100BASE-TX/FX
Auto-Negotiation
Wake-on-LAN
Energy Efficient Ethernet
Clock
Generation
Transmit Block
Receive Block
DAC
ADC
BIST
LED
Driver
Cable Diagnostics
Auto-MDIX
Reference
Clock
TD
RD
LEDs
图8-1. DP83822 Functional Block Diagram
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8.3 Feature Description
8.3.1 Energy Efficient Ethernet
8.3.1.1 EEE Overview
Energy Efficient Ethernet (EEE), defined by IEEE 802.3az, is a capability integrated into Layer 1 (Physical Layer)
and Layer 2 (Data Link Layer) to operate in Low Power Idle (LPI) mode. In LPI mode, power is saved during
periods of low packet utilization. EEE defines the protocol to enter and exit LPI mode without dropping the link or
corrupting packets. The transition time into and out of LPI mode is short enough to be transparent to the upper
layers within the OSI model.
The DP83822 EEE supports 100 Mbps and 10 Mbps speeds. In 10BASE-Te operation, EEE operates with a
reduced transmit amplitude that is fully interoperable with a 10BASE-T PHY.
8.3.1.2 EEE Negotiation
EEE is advertised during Auto-Negotiation. Auto-Negotiation is performed at power up, on management
command, after link failure, or due to user intervention. EEE is supported if and only if both link partners
advertise EEE capabilities. If EEE is not supported, all EEE functions are disabled and the MAC should not
assert LPI. To advertise EEE capabilities, the PHY needs to exchange an additional formatted next page and
unformatted next page in sequence.
EEE Negotiation can be activated in two ways:
• Hardware Bootstrapping
• Register Access
EEE Negotiation Advertisements can be activated using RX_D1 pin bootstrap. When RX_D1 is set to strap
mode 2 or mode 3, EEE capabilities will be advertised during the Auto-Negotiation process. EEE Negotiation
Advertisements can also be activated using regsiter access through the SMI. The DP83822 offers two different
ways of accessing EEE control registers within the PHY register set. IEEE 802.3az defines MMD3 and MMD7 as
the locations for EEE control and status registers. The MMD3 and MMD7 registers 0x3000, 0x3001, 0x3016,
0x703C, and 0x703D contain all the required controls and status indications for operating EEE. Additionally, the
DP83822 supports an EEE configuration bypass option that enables EEE control registers within Texas
Instruments' Vendor Specific DEVAD. This helps simplify configuration by allowing for a single DEVAD to be
used. The Energy Efficient Ethernet Configuration Register #2 (EEECFG2, address 0x04D0) contains controls
for enabling and selecting the pin allocation for TX_ER, which is part of the MAC transmit LPI command. The
Energy Efficient Ethernet Configuration Register #3 (EEECFG3, address 0x04D1) contains controls for EEE
configuration bypass.
8.3.2 Wake-on-LAN Packet Detection
Wake-on-LAN provides a mechanism to detect specific frames and notify the connected controller through either
register status change, GPIO indication or an interrupt flag. The WoL feature within the DP83822 allows for
connected devices residing above the Physical Layer to remain in a low power state until frames with the
qualifying credentials are detected. Supported WoL frame types include: Magic Packet, Magic Packet with
Secure-ON and Custom Pattern Match. When a qualifying WoL frame is received, the DP83822 WoL logic circuit
is able to generate a user defined event (either pulses or level change) through any of the GPIO pins or a status
interrupt flag to inform a connected controller that a wake event has occurred. Additionally, the DP83822
includes a CRC Gate to prevent invalid packets from triggering a wake-up event.
The Wake-on-LAN feature set includes:
• Identification of WoL frames in all supported speeds (100BASE-FX, 100BASE-TX and 10BASE-Te).
• Wakeup interrupt generation upon reception of a WoL frame.
• CRC error checking of WoL frames to prevent interrupt generation from invalid frames.
• Magic Packets with Secure-ON password and 64-byte Custom Pattern Match for security.
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8.3.2.1 Magic Packet Structure
When configured for Magic Packet detection, the DP83822 scans all incoming frames addressed to the node for
a specific data sequence. This sequence identifies the frame as a Magic Packet frame.
A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as SOURCE
ADDRESS, DESTINATION ADDRESS (which may be the receiving station’s IEEE address or a BROADCAST
ADDRESS), and CRC.
The specific Magic Packet sequence consists of 16 duplications of the MAC address of this node, with no breaks
or interruptions, followed by Secure-ON password if security is enabled. This sequence can be located anywhere
within the packet, but must be preceded by a synchronization stream. The synchronization stream is defined as
6-bytes of 0xFF.
DEST (6 bytes)
SRC (6 bytes)
MISC (X bytes, X >= 0)
FF … FF (6 bytes)
MAGIC Pattern
DEST * 16
Secure-On Password (6 bytes)
MISC (Y bytes, Y >= 0)
CRC (4 bytes)
Only if Secure-On is Enabled
图8-2. Magic Packet Structure
8.3.2.2 Magic Packet Example
The following is an example Magic Packet for a Destination Address of 11h 22h 33h 44h 55h 66h and a secure-
on password 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh:
DESTINATION SOURCE MISC FF FF FF FF FF FF
11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 2A 2B 2C 2D 2E 2F MISC CRC
8.3.2.3 Wake-on-LAN Configuration and Status
Wake-on-LAN functionality is configured through the Receive Configuration Register (RXFCFG, address
0x04A0). Wake-on-LAN status is reported in the Recieve Status Register (RXFS, address 0x04A1). Wake-on-
LAN interrupt flag configuration and status is located in the MII Interrupt Status Register #2 (MISR2, address
0x0013).
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8.3.3 Start of Frame Detect for IEEE 1588 Time Stamp
The DP83822 supports an IEEE 1588 indication pulse at the SFD (start frame delimiter) for receive and transmit
paths. The pulse can be delivered to any of the following pins: LED_0, LED_1 (GPIO1), COL (GPIO2), RX_D3
(GPIO3), INT/PWDN_N and CRS. The 1588 Time Stamp pulse indicates the actual time the symbol is presented
on the lines (for transmit), or the first symbol received (for receive). The exact timing of the pulse can be adjusted
via the IEEE 1588 PTP Configuration Register (PTPCFG, address 0x003F). Each increment of phase value is an
8-ns step.
Message Timestamp Point
Ethernet
Start-of-Frame
Delimiter
First Octet following
Start-of-Frame
Preamble Octet
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
bit
time
图8-3. IEEE 1588 Message Timestamp Point
There are three registers that are able to control the routing of the IEEE 1588 transmit and receive indications.
The IEEE 1588 PTP Pin Select Register (PTPPSEL, address 0x003E) is able to route both transmit and receive
indications to LED_0 (GPIO1), COL (GPIO2), CRS and INT/PWDN_N, which is also found in the TLK105L and
TLK106L PHYs. Two additional registers in the DP83822 allow for additional pin selections and a centralized
location for GPIO controls through the use of the IO MUX GPIO Control Register #1 and #2 (IOCTRL1 and
IOCTRL2, address 0x0462 and address 0x0463).
8.3.4 Clock Output
The DP83822 has several clock configuration options. An external crystal or CMOS-level oscillator provides the
stimulus for the internal PHY reference clock. The local reference clock acts as the central source for all clocking
within the device, excluding the pass-through clock option.
All clock configuration options are enabled using the DP83822 IO MUX GPIO Control Register #1 and #2
(IOCTRL1 IOCTRL2, address 0x0462 bits[14:12] for RX_D3 (GPIO3), address 0x0462 bits[6:4] for LED_1
(GPIO1), address 0x0463 bits[6:4] for COL (GPIO2)).
Clock options supported by the DP83822 include:
• MAC IF Clock
• XI Clock
• Free-Running Clock
• Recovered Clock
MAC IF Clock will operate at the same rate as the MAC interface selected. For MII operation, MAC IF Clock
frequency is 25 MHz. For RMII operation, MAC IF Clock frequency is 50 MHz. For RGMII operation, MAC IF
Clock frequency is 25 MHz. XI Clock is a pass-through option, which allows for the XI pin clock to be passed to a
GPIO pin. Please note that the clock is buffered prior to transmission out of the GPIOs, and output clock
amplitude will be at the selected VDDIO level. Free-Running Clock is an internally generated 125-MHz free-
running clock. Recovered Clock is a 125-MHz recovered clock from a connected link partner.
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8.4 Device Functional Modes
8.4.1 MAC Interfaces
8.4.1.1 Media Independent Interface (MII)
The Media Independent Interface is a synchronous 4-bit wide nibble data interface that connects the PHY to the
MAC in 100BASE-FX, 100BASE-TX and 10BASE-Te modes. The MII is fully compliant with IEEE 802.3-2002
clause 22.
The MII signals are summarized below:
表8-1. MII Signals
FUNCTION
PINS
TX_D[3:0]
RX_D[3:0]
TX_EN
RX_DV
CRS
Data Signals
Transmit and Receive Signals
Line-Status Signals
COL
TX_CLK
TX_EN
TX_D[3:0]
RX_CLK
RX_DV
RX_ER
RX_D[3:0]
CRS
PHY
MAC
COL
图8-4. MII Signaling
Additionally, the MII interface includes the carrier sense signal (CRS), as well as a collision detect signal (COL).
The CRS signal asserts to indicate the reception or transmission of data. The COL signal asserts as an
indication of a collision which can occur during Half-Duplex mode when both transmit and receive operations
occur simultaneously.
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8.4.1.2 Reduced Media Independent Interface (RMII)
The DP83822 incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII
specification from the RMII consortium. The purpose of this interface is to provide a reduced pin count alternative
to the IEEE 802.3u MII as specified in Clause 22. Architecturally, the RMII specification provides an additional
reconciliation layer on either side of the MII, but can be implemented in the absence of an MII. The DP83822
offers two types of RMII operations: RMII Slave and RMII Master. In RMII Slave operation, the DP83822
operates off of a 50-MHz CMOS-level oscillator connected to the XI pin and shares the same clock as the MAC.
In RMII Master operation, the DP83822 operates off of either a 25-MHz CMOS-level oscillator connected to XI
pin or a 25-MHz crystal connected across XI and XO pins. A 50-MHz output clock referenced from any of the
three DP83822 GPIOs is connected to the MAC.
备注
If RMII Master mode is configured through bootstraps, a 50-MHz output clock will automatically be
enabled on RX_D3 (GPIO3).
The RMII specification has the following characteristics:
• Supports 100BASE-FX, 100BASE-TX and 10BASE-Te.
• Single clock reference sourced from the MAC to PHY (or from an external source)
• Provides independent 2-bit wide transmit and receive data paths
• Uses CMOS signal levels, the same levels as the MII interface
In this mode, data transfers are two bits for every clock cycle using the internal 50-MHz reference clock for both
transmit and receive paths.
The RMII signals are summarized below:
表8-2. RMII Signals
FUNCTION
PINS
TX_D[1:0]
RX_D[1:0]
TX_EN
Data Signals
Transmit and Receive Signals
CRS_DV
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TX_EN
TX_D[1:0]
RX_CLK (optional)
RX_DV (optional)
RX_ER (optional)
RX_D[1:0]
PHY
MAC
CRS_DV
XI
(pin 23)
50-MHz Reference
Clock
图8-5. RMII Slave Signaling
TX_EN
TX_D[1:0]
RX_CLK (optional)
RX_DV (optional)
RX_ER (optional)
RX_D[1:0]
PHY
MAC
CRS_DV
50-MHz Reference Clock
RX_D3
(pin 1)
25-MHz Reference
Clock
图8-6. RMII Master Signaling
Data on TX_D[1:0] are latched at the PHY with reference to the clock edges on the XI pin. Data on RX_D[1:0]
are latched at the MAC with reference to the same clock edges on the XI pin. RMII operates at the same speed
in 10BASE-Te, 100BASE-TX and 100BASE-FX. In 10BASE-Te the data is 10 times slower than the reference
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clock, so transmit data is sampled every 10 clock cycles. Likewise, receive data is generated on every 10th clock
so that an attached MAC device can sample the data every 10 clock cycles.
In addition, RMII mode supplies an RX_DV signal that allows a simpler method of recovering receive data
without the need to separate RX_DV from the CRS_DV indication. RX_ER is also supported even though it is
not required by the RMII specification.
RMII includes a programmable elastic buffer to adjust for the frequency differences between the reference clock
and the recovered receive clock. The programmable elastic buffer minimizes internal propagation delay based
on expected maximum packet size and clock accuracy.
Table below indicates how to program the buffer FIFO based on the expected maximum packet size and clock
accuracy. It assumes that the RMII reference clock and the far-end transmitter clock have the same accuracy.
表8-3. Recommended RMII Packet Sizes
START THRESHOLD
RBR[1:0]
LATENCY
TOLERANCE
RECOMMENDED PACKET SIZE RECOMMENDED PACKET SIZE
AT ±50 ppm
2400 bytes
7200 bytes
12000 bytes
16800 bytes
AT ±100 ppm
1200 bytes
3600 bytes
6000 bytes
8400 bytes
1 (4-bits)
2 (8-bits)
3 (12-bits)
4 (16-bits)
2 bits
6 bits
10 bits
14 bits
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8.4.1.3 Reduced Gigabit Media Independent Interface (RGMII)
The DP83822 also supports Reduced Gigabit Media Independent Interface (RGMII) as specified by RGMII
version 2.0. RGMII is designed to reduce the number of pins required to connect the MAC and PHY. To
accomplish this goal, the control signals are multiplexed. Both rising and falling edges of the clock are used to
sample the control signal pin on the transmit and receive paths. For 10-Mbps operation, RX_CLK and TX_CLK
operate at 2.5 MHz. For 100-Mbps operation, RX_CLK and TX_CLK operate at 25 MHz.
The RGMII signals are summarized below:
表8-4. RGMII Signals
FUNCTION
PINS
TX_D[3:0]
RX_D[3:0]
TX_CTRL
RX_CTRL
Data Signals
Transmit and Receive Signals
TX_CLK
TX_CTRL
TX_D[3:0]
RX_CLK
PHY
MAC
RX_CTRL
RX_D[3:0]
25-MHz Crystal or
CMOS-level
Oscillator
图8-7. RGMII Signaling
During packet reception, RX_CLK may be stretched on either the positive or negative pulse to accommodate the
transition from the internal free running clock to a recovered clock (data synchronous). Additionally, when the
speed of the PHY changes, a similar clock stretching of the positive or negative pulses is allowed to prevent
clock glitches. Data may be duplicated on the falling edge of the clock because double data rate (DDR) is only
required for 1-Gbps operation, which is not supported by the DP83822.
The DP83822 supports in-band status indication. To help simplify detection of link status, speed and duplex, the
DP83822 provides inter-frame signals on RX_D[3:0] pins as specified in 表8-5 below.
表8-5. RGMII In-Band Status
RX_DV
RX_D3
RX_D[2:1]
RX_D0
0
Duplex Status:
1 = Full-Duplex
0 = Half-Duplex
RX_CLK Clock Speed:
00 = 2.5-MHz (10 Mbps)
01 = 25-MHz (100 Mbps)
10 = Reserved
Link Status:
1 = Valid link established
0 = Link not established
Note: In-band status only valid
when RX_DV is low
11 = Reserved
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8.4.2 Serial Management Interface
The Serial Management Interface provides access to the DP83822 internal register space for status information
and configuration. The SMI is compatible with IEEE 802.3 clause 22 and clause 45. The implemented register
set consists of the registers required by the IEEE 802.3 plus several others to provide additional visibility and
controllability of the DP83822.
The SMI includes the management clock (MDC) and the management input/output data pin (MDIO). MDC is
sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of
25 MHz. MDC is not expected to be continuous, and can be turned off by the external management entity when
the bus is idle.
MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched on the
rising edge of the MDC. MDIO pin requires a pullup resistor (2.2 KΩ), which pulls MDIO high during IDLE and
turnaround.
Up to 32 PHYs can share a common SMI bus. To distinguish between the PHYs, a 5-bit address is used. During
power up or hardware reset, the DP83822 latches the PHY_AD[4:0] configuration pins to determine its address.
The management entity must not start an SMI transaction in the first cycle after power up or hardware reset. To
maintain valid operation, the SMI bus must remain inactive at least one MDC cycle after reset is deaserted. In
normal MDIO transactions, the register address is taken directly from the management-frame reg_addr field,
thus allowing direct access to 32 16-bit registers (including those defined in IEEE 802.3 and vendor specific).
The data field is used for both reading and writing. The Start code is indicated by a <01> pattern. This pattern
makes sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit
time inserted between the Register Address field and the Data field. To avoid contention during a read
transaction, no device may actively drive the MDIO signal during the first bit of Turnaround. The addressed
DP83822 drives the MDIO with a zero for the second bit of turnaround and follows this with the required data.
For write transactions, the station-management entity writes data to the addressed DP83822, thus eliminating
the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity by inserting
<10>.
表8-6. SMI Protocol
SMI PROTOCOL
Read Operation
Write Operation
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
<idle><01><10><AAAAA><RRRRR><Z0><XXXX XXXX XXXX XXXX><idle>
<idle><01><01><AAAAA><RRRRR><10><XXXX XXXX XXXX XXXX><idle>
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8.4.2.1 Extended Register Space Access
The DP83822 SMI function supports read and write access to the extended register set using the Register
Control Register (REGCR, address 0x000D), the Data Register (ADDAR, address 0x000E), and the MDIO
Manageable Device (MMD) indirect method defined in IEEE 802.3ah Draft for Clause 22 for accessing the
Clause 45 extended register set.
The standard register set, MDIO registers 0 to 31, is accessed using the normal direct-MDIO access or the
indirect method, except for register REGCR and register ADDAR, which are accessed only using the normal
MDIO transaction. The SMI function will ignore indirect access to these registers.
REGCR is the MMD access control. In general, register REGCR[4:0] is the device address DEVAD that directs
any accesses of the ADDAR register to the appropriate MMD.
The DP83822 supports three MMD device addresses:
1. The Vendor-Specific device address DEVAD[4:0] = 11111 is used for general MMD register accesses.
2. DEVAD[4:0] = 00011 is used for Energy Efficient Ethernet MMD register accesses. Register names for
registers accessible at this device address are preceded by MMD3.
3. DEVAD[4:0] = 00111 is used for Energy Efficient Ethernet MMD registers accesses. Register names for
registers accessible at this device address are preceded by MMD7.
All accesses through register REGCR and ADDAR must use the correct DEVAD. Transactions with other
DEVAD are ignored. REGCR[15:14] holds the access function: address (00), data with no post increment (01),
data with post increment on writes only (11). Address (10) is not valid.
• ADDAR is the address/data MMD register. ADDAR is used in conjunction with REGCR to provide the access
to the extended register set. If register REGCR[15:14] is (00), then ADDAR holds the address of the
extended address space register. Otherwise, ADDAR holds the data as indicated by the contents of its
address register. When REGCR[15:14] is set to (00), accesses to register ADDAR modify the extended
register set address register. This address register must always be initialized in order to access any of the
registers within the extended register set.
• When REGCR[15:14] is set to (01), accesses to register ADDAR access the register within the extended
register set selected by the value in the address register.
• When REGCR[15:14] set to (10) is not a valid option.
• When REGCR[15:14] is set to (11), access to register ADDAR access the register within the extended
register set selected by the value in the address register. After that access is complete, for write access only,
the value in the address register is incremented. For read accesses, the value of the address register
remains unchanged.
The following sections describe how to perform operations on the extended register set using register REGCR
and ADDAR. The descriptions use the device address for general MMD register accesses (DEVAD[4:0] = 11111).
For register accesses to the MMD3 or MMD7 registers the corresponding device address would be used.
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8.4.2.2 Write Address Operation
To set the address register:
1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.
2. Write the register address to register ADDAR.
Subsequent writes to register ADDAR (step 2) continue to write the address register.
8.4.2.3 Read Address Operation
To read the address register:
1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.
2. Read the register address from register ADDAR.
Subsequent reads to register ADDAR (step 2) continue to read the address register.
8.4.2.4 Write (No Post Increment) Operation
To write a register in the extended register set:
1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.
2. Write the desired register address to register ADDAR.
3. Write the value 0x401F (data, no post increment function field = 01, DEVAD = 31) to register REGCR.
4. Write the content of the desired extended register set to register ADDAR.
Subsequent writes to register ADDAR (step 4) continue to rewrite the register selected by the value in the
address register.
备注
Steps (1) and (2) can be skipped if the address register was previously configured.
8.4.2.5 Read (No Post Increment) Operation
To read a register in the extended register set:
1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.
2. Write the desired register address to register ADDAR.
3. Write the value 0x401F (data, no post increment function field = 01, DEVAD = 31) to register REGCR.
4. Read the content of the desired extended register set in register ADDAR.
Subsequent reads to register ADDAR (step 4) continue to reading the register selected by the value in the
address register.
备注
Steps (1) and (2) can be skipped if the address register was previously configured.
8.4.2.6 Write (Post Increment) Operation
1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.
2. Write the desired register address to register ADDAR.
3. Write the value 0x801F (data, post increment function field = 10, DEVAD = 31) or the value 0xC01F (data,
post increment on writes function field = 11, DEVAD = 31) to register REGCR.
4. Write the content of the desired extended register set to register ADDAR.
Subsequent writes to register ADDAR (step 4) write the next higher addressed data register selected by the
value of the address register; the address register is incremented after each access.
8.4.2.7 Read (Post Increment) Operation
To read a register in the extended register set and automatically increment the address register to the next
higher value following the write operation:
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1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.
2. Write the desired register address to register ADDAR.
3. Write the value 0x801F (data, post increment function field = 10, DEVAD = 31) to register REGCR.
4. Read the content of the desired extended register set in register ADDAR.
Subsequent reads to register ADDAR (step 4) read the next higher addressed data register selected by the
value of the address register; the address register is incremented after each access.
8.4.2.8 Example Write Operation (No Post Increment)
The following example will demonstrate a write operation with no post increment. In this example, the MAC
impedance will be adjusted to 99.25 Ωusing the IO MUX GPIO Control Register (IOCTRL, address 0x0461).
1. Write the value 0x001F to register 0x000D.
2. Write the value 0x0461 to register 0x000E. (Sets desired register to the IOCTRL)
3. Write the value 0x401F to register 0x000D.
4. Write the value 0x0400 to register 0x000E. (Sets MAC impedance to 99.25 Ω)
8.4.2.9 Example Read Operation (No Post Increment)
The following example will demonstrate a read operation with no post increment. In this example, the MMD7
Energy Efficient Ethernet Link Partner Ability Register (MMD7_EEE_LP_ABILITY, address 0x703D) will be read.
1. Write the value 0x0007 to register 0x000D.
2. Write the value 0x003D to register 0x000E. (Sets desired register to the MMD7_EEE_LP_ABILITY)
3. Write the value 0x4007 to register 0x000D.
4. Read the value of register 0x000E. (Data read is the value contained within the MMD7_EEE_LP_ABILITY)
8.4.3 100BASE-TX
8.4.3.1 100BASE-TX Transmitter
The 100BASE-TX transmitter consists of several functional blocks which convert synchronous 4-bit nibble data,
as provided by the MII, to a scrambled MLT-3 125 Mbps serial data stream on the MDI. 4B5B encoding and
decoding is detailed in 表8-7 below.
The transmitter section consists of the following funcitonal blocks:
1. Code-Group Encoder and Injection Block
2. Scrambler Block with Bypass Option
3. NRZ to NRZI Encoder Block
4. Binary to MLT-3 Converter / Common Driver Block
The bypass option for the functional blocks within the 100BASE-TX transmitter provides flexibility for applications
where data conversion is not always required. The DP83822 implements the 100BASE-TX transmit state
machine diagram as specified in the IEEE 802.3u Standard, Clause 24.
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DATA CODES
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表8-7. 4B5B Code-Group Encoding / Decoding
NAME
PCS 5B CODE-GROUP
MII 4B NIBBLE CODE
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
IDLE AND CONTROL CODES(1)
H
00100
11111
11000
10001
01101
00111
00000
HALT code-group - Error code
Inter-Packet IDLE - 0000
First Start of Packet - 0101
Second Start of Packet - 0101
First End of Packet - 0000
Second End of Packet - 0000
EEE LPI - 0001(2)
I
J
K
T
R
P
INVALID CODES
V
V
V
V
V
V
V
V
V
00001
00010
00011
00101
00110
01000
01100
10000
11001
(1) Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted.
(2) Energy Efficient Ethernet LPI must also have TX_ER / RX_ER asserted and TX_EN / RX_DV deasserted.
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8.4.3.1.1 Code-Group Encoding and Injection
The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for
transmission. This conversion is required to allow control data to be combined with packet data code-groups.
Refer to 表8-7 for 4B to 5B code-group mapping details.
The code-group encoder substitutes the first 8-bits of the MAC preamble with a J/K code-group pair (11000
10001) upon transmission. The code-group encoder continues to replace subsequent 4B preamble and data
nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the deassertion of transmit
enable (TX_EN) signal from the MAC, the code-group encoder injects the T/R code-group pair (01101 00111)
indicating the end of the frame.
After the T/R code-group pair, the code-group encoder continuously injects IDLEs into the transmit data stream
until the next transmit packet is detected (reassertion of transmit enable).
8.4.3.1.2 Scrambler
The scrambler is required to control the radiated emissions at the media connector and on the twisted-pair cable.
By scrambling the data, the total energy launched onto the cable is randomly distributed over a wide frequency
range. Without the scrambler, energy levels at the MDI and on the cable could peak beyond FCC limitations at
frequencies related to repeating 5B sequences (that is, continuous transmission of IDLEs).
The scrambler is configured as a closed loop linear feedback shift register (LFSR) with an 11-bit polynomial. The
output of the closed loop LFSR is X-ORd with the serial NRZ data from the code-group encoder. The result is a
scrambled data stream with sufficient randomization to decrease radiated emissions at certain frequencies by as
much as 20 dB.
8.4.3.1.3 NRZ to NRZI Encoder
After the transmit data stream has been serialized and scrambled, the data must be NRZI encoded in order to
comply with the TP-PMD standard for 100BASE-TX transmission over Category-5 Unshielded twisted pair cable.
There is no ability to bypass this block within the DP83822. The NRZI data is sent to the 100 Mbps Driver.
8.4.3.1.4 Binary to MLT-3 Converter
The Binary to MLT-3 conversion is accomplished by converting the serial binary data stream output from the
NRZI encoder into two binary data streams with alternately phased logic one events. These two binary streams
are then fed to the twisted pair output driver which converts the voltage to current and alternately drives either
side of the transmit transformer primary winding, resulting in a minimal current MLT-3 signal.
The 100BASE-TX MLT-3 signal sourced by the PMD Output Pair common driver is slew rate controlled. This
should be considered when selecting AC coupling magnetics to ensure TP-PMD Standard compliant transition
times (3 ns < Trise/fall < 5 ns).
The 100BASE-TX transmit TP-PMD function within the DP83822 is capable of sourcing only MLT-3 encoded
data. Binary output from the PMD Output Pair is not possible in 100 Mbps mode. Fully encoded MLT-3 on both
Tx+ and Tx- and can be configured by configuring Register 0x0404h (for example, in transformer-less designs).
8.4.3.2 100BASE-TX Receiver
The 100BASE-TX receiver consists of several functional blocks which convert the scrambled MLT-3 125 Mbps
serial data stream to synchronous 4-bit nibble data that is provided to the MII.
The receive section consists of the following functional blocks:
1. Input and BLW Compensation
2. Signal Detect
3. Digital Adaptive Equalization
4. MLT-3 to Binary Decoder
5. Clock Recovery Module
6. NRZI to NRZ Decoder
7. Serial to Parallel
8. Descrambler
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9. Code-Group Alignment
10. 4B/5B Decoder
11. Link Integrity Monitor
12. Bad SSD Detection
8.4.4 100BASE-FX
The DP83822 provides IEEE 802.3 compliant 100BASE-FX operation. Hardware bootstrap or register
configuration can be used to enable 100BASE-FX operation.
8.4.4.1 100BASE-FX Transmit
In 100BASE-FX mode, the DP83822 transmit pins connect to an industry standard fiber transceiver through a
capacitively coupled circuit. During 100BASE-FX operation, the DP83822 transmit path will bypass the
scrambler and MLT-3 encoder so that only serialized 4B5B encoded NRZI data is transmitted at 125-MHz.
8.4.4.2 100BASE-FX Receive
In 100BASE-FX mode, the DP83822 receive pins connect to an industry standard fiber transceiver through a
capacitively coupled circuit. During 100BASE-FX operation, the DP83822 receive path will bypass the MLT-3
decoder and scrambler. This allows for reception of serialized 4B5B encoded NRZI data at 125 MHz.
The DP83822 also has the added feature of a signal detection pin for direct connection to an industry standard
fiber transceiver. When enabling 100BASE-FX operation using the FX_EN bootstrap, AMDIX_EN bootstrap turns
into SD_EN bootstrap. If 100BASE-FX operation is enabled by setting FX_EN to either bootstrap mode 2 or 3,
SD_EN will enable signal detection pin, LED_1, when SD_EN is set to either bootstrap mode 3 or 4. Please see
表8-10 for mode information regarding hardware bootstraps.
备注
100BASE-FX signal detect pin (LED_1) polarity is controlled by bit[0] in the Fiber General
Configuration Register (FIBER GENCFG, address 0x0465). By default, signal detect is an active
HIGH polarity.
备注
TI recommends connecting Signal Detect pin from the Optical Transceiver to the LED_1 pin and
enable it using SD_EN bootstrap pin in 100BASE-FX mode. The LED_1 pin is not used in design and
that, if the electrical link between the fiber module and the DP83822 is broken, disconnected or
otherwise disrupted, the link will recover only by initiating a soft reset through MDIO/MDC interface.
8.4.5 10BASE-Te
The 10BASE-Te transceiver module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision,
heartbeat, loopback, jabber, and link integrity functions, as defined in the standard.
8.4.5.1 Squelch
Squelch is responsible for determining when valid data is present on the differential receive inputs. The squelch
circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10BASE-
Te standard) to determine the validity of data on the twisted-pair inputs.
The signal at the start of a packet is checked by the squelch, and any pulses not exceeding the squelch level
(either positive or negative, depending upon polarity) are rejected. When this first squelch level is exceeded
correctly, the opposite squelch level must then be exceeded no earlier than 50ns. Finally, the signal must again
exceed the original squelch level no earlier than 50ns to qualify as a valid input waveform, and not be rejected.
This checking procedure results in the typical loss of three preamble bits at the beginning of each packet. When
the transmitter is operating, five consecutive transitions are checked before indicating that valid data is present.
At this time, the squelch circuitry is reset.
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8.4.5.2 Normal Link Pulse Detection and Generation
The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-Te standard. Each link pulse is
nominally 100 ns in duration and transmitted every 16 ms in the absence of transmit data. Link pulses are used
to check the integrity of the connection with the remote end.
8.4.5.3 Jabber
Jabber is a condition in which a station transmits for a period of time longer than the maximum permissible
packet length, usually due to a fault condition. The jabber function monitors the DP83822 output and disables
the transmitter if it attempts to transmit a packet of longer than legal size. A jabber timer monitors the transmitter
and disables the transmission if the transmitter is active for approximately 100ms. When disabled by the Jabber
function, the transmitter stays disabled for the entire time that the module's internal transmit enable is asserted.
This signal must be de-asserted for approximately 500ms (unjab time) before the Jabber function re-enables the
transmit outputs. The Jabber function is only available and active in 10BASE-Te mode.
8.4.5.4 Active Link Polarity Detection and Correction
Swapping the wires within the twisted-pair causes polarity errors. Wrong polarity affects 10BASE-Te
connections. 100BASE-TX is immune to polarity problems because it uses MLT-3 encoding. 10BASE-Te receive
block automatically detects reversed polarity.
8.4.6 Auto-Negotiation (Speed / Duplex Selection)
Auto-Negotiation provides a mechanism for exchanging configuration information between the two ends of a link
segment. This mechanism is implemented by exchanging Fast Link Pulses (FLP). FLPs are burst pulses that
provide the information used to communicate the abilities between two devices at each end of a link segment.
The DP83822 supports 100BASE-TX and 10BASE-Te modes of operation for Auto-Negotiation. 100BASE-FX is
not included in the Auto-Negotiation process. Auto-Negotiation ensures that the highest performance protocol is
selected based on the advertised abilities of the Link Partner and the local device. Auto-Negotiation can be
enabled or disabled in hardware, using the AN_EN bootstrap, or by regsiter configuration, using bit[12] in the
Basic Mode Control Register (BMCR, address 0x0000). For further details regarding Auto-Negotiation, refer to
Clause 28 of the IEEE 802.3 specification.
8.4.7 Auto-MDIX Resolution
The DP83822 can determine if a “straight” or “crossover” cable is used to connect to the Link Partner. It
can automatically re-assign channel A and B to establish link with the Link Partner. Auto-MDIX resolution
precedes the actual Auto-Negotiation process that involves exchange of FLPs to advertise capabilities.
Automatic MDI/MDIX is described in IEEE 802.3 Clause 40, section 40.8.2. It is not a required implementation
for 10BASE-Te and 100BASE-TX. Auto-MDIX can also be used when operating the PHY in Forced modes.
Auto-MDIX can be enabled or disabled in hardware, using the AMDIX bootstrap, or by register configuration,
using bit[15] of the PHY Control Register (PHYCR, address 0x0019). When Auto-MDIX is disabled, the PMA is
forced to either MDI (“straight”) or MDIX (“crossover”). Manual configuration of MDI or MDIX can also be
accomplished in hardware, using the AMDIX bootstrap, or by register configuration, using bit[14] of the PHYCR.
Additionally, the DP83822 supports Fast Auto-MDIX configuration via register configuration to enable faster
MDIX resolution for link establishment. Fast Auto-MDIX can be enabled using bit[6] in the Control Register #1
(CR1, address 0x0009).
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8.4.8 Loopback Modes
There are several loopback options within the DP83822 that test and verify various functional blocks within the
PHY. Enabling loopback modes allow for in-circuit testing of the digital and analog data paths. The DP83822
may be configured to any one of the Near-End Loopback modes or to the Far-End (reverse) Loopback mode. MII
Loopback is configured using the Basic Mode Control Register (BMCR, address 0x0000). All other loopback
modes are enabled using the BIST Control Register (BISCR, address 0x0016). Except where otherwise noted,
loopback modes are supported for all speeds (10/100 Mbps and all MAC interfaces).
Reverse
Loopback
PCS
Loopback
Analog
Loopback
MAC
MII
Loopback
Digital
Loopback
External
Loopback
图8-8. Loopback Test Modes
8.4.8.1 Near-End Loopback
Near-End Loopback provides the ability to loop the transmitted data back to the receiver via the digital or analog
circuitry. The point at which the signal is looped back is selected using loopback control bits[3:0] in the BISCR
register. Auto-Negotiation and Auto-MDIX should be disabled before selecting the Near-End Loopback modes.
This constraint does not apply for external-loopback mode.
8.4.8.2 MII Loopback
MII Loopback is the shallowest loop through the PHY. It is a useful test mode to validate communications
between the MAC and the PHY. When in MII Loopback, data transmitted from a connected MAC on the TX path
is internally looped back in the DP83822 to the RX pins where it can be checked by the MAC.
MII Loopback is enabled by setting bit[14] in the BMCR.
8.4.8.3 PCS Loopback
PCS Loopback occurs in the PCS layer of the PHY. No signal processing is performed when using PCS
Loopback.
PCS Input Loopback is enabled by setting bit[0] in the BISCR.
PCS Output Loopback is enabled by setting bit[1] in the BISCR.
8.4.8.4 Digital Loopback
Digital Loopback includes the entire digital transmit and receive paths. Data is looped back prior to the analog
circuity.
Digital Loopback is enabled by setting bit[2] in the BISCR.
8.4.8.5 Analog Loopback
When operating in 10BASE-Te or 100BASE-TX mode, signals can be looped back after the analog front-end.
Analog Loopback requires 100-Ω terminations accross pins #1 and #2 as well as 100-Ω terminations accross
pins #3 and #6 at the RJ45.
Analog Loopback is enabled by setting bit[3] in the BISCR.
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8.4.8.6 Far-End (Reverse) Loopback
Far-End (Reverse) loopback is a special test mode to allow PHY testing with a link partner. In this mode, data
that is received from the Link Partner passes through the PHY’s receiver, is looped back at the MAC interface
and then transmitted back to the Link Partner. While in Reverse Loopback mode, all data signals that come from
the MAC are ignored.
Reverse Loopback is enabled by setting bit[4] in the BISCR.
8.4.9 BIST Configurations
The DP83822 incorporates an internal PRBS Built-in Self-Test (BIST) circuit to accommodate in-circuit testing
and diagnostics. The BIST circuit can be used to test the integrity of transmit and receive data paths. The BIST
can be performed using both internal loopbacks (digital or analog) or external loopback using a cable fixture. The
BIST simulates pseudo-random data transfer scenarios in format of real packets and Inter-Packet Gap (IPG) on
the lines. The BIST allows full control of the packet lengths and the IPG.
The BIST Packet Length is controlled using bits[10:0] in the BIST Control and Status Register #2 (BICSR2,
address 0x001C). The BIST IPG Length is controlled using bits[7:0] in the BIST Control and Status Register #1
(BICSR1, address 0x001B).
The BIST is implemented with independent transmit and receive paths, with the transmit clock generating a
continuous stream of a pseudo-random sequence. The device generates a 15-bit pseudo-random sequence for
BIST. Received data is compared to the generated pseudo-random data to determine pass/fail status. The
number of error bytes that the PRBS checker received is stored in bits[15:8] of the BICSR1. PRBS lock status
and sync can be read from the BIST Control Register (BISCR, address 0x0016).
The PRBS test can be put in a continuous mode by using bit[14] in the BISCR. In continuous mode, when the
BIST error counter reaches the maximum value, the counter starts counting from zero again. To read the BIST
error count, bit[15] in the BICSR1 must be set to '1'. This will lock the current value of the BIST errors for
reading. Please note that setting bit[15] also clears the BIST Error Counter.
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8.4.10 Cable Diagnostics
With the vast deployment of Ethernet devices, the need for a reliable, comprehensive and user-friendly cable
diagnostic tool is more important than ever. The wide variety of cables, topologies and connectors deployed
results in the need to non-intrusively identify and report cable faults. The TI cable-diagnostic unit provides
extensive information about cable integrity. The DP83822 offers the following capabilities in its Cable Diagnostic
tool kit:
• Time Domain Reflectometry (TDR)
8.4.10.1 TDR
The DP83822 uses Time Domain Reflectometry (TDR) to determine the quality of the cables, connectors and
terminations in addition to estimating the cable length. Some of the possible problems that can be diagnosed
include opens, shorts, cable impedance mismatch, bad connectors, termination mismatches, cross faults, cross
shorts and any other discontinuities along the cable.
The DP83822 transmits a test pulse of known amplitude (1 V) down each of the two pairs of an attached cable.
The transmitted signal continues down the cable and reflects from each cable imperfection, fault, connector and
from the end of the cable itself. After the pulse transmission, the DP83822 measures the return time and
amplitude of all these reflected pulses. This technique enables measuring the distance and magnitude
(impedance) of non-terminated cables (open or short), discontinuities (bad connectors) and improperly
terminated cables with ±1m accuracy.
For all TDR measurements, the transformation between time of arrival and physical distance is done by the
external host using minor computations (such as multiplication, addition and lookup tables). The host must know
the expected propagation delay of the cable, which depends, among other things, on the cable category (for
example, CAT5, CAT5e, or CAT6).
TDR measurement is allowed in the following scenarios:
• While the Link Partner is disconnected –cable is unplugged at the other side
• Link Partner is connected but remains “quiet”(for example, in power down mode)
• TDR could be automatically activated when the link fails or is dropped
TDR Auto-Run can be enabled by using bit[8] in the Control Regsiter #1 (CR1, address 0x0009). When a link
drops, TDR will automatically execute and store the results in the respective TDR Cable Diagnostic Location
Result Registers #1 - #5 (CDLRR, addresses 0x0180 to 0x0184) and the Cable Diagnostic Amplitude Result
Registers #1 - #5 (CDLAR, addresses 0x0185 to 0x0189). TDR can also be run manually using bit[15] in the
Cable Diagnostic Control Register (CDCR, address 0x001E). Cable diagnostic status is obtained by reading
bits[1:0] in the CDCR. Additional TDR functions including cycle averaging, bypass channel and crossover
disable can be found in the Cable Diagnostic Specific Control Register (CDSCR, address 0x0170).
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8.4.11 Fast Link Down Functionality
The DP83822 includes advanced link-down capabilities that support various real-time applications. The link-
down mechanism is configurable and includes enhanced modes that allow extremely fast link-drop reaction
times.
The DP83822 supports an enhanced link drop mechanism, also called Fast Link Drop (FLD), which shortens the
observation window for determining link. There are multiple ways of determining link status, which can be
enabled or disabled based on user preference. Fast Link Drop can be enabled in hardware with bootstrapping or
in software using register configuration. RX_D2 when strapped to either mode 2 or mode 3 will enable FLD at
power up or hardware reset. Additionally, FLD can be configured using the Control Register #3 (CR3, address
0x000B). Bits[3:0] and bit[10] allow for various FLD conditions to be enabled. When link drop occurs, indication
of a particular fault condition can be read from the Fast Link Down Status Register (FLDS, address 0x000F).
First Link Failure
Occurrence
Valid Link
Low Quality Data / Link Loss
Link Drop
Link Loss
Indication
(Link LED)
图8-9. Fast Link Down
Fast Link Down criteria include:
• RX Error Count - when a predefined number of 32 RX_ERs occur in a 10μs window, the link will be dropped.
• MLT3 Error Count - when a predefined number of 20 MLT3 errors occur in a 10μs window, the link will be
dropped.
• Low SNR Threshold - when a predefined number of 20 threshold crossings occur in a 10μs window, the link
will be dropped.
• Signal/Energy Loss - when the energy detector indicates energy loss, the link will be dropped.
The Fast Link Down functionality allows the use of each of these options separately or in any combination.
备注
Because this mode enables extremely quick reaction time, it is more exposed to temporary bad link-
quality scenarios.
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8.5 Programming
8.5.1 Hardware Bootstrap Configurations
The DP83822 uses the receive path functional pins as bootstrap options to place the device into specific modes
of operation. The values of these pins are sampled at power up or hardware reset, through either the RESET pin
or bit[15] in the PHY Reset Control Register (PHYRCR, address 0x001F).
The DP83822 bootstrap pins are 4-level, which are described in greater detail below.
备注
Because bootstrap pins may have alternate functions after reset is de-asserted, they should not be
connected directly to VCC or GND. pullup and pulldown resistors are required for proper operation.
Pins: COL, LED_0, CRS and RX_ER have internal pullup resistors. All other pins with bootstraps have
internal pulldown resistors. To account for the difference between the internal pullup and pulldown,
please reference 表8-8 and 表8-9 below for proper implementation.
LED_0 and LED_1 require parallel pullup or pulldown resistors when using the pin in conjunction with
an LED and current limiting resistor.
Configuration of the device may be done via 4-level strapping or via serial management interface. A pullup
resistor and a pulldown resistor of suggested values should be used to set the voltage ratio of the bootstrap pin
input and the supply to select one of the possible modes.
VDDIO
VDDIO
VDDIO
RH
RH
50 kΩ
25%
9 kΩ
25%
RL
RL
图8-10. Bootstrap Circuits
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表8-8. Recommended 4-Level Strap Resistor Ratios(1)
MODE
IDEAL RH (kΩ)
IDEAL RL (kΩ)
PULLDOWN PINS (9 kΩ)
1 (Default)
OPEN
10
OPEN
2.49
2
3
5.76
2.49
2.49
4
OPEN
PULLUP PINS (50 kΩ)
1
OPEN
13
1.96
1.96
2
3
6.2
1.96
4 (Default)
OPEN
OPEN
(1) Strap resistors with 1% tolerance are recommended.
表8-9. 4-Level Strap Voltage Ratios(1)
TARGET VOLTAGE
Vmax (V)
MODE 1
MODE 2
MODE 3
MODE 4
0.098 x VDDIO
0.181 x VDDIO
0.165 x VDDIO
0.148 x VDDIO
0.277 x VDDIO
0.252 x VDDIO
0.227 x VDDIO
VDDIO
VDDIO
Vtyp (V)
0
0
Vmin (V)
0.694 x VDDIO
(1) Ensured by production test, characterization or design.
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表8-10 describes the DP83822 configuration bootstraps:
表8-10. 4-Level Strap Pins
PIN NAME
PIN #
DEFAULT
STRAP FUNCTION
DESCRIPTION
COL
29
[01]
MODE
FX_EN
PHY_AD0 FX_EN:
Enables 100BASE-FX when set to ‘1’
PHY_AD0:
PHY Address bit[0]
1
0
0
0
1
1
2
1
3
1
4 (Default)
0
RX_D0
RX_D1
RX_D2
RX_D3
LED_0
CRS
30
31
32
1
[10]
[00]
[00]
[10]
[X1]
[01]
[01]
MODE
AN_1
PHY_AD1 AN_1:
See 表8-11 below
PHY_AD1:
PHY Address bit[1]
1 (Default)
1
0
0
1
1
2
0
3
0
4
1
MODE
EEE_EN
PHY_AD2 EEE_EN:
Enables EEE operation when set to '1'
PHY_AD2:
PHY Address bit [2]
1 (Default)
0
0
0
1
1
2
1
3
1
4
0
MODE
FLD_EN
PHY_AD3 FLD_EN:
Enables Fast Link Drop when set to '1'.
1 (Default)
0
0
0
1
1
Energy Detection, Low SNR threshold and
RX_ER will be enabled.
PHY_AD3:
2
1
3
1
PHY Address bit[3]
4
0
MODE
AN_EN
PHY_AD4 AN_EN:
See 表8-11 below
PHY_AD4:
PHY Address bit[4]
1 (Default)
1
0
2
0
0
3
0
1
1
4
1
RESERVED
X
17
27
28
MODE
AN_0
0
AN_0:
See 表8-11 below
1
2
X
Do Not Use(1)
Do Not Use(1)
1
3
X
4 (Default)
X
MODE
LED_SPEED
LED_CFG LED_CFG:
See below
LED_SPEED:
1
0
0
2
3
1
0
1
1
See 表8-12 below
1
0
4 (Default)
MODE
RX_ER
RGMII_EN
AMDIX_EN AMDIX_EN:
(SD_EN)
Enables Auto-MDIX when set to '1'
RGMII_EN:
See 表8-13 below
SD_EN:
Enables 100BASE-FX Signal Detection on
LED_1 when set to '1'. FX_EN strap must be
enabled for SD_EN strap to be functional.
Signal Detection is Active HIGH, but polarity
can be changed using the Fiber General
Configuration Register (FIBER GENCFG,
address 0x0465).
1
0
1
1
0
0
0
1
1
2
3
4 (Default)
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表8-10. 4-Level Strap Pins (continued)
PIN NAME
PIN #
DEFAULT
STRAP FUNCTION
DESCRIPTION
RX_DV
26
[00]
MODE
XI_50
RMII_EN
XI_50:
See 表8-13 below
RMII_EN:
See 表8-13 below
1 (Default)
0
1
0
1
0
0
1
1
2
3
4
(1) Makes the phy go into test mode. Should not be used in funtional mode.
表8-11. Modes of Operation
FX_EN
AN_EN
AN_1
AN_0
Description
Force Modes
0
0
0
0
0
0
0
0
0
0
1
1
0
10BASE-Te, Half-Duplex
1
10BASE-Te, Full-Duplex
100BASE-TX, Half-Duplex
100BASE-TX, Full-Duplex
0
1
Advertised Modes
0
0
0
1
1
1
0
0
1
0
1
0
10BASE-Te, Half-Duplex
10BASE-Te, Half/Full-Duplex
10BASE-Te, Half-Duplex
100BASE-TX, Half-Duplex
0
1
1
1
10BASE-Te, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
Fiber Modes
1
1
X
X
X
X
0
1
100BASE-FX, Half Duplex
100BASE-FX, Full Duplex
表8-12. LED Configuration
CRS Strap
Mode
LED_SPEED LED_CFG[0]
LED_0
LED_1
ON for Good Link
BLINK for TX/RX Activity
LED_1 in Tri-State
1
2
3
4
0
1
1
0
0
0
1
1
ON for Good Link
BLINK for TX/RX Activity
ON for 100 Mbps SPEED
OFF for 10 Mbps SPEED
ON for Good Link
OFF for No Link
ON for 100 Mbps SPEED
OFF for 10 Mbps SPEED
ON for Good Link
OFF for No Link
LED_1 in Tri-State
表8-13. MAC Interface Configuration
RGMII_EN
RMII_EN
XI_50
Description
0
0
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
MII, 25-MHz Reference Clock
Reserved
RMII, 25-MHz Reference Clock
RMII, 50-MHz Reference Clock
RGMII, 25-MHz Reference Clock
Reserved
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8.5.2 LED Configuration
The DP83822 supports up to three configurable Light Emitting Diode (LED) pins: LED_0, LED_1 (GPIO1), COL
(GPIO2) and RX_D3 (GPIO3). Several functions can be multiplexed onto the LEDs for different modes of
operation. The LED configuration modes are selected using the LEDs Configuration Register (LEDCFG1,
register 0x0460) and the Multi-LED Control Register (MLEDCR, register 0x0025). LED_0 and COL (GPIO2) use
the MLED function found in register 0x0025. MLED can be routed to only one of these two pins at a time. MLED
routing is determined by bits[1:0] in register 0x0025.
Because LED pins are also used as bootstrap pins, external components must be considered in order to avoid
contention. LED pins are automatically configured for the proper polarity based on the bootstrap configuration at
power up or hardware reset. If an LED pin is resistively pulled low, the corresponding output will be configured as
an active high driver. Conversely, if a given bootstrap input is resistively pulled high, the corresponding output
will be configured as an active low driver.
An example below shows proper bootstrap connections for LED pins using either pullup or pulldown
configurations.
Note: LED_0 and LED_1 require parallel pullup or pulldown resistors when using the pin in conjunction with an
LED and current limiting resistor. A 1.96kΩ to 2.49kΩ resistor should be used as the parallel pull resistor. When
LED pins are not used, they can be left floating.
Pull-Down
VDDIO
Strap Pin
RCL
D1
RP
RP
D1
RCL
Pull-Up
Strap Pin
图8-11. Example Strap Connections
8.5.3 PHY Address Configuration
The DP83822 can be configured for any of the 32 possible PHY addresses available through bootstrap
configuration. The PHY address is latched into the device upon power up or hardware reset. Each DP83822 or
port sharing PHY on the serial management bus in the system must have a unique PHY address. The DP83822
supports PHY address strapping values 0x0000 (0b00000) through 0x001F (0b11111).
By default, the DP83822 will latch-in PHY address 0x0001 (0b00001). This address can be changed by adding
the required pullup or pulldown resistors defined in the bootstrap section above.
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8.6 Register Maps
In the register definitions under the “TYPE”heading, the following definitions apply:
COR
Strap
LH
Clear on Read
Default value loads from bootstrap pin after reset
Latched high and held until read
Latched low and held until read
Read Only Access
LL
RO
RO/COR
RO/P
RW
Read Only, Clear on Read
Read Only, Permanently set to a default value
Read Write access
RW/SC
SC
Read Write access, Self Clearing bit
Register sets on event occurrence and Self-Clears when event ends
表8-14. 0x0000 Basic Mode Control Register (BMCR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
PHY Software Reset:
1 = Initiate software Reset / Reset in Progress
0 = Normal Operation
Writing a 1 to this bit resets the PHY PCS registers. When the reset
operation is done, this bit is cleared to 0 automatically. PHY Vendor
Specific registers (with MMD = 1F) will not be cleared.
Straps are not re-latched with this reset. Straps are re-latched only
during power up and pin reset.
15
Reset
RW, SC
0
MII Loopback:
1 = MII Loopback enabled
14
13
12
MII Loopback
Speed Selection
RW
0
1
1
0 = Normal Operation
When MII loopback mode is activated, the transmitted data presented
on MII TXD is looped back to MII RXD internally.
Speed Select:
1 = 100 Mbps
RW, Strap
RW, Strap
0 = 10 Mbps
When Auto-Negotiation is disabled (bit[12] = 0 in Register 0x0000),
writing to this bit allows the port speed to be selected.
Auto-Negotiation Enable:
1 = Enable Auto-Negotiation
Auto-Negotiation Enable
0 = Disable Auto-Negotiation
If Auto-Negotiation is disabled, bit[8] and bit[13] of this register
determine the port speed and duplex mode.
Power Down:
1 = IEEE Power Down
0 = Normal Operation
The PHY is powered down after this bit is set. Only register access is
enabled during this power down condition. To control the power down
mechanism, this bit is OR'ed with the input from the INT/PWDN_N
pin. When the active low INT/PWDN_N is asserted, this bit is set.
Programmed register are not reset to default in power down. Since all
state machines undergo reset so status bits (RO) may show a change
in value.
11
IEEE Power Down
RW
0
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表8-14. 0x0000 Basic Mode Control Register (BMCR) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Isolate:
10
Isolate
RW
0
1 = Isolates the port from the MII with the exception of the SMI
0 = Normal Operation
Restart Auto-Negotiation:
1 = Restarts Auto-Negotiation
0 = Normal Operation
If Auto-Negotiation is disabled (bit[12] = 0), bit[9] is ignored. This bit is
self-clearing and will return a value of 1 until Auto-Negotiation is
initiated, whereupon it will self-clear. Operation of the Auto-
Negotiation process is not affected by the management entity clearing
this bit.
9
Restart Auto-Negotiation
RW, SC
0
Duplex Mode:
1 = Full-Duplex
8
Duplex Mode
RW, Strap
1
0 = Half-Duplex
When Auto-Negotiation is disabled, writing to this bit allows the port
Duplex capability to be selected.
Collision Test:
1 = Enable COL Signal Test
0 = Normal Operation
7
Collision Test
Reserved
RW
RO
0
0
When set, this bit causes the COL signal to be asserted in response
to the assertion of TX_EN within 512 bit times. The COL signal is de-
asserted within 4 bit times in response to the de-assertion to TX_EN.
6:0
Reserved
表8-15. 0x0001 Basic Mode Status Register (BMSR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
100Base-T4 Capable:
15
100Base-T4
RO
0
This protocol is not available. Always reads as 0.
100Base-TX Full-Duplex Capable:
14
13
12
100Base-TX Full-Duplex
100Base-TX Half-Duplex
10Base-Te Full-Duplex
RO
RO
RO
1
1
1
1 = Device able to perform Full-Duplex 100Base-TX
0 = Device not able to perform Full-Duplex 100Base-TX
100Base-TX Half-Duplex Capable:
1 = Device able to perform Half-Duplex 100Base-TX
0 = Device not able to perform Half-Duplex 100Base-TX
10Base-Te Full-Duplex Capable:
1 = Device able to perform Full-Duplex 10Base-Te
0 = Device not able to perform Full-Duplex 10Base-Te
10Base-Te Half-Duplex Capable:
11
10Base-Te Half-Duplex
Reserved
RO
RO
1
0
1 = Device able to perform Half-Duplex 10Base-Te
0 = Device not able to perform Half-Duplex 10Base-Te
10:7
Reserved
Preamble Suppression Capable:
1 = Device able to perform SMI transaction with preamble suppressed
0 = Device not able to perform SMI transaction with preamble
suppressed
6
SMI Preamble Suppression
RO
1
If this bit is set to 1, 32-bits of preamble needed only once after reset,
invalid opcode or invalid turnaround.
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表8-15. 0x0001 Basic Mode Status Register (BMSR) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Auto-Negotiation Complete:
1 = Auto-Negotiation process completed
5
Auto-Negotiation Complete
RO
0
0 = Auto Negotiation process not completed (either still in process,
disabled or reset)
Remote Fault:
1 = Remote fault condition detected
4
3
Remote Fault
RO, LH
0
1
0 = No remote fault condition detected
Far End Fault indication or notification from Link Partner of Remote
Fault. This bit is cleared on read or reset.
Auto-Negotiation Ability:
Auto-Negotiation Ability
RO
1 = Device is able to perform Auto-Negotiation
0 = Device is not able to perform Auto-Negotiation
Link Status:
1 = Valid link established (for either 10 Mbps or 100 Mbps operation)
0 = Link not established
2
Link Status
RO, LL
0
If link goes low anytime, this bit value will read 0 on first read after link
down event. Will get cleared to 1 only if status is read second time
after link-up.
Jabber Detect:
1 = Jabber condition detected
0 = No jabber condition detected
This bit only has meaning for 10Base-Te operation.
1
0
Jabber Detect
RO, LH
RO
0
1
Extended Capability:
Extended Capability
1 = Extended register capabilities
0 = Basic register set capabilities only
表8-16. 0x0002 PHY Identifier Register #1 (PHYIDR1)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Organizationally Unique
Identifier Bits 21:6
0010 0000
0000 0000
15:0
RO
表8-17. 0x0003 PHY Identifier Register #2 (PHYIDR2)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Organizationally Unique
Identifier Bits 5:0
15:10
RO
1010 00
Vendor Model Number:
9:4
3:0
Model Number
RO
RO
10 0100
0000
The six bits of vendor model number are mapped from bits [9] to [4]
Model Revision Number:
Revision Number
Four bits of the vendor model revision number are mapped from bits
[3:0]. This field is incremented for all major device changes.
表8-18. 0x0004 Auto-Negotiation Advertisement Register (ANAR)
BIT
15
NAME
TYPE
DEFAULT
FUNCTION
Next Page Indication:
Next Page
Reserved
RW
0
1 = Next Page Transfer desired
0 = Next Page Transfer not desired
14
RO
0
Reserved
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表8-18. 0x0004 Auto-Negotiation Advertisement Register (ANAR) (continued)
BIT
13
12
11
NAME
Remote Fault
Reserved
TYPE
DEFAULT
FUNCTION
Remote Fault:
RW
0
1 = Advertises that this device has detected a Remote Fault
0 = No Remote Fault detected
RO
0
0
Reserved
Asymmetric Pause Support For Full-Duplex Links:
1 = Advertise asymmetric pause ability
Asymmetric Pause
RW
0 = Do not advertise asymmetric pause ability
Pause Support for Full-Duplex Links:
1 = Advertise pause ability
10
9
Pause
RW
0
0
1
1
1
0 = Do not advertise pause ability
100Base-T4 Support:
100Base-T4
RO
1 = Advertise 100Base-T4 ability
0 = Do not advertise 100Base-T4 ability
100Base-TX Full-Duplex Support:
8
7
6
100Base-TX Full-Duplex
100Base-TX Half-Duplex
10Base-Te Full-Duplex
RW, Strap
RW, Strap
RW, Strap
1 = Advertise 100Base-TX Full-Duplex ability
0 = Do not advertise 100Base-TX Full-Duplex ability
100Base-TX Half-Duplex Support:
1 = Advertise 100Base-TX Half-Duplex ability
0 = Do not advertise 100Base-TX Half-Duplex ability
10Base-Te Full-Duplex Support:
1 = Advertise 10Base-Te Full-Duplex ability
0 = Do not advertise 10Base-Te Full-Duplex ability
10Base-Te Half-Duplex Support:
5
10Base-Te Half-Duplex
Selector Field
RW, Strap
RW
1
1 = Advertise 10Base-Te Half-Duplex ability
0 = Do not advertise 10Base-Te Half-Duplex ability
Protocol Selection Bits:
4:0
0 0001
Technology selector field (IEEE802.3u <00001>)
表8-19. 0x0005 Auto-Negotiation Link Partner Ability Register (ANLPAR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Next Page Indication:
15
Next Page
RO
0
1 = Link partner desires Next Page Transfer
0 = Link partner does not desire Next Page Transfer
Acknowledge:
14
Acknowledge
RO
0
1 = Link partner acknowledges reception of link code word
0 = Link partner does not acknowledge reception of link code word
Remote Fault:
13
12
11
Remote Fault
Reserved
RO
RO
RO
0
0
0
1 = Link partner advertises remote fault event detection
0 = Link partner does not advertise remote fault event detection
Reserved
Asymmetric Pause:
Asymmetric Pause
1 = Link partner advertises asymmetric pause ability
0 = Link partner does not advertise asymmetric pause ability
Pause:
10
Pause
RO
0
1 = Link partner advertises pause ability
0 = Link partner does not advertise pause ability
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表8-19. 0x0005 Auto-Negotiation Link Partner Ability Register (ANLPAR) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
100Base-T4 Support:
9
100Base-T4
RO
0
1 = Link partner advertises 100Base-T4 ability
0 = Link partner does not advertise 100Base-T4 ability
100Base-TX Full-Duplex Support:
8
7
6
100Base-TX Full-Duplex
100Base-TX Half-Duplex
10Base-Te Full-Duplex
RO
RO
RO
0
0
0
1 = Link partner advertises 100Base-TX Full-Duplex ability
0 = Link partner does not advertise 100Base-TX Full-Duplex ability
100Base-TX Half-Duplex Support:
1 = Link partner advertises 100Base-TX Half-Duplex ability
0 = Link partner does not advertise 100Base-TX Half-Duplex ability
10Base-Te Full-Duplex Support:
1 = Link partner advertises 10Base-Te Full-Duplex ability
0 = Link partner does not advertise 10Base-Te Full-Duplex ability
10Base-Te Half-Duplex Support:
5
10Base-Te Half-Duplex
Selector Field
RO
RO
0
1 = Link partner advertises 10Base-Te Half-Duplex ability
0 = Link partner does not advertise 10Base-Te Half-Duplex ability
Protocol Selection Bits:
4:0
0 0000
Technology selector field (IEEE802.3 <00001>)
表8-20. 0x0006 Auto-Negotiation Expansion Register (ANER)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:5
Reserved
RO
0
Reserved
Parallel Detection Fault:
4
3
2
1
0
Parallel Detection Fault
Link Partner Next Page Able
Local Device Next Page Able
Page Received
RO, LH
RO
0
0
1
0
0
1 = A fault has been detected during the parallel detection process
0 = No fault detected
Link Partner Next Page Ability:
1 = Link partner is able to exchange next pages
0 = Link partner is not able to exchange next pages
Next Page Ability:
RO
1 = Local device is able to exchange next pages
0 = Local device is not able to exchange next pages
Link Code Word Page Received:
1 = A new page has been received
0 = A new page has not been received
RO, LH
RO
Link Partner Auto-Negotiation Ability:
Link Partner Auto-Negotiation
Able
1 = Link partner supports Auto-Negotiation
0 = Link partner does not support Auto-Negotiation
表8-21. 0x0007 Auto-Negotiation Next Page Register (ANNPTR)
BIT
15
NAME
Next Page
Reserved
TYPE
DEFAULT
FUNCTION
Next Page Indication:
RW
0
1 = Advertise desire to send additional next pages
0 = Do not advertise desire to send additional next pages
14
RO
0
1
Reserved
Message Page:
13
Message Page
RW
1 = Current page is a message page
0 = Current page is an unformatted page
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表8-21. 0x0007 Auto-Negotiation Next Page Register (ANNPTR) (continued)
NAME
TYPE
DEFAULT
FUNCTION
Acknowledge2:
1 = Will comply with message
12
Acknowledge 2
RW
0
0 = Cannot comply with message
Acknowledge2 is used by the next page function to indicate that Local
Device has the ability to comply with the message received.
Toggle:
1 = Toggle bit in previously transmitted Link Code Word was 0
0 = Toggle bit in previously transmitted Link Code Word was 1
Toggle is used by the Arbiitration function within Auto-Negotiation to
synchronize with the Link Parnter during Next Page exchange. This
bit always takes the opposite value of the Toggle bit in the previously
exchanged Link Code Word.
11
Toggle
RO
0
This field represents the code field of the next page transmission. If
the Message Page bit is set (bit [13] of this register), then the code is
interpreted as a Message Page, as defined in annex 28C of IEEE
802.3u. Otherwise, the code is interperated as an Unformatted Page,
and the interpretation is application specific.
000 0000
0001
10:0
CODE
RW
The default value of the CODE represents a Null Page as defined in
Annex 28C of IEEE 802.3u.
表8-22. 0x0008 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Next Page Indication:
15
Next Page
RO
0
1 = Advertise desire to send additional next pages
0 = Do not advertise desire to send additional next pages
Acknowledge:
14
13
Acknowledge
RO
RO
0
0
1 = Link partner acknowledges reception of link code word
0 = Link partner does not acknowledge reception of link code work
Message Page:
Message Page
1 = Current page is a message page
0 = Current page is an unformatted page
Acknowledge2:
1 = Will comply with message
12
11
Acknowledge 2
RO
RO
0
0
0 = Cannot comply with message
Acknowledge2 is used by the next page function to indicate that Local
Device has the ability to comply with the message received.
Toggle:
1 = Toggle bit in previously transmitted Link Code Word was 0
0 = Toggle bit in previously transmitted Link Code Word was 1
Toggle is used by the Arbiitration function within Auto-Negotiation to
synchronize with the Link Parnter during Next Page exchange. This
bit always takes the opposite value of the Toggle bit in the previously
exchanged Link Code Word.
Toggle
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表8-22. 0x0008 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
This field represents the code field of the next page transmission. If
the Message Page bit is set (bit 13 of this register), then the code is
interpreted as a Message Page, as defined in annex 28C of IEEE
802.3u. Otherwise, the code is interperated as an Unformatted Page,
and the interpretation is application specific.
0 0000
0000
10:0
Message/ Unformatted Field
RO
The default value of the CODE represents a Null Page as defined in
Annex 28C of IEEE 802.3u.
表8-23. 0x0009 Control Register #1 (CR1)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:10
Reserved
RO
0
Reserved
RMII Enhanced Mode:
1 = Enable RMII Enhanced Mode
0 = RMII operated in normal mode
In normal RMII mode, if the line is not idle, CRS_DV goes high. As
soon as the False Carrier is detected, RX_ER is asserted and RXD is
set to "2" (0010). This situation remains for the duration of the receive
event. While in enhanced mode, CRS_DV is disqualified and de-
asserted when the False Carrier is detected. This status also remains
for the duration of the receive event. In addition, in normal mode, the
start of the packet is intact. Each symbol error is indicatied by setting
RX_ER high. The data on RXD is replaced with "1" starting with the
first symbol error. While in enhanced mode, the CRS_DV is de-
asserted with the first symbol error.
9
RMII Enhanced Mode
RW
0
TDR Auto-Run at Link Down:
8
7
TDR Auto-Run
RW
RW
0
0
1 = Enable execution of TDR procedure after link down event
0 = Disable automatic execution of TDR
Link Loss Recovery:
1 = Enable Link Loss Recovery mechanism
0 = Normal Link Loss operation
This mode allows recovery from short interference and continue to
hold the link up for a few additional mSec until the short interference is
gone and the signal is OK. Under Normal Link Loss operation, Link
status will go down approximately 250μs from signal loss.
Link Loss Recovery
Fast Auto-MDIX:
1 = Enable Fast Auto-MDIX
0 = Normal Auto-MDIX
6
Fast Auto MDIX
RW
0
If both link partners are configured to work in Force 100Base-TX
mode (Auto-Negotiation disabled), this mode enables Automatic MDI/
MDIX resolution in a shortened time.
Robust Auto-MDIX:
1 = Enable Robust Auto-MDIX
0 = Disable Auto-MDIX
If link partners are configured for operational modes that are not
supported by normal Auto-MDIX, Robust Auto-MDIX allows MDI/
MDIX resolution and prevents deadlock.
5
Robust Auto MDIX
RW
0
When the DP83822 is strapped for 100 Mbps operation with Auto-
MDIX capabilities, Robust Auto-MDIX will be automatically set to aid
in MDI/MDIX resolution and deadlock prevention.
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表8-23. 0x0009 Control Register #1 (CR1) (continued)
NAME
TYPE
DEFAULT
FUNCTION
Fast Auto-Negotiation Enable:
1 = Enable Fast Auto-Negotiation
4
Fast Auto-Negotiation Enable
RW
0
0 = Disable Fast Auto-Negotiation
The PHY Auto-Negotiaties using timer setting according to Fast Auto-
Negotiation Select bits (bits[3:2] in this register).
Fast Auto-Negotiation Select Bits:
Adjusting these bits reduces the time it takes to Auto-Negotiate
between two PHYs. In Fast Auto-Negotiation, both PHYs should be
set to the same configuration. These 2 bits define the duration for
each state of the Auto-Negotiation process according to the table
above. The new duration time must be enabled by setting "Fast Auto
Negotiation Enable" (bit [4] of this register). Note: Using this mode in
cases where both link partners are not configured to the same Fast-
Autonegotiation configuration might produce scenarios with
unexpected behavior.
3:2
Fast Auto-Negotiation Select
RW
0
Fast Auto-
Negotiation
Select
Auto-
Break Link
Timer
Link Fail Inhibit
Timer
Negotitation
Wait Timer
<00>
<01>
<10>
<11>
80
120
240
NA
50
75
35
50
150
NA
100
NA
Fast RX_DV Detection:
1 = Enable Fast RX_DV detection
0 = Diable Fast RX_DV detection
1
Fast RX_DV Detection
RW
RO
0
0
When Fast RX_DV is enabled, RX_DV will assert high on receive
packet due to detection of the /J/ symbol only. If a consecutive /K/
does not appear, RX_ER is generated. In normal mode, RX_DV will
only be asserted after detection of /JK/.
0
Reserved
Reserved
表8-24. 0x000A Control Register #2 (CR2)
BIT
NAME
TYPE
DEFAULT
FUNCTION
100Base-TX Force Far-End Link Drop:
Writing a 1 asserts the 100Base-TX Force Far-End link drop mode. In
this mode (only valid for 100 Mbps), the PHY disables the TX upon
link drop to allow the far-end peer to drop its link as well, thus allowing
both link partners to be aware of the system link failure. This mode
exceeds the standard definition of force 100 Mbps.
100Base-TX Force Far-End
Link drop
15
RW
0
100Base-FX Enable:
14
100Base-FX Enable
Reserved
RW, Strap
RW
0
1 = 100Base-FX mode enabled
0 = 100Base-FX mode disabled
13:7
00 0001 0 Reserved
Fast Link-Up in Parallel Detect Mode:
1 = Enable Fast Link-Up time during Paralled Detection
0 = Normal Parallel Detection Link establishment
6
Fast Link-Up in Parallel Detect
RW
0
In Fast Auto MDIX and in Robust Auto-MDIX modes (bit[6] and bit[5]
in register CR1), this bit is automatically set.
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表8-24. 0x000A Control Register #2 (CR2) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Extended Full-Duplex Ability:
1 = Enable Extended Full-Duplex Ability
0 = Diable Extended Full-Duplex Ability
In Extended Full-Duplex ability, when the PHY is set to Auto-
Negotiation or Force 100Base-TX and the link partner is operated in
Force 100Base-TX, the link is always Full-Duplex. When disabled, the
decision to work in Full-Duplex or Half-Duplex mode follows IEEE
specification.
5
Extended Full-Duplex Ability
RW
0
Enhanced LED Link:
1 = LED ON only when link is 100Base-TX Full-Duplex mode
0 = LED ON when link is established
4
Enhanced LED Link
RW
0
In Enhanced LED Link mode, TX/RX BLINK on activity is disabled for
this LED pin. LED will only indicate LINK for established 100Base-TX
Full-Duplex links.
Isolate MII:
1 = Isolate MII Enabled
Isolate MII in 100Base-TX Half-
Duplex or 10Base-Te
0 = Normal MII output operation
3
2
1
0
RW
RW
RW
RW
0
0
0
0
In Isolate MII, MII outputs are isolated when Half-Duplex link
established for 100Base-TX or when Half-Duplex or Full-Duplex link
established for 10Base-Te.
Detection of Receive Symbol Error During IDLE State:
1 = Enable detection of Receive symbol error during IDLE state
0 = Disable detection of Receive symbol error during IDLE state
RX_ER During IDLE
Odd-Nibble Detection Disable
RMII Receive Clock
Detection of Transmit Error:
1 = Disable detection of transmit error in odd-nibble boundary
0 = Enable detection of transmit error in odd-nibble boundary
Detection of odd-nibble will extend TX_EN by one additional TX_CLK
cycle and behaves as if TX_ER were asserted during that additional
cycle
RMII Receive Clock:
1 = RMII Data (RXD[1:0]) is sampled and referenced to RX_CLK
0 = RMII Data (RXD[1:0]) is sampled and referenced to XI
表8-25. 0x000B Control Register #3 (CR3)
BIT
15:13
12
NAME
Reserved
TYPE
DEFAULT
FUNCTION
RW
000
Reserved
Bypass Digital Equalizer Error
RW
1
0
1 = Ignores the intermittent error output of digital equalizer
Descrambler Fast Link Drop:
1 = Drop the link on descrambler link loss
0 = Do not drop the link on descrambler link loss
This option can be enabled in parallel to the other fast link down
modes in bits[3:0].
De-scrambler Fast Link Down
Mode
10
RW
Bypass Digital Equalizer
Coefficient
9
RW
RW
0
1 = Bypass 0th coefficient of digital equalizer
8:7
Reserved
00
Reserved
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表8-25. 0x000B Control Register #3 (CR3) (continued)
NAME
TYPE
DEFAULT
FUNCTION
Polarity Swap:
1 = Inverted polarity on both pairs: TD+ and TD-, RD+ and RD-
0 = Normal polarity
6
Polarity Swap
RW
0
Port Mirror Function:
To enable port mirroring, set this bit and bit [5] high.
MDI/MDIX Swap:
1 = Swap MDI pairs (Receive on TD pair, Transmit on RD pair)
0 = MDI pairs normal (Receive on RD pair, Transmit on TD pair)
Port Mirror Function:
5
4
MDI/MDIX Swap
Reserved
RW
RW
0
0
To enable port mirroring, set this bit and bit[6] high.
Reserved
Fast Link Down Modes:
Bit 3 Drop the link based on RX Error count of the MII interface.
When a predefined number of 32 RX Error occurences in a 10μs
interval is reached, the link will be dropped.
Bit 2 Drop the link based on MLT3 Error count (Violation of the MLT3
coding in the DSP output). When a predefined number of 20 MLT3
Error occurences in a 10μs interval is reached, the link will be
dropped.
3:0
Fast Link Down Mode
RW
0000
Bit 1 Drop the link based on Low SNR Threshold. When a
predefined number of 20 Threshold crossing occurences in a 10μs
interval is reached, the link will be dropped.
Bit 0 Drop the link based on Signal/Energy Loss indication. When
the Energy detector indicates Energy Loss, the link will be dropped.
Typical reaction time is 10μs.
The Fast Link Down function is an OR of all 5 options (bit[10] and
bits[3:0]), the designer can enable any combination of these
conditions.
表8-26. 0x000D Register Control Register (REGCR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Extended Register Command:
00 = Address
15:14
13:5
Extended Register Command
Reserved
RW
0
01 = Data, no post increment
10 = Data, post increment on read and write
11 = Data, post increment on write only
RO
0
0
Reserved
Device Address:
Bits[4:0] are the device address, DEVAD, that directs any accesses of
ADDAR register (0x000E) to the appropriate MMD. Specifically, the
DP83822 uses the vendor specific DEVAD [4:0] = "11111" for
accesses to registers 0x04D1 and lower. For MMD3 access, the
DEVAD[4:0] = '00011'. For MMD7 access, the DEVAD[4:0] = '00111'.
All accesses through registers REGCR and ADDAR should use the
DEVAD for either MMD, MMD3 or MMD7. Transactions with other
DEVAD are ignored.
4:0
DEVAD
RW
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表8-27. 0x000E Data Register (ADDAR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
If REGCR register bits[15:14] = '00', holds the MMD DEVAD's address
register, otherwise holds the MMD DEVAD's data.
15:0
Address/Data
RW
0
表8-28. 0x000F Fast Link Down Status Register (FLDS)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:9
Reserved
RO
0
Reserved
Fast Link Down Status:
1 0000 = Descrambler Loss Sync
0 1000 = RX Errors
0 0100 = MLT3 Errors
8:4
3:0
Fast Link Down Status
RO, LH
0
0
0 0010 = SNR Level
0 0001 = Signal/Energy Lost
Status Registers that latch high each time a given Fast Link Down
mode is activated and causes a link drop (assuming the modes were
enabled)
Reserved
RO
Reserved
表8-29. 0x0010 PHY Status Register (PHYSTS)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15
Reserved
RO
0
Reserved
MDI/MDIX Mode Status:
14
13
MDI/MDIX Mode
RO
0
0
1 = MDI Pairs swapped (Receive on TD pair, Transmit on RD pair)
0 = MDI Pairs normal (Receive on RD pair, Transmit on TD pair)
Receive Error Latch:
1 = Receive error event has occurred
0 = No receive error event has occurred
Receive error event has occured since last read of RECR register
(address 0x0015). This bit will be cleared upon a read of the RECR
register.
Receive Error Latch
RO, LH
Polarity Status:
1 = Inverted Polarity detected
0 = Correct Polarity detected
12
11
Polarity Status
RO, LH
0
0
This bit is a duplication of bit[4] in the 10BTSCR register (address
0x001A). This bit will be cleared upon a read of the 10BTSCR
register, but not upon a read of the PHYSTS register.
False Carrier Sense Latch:
1 = False Carrier event has occurred
0 = No False Carrier event has occurred
False Carrier event has occurred since last read of FCSCR register
(address 0x0014). This bit will be cleared upon a read of the FCSR
register.
False Carrier Sense Latch
RO, LH
Signal Detect:
Active high 100Base-TX unconditional Signal Detect indication from
PMD
10
9
Signal Detect
RO, LL
RO, LL
0
0
Note: During EEE_LPI the value of this register bit should be ignored
Descrambler Lock:
Descrambler Lock
Active high 100Base-TX Descrambler Lock indication from PMD
Note: During EEE_LPI the value of this register bit should be ignored
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表8-29. 0x0010 PHY Status Register (PHYSTS) (continued)
NAME
TYPE
DEFAULT
FUNCTION
Link Code Word Page Received:
1 = A new Link Code Word Page has been received
8
7
Page Received
RO
0
0 = Link Code Word Page has not been received
This bit is a duplicate of Page Received (bit[1]) in the ANER register
and it is cleared on read of the ANER register (address 0x0006).
MII Interrupt Pending:
1 = Indicates that an internal interrupt is pending
0 = No interrupt pending
MII Interrupt
RO, LH
0
0
Interrupt source can be determined by reading the MISR register
(0x0012). Reading the MISR will clear this interrupt bit indication.
Remote Fault:
1 = Remote Fault condition detected
0 = No Remote Fault condition detected
Fault criteria: notification from link partner of Remote Fault via Auto-
Negotiation. Cleared on read of BMSR register (address 0x0001) or
by reset.
6
5
Remote Fault
RO
Jabber Detection:
1 = Jabber condition detected
0 = No Jabber This bit is only for 10 Mbps operation.
This bit is a duplicate of the Jabber Detect bit in the BMSR register
(address 0x0001) and will not be cleared upon a read of the PHYSTS
register.
Jabber Detect
RO
0
Auto-Negotiation Status:
4
3
2
1
Auto-Negotiation Status
MII Loopback Status
Duplex Status
RO
RO
RO
RO
0
0
0
1
1 = Auto-Negotiation complete
0 = Auto-Negotiation not complete
MII Loopback Status:
1 = Loopback enabled
0 = Normal operation
Duplex Status:
1 = Full-Duplex mode
0 = Half-Duplex mode
Speed Status:
Speed Status
1 = 10 Mbps mode
0 = 100 Mbps mode
Link Status:
1 = Valid link established (for either 10 Mbps or 100 Mbps)
0 = No link established
0
Link Status
RO
0
This bit is duplicated from the Link Status bit in the BMSR register
(address 0x0001) and will not be cleared upon a read of the PHYSTS
register.
表8-30. 0x0011 PHY Specific Control Register (PHYSCR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Disable PLL:
1 = Disable internal clocks circuitry
15
Disable PLL
RW
0
0 = Normal operation
Note: clock circuitry can be disabled only in IEEE power down mode.
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表8-30. 0x0011 PHY Specific Control Register (PHYSCR) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Power Save Mode Enable:
14
Power Save Mode Enable
RW
0
1 = Enable power save modes
0 = Normal operation
Power Saving Modes Selection Field:
Power Save Mode Enable (bit[14]) must be set to '1' for power save
modes to be enabled.
Power Mode
<00>
Name
Normal
Description
Normal operation mode. PHY is
fully functional.
<01>
Reserved
Reserved
Low Power Active Energy Saving
mode that shuts down all internal
circuitry besides SMI and energy
detect functionalities. In this mode
the PHY sends NLP every 1.4
seconds to wake up link partner.
Automatic power-up is done when
link partner is detected.
13:12
Power Save Modes
RW
00
<10>
Active Sleep
Low Power Passive Energy
Saving mode that shuts down all
internal circuitry besides SMI and
energy detect functionalities.
Automatic power-up is done when
link partner is detected.
<11>
Passive Sleep
Scrambler Bypass:
11
10
Scrambler Bypass
Reserved
RW
RW
0
0
1 = Scrambler bypass enabled
0 = Scrambler bypass disabled
Reserved
Far-End Loopback FIFO Depth:
00 = 4 nibbles FIFO
01 = 5 nibbles FIFO
10 = 6 nibbles FIFO
9:8
Loopback FIFO Depth
RW
01
11 = 8 nibbles FIFO
This FIFO is used to adjust RX (receive) clock rate to TX clock rate.
FIFO depth needs to be set based on expected maximum packet size
and clock accuracy. Default value sets to 5 nibbles.
7:5
4
Reserved
RO
RW
0
0
Reserved
Collision in Full-Duplex Mode:
1 = Enable Collision generation signaling in Full-Duplex mode
0 = Disable Collision in Full-Duplex mode
COL Full-Duplex Enable
Note: When in Half-Duplex mode, Collision will always be active.
Interrupt Polarity:
3
Interrupt Polarity
RW
1
1 = Normal operation is 1 logic and during interrupt is 0 logic
0 = Normal operation is 0 logic and during interrupt is 1 logic
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表8-30. 0x0011 PHY Specific Control Register (PHYSCR) (continued)
NAME
TYPE
DEFAULT
FUNCTION
Test Interrupt:
1 = Generate an interrupt
0 = Do not generate interrupt
2
1
Test Interrupt
RW
0
Forces the PHY to generate an interrupt to facilitate interrupt testing.
Interrupts will continue to be generated as long as this bit remains set.
Interrupt Enable:
1 = Enable event based interrupts
0 = Disable event based interrupts
Enable interrupt dependent on the event enables in the MISR register
(address 0x0012).
Interrupt Enable
RW
RW
0
0
Interrupt Output Enable:
1 = INT/PWDN_N is an interrupt output
0 = INT/PWDN_N is a Power Down pin
Enable active low interrupt events via the INT/PWDN_N pin by
configuring the INT/PWDN_N pin as an output.
0
Interrupt Output Enable
表8-31. 0x0012 MII Interrupt Status Register #1 (MISR1)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Change of Link Quality Status Interrupt:
1 = Change of link quality when link is ON
0 = Link quality is Good
15
Link Quality Interrupt
RO, LH
0
Change of Energy Detection Status Interrupt:
1 = Change of energy detected
14
13
12
11
10
Energy Detect Interrupt
Link Status Changed Interrupt
Speed Changed Interrupt
RO, LH
RO, LH
RO, LH
RO, LH
RO, LH
0
0
0
0
0
0 = No change of energy detected
Change of Link Status Interrupt:
1 = Change of link status interrupt is pending
0 = No change of link status
Change of Speed Status Interrupt:
1 = Change of speed status interrupt is pending
0 = No change of speed status
Change of Duplex Status Interrupt:
1 = Change of duplex status interrupt is pending
0 = No change of duplex status
Duplex Mode Changed Interrupt
Auto-Negotiation Complete Interrupt:
Auto-Negotiation Completed
Interrupt
1 = Auto-Negotiation complete interrupt is pending
0 = No Auto-Negotiation complete event is pending
False Carrier Counter Half-Full Interrupt:
1 = False Carrier HF interrupt is pending
0 = False Carrier HF event is not pending
False Carrier counter (Register FCSCR, address 0x0014) exceeds
half-full interrupt is pending.
False Carrier Counter Half-Full
Interrupt
9
8
RO, LH
RO, LH
0
0
Receiver Error Counter Half-Full Interrupt:
1 = Receive Error HF interrupt is pending
0 = Receive Error HF event is not pending
Receiver Error counter (Register RECR, address 0x0015) exceeds
half-full interrupt is pending.
Receive Error Counter Half-Full
Interrupt
7
6
Link Quality Interrupt Enable
Energy Detect Interrupt Enable
RW
RW
0
0
Enable interrupt on change of link quality
Enable interrupt on change of energy detection
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表8-31. 0x0012 MII Interrupt Status Register #1 (MISR1) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
5
Link Status Changed Enable
RW
0
Enable interrupt on change of link status
Speed Changed Interrupt
Enable
4
3
2
RW
RW
RW
0
0
0
Enable Interrupt on change of speed status
Enable Interrupt on change of duplex status
Enable Interrupt on Auto-negotiation complete event
Duplex Mode Changed Interrupt
Enable
Auto-Negotiation Completed
Enable
1
0
False Carrier HF Enable
Receive Error HF Enable
RW
RW
0
0
Enable Interrupt on False Carrier Counter Register half-full event
Enable Interrupt on Receive Error Counter Register half-full event
表8-32. 0x0013 MII Interrupt Status Register #2 (MISR2)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Energy Efficient Ethernet Error Interrupt:
1 = EEE error has occurred
15
EEE Error Interrupt
RO, LH
0
0 = EEE error has not occurred
Auto-Negotiation Error Interrupt:
14
13
12
11
10
9
Auto-Negotiation Error Interrupt
Page Received Interrupt
RO, LH
RO, LH
RO, LH
RO, LH
RO, LH
RO, LH
RO, LH
0
0
0
0
0
0
0
1 = Auto-Negotiation error interrupt is pending
0 = No Auto-Negotiation error event pending
Page Receiver Interrupt:
1 = Page has been received
0 = Page has not been received
Loopback FIFO Overflow/Underflow Event Interrupt:
1 = FIFO Overflow/Underflow event interrupt pending
0 = No FIFO Overflow/Underflow event pending
Loopback FIFO OF/UF Event
Interrupt
MDI/MDIX Crossover Status Change Interrupt:
1 = MDI crossover status changed interrupt is pending
0 = MDI crossover status has not changed
MDI Crossover Change
Interrupt
Sleep Mode Event Interrupt:
Sleep Mode Interrupt
1 = Sleep mode event interrupt is pending
0 = No Sleep mode event pending
Polarity Change Interrupt / WoL Packet Received Interrupt:
1 = Data polarity interrupt pending / WoL packet was recieved
0 = No Data polarity pending / No WoL packet received
Polarity Changed Interrupt /
WoL Packet Received Interrupt
Jabber Detect Event Interrupt:
8
Jabber Detect Interrupt
1 = Jabber detect event interrupt pending
0 = No Jabber detect event pending
7
6
EEE Error Interrupt Enable
RW
RW
0
0
Enable interrupt on EEE Error
Auto-Negotiation Error Interrupt
Enable
Enable Interrupt on Auto-Negotiation error event
5
4
3
2
Page Received Interrupt Enable
Loopback FIFO OF/UF Enable
MDI Crossover Change Enable
Sleep Mode Event Enable
RW
RW
RW
RW
0
0
0
0
Enable Interrupt on page receive event
Enable Interrupt on loopback FIFO Overflow/Underflow event
Enable Interrupt on change of MDI/X status
Enable Interrupt on sleep mode event
Polarity Changed / WoL Packet
Enable
1
RW
0
Enable Interrupt on change of polarity status
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表8-32. 0x0013 MII Interrupt Status Register #2 (MISR2) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
0
Jabber Detect Enable
RW
0
Enable Interrupt on Jabber detection event
表8-33. 0x0014 False Carrier Sense Counter Register (FCSCR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:8
Reserved
RO
0
Reserved
False Carrier Event Counter:
This 8-bit counter increments on every false carrier event. This
counter stops when it reaches its maximum count (FFh). When the
counter exceeds half-full (7Fh), an interrupt event is generated. This
register is cleared on read.
7:0
BIT
15:0
False Carrier Event Counter
RO, COR
0
表8-34. 0x0015 Receive Error Count Register (RECR)
NAME
TYPE
DEFAULT
FUNCTION
RX_ER Counter:
When a valid carrier is presented (only while RXDV is set), and there
is at least one occurrence of an invalid data symbol, this 16-bit
counter increments for each receive error detected. The RX_ER
counter does not count in MII loopback mode. The counter stops
when it reaches its maximum count (FFFFh). When the counter
exceeds half-full (7Fh), an interrupt is generated. This register is
cleared on read.
Receive Error Counter
RO, COR
0
表8-35. 0x0016 BIST Control Register (BISCR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15
Reserved
RO
0
Reserved
BIST Error Counter Mode:
1 = Continuous mode
0 = Single mode
14
13
BIST Error Counter Mode
RW
RW
0
0
Continuous mode, when the BIST Error counter reaches its max
value, a pulse is generated and the counter starts counting from zero
again. When in Single mode, if the BIST Error Counter reaches its
max value, PRBS checker will stop counting.
PRBS Checker:
1 = PRBS Checker Enabled
PRBS Checker
0 = PRBS Checker Disabled
When PRBS checker is enabled, DP83822 will check PRBS data
received.
Packet Generation Enable:
12
11
10
9
Packet Generation Enable
PRBS Checker Lock/Sync
PRBS Checker Sync Loss
Packet Generator Status
RW
RO
0
0
0
0
1 = Enable packet generator with PRBS data
0 = Disable packet generator
PRBS Checker Lock/Sync Indication:
1 = PRBS checker is locked and synced on received bit stream
0 = PRBS checker is not locked
PRBS Checker Sync Loss Indication:
1 = PRBS checker has lost sync
RO, LH
RO
0 = PRBS checker has not lost sync
Packet Generation Status Indication:
1 = Packet Generator is active and generating packets
0 = Packet Generator is off
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表8-35. 0x0016 BIST Control Register (BISCR) (continued)
BIT
8
NAME
TYPE
DEFAULT
FUNCTION
Sleep Mode Indication:
Power Mode
Reserved
RO
1
1 = Indicates that the PHY is in normal power mode
0 = Indicates that the PHY is in one of the sleep modes
7
RO
0
0
0
Reserved
Transmit Data in MII Loopback Mode (valid only at 100 Mbps):
1 = Enable transmission
0 = Disable transmission
When enabled, data received from the MAC on the TX pins will be
routed to the MDI in parallel to the MII loopback (to RX pins). This bit
may be set only in MII Loopback mode - setting bit[14] in in BMCR
register (address 0x0000). When disabled, data from the MAC is not
transmitted to the MDI.
6
5
Transmit in MII Loopback
RW
RO
Reserved
Reserved
Loopback Mode Select:
The PHY provides several options for loopback that test and verify
various functional blocks within the PHY. Enabling loopback mode
allows in-circuit testing of the DP83822 digital and analog data paths
Near-end Loopback
00001 = PCS Input Loopback
4:0
Loopback Mode
RW
0
00010 = PCS Output Loopback
00100 = Digital Loopback
01000 = Analog Loopback (requires 100-Ωtermination) Far-end
Loopback
10000 = Reverse Loopback
表8-36. 0x0017 RMII and Status Register (RCSR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:13
Reserved
RO
0
Reserved
RGMII RX Clock Shift:
1 = Receive path internal clock shift is enabled
0 = Receive path internal clock shift is disabled
When enabled, receive path internal clock (RX_CLK) is delayed by
3.5ns relative to recieve data. When disabled, data and clock are in
align mode.
12
11
RGMII RX Clock Shift
RGMII TX Clock Shift
RW
RW
0
0
RGMII TX Clock Shift:
1 = Transmit path internal clock shift is disabled
0 = Transmit path internal clock shift is enabled
When enabled, transmit path internal clock (TX_CLK) is delayed by
3.5ns relative to transmit data.
RGMII TX Clock Sync:
1 = PHY and MAC share same clock reference
0 = PHY operates from same or independent clock source as MAC
This mode, when enabled, reduces latency since both MAC and PHY
are synchronized to the same clock source. This mode can also be
used when enabling the PHY Clock Output by connecting the MAC to
the PHY Output Clock.
10
RGMII TX Synced
RW
0
0
RGMII Mode Enable:
9
RGMII Mode
RW, Strap
1 = Enable RGMII mode of operation
0 = Mode determined by bit[5]
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表8-36. 0x0017 RMII and Status Register (RCSR) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
RMII TX Clock Shift:
8
RMII TX Clock Shift
RW
0
1 = Transmit path internal clock shift is enabled
0 = Transmit path internal clock shift is disabled
RMII Reference Clock Select:
Strap XI_50 determines the clock reference requirement.
1 = 50-MHz clock reference, CMOS-level oscillator
0 = 25-MHz clock reference, crystal or CMOS-level oscillator
7
RMII Clock Select
RW, Strap
0
RMII Recovered Clock Async FIFO Bypass:
0 = Bypass Asynchronous FIFO
RMII Recovered Clock Async
FIFO Bypass
1 = Normal operation
6
5
RW
RW
1
0
When in RMII Recovered Clock mode, the asynchronous FIFO can be
bypassed to reduce the receive path latency within the DP83822.
50-MHz clock is outputted on RX_CLK when in Async fifo bypass
RMII Mode Enable:
RMII Mode
1 = Enable RMII mode of operation
0 = Enable MII mode of operation
RMII Revision Select:
1 = RMII revision 1.0
0 = RMII revision 1.2
4
RMII Revision Select
RW
0
RMII revision 1.0, CRS_DV will remain asserted until final data is
transferred. CRS_DV will not toggle at the end of a packet.
RMII revision 1.2, CRS_DV will toggle at the end of a packet to
indicate de-assertion of CRS.
RX FIFO Overflow Status:
1 = Overflow detected
0 = Normal
3
2
RMII Overflow Status
RMII Underflow Status
RO, COR
RO, COR
0
0
RX FIFO Underflow Status:
1 = Underflow detected
0 = Normal
Receive Elasticity Buffer Size:
This field controls the Receive Elasticity Buffer which allows for
frequency variation tolerance between the 50-MHz RMII clock and the
recovered data. The following values indicate the tolerance in bits for
a single packet. The minimum setting allows for standard Ethernet
frame sizes at ±50ppm accuracy. For greater frequency tolerance, the
packet lengths may be scaled (for ±100ppm), divide the packet
lengths by 2). 00 = 14 bit tolerance (up to 16800 byte packets)
01 = 2 bit tolerance (up to 2400 byte packets)
1:0
Receive Elasticity Buffer Size
RW
01
10 = 6 bit tolerance (up to 7200 byte packets)
11 = 10 bit tolerance (up to 12000 byte packets)
表8-37. 0x0018 LED Control Register (LEDCR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:11
Reserved
RO
0
Reserved
LED_0 Blinking Rate (ON/OFF duration):
00 = 20Hz (50 ms)
10:9
Blink Rate
RW
10
01 = 10Hz (100 ms)
10 = 5Hz (200 ms)
11 = 2Hz (500 ms)
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表8-37. 0x0018 LED Control Register (LEDCR) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
8
Reserved
RW
0
Reserved
LED_0 Link Polarity Setting:
1 = Active High polarity setting
0 = Active Low polarity setting
7
LED_0 Polarity
RW, Strap
0
LED_0 polarity defined by strapping value of this pin. This register
allows for override of this strap value.
6:5
4
Reserved
RW
RW
0
0
Reserved
Drive Link LED_0 Select:
Drive LED_0
1 = Drive value of ON/OFF bit[1] onto LED_0 output pin
0 = Normal operation
3:2
1
Reserved
LED_0 ON/OFF Setting
Reserved
RW
RW
RW
0
0
0
Reserved
Value to force LED_0 output
Reserved
0
表8-38. 0x0019 PHY Control Register (PHYCR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Auto-MDIX Enable:
15
Auto MDI/X Enable
RW, Strap
0
1 = Enable Auto-Negotiation Auto-MDIX capability
0 = Disable Auto-Negotiation Auto-MDIX capability
Force MDIX:
1 = Force MDI pairs to cross (MDIX)
0 = Normal operation (MDI)
14
13
12
Force MDI/X
Pause RX Status
Pause TX Status
RW
RO
RO
0
0
0
When Force MDI/X is enabled, receive data is on the TD pair and
transmit data is on the RD pair. When disabled, receive data is on the
RD pair and transmit data is on the TD pair.
Pause Receive Negotiation Status:
Indicates that pause receive should be enabled in the MAC. Based on
bits[11:10] in ANAR register and bits[11:10] in ANLPAR register
settings. The function shall be enabled according to IEEE 802.3
Annex 28B Table 28B-3, "Pause Resolution", only if the Auto-
Negotiation highest common denominator is a Full-Duplex technology.
Pause Transmit Negotiated Status:
Indicates that pause should be enabled in the MAC. Based on
bits[11:10] in ANAR register and bits[11:10] in ANLPAR register
settings. This function shall be enabled according to IEEE 802.3
Annex 28B Table 28B-3, "Pause Resolution", only if the Auto-
Negotiation highest common denominator is a Full-Duplex technology.
MII Link Status:
11
MII Link Status
Reserved
RO
RO
0
0
1 = 100Base-TX Full-Duplex link is active
0 = No active 100Base-TX Full-Duplex link
10:8
Reserved
Bypass LED Stretching:
1 = Bypass LED stretching
7
6
Bypass LED Stretching
Reserved
RW
RW
0
0
0 = Normal LED operation
Set this bit to '1' to bypass the LED stretching, the LED reflects the
internal value.
Reserved
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表8-38. 0x0019 PHY Control Register (PHYCR) (continued)
NAME
TYPE
DEFAULT
FUNCTION
Configuration
LED_CFG
LED_0
ON for LINK
1
1
0
5
LED Configuration
RW, Strap
1
OFF for no LINK
ON for LINK
2
BLINK for TX/RX Activity
PHY Address:
4:0
PHY Address
RO, Strap 0000 1
Strapping configuration for PHY Address
表8-39. 0x001A 10Base-Te Status/Control Register (10BTSCR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:14
Reserved
RO
0
Reserved
Lower Receiver Threshold Enable:
1 = Enable 10Base-Te lower receiver threshold
0 = Normal 10Base-Te operation
13
Receiver Threshold Enable
RW
0
When enabled, receiver threshold is lowered to allow for operation
with longer cables.
Squelch Configuration: Used to set the Peak Squelch 'ON' threshold
for the 10Base-Te receiver. Starting from 200mV to 600mV, step size
of 50mV with some overlapping as shown below: 0000 = 200mV
0001 = 250mV
0010 = 300mV
0011 = 350mV
0100 = 400mV
0101 = 450mV
0110 = 500mV
0111 = 550mV
1000 = 600mV
12:9
Squelch
RW
0000
8
7
Reserved
NLP Disable
Reserved
RW
RW
RO
0
0
0
Reserved
NLP Transmission Control:
1 = Disable transmission of NLPs
0 = Enable transmission of NLPs
6:5
Reserved
Polarity Status:
1 = Inverted Polarity detected
0 = Correct Polarity detected
4
Polarity Status
RO
0
This bit is a duplication of bit[12] in the PHYSTS register (0x0010).
Both bits will be cleared upon a read of 10BTSCR register, but not
upon a read of the PHYSTS register.
3:1
0
Reserved
RO
RW
0
0
Reserved
Jabber Disable:
1 = Jabber function disabled
Jabber Disable
0 = Jabber function enabled
Note: This function is only applicable in 10Base-Te operation.
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表8-40. 0x001B BIST Control and Status Register #1 (BICSR1)
BIT
NAME
TYPE
DEFAULT
FUNCTION
BIST Error Count:
Holds number of errored bytes received by the PRBS checker. Value
in this register is locked and cleared when write is done to bit[15].
When BIST Error Counter Mode is set to '0', count stops on 0xFF (see
register 0x0016)
15:8
BIST Error Count
RO
0x0
Note: Writing '1' to bit[15] will lock the counter's value for successive
read operation and clear the BIST Error Counter.
BIST IPG Length:
Inter Packet Gap (IPG) Length defines the size of the gap (in bytes)
between any 2 successive packets generated by the BIST. Default
value is 0x7D (equal to 500 bytes).
7:0
BIST IPG Length
RW
0111 1101
表8-41. 0x001C BIST Control and Status Register #2 (BICSR2)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:11
Reserved
RO
0
Reserved
BIST Packet Length:
101 1110
1110
Length of the generated BIST packets. The value of this register
defines the size (in bytes) of every packet that is generated by the
BIST. Default value is 0x5EE, which is equal to 1518 bytes.
10:0
BIST Packet Length
RW
表8-42. 0x001E Cable Diagnostic Control Register (CDCR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Cable Diagnostic Process Start:
1 = Start cable measurement
15
Cable Diagnostic Start
RW
0
0 = Cable Diagnostic is disabled
Diagnostic Start bit is cleared once Diagnostic Done indication bit is
triggered.
000 0001
0000 00
14:2
1
Reserved
RO
RO
Reserved
Cable Diagnostic Process Done:
Cable Diagnostic Status
1
0
1 = Indication that cable measurement process is complete
0 = Cable Diagnostic had not completed
Cable Diagnostic Process Fail:
0
Cable Diagnostic Test Fail
RO
1 = Indication that cable measurement process failed
0 = Cable Diagnostic has not failed
表8-43. 0x001F PHY Reset Control Register (PHYRCR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Software Reset:
1 = Reset PHY
15
Software Reset
RW, SC
0
0 = Normal Operation
This bit is self cleared and has the same effect as Hardware reset pin.
Digital Restart:
1 = Restart PHY
14
Digital Restart
Reserved
RW, SC
RW
0
0
0 = Normal Operation
This bit is self cleared and resets all PHY digital circuitry except the
registers.
13:0
Reserved
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表8-44. 0x0025 Multi-LED Control Register (MLEDCR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:10
Reserved
RW
0
Reserved
MLED Polarity Swap:
The polarity of MLED depends on the routing configuration. If the pin
strap is Pull-Up then polarity is active low. If the pin strap is Pull-Down
then polarity is active high.
9
MLED Polarity Swap
Reserved
RW
RW
Strap
0 = Active Low (default when pin strapped HIGH)
1 = Active High (default when pin strapped LOW)
8:7
0
Reserved
MLED Configurations:
000 0 = LINK OK
000 1 = RX/TX Activity
001 0 = TX Activity
001 1 = RX Activity
010 0 = Collision
010 1 = Speed, High for 100Base-TX
011 0 = Speed, High for 10Base-Te
011 1 = Full-Duplex
100 0 = LINK OK / BLINK on TX/RX Activity
100 1 = Active Stretch Signal
101 0 = MII LINK (100BT+FD)
101 1 = LPI Mode (EEE)
6:3
MLED Configuration
RW
000 0
110 0 = TX/RX MII Error
110 1 = Link Lost
111 0 = Blink for PRBS error
111 1 = Reserved
Link Lost, LED remains ON until BMCR register (address 0x0001) is
read.
Blink for PRBS Errors, LED remains ON for single error and remains
until BICSR1 register (address 0x001B) is cleared.
2
Reserved
RW
RW
0
Reserved
MLED Route to LED_0:
00 = MLED routed to COL
01 = Reserved
1:0
MLED Route to LED_0
00
10 = Reserved
11 = MLED routed to LED_0
表8-45. 0x0027 Compliance Test Register (COMPT)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:5
Reserved
RW
0
Reserved
10Base-Te Test Pattern Enable:
1 = Enable 10Base-Te Test Patterns
0 = Disable 10Base-Te Test Patterns
4
10Base-Te Test Patterns Enable
RW
0
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表8-45. 0x0027 Compliance Test Register (COMPT) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Compliance Test Configuration Select:
Bit[4] in Register 0x0027 = 1, Enables 10Base-Te Test Patterns.
Bit[4] in Register 0x0428 = 1, Enables 100Base-TX Test Modes
Bits[3:0] select the 10Base-Te test pattern, as follows:
0000 = Single NLP
0001 = Single Pulse 1
0010 = Single Pulse 0
0011 = Repetitive 1
0100 = Repetitive 0
0101 = Preamble (repetitive ‘10’)
0110 = Single 1 followed by TP_IDLE
0111 = Single 0 followed by TP_IDLE
1000 = Repetitive ‘1001’sequence
1001 = Random 10Base-Te data
1010 = TP_IDLE_00
1011 = TP_IDLE_01
1100 = TP_IDLE_10
1101 = TP_IDLE_11
3:0
Compliance Test Configuration
RW
0000
100Base-TX Test Mode is determined by bits {[5] in register 0x0428,
[3:0] in register 0x0027}. The bits determine the number of 0's to
follow a '1'.
0,0001 = Single '0' after a '1'
0,0010 = Two '0' after a '1'
0,0011 = Three '0' after a '1'
0,0100 = Four '0' after a '1'
0,0101 = Five '0' after a '1'
0,0110 = Six '0' after a '1'
0,0111 = Seven '0' after a '1'
...
1,1111 = Thirty one '0' after a '1'
0,0000 = Clears the shift register
Note 1: To reconfigure the 100Base-TX Test Mode, bit[4] must be
cleared in register 0x0428 and then reset to '1' to configure the new
pattern.
Note 2: When performing 100Base-TX or 10Base-Te tests modes, the
speed must be forced using the Basic Mode Control Register
(BMCR), address 0x0000.
表8-46. 0x003E IEEE 1588 PTP Pin Select Register (PTPPSEL)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:7
Reserved
RO
0
Reserved
IEEE 1588 TX Pin Select:
Assigns transmit SFD pulse indication to pin selected by value
001 = Reserved
010 = Reserved
6:4
IEEE 1588 TX Pin Select
RW
RO
000
011 = LED_0 Pin
100 = CRS Pin
101 = COL Pin
110 = INT/PWDN_N Pin
111 = No pulse output
3
Reserved
0
Reserved
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表8-46. 0x003E IEEE 1588 PTP Pin Select Register (PTPPSEL) (continued)
NAME
TYPE
DEFAULT
FUNCTION
IEEE 1588 RX Pin Select:
Assigns receive SFD pulse indication to pin selected by value
001 = Reserved
010 = Reserved
2:0
IEEE 1588 RX Pin Select
RW
000
011 = LED_0 Pin
100 = CRS Pin
101 = COL Pin
110 = INT/PWDN_N Pin
111 = No pulse output
表8-47. 0x003F IEEE 1588 PTP Configuration Register IEEE 1588 Precision Timing Configuration
Register (PTPCFG)
BIT
NAME
TYPE
DEFAULT
FUNCTION
PTP Transmit Timing:
15:13
PTP Transmit Timing
RW
101
Set IEEE 1588 indication for TX path (8ns step)
PTP Receive Timing:
12:10
9:8
PTP Receive Timing
TX Error Input Pin
RW
RW
101
00
Set IEEE 1588 indication for RX path (8ns step)
Configure TX Error Input Pin:
00 = No TX Error
01 = Reserved
10 = Use INT/PWDN_N pin as TX error
11 = Use COL pin as TX error
Timer For De-scrambler Unlock
Based Link-Down
7:4
3:0
RW
RW
1111
1111
Reserved
Reserved
表8-48. 0x0040 Fiber Far-End Fault Generation/Detection Force
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:7
6
Reserved
RW
1100 0001 0
Reserved
1=Far end fault generation is
disabled
FEF Gen Disable
RW
0
1=Disable detection of far end
fault
5
FEF Detect Disable
Reserved
RW
RW
0
4:0
1 1101
Reserved
表8-49. 0x0042 TX_CLK Phase Shift Register (TXCPSR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:5
Reserved
RO
0
Reserved
TX Clock Phase Shift Enable:
1 = Perform Phase Shift to TX_CLK
0 = No change in TX_CLK phase
4
Phase Shift Enable
RW, SC
0
When enabled, TX_CLK phase shift is according to the value written
to TX Clock Phase Shift Value (bits[4:0]).
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表8-49. 0x0042 TX_CLK Phase Shift Register (TXCPSR) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
TX Clock Phase Shift Value:
The value of this register represents the current phase shift between
Reference clock at XI and MII tramsmit clock at TX_CLK. Any different
value that will be written to these bits will shift TX_CLK by 4 times the
difference (in ns).
3:0
Phase Shift Value
RW
0000
Example: If the value of the register is 0x0002, writing 0x0009 to this
register will shift TX_CLK by 28ns. (4 times 7ns)
表8-50. 0x0101 DSP Configuration Register 1 (DSPCR1)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:8
Reserved
RW
0010 0000
Reserved
1 = Disable internal filter during a
phase of link-up training
7
Internal Filter Disable
RW
0
表8-51. 0x0106 Digital Filter Configuration Register 1 (DFCR1)
BIT
NAME
Internal Threshold For Filter
Reserved
TYPE
DEFAULT
FUNCTION
Internal threshold to activate filter coefficients set1 for short cables.
Reserved
15:12
11
RW
1011
0
10
Enable Filter Coefficient
Reserved
RW
RW
RW
RW
RW
0
1= Enable internal filter coefficient in steady state
Reserved
9:8
7:6
5:4
3:0
00
Filter Coefficients
Reserved
10
Filter coefficient values for long cables
Reserved
11
Internal Threshold For Filter
1011
Internal threshold to activate filter coefficients set0 for short cables.
表8-52. 0x0107 Digital Filter Configuration Register 2 (DFCR2)
BIT
NAME
TYPE
DEFAULT
FUNCTION
0000 0110
0000 0101
15:0
Reserved
RW
Reserved
表8-53. 0x010F DSP Configuration Register 2 (DSPCR2)
BIT
15:9
8
NAME
Reserved
TYPE
DEFAULT
0000 001
1
FUNCTION
RW
Reserved
Selects the type of input for the gain correction loop
DSP Loop Input
Reserved
RW
7:0
RW
0000 0000 Reserved
表8-54. 0x0111 DSP Configuration Register 3 (DSPCR3)
BIT
NAME
TYPE
DEFAULT
0110 0000 0000
011
FUNCTION
Reserved
15:4
3:0
Reserved
RW
Starting Gain Index
RW
Initial value of gain index
表8-55. 0x0114 Digital Feedback Equalizer Control Register (DFECR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
0100 0000
0000 1010
15:0
Reserved
RW
Reserved
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表8-56. 0x0116 AGC Bandwidth Control Register (AGCBCR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
0000 0001
0100 1010
15:0
Reserved
RW
Reserved
表8-57. 0x0121 MSE Threshold To Enter Recovery State From Steady State
BIT
15
NAME
TYPE
DEFAULT
FUNCTION
Reserved
RO
0
Ignore on read
14:0
Bad MSE Threshold
RW
001 1001 1001 1010
Bad MSE threshold for 100M
表8-58. 0x0122 MSE Threshold For Timing Loop
BIT
15
NAME
TYPE
DEFAULT
FUNCTION
Ignore on read
Reserved
RO
0
14:0
Good MSE1 Threshold
RW
001 0000 0010 0111
Good MSE1 threshold for 100M
表8-59. 0x0123 MSE Threshold For Link-up
BIT
15
NAME
Reserved
TYPE
DEFAULT
FUNCTION
Ignore on read
RO
0
14:0
Good MSE2 Threshold
RW
000 0101 0001 1100
Good MSE2 threshold for 100M
表8-60. 0x0126 Digital Equalizer Timer Register (DETR)
BIT
15
NAME
TYPE
RW
RW
RW
RW
RW
DEFAULT
FUNCTION
Reserved
0
Reserved
14:12
11:6
5:3
Training Timer 1
Training Timer 2
Training Timer 3
Training Timer 4
100
Timer value used for DSP state shift
Timer value used in timing loop
Timer value used in gain loop
Timer value used in gain loop
0110 00
011
2:0
011
表8-61. 0x0129 DSP Configuration Register 4 (DSPCR4)
BIT
15:8
7:4
NAME
TYPE
DEFAULT
0000 0000
0000
FUNCTION
Reserved
Reserved
RW
Max Gain Index
Min Gain Index
RW
Limit of max gain index
Limit of min gain index
3:0
RW
1111
表8-62. 0x0130 DSP Configuration Register 5 (DSPCR5)
BIT
15:12
11
NAME
TYPE
DEFAULT
FUNCTION
Reserved
Reserved
RW
0000
0
Disable Gain Retrain
Reserved
RW
1 = Disable Gain Retraining
Reserved
10:0
RW
000 0000 0001
表8-63. 0x0155 ALCD Control and Results 1 Register (ALCDRR1)
BIT
15
NAME
ALCD Start Test
Reserved
TYPE
DEFAULT
FUNCTION
Active Link Cable Diagnostic Start:
SC
0
1 = Start ALCD test
0 = Do not start ALCD test
14:13
RO
00
Reserved
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表8-63. 0x0155 ALCD Control and Results 1 Register (ALCDRR1) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Active Link Cable Diagnostic Status:
1 = ALCD is not complete
12
ALCD Test Status
RO
0
0 = ALCD is complete
11:4
3:0
ALCD Sum Out
Reserved
RO
RW
0000 0000
0001
Reserved
表8-64. 0x0170 Cable Diagnostic Specific Control Register (CDSCR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15
Reserved
RO
0
Reserved
Cross TDR Diagnostic Mode:
1 = Disable TDR Cross Mode
0 = Enable TDR Cross Mode
14
13
Cable Diagnostic Cross Disable
Cable Diagnostic TD Bypass
RW
RW
0
0
When enabled, the TDR mechanism is looking for reflection on the
other pair to check for shorts between pairs.
TD Diagnostic Bypass:
1 = Bypass TD pair diagnostic
0 = TDR is executed on TD pair
When enabled, TDR on TD pair will not be executed.
RD Diganostic Bypass:
1= Bypass RD pair diagnostic
12
11
Cable Diagnostic RD Bypass
Reserved
RW
RW
0
1
0 = TDR is executed on RD pair
When enabled, TDR on RD pair will not be executed.
Reserved
Number of TDR Cycles to Average:
000 = 1 TDR cycle
001 = 2 TDR cycles
010 = 4 TDR cycles
011 = 8 TDR cycles
100 = 16 TDR cycles
101 = 32 TDR cycles
110 = 64 TDR cycles
111 = Reserved
Cable Diagnostic Average
Cycles
10:8
7:0
RW
RW
110
Reserved
0101 0010 Reserved
表8-65. 0x0171 Cable Diagnostic Specific Control Register 2 (CDSCR2)
BIT
15:4
3:0
NAME
TYPE
DEFAULT
FUNCTION
1100 1000
0101
Reserved
RW
Reserved
Configure expected self reflection in TDR
TDR Pulse Control
RW
1100
表8-66. 0x0173 Cable Diagnostic Specific Control Register 3 (CDSCR3)
BIT
15:8
7:0
NAME
Cable Length Configuration
Reserved
TYPE
DEFAULT
FUNCTION
RW
1111 1111
Configure duration of listening to detect long cable reflections
RW
0001 1110 Reserved
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表8-67. 0x0177 Cable Diagnostic Specific Control Register 4 (CDSCR4)
BIT
NAME
TYPE
DEFAULT
000
1 1000
1001 1011 Reserved
FUNCTION
15:13
Reserved
RW
Reserved
Threshold to compensate for strong reflections in short cables
12:8
7:0
Short Cables Threshold
Reserved
RW
RW
表8-68. 0x0180 Cable Diagnostic Location Result Register #1 (CDLRR1)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Location of the Second peak discovered by the TDR mechanism on
15:8
TD Peak Location 2
RO
0000 0000 Transmit Channel (TD). The value of these bits need to be translated
into distance from the PHY.
Location of the First peak discovered by the TDR mechanism on
0000 0000 Transmit Channel (TD). The value of these bits need to be translated
into distance from the PHY.
7:0
TD Peak Location 1
RO
表8-69. 0x0181 Cable Diagnostic Location Result Register #2 (CDLRR2)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Location of the Fourth peak discovered by the TDR mechanism on
15:8
TD Peak Location 4
RO
0000 0000 Transmit Channel (TD). The value of these bits need to be translated
into distance from the PHY.
Location of the Third peak discovered by the TDR mechanism on
0000 0000 Transmit Channel (TD). The value of these bits need to be translated
into distance from the PHY.
7:0
TD Peak Location 3
RO
表8-70. 0x0182 Cable Diagnostic Location Result Register #3 (CDLRR3)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Location of the First peak discovered by the TDR mechanism on
15:8
RD Peak Location 1
RO
0000 0000 Receive Channel (RD). The value of these bits need to be translated
into distance from the PHY.
Location of the Fifth peak discovered by the TDR mechanism on
0000 0000 Transmit Channel (TD). The value of these bits need to be translated
into distance from the PHY.
7:0
TD Peak Location 5
RO
表8-71. 0x0183 Cable Diagnostic Location Result Register #4 (CDLRR4)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Location of the Third peak discovered by the TDR mechanism on
15:8
RD Peak Location 3
RO
0000 0000 Receive Channel (RD). The value of these bits need to be translated
into distance from the PHY.
Location of the Second peak discovered by the TDR mechanism on
0000 0000 Receive Channel (RD). The value of these bits need to be translated
into distance from the PHY.
7:0
RD Peak Location 2
RO
表8-72. 0x0184 Cable Diagnostic Location Result Register #5 (CDLRR5)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Location of the Fifth peak discovered by the TDR mechanism on
15:8
RD Peak Location 5
RO
0000 0000 Receive Channel (RD). The value of these bits need to be translated
into distance from the PHY.
Location of the Fourth peak discovered by the TDR mechanism on
0000 0000 Receive Channel (RD). The value of these bits need to be translated
into distance from the PHY.
7:0
RD Peak Location 4
RO
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表8-73. 0x0185 Cable Diagnostic Amplitude Result Register #1 (CDLAR1)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15
Reserved
RO
0
Reserved
Amplitude of the Second peak discovered by the TDR mechanism on
Transmit Channel (TD). The value of these bits is translated into type
of cable fault and/or interference.
14:8
7
TD Peak Amplitude 2
Reserved
RO
RO
RO
000 0000
0
Reserved
Amplitude of the First peak discovered by the TDR mechanism on
Transmit Channel (TD). The value of these bits is translated into type
of cable fault and/or interference.
6:0
TD Peak Amplitude 1
000 0000
表8-74. 0x0186 Cable Diagnostic Amplitude Result Register #2 (CDLAR2)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15
Reserved
RO
0
Reserved
Amplitude of the Fourth peak discovered by the TDR mechanism on
Transmit Channel (TD). The value of these bits is translated into type
of cable fault and/or interference.
14:8
7
TD Peak Amplitude 4
Reserved
RO
RO
RO
000 0000
0
Reserved
Amplitude of the Third peak discovered by the TDR mechanism on
Transmit Channel (TD). The value of these bits is translated into type
of cable fault and/or interference.
6:0
TD Peak Amplitude 3
000 0000
表8-75. 0x0187 Cable Diagnostic Amplitude Result Register #3 (CDLAR3)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15
Reserved
RO
0
Reserved
Amplitude of the First peak discovered by the TDR mechanism on
Receive Channel (RD). The value of these bits is translated into type
of cable fault and/or interference.
14:8
7
RD Peak Amplitude 1
Reserved
RO
RO
RO
000 0000
0
Reserved
Amplitude of the Fifth peak discovered by the TDR mechanism on
Transmit Channel (TD). The value of these bits is translated into type
of cable fault and/or interference.
6:0
TD Peak Amplitude 5
000 0000
表8-76. 0x0188 Cable Diagnostic Amplitude Result Register #4 (CDLAR4)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15
Reserved
RO
0
Reserved
Amplitude of the Third peak discovered by the TDR mechanism on
Receive Channel (RD). The value of these bits is translated into type
of cable fault and/or interference.
14:8
7
RD Peak Amplitude 3
Reserved
RO
RO
RO
000 0000
0
Reserved
Amplitude of the Second peak discovered by the TDR mechanism on
Receive Channel (RD). The value of these bits is translated into type
of cable fault and/or interference.
6:0
RD Peak Amplitude 2
000 0000
表8-77. 0x0189 Cable Diagnostic Amplitude Result Register #5 (CDLAR5)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15
Reserved
RO
0
Reserved
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表8-77. 0x0189 Cable Diagnostic Amplitude Result Register #5 (CDLAR5) (continued)
BIT
14:8
7
NAME
TYPE
DEFAULT
000 0000
0
FUNCTION
Amplitude of the Fifth peak discovered by the TDR mechanism on
Receive Channel (RD). The value of these bits is translated into type
of cable fault and/or interference.
RD Peak Amplitude 5
Reserved
RO
RO
Reserved
Amplitude of the Fourth peak discovered by the TDR mechanism on
Receive Channel (RD). The value of these bits is translated into type
of cable fault and/or interference.
6:0
RD Peak Amplitude 4
RO
000 0000
表8-78. 0x018A Cable Diagnostic General Result Register (CDLGR)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Polarity of the Fifth peak discovered by the TDR mechanism on
15
TD Peak Polarity 5
RO
0
Transmit Channel (TD).
Polarity of the Fourth peak discovered by the TDR mechanism on
14
13
12
11
10
9
TD Peak Polarity 4
TD Peak Polarity 3
TD Peak Polarity 2
TD Peak Polarity 1
RD Peak Polarity 5
RD Peak Polarity 4
RD Peak Polarity 3
RD Peak Polarity 2
RD Peak Polarity 1
Cross Detect on TD
Cross Detect on RD
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
0
0
Transmit Channel (TD).
Polarity of the Third peak discovered by the TDR mechanism on
Transmit Channel (TD).
Polarity of the Second peak discovered by the TDR mechanism on
Transmit Channel (TD).
Polarity of the First peak discovered by the TDR mechanism on
Transmit Channel (TD).
Polarity of the Fifth peak discovered by the TDR mechanism on
Receive Channel (RD).
Polarity of the Fourth peak discovered by the TDR mechanism on
Receive Channel (RD).
Polarity of the Third peak discovered by the TDR mechanism on
8
Receive Channel (RD).
Polarity of the Second peak discovered by the TDR mechanism on
7
Receive Channel (RD).
Polarity of the First peak discovered by the TDR mechanism on
6
Receive Channel (RD).
Cross Reflections were detected on TD. Indicate on Short between
TD and TD
5
Cross Reflections were detected on RD. Indicate on Short between
TD and RD
4
3
2
Above 5 TD Peaks
Above 5 RD Peaks
Reserved
RO
RO
RO
0
0
0
More than 5 reflections were detected on TD
More than 5 reflections were detected on RD
Reserved
1:0
表8-79. 0x0215 ALCD Control and Results 2 Register (ALCDRR2)
BIT
15:4
3:0
NAME
TYPE
DEFAULT
FUNCTION
0000 0000
0000
Reserved
RO
Reserved
PGA Control
RO
1111
Control word to analog PGA
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表8-80. 0x021D ALCD Control and Results 3 Register (ALCDRR3)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:12
Reserved
RO
0
Reserved
0110 0000
0000
11:0
FAGC Accumulator
RW
FAGC Accumulator
表8-81. 0x0403 Line Driver Control Register (LDCTRL)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:12
Reserved
RW
1001
Reserved
100Base-FX Line Driver Swing Select (peak-to-peak):
0000 = 0.533-V
0001 = 0.567-V
0010 = 0.600-V
0011 = 0.633-V
0100 = 0.667-V
0101 = 0.700-V
0110 = 0.733-V
100Base-FX Line Driver Swing
Select
11:8
RW
1111
0111 = 0.767-V
1000 = 0.800-V
1001 = 0.833-V
1010 = 0.867-V
1011 = 0.900-V
1100 = 0.933-V
1101 = 0.976-V
1110 = 1.000-V
1111 = 1.033-V (Default Setting)
100Base-TX Line Driver Swing Select (peak-to-peak):
0000 = 1.600-V
0001 = 1.633-V
0010 = 1.667-V
0011 = 1.700-V
0100 = 1.733-V
0101 = 1.767-V
0110 = 1.800-V
100Base-TX Line Driver Swing
Select
7:4
RW
1100
0111 = 1.833-V
1000 = 1.867-V
1001 = 1.900-V
1010 = 1.933-V
1011 = 1.967-V
1100 = 2.000-V (Default Setting)
1101 = 2.033-V
1110 = 2.067-V
1111 = 2.100-V
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表8-81. 0x0403 Line Driver Control Register (LDCTRL) (continued)
NAME
TYPE
DEFAULT
FUNCTION
10Base-Te Line Driver Swing Select:
0000 = 3.200-V
0001 = 3.233-V
0010 = 3.267-V
0011 = 3.300-V
0100 = 3.333-V
0101 = 3.367-V
0110 =3.400-V
10Base-Te Line Driver Swing
Select
3:0
RW
1111
0111 = 3.433-V
1000 = 3.467-V
1001 = 3.500-V
1010 = 3.533-V
1011 = 3.567-V
1100 = 3.600-V
1101 = 3.633-V
1110 = 3.667-V
1111 = 3.700-V (Default Setting)
表8-82. 0x0404 Line Driver Class Selection (LDCSEL)
BIT
NAME
TYPE
DEFAULT
FUNCTION
0x0020 : Reduced MLT-3 (Class B)
0x0024 : To program full MLT-3 on both Tx+ and Tx–(Class A)
15:0
Line Driver Class Selection
RW
0020
表8-83. 0x040D Auto-neg Energy Threshold Register
BIT
NAME
TYPE
DEFAULT
FUNCTION
15: 5
4:0
Reserved
RW
0000 0000 000
Decides threshold of energy
Auto-neg Energy Threshold Value
RW
0 1000
detection during auto-negotiation
表8-84. 0x0410 DC Correction Control Register
BIT
NAME
TYPE
DEFAULT
FUNCTION
15
Reserved
RW
0
Reserved
1 = Enable Fixed Value of DC
Correction
14
Enable Fixed DC Correction
Reserved
RW
RW
0
13:0
10 0000 0000 0000
表8-85. 0x0416 Analog Filter Control Register 1
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:13
Reserved
RW
000
Reserved
Controls the cut-off frequency of
filter 1
12:8
7:0
Filter 1 cut-off
Reserved
RW
RW
01000
0111 0000
Reserved
表8-86. 0x0418 Analog Equalizer Control Register
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:14
Reserved
RW
00
Reserved
Analog equalizer controls useful
for short shielded cables
13:8
Analog Equalizer Control
RW
0000 00
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表8-86. 0x0418 Analog Equalizer Control Register (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
7:0
Reserved
RW
0000 0000
Reserved
表8-87. 0x041F Analog Power Detect Control
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:13
Reserved
RW
000
Reserved
Force AVDD to be detected as
3.3V
1=Force AVDD to be detected as
3.3V
12
Force AVDD Detect
RW
0
0=Internal circuit detects the
AVDD supply level
Force AVDDIO to be detected as
3.3V
11 = Force AVDDIO to be
detected as 3.3V
11:10
9:0
Force AVDDIO Detect
Reserved
RW
RW
00
00 = Internal circuit detects the
AVDDIO supply level
00 0000 0000
Reserved
A. For specific applications which require bypassing auto supply detection, registers 0x0421 and 0x041F can be used to program specific
supply levels
表8-88. 0x0421 Analog Power Detect Status
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:3
Reserved
RO
0
Reserved
1 for 3.3V AVDD
0 for 1.8V AVDD
2
AVDD Level
VDDIO Level
RO
RO
AVDD level indication
VDDIO level indication
11 for 3.3V VDDIO
00 for 1.8V VDDIO
01 for 2.5V VDDIO
1:0
表8-89. 0x0428 Deep Power Down Control Register (DPDWN)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:6
Reserved
RO
0
Reserved
MSB 100Base-TX Idle Pattern:
100Base-TX Test Mode is determined by bits {[5] in register 0x0428,
[3:0] in register 0x0027}. The bits determine the number of 0's to
follow a '1'.
0,0001 = Single '0' after a '1'
0,0010 = Two '0' after a '1'
0,0011 = Three '0' after a '1'
5
MSB 100Base-TX Idle Pattern
RW
0
0,0100 = Four '0' after a '1'
0,0101 = Five '0' after a '1'
0,0110 = Six '0' after a '1'
0,0111 = Seven '0' after a '1' .
..
1,1111 = Thirty one '0' after a '1'
0,0000 = Clears the shift register
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表8-89. 0x0428 Deep Power Down Control Register (DPDWN) (continued)
NAME
TYPE
DEFAULT
FUNCTION
100Base-TX Idle Pattern Test Mode:
1 = 100Base-TX Idle Pattern Enable
100Base-TX Idle Pattern Test
Mode
4
3
RW
0
0 = Normal operation
When enabled, 100Base-TX Idle Pattern is determined by bit[5] in
register 0x0428 and bits[3:0] in register 0x0027.
Deep Power Down Speed Selection:
Deep Power Down Speed
RW
0
1 = 50ms duration to exit Deep Power Down
0 = 100ms duration to exit Deep Power Down
Deep Power Down Enable:
1 = Deep Power Down activated
0 = Normal operation
2
Deep Power Down Enable
RW
RW
0
0
Note: If set, the DP83822 enters into deep power down mode. Deep
power down mode requires that IEEE Power Down be enabled first by
either register access (set bit[11] = '1' in register 0x0000) or using INT/
PWDN pin.
1:0
Reserved
Reserved
表8-90. 0x0450 DSP Configuration Register 6 (DSPCR6)
BIT
15:14
13
NAME
TYPE
DEFAULT
FUNCTION
Reserved
Reserved
RW
00
Equalizer Calibration Bypass
Reserved
RW
0
1 = Bypass equalizer calibration
Reserved
12:0
RW
0 0001 0100 0001
表8-91. 0x0456 General Configuration Register (GENCFG)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:4
Reserved
RW
0
Reserved
Min IPG Enable:
1 = Enable Minimum Inter-Packet Gap (IPG is set to 120ns)
0 = IPG set to 0.20μs
3
Min IPG Enable
Reserved
RW
RW
1
0
Note:
IPGs <200ns should only be used when operating with a MII MAC IF
configuration.
2:0
Reserved
表8-92. 0x0460 LEDs Configuration Register #1 (LEDCFG1)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:12
Reserved
RO
0
Reserved
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表8-92. 0x0460 LEDs Configuration Register #1 (LEDCFG1) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
LED_1 Control:
Selects the source for LED_1.
0000 = LINK OK
0001 = RX/TX Activity
0010 = TX Activity
0011 = RX Activity
0100 = Collision
0101 = Speed, High for 100Base-TX
0110 = Speed, High for 10Base-Te
0111 = Full-Duplex
1000 = LINK OK / BLINK on TX/RX Activity
1001 = Active Stretch Signal
1010 = MII LINK (100BT+FD)
1011 = LPI Mode (EEE)
1100 = TX/RX MII Error
1101 = Link Lost
11:8
LED_1 Control
RW
0101
1110 = Blink for PRBS error
1111 = Reserved
Link Lost, LED remains ON until BMCR register (address 0x0001) is
read.
Blink for PRBS Errors, LED remains ON for single error and remains
until BICSR1 register (address 0x001B) is cleared.
LED_3 Control:
7:4
3:0
LED_3 Control (RX_D3)
Reserved
RW
RW
0101
0001
Selects the source for RX_D3. Please reference bits[11:8] for list of
sources.
Reserved
表8-93. 0x0461 IO MUX GPIO Control Register (IOCTRL)
BIT
NAME
TYPE
DEFAULT
FUNCTION
0000 0100
000
15:5
Reserved
RW
Reserved
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表8-93. 0x0461 IO MUX GPIO Control Register (IOCTRL) (continued)
NAME
TYPE
DEFAULT
FUNCTION
MAC Impedance Control:
MAC interface impedance control sets the series termination for the
digital pins.
0 000 = 99.25 Ω
0 001 = 91.13 Ω
0 010 = 84.24 Ω
0 011 = 78.31 Ω
0 100 = 73.17 Ω
0 101 = 68.65 Ω
0 110 = 64.66 Ω
4:1
MAC Impedance Control
RW
1 000
0 111 = 61.11 Ω
1 000 = 58.07 Ω(Default Setting)
1 001 = 55.18 Ω
1 010 = 52.57 Ω
1 011 = 50.20 Ω
1 100 = 48.03 Ω
1 101 = 46.04 Ω
1 110 = 44.20 Ω
1 111 = 42.51 Ω
0
Reserved
RW
0
Reserved
表8-94. 0x0462 IO MUX GPIO Control Register #1 (IOCTRL1)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15
Reserved
RO
0
Reserved
Clock Source:
If RX_D3 is configured as a clock source from bits[10:8] the following
field determines the reference
000 = MAC IF Clock
001 = XI Clock (Pass-Through Clock from XI pin)
010 = Internal Reference Clock: 25-MHz
011 = Reserved
100 = RMII Master Mode Reference Clock: 50-MHz
101 = Reserved
14:12 RX_D3 / GPIO_3 Clock Source
RW
000
110 = Free Running Clock: 125-MHz
111 = Recovered Clock: 125-MHz
MAC IF Clock: MII Mode the clock frequency is 25-MHz, RMII Mode
the clock frequency is 50-MHz; RGMII Mode the clock frequency is
25-MHz.
RMII Master Mode Reference Clock: Identical to MAC IF Clock in
RMII Master Mode.
11
Reserved
RO
0
Reserved
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表8-94. 0x0462 IO MUX GPIO Control Register #1 (IOCTRL1) (continued)
BIT
10:8
7
NAME
RX_D3 / GPIO_3 Control
Reserved
TYPE
DEFAULT
FUNCTION
RX_D3 GPIO Configuration:
000 = Normal operation
001 = LED_3 (Default: Speed, High for 100Base-TX)
010 = WoL
RW
000
011 = Clock reference according to bits[14:12]
100 = IEEE 1588 TX Indication
101 = IEEE 1588 RX Indication
110 = Constant '0'
111 = Constand '1'
RO
0
Reserved
Clock Source:
If LED_1 is configured as a clock source from bits[2:0] the following
field determines the reference
000 = MAC IF Clock
001 = XI Clock (Pass-Through Clock from XI pin)
010 = Internal Reference Clock: 25-MHz
011 = Reserved
100 = RMII Master Mode Reference Clock: 50-MHz
101 = Reserved
6:4
LED_1 / GPIO_1 Clock Source
RW
000
110 = Free Running Clock: 125-MHz
111 = Recovered Clock: 125-MHz
MAC IF Clock: MII Mode the clock frequency is 25-MHz, RMII Mode
the clock frequency is 50-MHz; RGMII Mode the clock frequency is
25-MHz.
RMII Master Mode Reference Clock: Identical to MAC IF Clock in
RMII Master Mode.
3
Reserved
RO
0
Reserved
LED_1 GPIO Configuration:
000 = Tri-state
001 = LED_1 (Default: Speed, High for 100Base-TX)
010 = WoL
2:0
LED_1 / GPIO_1 Control
RW, Strap 000
011 = Clock reference according to bits[6:4]
100 = IEEE 1588 TX Indication
101 = IEEE 1588 RX Indication
110 = Constant '0'
111 = Constand '1'
表8-95. 0x0463 IO MUX GPIO Control Register #2 (IOCTRL2)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:7
Reserved
RO
0
Reserved
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表8-95. 0x0463 IO MUX GPIO Control Register #2 (IOCTRL2) (continued)
NAME
TYPE
DEFAULT
FUNCTION
Clock Source:
If COL is configured as a clock source from bits[2:0] the following field
determines the reference
000 = MAC IF Clock
001 = XI Clock (Pass-Through Clock from XI pin)
010 = Internal Reference Clock: 25-MHz
011 = Reserved
100 = RMII Master Mode Reference Clock: 50-MHz
101 = Reserved
6:4
COL / GPIO_2 Clock Source
RW
000
110 = Free Running Clock: 125-MHz
111 = Recovered Clock: 125-MHz
MAC IF Clock: MII Mode the clock frequency is 25-MHz, RMII Mode
the clock frequency is 50-MHz; RGMII Mode the clock frequency is
25-MHz.
RMII Master Mode Reference Clock: Identical to MAC IF Clock in
RMII Master Mode.
3
Reserved
RO
RW
0
Reserved
COL GPIO Configuration:
000 = Normal operation
001 = MLED (Register 0x0025)
010 = WoL
2:0
COL / GPIO_2 Control
000
011 = Clock reference according to bits[6:4]
100 = IEEE 1588 TX Indication
101 = IEEE 1588 RX Indication
110 = Constant '0'
111 = Constand '1'
表8-96. 0x0465 Fiber General Configuration Register (FIBER GENCFG)
BIT
NAME
TYPE
DEFAULT
FUNCTION
1111 1111
0000 000
15:1
Reserved
RW
Reserved
100Base-FX Signal Detect Polarity:
1 = Signal Detect is Active LOW
0 = Signal Detect is Active HIGH
When set to Active HIGH, Link drop will occur if SD pin senses a LOW
state (SD = '0').
100Base-FX Signal Detect
Polarity
0
RW
0
When set to Active LOW, Link drop will occur if SD pin senses a HIGH
state (SD = '1').
Note: To enable 100Base-FX Signal Detection on LED_1 (pin #24),
strap SD_EN = '1'
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表8-97. 0x0467 Strap Latch-In Register #1 (SOR1)
BIT
NAME
TYPE
DEFAULT
FUNCTION
RX_D1 Strap Mode:
00 = Mode 1
01 = Mode 2
10 = Mode 3
11 = Mode 4
15:14
RX_D1 Strap Mode
RO, Strap 00
Please refer to the strap section in the datasheet for information
regarding PHY configuration.
Note: Bit values ('00', '01', '10', '11') are just used to indicate the Strap
Mode and do not reflect the same bit sequence that is defined in the
strap section of the datasheet.
RX_D0 Strap Mode:
13:12
11:10
9:8
RX_D0 Strap Mode
COL Strap Mode
RX_ER Strap Mode
CRS Strap Mode
RO, Strap 00
RO, Strap 11
RO, Strap 11
RO, Strap 11
RO, Strap 00
Use same reference as defined by bits[15:14] in this register.
COL Strap Mode:
Use same reference as defined by bits[15:14] in this register.
RX_ER Strap Mode:
Use same reference as defined by bits[15:14] in this register.
CRS Strap Mode:
7:6
Use same reference as defined by bits[15:14] in this register.
RX_DV Strap Mode:
5:4
3:2
RX_DV Strap Mode
Reserved
Use same reference as defined by bits[15:14] in this register.
RO
00
Reserved
LED_0 Strap Mode:
00 = Mode 1
01 = Reserved
10 = Reserved
11 = Mode 4
1:0
LED_0 Strap Mode
RO, Strap 11
Please refer to the strap section in the datasheet for information
regarding PHY configuration.
Note: Bit values ('00', '01', '10', '11') are just used to indicate the Strap
Mode and do not reflect the same bit sequence that is defined in the
strap section of the datasheet.
表8-98. 0x0468 Strap Latch-In Register #2 (SOR2)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:4
Reserved
RO
0
Reserved
RX_D3 Strap Mode:
3:2
1:0
RX_D3 Strap Mode
RX_D2 Strap Mode
RO, Strap 00
RO, Strap 00
Use same reference as defined by bits[15:14] in register 0x0467.
RX_D2 Strap Mode:
Use same reference as defined by bits[15:14] in register 0x0467.
表8-99. 0x0469 LEDs Configuration Register #2 (LEDCFG2)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:11
Reserved
RO
0
Reserved
LED_1 Polarity:
1 = Active High
0 = Active Low
10
LED_1 Polarity
RW
0
Value depends upon pull configuration on LED_1 pin.
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表8-99. 0x0469 LEDs Configuration Register #2 (LEDCFG2) (continued)
NAME
TYPE
DEFAULT
FUNCTION
LED_1 Force Override Value:
9
8
LED_1 Force Override Value
LED_1 Force Override Enable
RW
0
1 = LED_1 forced High
0 = LED_1 forced Low
LED_1 Force Override Enable:
1 = Enable Force Override
RW
0
0 = Disable Force Override
When enabled, bit[9] in this register determines state of LED_1.
7
6
Reserved
RO
RW
0
1
Reserved
LED_3 Polarity:
1 = Active High
0 = Active Low
LED_3 Polarity
LED_3 Force Override Value:
1 = RX_D3 forced High
5
LED_3 Force Override Value
RW
0
0 = RX_D3 forced Low
LED_3 Force Override Enable:
1 = Enable Force Override
4
LED_3 Force Override Enable
Reserved
RW
RO
0
0
0 = Disable Force Override
When enabled, bit[5] in this register determines state of RX_D3.
3:0
Reserved
表8-100. 0x04A0 Receive Configuration Register (RXFCFG)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Bit Nibble Swap:
00 = Normal order, no swap (RXD[3:0])
15:14
Bit Nibble Swap
RW
00
01 = Swap bits order (RXD[0:3])
10 = Swap nibbles order (RXD[3:0] , RXD[7:4])
11 = Swap bits order in each nibble (RXD[4:7] , RXD[0:3])
SFD Byte Search:
13
12
11
SFD Byte
CRC Gate
RW
RW
0
1
0
1 = SFD is 0x5D (i.e. Receive module searches for 0x5D)
0 = SFD is 0xD5 (i.e. Receive module searches for 0xD5)
CRC Gate:
1 = Bad CRC gates Magic Packet and Pattern Indications
0 = Bad CRC does not gate Magic Packet or Pattern Indications
If Magic Packet has Bad CRC there will be no indication (status,
interrupt, GPIO) when enabled.
WoL Level Change Indication Clear:
If WoL Indication is set for Level change mode, this bit clears the level
upon a write.
WoL Level Change Indication
Clear
W, SC
WoL Pulse Indication Select:
Only valid when WoL Indication is set for Pulse mode.
00 = 8 clock cycles (of 125-MHz clock)
01 = 16 clock cycles
10:9
WoL Pulse Indication Select
WoL Indication Select
RW
RW
00
10 = 32 clock cycles
11 = 64 clock cycles
WoL Indication Select:
1 = Level change mode
0 = Pulse mode
8
0
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表8-100. 0x04A0 Receive Configuration Register (RXFCFG) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
WoL Enable:
7
WoL Enable
RW
0
1 = Enable Wake-on-LAN (WoL)
0 = Normal operation
6
5
Bit Mask Flag
Secure-ON Enable
Reserved
RW
RW
RW
RW
RW
0
0
0
0
0
Bit Mask Flag
Enable Secure-ON password for Magic Packets
4:2
1
Reserved
WoL Pattern Enable
WoL Magic Packet Enable
Enable Interrupt upon reception of packet with configured pattern
Enable Interrupt upon reception of Magic Packet
0
表8-101. 0x04A1 Receive Status Register (RXFS)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:13
Reserved
RO
0
Reserved
WoL Interrupt Source:
Source of Interrupt for bit[1] of register 0x0013.
1 = WoL Interrupt
12
WoL Interrupt Source
RW
RO
0
0
0 = Data Polarity Interrupt
When enabling WoL, this bit is automatically set to WoL Interrupt.
11:8
7
Reserved
SFD Error
Reserved
SFD Error:
RO, LH, SC 0
RO, LH, SC 0
1 = Packet with SFD error
0 = No SFD error
Bad CRC:
6
Bad CRC
1 = Bad CRC was received
0 = No bad CRC received
Secure-ON Hack Flag:
5
4:2
1
Secure-On Hack Flag
Reserved
RO, LH, SC 0
RO, LH, SC 0
RO, LH, SC 0
1 = Invalid Password detected in Magic Packet
0 = Valid Secure-ON Password
Reserved
WoL Pattern Status:
WoL Pattern Status
1 = Valid packet with configured pattern received
0 = No valid packet with configured pattern received
WoL Magic Packet Status:
0
WoL Magic Packet Status
RO, LH, SC 0
1 = Valid Magic Packet received
0 = No valid Magic Packet received
表8-102. 0x04A2 Receive Perfect Match Data Register #1 (RXFPMD1)
BIT
NAME
TYPE
DEFAULT
FUNCTION
MAC Destination Address Byte
4
Perfect Match Data:
15:8
RW
0
Configured for MAC Destination Address
MAC Destination Address Byte
5
Perfect Match Data:
7:0
RW
0
Configured for MAC Destination Address
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表8-103. 0x04A3 Receive Perfect Match Data Register #2 (RXFPMD2)
NAME
TYPE
DEFAULT
FUNCTION
MAC Destination Address Byte
2
Perfect Match Data:
15:8
7:0
RW
0
Configured for MAC Destination Address
MAC Destination Address Byte
3
Perfect Match Data:
RW
0
Configured for MAC Destination Address
表8-104. 0x04A4 Receive Perfect Match Data Register #3 (RXFPMD3)
BIT
NAME
TYPE
DEFAULT
FUNCTION
MAC Destination Address Byte
0
Perfect Match Data:
15:8
RW
0
Configured for MAC Destination Address
MAC Destination Address Byte
1
Perfect Match Data:
7:0
RW
0
Configured for MAC Destination Address
表8-105. 0x04A5 Receive Secure-ON Password Register #1 (RXFSOP1)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Secure-ON Password Select:
15:8
Secure-ON Password Byte 1
RW
0
Secure-ON password for Magic Packets
Secure-ON Password Select:
7:0
Secure-ON Password Byte 0
RW
0
Secure-ON password for Magic Packets
表8-106. 0x04A6 Receive Secure-ON Password Register #2 (RXFSOP2)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Secure-ON Password Select:
15:8
Secure-ON Password Byte 3
RW
0
Secure-ON password for Magic Packets
Secure-ON Password Select:
7:0
Secure-ON Password Byte 2
RW
0
Secure-ON password for Magic Packets
表8-107. 0x04A7 Receive Secure-ON Password Register #3 (RXFSOP3)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Secure-ON Password Select:
15:8
Secure-ON Password Byte 5
RW
0
Secure-ON password for Magic Packets
Secure-ON Password Select:
7:0
Secure-ON Password Byte 4
RW
0
Secure-ON password for Magic Packets
表8-108. 0x04A8 Receive Pattern Register #1 (RXFPAT1)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 1
RW
0
Configures byte 1 of the pattern
Pattern Configuration:
7:0
Pattern Byte 0
RW
0
Configures byte 0 of the pattern
表8-109. 0x04A9 Receive Pattern Register #2 (RXFPAT2)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
Configures byte 3 of the pattern
15:8
Pattern Byte 3
RW
0
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表8-109. 0x04A9 Receive Pattern Register #2 (RXFPAT2) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
Configures byte 2 of the pattern
7:0
Pattern Byte 2
RW
0
表8-110. 0x04AA Receive Pattern Register #3 (RXFPAT3)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 5
RW
0
Configures byte 5 of the pattern
Pattern Configuration:
7:0
Pattern Byte 4
RW
0
Configures byte 4 of the pattern
表8-111. 0x04AB Receive Pattern Register #4 (RXFPAT4)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 7
RW
0
Configures byte 7 of the pattern
Pattern Configuration:
7:0
Pattern Byte 6
RW
0
Configures byte 6 of the pattern
表8-112. 0x04AC Receive Pattern Register #5 (RXFPAT5)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 9
RW
0
Configures byte 9 of the pattern
Pattern Configuration:
7:0
Pattern Byte 8
RW
0
Configures byte 8 of the pattern
表8-113. 0x04AD Receive Pattern Register #6 (RXFPAT6)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 11
RW
0
Configures byte 11 of the pattern
Pattern Configuration:
7:0
Pattern Byte 10
RW
0
Configures byte 10 of the pattern
表8-114. 0x04AE Receive Pattern Register #7 (RXFPAT7)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 13
RW
0
Configures byte 13 of the pattern
Pattern Configuration:
7:0
Pattern Byte 12
RW
0
Configures byte 12 of the pattern
表8-115. 0x04AF Receive Pattern Register #8 (RXFPAT8)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 15
RW
0
Configures byte 15 of the pattern
Pattern Configuration:
7:0
Pattern Byte 14
RW
0
Configures byte 14 of the pattern
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表8-116. 0x04B0 Receive Pattern Register #9 (RXFPAT9)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 17
RW
0
Configures byte 17 of the pattern
Pattern Configuration:
7:0
Pattern Byte 16
RW
0
Configures byte 16 of the pattern
表8-117. 0x04B1 Receive Pattern Register #10 (RXFPAT10)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 19
RW
0
Configures byte 19 of the pattern
Pattern Configuration:
7:0
Pattern Byte 18
RW
0
Configures byte 18 of the pattern
表8-118. 0x04B2 Receive Pattern Register #11 (RXFPAT11)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 21
RW
0
Configures byte 21 of the pattern
Pattern Configuration:
7:0
Pattern Byte 20
RW
0
Configures byte 20 of the pattern
表8-119. 0x04B3 Receive Pattern Register #12 (RXFPAT12)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 23
RW
0
Configures byte 23 of the pattern
Pattern Configuration:
7:0
Pattern Byte 22
RW
0
Configures byte 22 of the pattern
表8-120. 0x04B4 Receive Pattern Register #13 (RXFPAT13)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 25
RW
0
Configures byte 25 of the pattern
Pattern Configuration:
7:0
Pattern Byte 24
RW
0
Configures byte 24 of the pattern
表8-121. 0x04B5 Receive Pattern Register #14 (RXFPAT14)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 27
RW
0
Configures byte 27 of the pattern
Pattern Configuration:
7:0
Pattern Byte 26
RW
0
Configures byte 26 of the pattern
表8-122. 0x04B6 Receive Pattern Register #15 (RXFPAT15)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
Configures byte 29 of the pattern
15:8
Pattern Byte 29
RW
0
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表8-122. 0x04B6 Receive Pattern Register #15 (RXFPAT15) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
Configures byte 28 of the pattern
7:0
Pattern Byte 28
RW
0
表8-123. 0x04B7 Receive Pattern Register #16 (RXFPAT16)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 31
RW
0
Configures byte 31 of the pattern
Pattern Configuration:
7:0
Pattern Byte 30
RW
0
Configures byte 30 of the pattern
表8-124. 0x04B8 Receive Pattern Register #17 (RXFPAT17)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 33
RW
0
Configures byte 33 of the pattern
Pattern Configuration:
7:0
Pattern Byte 32
RW
0
Configures byte 32 of the pattern
表8-125. 0x04B9 Receive Pattern Register #18 (RXFPAT18)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 35
RW
0
Configures byte 35 of the pattern
Pattern Configuration:
7:0
Pattern Byte 34
RW
0
Configures byte 34 of the pattern
表8-126. 0x04BA Receive Pattern Register #19 (RXFPAT19)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 37
RW
0
Configures byte 37 of the pattern
Pattern Configuration:
7:0
Pattern Byte 36
RW
0
Configures byte 36 of the pattern
表8-127. 0x04BB Receive Pattern Register #20 (RXFPAT20)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 39
RW
0
Configures byte 39 of the pattern
Pattern Configuration:
7:0
Pattern Byte 38
RW
0
Configures byte 38 of the pattern
表8-128. 0x04BC Receive Pattern Register #21 (RXFPAT21)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 41
RW
0
Configures byte 41 of the pattern
Pattern Configuration:
7:0
Pattern Byte 40
RW
0
Configures byte 40 of the pattern
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表8-129. 0x04BD Receive Pattern Register #22 (RXFPAT22)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 43
RW
0
Configures byte 43 of the pattern
Pattern Configuration:
7:0
Pattern Byte 42
RW
0
Configures byte 42 of the pattern
表8-130. 0x04BE Receive Pattern Register #23 (RXFPAT23)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 45
RW
0
Configures byte 45 of the pattern
Pattern Configuration:
7:0
Pattern Byte 44
RW
0
Configures byte 44 of the pattern
表8-131. 0x04BF Receive Pattern Register #24 (RXFPAT24)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 47
RW
0
Configures byte 47 of the pattern
Pattern Configuration:
7:0
Pattern Byte 46
RW
0
Configures byte 46 of the pattern
表8-132. 0x04C0 Receive Pattern Register #25 (RXFPAT25)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 49
RW
0
Configures byte 49 of the pattern
Pattern Configuration:
7:0
Pattern Byte 48
RW
0
Configures byte 48 of the pattern
表8-133. 0x04C1 Receive Pattern Register #26 (RXFPAT26)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 51
RW
0
Configures byte 51 of the pattern
Pattern Configuration:
7:0
Pattern Byte 50
RW
0
Configures byte 50 of the pattern
表8-134. 0x04C2 Receive Pattern Register #27 (RXFPAT27)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 53
RW
0
Configures byte 53 of the pattern
Pattern Configuration:
7:0
Pattern Byte 52
RW
0
Configures byte 52 of the pattern
表8-135. 0x04C3 Receive Pattern Register #28 (RXFPAT28)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
Configures byte 55 of the pattern
15:8
Pattern Byte 55
RW
0
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表8-135. 0x04C3 Receive Pattern Register #28 (RXFPAT28) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
Configures byte 54 of the pattern
7:0
Pattern Byte 54
RW
0
表8-136. 0x04C4 Receive Pattern Register #29 (RXFPAT29)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 57
RW
0
Configures byte 57 of the pattern
Pattern Configuration:
7:0
Pattern Byte 56
RW
0
Configures byte 56 of the pattern
表8-137. 0x04C5 Receive Pattern Register #30 (RXFPAT30)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 59
RW
0
Configures byte 59 of the pattern
Pattern Configuration:
7:0
Pattern Byte 58
RW
0
Configures byte 58 of the pattern
表8-138. 0x04C6 Receive Pattern Register #31 (RXFPAT31)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 61
RW
0
Configures byte 61 of the pattern
Pattern Configuration:
7:0
Pattern Byte 60
RW
0
Configures byte 60 of the pattern
表8-139. 0x04C7 Receive Pattern Register #32 (RXFPAT32)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Configuration:
15:8
Pattern Byte 63
RW
0
Configures byte 63 of the pattern
Pattern Configuration:
7:0
Pattern Byte 62
RW
0
Configures byte 62 of the pattern
表8-140. 0x04C8 Receive Pattern Byte Mask Register #1 (RXFPBM1)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Byte Mask Configuration:
15:0
Mask Bytes 0 to 15
RW
0
Configures masks for bytes 0 to 15.
For each byte '1' means it is masked.
表8-141. 0x04C9 Receive Pattern Byte Mask Register #2 (RXFPBM2)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Byte Mask Configuration:
15:0
Mask Bytes 16 to 31
RW
0
Configures masks for bytes 16 to 31.
For each byte '1' means it is masked.
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表8-142. 0x04CA Receive Pattern Byte Mask Register #3 (RXFPBM3)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Byte Mask Configuration:
15:0
Mask Bytes 32 to 47
RW
0
Configures masks for bytes 32 to 47.
For each byte '1' means it is masked.
表8-143. 0x04CB Receive Pattern Byte Mask Register #4 (RXFPBM4)
BIT
NAME
TYPE
DEFAULT
FUNCTION
Pattern Byte Mask Configuration:
15:0
Mask Bytes 48 to 63
RW
0
Configures masks for bytes 48 to 63.
For each byte '1' means it is masked.
表8-144. 0x04CC Receive Pattern Control Register (RXFPATC)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:6
Reserved
RO
0
Reserved
Pattern Start Point:
Number of bytes after SFD where comparison begins on RX packets
to the configured pattern.
00000 = Start compare on 1st byte after SFD
00001 = Start compare on 2nd byte after SFD
...
5:0
Pattern Start Point
RW
01100
01100 = Start compare on 13th byte (Default)
Default setting is 0xC, which means the pattern comparision will begin
after source and destination addresses since they are each 6 bytes.
表8-145. 0x04D0 Energy Efficient Ethernet Configuration Register #2 (EEECFG2)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15
Reserved
RO
0
Reserved
TX_ER for LPI Request:
14
TX_ER for LPI Request
Reserved
RW
RO
0
1 = TX_ER used for LPI Request
0 = TX_ER not used for LPI Request
13:7
00 0011 0
Reserved
TX_ER Pin Select:
00 = No Pin Selected
01 = INT/PWDN
6:5
4:0
TX_ER Pin Select
Reserved
RW
RO
00
10 = COL/GPIO
11 = No Pin Selected
0 0010
Reserved
表8-146. 0x04D1 Energy Efficient Ethernet Configuration Register #2 (EEECFG3)
BIT
NAME
TYPE
DEFAULT
FUNCTION
0000 0001
1000
15:4
Reserved
RW
Reserved
EEE Advertise Bypass:
1 = Bit [0] determines EEE Auto-Negotiation Abilities
0 = MMD3 and MMD7 determine EEE Auto-Negotiation Abilities
Allows for EEE Advertisment during Auto-Negotiation to be
determined by bit[0] in register 0x04D1 rather than the Next Page
Registers (Register 0x003C and Register 0x003D in MMD7).
3
EEE Capabilities Bypass
RW
1
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表8-146. 0x04D1 Energy Efficient Ethernet Configuration Register #2 (EEECFG3) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
EEE Next Page Disable:
2
EEE Next Page Disable
RW
0
1 = Reception of EEE Next Pages is disabled
0 = Reception of EEE Next Pages is enabled
EEE RX Path Shutdown:
1
0
EEE RX Path Shutdown
EEE Capabilities Enable
RW
1
1
1= Enable shutdown of Analog RX path at LPI_Quiet
0 = Analog RX path is active during LPI_Quiet
EEE Capabilities Enable:
1 = PHY supports EEE capabilities
0 = PHY does not support EEE
When enabled, Auto-Negotiation will negotiate to EEE as defined by
register 0x003C and register 0x003D in MMD7.
When disabled, register 0x0014 in MMD3, register 0x003C and
register 0x003D in MMD7 are ignored.
RW, Strap
Bit should be written to 0 (irrespective of strap used) to disable EEE.
表8-147. 0x04D4 TLOOP Bandwidth Control Register 1 (TLBCR1)
BIT
NAME
TYPE
DEFAULT
FUNCTION
0111 0010
0010 0000
15:0
Reserved
RW
Reserved
表8-148. 0x04D5 TLOOP Bandwidth Control Register 2 (TLBCR2)
BIT
NAME
TYPE
DEFAULT
FUNCTION
1111 1011
1100 0001
15:0
Reserved
RW
Reserved
表8-149. 0x04D6 TLOOP Bandwidth Control Register 3 (TLBCR3)
BIT
NAME
TYPE
DEFAULT
FUNCTION
0000 0001
1100 0001
15:0
Reserved
RW
Reserved
表8-150. 0x3000 MMD3 PCS Control Register #1 (MMD3_PCS_CTRL_1)
BIT
NAME
TYPE
DEFAULT
FUNCTION
PCS Reset:
1 = Soft Reset of MMD3, MMD7 and PCS registers
0 = Normal operation
15
PCS Reset
RW, SC
0
Reset clears MMD3, MMD7 and PCS registers. Reset does not clear
Vendor Specific Registers (DEVAD = 31).
14:11
10
Reserved
RO
RW
000 0
1
Reserved
RX Clock Stoppable:
RX Clock Stoppable
1 = Receive Clock stoppable during LPI
0 = Receive Clock not stoppable
00 0000
0000
9:0
Reserved
RO
Reserved
表8-151. 0x3001 MMD3 PCS Status Register #1 (MMD3_PCS_STATUS_1)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:12
Reserved
RO
0
Reserved
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表8-151. 0x3001 MMD3 PCS Status Register #1 (MMD3_PCS_STATUS_1) (continued)
BIT
NAME
TYPE
DEFAULT
FUNCTION
TX LPI Received:
11
TX LPI Received
RO
0
1 = TX PCS has received LPI
0 = LPI not received
RX LPI Received:
10
9
RX LPI Received
TX LPI Indication
RO
RO
0
0
1 = RX PCS has received LPI
0 = LPI not received
TX LPI Indication:
1 = TX PCS is currently receiving LPI
0 = TX PCS is not currently receiving LPI
RX LPI Indication:
8
7
RX LPI Indication
Reserved
RO
RO
RO
RO
0
0
1
0
1 = RX PCS is currently receiving LPI
0 = RX PCS is not currenly receiving LPI
Reserved
TX Clock Stoppable:
6
TX Clock Stoppable
Reserved
1 = MAC may stop clock during LPI
0 = TX Clock is not stoppable
5:0
Reserved
表8-152. 0x3014 MMD3 Energy Efficient Ethernet Capability Register (MMD3_EEE_CAPABILITY)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:3
Reserved
RO
0
Reserved
EEE 1Gbps Enable:
2
EEE 1Gbps Enable
RO
0
1 = EEE is supported for 1000Base-T
0 = EEE is not supported for 1000Base-T
EEE 100Mbps Enable:
1
0
EEE 100Mbps Enable
Reserved
RO
RO
1
0
1 = EEE is supported for 100Base-TX
0 = EEE is not supported for 100Base-TX
Reserved
表8-153. 0x3016 MMD3 Wake Error Counter Register (MMD3_WAKE_ERR_CNT)
BIT
NAME
TYPE
DEFAULT
FUNCTION
EEE Wake Error Counter:
This register counts the wake time faults where the PHY fails to
complete its normal wake sequence within the time required for the
specific PHY type.
15:0
EEE Wake Error Counter
RO, LH
0
This counter is cleared after a read and holds at all ones in the case
of overflow. PCS Reset also clears this register.
表8-154. 0x703C MMD7 Energy Efficient Ethernet Advertisement Register
(MMD7_EEE_ADVERTISEMENT)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:2
Reserved
RO
0
Reserved
Advertise 100Base-TX EEE:
1
0
Advertise 100Base-TX EEE
Reserved
RW,Strap
RO
1
0
1 = Energy Efficient Ethernet is advertised for 100Base-TX
0 = Energy Efficient Ethernet is not advertised
Reserved
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表8-155. 0x703D MMD7 Energy Efficient Ethernet Link Partner Ability Register (MMD7_EEE_LP_ABILITY)
BIT
NAME
TYPE
DEFAULT
FUNCTION
15:2
Reserved
RO
0
Reserved
Link Partner EEE Capability:
1
0
Link Partner EEE Capability
Reserved
RO
RO
0
0
1 = Link Partner is advertising EEE capability for 100Base-TX
0 = Link Partner is not advertising EEE capability for 100Base-TX
Reserved
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
9.1 Application Information
The DP83822 is a single-port 10/100 Mbps Ethernet PHY. It supports connections to an Ethernet MAC through
MII, RMII, or RGMII. Connections to the Ethernet media are made via the IEEE 802.3 defined Media Dependent
Interface.
When using the device for Ethernet applications, it is necessary to meet certain requirements for normal
operation. The following subsections are intended to assist in appropriate component selection and required
circuit connections.
9.2 Typical Applications
图9-1 shows a typical application for the DP83822. More typical application examples are given in this section.
100BASE-FX
MII
RMII
RGMII
DP83822
10/100 Mbps
Ethernet PHY
MAC
10BASE-Te
100BASE-TX
RJ-45
25-MHz / 50-MHz
Clock Source
Status
LEDs
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图9-1. Typical DP83822 Application
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9.2.1 TPI Network Circuit
图 9-2 shows the recommended twisted-pair interface network circuit for 10/100 Mbps. Variations with PCB and
component characteristics require that the application be tested to verify that the circuit meets the requirements
of the intended application.
Center tap of the transformer must be connected to analog supply rail (AVD) with decoupling capacitors close to
the transformer. All resistors and capacitors should be placed as close to the device as possible.
3.3-V
Supply
Pin 9
(RD-)
Ferrite bead for improved
EMC (optional)
3.3-V
Supply
49.9 Ω
49.9 Ω
1:1
RD -
1 ꢀF
0.1 ꢀF
Pin 10
(RD+)
RD +
1 ꢀF
0.1 ꢀF
Pin 11
(TD-)
TD -
3.3-V
Supply
49.9 Ω
49.9 Ω
TD +
1 ꢀF
0.1 ꢀF
1:1
1 ꢀF
0.1ꢀF
RJ 45
Pin 12
(TD+)
图9-2. TPI Network Circuit
9.2.1.1 Design Requirements
The design requirements for the DP83822 in TPI operation (100BASE-TX or 10BASE-Te) are:
1. AVD Suppy = 3.3 V or 1.8 V
2. Center Tap Supply = AVD Supply
3. VDDIO Supply = 3.3 V, 2.5 V, or 1.8 V
4. Reference Clock Input = 25-MHz or 50-MHz (RMII Slave)
9.2.1.2 Detailed Design Procedure
For the detailed design procedure of the TPI network circuit, see 节9.2.2.2.
9.2.1.3 Application Curves
For expected TPI network MDI curves, see 图7-18 and 图7-19 and 图7-21.
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9.2.2 Fiber Network Circuit
图 9-3 shows the recommended circuit for a 100-Mbps fiber network. Variations with PCB and component
characteristics require that the application be tested to verify that the circuit meets the requirements of the
intended application.
All resistors and capacitors should be placed as close to the fiber transceiver as possible.
3.3 V
49.9 Ω
49.9 Ω
49.9 Ω
49.9 Ω
Pin 12
(FX_TDP)
0.1 ꢀF
Pin 11
(FX_TDM)
0.1 ꢀF
DP83822
PHY
Pin 24
(SD_IN)
Fiber Transceiver
Pin 10
(FX_RDP)
0.1 ꢀF
Pin 9
(FX_RDM)
0.1 ꢀF
Place resistors and capacitors
close to the fiber transceiver
All values are typical and are 1%
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图9-3. Fiber Network Circuit
9.2.2.1 Design Requirements
9.2.2.1.1 Clock Requirements
The DP83822 supports an external CMOS-level oscillator source or an internal oscillator with an external crystal.
9.2.2.1.1.1 Oscillator
If an external clock source is used, XI should be tied to the clock source and XO should be left floating. The
amplitude of the oscillator should be a nominal voltage of VDDIO.
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备注
The DP83822 requires Clock to be present at PoR. In case clock is delayed, pull-down on XI is
recommended to avoid spurious signal latch-up.
9.2.2.1.1.2 Crystal
The use of a 25-MHz, parallel, 20-pF load crystal is recommended if operating with a crystal. A typical
connection diagram is shown below for a crystal resonator circuit. The load capacitor values will vary with the
crystal vendors; check with the vendor for the recommended loads.
XI
(pin 23)
XO
(pin 22)
R
1
C
L1
C
L2
图9-4. Crystal Oscillator Circuit
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表9-1. 25-MHz Oscillator Specification
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
ppm
Frequency
25
Frequency Tolerance
Including operational
-100
100
temperature, aging and other
factors
Rise / Fall Time
Jitter (Short Term)
Jitter (Long Term)
Symmetry
10% - 90%
8
100
1
nsec
psec
nsec
%
Cycle-to-cycle
Accumulative over 10 ms
Duty Cycle
50
15
40
60
30
Load Capacitance
pF
表9-2. 50-MHz Oscillator Specification
PARAMETER
Frequency
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
ppm
50
Frequency Tolerance
Including operational
-100
100
temperature, aging and other
factors
Rise / Fall Time
Jitter (Short Term)
Jitter (Long Term)
Symmetry
10% - 90%
8
nsec
psec
nsec
%
Cycle-to-cycle
Accumulative over 10 ms
Duty Cycle
50
15
1
60
30
40
Load Capacitance
pF
表9-3. 25-MHz Crystal Specification
PARAMETER
Frequency
TEST CONDITIONS
MIN
TYP
MAX
UNIT
25
MHz
Frequency Tolerance
Including operational
temperature, aging and other
factors
-100
100
40
ppm
pF
Load Capacitance
10
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9.2.2.2 Detailed Design Procedure
The Media Independent Interface (MII / RMII / RGMII) connects the DP83822 to the Media Access Controller
(MAC). The MAC may in-fact be a discrete device or integrated into a microprocessor, CPU, FPGA, or ASIC.
The Media Dependent Interface (MDI) connects the DP83822 to the transformer of the Ethernet network or to
AC isolation capacitors when interfacing with a fiber transceiver.
9.2.2.2.1 MII Layout Guidelines
1. MII signals are single-ended signals
2. Traces should be routed with 50-Ωimpedance to ground
3. Keep trace lengths as short as possible, less than two inches is recommended and less than six inches
maximum
9.2.2.2.2 RMII Layout Guidelines
1. RMII signals are single-ended signals
2. Traces should be routed with 50-Ωimpedance to ground
3. Keep trace lengths as short as possible, less than two inches is recommended and less than six inches
maximum
9.2.2.2.3 RGMII Layout Guidelines
1. RGMII signals are single-ended signals
2. Traces should be routed with 50-Ωimpedance to ground
3. Keep trace lengths as short as possible, less than two inches is recommended and less than six inches
maximum
4. Internal Clock Delay can be enabled on the transmit and receive path independently within the DP83822
using register access
9.2.2.2.4 MDI Layout Guidelines
1. MDI signals are differential
2. Traces should be routed with 50-Ωimpedance to ground and 100-Ωdifferential controlled impedance
3. Route MDI traces to the transformer on the same layer
4. Use a metal shielded RJ-45 connector and electrically connect the shield to chassis ground
5. Avoid supplies and ground beneath the magnetics
6. Do not overlap the circuit ground and chassis ground planes. Keep chassis ground and circuit ground
isolated by turning chassis ground into an isolated island by leaving a gap between the planes. Connecting a
1206 (size) capacitor between chassis ground and circuit ground is recommended to avoid floating metal.
Capacitors less than 805 (size) can create an arching path for ESD due to a small air-gap.
9.2.2.3 Application Curves
For expected Fiber network MDI curve, see 图7-20.
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10 Power Supply Recommendations
The DP83822 is capable of operating with a wide range of I/O supply voltages (3.3 V, 2.5 V, or 1.8 V) along with
any of the two analog supply options (3.3 V or 1.8 V).
The recommended power supply de-coupling network is shown below:
3.3-V, 2.5-V or
1.8-V Supply
VDDIO
(pin 21)
Ferrite bead for improved EMC
(optional)
10 nF
100 nF 1 ꢀF
10 ꢀF
Ferrite bead for improved EMC
(optional)
3.3-V or 1.8-V
Supply
AVD
(pin 14)
10 ꢀF 1 ꢀF
100 nF 10 nF
A. The smallest value is placed closest to the pin
图10-1. Power Connections
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Power Supply Characteristics
The following data was measured using a DP83822 evaluation module. All the power dissipation numbers are
measured at nominal voltage under typical temperature of 25°C. Center tap must be connected to the same
potential as the analog supply rail (AVD).
表10-1. Power Supply Characteristics(1)
MAGNETIC
SUPPLY
(mA)
AVD
SUPPLY
(mA)
VDDIO
SUPPLY POWER
(mA) (mW)
TOTAL
PARAMETER
TEST CONDITIONS
3.3-V AVD/CT AND 3.3-V VDDIO
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VDDIO TOTAL
表10-1. Power Supply Characteristics(1) (continued)
MAGNETIC
SUPPLY
(mA)
AVD
SUPPLY
(mA)
PARAMETER
TEST CONDITIONS
MII, Link-Up, No Traffic
SUPPLY POWER
(mA)
(mW)
22
22
36
36
15
241
MII, Link-Up, 960-ns IPG (100%
21
261
221
Utilization), 1514-byte Packets, 25oC
MII, Link-Up, 960-ns IPG (100%
22
22
25
52
20
22
Utilization), 1514-byte Packets, -40oC
MII, Link-Up, 960-ns IPG (100%
317
211
215
218
221
89
Utilization), 1514-byte Packets, 125oC
100BASE-TX
RMII, Link-Up, No Traffic
22
22
36
36
6
7
RMII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
RGMII, Link-Up, No Traffic
22
22
36
36
8
9
RGMII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
MII, Link-Up, No Traffic
2
18
18
7
7
MII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
49
244
86
RMII, Link-Up, No Traffic
2
18
18
6
6
10BASE-Te
RMII, Link-Up, 960ns IPG (100%
Utilization), 1514-byte Packets
49
241
89
RGMII, Link-Up, No Traffic
2
18
18
7
7
RGMII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
49
244
Passive Sleep
Active Sleep
RMII, bits[15:12] = 0b0111 in register
0x0011
2
2
16
16
6
6
79
RMII, bits[15:12] = 0b0110 in register
0x0011
79
40
36
83
IEEE Power Down
Deep Power Down
RMII, bits[11] = 1 in register 0x0000
2
2
4
3
6
6
RMII, bits[11] = 1 in register 0x0000 and
bit[2] = 1 in register 0x0428
Energy Efficient Ethernet
TX and RX LPI, RMII
2
17
6
3.3-V AVD/CT AND 1.8-V VDDIO
MII, Link-Up, No Traffic
22
22
36
36
10
12
209
213
197
199
200
200
73
MII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
RMII, Link-Up, No Traffic
22
22
36
36
3
4
100BASE-TX
RMII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
RGMII, Link-Up, No Traffic
22
22
36
36
5
5
RGMII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
MII, Link-Up, No Traffic
2
18
18
4
4
MII, Link-Up, 960ns IPG (100%
Utilization), 1514-byte Packets
49
228
71
RMII, Link-Up, No Traffic
2
18
18
3
3
10BASE-Te
RMII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
49
227
73
RGMII, Link-Up, No Traffic
2
18
18
4
4
RGMII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
49
228
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表10-1. Power Supply Characteristics(1) (continued)
MAGNETIC
SUPPLY
AVD
SUPPLY
(mA)
VDDIO
SUPPLY POWER
TOTAL
PARAMETER
TEST CONDITIONS
(mA)
(mA)
(mW)
Passive Sleep
Active Sleep
RMII, bits[15:12] = 0b0111 in register
0x0011
2
16
3
65
RMII, bits[15:12] = 0b0110 in register
0x0011
2
16
3
65
25
22
68
IEEE Power Down
Deep Power Down
RMII, bits[11] = 1 in register 0x0000
2
2
4
3
3
3
RMII, bits[11] = 1 in register 0x0000 and
bit[2] = 1 in register 0x0428
Energy Efficient Ethernet
TX and RX LPI, RMII
2
17
3
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VDDIO TOTAL
表10-1. Power Supply Characteristics(1) (continued)
MAGNETIC
SUPPLY
(mA)
AVD
SUPPLY
(mA)
PARAMETER
TEST CONDITIONS
SUPPLY POWER
(mA)
(mW)
1.8-V AVD/CT AND 3.3-V VDDIO
MII, Link-Up, No Traffic
22
22
36
36
15
21
154
174
124
128
131
134
56
MII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
RMII, Link-Up, No Traffic
22
22
36
36
6
7
100BASE-TX
RMII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
RGMII, Link-Up, No Traffic
22
22
36
36
8
9
RGMII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
MII, Link-Up, No Traffic
1
17
17
7
7
MII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
49
142
52
RMII, Link-Up, No Traffic
1
17
17
6
6
10BASE-Te
RMII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
49
139
56
RGMII, Link-Up, No Traffic
1
17
17
7
7
RGMII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
49
142
Passive Sleep
Active Sleep
RMII, bits[15:12] = 0b0111 in register
0x0011
1
1
16
16
6
6
50
RMII, bits[15:12] = 0b0110 in register
0x0011
50
29
27
52
IEEE Power Down
Deep Power Down
RMII, bits[11] = 1 in register 0x0000
1
1
4
3
6
6
RMII, bits[11] = 1 in register 0x0000 and
bit[2] = 1 in register 0x0428
Energy Efficient Ethernet
TX and RX LPI, RMII
1
17
6
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表10-1. Power Supply Characteristics(1) (continued)
MAGNETIC
SUPPLY
AVD
SUPPLY
(mA)
VDDIO
SUPPLY POWER
TOTAL
PARAMETER
TEST CONDITIONS
(mA)
(mA)
(mW)
1.8-V AVD/CT AND 1.8-V VDDIO
MII, Link-Up, No Traffic
22
22
36
36
10
12
122
126
110
112
113
113
40
MII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
RMII, Link-Up, No Traffic
22
22
36
36
3
4
100BASE-TX
RMII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
RGMII, Link-Up, No Traffic
22
22
36
36
5
5
RGMII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
MII, Link-Up, No Traffic
1
17
17
4
4
MII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
49
126
38
RMII, Link-Up, No Traffic
1
17
17
3
3
10BASE-Te
RMII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
49
124
40
RGMII, Link-Up, No Traffic
1
17
17
4
4
RGMII, Link-Up, 960-ns IPG (100%
Utilization), 1514-byte Packets
49
126
Passive Sleep
Active Sleep
RMII, bits[15:12] = 0b0111 in register
0x0011
1
1
16
16
3
3
36
RMII, bits[15:12] = 0b0110 in register
0x0011
36
14
13
38
IEEE Power Down
Deep Power Down
RMII, bits[11] = 1 in register 0x0000
1
1
4
3
3
3
RMII, bits[11] = 1 in register 0x0000 and
bit[2] = 1 in register 0x0428
Energy Efficient Ethernet
TX and RX LPI, RMII
1
17
3
(1) Ensured by production test, characterization, or design.
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11 Layout
11.1 Layout Guidelines
11.1.1 Signal Traces
PCB traces are lossy and long traces can degrade signal quality. Traces should be kept short as possible.
Unless mentioned otherwise, all signal traces should be 50-Ω single-ended impedance. Differential traces
should be 50-Ω single-ended and 100-Ω differential. Take care to ensure impedance is controlled throughout.
Impedance discontinuities will cause reflections leading to emissions and signal integrity issues. Stubs should be
avoided on all signal traces, especially differential signal pairs.
图11-1. Differential Signal Traces
Within the differential pairs, trace lengths should be run parallel to each other and matched in length. Matched
lengths minimize delay differences, avoiding an increase in common mode noise and emissions. Length
matching is also important for MAC interface connections. All transmit signal traces should be length matched to
each other and all receive signal traces should be length matched to each other.
Ideally, there should be no crossover or vias on signal path traces. Vias present impedance discontinuities and
should be minimized when possible. Route trace pairs on the same layer. Signals on different layers should not
cross each other without at least one return path plane between them. Differential pairs should always have a
constant coupling distance between them. For convenience and efficiency, TI recommends routing critical
signals first (that is, MDI differential pairs, reference clock, and MAC IF traces).
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11.1.2 Return Path
A general best practice is to have a solid return path beneath all signal traces. This return path can be a
continuous ground or DC power plane. Reducing the width of the return path can potentially affect the
impedance of the signal trace. This effect is more prominent when the width of the return path is comparable to
the width of the signal trace. Breaks in return path between the signal traces should be avoided at all cost. A
signal crossing a split plane may cause unpredictable return path currents and could impact signal quality and
result in emissions issues.
图11-2. Differential Signal Pair and Plane Crossing
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11.1.3 Transformer Layout
There must be no metal layer running beneath the transformer. Transformers can inject noise into metal beneath
them, which can affect the performance of the system. Because the DP83822 is a current mode line driver
design, the center tap pin on the device side of the transformer must be tied to the analog supply rail (AVD). De-
coupling capacitors must be placed near the center tap pin of the transformer as shown in 图9-2.
11.1.3.1 Transformer Recommendations
The following magnetics have been tested with the DP83822 using the DP83822EVM.
表11-1. Recommended Transformers
MANUFACTURER
PART NUMBER
HX1198FNL
HX1188NL
HX1188FNL
H2019NL
Pulse Electronics
H1102NL
Abracon
Bel Fuse
Sumida
ALAN101
S5585999J1F
CLP0612
7490120110
733330
Wurth Electronics
7490100111a
表11-2. Transformer Electrical Specifications
PARAMETER
Turn Ratio
TEST CONDITIONS
TYP
1:1
UNIT
-
±2%
1 - 100 MHz
1 - 30 MHz
30 - 60 MHz
60 - 80 MHz
1 - 50 MHz
50 - 150 MHz
30 MHz
dB
dB
dB
dB
dB
dB
dB
dB
Vrms
Insertion Loss
–1
–16
–12
–10
–30
–20
–35
–30
1500
Return Loss
Differential to Common Rejection Ratio
Crosstalk
Isolation
60 MHz
HPOT
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11.1.4 Metal Pour
All metal pours that are not signals or power must be tied to ground. There must be no floating metal in the
system, and there must be no metal between differential traces.
11.1.5 PCB Layer Stacking
To meet signal integrity and performance requirements, a minimum four-layer PCB is recommended. However, a
six-layer PCB should be used when possible.
图11-3. Recommended Layer Stack-Up
11.2 Layout Example
See the DP83822EVM for more information regarding layout.
Transformer
Plane
PHY
Component
(if not
integrated
in RJ-45)
RJ-45
Connector
Termination
components
Coupling
Components
Chassis
Ground Plane
System Power/Ground Planes
图11-4. Layout Example
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
表12-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
DP83822HF
DP83822IF
DP83822H
DP83822I
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
备注
These devices can not be differntiated by register reads. These devices are distinguished by
production tests of the corresponding functionalities.
12.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
ProfiNET® is a registered trademark of PROFIBUS and PROFINET International (PI)..
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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13.1 Package Option Addendum
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13.1.1 Packaging Information
Status Package Package
Package Eco Plan
Qty
Lead/Ball
Finish
Op Temp
(°C)
Orderable Device
Pins
32
32
32
32
32
32
32
32
MSL Peak Temp (3)
Device Marking(4) (5)
(1)
(2)
Type
Drawing
RoHS &
3000
DP83822HFRHBR ACTIVE
DP83822HFRHBT ACTIVE
VQFN
RHB
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR -40 to 125
Level-2-260C-1 YEAR -40 to 125
Level-2-260C-1 YEAR -40 to 125
Level-2-260C-1 YEAR -40 to 125
822HF
822HF
822H
822H
822IF
822IF
822I
Green
RoHS &
250
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHB
RHB
RHB
RHB
RHB
RHB
RHB
Green
RoHS &
3000
DP83822HRHBR
DP83822HRHBT
ACTIVE
ACTIVE
Green
RoHS &
250
Green
RoHS &
3000
DP83822IFRHBR ACTIVE
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Green
RoHS &
250
DP83822IFRHBT
DP83822IRHBR
DP83822IRHBT
ACTIVE
ACTIVE
ACTIVE
Green
RoHS &
3000
Green
RoHS &
250
822I
Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using
this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please
check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS
requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where
designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the
die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free
(RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb)
based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
space
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
space
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(5) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will
appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device
Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI
bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and
accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers
consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to
Customer on an annual basis.
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13.1.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
DP83822HFRHBR
DP83822HFRHBT
DP83822HRHBR
DP83822HRHBT
DP83822IFRHBR
DP83822IFRHBT
DP83822IRHBR
DP83822IRHBT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHB
RHB
RHB
RHB
RHB
RHB
RHB
RHB
32
32
32
32
32
32
32
32
3000
250
330.0
178.0
330.0
178.0
330.0
178.0
330.0
178.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
SPQ
3000
250
Length (mm) Width (mm)
Height (mm)
35.0
DP83822HFRHBR
DP83822HFRHBT
DP83822HRHBR
DP83822HRHBT
DP83822IFRHBR
DP83822IFRHBT
DP83822IRHBR
DP83822IRHBT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHB
RHB
RHB
RHB
RHB
RHB
RHB
RHB
32
32
32
32
32
32
32
32
367.0
210.0
367.0
213.0
367.0
213.0
367.0
213.0
367.0
185.0
367.0
191.0
367.0
191.0
367.0
191.0
35.0
3000
250
35.0
55.0
3000
250
35.0
55.0
3000
250
35.0
55.0
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重要声明和免责声明
TI 提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证没
有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
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证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更,恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务,TI 对此概不负责。
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提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021,德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
29-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DP83822HFRHBR
DP83822HFRHBT
DP83822HRHBR
DP83822HRHBT
DP83822IFRHBR
DP83822IFRHBT
DP83822IRHBR
DP83822IRHBT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHB
RHB
RHB
RHB
RHB
RHB
RHB
RHB
32
32
32
32
32
32
32
32
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
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Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 85
-40 to 85
-40 to 85
-40 to 85
822HF
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Call TI | NIPDAU
Call TI | NIPDAU
Call TI | NIPDAU
Call TI | NIPDAU
Call TI | NIPDAU
Call TI | NIPDAU
822HF
822H
822H
822IF
822IF
822I
822I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Mar-2022
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
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