DP83826E_技术文档

DP83826E, DP83826I

ZHCSKM7F –DECEMBER 2019 –REVISED NOVEMBER 2022

DP83826 确定性、低延迟、低功耗、10/100Mbps 工业以太网PHY

• 符合IEEE 802.3 标准：10BASE-Te、100BASE-

1 特性

TX

• 符合EtherCAT^®标准

• 较低的确定性延迟

– TX 延迟：40ns、RX 延迟：170ns

– 电源循环上的确定性延迟< ±2ns

– 固定相位XI 到TX_CLK 关系< ±2ns

• 强大的小型系统解决方案

– 用于增强EMC 的集成电路

– IEC 61000-4-2 ESD：±8kV 接触，±15kV 空气

– IEC 61000-4-4 EFT：5kHz、100kHz 下为±4kV

– CISPR 22 传导发射B 类

– 符合CISPR 22 B 类辐射发射限制

– 快速链路丢弃< 10µs

2 应用

• 工厂自动化、机器人和运动控制

• 电机驱动器

• 电网基础设施

• 楼宇自动化

• 工业以太网现场总线

3 说明

DP83826 能够提供很低的确定性延迟和低功耗，并支

持 10BASE-Te、100BASE-TX 以太网协议，可以满足

实时工业以太网系统中的严格要求。该器件包含可实现

快速链接的硬件自举、快速链路丢弃检测模式以及用于

对系统上的其他模块进行时钟同步的专用参考

CLKOUT。

– 电缆长度> 150 米

– 电压模式线路驱动器

– MAC 接口上的集成终端

– 电压容限：±10%

• 单个器件中具有两种可选引脚模式

– 用于附加功能的ENHANCED 模式

– 用于通用以太网引脚的BASIC 模式

• 低功耗< 160mW

• MAC 接口：MII、RMII

• 可编程节能模式

两种可配置模式为：使用通用以太网引脚排列的

BASIC 标准以太网模式，以及支持标准以太网模式和

多个工业以太网现场总线应用（通过附加功能和硬件自

举配置）的ENHANCED 以太网模式。

器件系列信息

– 主动睡眠

– 深度断电

封装尺寸

（NOM）

器件型号⁽¹⁾

封装

属性

5.00mm ×

5.00mm

– 节能以太网(EEE) IEEE 802.3az

– 局域网唤醒(WoL)

• 诊断工具：电缆诊断、内置自检(BIST)、环回模式

• 3.3V 单电源

• I/O 电压：1.8V 或3.3V

• RMII 背对背中继器模式

超低延迟、通用引

脚

DP83826E/I

DP83825I

VQFN (32)

WQFN (24)

3.00mm ×

3.00mm

小尺寸、经优化的

解决方案成本

5.00mm ×

5.00mm

宽温度范围、光纤

和RGMII 支持

DP83822HF/IF/H/I VQFN (32)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• DP83826E 工作温度范围：–40°C 至105°C

• DP83826I 工作温度范围：–40°C 至85°C

25 MHz XTAL/Ref Clock 25/50 MHz

VDDIO: 3.3 V or 1.8 V

VDDA3V3: 3.3 V

Media Types

100BASE-TX

10BASE-Te

Ref Clock: 25/50/125 MHz

Interrupt

Media Dependent

Interface (MDI)

DP83826

RJ-45

MII, RMII (master/slave)

SMI: MDC, MDIO

简化版应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNLS647

DP83826E, DP83826I

ZHCSKM7F –DECEMBER 2019 –REVISED NOVEMBER 2022

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Table of Contents

9.2 Functional Block Diagram.........................................26

9.3 Feature Description...................................................26

9.4 Programming............................................................ 47

9.5 Register Maps...........................................................51

10 Application and Implementation..............................135

10.1 Application Information......................................... 135

10.2 Typical Applications.............................................. 135

11 Power Supply Recommendations............................140

12 Layout.........................................................................141

12.1 Layout Guidelines................................................. 141

13 Device and Documentation Support........................144

13.1 Related Documentation........................................ 144

13.2 Receiving Notification of Documentation Updates144

13.3 Support Resources............................................... 144

13.4 Trademarks...........................................................144

13.5 Electrostatic Discharge Caution............................144

13.6 术语表................................................................... 144

14 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Mode Comparison Tables...............................................4

6 Pin Configuration and Functions (ENHANCED

Mode)............................................................................... 5

7 Pin Configuration and Functions (BASIC Mode)..........8

8 Specifications................................................................ 11

8.1 绝对最大额定值.........................................................11

8.2 ESD 等级...................................................................11

8.3 建议运行条件............................................................ 12

8.4 热性能信息................................................................12

8.5 电气特性....................................................................13

8.6 时序要求....................................................................16

8.7 Timing Diagrams.......................................................19

8.8 Typical Characteristics..............................................24

9 Detailed Description......................................................25

9.1 Overview...................................................................25

Information.................................................................. 145

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision E (February 2022) to Revision F (November 2022)

Page

• Corrected Reset states for RX_D3, LED0.......................................................................................................... 8

• 更新了热指标.................................................................................................................................................... 12

• Adjusted Power-Up Timing (Power Sequencing) graphic ................................................................................19

• Adjusted RMII Repeater Mode: Master-Slave and RMII Repeater Mode: Slave-Slave graphics .................... 30

• Clarified MDIO pullup resistor values............................................................................................................... 35

• Changed Rlo strap for internal PU pin to 1.5kΩ. Added recommended tolerance for resistor values.............47

• Added Enhanced Bootstrap Flowchart graphic................................................................................................ 49

• Corrected Strap0 default and functionality in Enhanced Mode.........................................................................49

• Updated device registers..................................................................................................................................51

• Adjusted location of Transformer Recommendations .................................................................................... 136

Changes from Revision D (October 2020) to Revision E (February 2022)

Page

• Pin 31 default is changed to LED1, added odd nibble detection and FLD detection mechanisms in hardware

bootstrap differences table..................................................................................................................................4

• Added TX_ER to pin 28......................................................................................................................................5

• Pin 31 default is changed to LED1..................................................................................................................... 8

• Pin 31 default is changed to LED1, updated pin 16 and pin 31 to PU................................................................8

• Added fast link drop modes table, updated description for fast link drop functionality in Included specification

for the different defaults between enhanced and basic mode, added strap8 description.................................45

• Added description that LED1/0 are autopolarity (enhanced), active low by default (basic)..............................46

• Added odd nibble detection table, added strap7 and strap1 interaction to MII MAC mode strap table, added

signal energy alternate function to strap8.........................................................................................................49

• Pin 31 default is changed to LED1, pin 16 default changed to half duplex.......................................................51

• TPI network cap updates................................................................................................................................136

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Changes from Revision C (July 2020) to Revision D (October 2020)

Page

• Updated Electrical Characteristics table........................................................................................................... 11

• Added section.................................................................................................................................................137

Changes from Revision B (March 2020) to Revision C (July 2020)

Page

• Added link to SNLA338 application note............................................................................................................ 4

• Added link to SNLA338.....................................................................................................................................25

• Energy Efficient Ethernet section......................................................................................................................27

• EEE Overview section...................................................................................................................................... 27

• EEE Negotiation section...................................................................................................................................27

• Added EEE for Legacy MACs Not Supporting 802.3az section....................................................................... 28

• Updated device registers..................................................................................................................................51

• Added link to SNLA338 application note........................................................................................................ 135

Changes from Revision A (February 2020) to Revision B (March 2020)

Page

• 还在“电气”部分中添加了DP83826I 温度范围................................................................................................ 1

• 向“器件系列信息”表添加了DP83826I............................................................................................................1

Changes from Revision * (January 2020) to Revision A (February 2020)

Page

• 添加了指向DP83826EVM 用户指南的链接........................................................................................................1

• Deleted pin 18 from 表5-2 .................................................................................................................................4

• Changed ENHANCED Mode pin map and pin functions table to match pin names...........................................5

• Changed BASIC Mode pin map and pin functions table to match pin names.................................................... 8

• Deleted "This pin can be configured to RX_DV in RMII mode to enable RMII Repeater Mode." from Pin

Functions (BASIC Mode)....................................................................................................................................8

• Added the 100BASE-TX Transmit Latency Timing graphic ............................................................................. 19

• Added the 100BASE-TX Receive Latency Timing graphic ..............................................................................19

• Added steps to disable CLKOUT via register configuration in 节9.3.8 ........................................................... 31

• Deleted mentions of "clause 45" from 节9.3.11 and 节9.3.11.1 .....................................................................35

• Deleted "Analog Loopback requires 100-Ω terminations across pins #1 and #2 as well as 100-Ω terminations

across pins #3 and #6 at the RJ45." from 节9.3.14.5 ..................................................................................... 43

• Added row for RMII slave mode configuration in 表9-15 ................................................................................ 51

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5 Mode Comparison Tables

The DP83826 can be strapped to operate in either ENHANCED mode or BASIC mode. ENHANCED mode

allows the DP83826 to support real-time Ethernet applications in addition to standard Ethernet applications.

BASIC mode allows the DP83826 to support standard Ethernet applications. Additionally, the DP83826 pinout in

BASIC mode matches a common PHY pinout used in many applications.

表5-1. Selecting EHANCED Mode or BASIC Mode

ENHANCED Mode

BASIC Mode

Connect ModeSelect (Pin 1) to VDDIO through pullup resistor

Short ModeSelect (Pin 1) to GND

表5-2. Pin Map Difference Between ENHANCED Mode and BASIC Mode

PIN NO.

31

ENHANCED MODE

CLKOUT/LED1

PWRDN/INT

BASIC MODE

LED1/TX_ER

INT

DESCRIPTION

Offers reference clockout 25 MHz at POR. Clock is not

interrupted by RST_N.

21

Offers power down as default pin function

表5-3. Hardware Bootstraps Difference Between ENHANCED Mode and BASIC Mode

HARDWARE BOOTSTRAPS

ENHANCED Mode⁽³⁾

BASIC Mode

Fast link-drop enable and disable⁽¹⁾

Yes

No

MLT3_error and Signal Energy

enabled by default

Fast link-drop detection mechanism

Strap controllable

Auto-MDIX enable and disable⁽¹⁾

Force MDI/MDIX selection⁽¹⁾

RMII back-to-back repeater mode configuration⁽²⁾

MII or RMII selection

Yes

No

Yes

No

Yes

No

Yes

Speed selection (10 M or 100 M)

MII isolate enable and disable

Auto-negotiation enable and disable

Number of PHY addresses available

Half or full duplex selection

No

Yes

No

Yes

8

No

Yes

No

CLKOUT in place of LED1

Odd Nibble Detection

Strap controllable

Disabled by default

(1) These pin bootstraps enable the ENHANCED mode DP83826 to meet the stringent requirements of real-time Ethernet applications.

(2) This pin bootstrap enables the ENHANCED mode DP83826 to function as an RMII repeater.

(3) ENHANCED mode includes all the modes of operation BASIC mode can be configured to. The difference is, in these modes of

operation, ENHANCED mode may require register configuration.

备注

For a step by step approach on using the DP83826 BASIC mode in existing systems that use a

common standard Ethernet pinout, please refer to SNLA338.

备注

For standardized list of Ethernet related acronyms, refer to Chinese and English Definitions of

Acronyms Related to Ethernet Products.

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6 Pin Configuration and Functions (ENHANCED Mode)

The ENHANCED mode is one of two modes that the DP83826 can be configured in at start-up. This mode

allows the DP83826 to support real-time Ethernet applications in addition to the standard Ethernet applications.

To configure the DP83826 to ENHANCED mode, leave ModeSelect (pin 1) unconnected or pull up with a resistor

to VDDIO.

32

31

30

29

28

27

26

25

ModeSelect

CEXT

1

2

3

4

5

6

7

8

24 TX_D0

23 TX_EN

VDDA3V3

RD_M

RD_P

22 TX_CLK/Strap5

21 PWRDN/INT

20 RX_ER/Strap6

19 RX_CLK/50MHz_RMII

18 RX_DV/CRS_DV/Strap10

17 VDDIO

TD_M

TD_P

Thermal Pad

(connect to GND)

XO

9

10

11

12

13

14

15

16

(not to scale)

图6-1. RHB Package

32-Pin QFN

(Top View)

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表6-1. Pin Functions (ENHANCED Mode)

TYPE ⁽¹⁾

DESCRIPTION

NAME

NO

This pin selects the DP83826 operating mode: BASIC mode or ENHANCED mode. For

ENHANCED mode, this pin shall be left NC or pulled-up with a resistor to VDDIO. For BASIC

mode, this pin shall be shorted to GND.

Reset: I, PU

Active: I, PU

ModeSelect

1

CEXT

2

3

A

External capacitor: Connect the CEXT pin through a 2-nF capacitor to GND.

Input analog supply: 3V3. For decoupling capacitor requirements, refer to Power Supply

Recommendations section of data sheet.

VDDA3V3

Power

RD_M

RD_P

TD_M

TD_P

4

5

6

7

A

Differential receive input (physical media dependent: PMD): These differential inputs are

automatically configured to accept either 10BASE-Te, 100BASE-TX specific signaling mode.

Differential transmit output (PMD): These differential outputs are configured to either

10BASE-Te or 100BASE-TX signaling mode based on configuration chosen for PHY.

Crystal output: Reference clock output. XO pin is used for crystal only. Leave this pin floating

when a CMOS-level oscillator is connected to XI.

XO

8

A

Crystal or oscillator input clock:

MII mode, RMII master mode: 25-MHz ±50 ppm-tolerance crystal or oscillator clock.

XI/50MHzIn

9

A

RMII slave mode: 50-MHz ±50 ppm-tolerance CMOS-level oscillator clock.

RBIAS

MDIO

10

11

RBIAS ( Bias resistor) value 6.49 kΩwith 1% precision connected to ground.

Management data I/O: Bi-directional management data signal that may be sourced by the

management station or the PHY. This pin has internal pullup resistor of 10 kΩ. An external

pullup resistor can be added if needed.

Reset: I, PU

Active: I/O, PU

Management data clock: Synchronous clock to the MDIO serial management input/output

data. This clock may be asynchronous to the MAC transmit and receive clocks. The

maximum clock rate is 25 MHz. There is no minimum clock rate.

Reset: I, PD

Active: I, PD

MDC

12

13

14

Reset: I, PD

Active: O

Strap7

RX_D3

Reset: I, PD

Active: O

Strap8

RX_D2

RX_D1

Receive data: Symbols received on the cable are decoded and presented on these pins

synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted.

A nibble RX_D[3:0] is received in MII mode. 2-bits RX_D[1:0] is received in RMII mode.

Reset: I, PD

Active: O

Strap9

15

Reset: I, PU

Active: O

Strap0

RX_D0

VDDIO

16

17

I/O supply voltage: 3.3 V/1.8 V. For decoupling capacitor requirements, refer to Power Supply

Decoupling Recommendations section of data sheet.

Power

Receive data valid: This pin indicates valid data is present on the RX_D[3:0] for MII mode and

on RX_D[1:0] in RMII mode. In MII mode, this pin acts as RX_DV. In RMII mode, this pin acts

as CRS_DV and combines the RMII Carrier and Receive Data Valid indications. This pin can

be configured to RX_DV in RMII mode to enable RMII Repeater Mode.

Reset: I, PD

Active: O

Strap10

RX_DV/

CRS_DV

18

19

MII receive clock: MII Receive Clock provides a 25-MHz reference clock for 100-Mbps speed

and a 2.5-MHz reference clock for 10-Mbps speed, which is derived from the received data

stream.

In RMII Master mode, this provides 50-MHz reference clock. In RMII Slave mode, this pin is

not used and remains Input, pulldown.

RX_CLK/

50MHz_RMII

Reset: I, PD

Active: O

Receive error: This pin indicates that an error symbol has been detected within a received

packet in both MII and RMII mode.

In MII mode, RX_ER is asserted high synchronously to the rising edge of RX_CLK.

In RMII mode, RX_ER is asserted high synchronously to the rising edge of the reference

clock. RX_ER is asserted high for every reception error, including errors during Idle.

This strap only latches on power-up and not on pin reset.

Reset: I, PD

Active: O

Strap6

RX_ER

20

6

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表6-1. Pin Functions (ENHANCED Mode) (continued)

TYPE ⁽¹⁾

DESCRIPTION

NAME

NO

Power down (default), interrupt: The default function of this pin is power down. Register

access is required to configure this pin as an interrupt. In power down function, an active low

signal on this pin places the device in power down mode. When this pin is configured as an

interrupt pin, this pin is asserted low when an interrupt condition occurs. The pin has an open-

drain output with a weak internal pullup resistor (9.5 kΩ). Some applications may require an

external PU resistor.

Reset: I, PU

Active: I, PU

PWRDN/INT

21

Reset: I, PD

Active: O

Strap5

MII transmit clock: MII transmit clock provides a 25-MHz reference clock for 100-Mbps speed

and a 2.5-MHz reference clock for 10-Mbps speed. Note that in MII mode, this clock has

constant phase referenced to the input clock. Unused in RMII Mode.

TX_CLK

TX_EN

22

23

Transmit enable: TX_EN is presented on the rising edge of the TX_CLK. TX_EN indicates the

presence of valid data inputs on TX_D[3:0] in MII mode and on TX_D[1:0] in RMII mode.

TX_EN is an active high signal.

Reset: I, PD

Active: I, PD

Reset: I, PD

Active: I, PD

TX_D0

TX_D1

TX_D2

TX_D3

24

25

26

27

Transmit data:

Reset: I, PD

Active: I, PD

In MII mode, the transmit data nibble received from the MAC is synchronous to the rising

edge of TX_CLK.

Reset: I, PD

Active: I, PD

In RMII mode, TX_D[1:0] received from the MAC is synchronous to the rising edge of the

reference clock.

Reset: I, PD

Active: I, PD

Collision Detect (default): In MII mode when the pin is acting as Collision Detect (COL), this

pin is always LOW in Full Duplex mode. In Half Duplex mode, COL is asserted HIGH only

when both transmit and receive media are non-idle. This pin can also be configured as a

second additional LED driver (LED2), the MII TX_ER signal or general purpose I/O (GPIO)

through register configurations.

Reset: I, PD

Active: O

Strap4

COL/LED2/

TX_ER GPIO

28

In RMII mode, this pin acts as LED2 by default.

Carrier sense (default):

In MII mode this pin is asserted high when the receive or transmit medium is non-idle. Carrier

Reset: I, PD

Active: O

Strap3

sense and receive data valid. This pin can be configured as third LED (LED3) through register

configuration.

CRS/LED3

LED0

29

30

In RMII mode, it is configured as LED3 by default.

LED0: This LED indicates transmit and receive activity in addition to the status of the Link.

The LED is ON when link is good. The LED blinks when the transmitter or receiver is active.

LED polarity is auto-detected (Active Low/ Active High) based on external pull-up or pull-down

on the pin.

Reset: I, PD

Active: O

Strap2

This pin provides 25-MHz reference clock from XI as default to clock. The output is not

affected by Resets allowing Application to reset PHY without impacting other system getting

impacted. The output clock switches off only by Deep Power Down.

Reset: I, PU

Active: O

Strap1

The pin can be configured to act as LED1 using strap or register configuration. The strap only

latches on power-up and not on pin reset. The LED is ON when link is 100 M. LED remains

OFF if Link is 10 M or no Link.

CLKOUT/

LED1

31

32

LED polarity is auto-detected (Active Low/ Active High) based on external pull-up or pull-down

on the pin.

Reset low: RST_N pin is an active low reset input. Asserting this pin low for at least 25 μs

forces a reset process to occur. Initiation of reset causes strap pins to be re-scanned and

resets all the internal registers of the PHY to default value.

Reset: I, PU

Active: I, PU

RST_N

(1) I = Input, O = Output, I/O = Input/Ouput, A = Analog, PU or PD = Internal pullup or pulldown: Hardware bootstrap configuration

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7 Pin Configuration and Functions (BASIC Mode)

The BASIC mode is one of two modes that the DP83826 can be configured in at start-up. This mode allows the

DP83826 to support all the standard Ethernet applications and matches a common pinout configuration used in

many of today's applications. To configure the DP83826 to BASIC mode, ModeSelect (pin 1) should be shorted

to GND.

32

31

30

29

28

27

26

25

ModeSelect

CEXT

1

2

3

4

5

6

7

8

24 TX_D0

23 TX_EN

VDDA3V3

RD_M

RD_P

22 TX_CLK/Strap5

21 INT

20 RX_ER/Strap6

19 RX_CLK/50MHz_RMII

18 RX_DV/CRS_DV/Strap10

17 VDDIO

TD_M

TD_P

Thermal Pad

(connect to GND)

XO

9

10

11

12

13

14

15

16

(not to scale)

图7-1. RHB Package

32-Pin QFN

(Top View)

表7-1. Pin Functions (BASIC Mode)

NO

TYPE ⁽¹⁾

DESCRIPTION

NAME

This pin selects the operating mode: BASIC mode or ENHANCED mode. This pin shall be

shorted to GND to configure DP83826 in BASIC mode. For ENHANCED mode, this pin shall

be left NC or pulled-up with a resistor to VDDIO.

Reset: I, PU

Active: I, PU

ModeSelect

1

CEXT

2

3

A

External capacitor: Connect the CEXT pin through a 2-nF capacitor to GND.

Input analog power supply pin: This pin shall be connected with 3.3 V. For decoupling

capacitor requirements, refer to section of datasheet.

VDDA3V3

Power

8

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表7-1. Pin Functions (BASIC Mode) (continued)

NAME

TYPE ⁽¹⁾

DESCRIPTION

NO

4

RD_M

A

Differential receive input (PMD): These differential inputs are automatically configured to

accept either 10BASE-Te or 100BASE-TX specific signaling mode.

RD_P

5

TD_M

6

Differential transmit output (PMD): These differential outputs are configured to either

10BASE-Te or 100BASE-TX signaling mode based on the configuration chosen for the PHY.

TD_P

7

Crystal output: reference clock output. XO pin is used for crystal only. Leave this pin floating

when a CMOS-level oscillator is connected to XI.

XO

8

A

Crystal or oscillator input clock:

MII mode or RMII master mode: 25-MHz ±50 ppm-tolerance crystal or oscillator clock.

XI/50MHzIn

9

A

RMII slave mode: 50-MHz ±50 ppm-tolerance CMOS-level oscillator clock.

RBIAS

MDIO

10

11

Bias resistance: R_BIASvalue 6.49 kΩ1% precision connected to ground.

Management data I/O: Bi-directional management data signal that may be sourced by the

management station or the PHY. This pin has internal pullup resistor of 10 kΩ. An external

pullup resistor can be added if needed.

Reset: I, PU

Active: I/O, PU

Management data clock: Synchronous clock to the MDIO serial management input/output

data. This clock may be asynchronous to the MAC transmit and receive clocks. The

maximum clock rate is 25 MHz. There is no minimum clock rate.

Reset: I, PD

Active: I, PD

MDC

12

13

14

15

Reset: I, PU

Active: O

Strap7

RX_D3

RX_D2

RX_D1

Reset: I, PD

Active: O

Strap8

Receive data: Symbols received on the cable are decoded and presented on these pins

synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted.

A nibble RX_D[3:0] is received in MII mode. 2-bits RX_D[1:0] is received in RMII mode.

Reset: I, PD

Active: O

Strap9

Reset: I, PU

Active: O

Strap0

RX_D0

VDDIO

16

17

18

I/O supply voltage: 3.3 V or 1.8 V. For decoupling capacitor requirements, refer to section of

datasheet.

Power

Reset: I, PD

Active: O

Strap10

Receive data valid: This pin indicates valid data is present on the RX_D[3:0] for MII mode and

on RX_D[1:0] in RMII mode. In MII mode, this pin acts as RX_DV. In RMII mode, this pin acts

as CRS_DV and combines the RMII carrier and receive data valid indications.

RX_DV/

CRS_DV

MII receive clock: MII receive clock provides a 25-MHz reference clock for 100-Mbps speed

and a 2.5-MHz reference clock for 10-Mbps speed, which is derived from the received data

stream.

In RMII master mode, this provides 50-MHz reference clock. In RMII slave mode, this pin is

not used and remains Input/PD.

RX_CLK/

50MHz_RMII

Reset: I, PD

Active: O

19

20

Receive Error: This pin indicates that an error symbol has been detected within a received

packet in both MII and RMII mode. In MII mode, RX_ER is asserted high synchronously to the

rising edge of RX_CLK. In RMII mode, RX_ER is asserted high synchronously to the rising

edge of the reference clock. RX_ER is asserted high for every reception error, including

errors during Idle.

Reset: I, PD

Active: O

Strap6

RX_ER

The strap only latches upon power-up and not on pin reset.

Interrupt: The default function of this pin is power down. Register access is required to

configure this pin as an interrupt. In power down function, an active low signal on this pin

places the device in power down mode. When this pin is configured as an interrupt pin, this

pin is asserted low when an interrupt condition occurs. The pin has an open-drain output with

a weak internal pullup resistor (9.5 kΩ). Some applications may require an external PU

resistor.

Reset: I, PU;

Active: I, PU

INT

21

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表7-1. Pin Functions (BASIC Mode) (continued)

TYPE ⁽¹⁾

DESCRIPTION

NAME

NO

MII transmit clock: MII Transmit Clock provides a 25-MHz reference clock for 100-Mbps

speed and a 2.5-MHz reference clock for 10-Mbps speed. Note that in MII mode, this clock

has constant phase referenced to the reference clock. Applications requiring such constant

phase may use this feature. Unused in RMII Mode.

Reset: I, PD

Active: O

Strap5

TX_CLK

22

Transmit enable: TX_EN is presented on the rising edge of the TX_CLK. TX_EN indicates the

presence of valid data inputs on TX_D[3:0] in MII mode and on TX_D[1:0] in RMII mode.

TX_EN is an active high signal.

Reset: I, PD

Active: I, PD

TX_EN

23

Reset: I, PD

Active: I, PD

TX_D0

TX_D1

TX_D2

TX_D3

24

25

26

27

Transmit data:

Reset: I, PD

Active: I, PD

In MII mode, the transmit data nibble received from the MAC is synchronous to the rising

edge of TX_CLK.

Reset: I, PD

Active: I, PD

In RMII mode, TX_D[1:0] received from the MAC is synchronous to the rising edge of the

reference clock.

Reset: I, PD

Active: I, PD

Collision detect:

Reset: I, PD

Active: O

Strap4

In MII mode: For Full-Duplex mode, this pin is always LOW. In Half Duplex mode, this pin is

COL

CRS

28

29

asserted HIGH only when both transmit and receive media are non-idle.

In RMII mode, this pin is not used.

Carrier sense:

Reset: I, PD

Active: O

In MII mode this pin is asserted high when the receive or transmit medium is non-idle.

Strap3

carrier sense or receive data valid. In RMII mode, this pin is not used.

LED0: This LED indicates transmit and receive activity in addition to the status of the Link.

The LED is ON when link is good. The LED blinks when the transmitter or receiver is active.

LED polarity is fixed Active Low. If an external pull-down is required for strapping purposes,

both the strap and LED series resistance will need adjustment for correct operation of both

the LED and the strap. Please see the LED section for further details.

Reset: I, PU

Active: O

Strap2

LED0

30

LED1: The pin acts as LED1 as default. The LED is ON when link is 100 M. LED remains

OFF if the Link is 10 M, or there is no Link. This pin can be configured to TX_ER through

register configuration.

LED polarity is fixed Active Low. If an external pull-down is required for strapping purposes,

both the strap and LED series resistance will need adjustment for correct operation of both

the LED and the strap. Please see the LED section for further details.

Reset: I, PU

Active: O

Strap1

LED1/TX_ER

RST_N

31

32

Reset low: RST_N pin is an active low reset input. Asserting this pin low for at least 25 μs

forces a reset process to occur. Initiation of reset causes strap pins to be re-scanned and

resets all the internal registers of the PHY to default value.

Reset: I, PU

Active: I, PU

(1) I = Input, O = Output, I/O = Input/Ouput, A = Analog, PU or PD = Internal pullup or pulldown: Hardware bootstrap configuration

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8 Specifications

8.1 绝对最大额定值

在自然通风条件下的工作温度范围内测得（除非另有说明）⁽¹⁾

参数

最小值

–0.3

-65

最大值

单位

VDDA3V3

4

V

模拟电源电压

VDDIO3V3

VDDIO1V8

Tstg

4

2.1

150

4

V

IO 电源电压

贮存温度

°C

V

-0.6

MDI 引脚

-0.3

4

V

MAC 接口引脚

MDIO、MDC 接口引脚

XI

-0.3

4

V

-0.3

4

V

-0.3

4

V

复位

(1) 超出“绝对最大额定值”下列出的压力可能会对器件造成永久损坏。这些仅仅是压力额定值，并不表示器件在这些条件下以及在“建议

运行条件”以外的任何其他条件下能够正常运行。长时间处于绝对最大额定条件下可能会影响器件的可靠性。

8.2 ESD 等级

参数

定义

值

单位

人体放电模型(HBM)，符合ANSI/ESDA/JEDEC JS-001(1) MDI

（媒体相关接口）引脚

+/- 5

kV

ESD (HBM)⁽¹⁾

人体放电模型(HBM)，符合ANSI/ESDA/JEDEC JS-001(1)，除

MDI 以外的所有引脚

+/- 2

±750

kV

V

充电器件模型(CDM)，符合JEDEC 规范JESD22-C101，所有

引脚

ESD (CDM)⁽²⁾

(1) JEDEC 文档JEP155 指出：500V HBM 可实现在标准ESD 控制流程下安全生产。如果具备必要的预防措施，则可以在低于500V HBM

时进行生产。列为±5kV 和/或±4kV 的引脚实际上可能具有较高的性能。

(2) JEDEC 文件JEP157 指出：250V CDM 可实现在标准ESD 控制流程下安全生产。若部署必要的预防措施，不足250V CDM 时也能进

行生产。列为±500 V 的引脚实际上可能具有更高的性能。

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8.3 建议运行条件

在自然通风条件下的工作温度范围内测得（除非另有说明）

参数

最小值

典型值

3.3

最大值

3.6

单位

V

VDDA3V3

VDDIO3V3

VDDIO1V8

3

模拟电源电压

3.3

3.6

V

IO 电源电压

1.62

1.8

1.98

V

自然通风工作温度

(DP83826E)

Ta

25

105

85

C

–40

自然通风工作温度

(DP83826I)

TX_EN、TX_D0、TX_D1、TX_D2、TX_D3、

TX_CLK、RX_D0、RX_D1、RX_D2、RX_D3、

RX_DV、RX_ER、MDIO、MDC、COL/LED2、

CRS、CLKOUT/LED1、INT/PWDN、RESET、

TX_ER

VDDIO：1.8v

1.62

1.8

1.98

V

1.62

1.8

1.98

V

XI 振荡器输入

LED0

TX_EN、TX_D0、TX_D1、TX_D2、TX_D3、

TX_CLK、RX_D0、RX_D1、RX_D2、RX_D3、

RX_DV、RX_ER、MDIO、MDC、COL/LED2、

CRS、CLKOUT/LED1、INT/PWDN、RESET、

TX_ER

VDDIO：3.3v

3.0

3.3

3.6

V

3.0

3.3

3.6

V

XI 振荡器输入

LED0

8.4 热性能信息

(1)

热指标

单位

R_θJA

52

°C/W

结至环境热阻

R_θJC(top)

R_θJC(bot)

R_θJB

42

°C/W

结至外壳（顶部）热阻

结至外壳（底部）热阻

结至电路板热阻

11.9

31.5

2.1

Y_JT

结至顶部特征参数

Y_JB

31.4

结至电路板特征参数

(1) 有关新旧热指标的更多信息，请参阅半导体和IC 封装热指标应用报告。

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8.5 电气特性

在VDDA3V3 = 3V3 的自然通风条件下的工作温度范围内（除非另有说明）⁽¹⁾

参数

IEEE Tx 一致性(100BaseTx)

差分输出电压

测试条件

最小值

典型值

最大值

单位

950

1050

mV

IEEE Tx 一致性(10BaseTe)

输出差分电压⁽²⁾

1.54

1.75

45

1.96

V

功耗基线（活动模式、50% 流量、数据包大小：1518、随机内容、150 米电缆）

I(VDDA3

MII (100BaseTx)

V3=3V3)

53

mA

MII (10BaseTe)

35

45

35

45

35

46

53

46

53

46

mA

RMII 主模式(100BaseTx)

RMII 主模式(10BaseTe)

RMII 从模式(100BaseTx)

RMII 从模式(10BaseTe)

I(VDDIO

MII (100BaseTx)

=3V3)

8

14

mA

MII (10BaseTe)

5

9

7

5

12

14

12

8.5

6

mA

RMII 主模式(100BaseTx)

RMII 主模式(10BaseTe)

RMII 从模式(100BaseTx)

RMII 从模式(10BaseTe)

I(VDDIO

MII (100BaseTx)

=1V8)

5

7

mA

MII (10BaseTe)

3

5

3

2

6

7

6

3

mA

RMII 主模式(100BaseTx)

RMII 主模式(10BaseTe)

RMII 从模式(100BaseTx)

RMII 从模式(10BaseTe)

功耗（工作模式最坏情况，100% 流量，数据包大小：1518、随机内容、150 米电缆）

I(VDDA3

MII (100BaseTx)

V3=3V3)

44

55

mA

MII (10BaseTe)

35

44

35

44

35

48

55

48

55

48

mA

RMII 主模式(100BaseTx)

RMII 主模式(10BaseTe)

RMII 从模式(100BaseTx)

RMII 从模式(10BaseTe)

I(VDDIO

MII (100BaseTx)

=3V3)

10

15

mA

MII (10BaseTe)

5

11

9

12

15

12

10

mA

RMII 主模式(100BaseTx)

RMII 主模式(10BaseTe)

RMII 从模式(100BaseTx)

RMII 从模式(10BaseTe)

8

5

I(VDDIO

MII (100BaseTx)

=1V8)

6

2

9

6

mA

MII (10BaseTe)

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8.5 电气特性(continued)

在VDDA3V3 = 3V3 的自然通风条件下的工作温度范围内（除非另有说明）⁽¹⁾

参数

测试条件

最小值

典型值

最大值

单位

6

9

7

8

6

mA

RMII 主模式(100BaseTx)

RMII 主模式(10BaseTe)

RMII 从模式(100BaseTx)

RMII 从模式(10BaseTe)

5

4

2

mA

功耗（低功耗模式）

I(AVDD3

V3=3V3)

开启LPI 时EEE 模式下的100 BaseTx 链

路

15

mA

100 BaseTx EEE 模式

11

18

mA

IEEE 断电

主动睡眠

复位

12.5

I(VDDIO

=3V3)

开启LPI 时EEE 模式下的100 BaseTx 链

路

6

mA

100 BaseTx EEE 模式

IEEE 断电

I(VDDIO

=3V3)

10.5

I(VDDIO

=3V3)

主动睡眠

I(VDDIO

=3V3)

复位

I(VDDIO

=1V8)

开启LPI 时EEE 模式下的100 BaseTx 链

路

4

100 BaseTx EEE 模式

IEEE 断电

I(VDDIO

=1V8)

5.5

I(VDDIO

=1V8)

主动睡眠

I(VDDIO

=1V8)

复位

自举直流特性（2 级）

V_{IH_3v3}

1.3

V

高电平自举阈值：3V3

低电平自举阈值：3V3

高电平自举阈值：1V8

低电平自举阈值：1V8

V_{IL_3v3}

0.6

V_{IH_1v8}

V_{IL_1v8}

0.6

30

晶体振荡器

15

pF

负载电容

IO

VDDIO = 3.3V ±10%

1.7

2.4

V

高电平输入电压

低电平输入电压

高电平输出电压

低电平输出电压

VDDIO = 3.3V ±10%

0.8

3V3

I_OH=-2mA、VDDIO = 3.3V ±10%

I_OL= 2mA、VDDIO = 3.3V ±10%

0.65 x

VDDIO

VDDIO = 1.8V ±10%

V

高电平输入电压

低电平输入电压

高电平输出电压

0.35 x

VDDIO

VDDIO = 1.8V ±10%

1V8

VDDIO -

0.45

I_OH=-2mA、VDDIO = 1.8V ±10%

0.45

15

V

I_OL= 2mA、VDDIO = 1.8V ±10%

T_A= -40℃至85℃，VIN=VDDIO

T_A= -40℃至105℃，VIN=VDDIO

低电平输出电压

Iih (VIN=VCC)

uA

25

14

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8.5 电气特性(continued)

在VDDA3V3 = 3V3 的自然通风条件下的工作温度范围内（除非另有说明）⁽¹⁾

参数

测试条件

最小值

典型值

最大值

单位

Iil (VIN=GND)

15

uA

T_A= -40℃至85℃，VIN=GND

T_A= -40℃至105℃，VIN=GND

三态输出高电流（-40C 至85C）

三态输出高电流（-40C 至105C）

三态输出低电流（-40 至85C）

三态输出低电流（-40 至105C）

Iil (VIN=GND)

25

15

uA

kΩ

pF

V

Iozh

Iozl

-15

-25

-15

-25

7.5

25

15

Iozl

25

10

1

12.5

R 下拉

内部下拉电阻

R 上拉

内部上拉电阻器

C_IN

输入电容XI

输入电容输入引脚

输出电容XO

C_IN

5

C_OUT

1

输入电容输入引脚

5

输出电容XO

输出电容输出引脚

0.9

1.65

XI 输入osc 时钟共模VDDIO 1V8

XI 输入osc 时钟共模VDDIO 3V3

V

RX_D[3:0]、RX_ER、RX_DV、

RX_CLK、TX_CLK

R_series

50

集成MAC 串联终端电阻器

Ω

(1) 由生产测试、特性或设计确保

(2) 要求寄存器0x030E 编程到0x4A40

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8.6 时序要求

(1)

参数

最小值

标称值

最大值

单位

上电时序

T1

0.5

0

50

200

50

ms

V

电压斜坡持续时间（0% 至100% VDDIO）

T2，⁽²⁾

T3

电源时序控制VDDA3V3，后跟VDDIO 或VDDIO，后跟VDDA3V3⁽⁵⁾

电压斜坡持续时间（VDDA3V3 的0% 至100%）

POR 释放时间/加电至SMI 就绪：用于寄存器访问的前导码前上电稳定时间

加电至FLP

0.5

T4

50

T5

1500

0.3

2

VDDA3V3 上的基座电压，电源斜升前的VDDIO

复位时序

T1

25

us

ms

复位脉冲宽度：能够复位的最小复位脉冲宽度（无消抖电容）

重置为SMI 就绪：用于寄存器访问的前导码前复位后稳定时间

到FLP 的复位

T2

T3

1500

0.5

重置为100M 信令（捆绑模式）

0.2

重置为RMII 主时钟

快速链路脉冲时序

T1

111

125

62.5

104

16

139

μs

ns

时钟脉冲到时钟脉冲周期

T2

T3

T4

T5

55.5

69.5

时钟脉冲到数据脉冲周期

时钟/数据脉冲宽度

FLP 突发到FLP 突发周期

FLP 突发宽度

8

24

33

ms

2

17

突发宽度脉冲

链路接通时序

使用搭接启用快速链路丢弃，150 米电缆

10

11

us

使用模式1 的快速链路丢弃时间（信号/能量损失指示）

使用模式2 的快速链路丢弃时间（低SNR 阈值）

使用模式3 的快速链路丢弃时间（MLT3 错误计数）⁽⁴⁾

使用模式4 的快速链路丢弃时间（RX 错误计数）

使用模式5 的快速链路丢弃时间（解扰器链路丢弃）⁽⁴⁾

100M EEE 时序

210

20

us

ms

us

睡眠时间

静态时间

36

唤醒时间(Tw_sys_tx)

刷新时间

200

µs

100M MII 接收时序

T1

T2

16

10

20

24

30

ns

RX_CLK 高电平/低电平时间

RX_D[3:0]，从RX_CLK 上升的RX_ER、RX_DV 延迟

100M MII 传输时序

T1

T2

T3

16

10

0

24

ns

TX_CLK 高电平/低电平时间

TX_D[3:0]，TX_ER、TX_EN 设置为TX_CLK

TX_D[3:0]，来自TX_CLK 的TX_ER、TX_EN 保持

10M MII 接收时序

RX_CLK 高电平/低电平时间⁽³⁾

T1

T2

160

100

200

240

300

ns

RX_D[3:0]，从RX_CLK 上升的RX_ER、RX_DV 延迟⁽³⁾

16

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8.6 时序要求(continued)

(1)

参数

最小值

标称值

最大值

单位

10M MII 传输时序

T1

T2

T3

190

25

0

200

210

ns

TX_CLK 高电平/低电平时间

TX_D[3:0]，TX_ER、TX_EN 设置为TX_CLK

TX_D[3:0]，来自TX_CLK 的TX_ER、TX_EN 保持

100M RMII 主时序

RMII 主时钟周期

RMII 主时钟占空比

100M RMII 时序

20

ns

%

35

65

T2

4

2

4

ns

TX_D[1:0]，TX_ER、TX_EN 设置为参考时钟上升沿

来自参考时钟上升沿的TX_D[1:0]、TX_ER、TX_EN 保持

来自参考时钟上升的RX_D[1:0]、RX_ER、CRS_DV 延迟

T3

T4

14

13

SMI 时序

T1

0

10

ns

MDC 至MDIO（输出）延迟时间

MDIO（输入）至MDC 建立时间

MDIO（输入）至MDC 保持时间

MDC 频率

T2

T3

ns

T4

2.5

24

MHz

输出时钟时序（50M RMII 主时钟）

频率(PPM)

50

450

5

ppm

ps

抖动（长期500 周期）

上升/下降时间

ns

40

35

60

%

占空比

输出时钟时序（25M 时钟输出）

频率(PPM)

50

65

ppm

%

占空比

4000

5000

300

ps

上升时间

ps

下降时间

ps

抖动（长期：500 个周期）

抖动（短期）

250

ps

25

MHz

频率

25MHz 输入时钟容差

频率容差

-100

100

5

ppm

ns

上升/下降时间

50

ps

抖动容差(RMS)

1kHz 时的输入相位噪声

10kHz 时的输入相位噪声

100kHz 时的输入相位噪声

1MHz 时的输入相位噪声

10MHz 时的输入相位噪声

占空比

-98 dBc/Hz

-113 dBc/Hz

40

60

%

50MHz 输入时钟容差

频率容差

-100

100

5

ppm

ns

上升/下降时间

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8.6 时序要求(continued)

(1)

参数

抖动容差(RMS)

最小值

标称值

最大值

50

单位

ps

源自相位噪声的抖动容差长期抖动（100,000 个周期）

1kHz 时的输入相位噪声

10kHz 时的输入相位噪声

100kHz 时的输入相位噪声

1MHz 时的输入相位噪声

10MHz 时的输入相位噪声

占空比

-87 dBc/Hz

-107 dBc/Hz

40

60

%

延迟时序

MII 100M Tx（MII 到MDI）：上升沿TX_CLK 在MDI 上置位TX_EN 至

SSD 符号、启用FAST RX_DV、100 米电缆

38

40

170

540

96

ns

MII 100 Rx（MDI 到MII）：MDI 上的SSD 符号到RX_CLK 的上升沿、

RX_DV 置位、启用FAST RX_DV、100 米电缆

166

MII 10M Tx（MII 到MDI）：在MDI 上设置TX_EN 至SSD 符号的上升沿

TX_CLK

RMII 从器件100M Tx（RMII 到MDI）：从器件RMII 上升沿XI 时钟，在

MDI 上置位TX_EN 至SSD 符号，启用FAST RX_DV，100 米电缆

88

RMII 主器件100M Tx（RMII 到MDI）：主器件RMII 上升沿时钟，在MDI

上置位TX_EN 至SSD 符号，启用FAST RX_DV，100 米电缆

96

RMII 从站10M Tx（RMII 到MDI）：从器件RMII 上升沿XI 时钟在MDI 上

置位TX_EN 至SSD 符号

1360

1640

288

270

2152

RMII 主器件10M Tx（RMII 至MDI）主器件RMII 上升沿时钟，在MDI 上

置位TX_EN 至SSD 符号

MII 10M Rx（MDI 至MII）：MDI 上的SSD 符号到RX_CLK 的上升沿、

RX_DV 置位、启用FAST RX_DV、100 米电缆

RMII 从器件100M Rx（MDI 到RMII）：MDI 上的SSD 符号到XI 时钟的从

器件RMII 上升沿、CRS_DV 置位、启用FAST RX_DV、100 米电缆

268

252

RMII 主器件100M Rx（MDI 到RMII）：MDI 上的SSD 符号到主时钟的主

RMII 上升沿，CRS_DV 置位

RMII 从器件10M（MDI 到RMII）：MDI 上的SSD 符号到XI 时钟的从器件

RMII 上升沿，CRS_DV (10M) 置位

2110

RMII 主器件10M（MDI 至RMII）：MDI 上的SSD 符号到主时钟的主RMII

上升沿，CRS_DV 置位(10M)

2110

0

2152

4

ns

2

MII：XI 至TXCLK 相位差（跨复位、下电上电）

(1) 由设计、生产或特性测试确保

(2) 时钟应在电源的功率斜升开始时可用。如果时钟被延迟，在POR 完成后需要额外的RESET_N。可在100 微秒的时钟稳定和POR 完成

后启动复位

(3) 在接收数据的第一个半字节时，PHY 从本地时钟源切换到恢复时钟源。它会使RX_CLK 和RX_CLK 延伸至RX_DV 延迟

(4) MLT3 和解码器快速链路丢弃需要额外配置。请参阅特性部分

(5) VDDIO 或AVDD 电源都可以一起斜升，也可以将其中任何一个电源的斜升延迟至最大值）

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8.7 Timing Diagrams

T1

VDDIO

0.3V

0V

T3

T2

VDDA3V3

0.3V

0V

Clock in external clock mode shall be available at power ramp. If not

available, it is recommended to hold RESET_N low and release it at least 100

us aꢀer external clock is stable.

XI

Hardware

RESET_N

T4

MDC

FLP Burst

T5

图8-1. Power-Up Timing (Power Sequencing)

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VDDA3V3

XI

tT1

Hardware

RESET_N

32 Clocks

tT2

MDC

T3

FLP Burst

图8-2. Reset Timing (POR)

MDC

tT4t

tT1t

MDIO

(output)

MDC

tT2t

tT3t

MDIO

(input)

Valid Data

图8-3. Serial Management Timing

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tT1t

XI

Master Clock

tT2t

tT3t

TX_D[1:0]

TX_EN

Valid Data

图8-4. RMII Transmit Timing

tT1t

XI

RX_CLK

Master Clock

tT2t

RX_D[1:0]

CRS_DV

RX_DV

Valid Data

RX_ER

图8-5. RMII Receive Timing

tT1t

TX_CLK

tT2t

tT3t

TX_D [3:0]

TX_EN

Valid Data

图8-6. 100-M MII Transmit Timing

tT1t

RX_CLK

tT2t

RX_D [3:0]

RX_DV

RX_ER

Valid Data

图8-7. 100-M MII Receive Timing

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tT1t

TX_CLK

tT2t

tT3t

TX_D [3:0]

TX_EN

Valid Data

图8-8. 10-M MII Transmit Timing

tT1t

RX_CLK

tT2t

RX_D [3:0]

RX_DV

RX_ER

Valid Data

图8-9. 10-M MII Receive Timing

tT1t

tT2t

T3

Fast Link

Pulse(s)

Clock

Pulse

Data

Pulse

Clock

Pulse

Data

Pulse

tT4t

tT5t

FLP Bursts

FLP Burst

图8-10. Fast Link Pulse Timing

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TX_CLK

TX_EN

TX_D[3:0]

tT1t

PMD Output

Pair

IDLE

(J/K)

DATA

图8-11. 100BASE-TX Transmit Latency Timing

PMD Input Pair

IDLE

(J/K)

DATA

T2

RX_DV

RX_CLK

图8-12. 100BASE-TX Receive Latency Timing

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8.8 Typical Characteristics

图8-13. 100BASE-TX PMD Eye Waveform

图8-14. 10BASE-Te Link Pulse Waveform

图8-15. Auto-Negotiation Fast Link Pulses Waveform

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9 Detailed Description

9.1 Overview

The DP83826 is a single-port physical layer transceiver compliant to IEEE802.3 10BASE-Te and 100BASE-TX

standards. The DP83826 is designed to meet stringent Industrial fieldbus applications' needs and offers very low

latency, deterministic variation in latency (across reset, power cycle), fixed phase between XI and TX_CLK, low

power, and configuration using hardware bootstraps to achieve fast link up. The device supports the standard

MII and RMII (Master mode and Slave mode) for direct connection to the media access controller (MAC). Its

dedicated CLKOUT pin can be used to clock other modules on the system. In addition, the PWRDN pin controls

the DP83826 link up from power-on-reset (POR) and helps with design of asynchronous power-up of the

DP83826 and host system-on-a-chip (SoC) or field-programmable-gate-array (FPGA) controller.

The device operates from a single 3.3-V power supply and has an integrated LDO to provide voltage rails

needed for internal blocks. The device allows I/O voltage interfaces of 3.3 V or 1.8 V, which in turn enables the

DP83826 to operate as a single-supply PHY. Automatic supply configuration within the DP83826 allows for any

combination of VDDIO supply without the need for additional configuration settings.

The DP83826 uses mixed-signal processing to perform equalization, data recovery, and error correction to

achieve robust operation over a CAT5e twisted-pair cable length greater than 150 meters.

DP83826 offers two modes selectable during the power-up sequence using hardware bootstraps.

• BASIC mode

• ENHANCED mode

BASIC mode provides all the features required for standard Ethernet applications, using a common pinout

configuration used in many of today's applications. This makes it easy to evaluate and test the product on

existing platforms. The integrated MAC and MDI terminations streamline the design of boards when using the

DP83826. All the required clock outputs are generated from a single PLL with a 25-MHz external crystal or

oscillator input.

备注

For a step-by-step approach on using the DP83826 BASIC mode in existing systems that use a

common standard Ethernet pinout, please refer to SNLA338.

ENHANCED mode includes all the modes of operation described in BASIC Mode, however, the change in pins

enable additional features. This makes it easy to use the DP83826 in ENHANCED Mode for Ethernet fieldbus

applications in addition to the standard Ethernet applications. The feature includes:

• Dedicated Reference Clock Output: CLKOUT (pin 31) can be used to synchronize the whole system resulting

in lower latency (reduced FIFO on MAC). This clock is enabled at POR and remains available across the

reset. It also reduces the need for a dedicated clock for other PHYs and the host SoC/FPGA on the board.

• Dedicated HW Strap to use Force Mode, MDI or MDIX for fast link-up from POR and Reset.

• IEEE Power Down Pin: PWRDN (pin 21) helps asynchronous power-up of the DP83826 and host SoC/FPGA

control, and can still manage the DP83826 link-up through this dedicated pin.

• PHY address hardware bootstraps on non MAC interface pins to improve Signal Integrity on MII and RMII

MAC interface pins.

For pin maps of both modes, refer to section 节6and 节7.

To configure the hardware bootstraps for both modes, refer to sections 节9.4.1.1 and 节9.4.1.2.

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9.2 Functional Block Diagram

MII Option

Serial

Management

RMII Option

MII / RMII Interface

TX

RX

Data

TX_CLK

Data

RX_CLK

MII

Registers

10BASE-Te

And

10BASE-Te

And

100BASE-TX

Auto-Negotiation

Wake-on-LAN

Energy Efficient Ethernet

Clock

Generation

Transmit Block

Receive Block

DAC

ADC

BIST

LED

Driver

Cable Diagnostics

Auto-MDIX

Reference

Clock

TD

RD

LEDs

9.3 Feature Description

9.3.1 Auto-Negotiation (Speed/Duplex Selection)

Auto-Negotiation provides a mechanism for exchanging configuration information between the two ends of a link

segment. This mechanism is implemented by exchanging fast link pulses (FLP). FLPs are burst pulses that

provide the information used to communicate the abilities between two devices at each end of a link segment.

The DP83826 supports 100BASE-TX and 10BASE-Te modes of operation for auto-negotiation. Auto-negotiation

ensures that the highest common speed is selected based on the advertised abilities of the link partner and the

local device. Auto-negotiation can be enabled or disabled in hardware, using the bootstrap, or by register

configuration, using bit[12] in the BASIC mode Control Register (BMCR, address 0x0000). For further details

regarding auto-negotiation, refer to Clause 28 of the IEEE 802.3 specification.

9.3.2 Auto-MDIX Resolution

The DP83826 can determine if a “straight”or “crossover”cable is used to connect to the link partner. It can

automatically re-assign to Td (MDI) channel and Rd (MDIX) channel to establish link with the link partner. Auto-

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MDIX resolution precedes the actual Auto-Negotiation process that involves exchange of FLPs to advertise

capabilities. Automatic MDI/MDIX is described in IEEE 802.3 Clause 40, section 40.8.2. It is not a required

implementation for 10BASE-Te and 100BASE-TX. Auto-MDIX can also be used when operating the PHY in

Force Mode.

Auto-MDIX can be enabled or disabled in hardware, using the hardware bootstrap, or by register configuration,

using bit[15] of the PHY Control Register (PHYCR, address 0x0019). When Auto-MDIX is disabled, the PMA is

forced to either MDI (“straight”) or MDIX (“crossover”). Manual configuration of MDI or MDIX can also be

accomplished using register configuration, using bit[14] of the PHYCR or hardware bootstraps in ENHANCED

mode.

9.3.3 Energy Efficient Ethernet

9.3.3.1 EEE Overview

Energy Efficient Ethernet (EEE), defined by IEEE 802.3az, is a capability integrated into Layer 1 (Physical Layer)

and Layer 2 (Data Link Layer) to operate in Low Power Idle (LPI) mode. In LPI mode, power is saved during

periods of low packet utilization. EEE defines the protocol to enter and exit LPI mode without dropping the link or

corrupting packets.

The DP83826 EEE supports 100-Mbps and 10-Mbps speeds. It is supported for both MII and RMII MAC

interface. In 10BASE-Te operation, EEE operates with a reduced transmit amplitude that is fully interoperable

with a 10BASE-T PHY.

EEE must be enabled through register programming. The steps below describe how to configure the DP83826

for EEE through the MDC/MDIO interface.

Register Address

001F

Data

8000

0002

008B

4F12

0180

A681

0003

0800

8848

FE00

261D

1F30

2864

FFF2

FE36

0000

0800

3300

203C

04D1

04D3

04DF

033E

033F

0123

031B

0466

04CF

0416

04F5

04E0

031F

0308

04F4

0000

9.3.3.2 EEE Negotiation

EEE is advertised during auto-negotiation. Auto-Negotiation is performed at power up, on management

command, after link failure, or due to user intervention. EEE is supported if and only if both link partners

advertise EEE capabilities. If EEE is not supported, all EEE functions are disabled and the MAC should not

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assert LPI. To advertise EEE capabilities, the PHY needs to exchange an additional formatted next page and

unformatted next page in sequence.

EEE Negotiation can be activated using Register Access. IEEE 802.3az defines MMD3 and MMD7 as the

locations for EEE control and status registers. The MMD3 registers 0x1014, 0x1001, 0x1016, and MMD7

registers 0x203C and 0x203D contain all the required controls and status indications for operating EEE. The

Energy Efficient Ethernet Configuration Register #3 (EEECFG3, address 0x04D1) contains controls for EEE

configuration bypass.

By default, EEE capabilities are bypassed. To advertise EEE based on MMD3 and MMD7 registers, EEE

capabilities bypass needs to be disabled (0x04D1.0 = 1, 0x04D1.3 = 1) and EEE Advertisement shall be enabled

(MMD7 0x203C.1 = 1).

9.3.4 EEE for Legacy MACs Not Supporting 802.3az

The device can be configured to initiate LPI signaling (Idle and Refresh) through register programming as well.

This feature enables the system to perform EEE even when the MAC used is not supporting EEE. In this mode,

responsibility of enabling and disabling LPI signaling lies on the Host Controller Application. While the

*DP83826* is in LPI signaling mode, the application moves the DP83826 into active mode before sending any

data over the MAC interface.

The DP83826 does not have buffering capability to store the data while in LPI signaling mode. To enable EEE

through register configuration, the following registers must be configured:

1. Enable EEE capabilities by writing 0x04D1.0 = 1, 0x04D1.3 = 1

2. Advertise EEE capabilities during auto-negotiation by writing (MMD7 0x203C.1 = 1)

3. Renegotiate the link by writing 0x0000.9 = 1

4. Forced Tx LPI idles by writing 0x04D1.12 = 1

5. Write 0x04D1.12 = 0 to stop transmitting LPI Idles

9.3.5 Wake-on-LAN Packet Detection

Wake-on-LAN (WoL) provides a mechanism to detect specific frames and notify the connected controller through

either register status change, GPIO indication, or an interrupt flag. The WoL feature within the DP83826 device

allows for connected devices residing above the Physical Layer to remain in a low power state until frames with

the qualifying credentials are detected. This device supports WoL Magic Packet^™frame type. When a qualifying

WoL frame is received, the device WoL logic circuit generates a user-defined event (either pulses or level

change) through the GPIO pins or a status interrupt flag to inform a connected controller that a wake event has

occurred. The device includes a cycle redundancy check (CRC) gate to prevent invalid packets from triggering a

wake-up event. The Wake-on-LAN feature includes:

• Identification of WoL frames in all supported speeds (100BASE-TX and 10BASE-Te)

• Wake-up interrupt generation upon reception of a WoL frame

• CRC error checking of WoL frames to prevent interrupt generation from invalid frames

• Magic Packet technology with SecureOn password protection

9.3.5.1 Magic Packet Structure

When configured for Magic Packet detection, the DP83826 scans all incoming frames addressed to the node for

a specific data sequence. This sequence identifies the frame as a Magic Packet frame.

A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as SOURCE

ADDRESS, DESTINATION ADDRESS (which may be the receiving station’s IEEE address or a BROADCAST

ADDRESS), and CRC.

The specific Magic Packet sequence consists of 16 duplications of the MAC address of this node, with no breaks

or interruptions, followed by Secure-ON password if security is enabled. This sequence can be located anywhere

within the packet, but must be preceded by a synchronization stream. The synchronization stream is defined as

6 bytes of 0xFF.

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DEST (6 bytes)

SRC (6 bytes)

MISC (X bytes, X >= 0)

FF … FF (6 bytes)

DEST * 16

MAGIC Pattern

Secure-On Password (6 bytes)

MISC (Y bytes, Y >= 0)

CRC (4 bytes)

Only if Secure-On is Enabled

图9-1. Magic Packet Structure

9.3.5.2 Magic Packet Example

The following is an example Magic Packet for a Destination Address of 11h 22h 33h 44h 55h 66h and a

SecureOn password 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh:

DESTINATION SOURCE MISC FF FF FF FF FF FF

11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66

11 22 33 44 55 66 2A 2B 2C 2D 2E 2F MISC CRC

9.3.5.3 Wake-on-LAN Configuration and Status

Wake-on-LAN functionality is configured through the Receive Configuration Register (RXFCFG, address

0x04A0). Wake-on-LAN status is reported in the Receiver Status Register (RXFS, address 0x04A1). The Wake-

on-LAN interrupt flag configuration and status is located in the MII Interrupt Status Register #2 (MISR2, address

0x0013).

9.3.6 Low Power Modes

The DP83826 device supports three low power modes. This section discusses the principles behind these low

power modes and configuration to enable them.

9.3.6.1 Active Sleep

Active sleep mode reduces power consumption when no link partner is connected. The feature can be enabled

during initialization of the PHY by writing the correct bit to the PHYSCR register. The feature can be verified by

reading the BISCR register.

Once Active Sleep in enabled and when the PHY does not detect a cable connection, the PHY automatically

enters active sleep mode. When the device enters this mode, all internal circuitry shuts down except for the SMI

circuitry and energy detection circuitry on the TD± and RD± pins. In active sleep mode, the device transmits

normal link pulses (NLP) every 1.4 seconds to check for the presence of a link partner. When a link partner is

detected, the PHY automatically switches back to Normal mode, powering the rest of the internal circuitry.

The device enables active sleep mode by setting bits[14:12] = 0b110 in the PHY Specific Control Register

(PHYSCR, address 0x0011).

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9.3.6.2 IEEE Power-Down

IEEE power-down switch disables all PHY circuitry except the SMI and internal clock circuitry.

IEEE power-down switch can be activated by either register access or through the INTR/PWRDN pin when the

pin is configured for power-down function.

To enable IEEE power-down switch through the INTR/PWRDN pin, the pin must be driven LOW to ground.

To enable IEEE power-down switch through the SMI, set bit[11] = 1 in the BASIC mode Control Register (BMCR,

address 0x0000).

9.3.6.3 Deep Power Down State

A Deep Power Down state (DPD) disables all PHY circuitry except the SMI. In this mode, the device disables the

PHY PLL to further reduce power consumption.

The device uses this sequence to enter DPD state.

1. Enable DPD state (0x0428.2 = 1)

2. Enable IEEE power-down state (pin or 0x0000.11 = 1)

9.3.7 RMII Repeater Mode

The DP83826 device provides the option to enable RMII back-to-back repeater mode functionality to extend

cable reach. Two DP83826 devices can be connected in RMII repeater mode without need of any external

configuration. It provides a hardware strap to configure the CRS_DV pin of RMII interface to RX_DV pin for

back-to-back operation. 图 9-2 and 图 9-3 show the RMII pin connections that enables the device to operate in

repeater mode.

TX_D0

TX_D1

RX_D0

RX_D1

TX_D0

TX_D1

RX_D0

RX_D1

DP83826

(RMII Slave Mode)

DP83826

(RMII Master Mode)

RX_DV

TX_EN

RX_DV

50MHz_RMII

XI

XI 25 MHz

(XTAL/OsC)

图9-2. RMII Repeater Mode: Master-Slave

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TX_D0

TX_D1

RX_D0

RX_D1

TX_D0

TX_D1

RX_D0

RX_D1

DP83826

(RMII Slave Mode)

DP83826

(RMII Slave Mode)

RX_DV

TX_EN

RX_DV

TX_EN

XI

50 MHz

Oscillator

图9-3. RMII Repeater Mode: Slave-Slave

9.3.8 Clock Output

The device has several clock output configuration options. An external crystal or CMOS-level oscillator provides

the stimulus for the internal PHY reference clock. The local reference clock acts as the central source for all

clocking within the device.

Clock output options supported by the device include:

• MAC IF clock

• XI clock

• Free-running clock

• Recovered clock

MAC IF clock operates at the same rate as the MAC interface selected. For RMII operation, MAC IF Clock

frequency is 50 MHz.

XI clock is a pass-through option, which allows for the XI pin clock to be passed to a GPIO pin. Note that the

clock is buffered prior to transmission out of the GPIOs, and output clock amplitude is at the selected VDDIO

level. This clock is available on CLK_OUT/LED1 pin by default after POR release (Refer to T4 in Power-Up

Timing).

The Free-running clock is an internally generated 125-MHz free-running clock generated by the PLL. The free-

running clock is suitable for asynchronous data transmission applications.

The recovered clock is a 125-MHz recovered clock that is recovered from the connected link partner. The PHY

recovers the clock from the data received (transmitted from the link partner).

All clock configuration options are enabled using the LED GPIO configuration registers.

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CLKOUT can be disabled by configuring this pin as an input pin via register configuration. To do this set bit[0] = 1

in the PIN_CFG1 Register (Address = 0x459) and then set bit[0] = 1 in the PIN_CFG2 Register (Address =

0x45A).

9.3.9 Media Independent Interface (MII)

The media-independent interface (MII) is a synchronous 4-bit wide nibble data interface that connects the PHY

to the MAC. The MII is fully compliant with IEEE 802.3-2002 clause 22.

The MII signals are summarized below:

表9-1. MII Signals

FUNCTION

PINS

TX_D[3:0]

RX_D[3:0]

TX_EN

RX_DV

CRS

Data Signals

Transmit and Receive Signals

Line-Status Signals

Error Signals

COL

RX_ER

TX_CLK

TX_EN

TX_D[3:0]

RX_CLK

RX_DV

RX_ER

RX_D[3:0]

CRS

PHY

MAC

COL

图9-4. MII Signaling

Additionally, the MII interface includes the carrier sense signal (CRS), as well as a collision detect signal (COL).

The CRS signal asserts to indicate the reception or transmission of data. The COL signal asserts as an

indication of a collision which can occur during half-duplex mode when both transmit and receive operations

occur simultaneously.

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9.3.10 Reduced Media Independent Interface (RMII)

The DP83826 incorporates the reduced media-independent interface (RMII) as specified in the RMII

specification v1.2. The purpose of this interface is to provide a reduced pin count alternative to the IEEE 802.3

MII as specified in Clause 22. Architecturally, the RMII specification provides an additional reconciliation layer on

either side of the MII, but can be implemented in the absence of an MII. The DP83826 offers two types of RMII

operations: RMII Slave and RMII Master. In RMII Master operation, the DP83826 operates from either a 25-MHz

CMOS-level oscillator connected to XI pin, a 25-MHz crystal connected across XI and XO pins. A 50-MHz output

clock referenced from DP83826 can be connected to the MAC. In RMII Slave operation, the DP83826 operates

from a 50-MHz CMOS-level oscillator connected to the XI pin and shares the same clock as the MAC.

Alternatively, in RMII slave mode, the PHY can operate from a 50-MHz clock provided by the Host MAC

The RMII specification has the following characteristics:

• Supports 100BASE-TX and 10BASE-Te

• Single clock reference sourced from the MAC to PHY (or from an external source)

• Provides independent 2-bit wide transmit and receive data paths

• Uses CMOS signal levels, the same levels as the MII interface

In this mode, data transfers are 2 bits for every clock cycle using the internal 50-MHz reference clock for both

transmit and receive paths.

The RMII signals are summarized below:

表9-2. RMII Signals

FUNCTION

PINS

Receive data lines

TX_D[1:0]

RX_D[1:0]

TX_EN

Transmit data lines

Receive control signal

Transmit control signal

CRS_DV

TX_EN

TX_D[1:0]

PHY

RX_DV (optional)

RX_ER (optional)

RX_D[1:0]

MAC

CRS_DV

XI

50-MHz Reference

Clock

图9-5. RMII Slave Signaling

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TX_EN

TX_D[1:0]

PHY

RX_DV (optional)

RX_ER (optional)

RX_D[1:0]

MAC

CRS_DV

50-MHz Reference Clock

25-MHz Reference

Clock

图9-6. RMII Master Signaling

Data on TX_D[1:0] are latched at the PHY with reference to the 50 MHz-clock in RMII master mode and slave

mode. Data on RX_D[1:0] is provided in reference to 50-MHz clock.

In addition, CRX_DV can be configured as RX_DV signal. It allows a simpler method of recovering receive data

without the need to separate RX_DV from the CRS_DV indication.

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9.3.11 Serial Management Interface

The Serial Management Interface provides access to the DP83826 internal register space for status information

and configuration. The SMI is compatible with IEEE 802.3 clause 22. The implemented register set consists of

the registers required by the IEEE 802.3 plus several others to provide additional visibility and controllability of

the DP83826.

The SMI includes the management clock (MDC) and the management input/output data pin (MDIO). MDC is

sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of

24 MHz. MDC is not expected to be continuous, and can be turned off by the external management entity when

the bus is idle.

MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched on the

rising edge of the MDC. MDIO pin requires a pullup resistor (2.2 KΩ or 1.5 KΩ are widely used values), which

pulls MDIO high during IDLE and turnaround.

Up to 8 PHYs can share a common SMI bus. To distinguish between the PHYs, during power up or hardware

reset, the DP83826 latches the Phy_Address[2:0] configuration pins to determine its address.

The management entity must not start an SMI transaction in the first cycle after power up or hardware reset. To

maintain valid operation, the SMI bus must remain inactive at least until 50ms after power-up and at least until

2ms after reset is de-asserted (Refer to T4 in Power-up Timing and T2 in Reset Timing). In normal MDIO

transactions, the register address is taken directly from the management-frame reg_addr field, thus allowing

direct access to 32 16-bit registers (including those defined in IEEE 802.3 and vendor specific). The data field is

used for both reading and writing. The Start code is indicated by a <01> pattern. This pattern makes sure that

the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time inserted

between the Register Address field and the Data field. To avoid contention during a read transaction, no device

may actively drive the MDIO signal during the first bit of turnaround. The addressed DP83826 drives the MDIO

with a zero for the second bit of turnaround and follows this with the required data.

For write transactions, the station-management entity writes data to the addressed DP83826, thus eliminating

the requirement for MDIO Turnaround. The turnaround time is filled by the management entity by inserting <10>.

表9-3. SMI Protocol

SMI PROTOCOL

Read Operation

Write Operation

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9.3.11.1 Extended Register Space Access

The DP83826 SMI function supports read and write access to the extended register set using the Register

Control Register (REGCR, address 0x000D), the Data Register (ADDAR, address 0x000E), and the MDIO

Manageable Device (MMD) indirect method defined in IEEE 802.3ah draft for Clause 22 for accessing the

extended register set.

The standard register set, MDIO registers 0 to 31, is accessed using the normal direct-MDIO access or the

indirect method, except for register REGCR and register ADDAR, which are accessed only using the normal

MDIO transaction. The SMI function ignores indirect access to these registers.

REGCR is the MMD access control. In general, register REGCR[4:0] is the device address DEVAD that directs

any accesses of the ADDAR register to the appropriate MMD.

The DP83826 supports three MMD device addresses:

1. The Vendor-Specific device address DEVAD[4:0] = 11111 is used for general MMD register accesses.

2. DEVAD[4:0] = 00011 is used for Energy Efficient Ethernet MMD register accesses. Register names for

registers accessible at this device address are preceded by MMD3.

3. DEVAD[4:0] = 00111 is used for Energy Efficient Ethernet MMD registers accesses. Register names for

registers accessible at this device address are preceded by MMD7.

All accesses through register REGCR and ADDAR must use the correct DEVAD. Transactions with other

DEVAD are ignored. REGCR[15:14] holds the access function: address (00), data with no post increment (01).

• ADDAR is the address/data MMD register. ADDAR is used in conjunction with REGCR to provide the access

to the extended register set. If register REGCR[15:14] is (00), then ADDAR holds the address of the

extended address space register. Otherwise, ADDAR holds the data as indicated by the contents of its

address register. When REGCR[15:14] is set to (00), accesses to register ADDAR modify the extended

register set address register. This address register must always be initialized in order to access any of the

registers within the extended register set.

• When REGCR[15:14] is set to (01), accesses to register ADDAR access the register within the extended

register set selected by the value in the address register.

The following sections describe how to perform operations on the extended register set using register REGCR

and ADDAR. The descriptions use the device address for general MMD register accesses (DEVAD[4:0] = 11111).

For register accesses to the MMD3 or MMD7 registers the corresponding device address would be used.

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9.3.11.2 Write Address Operation

To set the address register:

1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.

2. Write the register address to register ADDAR.

Subsequent writes to register ADDAR (step 2) continue to write the address register.

9.3.11.3 Read Address Operation

To read the address register:

1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.

2. Read the register address from register ADDAR.

Subsequent reads to register ADDAR (step 2) continue to read the address register.

9.3.11.4 Write (No Post Increment) Operation

To write a register in the extended register set:

1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.

2. Write the desired register address to register ADDAR.

3. Write the value 0x401F (data, no post increment function field = 01, DEVAD = 31) to register REGCR.

4. Write the content of the desired extended register set to register ADDAR.

Subsequent writes to register ADDAR (step 4) continue to rewrite the register selected by the value in the

address register.

备注

Steps (1) and (2) can be skipped if the address register was previously configured.

9.3.11.5 Read (No Post Increment) Operation

To read a register in the extended register set:

1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.

2. Write the desired register address to register ADDAR.

3. Write the value 0x401F (data, no post increment function field = 01, DEVAD = 31) to register REGCR.

4. Read the content of the desired extended register set in register ADDAR.

Subsequent reads to register ADDAR (step 4) results in the output of the register set in step 3.

备注

Steps (1) and (2) can be skipped if the address register was previously configured.

9.3.11.6 Example Write Operation (No Post Increment)

This example demonstrates a write operation with no post increment. In this example, the MAC impedance is

adjusted to 99.25 Ωusing the IO MUX GPIO Control Register (IOCTRL, address 0x0461).

1. Write the value 0x001F to register 0x000D.

2. Write the value 0x0461 to register 0x000E (sets desired register to the IOCTRL).

3. Write the value 0x401F to register 0x000D.

4. Write the value 0x0400 to register 0x000E (sets MAC impedance to 99.25 Ω).

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9.3.12 100BASE-TX

9.3.12.1 100BASE-TX Transmitter

The 100BASE-TX transmitter consists of several functional blocks which convert synchronous 4-bit nibble data,

as provided by the MII, to a scrambled MLT-3 125-Mbps serial data stream on the MDI. 4B5B encoding and

decoding is detailed in 表9-4 below.

The transmitter section consists of the following functional blocks:

1. Code-Group Encoder and Injection Block

2. Scrambler Block with Bypass Option

3. NRZ to NRZI Encoder Block

4. Binary to MLT-3 Converter / Common Driver Block

The bypass option for the functional blocks within the 100BASE-TX transmitter provides flexibility for applications

where data conversion is not always required. The DP83826 implements the 100BASE-TX transmit state

machine diagram as specified in the IEEE 802.3 Standard, Clause 24.

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DATA CODES

表9-4. 4B5B Code-Group Encoding / Decoding

NAME

PCS 5B CODE-GROUP

MII 4B NIBBLE CODE

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

11110

01001

10100

10101

01010

01011

01110

01111

10010

10011

10110

10111

11010

11011

11100

11101

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

IDLE AND CONTROL CODES⁽¹⁾

H

00100

11111

11000

10001

01101

00111

00000

HALT code-group - Error code

Inter-Packet IDLE - 0000

First Start of Packet - 0101

Second Start of Packet - 0101

First End of Packet - 0000

Second End of Packet - 0000

EEE LPI - 0001⁽²⁾

I

J

K

T

R

P

INVALID CODES

V

00001

00010

00011

00101

00110

01000

01100

10000

11001

(1) Control code-groups I, J, K, T and R in data fields are mapped as invalid codes, together with RX_ER asserted.

(2) Energy Efficient Ethernet LPI must also have TX_ER / RX_ER asserted and TX_EN / RX_DV deasserted.

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9.3.12.1.1 Code-Group Encoding and Injection

The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for

transmission. This conversion is required to allow control data to be combined with packet data code-groups.

Refer to 表9-4 for 4B to 5B code-group mapping details.

The code-group encoder substitutes the first 8 bits of the MAC preamble with a J/K code-group pair (11000

10001) upon transmission. The code-group encoder continues to replace subsequent 4B preamble and data

nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the deassertion of transmit

enable (TX_EN) signal from the MAC, the code-group encoder injects the T/R code-group pair (01101 00111)

indicating the end of the frame.

After the T/R code-group pair, the code-group encoder continuously injects IDLEs into the transmit data stream

until the next transmit packet is detected (reassertion of transmit enable).

9.3.12.1.2 Scrambler

The scrambler is required to control the radiated emissions at the media connector and on the twisted-pair cable.

By scrambling the data, the total energy launched onto the cable is randomly distributed over a wide frequency

range. Without the scrambler, energy levels at the MDI and on the cable could peak beyond FCC limitations at

frequencies related to repeating 5B sequences (that is, continuous transmission of IDLEs).

The scrambler is configured as a closed loop linear feedback shift register (LFSR) with an 11-bit polynomial. The

output of the closed loop LFSR is X-ORd with the serial NRZ data from the code-group encoder. The result is a

scrambled data stream with sufficient randomization to decrease radiated emissions at certain frequencies by as

much as 20 dB.

9.3.12.1.3 NRZ to NRZI Encoder

After the transmit data stream has been serialized and scrambled, the data must be NRZI encoded in order to

comply with the TP-PMD standard for 100BASE-TX transmission over Category-5 unshielded twisted pair cable.

There is no ability to bypass this block within the DP83826. The NRZI data is sent to the 100-Mbps Driver.

9.3.12.1.4 Binary to MLT-3 Converter

The binary to MLT-3 conversion is accomplished by converting the serial binary data stream output from the

NRZI encoder into two binary data streams with alternately phased logic one events. These two binary streams

are then fed to the twisted pair output driver which converts the voltage to current and alternately drives either

side of the transmit transformer primary winding, resulting in a minimal current MLT-3 signal.

The 100BASE-TX MLT-3 signal sourced by the PMD output pair common driver is slew rate controlled. This

should be considered when selecting AC coupling magnetics to ensure TP-PMD standard compliant transition

times (3 ns < T_RISE(and T_FALL) < 5 ns).

9.3.12.2 100BASE-TX Receiver

The 100BASE-TX receiver consists of several functional blocks which convert the scrambled MLT-3 125-Mbps

serial data stream to synchronous to 4-bit data provided to the MII and 2-bit wide data to the RMII.

The receive section consists of the following functional blocks:

• Input and BLW compensation

• Signal detect

• Digital adaptive equalization

• MLT-3 to binary decoder

• Clock recovery module

• NRZI to NRZ decoder

• Descrambler

• Serial-to-parallel data conversion

• Code-group alignment

• 4B/5B decoder

• Link integrity monitor

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• Bad SSD detection

9.3.13 10BASE-Te

The 10BASE-Te transceiver module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision

detection, heartbeat, loopback, jabber, and link integrity functions, as defined in the standard.

备注

When using the DP83826 for 10BASE-Te applications, configure VOD_CFG3 (register address:

0x030E) to 0x4A40.

9.3.13.1 Squelch

Squelch is responsible for determining when valid data is present on the differential receive inputs. The squelch

circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10BASE-

Te standard) to determine the validity of data on the twisted-pair inputs.

The signal at the start of a packet is checked by the squelch, and any pulses not exceeding the squelch level

(either positive or negative, depending upon polarity) are rejected. When this first squelch level is exceeded

correctly, the opposite squelch level must then be exceeded no earlier than 50 ns. Finally, the signal must again

exceed the original squelch level no earlier than 50 ns to qualify as a valid input waveform, and not be rejected.

This checking procedure results in the typical loss of three preamble bits at the beginning of each packet. When

the transmitter is operating, five consecutive transitions are checked before indicating that valid data is present.

At this time, the squelch circuitry is reset.

DP83826 supports both IEEE Preamble Mode and Short Preamble Mode. Refer to the 10M_CFG Register

(address = 0x2A).

9.3.13.2 Normal Link Pulse Detection and Generation

The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-Te standard. Each link pulse is

nominally 100 ns in duration and transmitted every 16 ms in the absence of transmit data. Link pulses are used

to check the integrity of the connection with the remote end.

9.3.13.3 Jabber

Jabber is a condition in which a station transmits for a period of time longer than the maximum permissible

packet length, usually due to a fault condition. The jabber function monitors the DP83826 output and disables

the transmitter if it attempts to transmit a packet of longer than legal size. A jabber timer monitors the transmitter

and disables the transmission if the transmitter is active for approximately 100 ms. When disabled by the Jabber

function, the transmitter stays disabled for the entire time that the module's internal transmit enable is asserted.

This signal must be de-asserted for approximately 500 ms (unjab time) before the Jabber function re-enables the

transmit outputs. The Jabber function is only available and active in 10BASE-Te Mode.

9.3.13.4 Active Link Polarity Detection and Correction

Swapping the wires within the twisted-pair causes polarity errors. Wrong polarity affects 10BASE-Te

connections. 100BASE-TX is immune to polarity problems because it uses MLT-3 encoding. 10BASE-Te receive

block automatically detects reversed polarity.

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9.3.14 Loopback Modes

There are several loopback options within the DP83826 that test and verify various functional blocks within the

PHY. Enabling loopback modes allow for in-circuit testing of the digital and analog data paths. The DP83826

may be configured to any one of the Near-end Loopback modes or to the far-end (reverse) loopback mode. MII

loopback is configured using the BASIC mode Control Register (BMCR, address 0x0000). All other loopback

modes are enabled using the BIST Control Register (BISCR, address 0x0016). Except where otherwise noted,

loopback modes are supported for all speeds (10/100 Mbps and all MAC interfaces).

Reverse

Loopback

PCS

Loopback

Analog

Loopback

MAC

MII

Loopback

Digital

Loopback

External

Loopback

图9-7. Loopback Test Modes

9.3.14.1 Near-end Loopback

Near-end Loopback provides the ability to loop the transmitted data back to the receiver via the digital or analog

circuitry. The point at which the signal is looped back is selected using loopback control bits[3:0] in the BISCR

register. Auto-Negotiation should be disabled before selecting the Near-end Loopback modes. This constraint

does not apply for External Loopback Mode.

9.3.14.2 MII Loopback

MII Loopback is the shallowest loop through the PHY. It is a useful test mode to validate communications

between the MAC and the PHY. When in MII Loopback, data transmitted from a connected MAC on the TX path

is internally looped back in the DP83826 to the RX pins where it can be checked by the MAC.

MII Loopback is enabled by setting bit[14] in the BMCR and bit[2] in BISCR.

9.3.14.3 PCS Loopback

PCS Loopback occurs in the PCS layer of the PHY. No signal processing is performed when using PCS

Loopback.

PCS Input Loopback is enabled by setting bit[0] in the BISCR.

PCS Output Loopback is enabled by setting bit[1] in the BISCR.

9.3.14.4 Digital Loopback

Digital Loopback includes the entire digital transmit and receive paths. Data is looped back prior to the analog

circuitry.

Digital Loopback is requires following configuration:

• 0x0000 = 0x2100 // Disable Auto-Neg

• 0x0016 = 0x0104 // Digital Loopback

• 0x0122 = 0x2000 /

• 0x0123 = 0x2000

• 0x0130 = 0x47FF

• 0x001F = 0x4000 // Soft Reset

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9.3.14.5 Analog Loopback

When operating in 10BASE-Te or 100BASE-TX mode, signals can be looped back after the analog front-end.

Analog Loopback is enabled by setting bit[3] in the BISCR.

9.3.14.6 Far-End (Reverse) Loopback

Far-End (Reverse) loopback is a special test mode to allow PHY testing with a link partner. In this mode, data

that is received from the Link Partner passes through the PHY’s receiver, is looped back at the MAC interface

and then transmitted back to the Link Partner. While in reverse loopback mode, all data signals that come from

the MAC are ignored.

Reverse Loopback is enabled by setting bit[4] in the BISCR.

9.3.15 BIST Configurations

The DP83826 incorporates an internal PRBS built-in self-test (BIST) circuit to accommodate in-circuit testing and

diagnostics. The BIST circuit can be used to test the integrity of transmit and receive data paths. The BIST can

be performed using both internal loopbacks (digital or analog) or external loopback using a cable fixture. The

BIST simulates pseudo-random data transfer scenarios in format of real packets and inter-packet gap (IPG) on

the lines. The BIST allows full control of the packet lengths and the IPG.

The BIST packet length is controlled using bits[10:0] in the BIST Control and Status Register #2 (BICSR2,

address 0x001C). The BIST IPG length is controlled using bits[7:0] in the BIST Control and Status Register #1

(BICSR1, address 0x001B).

The BIST is implemented with independent transmit and receive paths, with the transmit clock generating a

continuous stream of a pseudo-random sequence. The device generates a 15-bit pseudo-random sequence for

BIST. Received data is compared to the generated pseudo-random data to determine pass/fail status. The

number of error bytes that the PRBS checker received is stored in bits[15:8] of the BICSR1. PRBS lock status

and sync can be read from the BIST Control Register (BISCR, address 0x0016).

The PRBS test can be put in a continuous mode by using bit[14] in the BISCR. In continuous mode, when the

BIST error counter reaches the maximum value, the counter starts counting from zero again. To read the BIST

error count, bit[15] in the BICSR1 must be set to '1'. This setting locks the current value of the BIST errors for

reading. Setting bit[15] also clears the BIST Error Counter.

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9.3.16 Cable Diagnostics

With the vast deployment of Ethernet devices, the need for a reliable, comprehensive and user-friendly cable

diagnostic tool is more important than ever. The wide variety of cables, topologies and connectors deployed

results in the need to non-intrusively identify and report cable faults. The DP83826 offers time domain

reflectometry (TDR) capabilities in its Cable Diagnostic tool kit.

9.3.16.1 Time Domain Reflectometry (TDR)

The DP83826 uses TDR to determine the quality of the cables, connectors and terminations in addition to

estimating the cable length. Some of the possible problems that can be diagnosed include opens, shorts, cable

impedance mismatch, bad connectors, termination mismatches, cross faults, cross shorts and any other

discontinuities along the cable.

The DP83826 transmits a test pulse of known amplitude (1 V) down each of the two pairs of an attached cable.

The transmitted signal continues down the cable and reflects from each cable imperfection, fault, connector and

from the end of the cable itself. After the pulse transmission, the DP83826 measures the return time and

amplitude of all these reflected pulses. This technique enables measuring the distance and magnitude

(impedance) of non-terminated cables (open or short), discontinuities (bad connectors) and improperly

terminated cables with ±1-m accuracy.

For all TDR measurements, the transformation between time of arrival and physical distance is done by the

external host using minor computations (such as multiplication, addition and lookup tables). The host must know

the expected propagation delay of the cable, which depends, among other things, on the cable category (for

example, CAT5, CAT5e, or CAT6).

TDR measurement is allowed in the following scenarios:

• While the link partner is disconnected –cable is unplugged at the other side

• Link partner is connected but remains “quiet”(for example, in power down mode)

• TDR could be automatically activated when the link fails or is dropped

TDR Auto-Run can be enabled by using bit[8] in the Control Regsiter #1 (CR1, address 0x0009). When a link-

drops, TDR automatically executes and stores the results in the respective TDR Cable Diagnostic Location

Result Registers #1 - #5 (CDLRR, addresses 0x0180 to 0x0184) and the Cable Diagnostic Amplitude Result

Registers #1 - #5 (CDLAR, addresses 0x0185 to 0x0189). TDR can also be run manually using bit[15] in the

Cable Diagnostic Control Register (CDCR, address 0x001E). Cable diagnostic status is obtained by reading

bits[1:0] in the CDCR. Additional TDR functions including cycle averaging and crossover disable can be found in

the Cable Diagnostic Specific Control Register (CDSCR, address 0x0170). Refer to the application report

Solving Cable Faults Challenges with TI Ethernet PHYs for details.

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9.3.16.2 Fast Link-Drop Functionality

The DP83826 includes advanced link-drop capabilities that support various real-time applications. The link-drop

mechanism is configurable and includes enhanced modes that allow extremely fast link-drop reaction times.

The DP83826 supports an enhanced link-drop mechanism, also called fast link-drop (FLD), which shortens the

observation window for determining link. There are multiple ways of determining link status, which can be

enabled or disabled based on user preference.

Depending on what mode the DP83826 is in, the default state of FLD will differ. In ENHANCED mode, FLD and

all its detection mechanisms are disabled by default through Strap7. In ENHANCED mode when Strap7 (FLD) is

enabled, all detection mechanisms except MTL3 error count are enabled and FLD is enabled. If Strap1 (Odd

Nibble) and Strap7 (FLD) are both enabled in ENHANCED mode, only SNR and signal/energy loss mechanisms

are enabled. If Strap1 (Odd Nibble) and Strap7 (FLD) are both enabled, Strap8 will toggle the signal energy

detect mechanism. For EtherCAT applications or applications with Fast link drop enabled and expect to handle

Baseline wander packets, it is recommended to disable signal energy detect, which can be done by setting

Strap8. The table below summarizes the modes enabled by strap. Any of the listed modes can be both disabled

or enabled after power-up via register settings.

表9-5. FLD Detection Modes by Strap

Strap Configuration RX Error Count

MLT3 Error Count

Low SNR Threshold Signal/Energy Loss Descrambler Link

Loss

Strap7 (Active High) = Disabled

Disabled

LOW

Strap1 (Active Low) =

X

Strap8 (Active High) =

X

Strap7 (AH) = HIGH Enabled

Strap1 (AL) = HIGH

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Strap8 (AH) = LOW

Strap7 (AH) = HIGH Enabled

Strap1 (AL) = LOW

Strap8 (AH) = LOW

Strap7 (AH) = HIGH Enabled

Strap1 (AL) = LOW

Strap8 (AH) = HIGH

In BASIC mode, fast link-drop is enabled by default. The default mechanisms in BASIC mode will be RX error

and signal/energy loss. Any adjustments to FLD in BASIC mode must be changed using register configuration.

In both modes, FLD can be configured using the Control Register #3 (CR3, address 0x000B). Bits[3:0] and

bit[10] allow for various FLD conditions to be enabled. When link-drop occurs, indication of a particular fault

condition can be read from the Fast Link Drop Status Register (FLDS, address 0x000F).

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First Link Failure

Occurrence

Valid Link

Low Quality Data / Link Loss

Link Drop

Link Loss

Indication

(Link LED)

图9-8. Fast Link-Drop

Fast link-drop criteria include:

• RX error count - when a predefined number of 32 RX_ERs occur in a 10-μs window, the link is dropped.

• MLT3 error count - when a predefined number of 20 MLT3 errors occur in a 10-μs window, the link is

dropped. To use the MLT3 error based FLD, please configure register Fast Link Drop Config Register 1

(FLDCFG1, address 0x0117) to 0x0417.

• Low SNR threshold - when a predefined number of 20 threshold crossings occur in a 10-μs window, the link

is dropped.

• Signal/energy loss - when the energy detector indicates energy loss, the link is dropped.

• Descrambler link loss - when the Descrambler loses lock, the link is dropped. To use the Descrambler link

loss based FLD, please configure bits[5:0] of Fast Link Drop Config Register 2 (FLDCFG2, address 0x0131)

to 0x08.

The fast link-drop functionality allows the use of each of these options separately or in any combination.

9.3.17 LED and GPIO Configuration

The DP83826 offers flexible LED and GPIO pins which can be set for various functions using register

configuration. Refer to 图9-9, for details on LED and GPIO configuration.

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Controls for LED0 = MLEDCR_0x25, LEDCR_0x18

Pin30 = led_0_gpio_ctrl = LED_0_CFG_REG_0x303[2:0]

Pin31 = led_1_gpio_ctrl = LED_1_CFG_REG_0x304[2:0]

Pin28 = led_2_gpio_ctrl = LED_2_CFG_REG_0x305[2:0]

Pin29 = led_3_gpio_ctrl = LED_3_CFG_REG_0x306[2:0]

Controls for LED1 = LEDCFG_0x460 , LEDCFG2_0x469

Controls for LED2 = LEDCFG_0x460 , LEDCFG2_0x469

Controls for LED3 = LEDCFG_0x460 , LEDCFG2_0x469

Bypass LED Stretching = PHYCR_0x19[7] – Common for all LED

Blink Rate = LEDCR_0x18[10:9] – Common for all LED

Link status

LED Genera on

Pin30

Pin31

Pin28

Pin29

0

1

2

3

4

5

6

7

Speed

WOL

LOW

INT

WOL

LOW

INT

WOL

COL

INT

WOL

CRS

Clocks

Genera on

INT

LOW

HIGH

LOW

HIGH

COL

HIGH

CRS

HIGH

led_0_clk_source = LED_0_CFG_REG_0x303[5:3]

led_1_clk_source = LED_1_CFG_REG_0x304[5:3]

led_2_clk_source = LED_2_CFG_REG_0x305[5:3]

led_3_clk_source = LED_3_CFG_REG_0x306[5:3]

图9-9. LED and GPIO Configuration

备注

A clock output is available on Pin 28 and 29 in ENHANCED mode only. These pins can be configured

to output only a 25-MHz or 50-MHz clock.

In ENHANCED mode, the LEDs have auto-polarity detection. The LED drive will adjust according to the strap

configured on the pin. For example, if the LED pin is configured for a pull-down strap, then the PHY will assign

the LED polarity as active high. If the LED pin is configured with a pull-up, the PHY will assign the LED polarity

as active low.

In BASIC mode, the LED polarity will always be active low. In the case that the LED pin must be strapped low, a

1 kΩ pull-up resistor in series with the LED should be used and a 5 kΩ pull-down resistor. This will result in the

strap selecting 0. Please note that using higher resistance may decrease the brightness of the LED.

9.4 Programming

The DP83826 provides hardware based configuration (via bootstraps) and the IEEE defined register set for

programming and status indications. It also provides an additional register set to configure other features not

supported through IEEE registers.

9.4.1 Hardware Bootstraps Configuration

DP83826 uses many of the functional pins as strap options to place the device into specific modes of operation.

The values of these pins are sampled at power up or hard reset. During software resets, the strap options are

internally reloaded from the values sampled at power up or hard reset. The strap option pin assignments are

defined below. Configuration of the device may be done through the strap pins or through the management

register interface. A pullup resistor or a pulldown resistor of suggested values may be used to set the voltage

ratio of the strap pin input and the supply to select one of the possible selected modes. All strap pins have two

levels.

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Internal PU pins

Internal PD pins

VDDIO

Rhi

10 kΩ

25%

10 kΩ

25%

Rlo

图9-10. Strap Circuit

表9-6. 2-Level Strap Resistor Ratios

SUGGESTED RESISTORS

Mode ⁽¹⁾

R_HI(kΩ)

R_LO(kΩ)

INTERNAL 10-kΩPULLDOWN (PD) PINS

0-DEFAULT

OPEN

2.49

OPEN

1

INTERNAL 10-kΩPULLUP (PU) PINS

0

OPEN

1.5

1-DEFAULT

OPEN

(1) Resistor ratios are only a recommendation. Use the bootstrap threshold values contained within the Electrical Characteristics table for

more precise mode selections. Recommended tolerance is 1%.

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9.4.1.1 DP83826 Bootstrap Configurations (ENHANCED Mode)

This section describes the hardware bootstraps available for some options for DP83826's Enhanced Mode. If no

strap resistors are implemented, the default value is Odd Nibble Enabled, MII mode, FLD disabled. '0'

corresponds to Mode 0 while '1' corresponds to Mode 1.

Strap1

‘1’

‘0’

Odd Nibble Enabled

Strap 8 selects MAC IF

Odd Nibble Disable

PHY automatically in MII

Strap8

‘1’

Strap7

‘0’

‘1’

‘0’

PHY is in

RMII mode

FLD disabled

Strap8 == X

PHY is in

MII mode

FLD

enabled

Strap5

Strap7

Strap8

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

FLD

Enabled

FLD

Disabled

Signal Energy

Detect Disabled

Signal Energy

Detect Enabled

RMII Slave

RMII Master

Strap7

‘1’

‘0’

Pin 18 is

CRS_DV

(RMII Repeater)

Pin 18 is

RX_DV

图9-11. Enhanced Bootstrap Flowchart

表9-7. PHY Address Strap Table

9.4.1.1.1 Bootstraps for PHY Address

PIN NAME

STRAP NAME

PIN NO.

DEFAULT

Mode

Function

PHY_ADD0

LED0

Strap2

30

0

1

0

1

PHY_ADD1

CRS/LED3

COL/LED2

Strap3

Strap4

29

28

0

1

0

1

PHY_ADD2

0

1

0

1

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表9-8. MAC Mode Selection Strap Table

PIN NAME

STRAP NAME

PIN NO.

DEFAULT

Mode

Function

MII MAC mode

ALT. Function: When Strap1 =0 AND

0

Strap7 =1, Signal Energy Detect enabled

RX_D2

Strap8

14

0

RMII MAC mode

ALT. Function: When Strap1 =0 AND

1

Strap7 =1, Signal Energy Detect disabled

表9-9. MII MAC Mode Strap Table

PIN NAME

STRAP NAME

PIN NO.

DEFAULT

Mode

Function

0

1

fast link-drop disable

fast link-drop enable

All available mechanisms will be enabled

RX_D3

Strap7

13

0

except MLT3_Error.

表9-10. RMII MAC Mode Strap Table

PIN NAME

STRAP NAME

PIN NO.

DEFAULT

Mode

Function

RMII master mode

0

1

0

1

TX_CLK

Strap5

22

0

RMII slave mode

RMII_CRS_DV

RX_D3

Strap7

13

0

RMII_RX_DV (for RMII repeater mode)

表9-11. Auto_Neg Strap Table

PIN NAME

STRAP NAME

PIN NO.

DEFAULT

Mode

Function

0

1

0

auto MDIX enable

auto MDIX disable

auto-negotiation enable

RX_D1

Strap9

15

0

RX_D0

RX_DV

Strap0

16

18

0

auto negotiation disable. force mode 100

M enabled

1

0

1

MDIX (applicable only when auto-MDIX is

disabled)

Strap10

MDI (applicable only when auto-MDIX is

disabled)

表9-12. CLKOUT/LED1 Bootstrap

PIN NAME

STRAP NAME

PIN NO.

DEFAULT

Mode

Function

0

1

CLKOUT 25 MHz on Pin 31

LED1 on Pin 31

RX_ER

Strap6

20

0

表9-13. Odd Nibble Detection Bootstrap

PIN NAME

STRAP NAME

PIN NO.

DEFAULT

Mode

Function

Odd Nibble Detection disabled

If Strap7 = 1, only RX_Error and Signal

0

1

CLKOUT/LED1

Strap1

31

1

Energy detect will be enabled for FLD.

Odd Nibble Detection enabled

Note: This strap is latched at POR only. HW reset using pin or register will not re-latch this strap.

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9.4.1.2 DP83826 Strap Configuration (BASIC Mode)

This section describes the strap configuration available for BASIC mode.

9.4.1.2.1 Bootstraps for PHY Address

表9-14. PHY Address Strap Table

PIN NAME

STRAP NAME

PIN NO.

DEFAULT

Mode

Function

PHY_ADD0

RX_D3

Strap7

13

1

0

1

0

1

PHY_ADD1

RX_D2

RX_D1

Strap8

Strap9

14

15

0

1

0

1

PHY_ADD2

0

1

0

1

表9-15. MAC Mode Selection Strap Table

STRAP

NAME

PIN NAME

PIN NO.

DEFAULT

Strap10

Strap3 Strap4

Function

0

1

MII MAC mode

RMII master mode

RMII slave mode

COL

Strap4

28

0

1

CRS

Strap3

29

18

0

other values are reserved

RX_DV

Strap10

表9-16. Auto Negotiation Strap Table

PIN NAME

STRAP NAME

PIN NO.

DEFAULT

Mode

Function

0

1

Auto Negotiation Disable

Auto Negotiation Enable

LED0

Strap2

30

1

表9-17. Speed Strap Table

PIN NAME

STRAP NAME

PIN NO.

DEFAULT

Mode

Function

0

1

Speed 10 M

Speed 100 M

LED1/

TX_ER

Strap1

31

1

表9-18. Full/Half Duplex Table

PIN NAME

STRAP NAME

PIN NO.

DEFAULT

Mode

Function

0

1

Full Duplex

Half Duplex

RX_D0

Strap0

16

1

表9-19. MII Isolate Bootstraps

PIN NAME

STRAP NAME

Strap6

PIN NO.

DEFAULT

Mode

Function

0

1

MII Isolate Disable

MII Isolate Enable

RX_ER

20

0

9.5 Register Maps

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9.5.1 DP83826 Registers

表 9-20 lists the memory-mapped registers for the DP83826 registers. All register offset addresses not listed in

表9-20 should be considered as reserved locations and the register contents should not be modified.

表9-20. DP83826 Registers

Offset

0h

Acronym

Register Name

Section

BMCR Register

BMSR Register

PHYIDR1 Register

PHYIDR2 Register

ANAR Register

ALNPAR Register

ANER Register

ANNPTR Register

ANLNPTR Register

CR1 Register

Basic Mode Control Register

Basic Mode Status Register

PHY Identifier Register #1

节9.5.1.1

节9.5.1.2

节9.5.1.3

节9.5.1.4

节9.5.1.5

节9.5.1.6

节9.5.1.7

节9.5.1.8

节9.5.1.9

节9.5.1.10

节9.5.1.11

节9.5.1.12

节9.5.1.13

节9.5.1.14

节9.5.1.15

节9.5.1.16

节9.5.1.17

节9.5.1.18

节9.5.1.19

节9.5.1.20

节9.5.1.21

节9.5.1.22

节9.5.1.23

节9.5.1.24

节9.5.1.25

节9.5.1.26

节9.5.1.27

节9.5.1.28

节9.5.1.29

节9.5.1.30

节9.5.1.31

节9.5.1.32

节9.5.1.33

节9.5.1.34

节9.5.1.35

节9.5.1.36

节9.5.1.37

节9.5.1.38

节9.5.1.39

1h

2h

3h

PHY Identifier Register #2

4h

Auto-Negotiation Advertisement Register

Auto-Negotiation Link Partner Ability Register

Auto-Negotiation Expansion Register

Auto-Negotiation Next Page Register

Auto-Negotiation Link Partner Ability Next Page Register

Control Register #1

5h

6h

7h

8h

9h

Ah

CR2 Register

Control Register #2

Bh

CR3 Register

Control Register #3

Dh

REGCR Register

ADDAR Register

FLDS Register

PHYSTS Register

PHYSCR Register

MISR1 Register

MISR2 Register

FCSCR Register

RECR Register

BISCR Register

RCSR Register

LEDCR Register

PHYCR Register

10BTSCR Register

BICSR1 Register

BICSR2 Register

CDCR Register

PHYRCR Register

MLEDCR Register

COMPT Regsiter

10M_CFG

Extended Register Control Register

Extended Register Data Register

Fast Link Down Status Register

PHY Status Register

Eh

Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Eh

1Fh

25h

27h

2Ah

117h

131h

170h

171h

173h

175h

PHY Specific Control Register

MII Interrupt Status Register #1

MII Interrupt Status Register #2

False Carrier Sense Counter Register

Receive Error Count Register

BIST Control Register

RMII and Status Register

LED Control Register

PHY Control Register

10Base-Te Status/Control Register

BIST Control and Status Register #1

BIST Control and Status Register #2

Cable Diagnostic Control Register

PHY Reset Control Register

Multi-LED Control Register

Compliance Test Register

FLD_CFG1

FLD_CFG2

CDSCR Register

CDSCR2 Register

CDSCR3 Register

TDR_175 Register

Cable Diagnostic Specific Control Register

Cable Diagnostic Specific Control Register 2

Cable Diagnostic Specific Control Register 3

TDR Control Register #1

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表9-20. DP83826 Registers (continued)

Offset

176h

177h

178h

180h

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

302h

303h

304h

305h

306h

308h

30Bh

30Ch

30Eh

404h

40Dh

456h

460h

461h

467h

468h

469h

4A0h

4A1h

4A2h

4A3h

4A4h

4A5h

4A6h

4A7h

Acronym

Register Name

Section

TDR_176 Register

CDSCR4 Register

TDR_178 Register

CDLRR1 Register

CDLRR2 Register

CDLRR3 Register

CDLRR4 Register

CDLRR5 Register

CDLAR1 Register

CDLAR2 Register

CDLAR3 Register

CDLAR4 Register

CDLAR5 Register

CDLAR6 Register

IO_CFG1 Register

LED0_GPIO_CFG

LED1_GPIO_CFG

LED2_GPIO_CFG

LED3_GPIO_CFG

CLK_OUT_LED_STATUS register

VOD_CFG1 Register

VOD_CFG2 Register

VOD_CFG3 Register

ANA_LD_PROG_SL Register

ANA_RX10BT_CTRL Register

GENCFG Register

LEDCFG Register

IOCTRL Register

TDR Control Register #2

节9.5.1.40

节9.5.1.41

节9.5.1.42

节9.5.1.43

节9.5.1.44

节9.5.1.45

节9.5.1.46

节9.5.1.47

节9.5.1.48

节9.5.1.49

节9.5.1.50

节9.5.1.51

节9.5.1.52

节9.5.1.53

节9.5.1.54

节9.5.1.55

节9.5.1.56

节9.5.1.57

节9.5.1.58

节9.5.1.59

节9.5.1.60

节9.5.1.61

节9.5.1.62

节9.5.1.63

节9.5.1.64

节9.5.1.65

节9.5.1.66

节9.5.1.67

节9.5.1.68

节9.5.1.69

节9.5.1.70

节9.5.1.71

节9.5.1.72

节9.5.1.73

节9.5.1.74

节9.5.1.75

节9.5.1.76

节9.5.1.77

节9.5.1.78

Cable Diagnostic Specific Control Register 4

TDR Control Register #3

Cable Diagnostic Location Result Register #1

Cable Diagnostic Location Result Register #2

Cable Diagnostic Location Result Register #3

Cable Diagnostic Location Result Register #4

Cable Diagnostic Location Result Register #5

Cable Diagnostic Amplitude Result Register #1

Cable Diagnostic Amplitude Result Register #2

Cable Diagnostic Amplitude Result Register #3

Cable Diagnostic Amplitude Result Register #4

Cable Diagnostic Amplitude Result Register #5

Cable Diagnostic Amplitude Result Register #6

GPIO Pin configuration Register #1

CLK_OUT_LED_STATUS configuration Register #3

VoD Config Register #1

VoD Config Register #2

VoD Config Register #3

Line Driver Config Register

Receive Configuration Register 10M

General Configuration Register

LEDs Configuration Register #1

IO MUX GPIO Control Register

Strap Latch-In Register #2

SOR1 Register

SOR2 Register

Strap Latch-In Register #2

LEDCFG2 Register

RXFCFG1 Register

RXFS Register

LEDs Configuration Register #2

Receive Configuration Register #1

Receive Status Register

RXFPMD1 Register

RXFPMD2 Register

RXFPMD3 Register

RXFSOP1 Register

RXFSOP2 Register

RXFSOP3 Register

Receive Perfect Match Data Register #1

Receive Perfect Match Data Register #2

Receive Perfect Match Data Register #3

Receive Secure-ON Password Register #1

Receive Secure-ON Password Register #2

Receive Secure-ON Password Register #3

Complex bit access types are encoded to fit into small table cells. 表 9-21 shows the codes that are used for

access types in this section.

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表9-21. DP83826 Access Type Codes

Access Type

Code

Description

Read Type

H

R

Set or cleared by hardware

Read

R

RC

R

C

Read

to Clear

RH

R

H

Read

Set or cleared by hardware

Write Type

W

Write

W, STRAP

W, W1S

W0C

W

Write

0C

0 to clear

W1S

W

Write

1S

1 to set

Reset or Default Value

-n

Value after reset or the default

value

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9.5.1.1 BMCR Register (Offset = 0h) [Reset = 3000h]

BMCR Register is shown in 表9-22.

Return to the 表9-20.

Basic Mode Control Register

表9-22. BMCR Register Field Descriptions

Bit

Field

Type

Reset

Description

15

Reset

HW1S

0h

PHY Software Reset: Writing a 1 to this bit resets the PHY PCS

registers. When the reset operation is completed,, this bit is cleared

to 0 automatically. PHY Vendor Specific registers will not be cleared.

0h = Normal Operation

1h = Initiate software Reset / Reset in Progress

14

13

MII Loopback

R/W

0h

MII Loopback: When MII loopback mode is activated, the transmitted

data presented on MII TXD is looped back to MII RXD internally.

Additionally set following additional bit BISCR 0x0016[4:0] =

0b00100 for 100Base-TX and BISCR 0x0016[4:0] = 00001b for

10Base-Te

0h = Normal Operation

1h = MII Loopback enabled

Speed Selection

R/W,STRAP 1h

Speed Selection: When Auto-Negotiation is disabled (bit [12] = 0 in

Register 0x0000), writing to this bit allows the port speed to be

selected.

In BASIC Mode: It is also determined by strap when Auto-

Negotiation is disabled.

0h = 10 Mbps

1h = 100 Mbps

12

11

Auto-Negotiation Enable

IEEE Power Down

Auto-Negotiation Enable: In BASIC Mode and ENHANCED Mode:

Latched by strap

0h = Disable Auto-Negotiation - bits [8] and [13] determine the port

speed and duplex mode

1h = Enable Auto-Negotiation - bits [8] and [13] of this register are

ignored when this bit is set

R/W

0h

Power Down: The PHY is powered down after this bit is set. Only

register access is enabled during this power down condition. To

control the power down mechanism, this bit is OR'ed with the input

from the INT/PWDN_N (in ENHANCED mode) pin. When the active

low INT/PWDN_N is asserted, this bit is set.

0h = Normal Operation

1h = IEEE Power Down

10

9

Isolate

R/W,STRAP 0h

RH/W,W1S 0h

In BASIC Mode, the value is Latched by strap

0h = Normal Operation

1h = Isolates the port from the MII with the exception of the serial

management interface. It also disables50MHz clock in RMII Master

Mode

Restart Auto-Negotiation

Restart Auto-Negotiation: If Auto-Negotiation is disabled (bit [12] =

0), bit [9] is ignored. This bit is self-clearing and will return a value of

1 until Auto-Negotiation is initiated, whereupon it will self-clear.

Operation of the Auto-Negotiation process is not affected by the

management entity clearing this bit.

0h = Normal Operation

1h = Restarts Auto-Negotiation, Re-initiates the Auto-Negotiation

process

8

Duplex Mode

R/W,STRAP 0h

Duplex Mode: When Auto-Negotiation is disabled, writing to this bit

allows the port Duplex capability to be selected. In BASIC Mode, this

bit is Latched by strap

0h = Half-Duplex

1h = Full-Duplex

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表9-22. BMCR Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

7

Collision Test

R/W

0h

Collision Test: When set, this bit causes the COL signal to be

asserted in response to the assertion of TX_EN within 512 bit times.

The COL signal is de-asserted within 4 bit times in response to the

de-assertion to TX_EN.

0h = Normal Operation

1h = Enable COL Signal Test

6-0

RESERVED

R

0h

Reserved

56

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9.5.1.2 BMSR Register (Offset = 1h) [Reset = 7849h]

BMSR Register is shown in 表9-23.

Return to the 表9-20.

Basic Mode Status Register

表9-23. BMSR Register Field Descriptions

Bit

Field

Type

Reset

Description

15

100Base-T4

R

0h

100Base-T4 Capable: This protocol is not available. Always reads as

0.

14

13

12

11

100Base-TX Full-Duplex

100Base-TX Half-Duplex

10Base-T Full-Duplex

10Base-T Half-Duplex

RESERVED

R

1h

100Base-TX Full-Duplex Capable:

0h = Device not able to perform Full-Duplex 100Base-TX

1h = Device able to perform Full-Duplex 100Base-TX

100Base-TX Half-Duplex Capable:

0h = Device not able to perform Half-Duplex 100Base-TX

1h = Device able to perform Half-Duplex 100Base-TX

10Base-T Full-Duplex Capable:

0h = Device not able to perform Full-Duplex 10Base-T

1h = Device able to perform Full-Duplex 10Base-T

10Base-T Half-Duplex Capable:

0h = Device not able to perform Half-Duplex 10Base-T

1h = Device able to perform Half-Duplex 10Base-T

10-7

6

R

0h

1h

Reserved

SMI Preamble

Suppression

Preamble Suppression Capable: If this bit is set to 1, 32-bits of

preamble needed only once after reset, invalid opcode or invalid

turnaround.

The device requires minimum of 500ns gap between two

transactions, followed by one positive edge of MDC and MDIO=1,

before starting the next transaction.

0h = Device not able to perform management transaction with

preambles suppressed

1h = Device able to perform management transaction with preamble

suppressed

5

4

Auto-Negotiation

Complete

R

H

0h

Auto-Negotiation Complete:

0h = Auto Negotiation process not completed (either still in process,

disabled or reset)

1h = Auto-Negotiation process completed

Remote Fault

Remote Fault: Far End Fault indication or notification from Link

Partner of Remote Fault. This bit is cleared on read or reset.

0h = No remote fault condition detected

1h = Remote fault condition detected

3

2

Auto-Negotiation Ability

Link Status

R

1h

0h

Auto-Negotiation Ability:

0h = Device is not able to perform Auto-Negotiation

1h = Device is able to perform Auto-Negotiation

RC

Link Status:

Last latched value is cleared on read

0h = Link not established

1h = Valid link established (for either 10 Mbps or 100 Mbps

operation)

1

0

Jabber Detect

H

R

0h

1h

Jabber Detect:

0h = No jabber condition detected This bit only has meaning for

10Base-T operation.

1h = Jabber condition detected

Extended Capability

Extended Capability:

0h = Basic register set capabilities only

1h = Extended register capabilities

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9.5.1.3 PHYIDR1 Register (Offset = 2h) [Reset = 2000h]

PHYIDR1 Register is shown in 表9-24.

Return to the 表9-20.

PHY Identifier Register #1

表9-24. PHYIDR1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

Organizationally Unique

Identifier Bits 21:6

R

2000h

PHY Identifier Register #1

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9.5.1.4 PHYIDR2 Register (Offset = 3h) [Reset = A131h]

PHYIDR2 Register is shown in 表9-25.

Return to the 表9-20.

PHY Identifier Register #2

表9-25. PHYIDR2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-10

Organizationally Unique

Identifier Bits 5:0

R

28h

PHY Identifier Register #2

9-4

3-0

Model Number

R

13h

1h

Vendor Model Number: The six bits of vendor model number are

mapped from bits [9] to [4]

11h = Basic Mode

13h = ENHANCED Mode

Revision Number

Model Revision Number: Four bits of the vendor model revision

number are mapped from bits [3:0]. This field is incremented for all

major device changes.

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9.5.1.5 ANAR Register (Offset = 4h) [Reset = 01E1h]

ANAR Register is shown in 表9-26.

Return to the 表9-20.

Auto-Negotiation Advertisement Register

表9-26. ANAR Register Field Descriptions

Bit

Field

Type

Reset

Description

15

0h

Next Page Indication:

0h = Next Page Transfer not desired

1h = Next Page Transfer desired

14

13

RESERVED

Remote Fault

R

0h

Reserved

R/W

Remote Fault:

0h = No Remote Fault detected

1h = Advertises that this device has detected a Remote Fault. Please

note DP83826 does not support Remote Fault. This bit shall not be

set by Application

12

11

RESERVED

R

0h

Reserved

Asymmetric Pause

R/W

Asymmetric Pause Support For Full-Duplex Links:

0h = Do not advertise asymmetric pause ability

1h = Advertise asymmetric pause ability

10

9

Pause

R/W

R

0h

Pause Support for Full-Duplex Links:

0h = Do not advertise pause ability

1h = Advertise pause ability

100Base-T4

100Base-T4 Support:

0h = Do not advertise 100Base-T4 ability

1h = Advertise 100Base-T4 ability

8

100Base-TX Full-Duplex

R/W,STRAP 1h

100Base-TX Full-Duplex Support:

Values does not matter in force-mode

BASIC Mode : Latched by strap

0h = Do not advertise 100Base-TX Full-Duplex ability Values does

not matter in force-mode

1h = Advertise 100Base-TX Full-Duplex ability

7

6

100Base-TX Half-Duplex R/W,STRAP 1h

100Base-TX Half-Duplex Support:

Values does not matter in force-mode

BASIC Mode: Latched by strap

0h = Do not advertise 100Base-TX Half-Duplex ability Values does

not matter in force-mode

1h = Advertise 100Base-TX Half-Duplex ability

10Base-T Full-Duplex

R/W,STRAP 1h

10Base-T Full-Duplex Support:

Values does not matter in force-mode

BASIC Mode: Latched by strap

0h = Do not advertise 10Base-T Full-Duplex ability Values does not

matter in force-mode

1h = Advertise 10Base-T Full-Duplex ability

5

10Base-T Half-Duplex

Selector Field

10Base-T Half-Duplex Support: Values does not matter in force-

mode BASIC Mode/ENHANCED Mode : Latched by strap

0h = Do not advertise 10Base-T Half-Duplex ability Values does not

matter in force-mode

1h = Advertise 10Base-T Half-Duplex ability

4-0

R/W

1h

Protocol Selection Bits: Technology selector field (IEEE802.3u

<00001>)

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9.5.1.6 ALNPAR Register (Offset = 5h) [Reset = 0000h]

ALNPAR Register is shown in 表9-27.

Return to the 表9-20.

Auto-Negotiation Link Partner Ability Register

表9-27. ALNPAR Register Field Descriptions

Bit

Field

Type

Reset

Description

15

0h

Next Page Indication:

0h = Link partner does not desire Next Page Transfer

1h = Link partner desires Next Page Transfer

14

13

Acknowledge

Remote Fault

R

0h

Acknowledge:

0h = Link partner does not acknowledge reception of link code word

1h = Link partner acknowledges reception of link code word

Remote Fault:

0h = Link partner does not advertise remote fault event detection

1h = Link partner advertises remote fault event detection

12

11

RESERVED

R

0h

Reserved

Asymmetric Pause

Asymmetric Pause:

0h = Link partner does not advertise asymmetric pause ability

1h = Link partner advertises asymmetric pause ability

10

9

Pause

R

0h

Pause:

0h = Link partner does not advertise pause ability

1h = Link partner advertises pause ability

100Base-T4

100Base-T4 Support:

0h = Link partner does not advertise 100Base-T4 ability

1h = Link partner advertises 100Base-T4 ability

8

100Base-TX Full-Duplex

100Base-TX Half-Duplex

10Base-T Full-Duplex

10Base-T Half-Duplex

Selector Field

100Base-TX Full-Duplex Support:

0h = Link partner does not advertise 100Base-TX Full-Duplex ability

1h = Link partner advertises 100Base-TX Full-Duplex ability

7

100Base-TX Half-Duplex Support:

0h = Link partner does not advertise 100Base-TX Half-Duplex ability

1h = Link partner advertises 100Base-TX Half-Duplex ability

6

10Base-T Full-Duplex Support:

0h = Link partner does not advertise 10Base-T Full-Duplex ability

1h = Link partner advertises 10Base-T Full-Duplex ability

5

10Base-T Half-Duplex Support:

0h = Link partner does not advertise 10Base-T Half-Duplex ability

1h = Link partner advertises 10Base-T Half-Duplex ability

4-0

Protocol Selection Bits: Technology selector field (IEEE802.3

<00001>)

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9.5.1.7 ANER Register (Offset = 6h) [Reset = 0004h]

ANER Register is shown in 表9-28.

Return to the 表9-20.

Auto-Negotiation Expansion Register

表9-28. ANER Register Field Descriptions

Bit

15-5

4

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

Parallel Detection Fault

H

0h

Parallel Detection Fault:

0h = No fault detected

1h = A fault has been detected during the parallel detection process

3

2

1

0

Link Partner Next Page

Able

R

H

R

0h

1h

0h

Link Partner Next Page Ability:

0h = Link partner is not able to exchange next pages

1h = Link partner is able to exchange next pages

Local Device Next Page

Able

Next Page Ability:

0h = Local device is not able to exchange next pages

1h = Local device is able to exchange next pages

Page Received

Link Code Word Page Received:

0h = A new page has not been received

1h = A new page has been received

Link Partner Auto-

Negotiation Able

Link Partner Auto-Negotiation Ability:

0h = Link partner does not support Auto-Negotiation

1h = Link partner supports Auto-Negotiation

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9.5.1.8 ANNPTR Register (Offset = 7h) [Reset = 2001h]

ANNPTR Register is shown in 表9-29.

Return to the 表9-20.

Auto-Negotiation Next Page Register

表9-29. ANNPTR Register Field Descriptions

Bit

Field

Type

Reset

Description

15

0h

Next Page Indication:

0h = Do not advertise desire to send additional next pages

1h = Advertise desire to send additional next pages

14

13

RESERVED

R

0h

1h

Reserved

Message Page

R/W

Message Page:

0h = Current page is an unformatted page

1h = Current page is a message page

12

11

Acknowledge 2

Toggle

R/W

R

0h

Acknowledge2: Acknowledge2 is used by the next page function to

indicate that Local Device has the ability to comply with the message

received.

0h = Cannot comply with message

1h = Will comply with message

Toggle: Toggle is used by the Arbiitration function within Auto-

Negotiation to synchronize with the Link Parnter during Next Page

exchange. This bit always takes the opposite value of the Toggle bit

in the previously exchanged Link Code Word.

0h = Value of toggle bit in previously transmitted Link Code Word

was 1

1h = Value of toggle bit in previously transmitted Link Code Word

was 0

10-0

CODE

R/W

1h

This field represents the code field of the next page transmission. If

the Message Page bit is set (bit [13] of this register), then the code is

interpreted as a Message Page, as defined in annex 28C of IEEE

802.3u. Otherwise, the code is interperated as an Unformatted Page,

and the interpretation is application specific.

The default value of the CODE represents a Null Page as defined in

Annex 28C of IEEE 802.3u.

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9.5.1.9 ANLNPTR Register (Offset = 8h) [Reset = 0000h]

ANLNPTR Register is shown in 表9-30.

Return to the 表9-20.

Auto-Negotiation Link Partner Ability Next Page Register

表9-30. ANLNPTR Register Field Descriptions

Bit

Field

Type

Reset

Description

15

0h

Next Page Indication:

0h = Do not advertise desire to send additional next pages

1h = Advertise desire to send additional next pages

14

13

12

Acknowledge

Message Page

Acknowledge 2

R

0h

Acknowledge:

0h = Link partner does not acknowledge reception of link code work

1h = Link partner acknowledges reception of link code word

Message Page:

0h = Current page is an unformatted page

1h = Current page is a message page

Acknowledge2: Acknowledge2 is used by the next page function to

indicate that Local Device has the ability to comply with the message

received.

0h = Cannot comply with message

1h = Will comply with message

11

Toggle

R

0h

Toggle: Toggle is used by the Arbiitration function within Auto-

Negotiation to synchronize with the Link Parnter during Next Page

exchange. This bit always takes the opposite value of the Toggle bit

in the previously exchanged Link Code Word.

0h = Value of toggle bit in previously transmitted Link Code Word

was 1

1h = Value of toggle bit in previously transmitted Link Code Word

was 0

10-0

Message/Unformatted

Field

R

0h

This field represents the code field of the next page transmission. If

the Message Page bit is set (bit 13 of this register), then the code is

interpreted as a Message Page, as defined in annex 28C of IEEE

802.3u. Otherwise, the code is interperated as an Unformatted Page,

and the interpretation is application specific.

The default value of the CODE represents a Null Page as defined in

Annex 28C of IEEE 802.3u.

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9.5.1.10 CR1 Register (Offset = 9h) [Reset = 0000h]

CR1 Register is shown in 表9-31.

Return to the 表9-20.

Control Register #1

表9-31. CR1 Register Field Descriptions

Bit

15-10

9

Field

Type

Reset

Description

Reserved

RESERVED

TDR Auto-Run

R

0h

R/W

0h

8

0h

TDR Auto-Run at Link Down

0h = Disable automatic execution of TDR

1h = Enable execution of TDR procedure after link down event

7

6

5

RESERVED

R/W

0h

Reserved

RESERVED

Robust Auto MDIX

Robust Auto-MDIX: If link partners are configured for operational

modes that are not supported by normal Auto-MDIX, Robust Auto-

MDIX allows MDI/MDIX resolution and prevents deadlock. When

using in Force Mode, Robust Auto-MDIX shall be enabled

0h = Disable Auto-MDIX

1h = Enable Robust Auto-MDIX

4

3-2

1

RESERVED

R/W

0h

Reserved

RESERVED

Fast RXDV Detection

Fast RXDV Detection:

0h = Disable Fast RX_DV detection. The PHY operates in normal

mode. RX_DV assertion after detection of /JK/.

1h = Enable assertion high of RX_DV on receive packet due to

detection of /J/ symbol only. If a consecutive /K/ does not appear,

RX_ER is generated.

0

RESERVED

R

0h

Reserved

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9.5.1.11 CR2 Register (Offset = Ah) [Reset = 0102h]

CR2 Register is shown in 表9-32.

Return to the 表9-20.

Control Register #2

表9-32. CR2 Register Field Descriptions

Bit

15

14

13-7

6

Field

Type

R/W

Reset

Description

RESERVED

0h

Reserved

0h

Reserved

2h

Reserved

0h

Reserved

5

Extended Full-Duplex

Ability

0h

Extended Full-Duplex Ability:

0h = Disable Extended Full-Duplex Ability. Decision to work in Full-

Duplex or Half-Duplex mode follows IEEE specification

1h = Enable Full-Duplex while working with link partner in force

100Base-TX. When the PHY is set to Auto-Negotiation or Force

100Base-TX and the link partner is operated in Force 100Base-TX,

the link is always Full-Duplex

4

3

2

RESERVED

R/W

0h

Reserved

RESERVED

RX_ER During IDLE

Detection of Receive Symbol Error During IDLE State:

0h = Disable detection of Receive symbol error during IDLE state

1h = Enable detection of Receive symbol error during IDLE state

1

Odd-Nibble Detection

Disable

R/W,STRAP 1h

Detection of Transmit Error. ENHANCED mode: Enabled by default,

can be changed with Strap1 BASIC mode: Disabled

0h = Enable detection of de-assertion of TX_EN on an odd-nibble

boundary. In this case TX_EN is extended by one additional TX_CLK

cycle and behaves as if TX_ER were asserted during that additional

cycle

1h = Disable detection of transmit error in odd-nibble boundary

0

RESERVED

R/W

0h

Reserved

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9.5.1.12 CR3 Register (Offset = Bh) [Reset = 0000h]

CR3 Register is shown in 表9-33.

Return to the 表9-20.

Control Register #3

表9-33. CR3 Register Field Descriptions

Bit

15-11

10

Field

Type

R/W

Reset

Description

RESERVED

0h

Reserved

Descrambler Fast Link

Down Mode

0h

Descrambler Fast Link Drop:

This option can be enabled in parallel to the other fast link down

modes in bits [3:0].

0h = Do not drop the link on descrambler link loss

1h = Drop the link on descrambler link loss

9

8

7

6

RESERVED

Polarity Swap

R

0h

Reserved

R/W

Polarity Swap:

Port Mirror Function: To enable port mirroring, set this bit and bit [5]

high.

1h = Inverted polarity on both pairs: TD+ and TD-, RD+ and RD- 0h

= Normal polarity

5

MDI/MDIX Swap

R/W

0h

MDI/MDIX Swap:

Port Mirror Function: To enable port mirroring, set this bit and bit [6]

high.

0h = MDI pairs normal (Receive on RD pair, Transmit on TD pair)

1h = Swap MDI pairs (Receive on TD pair, Transmit on RD pair)

4

RESERVED

Reserved

3-0

Fast Link Down Mode

R/W,STRAP 0h

Fast Link Down Modes:

Bit 3 Drop the link based on RX Error count of the MII interface.

When a predefined number of 32 RX Error occurences in a 10us

interval is reached, the link will be dropped.

Bit 2 Drop the link based on MLT3 Error count (Violation of the MLT3

coding in the DSP output). When a predefined number of 20 MLT3

Error occurences in10us interval is reached, the link will be dropped.

Bit 1 Drop the link based on Low SNR Threshold. When a predefined

number of 20 Threshold crossing occurences in a 10us interval is

reached, the link will be dropped.

Bit 0 Drop the link based on Signal/Energy Loss indication. When the

Energy detector indicates Energy Loss, the link will be dropped.

Typical reaction time is 10us

C : Bit 0 default is 0

NC+ MII: Bit 0 is taken from STRAP in ENHANCED mode

NC + RMII: Bit 0 default is 0

The Fast Link Down function is an OR of all 5 options (bits [10] and

[3:0]), the designer can enable any combination of these conditions.

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9.5.1.13 REGCR Register (Offset = Dh) [Reset = 0000h]

REGCR Register is shown in 表9-34.

Return to the 表9-20.

表9-34. REGCR Register Field Descriptions

Bit

Field

Type

Reset

Description

15-14

Extended Register

Command

R/W

0h

Extended Register Command:

0h = Address

1h = Data, no post increment

2h = Data, post increment on read and write

3h = Data, post increment on write only

13-5

4-0

RESERVED

DEVAD

R

0h

Reserved

R/W

Device Address: Bits [4:0] are the device address, DEVAD, that

directs any accesses of ADDAR register (0x000E) to the appropriate

MMD.

Specifically, the DP83826 uses the vendor specific DEVAD [4:0] =

'11111' for accesses to registers 0x04D1 and lower. For MMD3

access, the DEVAD[4:0] = '00011'. For MMD7 access, the

DEVAD[4:0] = '00111'.

All accesses through registers REGCR and ADDAR should use the

DEVAD for either MMD, MMD3 or MMD7. Transactions with other

DEVAD are ignored.

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9.5.1.14 ADDAR Register (Offset = Eh) [Reset = 0000h]

ADDAR Register is shown in 表9-35.

Return to the 表9-20.

表9-35. ADDAR Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

Address/Data

R/W

0h

If REGCR register bits [15:14] = '00', holds the MMD DEVAD's

address register, otherwise holds the MMD DEVAD's data.

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9.5.1.15 FLDS Register (Offset = Fh) [Reset = 0000h]

FLDS Register is shown in 表9-36.

Return to the 表9-20.

表9-36. FLDS Register Field Descriptions

Bit

15-9

8-4

Field

Type

Reset

Description

RESERVED

Fast Link Down Status

R

0h

Reserved

RC

0h

Fast Link Down Status:

Status Registers that latch high each time a given Fast Link Down

mode is activated and causes a link drop (assuming the modes were

enabled)

1h = Signal/Energy Lost

2h = SNR Level

4h = MLT3 Errors

8h = RX Errors

10h = Descrambler Loss Sync

3-0

RESERVED

R

0h

Reserved

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9.5.1.16 PHYSTS Register (Offset = 10h) [Reset = 0002h]

PHYSTS Register is shown in 表9-37.

Return to the 表9-20.

表9-37. PHYSTS Register Field Descriptions

Bit

15

14

Field

Type

Reset

Description

RESERVED

MDI/MDIX Mode

R

0h

Reserved

R

0h

MDI/MDIX Mode Status:

0h = MDI Pairs normal (Receive on RD pair, Transmit on TD pair)

1h = MDI Pairs swapped (Receive on TD pair, Transmit on RD pair)

13

12

Receive Error Latch

Polarity Status

RC

0h

Receive Error Latch:

This bit will be cleared upon a read of the RECR register

0h = No receive error event has occurred

1h = Receive error event has occurred since last read of RXERCNT

register (0x0015)

Polarity Status:

This bit is a duplication of bit [4] in the 10BTSCR register (0x001A).

This bit will be cleared upon a read of the 10BTSCR register, but not

upon a read of the PHYSTS register.

0h = Correct Polarity detected

1h = Inverted Polarity detected

11

10

False Carrier Sense Latch RC

0h

False Carrier Sense Latch:

This bit will be cleared upon a read of the FCSR register.

0h = No False Carrier event has occurred

1h = False Carrier even has occurred since last read of FCSCR

register (0x0014)

Signal Detect

RC

Signal Detect:

Active high 100Base-TX unconditional Signal Detect indication from

PMD

9

8

Descrambler Lock

Page Received

RC

0h

Descrambler Lock:

Active high 100Base-TX Descrambler Lock indication from PMD

Link Code Word Page Received:

This bit is a duplicate of Page Received (bit [1]) in the ANER register

and it is cleared on read of the ANER register (0x0006).

0h = Link Code Word Page has not been received

1h = A new Link Code Word Page has been received

7

6

5

MII Interrupt

Remote Fault

Jabber Detect

RC

0h

MII Interrupt Pending:

Interrupt source can be determined by reading the MISR register

(0x0012). Reading the MISR will clear this interrupt bit indication.

0h = No interrupt pending

1h = Indicates that an internal interrupt is pending

Remote Fault:

Cleared on read of BMSR register (0x0001) or by reset.

1h = Remote Fault condition detected. Fault criteria: notification from

link partner of Remote Fault via Auto-Negotiation 0h = No Remote

Fault condition detected

Jabber Detection:

This bit is only for 10 Mbps operation. This bit is a duplicate of the

Jabber Detect bit in the BMSR register (0x0001) and will not be

cleared upon a read of the PHYSTS register.

0h = No Jabber

1h = Jabber condition detected

4

3

Auto-Negotiation Status

MII Loopback Status

R

0h

Auto-Negotiation Status:

0h = Auto-Negotiation not complete

1h = Auto-Negotiation complete

MII Loopback Status:

0h = Normal operation

1h = Loopback enabled

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表9-37. PHYSTS Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2

Duplex Status

0h

Duplex Status:

BASIC Mode: Latched by Strap when Auto-Negotiation is disabled

ENHANCED Mode : 1 when Auto-Negotiation is disabled

0h = Half-Duplex mode

1h = Full-Duplex mode

1

0

Speed Status

Link Status

1h

0h

Speed Status:

BASIC Mode : Latched by Strap when Auto-Negotiation is disabled

ENHANCED Mode : 1 when Auto-Negotiation is disabled

0h = 100 Mbps mode

1h = 10 Mbps mode

R

Link Status:

This bit is duplicated from the Link Status bit in the BMSR register

( address 0x0001) and will not be cleared upon a read of the

PHYSTS register.

0h = No link established

1h = Valid link established (for either 10 Mbps or 100 Mbps)

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9.5.1.17 PHYSCR Register (Offset = 11h) [Reset = 0108h]

PHYSCR Register is shown in 表9-38.

Return to the 表9-20.

表9-38. PHYSCR Register Field Descriptions

Bit

Field

Type

Reset

Description

15

Disable PLL

R/W

0h

Disable PLL:

Note: clock circuitry can be disabled only in IEEE power down mode.

0h = Normal operation

1h = Disable internal clocks circuitry

14

Power Save Mode Enable R/W

0h

Power Save Mode Enable:

0h = Normal operation

1h = Enable power save modes

13-12

Power Save Modes

R/W

Power Save Mode:

0h = Normal operation mode. PHY is fully functional

1h = Reserved

2h = Active Sleep, Low Power Active Energy Saving mode that shuts

down all internal circuitry besides SMI and energy detect

functionalities. In this mode the PHY sends NLP every 1.4 seconds

to wake up link partner. Automatic power-up is done when link

partner is detected.

11

Scrambler Bypass

R/W

0h

Scrambler Bypass:

0h = Scrambler bypass disabled

1h = Scrambler bypass enabled

10

RESERVED

R/W

0h

1h

Reserved

9-8

Loopback FIFO Depth

Far-End Loopback FIFO Depth:

This FIFO is used to adjust RX (receive) clock rate to TX clock rate.

FIFO depth needs to be set based on expected maximum packet

size and clock accuracy. Default value sets to 5 nibbles.

0h = 4 nibbles FIFO

1h = 5 nibbles FIFO

2h = 6 nibbles FIFO

3h = 8 nibbles FIFO

7-5

4

RESERVED

R

0h

Reserved

COL Full-Duplex Enable

R/W

Collision in Full-Duplex Mode:

0h = Disable Collision in Full-Duplex mode. Collision will be active in

Half-Duplex only.

1h = Enable generating Collision signaling in Full-Duplex mode

3

2

Interrupt Polarity

Test Interrupt

R/W

1h

0h

Interrupt Polarity:

0h = Steady state (normal operation) is 0 logic and during interrupt is

1 logic

1h = Steady state (normal operation) is 1 logic and during interrupt is

0 logic

Test Interrupt:

Forces the PHY to generate an interrupt to facilitate interrupt testing.

Interrupts will continue to be generated as long as this bit remains

set.

0h = Do not generate interrupt

1h = Generate an interrupt

1

0

Interrupt Enable

R/W

0h

Interrupt Enable:

Enable interrupt dependent on the event enables in the MISR

register (0x0012).

0h = Disable event based interrupts

1h = Enable event based interrupts

Interrupt Output Enable

Interrupt Output Enable:

Enable active low interrupt events via the INTR/PWERDN pin by

configuring the INTR/PWRDN pin as an output( for ENHANCED

mode)

0h = INTR/PWRDN is a Power Down pin

1h = INTR/PWRDN is an interrupt output

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9.5.1.18 MISR1 Register (Offset = 12h) [Reset = 0000h]

MISR1 Register is shown in 表9-39.

Return to the 表9-20.

表9-39. MISR1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15

Link Quality Interrupt

RC

0h

Change of Link Quality Status Interrupt:

0h = Link quality is Good

1h = Change of link quality when link is ON

14

13

12

11

10

9

Energy Detect Interrupt

RC

0h

Change of Energy Detection Status Interrupt:

0h = No change of energy detected

1h = Change of energy detected

Link Status Changed

Interrupt

Change of Link Status Interrupt:

0h = No change of link status

1h = Change of link status interrupt is pending

Speed Changed Interrupt RC

Change of Speed Status Interrupt:

0h = No change of speed status

1h = Change of speed status interrupt is pending

Duplex Mode Changed

Interrupt

RC

Change of Duplex Status Interrupt:

0h = No change of duplex status

1h = Change of duplex status interrupt is pending

Auto-Negotiation

Completed Interrupt

Auto-Negotiation Complete Interrupt:

0h = No Auto-Negotiation complete event is pending

1h = Auto-Negotiation complete interrupt is pending

False Carrier Counter

Half-Full Interrupt

False Carrier Counter Half-Full Interrupt:

0h = False Carrier half-full event is not pending

1h = False Carrier counter (Register FCSCR, address 0x0014)

exceeds half-full interrupt is pending

8

Receive Error Counter

Half-Full Interrupt

RC

0h

Receiver Error Counter Half-Full Interrupt:

0h = Receive Error half-full event is not pending

1h = Receive Error counter (Register RECR, address 0x0015)

exceeds half-full interrupt is pending

7

6

5

4

3

2

Link Quality Interrupt

Enable

R/W

0h

Enable interrupt on change of link quality

Enable interrupt on change of energy detection

Enable interrupt on change of link status

Energy Detect Interrupt

Enable

Link Status Changed

Enable

Speed Changed Interrupt R/W

Enable

Enable Interrupt on change of speed status

Enable Interrupt on change of duplex status

Enable Interrupt on Auto-negotiation complete event

Duplex Mode Changed

Interrupt Enable

R/W

Auto-Negotiation

Completed Enable

1

0

False Carrier HF Enable

0h

Enable Interrupt on False Carrier Counter Register half-full event

Enable Interrupt on Receive Error Counter Register half-full event

Receive Error HF Enable R/W

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9.5.1.19 MISR2 Register (Offset = 13h) [Reset = 0000h]

MISR2 Register is shown in 表9-40.

Return to the 表9-20.

表9-40. MISR2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15

EEE Error Interrupt

RC

0h

Energy Efficient Ethernet Error Interrupt:

0h = EEE error has not occurred

1h = EEE error has occurred

14

13

12

11

10

9

Auto-Negotiation Error

Interrupt

RC

0h

Auto-Negotiation Error Interrupt:

0h = No Auto-Negotiation error even pending

1h = Auto-Negotiation error interrupt is pending

Page Received Interrupt

Page Receiver Interrupt:

0h = Page has not been received

1h = Page has been received

Loopback FIFO OF/UF

Event Interrupt

Loopback FIFO Overflow/Underflow Event Interrupt:

0h = No FIFO Overflow/Underflow event pending

1h = FIFO Overflow/Underflow event interrupt pending

MDI Crossover Change

Interrupt

MDI/MDIX Crossover Status Change Interrupt:

0h = MDI crossover status has not changed

1h = MDI crossover status changed interrupt is pending

Sleep Mode Interrupt

Sleep Mode Event Interrupt:

0h = No Sleep mode event pending

1h = Sleep mode event interrupt is pending

Inverted Polarity Interrupt / RC

WoL Packet Received

Interrupt

Inverted Polarity Interrupt / WoL Packet Received Interrupt:

0h = No Inverted polarity event pending / No WoL oacket received

1h = Inverted Polarity interrupt pending / WoL packet was recieved

8

Jabber Detect Interrupt

RC

Jabber Detect Event Interrupt:

0h = No Jabber detect event pending

1h = Jabber detect even interrupt pending

7

6

EEE Error Interrupt Enable R/W

0h

Enable interrupt on EEE Error

Auto-Negotiation Error

Interrupt Enable

R/W

Enable Interrupt on Auto-Negotiation error event

5

4

3

Page Received Interrupt

Enable

0h

Enable Interrupt on page receive event

Loopback FIFO OF/UF

Enable

Enable Interrupt on loopback FIFO Overflow/Underflow event

Enable Interrupt on change of MDI/X status

MDI Crossover Change

Enable

2

1

Sleep Mode Event Enable R/W

0h

Enable Interrupt on sleep mode event

Polarity Changed / WoL

Packet Enable

R/W

Enable Interrupt on change of polarity status

0

Jabber Detect Enable

R/W

0h

Enable Interrupt on Jabber detection event

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9.5.1.20 FCSCR Register (Offset = 14h) [Reset = 0000h]

FCSCR Register is shown in 表9-41.

Return to the 表9-20.

表9-41. FCSCR Register Field Descriptions

Bit

15-8

7-0

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

False Carrier Event

Counter

0h

False Carrier Event Counter:

This 8-bit counter increments on every false carrier event. This

counter stops when it reaches its maximum count (FFh).

When the counter exceeds half-full (7Fh), an interrupt event is

generated. This register is cleared on read.

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9.5.1.21 RECR Register (Offset = 15h) [Reset = 0000h]

RECR Register is shown in 表9-42.

Return to the 表9-20.

表9-42. RECR Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

Receive Error Counter

0h

RX_ER Counter:

When a valid carrier is presented (only while RXDV is set), and there

is at least one occurrence of an invalid data symbol, this 16-bit

counter increments for each receive error detected.

The RX_ER counter does not count in MII loopback mode.

The counter stops when it reaches its maximum count (FFh). When

the counter exceeds half-full (7Fh), an interrupt is generated. This

register is cleared on read.

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9.5.1.22 BISCR Register (Offset = 16h) [Reset = 0100h]

BISCR Register is shown in 表9-43.

Return to the 表9-20.

表9-43. BISCR Register Field Descriptions

Bit

15

14

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

BIST Error Counter Mode R/W

0h

BIST Error Counter Mode:

0h = Single mode, when BIST Error Counter reaches its max value,

PRBS checker stops counting.

1h = Continuous mode, when the BIST Error counter reaches its max

value, a pulse is generated and the counter starts counting from zero

again.

13

12

PRBS Checker Config

R/W

0h

PRBS Checker Config:bit[13:12]

0h = PRBS Generator and Checker both are disabled

1h = PRBS Generator Enabled, Trasnmit Single Packet with

Constant Data as configured in register 0x001C. Checker is disabled

2h = PRBS Generation is disabled. PRBS Checker is Enabled

3h = PRBS Generator and Checker both enabled. PRBS Generating

Continous Packets as configured in register 0x001C

Packet Generation Enable R/W

Packet Generation Enable:bit[13:12]

0h = PRBS Generator and Checker both are disabled

1h = PRBS Generator Enabled, Trasnmit Single Packet with

Constant Data as configured in register 0x001C. Checker is disabled

2h = PRBS Generation is disabled. PRBS Checker is Enabled

3h = PRBS Generator and Checker both enabled. PRBS Generating

Continous Packets as configured in register 0x001C

11

10

9

PRBS Checker Lock/Sync

PRBS Checker Sync Loss

Packet Generator Status

Power Mode

R

H

R

0h

1h

PRBS Checker Lock/Sync Indication:

0h = PRBS checker is not locked

1h = PRBS checker is locked and synced on received bit stream

PRBS Checker Sync Loss Indication:

0h = PRBS checker has not lost sync

1h = PRBS checker has lost sync

Packet Generation Status Indication:

0h = Packet Generator is off

1h = Packet Generator is active and generating packets

8

Sleep Mode Indication:

0h = Indicates that the PHY is in active sleep mode

1h = Indicates that the PHY is in normal power mode

7

6

RESERVED

0h

Reserved

Transmit in MII Loopback R/W

Transmit Data in MII Loopback Mode (valid only at 100 Mbps)

0h = Data is not transmitted to the line in MII loopback

1h = Enable transmission of data from the MAC received on the TX

pins to the line in parallel to the MII loopback to RX pins. This bit may

be set only in MII Loopback mode - setting bit [14] in in BMCR

register (0x0000)

5

RESERVED

R

0h

Reserved

4-0

Loopback Mode

R/W

Loopback Mode Select: The PHY provides several options for

loopback that test and verify various functional blocks within the PHY.

Enabling loopback mode allows in-circuit testing of the DP83826

digital and analog data paths

1h = PCS Input Loopback (Use for 10Base-Te only)

2h = PCS Output Loopback

4h = Digital Loopback ( Use for 100Base-TX Only) Additional

Register writes are required.

8h = Analog Loopback (requires 100Ωtermination)

10h = Reverse Loopback

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9.5.1.23 RCSR Register (Offset = 17h) [Reset = 0041h]

RCSR Register is shown in 表9-44.

Return to the 表9-20.

表9-44. RCSR Register Field Descriptions

Bit

15-13

12

Field

Type

Reset

Description

Reserved

RESERVED

RMII TX Clock Shift

R

0h

R

0h

11

R

0h

10

R

0h

9

R

0h

8

R/W

0h

RMII TX Clock Shift: Applicable only in RMII Slave Mode

0h = Transmit path internal clock shift is disabled

1h = Transmit path internal clock shift is enabled

7

RMII Clock Select

R/W,STRAP 0h

RMII Reference Clock Select:

BASIC Mode: Latched by strap

ENHANCED Modie: Latched by strap

0h = 25MHz clock reference, crystal or CMOS-level oscillator

1h = 50MHz clock reference, CMOS-level oscillator

6

5

4

RESERVED

R/W

1h

Reserved

RESERVED

R/W,STRAP 0h

RMII Revision Select

R/W

0h

RMII Revision Select:

0h = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to

indicate de-assertion of CRS

1h = (RMII revision 1.0) CRS_DV will remain asserted until final data

is transferred. CRS_DV will not toggle at the end of a packet

3

2

RMII Overflow Status

RMII Underflow Status

0h

1h

RX FIFO Overflow Status:

0h = Overflow detected

1h = Normal

RX FIFO Underflow Status:

0h = Underflow detected

1h = Normal

1-0

Receive Elasticity Buffer

Size

R/W

Receive Elasticity Buffer Size:

This field controls the Receive Elasticity Buffer which allows for

frequency variation tolerance between the 50MHz RMII clock and the

recovered data. The following values indicate the tolerance in bits for

a single packet. The minimum setting allows for standard Ethernet

frame sizes at +/-50ppm accuracy. For greater frequency tolerance,

the packet lengths may be scaled (for +/-100ppm), divide the packet

lengths by 2).

0h = 14 bit tolerance (up to 16800 byte packets)

1h = 2 bit tolerance (up to 2400 byte packets)

2h = 6 bit tolerance (up to 7200 byte packets)

3h = 10 bit tolerance (up to 12000 byte packets)

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9.5.1.24 LEDCR Register (Offset = 18h) [Reset = 0400h]

LEDCR Register is shown in 表9-45.

Return to the 表9-20.

表9-45. LEDCR Register Field Descriptions

Bit

Field

Type

Reset

Description

15-11

10-9

RESERVED

Blink Rate

R

0h

Reserved

R/W

2h

LED Blinking Rate (ON/OFF duration):

0h = 20Hz (50 ms)

1h = 10Hz (100 ms)

2h = 5Hz (200 ms)

3h = 2Hz (500 ms)

8

7

RESERVED

R/W

0h

Reserved

LED Link Polarity

R/W,STRAP 0h

LED Link Polarity Setting: Link LED polarity is Active Low in BASIC

mode and defined by direction of strapping on this pin in

ENHANCED mode. This register allows for override of this strap

value.

0h = Active Low polarity setting

1h = Active High polarity setting

6-5

4

RESERVED

R/W

0h

Reserved

Drive Link LED

Drive Link LED Select:

0h = Normal operation

1h = Drive value of ON/OFF bit [1] onto LED0 output pin

3-2

1

RESERVED

R/W

0h

Reserved

Link LED ON/OFF Setting R/W

Value to force on Link LED output

0h = LOW

1h = HIGH

0

RESERVED

R/W

0h

Reserved

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9.5.1.25 PHYCR Register (Offset = 19h) [Reset = 8000h]

PHYCR Register is shown in 表9-46.

Return to the 表9-20.

表9-46. PHYCR Register Field Descriptions

Bit

Field

Type

Reset

Description

15

Auto MDI/X Enable

R/W,STRAP 1h

Auto-MDIX Enable: BASIC Mode: Default to A-MDIX enabled.

ENHANCED Mode : Latched by strap A-MDIX

0h = Disable Auto-Negotiation Auto-MDIX capability

1h = Enable Auto-Negotiation Auto-MDIX capability

14

13

Force MDI/X

R/W,STRAP 0h

Force MDIX: ENHANCED Mode: When A-MDIX strap is disabled,

latched by FORCE MDI/MDIX strap

0h = Normal operation (Receive on RD pair, Transmit on TD pair)

1h = Force MDI pairs to cross (Receive on TD pair, Transmit on RD

pair)

Pause RX Status

R

0h

Pause Receive Negotiation Status: Indicates that pause receive

should be enabled in the MAC. Based on bits [11:10] in ANAR

register and bits [11:10] in ANLPAR register settings. The function

shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3,

'Pause Resolution', only if the Auto-Negotiation highest common

denominator is a Full-Duplex technology.

12

11

Pause TX Status

MII Link Status

Pause Transmit Negotiated Status: Indicates that pause should be

enabled in the MAC. Based on bits [11:10] in ANAR register and bits

[11:10] in ANLPAR register settings. This function shall be enabled

according to IEEE 802.3 Annex 28B Table 28B-3, 'Pause

Resolution', only if the Auto-Negotiation highest common

denominator is a Full-Duplex technology.

MII Link Status:

0h = No active 100Base-TX Full-Duplex link, established using Auto-

Negotiation

1h = 100Base-TX Full-Duplex link is active and it was established

using Auto-Negotiation

10-8

7

RESERVED

R

0h

Reserved

Bypass LED Stretching

R/W

Bypass LED Stretching: Set this bit to '1' to bypass the LED

stretching, the LED reflects the internal value.

0h = Normal LED operation

1h = Bypass LED stretching

6

5

RESERVED

R/W

0h

Reserved

LED Configuration

PHY Address

4-0

PHY Address: BASIC Mode: Latched by Strap ENHANCED Mode:

Latched by Strap

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9.5.1.26 10BTSCR Register (Offset = 1Ah) [Reset = 0000h]

10BTSCR Register is shown in 表9-47.

Return to the 表9-20.

表9-47. 10BTSCR Register Field Descriptions

Bit

15-14

13

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

Receiver Threshold

Enable

R/W

0h

Lower Receiver Threshold Enable:

0h = Normal 10Base-T operation

1h = Enable 10Base-T lower receiver threshold to allow operation

with longer cables

12-9

Squelch

R/W

0h

Squelch Configuration: Used to set the Peak Squelch 'ON' threshold

for the 10Base-T receiver. Starting from 200mV to 600mV, step size

of 50mV with some overlapping as shown below:

0h = 200mV

1h = 250mV

2h = 300mV

3h = 350mV

4h = 400mV

5h = 450mV

6h = 500mV

7h = 550mV

8h = 600mV

8

7

RESERVED

NLP Disable

R/W

0h

Reserved

NLP Transmission Control:

0h = Enable transmission of NLPs

1h = Disable transmission of NLPs

6-5

4

RESERVED

R

0h

Reserved

Polarity Status

Polarity Status:

This bit is a duplication of bit [12] in the PHYSTS register (0x0010).

Both bits will be cleared upon a read of 10BTSCR register, but not

upon a read of the PHYSTS register.

0h = Correct Polarity detected

1h = Inverted Polarity detected

3-1

0

RESERVED

R

0h

Reserved

Jabber Disable

R/W

Jabber Disable:

Note: This function is only applicable in 10Base-Te operation.

0h = Jabber function enabled

1h = Jabber function disabled

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9.5.1.27 BICSR1 Register (Offset = 1Bh) [Reset = 007Dh]

BICSR1 Register is shown in 表9-48.

Return to the 表9-20.

表9-48. BICSR1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-8

BIST Error Count

R

0h

BIST Error Count:

Holds number of errored bytes received by the PRBS checker. Value

in this register is locked and cleared when write is done to bit [15].

When BIST Error Counter Mode is set to '0', count stops on 0xFF

(see register 0x0016)

Note: Writing '1' to bit [15] will lock the counter's value for successive

read operation and clear the BIST Error Counter.

7-0

BIST IPG Length

R/W

7Dh

BIST IPG Length:

Inter Packet Gap (IPG) Length defines the size of the gap (in bytes)

between any 2 successive packets generated by the BIST.

Default value is 0x7D (equal to 125 bytes*4 = 500 bytes).

Binary values shall be multiplied by 4 to get the actual IPG length

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9.5.1.28 BICSR2 Register (Offset = 1Ch) [Reset = 05EEh]

BICSR2 Register is shown in 表9-49.

Return to the 表9-20.

表9-49. BICSR2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-11

10-0

RESERVED

BIST Packet Length

R

0h

Reserved

R/W

5EEh

BIST Packet Length:

Length of the generated BIST packets. The value of this register

defines the size (in bytes) of every packet that is generated by the

BIST.

Default value is 0x05EE, which is equal to 1518 bytes.

84

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9.5.1.29 CDCR Register (Offset = 1Eh) [Reset = 0100h]

CDCR Register is shown in 表9-50.

Return to the 表9-20.

表9-50. CDCR Register Field Descriptions

Bit

Field

Type

Reset

Description

15

Cable Diagnostic Start

R/W

0h

Cable Diagnostic Process Start:

Diagnostic Start bit is cleared once Diagnostic Done indication bit is

triggered.

0h = Cable Diagnostic is disabled

1h = Start cable measurement

14

13-2

1

cfg_rescal_en

R/W

R

0h

Resistor calibration Start

Reserved

RESERVED

40h

0h

Cable Diagnostic Status

R

Cable Diagnostic Process Done:

0h = Cable Diagnostic had not completed

1h = Indication that cable measurement process is complete

0

Cable Diagnostic Test Fail

R

0h

Cable Diagnostic Process Fail:

0h = Cable Diagnostic has not failed

1h = Indication that cable measurement process failed

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9.5.1.30 PHYRCR Register (Offset = 1Fh) [Reset = 0000h]

PHYRCR Register is shown in 表9-51.

Return to the 表9-20.

表9-51. PHYRCR Register Field Descriptions

Bit

Field

Type

Reset

Description

15

Software Hard Reset

HW1S

0h

Software Hard Reset:

0h = Normal Operation

1h = Reset PHY. This bit is self cleared and has the same effect as

Hardware reset pin.

14

Digital reset

HW1S

0h

Software Restart:

0h = Normal Operation

1h = Restart PHY. This bit is self cleared and resets all PHY circuitry

except the registers.

13

RESERVED

R/W

0h

Reserved

12-0

86

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9.5.1.31 MLEDCR Register (Offset = 25h) [Reset = 0041h]

MLEDCR Register is shown in 表9-52.

Return to the 表9-20.

表9-52. MLEDCR Register Field Descriptions

Bit

15-10

9

Field

Type

R/W

Reset

Description

RESERVED

MLED Polarity Swap

0h

Reserved

0h

MLED Polarity Swap:

The polarity of MLED depends on the routing configuration and the

strap on LED1 pin, but only in ENHANCED mode. If the pin strap is

Pull-Up then polarity is active low. If the pin strap is Pull-Down then

polarity is active high. In BASIC mode, the polarity is always active

low.

8-7

6-3

RESERVED

R/W

0h

8h

Reserved

LED0 Configuration

MLED Configurations: Selects the source for LED0

0h = LINK OK

1h = RX/TX Activity

2h = TX Activity

3h = RX Activity

4h = Collision

5h = Speed, High for 100BASE-TX

6h = Speed, High for 10BASE-T

7h = Full-Duplex

8h = LINK OK / BLINK on TX/RX Activity

9h = Active Stretch Signal

Ah = MII LINK (100BT+FD)

Bh = LPI Mode (EEE)

Ch = TX/RX MII Error

Dh = Link Lost (remains on until register 0x0001 is read)

Eh = Blink for PRBS error (remains ON for single error, remains until

counter is cleared)

Fh = Reserved

2-1

0

RESERVED

cfg_mled_en

R

0h

1h

Reserved

R/W

MLED Route to LED0:

0h = Reserved

1h = Value routed as per MLEDCR[6:3]

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9.5.1.32 COMPT Regsiter Register (Offset = 27h) [Reset = 0000h]

COMPT Regsiter is shown in 表9-53.

Return to the 表9-20.

表9-53. COMPT Regsiter Register Field Descriptions

Bit

15-4

3-0

Field

Type

R/W

Reset

0h

Description

Reserved

Compliance Test Configuration Select:

Bit [4] in Register 0x0027 = 1, Enables 10Base-T Test Patterns

Bit [4] in Register 0x0428 = 1, Enables 100Base-TX Test Modes

Bits [3:0] select the 10Base-T test pattern, as follows:

0000 = Single NLP

RESERVED

Compliance Test

Configuration

0001 = Single Pulse 1

0010 = Single Pulse 0

0011 = Repetitive 1

0100 = Repetitive 0

0101 = Preamble (repetitive '10')

0110 = Single 1 followed by TP_IDLE

0111 = Single 0 followed by TP_IDLE

1000 = Repetitive '1001' sequence

1001 = Random 10Base-T data

1010 = TP_IDLE_00

1011 = TP_IDLE_01

1100 = TP_IDLE_10

1101 = TP_IDLE_11

100Base-TX Test Mode is determined by bits {[5] in register 0x0428,

[3:0] in register 0x0027}. The bits determine the number of 0's to

follow a '1'.

0,0001 = Single '0' after a '1'

0,0010 = Two '0' after a '1'

0,0011 = Three '0' after a '1'

0,0100 = Four '0' after a '1'

0,0101 = Five '0' after a '1'

0,0110 = Six '0' after a '1'

0,0111 = Seven '0' after a '1'

...

1,1111 = Thirty one '0' after a '1'

0,0000 = Clears the shift register

Note 1: To reconfigure the 100Base-TX Test Mode, bit [4] must be

cleared in register 0x0428 and then reset to '1' to configure the new

pattern.

Note 2: When performing 100Base-TX or 10Base-T tests modes, the

speed must be force using the Basic Mode Control Register (BMCR),

address 0x0000.

88

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9.5.1.33 10M_CFG Register (Offset = 2Ah) [Reset = 7998h]

10M_CFG is shown in 表9-54.

Return to the 表9-20.

表9-54. 10M_CFG Register Field Descriptions

Bit

15

14

Field

Type

Reset

Description

RESERVED

10M Preamble Mode

R

0h

Reserved

R/W

1h

The device supports two preamble size for 10Mbps. - (0) Long

Preamble Mode (1) Short Preamble Mode, This does not affect the

100Mbps mode.

In Long Preamble mode, "Long" denotes the number of preamble

received from MDI. In this mode, the receiver takes up to 7 bytes of

preamble to declare this as a valid preamble. The preamble on the

MAC can have lesser preambles than the bytes from MDI. The

device expects at least 7 bytes of preamble to be on the MDI line.

In Short Preamble mode, "Short" denotes the preamble bytes on the

MDI line. In this mode, the receiver can work with shorter preambles

> 3 bytes. If Link Partner is expected to transfer shorter preamble ( <

3 bytes), it is recommended to configure to "Long" preamble mode.

0h = Long Preamble Mode

1h = Short Preamble Mode

13-0

RESERVED

R/W

3998h

Reserved

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9.5.1.34 FLD_CFG1 Register (Offset = 117h) [Reset = 0000h]

FLD_CFG1 is shown in 表9-55.

Return to the 表9-20.

表9-55. FLD_CFG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-10

Config MLT3 Error Cnt

Len

R/W

0h

MLT3 Error count window. Sets the window in terns if number of

clocks (8ns). The counter counts in steady state.

0h = Reserved

1h = 2 cycle

3Fh = 64 cycle

9-4

3-0

Config MLT3 Error

Number Cnt

R/W

R

0h

Numbers of MLT3 errors to be counted for link down

0h = Reserved

1h = 1 Error

3Fh = 63 Errors

RESERVED

Reserved

90

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9.5.1.35 FLD_CFG2 Register (Offset = 131h) [Reset = 0000h]

FLD_CFG2 is shown in 表9-56.

Return to the 表9-20.

表9-56. FLD_CFG2 Register Field Descriptions

Bit

15-6

5-0

Field

Type

R/W

Reset

Description

RESERVED

0h

Reserved

Config Scrambler

Threshold

0h

Configures the window to declare link down based on descrambler

errors.

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9.5.1.36 CDSCR Register (Offset = 170h) [Reset = 0C12h]

CDSCR Register is shown in 表9-57.

Return to the 表9-20.

表9-57. CDSCR Register Field Descriptions

Bit

15

14

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

Cable Diagnostic Cross

Disable

R/W

0h

Cross TDR Diagnostic Mode:

0h = TDR looks for reflections on channel other than the transmit

channel configured by 0x170[13]

1h = TDR looks for reflections on same channel as transmit channel

configured by 0x170[13]

13

12

cfg_tdr_chan_sel

R/W

0h

TDR TX channel select:

0h = Select channel A as transmit channel.

1h = Select channel B as transmit channel.

cfg_tdr_dc_rem_no_init

RESERVED

R/W

To make sure DC removal module is not reset before TDR and dc

removal is effective on TDR reflection

11

1h

4h

Reserved

10-8

Cable Diagnostic Average R/W

Cycles

Number of TDR Cycles to Average:

0h = 1 TDR cycle

1h = 2 TDR cycles

2h = 4 TDR cycles

3h = 8 TDR cycles

4h = 16 TDR cycles

5h = 32 TDR cycles

6h = 64 TDR cycles

7h = Reserved

7

RESERVED

R/W

0h

1h

Reserved

6-4

cfg_tdr_seg_num

Selects cable segment on which TDR is to be performed - 000b =

Reserved 001b = 0m to 10m 010b = 10m to 20m 011b = 20m to 40m

100b = 40m to 80m 101b = 80m and beyond 110b = Reserved 111b

= Reserved

3-0

RESERVED

R/W

2h

Reserved

92

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9.5.1.37 CDSCR2 Register (Offset = 171h) [Reset = C850h]

CDSCR2 Register is shown in 表9-58.

Return to the 表9-20.

表9-58. CDSCR2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

RESERVED

R/W

C850h

Reserved

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9.5.1.38 CDSCR3 Register (Offset = 173h) [Reset = 0D04h]

CDSCR3 Register is shown in 表9-59.

Return to the 表9-20.

表9-59. CDSCR3 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-8

cfg_tdr_seg_duration

R/W

Dh

Duration of the segment selected for TDR, calculated by -

(Length_in_meters*2*5.2)/8 For Segment #1, 8'hD For Segment #2,

8'hD For Segment #3, 8'h1A For Segment #4, 8'h34 For Segment

#5, 8'h8F

7-0

cfg_tdr_initial_skip

R/W

4h

No of samples to be avoided before start of segment configured - For

Segment #1, 8'h7 For Segment #2, 8'h14 For Segment #3, 8'h21 For

Segment #4, 8'h3B For Segment #5, 8'h6F

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9.5.1.39 TDR_175 Register (Offset = 175h) [Reset = 1004h]

TDR_175 Register is shown in 表9-60.

Return to the 表9-20.

表9-60. TDR_175 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-14

13-11

RESERVED

cfg_tdr_sdw_avg_loc

R

0h

Reserved

R/W

2h

TDR shadow average location - For Segment #1, 3'h2 For Segment

#2, 3'h2 For Segment #3, 3'h2 For Segment #4, 3'h2 For Segment

#5, 3'h2

10-5

4

RESERVED

R

0h

4h

Reserved

RESERVED

R/W

3-0

cfg_tdr_fwd_shadow

Length of forward shadow for the segment configured (to avoid

shadow of a fault peak be seen as another fault peak) - For Segment

#1, 4'h4 For Segment #2, 4'h4 For Segment #3, 4'h5 For Segment

#4, 4'h8 For Segment #5, 4'hB

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9.5.1.40 TDR_176 Register (Offset = 176h) [Reset = 0005h]

TDR_176 Register is shown in 表9-61.

Return to the 表9-20.

表9-61. TDR_176 Register Field Descriptions

Bit

15-5

4-0

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

cfg_tdr_p_loc_thresh_seg R/W

5h

96

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9.5.1.41 CDSCR4 Register (Offset = 177h) [Reset = 1E00h]

CDSCR4 Register is shown in 表9-62.

Return to the 表9-20.

表9-62. CDSCR4 Register Field Descriptions

Bit

15-13

12-8

7-0

Field

Type

R/W

Reset

Description

RESERVED

Short Cables Threshold

RESERVED

0h

Reserved

1Eh

0h

TH to compensate for strong reflections in short cables

Reserved

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9.5.1.42 TDR_178 Register (Offset = 178h) [Reset = 0002h]

TDR_178 Register is shown in 表9-63.

Return to the 表9-20.

表9-63. TDR_178 Register Field Descriptions

Bit

15-3

2-0

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

cfg_tdr_tx_pulse_width_se R/W

g

2h

TDR TX Pulse width for Segment - For Segment #1, 3'h2 For

Segment #2, 3'h2 For Segment #3, 3'h2 For Segment #4, 3'h2 For

Segment #5, 3'h6

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9.5.1.43 CDLRR1 Register (Offset = 180h) [Reset = 0000h]

CDLRR1 Register is shown in 表9-64.

Return to the 表9-20.

表9-64. CDLRR1 Register Field Descriptions

Bit

15-8

7-0

Field

Type

Reset

Description

RESERVED

TD Peak Location 1

R

0h

Reserved

R

0h

Location of the First peak discovered by the TDR mechanism on

Transmit Channel (TD). The value of these bits need to be translated

into distance from the PHY.

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9.5.1.44 CDLRR2 Register (Offset = 181h) [Reset = 0000h]

CDLRR2 Register is shown in 表9-65.

Return to the 表9-20.

表9-65. CDLRR2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

RESERVED

R

0h

Reserved

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9.5.1.45 CDLRR3 Register (Offset = 182h) [Reset = 0000h]

CDLRR3 Register is shown in 表9-66.

Return to the 表9-20.

表9-66. CDLRR3 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

RESERVED

R

0h

Reserved

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9.5.1.46 CDLRR4 Register (Offset = 183h) [Reset = 0000h]

CDLRR4 Register is shown in 表9-67.

Return to the 表9-20.

表9-67. CDLRR4 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

RESERVED

R

0h

Reserved

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9.5.1.47 CDLRR5 Register (Offset = 184h) [Reset = 0000h]

CDLRR5 Register is shown in 表9-68.

Return to the 表9-20.

表9-68. CDLRR5 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

RESERVED

R

0h

Reserved

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9.5.1.48 CDLAR1 Register (Offset = 185h) [Reset = 0000h]

CDLAR1 Register is shown in 表9-69.

Return to the 表9-20.

表9-69. CDLAR1 Register Field Descriptions

Bit

15-7

6-0

Field

Type

Reset

Description

RESERVED

TD Peak Amplitude 1

R

0h

Reserved

R

0h

Amplitude of the First peak discovered by the TDR mechanism on

Transmit Channel (TD). The value of these bits is translated into type

of cable fault and/or interference.

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9.5.1.49 CDLAR2 Register (Offset = 186h) [Reset = 0000h]

CDLAR2 Register is shown in 表9-70.

Return to the 表9-20.

表9-70. CDLAR2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

RESERVED

R

0h

Reserved

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9.5.1.50 CDLAR3 Register (Offset = 187h) [Reset = 0000h]

CDLAR3 Register is shown in 表9-71.

Return to the 表9-20.

表9-71. CDLAR3 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

RESERVED

R

0h

Reserved

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9.5.1.51 CDLAR4 Register (Offset = 188h) [Reset = 0000h]

CDLAR4 Register is shown in 表9-72.

Return to the 表9-20.

表9-72. CDLAR4 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

RESERVED

R

0h

Reserved

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9.5.1.52 CDLAR5 Register (Offset = 189h) [Reset = 0000h]

CDLAR5 Register is shown in 表9-73.

Return to the 表9-20.

表9-73. CDLAR5 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

RESERVED

R

0h

Reserved

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9.5.1.53 CDLAR6 Register (Offset = 18Ah) [Reset = 0000h]

CDLAR6 Register is shown in 表9-74.

Return to the 表9-20.

表9-74. CDLAR6 Register Field Descriptions

Bit

15-12

11

Field

Type

Reset

Description

RESERVED

TD Peak Polarity 1

R

0h

Reserved

R

0h

Polarity of the First peak discovered by the TDR mechanism on

Transmit Channel (TD).

10-6

5

RESERVED

R

0h

Reserved

Cross Detect on TD

Cross Reflections were detected on TD. Indicate on Short between

TD+ and TD-

4

3

RESERVED

R

0h

Reserved

2

1-0

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9.5.1.54 IO_CFG1 Register (Offset = 302h) [Reset = 0000h]

IO_CFG1 Register is shown in 表9-75.

Return to the 表9-20.

表9-75. IO_CFG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-14

MaC Impedance Control

R/W

0h

MAC Impedance Control: MAC interface impedance control sets the

series termination for the digital pins.

0h = Slow Mode

1h = Fast Mode

13

12-9

8

RESERVED

cfg_clkout25m_off

R/W

0h

Reserved

7

6

For ENHANCED Mode only : Configure Clockout or LED1

0h = CLKOUT25 available

1h = LED1_GPIO is available

5-0

RESERVED

R

0h

Reserved

110

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9.5.1.55 LED0_GPIO_CFG Register (Offset = 303h) [Reset = 0008h]

LED0_GPIO_CFG is shown in 表9-76.

Return to the 表9-20.

表9-76. LED0_GPIO_CFG Register Field Descriptions

Bit

15-6

5-3

Field

Type

Reset

Description

RESERVED

cfg_led0_clk_sel

R

0h

Reserved

R/W

1h

Selects one of the internal clock, for output on LED0. This is enabled

when cfg_led0_gpio_ctrl[2:0] = 001b. The possible configurations

are:

0h = Reserved

1h = Reserved

2h = Reserved

3h = Reserved

4h = Reserved

5h = PLL Clock out

6h = Recovered Clock

7h = Reserved

2-0

cfg_led0_gpio_ctrl

R

0h

GPIO Configuration for LED0:

0h = LED0

1h = Clock output selected by register field cfg_led0_clk_sel

2h = WoL

3h = 0

4h = Interrupt

5h = 0

6h = 0

7h = 1

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9.5.1.56 LED1_GPIO_CFG Register (Offset = 304h) [Reset = 0008h]

LED1_GPIO_CFG is shown in 表9-77.

Return to the 表9-20.

表9-77. LED1_GPIO_CFG Register Field Descriptions

Bit

15-6

5-3

Field

Type

Reset

Description

RESERVED

cfg_led1_clk_sel

R

0h

Reserved

R/W

1h

Selects one of the internal clock, for output on LED1. This is enabled

when cfg_led1_gpio_ctrl[2:0] = 001b. The possible configurations

are:

0h = Reserved

1h = Reserved

2h = Reserved

3h = Reserved

4h = Reserved

5h = PLL Clock out

6h = Recovered Clock

7h = Reserved

2-0

cfg_led1_gpio_ctrl

R/W

0h

GPIO Configuration for LED1:

0h = LED1 (default in BASIC mode)

1h = Reserved

2h = WoL

3h = Reserved

4h = Interrupt

5h = TX_ER

6h = CLKOUT25M (default in ENHANCED Mode, selectable by

Strap)

7h = Reserved

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9.5.1.57 LED2_GPIO_CFG Register (Offset = 305h) [Reset = 0008h]

LED2_GPIO_CFG is shown in 表9-78.

Return to the 表9-20.

表9-78. LED2_GPIO_CFG Register Field Descriptions

Bit

15-6

5-3

Field

Type

Reset

Description

Reserved

RESERVED

cfg_led2_gpio_ctrl

R

0h

R/W

1h

2-0

0h

GPIO Configuration for LED2:

0h = LED2

1h = Reserved

2h = WoL

3h = COL

4h = Interrupt

5h = COL

6h = COL

7h = High

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9.5.1.58 LED3_GPIO_CFG Register (Offset = 306h) [Reset = 0008h]

LED3_GPIO_CFG is shown in 表9-79.

Return to the 表9-20.

表9-79. LED3_GPIO_CFG Register Field Descriptions

Bit

15-6

5-3

Field

Type

Reset

Description

Reserved

RESERVED

cfg_led3_gpio_ctrl

R

0h

R/W

R

1h

2-0

0h

GPIO Configuration for LED3:

0h = LED3

1h = Reserved

2h = WoL

3h = CRS

4h = Interrupt

5h = CRS

6h = CRS

7h = High

114

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9.5.1.59 CLK_OUT_LED_STATUS register Register (Offset = 308h) [Reset = 0002h]

CLK_OUT_LED_STATUS register is shown in 表9-80.

Return to the 表9-20.

表9-80. CLK_OUT_LED_STATUS register Register Field Descriptions

Bit

15-1

0

Field

Type

Reset

Description

RESERVED

R/W

1h

Reserved

cfg_clkout_25m_off_status R

0h

This bit is applicable in ENHANCED mode only

0h = CLKOUT25 available

1h = LED1_GPIO is available

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9.5.1.60 VOD_CFG1 Register (Offset = 30Bh) [Reset = 3C00h]

VOD_CFG1 Register is shown in 表9-81.

Return to the 表9-20.

表9-81. VOD_CFG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-14

13-12

RESERVED

R

0h

Reserved

cfg_dac_minus_one_val_ R/W

mdix_5_to_4

3h

LD data for mlt3 encoded data of minus one in MDIX mode. The 6 bit

data is split into two fields - {cfg_dac_minus_one_val_mdix_5_to_4,

cfg_dac_minus_one_val_mdix_3_to_0}

28h = 150%

29h = 143.75%

2Ah = 137.50%

2Bh = 131.25%

2Ch = 125%

2Dh = 118.75%

2Eh = 112.50%

2Fh = 106.25%

30h = 100%

31h = 93.75%

32h = 87.50%

33h = 81.25%

34h = 75%

35h = 68.75%

36h = 62.50%

37h = 56.25%

38h = 50%

11-6

cfg_dac_minus_one_val_ R/W

mdi

30h

LD data for mlt3 encoded data of minus one in MDI mode.

28h = 150%

29h = 143.75%

2Ah = 137.50%

2Bh = 131.25%

2Ch = 125%

2Dh = 118.75%

2Eh = 112.50%

2Fh = 106.25%

30h = 100%

31h = 93.75%

32h = 87.50%

33h = 81.25%

34h = 75%

35h = 68.75%

36h = 62.50%

37h = 56.25%

38h = 50%

5-0

cfg_dac_zero_val

R/W

0h

LD data for mlt3 encoded data of zero

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9.5.1.61 VOD_CFG2 Register (Offset = 30Ch) [Reset = 0410h]

VOD_CFG2 Register is shown in 表9-82.

Return to the 表9-20.

表9-82. VOD_CFG2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

cfg_dac_minus_one_val_ R/W

mdix_3_to_0

0h

LD data for mlt3 encoded data of minus one in MDX mode. 6 bit data

is split into two fields - {cfg_dac_minus_one_val_mdix_5_to_4,

cfg_dac_minus_one_val_mdix_3_to_0}

28h = 150%

29h = 143.75%

2Ah = 137.50%

2Bh = 131.25%

2Ch = 125%

2Dh = 118.75%

2Eh = 112.50%

2Fh = 106.25%

30h = 100%

31h = 93.75%

32h = 87.50%

33h = 81.25%

34h = 75%

35h = 68.75%

36h = 62.50%

37h = 56.25%

38h = 50%

11-6

cfg_dac_plus_one_val_md R/W

ix

10h

LD data for mlt3 encoded data of plus one in MDIX mode

08h = 50%

09h = 56.25%

0Ah = 62.50%

0Bh = 68.75%

0Ch = 75%

0Dh = 81.25%

0Eh = 87.50%

0Fh = 93.75%

10h = 100%

11h = 106.25%

12h = 112.50%

13h = 118.75%

14h = 125%

15h = 131.25%

16h = 137.50%

17h = 143.75%

18h = 150%

5-0

cfg_dac_plus_one_val_md R/W

i

10h

LD data for mlt3 encoded data of plus one in MDI mode

08h = 50%

09h = 56.25%

0Ah = 62.50%

0Bh = 68.75%

0Ch = 75%

0Dh = 81.25%

0Eh = 87.50%

0Fh = 93.75%

10h = 100%

11h = 106.25%

12h = 112.50%

13h = 118.75%

14h = 125%

15h = 131.25%

16h = 137.50%

17h = 143.75%

18h = 150%

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9.5.1.62 VOD_CFG3 Register (Offset = 30Eh) [Reset = 0000h]

VOD_CFG3 Register is shown in 表9-83.

Return to the 表9-20.

表9-83. VOD_CFG3 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

ld_term_mdi_10M_reg

R/W

0h

10M mode, MDI Termination Value Register

0h = 122

1h = 119

2h = 116

3h = 113

4h = 110

5h = 107

6h = 105

7h = 102

8h = 100

9h = 98

Ah = 96

Bh = 94

Ch = 92

Dh = 90

Eh = 88

Fh = 86

11

ld_term_mdi_10M_en

ld_term_mdix_10M_reg

R/W

0h

10M mode, MDI Termination Value Register Enable

0h = Disable

1h = Enable

10-7

10M mode, MDIX Termination Value Register

0h = 122

1h = 119

2h = 116

3h = 113

4h = 110

5h = 107

6h = 105

7h = 102

8h = 100

9h = 98

Ah = 96

Bh = 94

Ch = 92

Dh = 90

Eh = 88

Fh = 86

6

ld_term_mdix_10M_en

R/W

0h

10M mode, MDIX Termination Value Register Enable

0h = Disable

1h = Enable

5-2

1-0

RESERVED

R/W

R

0h

Reserved

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9.5.1.63 ANA_LD_PROG_SL Register (Offset = 404h) [Reset = 0080h]

ANA_LD_PROG_SL Register is shown in 表9-84.

Return to the 表9-20.

表9-84. ANA_LD_PROG_SL Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

RESERVED

R/W

80h

Reserved

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9.5.1.64 ANA_RX10BT_CTRL Register (Offset = 40Dh) [Reset = 0000h]

ANA_RX10BT_CTRL Register is shown in 表9-85.

Return to the 表9-20.

表9-85. ANA_RX10BT_CTRL Register Field Descriptions

Bit

15-5

4-0

Field

Type

R/W

Reset

Description

RESERVED

rx10bt_comp_sl

0h

Reserved

0h

10B-T current Gain, common for both POS and NEG, Starting from

200mV to 575mV, step size of 25mV

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9.5.1.65 GENCFG Register (Offset = 456h) [Reset = 0008h]

GENCFG Register is shown in 表9-86.

Return to the 表9-20.

表9-86. GENCFG Register Field Descriptions

Bit

15-4

3

Field

Type

R/W

Reset

Description

RESERVED

Min IPG Enable

0h

Reserved

1h

Min IPG Enable:

0h = Minimal IPG set to 200 ns

1h = Enable Minimum Interpacket Gap (IPG is set to 120ns instead

of 200ns)

2-0

RESERVED

R/W

0h

Reserved

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9.5.1.66 LEDCFG Register (Offset = 460h) [Reset = 5665h]

LEDCFG Register is shown in 表9-87.

Return to the 表9-20.

表9-87. LEDCFG Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

LED1 Control

R/W

5h

LED1 Control: Selects the source for LED1.

0h = LINK OK

1h = RX/TX Activity

2h = TX Activity

3h = RX Activity

4h = Collision

5h = Speed, High for 100BASE-TX

6h = Speed, High for 10BASE-T

7h = Full-Duplex

8h = LINK OK / BLINK on TX/RX Activity

9h = Active Stretch Signal

Ah = MII LINK (100BT+FD)

Bh = LPI Mode (Energy Efficient Ethernet)

Ch = TX/RX MII Error

Dh = Link Lost (remains on until register 0x0001 is read)

Eh = Blink for PRBS error (remains ON for single error, remains until

counter is cleared)

Fh = Reserved

11-8

LED2 Control

LED3 Control

RESERVED

R/W

6h

5h

LED2 Control: Selects the source for LED2.

0h = LINK OK

1h = RX/TX Activity

2h = TX Activity

3h = RX Activity

4h = Collision

5h = Speed, High for 100BASE-TX

6h = Speed, High for 10BASE-T

7h = Full-Duplex

8h = LINK OK / BLINK on TX/RX Activity

9h = Active Stretch Signal

Ah = MII LINK (100BT+FD)

Bh = LPI Mode (Energy Efficient Ethernet)

Ch = TX/RX MII Error

Dh = Link Lost (remains on until register 0x0001 is read)

Eh = Blink for PRBS error (remains ON for single error, remains until

counter is cleared)

Fh = Reserved

7-4

LED3 Control:Selects the source for LED3.

0h = LINK OK

1h = RX/TX Activity

2h = TX Activity

3h = RX Activity

4h = Collision

5h = Speed, High for 100BASE-TX

6h = Speed, High for 10BASE-T

7h = Full-Duplex

8h = LINK OK / BLINK on TX/RX Activity

9h = Active Stretch Signal

Ah = MII LINK (100BT+FD)

Bh = LPI Mode (Energy Efficient Ethernet)

Ch = TX/RX MII Error

Dh = Link Lost (remains on until register 0x0001 is read)

Eh = Blink for PRBS error (remains ON for single error, remains until

counter is cleared)

Fh = Reserved

3-0

Reserved

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9.5.1.67 IOCTRL Register (Offset = 461h) [Reset = 0010h]

IOCTRL Register is shown in 表9-88.

Return to the 表9-20.

表9-88. IOCTRL Register Field Descriptions

Bit

15

Field

Type

R/W

Reset

Description

Reserved

RESERVED

MAC Impedance Control

0h

14

0h

13-12

11

0h

10-7

6-5

4-0

0h

10h

Controls the Slew Rate of the IO. Only LSB is used.

10h = Fast

11h = Slow

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9.5.1.68 SOR1 Register (Offset = 467h) [Reset = 0000h]

SOR1 Register is shown in 表9-89.

Return to the 表9-20.

表9-89. SOR1 Register Field Descriptions

Bit

15

14

13

12

11

10

Field

Type

Reset

Description

Reserved

RESERVED

Strap10

R

0h

R

0h

R

0h

R

0h

R

0h

Strap on pin#18

0h = active low,

1h = active high

9

8

7

6

5

4

3

2

1

0

Strap9

Strap8

Strap7

Strap6

Strap5

Strap4

Strap3

Strap2

Strap1

Strap0

0h

Strap on pin#15

0h = active low,

1h = active high

Strap on pin#14

0h = active low,

1h = active high

Strap on pin#13

0h = active low,

1h = active high

Strap on pin#20

0h = active low,

1h = active high

Strap on pin#22

0h = active low,

1h = active high

Strap on pin#28

0h = active low,

1h = active high

Strap on pin#29

0h = active low,

1h = active high

Strap on pin#30

0h = active low,

1h = active high

Strap on pin#31

0h = active low,

1h = active high

Strap on pin#16

0h = active low,

1h = active high

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9.5.1.69 SOR2 Register (Offset = 468h) [Reset = 0287h]

SOR2 Register is shown in 表9-90.

Return to the 表9-20.

表9-90. SOR2 Register Field Descriptions

Bit

15

14

Field

Type

Reset

Description

RESERVED

XMII_ISOLATE_EN

R

0h

Reserved

0h

Applicable in BASIC Mode. Controls the MII Isolation bit field in

register BMCR[10]

0h = No Isolation

1h = MAC pins Isolated

13

12

RESERVED

R

0h

Reserved

CRS_DV_vs_RX_DV

RMII mode RX_DV pin as CRS_DV or RX_DV

0h = RMI CRS_DV

1h = RMII RX_DV

11

10

9

RESERVED

CFG_FLD_EN

R

0h

1h

0h

Reserved

8

Configures Fast Link Down Feature. This affects register CR3[3:0].

0h = CR3[10,3:0] is set to 5b00000

1h = CR3[10,3:0] is set to 5b11010

7

CFG_AMDIX

1h

AMDIX Enable. This captures the inversion of AMDIX_DIS strap

0h = AMDIX Disable

1h = AMDIX Enable

6

5

4

RESERVED

R

0h

Reserved

RESERVED

CFG_RMII_MODE

MII/RMII mode Selection

0h = MII

1h = RMII

3

CFG_XI_50_SLAVE

0h

RMII Master / Slave mode Selection

0h = RMII Master Mode

1h = RMII Slave Mode

2

1

0

CFG_AN_1

CFG_AN_0

CFG_AN_EN

1h

This is to derive ANAR register bit [8:5]

ANEG Enable. This captures the inversion of ANEG_DIS

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9.5.1.70 LEDCFG2 Register (Offset = 469h) [Reset = 0440h]

LEDCFG2 Register is shown in 表9-91.

Return to the 表9-20.

表9-91. LEDCFG2 Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

15-11

RESERVED

LED2_polarity

R

0h

10

9

R/W

R

1h

0h

8

0h

7

0h

6

R/W,STRAP 1h

led 2 polarity

0h = active low,

1h = active high

5

4

LED2_drv_val

LED2_drv_en

R/W

0h

led 2 drive value

led 2 drive enable

0h = Normal operation

1h = drive LED polarity,

3

2

RESERVED

R

0h

Reserved

LED1_polarity

R/W,STRAP 0h

led 1 polarity

0h = active low,

1h = active high

1

0

LED1_drv_val

LED1_drv_en

R/W

0h

led1 drive value

led 1 drive enable

0h = Normal operation

1h = drive LED polarity,

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9.5.1.71 RXFCFG1 Register (Offset = 4A0h) [Reset = 1081h]

RXFCFG1 Register is shown in 表9-92.

Return to the 表9-20.

表9-92. RXFCFG1 Register Field Descriptions

Bit

15-14

13

Field

Type

Reset

Description

Reserved

RESERVED

CRC Gate

R

0h

R

0h

12

R/W

1h

CRC Gate: If Magic Packet has Bad CRC there will be no indication

(status, interrupt, GPIO) when enabled.

0h = Bad CRC does not gate Magic Packet or Pattern Indications

1h = Bad CRC gates Magic Packet and Pattern Indications

11

WoL Level Change

Indication Clear

W0C

R/W

0h

WoL Level Change Indication Clear: If WoL Indication is set for Level

change mode, this bit clears the level upon a write.

0h = Clear

10-9

WoL Pulse Indication

Select

WoL Pulse Indication Select: Only valid when WoL Indication is set

for Pulse mode.

0h = 8 clock cycles (of 125MHz clock)

1h = 16 clock cycles

2h = 32 clock cycles

3h = 64 clock cycles

8

7

WoL Indication Select

WoL Enable

R/W

0h

1h

WoL Indication Select:

0h = Pulse mode

1h = Level change mode

WoL Enable:

0h = normal operation

1h = Enable Wake-on-LAN (WoL)

6

5

4

3

2

1

0

Bit Mask Flag

Secure-ON Enable

RESERVED

R/W

R

0h

Bit Mask Flag

Enable Secure-ON password for Magic Packets

Reserved

RESERVED

R

Reserved

RESERVED

R

Reserved

RESERVED

R

Reserved

WoL Magic Packet Enable R/W,STRAP 1h

Enable Interrupt upon reception of Magic Packet

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9.5.1.72 RXFS Register (Offset = 4A1h) [Reset = 1000h]

RXFS Register is shown in 表9-93.

Return to the 表9-20.

表9-93. RXFS Register Field Descriptions

Bit

15-13

12

Field

Type

Reset

Description

RESERVED

WoL Interrupt Source

R

0h

Reserved

R/W

1h

WoL Interrupt Source: Source of Interrupt for bit [1] of register

0x0013. When enabling WoL, this bit is automatically set to WoL

Interrupt.

0h = Data Polarity Interrupt

1h = WoL Interrupt

11-8

7

RESERVED

SFD Error

R

H

0h

Reserved

SFD Error:

0h = No SFD error

1h = Packet with SFD error (without the SFD byte indicated in bit [13]

register 0x04A0)

6

5

Bad CRC

H

0h

Bad CRC:

0h = No bad CRC received

1h = Bad CRC was received

Secure-On Hack Flag

Secure-ON Hack Flag:

0h = Valid Secure-ON Password

1h = Invalid Password detected in Magic Packet

4

3

2

1

0

RESERVED

H

0h

Reserved

RESERVED

Reserved

RESERVED

Reserved

RESERVED

Reserved

WoL Magic Packet Status

WoL Magic Packet Status:

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9.5.1.73 RXFPMD1 Register (Offset = 4A2h) [Reset = 0000h]

RXFPMD1 Register is shown in 表9-94.

Return to the 表9-20.

表9-94. RXFPMD1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-8

MAC Destination Address R/W

Byte 4

0h

Perfect Match Data: Configured for MAC Destination Address

7-0

MAC Destination Address R/W

Byte 5 (MSB)

0h

Perfect Match Data: Configured for MAC Destination Address

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9.5.1.74 RXFPMD2 Register (Offset = 4A3h) [Reset = 0000h]

RXFPMD2 Register is shown in 表9-95.

Return to the 表9-20.

表9-95. RXFPMD2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-8

MAC Destination Address R/W

Byte 2

0h

Perfect Match Data: Configured for MAC Destination Address

7-0

MAC Destination Address R/W

Byte 3

0h

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9.5.1.75 RXFPMD3 Register (Offset = 4A4h) [Reset = 0000h]

RXFPMD3 Register is shown in 表9-96.

Return to the 表9-20.

表9-96. RXFPMD3 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-8

MAC Destination Address R/W

Byte 0

0h

Perfect Match Data: Configured for MAC Destination Address

7-0

MAC Destination Address R/W

Byte 1

0h

Perfect Match Data: Configured for MAC Destination Address

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9.5.1.76 RXFSOP1 Register (Offset = 4A5h) [Reset = 0000h]

RXFSOP1 Register is shown in 表9-97.

Return to the 表9-20.

May need to be added in 825 also after testing

表9-97. RXFSOP1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-8

Secure-ON Password

Byte 1

R/W

0h

Secure-ON Password Select: Secure-ON password for Magic

Packets

7-0

Secure-ON Password

Byte 0

R/W

0h

Secure-ON Password Select: Secure-ON password for Magic

Packets

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9.5.1.77 RXFSOP2 Register (Offset = 4A6h) [Reset = 0000h]

RXFSOP2 Register is shown in 表9-98.

Return to the 表9-20.

May need to be added in 825 also after testing

表9-98. RXFSOP2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-8

Secure-ON Password

Byte 3

R/W

0h

Secure-ON Password Select: Secure-ON password for Magic

Packets

7-0

Secure-ON Password

Byte 2

R/W

0h

Secure-ON Password Select: Secure-ON password for Magic

Packets

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9.5.1.78 RXFSOP3 Register (Offset = 4A7h) [Reset = 0000h]

RXFSOP3 Register is shown in 表9-99.

Return to the 表9-20.

May need to be added in 825 also after testing

表9-99. RXFSOP3 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-8

Secure-ON Password

Byte 5

R/W

0h

Secure-ON Password Select: Secure-ON password for Magic

Packets

7-0

Secure-ON Password

Byte 4

R/W

0h

Secure-ON Password Select: Secure-ON password for Magic

Packets

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10 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

10.1 Application Information

The DP83826 is a single-port 10/100-Mbps Ethernet PHY. It supports connections to an Ethernet MAC through

MII and RMII. Connections to the Ethernet media are made via the IEEE 802.3 defined media-dependent

interface.

When using the device for Ethernet applications, it is necessary to meet certain requirements for normal

operation. The following subsections are intended to assist in appropriate component selection and required

circuit connections.

备注

For a step-by-step approach to using the DP83826 BASIC mode in existing systems that use a

common standard Ethernet pinout Refer to SNLA338

10.2 Typical Applications

Following figure shows a typical application for the DP83826.

VDDA3V3

VDDIO

10BASE-Te

100BASE-TX

DP83826

MII/RMII

MAC

10/100 Mbps

Ethernet PHY

RJ-45

25-MHz / 50-MHz

Clock Source

Status

LEDs

图10-1. Typical DP83826 Application

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10.2.1 Twisted-Pair Interface (TPI) Network Circuit

图 10-2 shows the recommended twisted-pair interface network circuit for 10 Mbps or 100 Mbps. Variations with

PCB and component characteristics require that the application be tested to verify that the circuit meets the

requirements of the intended application.

TD+

1:1

PHY

TD+

TD-

75

2 nF

RJ 45

RD+

RD-

75

2 nF

0.01μF

RD-

图10-2. TPI Network Circuit

10.2.2 Transformer Recommendations

The following magnetics have been tested using the DP83826.

表10-1. Recommended Transformers

MANUFACTURER

PART NUMBER

HX1198FNL

HX1188NL

Pulse electronics

HX1188FNL

表10-2. Transformer Electrical Specifications

PARAMETER

TEST CONDITIONS

TYP

1:1

UNIT

-

Turn ratio

±2%

1 - 100 MHz

1 - 30 MHz

30 - 60 MHz

60 - 80 MHz

1 - 50 MHz

50 - 150 MHz

30 MHz

dB

Insertion loss

–1

–16

–12

–10

–30

–20

–35

–30

Return loss

Differential to common rejection ratio

Crosstalk

60 MHz

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表10-2. Transformer Electrical Specifications (continued)

PARAMETER

TEST CONDITIONS

TYP

UNIT

Isolation

HPOT

1500

Vrms

10.2.3 Capacitive DC Blocking

In order to meet the operational requirements of transformer-less network applications, the following design

showed in the schematic in 图10-3 should be used.

DC Blocking

Capacitors

TD+

PHY

TD+

33 nF

TD-

33 nF

RJ 45

RD+

RD-

33 nF

RD-

图10-3. Transformerless DC Blocking Configuration

10.2.4 Design Requirements

The design requirements for the DP83826 in TPI operation (100BASE-TX or 10BASE-Te) are:

• VDDA3V3 supply = 3.3 V

• VDDIO supply = 3.3 V or 1.8 V

• Reference clock input = 25 MHz or 50 MHz (RMII slave)

10.2.4.1 Clock Requirements

The DP83826 supports an external CMOS-level oscillator source or an internal oscillator with an external crystal.

10.2.4.1.1 Oscillator

If an external clock source is used, tie XI to the clock source, and leave XO floating. The amplitude of the

oscillator clock must be a nominal voltage of VDDIO.

10.2.4.1.2 Crystal

The use of a 25-MHz, parallel resonant, 20-pF load crystal is recommended if operating with a crystal. See 图

10-4 for a typical connection diagram for a crystal resonator circuit. The load capacitor values vary with the

crystal vendors; check with the vendor for the recommended loads. Refer to the application report Selection and

specification of crystals for Texas Instruments ethernet physical layer transceivers for more details.

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XI

XO

R1

Crystal

C_L1

C_L2

图10-4. Crystal Oscillator Circuit

表10-3. 25-MHz Crystal Specification

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Frequency

25

MHz

Including operational temperature, aging and

other factors

Frequency tolerance

100

ppm

–100

Load capacitance

ESR

15

40

50

pF

Ω

10.2.5 Detailed Design Procedure

10.2.5.1 MII Layout Guidelines

1. MII signals are single-ended signals

2. Traces should be routed with 50-Ωimpedance to ground

3. Keep trace lengths as short as possible, less than two inches (~5 cm) is recommended and less than six

inches (~15 cm) maximum

10.2.5.2 RMII Layout Guidelines

• RMII signals are single-ended signals

• Traces should be routed with 50-Ωimpedance to ground

• Keep trace lengths as short as possible, less than two inches (~5 cm) is recommended and less than six

inches (~15 cm) maximum

10.2.5.3 MDI Layout Guidelines

• MDI signals are differential.

• Route traces with 50-Ωimpedance to ground and 100-Ωdifferential controlled impedance.

• Route MDI traces to the transformer on the same layer.

• Use a metal shielded RJ-45 connector and electrically connect the shield to chassis ground.

• Avoid supplies and ground beneath the magnetics.

• Do not overlap the circuit ground and chassis ground planes. Keep chassis ground and circuit ground

isolated by turning chassis ground into an isolated island by leaving a gap between the planes. Connecting a

1206 (size) capacitor between chassis ground and circuit ground is recommended to avoid floating metal.

Capacitors less than 805 (size) can create an arching path for ESD due to a small air-gap.

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10.2.6 Application Curves

图10-5 depicts the DP83826 output pin drive characteristics for I/O supply voltages of 1.8 V and 3.3 V.

图10-5. DP83826 Output Pin Drive Characteristics

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11 Power Supply Recommendations

The DP83826 is capable of operating with a 3.3-V or 1.8-V I/O supply voltage along with an analog supply of 3.3

V. If a 3.3-V I/O supply voltage is desired, the DP83826 can also operate on a single 3.3-V power rail. An internal

LDO generates all the power rails required for the device to operate. The single voltage supply simplifies the

design requirements, decreases the BOM cost and the overall solution size, making the DP83826 a viable

solution in a wide range of applications. The recommended power supply de-coupling network is shown below:

3.3-V or 1.8-V

Supply

Ferrite Bead for

improved EMC

(Optional)

VDDIO

100 nF

10 nF

1 ꢀF

10 ꢀF

Ferrite Bead for

improved EMC

(Optional)

3.3-V Supply

AVDD3V3

10 ꢀF 1 ꢀF

100 nF 10 nF

图11-1. Power Supply Decoupling Recommendation

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12 Layout

12.1 Layout Guidelines

Please see DP83826EVM.

12.1.1 Signal Traces

PCB traces are lossy and long traces can degrade signal quality. Keep all traces as short as possible. Unless

mentioned otherwise, all signal traces must be 50-Ωsingle-ended impedance. Differential traces must be 100-Ω

differential. Take care to ensure impedance is controlled throughout. Impedance discontinuities causes

reflections leading to emissions and signal integrity issues. Stubs should be avoided on all signal traces,

especially differential signal pairs.

图12-1. Differential Signal Traces

Within the differential pairs, trace lengths must be run parallel to each other and be matched in length. Matched

lengths minimize delay differences, avoiding an increase in common mode noise and emissions. Length

matching is also important for MAC interface connections. All MII and RMII transmit signal traces should be

length matched to each other and all MII and RMII receive signal traces should be length matched to each other.

Ideally, there should be no crossover or vias on signal path traces. Vias present impedance discontinuities and

should be minimized when possible. Route trace pairs on the same layer. Signals on different layers should not

cross each other without at least one return path plane between them. Differential pairs should always have a

constant coupling distance between them. For convenience and efficiency, TI recommends routing critical

signals first (that is, MDI differential pairs, reference clock, and MAC IF traces).

12.1.2 Return Path

A general best practice is to have a solid return path beneath all MDI signal traces. This return path can be a

continuous ground or DC power plane. Reducing the width of the return path can potentially affect the

impedance of the signal trace. This effect is more prominent when the width of the return path is comparable to

the width of the signal trace. Avoid breaks in return path between the signal traces at all cost. A signal crossing a

split plane may cause unpredictable return path currents and could impact signal quality and result in emissions

issues.

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图12-2. Differential Signal Pair and Plane Crossing

12.1.3 Transformer Layout

There must be no metal layer running beneath the transformer. Transformers can inject noise into metal beneath

them, which can affect the performance of the system. See 图10-2.

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12.1.4 Metal Pour

All metal pours that are not signals or power must be tied to ground. There must be no floating metal in the

system, and there must be no metal between differential traces.

12.1.5 PCB Layer Stacking

To meet signal integrity and performance requirements, a minimum four-layer PCB is recommended. However, a

six-layer PCB should be used when possible.

图12-3. Recommended Layer Stack-Up

12.1.5.1 Layout Example

See the DP83826EVM for more information regarding layout.

Transfo

rmer

( if not

integrat

ed in

Plan Coupling

Components

RJ-45

White

PHY

RJ-45)

System Power/ Ground Planes

Chasis Ground Plane

GND

图12-4. Layout Example

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13 Device and Documentation Support

13.1 Related Documentation

For related documentation see the following:

Solving Cable Faults Challenges with TI Ethernet PHYs

Selection and specification of crystals for Texas Instruments ethernet physical layer transceivers

Chinese and English Definitions of Acronyms Related to Ethernet Products

13.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

13.3 Support Resources

13.4 Trademarks

Magic Packet^™is a trademark of Advanced Micro Devices, Inc..

EtherCAT^®is a registered trademark of Beckhoff Automation GmbH, Germany.

所有商标均为其各自所有者的财产。

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

RHB 32

5 x 5, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224745/A

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PACKAGE OUTLINE

VQFN - 1 mm max height

RHB0032M

PLASTIC QUAD FLATPACK-NO LEAD

A

5.1

4.9

B

5.1

4.9

PIN 1 INDEX AREA

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

(0.2) TYP

ꢀꢀꢀꢁꢂꢃꢄꢂꢃ

9

16

28X 0.5

8

17

SYMM

33

2X

3.5

1

24

0.3

0.2

32X

32

25

PIN 1 ID

(OPTIONAL)

SYMM

0.1

0.05

C A B

C

0.5

0.3

32X

4223725/A 08/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RHB0032M

PLASTIC QUAD FLATPACK-NO LEAD

(4.8)

2.1)

(

32

25

32X (0.6)

32X (0.25)

1

24

28X (0.5)

33

SYMM

(4.8)

2X

(0.8)

ꢅꢄꢂꢁꢆ

VIA TYP

8

17

(R0.05) TYP

9

16

2X (0.8)

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

EXPOSED

METAL

OPENING

EXPOSED

METAL UNDER

SOLDER MASK

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223725/A 08/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RHB0032M

PLASTIC QUAD FLATPACK-NO LEAD

(4.8)

4X ( 0.94)

32

25

32X (0.6)

32X (0.25)

1

24

28X (0.5)

33

SYMM

(4.8)

2X

(0.57)

METAL

TYP

8

17

(R0.05) TYP

9

16

2X (0.57)

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

80% PRINTED COVERAGE BY AREA

SCALE: 15X

4223725/A 08/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DP83826E
厂家：	TEXAS INSTRUMENTS
描述：	具有 MII 接口和 ENHANCED 模式的低延迟 10/100Mbps 以太网 PHY 以太网局域网（LAN）标准
文件：	总154页 (文件大小：3616K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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