DP83869HMRGZR_技术文档

DP83869HM

ZHCSIS3B –SEPTEMBER 2018 –REVISED DECEMBER 2022

配备铜缆和光纤接口的DP83869HM 高抗扰性10/100/1000 以太网物理层收发器

• 电网基础设施

• 电机和运动控制

1 特性

• 测试和测量

• 楼宇自动化

• 实时工业以太网应用，如ProfiNET®

• 多种工作模式

– 支持媒介：铜缆和光纤

– 可在铜缆和光纤之间进行切换

– 在RGMII 与SGMII 之间建立桥接

• 可用的最高环境温度为125°C

• 超过了8kV IEC61000-4-2 ESD

• 低功耗

3 说明

DP83869HM 器件是一款集成了 PMD 子层的稳健耐用

型全功能千兆位物理层 (PHY) 收发器，支持 10BASE-

Te、100BASE-TX 和 1000BASE-T 以太网协议。

DP83869 还支持 1000BASE-X 和 100BASE-FX 光纤

协议。DP83869HM 经优化可提供 ESD 保护，超过了

8kV IEC 61000-4-2 标准（直接接触）。该器件通过简

化 GMII (RGMII) 和 SGMII 连接到 MAC 层。在 100M

模式中，该器件允许设计人员使用 MII 以实现低延迟。

RGMII/MII 上的可编程集成终端阻抗有助于降低系统

BOM。

– 对于1000Base-X，< 150mW

– 对于1000Base-T，< 500mW

• 低RGMII 延迟

– 对于1000Base-T，总延迟≤384ns

– 对于100Base-TX，总延迟≤361ns

• 符合时间敏感网络(TSN) 标准

• 适用于SyncE 的恢复时钟输出

• 可选同步时钟输出：25 MHz 和125 MHz

• SFF-8431 V4.1、1000BASE-X 和100BASE-FX 兼

容

DP83869HM 支持非托管模式下的媒介转换。在此模式

下， DP83869HM 可以运行 1000BASE-X 至

1000BASE-T 和 100BASE-FX 至 100BASE-TX 转

换。

• 通过SFD 支持IEEE1588

• 支持局域网唤醒

• 可配置的IO 电压：1.8V、2.5V 和3.3V

• SGMII、RGMII、MII MAC 接口

• 巨型帧支持1000M 和100M 速度

• 电缆诊断

DP83869HM 还支持从 RGMII 到 SGMII 和从 SGMII

到RGMII 的桥接转换。DP83869HM 符合TSN 标准，

可实现低延迟。

器件信息

封装⁽¹⁾

– TDR

– BIST

• 可编程RGMII 终端阻抗

• 集成MDI 终端电阻器

• 快速链路丢弃模式

封装尺寸（标称值）

7.00mm × 7.00mm

器件型号

DP83869HM

VQFN (48)

DP83867E/IS/CS

DP83867IR/CR

VQFN(48)

• 符合IEEE 802.3 1000Base-T、100Base-TX、

10Base-Te、1000Base-X、100Base-FX 标准

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 工业工厂自动化

10BASE-Te

100BASE-TX

1000BASE-T

SGMII (Copper Only)

RGMII

MII

DP83869

10/100/1000 Mbps

Ethernet Physical Layer

Connector/

Fiber

Transceiver

Ethernet MAC

Isolation

100BASE-FX

1000BASE-X

25 MHz

Crystal or

Oscillator

Status

LEDs

标准以太网系统方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNLS614

DP83869HM

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ZHCSIS3B –SEPTEMBER 2018 –REVISED DECEMBER 2022

Table of Contents

9.5 Programming............................................................ 46

9.6 Register Maps...........................................................52

10 Application and Implementation................................91

10.1 Application Information........................................... 91

10.2 Typical Applications................................................ 91

11 Power Supply Recommendations..............................96

11.1 Two-Supply Configuration.......................................96

11.2 Three-Supply Configuration.................................... 98

12 Layout.........................................................................100

12.1 Layout Guidelines................................................. 100

12.2 Layout Example.................................................... 103

13 Device and Documentation Support........................104

13.1 Documentation Support........................................ 104

13.2 Receiving Notification of Documentation Updates104

13.3 支持资源................................................................104

13.4 Trademarks...........................................................104

13.5 Electrostatic Discharge Caution............................104

13.6 术语表................................................................... 104

14 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 说明（续）.........................................................................3

6 Device Comparison Table...............................................3

7 Pin Configuration and Functions...................................4

8 Specifications................................................................ 11

8.1 Absolute Maximum Ratings ..................................... 11

8.2 ESD Ratings..............................................................11

8.3 Recommended Operating Conditions.......................11

8.4 Thermal Information..................................................12

8.5 Electrical Characteristics ..........................................12

8.6 Timing Requirements ...............................................17

8.7 Timing Diagrams ......................................................19

8.8 Typical Characteristics..............................................22

9 Detailed Description......................................................23

9.1 Overview...................................................................23

9.2 Functional Block Diagram.........................................24

9.3 Feature Description...................................................25

9.4 Device Functional Modes..........................................34

Information.................................................................. 104

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (September 2018) to Revision B (December 2022)

Page

• 更改了电流规格的光纤合规性.............................................................................................................................1

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• Deleted leading 0 from all register, read, and write statements .......................................................................26

• Deleted 1000Base-X fiber application clarification, bug has been fixed ..........................................................34

• Changed bridge mode image and description to clarify TX and RX pin behavior............................................ 39

• Changed description of Media Converter mode to support Unmanaged Media Converter mode in response to

bug fix .............................................................................................................................................................. 39

• Changed register read and writes to correct values with comments ............................................................... 40

• Changed number of PHYs and size of PHY address to correct values............................................................41

• Added clarification for Auto-Negotiation setting................................................................................................49

• Changed strapping modes in the figure and description to correct values.......................................................49

• Changed 表10-1 to clarify Frequency Tolerance ............................................................................................ 92

• Changed 表10-2 to clarify Frequency Tolerance ............................................................................................ 93

• Changed the two-supply config figure to the correct number of pins for VDDIO and VDD1P1, also changed

the pin name from VDDA1P1 to VDD1P1........................................................................................................ 96

• Changed the three-supply config figure to the correct number of pins for VDDIO and VDD1P1, also changed

the pin name from VDDA1P1 to VDD1P1........................................................................................................ 98

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5 说明（续）

DP83869HM 还可为 MAC 生成 IEEE 1588 同步帧检测指示。这样可以减少时间同步中的抖动，并帮助系统解决

数据包传输和接收中的不对称延迟。

标准以太网系统方框图显示在第一页上。设计人员还可以在媒体转换器模式、RGMII 至 SGMII 桥接应用以及

SGMII-RGMII 桥接应用中使用DP83869。

1000BASE-T

1000BASE-X

100BASE-TX

100BASE-FX

DP83869

10/100/1000 Mbps

Ethernet Physical Layer

Ethernet

PHY

Cable

Connector

Ethernet

PHY

Fiber

Transceiver

25 MHz

Crystal or

Oscillator

Status

LEDs

图5-1. 媒介转换器系统方框图

RGMII

SGMII

DP83869

10/100/1000 Mbps

Ethernet Physical Layer

Ethernet

PHY

Ethernet MAC

25 MHz

Crystal or

Oscillator

Status

LEDs

图5-2. RGMII-SGMII 桥接系统方框图

SGMII

RGMII

DP83869

10/100/1000 Mbps

Ethernet Physical Layer

Ethernet

PHY

Ethernet MAC

25 MHz

Status

Crystal or

LEDs

Oscillator

图5-3. SGMII-RGMII 桥接系统方框图

6 Device Comparison Table

DEVICE

BRIDGE MODE

TEMPERATURE

-40°C to +125°C

TEMPERATURE GRADE

DP83869HM

Yes

High Temp

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7 Pin Configuration and Functions

48 47 46 45 44 43 42 41 40 39 38 37

RX_D3

1

2

36

35

34

33

32

31

30

29

28

27

26

25

TD_P_A

TD_M_A

VDDA2P5

TD_P_B

TD_M_B

RX_D2

RX_D1

3

RX_D0

4

DP83869

RX_CLK

VDD1P1

VDDIO

5

TOP VIEW

(not to scale)

6

VDD1P1

TD_P_C

48-pin QFN Package

7

TD_M_C

VDDA2P5

TD_P_D

DAP = GND

GTX_CLK / TX_CLK

TX_D0

8

9

TX_D1

10

11

TX_D2

TD_M_D

TX_D3

RBIAS 12

13 14 15 16 17 18 19 20 21 22 23 24

图7-1. RGZ Package (48-Pin VQFN) Top View

表7-1. RGZ Package (VQFN) Pin Functions

NAME

I/O

TYPE

DESCRIPTION

NO.

1

TD_P_A

TD_M_A

VDDA2P5

TD_P_B

TD_M_B

VDD1P1

TD_P_C

TD_M_C

VDDA2P5

TD_P_D

TD_M_D

I/O

I

Analog

Power

Analog

Power

Analog

Power

Analog

Differential Transmit and Receive Signals

2

3

2.5-V Analog Supply (+/-5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND.

Differential Transmit and Receive Signals

4

I/O

I

5

Differential Transmit and Receive Signals

6

1.1-V Digital Supply (+/-10%). Each pin requires a 1-µF and 0.1-µF capacitor to GND.

Differential Transmit and Receive Signals

7

I/O

I

8

Differential Transmit and Receive Signals

9

2.5-V Analog Supply (+/-5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND.

Differential Transmit and Receive Signals

10

11

I/O

Differential Transmit and Receive Signals

Bias Resistor Connection. An 11 kΩ+/-1% resistor should be connected from RBIAS to

GND.

12

RBIAS

I

—

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表7-1. RGZ Package (VQFN) Pin Functions (continued)

I/O

TYPE

DESCRIPTION

NO.

NAME

No external supply is required for this pin in two-supply mode. When unused, no

connections should be made to these pins. In three-supply mode, an external

1.8V(+/-5%) supply can be connected to these pins. When using an external supply,

each pin requires a 1-µF and 0.1-µF capacitor to GND.

13

VDDA1P8_1

I

Power

Differential SGMII or Fiber Data Output: This signal carries data from the PHY to the

MAC, fiber transceiver, or link partner in SGMII and fiber modes. This pin should be AC-

coupled to the distant device through a 0.1-µF capacitor. This pin provides LVDS

signals, additional components may be required for the optical transceiver.

14

15

16

SON

SOP

SIP

O

I

Analog

Differential SGMII or Fiber Data Output: This signal carries data from the PHY to the

MAC, fiber transceiver, or link partner in SGMII and fiber modes. This pin should be AC-

coupled to the distant device through a 0.1-µF capacitor. This pin provides LVDS

signals, additional components may be required for the optical transceiver

Differential SGMII or Fiber Data Input: This signal carries data from the MAC, fiber

transceiver, or link partner, to the PHY in SGMII and fiber modes. This pin should be

AC-coupled to the distant device through a 0.1-µF capacitor. This pin accepts LVDS

signals, additional components may be required for the optical transceiver

Differential SGMII or Fiber Data Input: This signal carries data from the MAC, fiber

transceiver, or link partner, to the PHY in SGMII and fiber modes. This pin should be

AC-coupled to the distant device through a 0.1-µF capacitor. This pin accepts LVDS

signals, additional components may be required for the optical transceiver

17

18

SIN

I

Analog

Power

I/O Power: 1.8 V (±5%), 2.5 V (±5%) or 3.3 V (±5%). Each pin requires a 1-µF and 0.1-

µF capacitor to GND

VDDIO

CRYSTAL OSCILLATOR OUTPUT: Second terminal for 25 MHz crystal. Must be left

floating if a clock oscillator is used.

19

20

XO

XI

O

I

Clock

CRYSTAL OSCILLATOR INPUT: 25 MHz oscillator or crystal input.

JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all test

logic input and output controlled by the testing entity.

MII Mode: In MII mode, this pin will be configured as TX_ER pin and will be sourced

from MAC to PHY. Use of this pin is optional.

21

22

JTAG_CLK/TX_ER

JTAG_TDO/GPIO_1

I

WPU

JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most recent test

results are scanned out of the device via TDO.

General Purpose I/O: This signal provides a multi-function configurable I/O. Please

refer to the GPIO_MUX_CTRL register for details.

O

—

JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin

sequences the Tap Controller (16-state FSM) to select the desired test instruction. It is

recommended to apply 3 clock cycles with JTAG_TMS high to reset the JTAG.

23

24

JTAG_TMS

I

WPU

JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is scanned into

the device via TDI. SD: In 1000Base-X and 100Base-FX mode, this pin will act as

Signal Detect. This should be connected to Signal Detect of optical transceiver.

JTAG_TDI/SD

25

26

27

28

TX_D3

TX_D2

TX_D1

TX_D0

I

WPD

TRANSMIT DATA: Signal TX_D[3:0] carries data from the MAC to the PHY in RGMII

mode and MII mode. Data is synchronous to the transmit clock. In RGMII mode

GTX_CLK is the transmit clock and in MII mode TX_CLK is the transmit clock.

RGMII TRANSMIT CLOCK: This continuous clock signal is sourced from the MAC layer

to the PHY. Nominal frequency is 125 MHz in 1000 Mbps mode. This pin will be Input in

RGMII mode.

29

GTX_CLK/TX_CLK

I/O

WPD

MII TRANSMIT CLOCK: In MII mode, this pin provides a 25-MHz reference clock for

100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps speed. This pin will be

output in MII mode. This pin will be GTX_CLK by default and can be changed to

TX_CLK by register configurations.

I/O Power: 1.8 V (±5%), 2.5 V (±5%) or 3.3 V (±5%). Each pin requires a 1-µF and 0.1-

µF capacitor to GND

30

31

32

VDDIO

VDD1P1

RX_CLK

I

Power

1.1-V Digital Supply (+/-10%). Each pin requires a 1-µF and 0.1-µF capacitor to GND.

RECEIVE CLOCK: Provides the recovered receive clocks for different modes of

operation: 125 MHz in 1000 Mbps RGMII mode.

O

Strap, WPD

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表7-1. RGZ Package (VQFN) Pin Functions (continued)

NAME

I/O

TYPE

DESCRIPTION

NO.

33

RX_D0

RX_D1

RX_D2

RX_D3

O

Strap, WPD

RECEIVE DATA: Signal RX_D[3:0] carries data from the PHY to the MAC in RGMII

mode and in MII mode. Symbols received on the cable are decoded and presented on

these pins synchronous to RX_CLK.

34

35

36

TRANSMIT CONTROL: In RGMII mode, TX_CTRL combines the transmit enable and

the transmit error signal inputs from the MAC using both clock edges.

TX_EN: In MII mode, this pin will function as TX_EN.

37

38

TX_CTRL/TX_EN

RX_CTRL/RX_DV

I

WPD

RECEIVE CONTROL: In RGMII mode, the receive data available and receive error are

combined (RXDV_ER) using both rising and falling edges of the receive clock

(RX_CLK).

O

RX_DV: In MII mode, this pin will function as RX_DV.

39

40

VDD1P1

I

Power

Clock

1.1-V Digital Supply (+/-10%). Each pin requires a 1-µF and 0.1-µF capacitor to GND.

CLOCK OUTPUT: Output clock

CLK_OUT

O

MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may

be sourced by the management station or the PHY. This open-drain pin requires a

1.5kΩpull-up resistor.

41

42

MDIO

MDC

I/O

I

—

MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial management

input/output data. This clock may be asynchronous to the MAC transmit and receive

clocks. The maximum clock rate is 25MHz. There is no minimum clock rate.

RESET_N: This pin is an active-low reset input that initializes or re-initializes all the

internal registers of the DP83869. Asserting this pin low for at least 1µs will force a

reset process to occur. It is in IO voltage domain. A 100Ωresistor and 47uF capacitor

are required to be connected in series between RESET_N pin and Ground.

43

RESET_N

I

—

INTERRUPT / POWER DOWN: The default function of this pin is POWER DOWN.

POWER DOWN: This is an Active Low Input. Asserting this signal low enables the

power-down mode of operation. In this mode the device powers down and consumes

minimum power. Register access is available through the Management Interface to

configure and power up the device.

INTERRUPT: The interrupt pin is an open-drain, active low output signal indicating an

interrupt condition has occurred. Register access is required to determine which event

caused the interrupt. TI recommends using an external 2.2-kΩresistor connected to

the VDDIO supply. When register access is disabled through pin option, the interrupt

will be asserted for 500ms before self-clearing.

44

45

INT_N/PWDN_N

LED_2/GPIO_0

I/O

—

LED_2: Part of VIO voltage domain.

Strap, WPD General Purpose I/O: This signal provides a multi-function configurable I/O. Please

refer to the GPIO_MUX_CTRL register for details.

LED_1: Part of VIO voltage domain.

46

47

LED_1/RX_ER

LED_0

O

Strap, WPD MII Mode: In MII mode this pin will be configured as RX_ER. This pin is asserted high

synchronously to rising edge of RX_CLK. Use of this pin is optional.

Strap, WPD LED_0: This pin is part of the VDDIO voltage domain

No external supply is required for this pin in two-supply mode. When unused, no

connections should be made to these pins. In three-supply mode, an external

1.8V(+/-5%) supply can be connected to these pins. When using an external supply,

48

VDDA1P8_2

I

Power

each pin requires a 1-µF and 0.1-µF capacitor to GND.

Pin Functionality definitions are given below:

• I: Input

• O: Output

• I/O: Input/Output

• Strap: Multifunctional bootstrap pins

• WPD: Weak Pull Down Resistor (internal)

• WPU: Weak Pull Up Resistor (internal)

• Power: Power Supply Pins

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• Analog: Analog pins

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表7-2. Pin States-1

COPPER MODE

RGMII

RESET

PIN NO

PIN NAME

MII

SGMII

PIN STATE PULL/HI-Z PIN STATE PULL/HI-Z PIN STATE PULL/HI-Z PIN STATE PULL/HI-Z

14

15

16

17

21

SON

SOP

SIP

O

I

Hi-Z

PU

O

I

Hi-Z

PU

O

I

Hi-Z

PU

O

I

50Ω

PU

SIN

I

JTAG_CLK/

TX_ER

I

22

JTAG_TDO

/ GPIO_1

I

PD

O

Hi-Z

O

Hi-Z

O

Hi-Z

23

24

JTAG_TMS

I

PU

I

PU

I

PU

I

PU

JTAG_TDI /

SD

25

26

27

28

29

TX_D3

TX_D2

TX_D1

TX_D0

I

PD

I

PD

I

PD

I

PD

I

GTX_CLK /

TX_CLK

O

32

33

34

35

36

37

RX_CLK

RX_D0

RX_D1

RX_D2

RX_D3

I

PD

O

I

Hi-Z

PD

O (125MHz)

Hi-Z

PD

I

PD

O

I

TX_CTRL /

TX_EN

38

RX_CTRL /

RX_DV

I

PD

O

Hi-Z

O

Hi-Z

I

Hi-Z

40

41

42

43

44

CLK_OUT O (25MHz)

Hi-Z

PU

O (25MHz)

Hi-Z

O (25MHz)

Hi-Z

O (25MHz)

Hi-Z

MDIO

MDC

I

I/O

I

Hi-Z

I

Hi-Z

I

Hi-Z

RESET_N

PU

INT_N /

PU

I/O

PU/OD-PU

I/O

PU/OD-PU

I/O

PU/OD-PU

PWDN_N

45

46

47

LED_2 /

GPIO_0

I

PD

I/O

O

Hi-Z

I/O

O

Hi-Z

I/O

O

Hi-Z

LED_1 /

RX_ER

LED_0

O

8

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PIN NO

ZHCSIS3B –SEPTEMBER 2018 –REVISED DECEMBER 2022

表7-3. Pin States-2

BRIDGE MODE

MEDIA CONVERTOR

PIN NAME

RGMII TO SGMII

SGMII TO RGMII

PIN STATE PULL/HI-Z

PIN STATE

PULL/HI-Z

50Ω

PIN STATE

PULL/HI-Z

50Ω

14

15

16

17

21

SON

SOP

SIP

O

I

O

I

O

I

50Ω

PU

50Ω

SIN

I

50Ω

JTAG_CLK/

TX_ER

I

PU

I

PU

22

JTAG_TDO /

GPIO_1

O

Hi-Z

O

Hi-Z

O

Hi-Z

23

24

25

26

27

28

29

JTAG_TMS

JTAG_TDI / SD

TX_D3

I

PU

PD

I

PU

PD

I

PU

PD

TX_D2

TX_D1

TX_D0

GTX_CLK /

TX_CLK

32

33

34

36

37

RX_CLK

RX_D0

RX_D1

RX_D2

RX_D3

I

PD

O

I

Hi-Z

PD

O

I

Hi-Z

PD

TX_CTRL /

TX_EN

38

RX_CTRL /

RX_DV

I

PD

O

Hi-Z

O

Hi-Z

40

41

42

43

44

CLK_OUT

MDIO

O (25MHz)

Hi-Z

O (25MHz)

Hi-Z

O (25MHz)

Hi-Z

I/O

MDC

I

Hi-Z

I

Hi-Z

I

Hi-Z

RESET_N

PU

INT_N /

I/O

PU/OD-PU

I/O

PU/OD-PU

I/O

PU/OD-PU

PWDN_N

45

LED_2 /

GPIO_0

I/O

Hi-Z

I/O

Hi-Z

I/O

Hi-Z

46

47

LED_1 / RX_ER

LED_0

O

Hi-Z

O

Hi-Z

O

Hi-Z

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表7-4. Pin States-3

PIN NO

PIN NAME

IEEE PWDN

MII ISOLATE

PIN STATE

PULL/HI-Z

50Ω

PU

14

15

16

17

21

22

23

24

25

26

27

28

29

32

33

34

36

37

38

40

41

42

43

44

45

46

47

SON

SOP

O

50Ω

PU

O

SIP

I

SIN

I

JTAG_CLK/ TX_ER

JTAG_TDO / GPIO_1

JTAG_TMS

JTAG_TDI / SD

TX_D3

I/O

I

O

Hi-Z

PU

O

Hi-Z

PU

I

PU

I

PU

I

PD

I

PD

TX_D2

I

PD

I

PD

TX_D1

I

PD

I

PD

TX_D0

I

PD

I

PD

GTX_CLK / TX_CLK

RX_CLK

I

PD

I

PD

O (2.5MHz)

Hi-Z

PD

I

PD

RX_D0

O

I

PD

RX_D1

O

I

PD

RX_D2

O

I

PD

RX_D3

O

I

PD

TX_CTRL / TX_EN

RX_CTRL / RX_DV

CLK_OUT

MDIO

I

PD

O

Hi-Z

PD

I

PD

O (25MHz)

Hi-Z

PU

I

MDC

RESET_N

INT_N / PWDN_N

LED_2 / GPIO_0

LED_1 / RX_ER

LED_0

I

I/O

O

PU/OD-PU

Hi-Z

I/O

O

PU/OD-PU

Hi-Z

10

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8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

MIN

-0.3

MAX

1.4

2.16

3

UNIT

V

VDD1P1

VDD1P8

V

VDD2P5

V

Supply voltage

VDDIO (3V3)

3.8

3

V

VDDIO (2V5)

VDDIO (1V8)

V

2.1

6.5

V

Pins

MDI

V

VDDIO +

0.3

MAC Interface, MDIO, MDC, GPIO

-0.3

V

VDDIO +

0.3

Pins

INT/PWDN, RESET

VDDIO +

0.3

Pins

JTAG

Tstg

-0.3

-60

V

C

Storage temperature

150

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

8.2 ESD Ratings

Parameter

VALUE UNIT

All pins except MDI

MDI pins⁽²⁾

+/-2500

Human-body model (HBM),

perANSI/ESDA/JEDEC JS-001⁽¹⁾

+/-8000

V

Charged-device model (CDM), per

JEDEC specification JESD22-

C101⁽³⁾

V_(ESD)V(ESD) Electrostatic discharge

All Pins

+/-1500

IEC 61000-4-2 contact discharge

MDI pins

+/-8000

V

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. Manufacturing

withless than 500 V HBM is possible with the necessary precautions. Pins listed as ±8 kV and/or ± 2 kV may actually have

higherperformance.

(2) MDI Pins tested as per IEC 61000-4-2 standards.

(3) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Manufacturing

withless than 250 V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

Parameter

Digital Supply Voltage, 1.8V operation

Digital Supply Voltage, 2.5V operation

Digital Supply Voltage, 3.3V operation

Digital Supply

MIN

1.71

2.375

3.15

0.99

1.71

2.375

-40

NOM

1.8

2.5

3.3

1.1

1.8

2.5

MAX

1.89

2.625

3.45

1.21

1.89

2.625

125

UNIT

VDDIO

V

VDD1P1

V

VDDA1P8 Analog Supply

VDDA2P5 Analog Supply

V

T_A

Operating Ambient Temperature (DP83869HM)

℃

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8.4 Thermal Information

THERMAL METRIC⁽¹⁾

48PIN VQFN

UNIT

°C/W

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-case (bottom) thermal resistance

Junction-to-board thermal resistance

30.8

18.7

1.4

R_θJC(top)

R_θJC(bot)

R_θJB

7.5

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.3

Ψ_JT

7.5

Ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

1000Base-X/100Base-FX/SGMII INPUT

Input differential voltage tolerance

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SI_P and SI_N, AC coupled

0.3

80

0.5

2.0

120

V

Receiver differential input impedance

(DC)

100

Ohm

ppm

Frequency tolerance

SI_P and SI_N, AC coupled

-100

+100

1000Base-X OUTPUT

SO_P and SO_N, AC coupled,

0101010101 pattern

Clock signal duty cycle

Vod fall time (20%-80%)

48

100

52

200

%

SO_P and SO_N, AC coupled,

0101010101 pattern

ps

SO_P and SO_N, AC coupled,

0101010101 pattern

Vod rise time (20%-80%)

Total Ouput Jitter

ps

SO_P and SO_N, AC coupled

192

Output Differential Voltage (Configuration

bits for 0.6V - 1.27V; Default at 1.1V)

1060

1100

1140

mV

100Base-FX OUTPUT

Clock signal duty cycle at 625MHz

Vod fall time (20%-80%)

Vod rise time (20%-80%)

Jitter

SO_P and SO_N, AC coupled

55

330

192

%

ps

Output Differential Voltage (Configuration

bits for 0.6V - 1.8V)

SO_P and SO_N, AC coupled

450

910

mV

SGMII OUTPUT

SO_P and SO_N, AC coupled,

0101010101 pattern

Clock signal duty cycle @625MHz

48

100

52

%

SO_P and SO_N, AC coupled,

0101010101 pattern

Vod fall time (20%-80%)

200

ps

SO_P and SO_N, AC coupled,

0101010101 pattern

Vod rise time (20%-80%)

Output Jitter

200

300

ps

SO_P and SO_N, AC coupled

Output Differential Voltage (Configuration

bits for 0.6V - 1.27V; Default at 1.1V)

1060

1100

1140

mV

IEEE Tx CONFORMANCE (1000BaseT)

Output Differential Voltage

Normal Mode, All channels

0.67

0.95

0.745

1.00

0.82

1.05

V

IEEE Tx CONFORMANCE (100BaseTx)

Output Differential Voltage

Normal Mode, Channels A and B

12

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8.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

IEEE Tx CONFORMANCE (10BaseTe)

Output Differential Voltage

TEST CONDITIONS

MIN

TYP

MAX

UNIT

1.75

V

POWER CONSUMPTION Copper mode (100m cable)

RGMII to Copper (1G)

483

215

260

212

261

496

251

294

131

47

mW

mA

RGMII to Copper (100M)

RGMII to Copper (10M)

MII to Copper (100M)

Total

Room Temperature, Nominal supply

voltages

MII to Copper (10M)

SGMII to Copper (1G)

SGMII to Copper (100M)

SGMII to Copper (10M)

RGMII to Copper (1G)

RGMII to Copper (100M)

RGMII to Copper (10M)

195

110

100

110

95

37

MII to Copper (100M)

I(1V1)

43

Room Temperature, 1.1V supply voltage

Room Temperature, 1.8V supply voltage

Room Temperature, 2.5V supply voltage

MII to Copper (10M)

36

SGMII to Copper (1G)

SGMII to Copper (100M)

SGMII to Copper (10M)

RGMII to Copper (1G)

RGMII to Copper (100M)

RGMII to Copper (10M)

141

60

220

125

112

55

50

52

21

26

11

15

MII to Copper (100M)

I(1V8)

21

26

MII to Copper (10M)

10

15

SGMII to Copper (1G)

SGMII to Copper (100M)

SGMII to Copper (10M)

RGMII to Copper (1G)

RGMII to Copper (100M)

RGMII to Copper (10M)

55

60

24

28

14

18

86

100

50

46

76

90

MII to Copper (100M)

I(2V5)

45

52

MII to Copper (10M)

78

92

SGMII to Copper (1G)

SGMII to Copper (100M)

SGMII to Copper (10M)

RGMII to Copper (1G)

RGMII to Copper (100M)

RGMII to Copper (10M)

93

100

58

53

82

95

30

80

13

22

10

16

MII to Copper (100M)

MII to Copper (10M)

15

66

I(VDDIO

=3.3V)

Room Temperature, 3.3V supply voltage

11

38

SGMII to Copper (1G)

SGMII to Copper (100M)

SGMII to Copper (10M)

10

16

10

16

10

16

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8.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

RGMII to Copper (1G)

RGMII to Copper (100M)

RGMII to Copper (10M)

MII to Copper (100M)

MII to Copper (10M)

TEST CONDITIONS

MIN

TYP

17

6

MAX

UNIT

mA

30

12

10

15

10

5

8

I(VDDIO

=1.8V)

Room Temperature, 1.8V supply voltage

5

SGMII to Copper (1G)

SGMII to Copper (100M)

SGMII to Copper (10M)

5

POWER CONSUMPTION Fiber mode

RGMII to 1000Base-X

142

111

107

52

44

41.8

14

12

11

mW

mA

Room Temperature, Nominal supply

voltages

Total

RGMII to 100Base-FX

MII to 100Base-FX

RGMII to 1000Base-X

RGMII to 100Base-FX

MII to 100Base-FX

I(1V1)

I(1V8)

I(2V5)

Room Temperature, 1.1V supply voltage

Room Temperature, 1.8V supply voltage

Room Temperature, 2.5V supply voltage

Room Temperature, 3.3V supply voltage

Room Temperature, 1.8V supply voltage

RGMII to 1000Base-X

RGMII to 100Base-FX

MII to 100Base-FX

RGMII to 1000Base-X

RGMII to 100Base-FX

MII to 100Base-FX

10

32

14

16

18

7

RGMII to 1000Base-X

RGMII to 100Base-FX

MII to 100Base-FX

I(VDDIO

=3.3V)

RGMII to 1000Base-X

RGMII to 100Base-FX

MII to 100Base-FX

I(VDDIO

=1.8V)

8

POWER CONSUMPTION R2S mode

RGMII to SGMII (1G)

142

120

117

52

50

49

14

13

14

11

mW

mA

Room Temperature, Nominal supply

voltages

Total

RGMII to SGMII (100M)

RGMII to SGMII (10M)

RGMII to SGMII (1G)

RGMII to SGMII (100M)

RGMII to SGMII (10M)

RGMII to SGMII (1G)

RGMII to SGMII (100M)

RGMII to SGMII (10M)

RGMII to SGMII (1G)

RGMII to SGMII (100M)

RGMII to SGMII (10M)

RGMII to SGMII (1G)

RGMII to SGMII (100M)

RGMII to SGMII (10M)

I(1V1)

I(1V8)

I(2V5)

Room Temperature, 1.1V supply voltage

Room Temperature, 1.8V supply voltage

Room Temperature, 2.5V supply voltage

Room Temperature, 3.3V supply voltage

11

32

15

12

I(VDDIO

=3.3V)

14

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8.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

RGMII to SGMII (1G)

RGMII to SGMII (100M)

RGMII to SGMII (10M)

TEST CONDITIONS

MIN

TYP

18

8

MAX

UNIT

mA

I(VDDIO

=1.8V)

Room Temperature, 1.8V supply voltage

mA

6

mA

POWER CONSUMPTION S2R mode

SGMII to RGMII (1G)

142

121

117

52

49

14

11

33

16

13

18

8

mW

mA

Room Temperature, Nominal supply

voltages

Total

SGMII to RGMII (100M)

SGMII to RGMII (10M)

SGMII to RGMII (1G)

SGMII to RGMII (100M)

SGMII to RGMII (10M)

SGMII to RGMII (1G)

SGMII to RGMII (100M)

SGMII to RGMII (10M)

SGMII to RGMII (1G)

SGMII to RGMII (100M)

SGMII to RGMII (10M)

SGMII to RGMII (1G)

SGMII to RGMII (100M)

SGMII to RGMII (10M)

SGMII to RGMII (1G)

SGMII to RGMII (100M)

SGMII to RGMII (10M)

I(1V1)

I(1V8)

I(2V5)

Room Temperature, 1.1V supply voltage

Room Temperature, 1.8V supply voltage

Room Temperature, 2.5V supply voltage

Room Temperature, 3.3V supply voltage

Room Temperature, 1.8V supply voltage

I(VDDIO

=3.3V)

I(VDDIO

=1.8V)

6

POWER CONSUMPTION Cu-Fiber mode (100m cable)

1000Base-TX to 1000Base-FX

100Base-TX to 100Base-FX

1000Base-TX to 1000Base-FX

100Base-TX to 100Base-FX

1000Base-TX to 1000Base-FX

100Base-TX to 100Base-FX

1000Base-TX to 1000Base-FX

100Base-TX to 100Base-FX

1000Base-TX to 1000Base-FX

100Base-TX to 100Base-FX

1000Base-TX to 1000Base-FX

100Base-TX to 100Base-FX

495

243

142

55

24

93

52

9

mW

mA

Room Temperature, Nominal supply

voltage

Total

I(1V1)

I(1V8)

I(2V5)

Room Temperature, 1.1V supply voltage

Room Temperature, 1.8V supply voltage

Room Temperature, 2.5V supply voltage

Room Temperature, 3.3V supply voltage

Room Temperature, 1.8V supply voltage

I(VDDIO

=3.3V)

10

4

I(VDDIO

=1.8V)

5

POWER CONSUMPTION Low power modes

IEEE Power Down

76

165

82

mW

Total

Active Sleep

RESET

Room Temperature, Nominal Voltages

BOOTSTRAP DC CHARACTERISTICS (4 Level) (PHY address pins)

0.093 x

VDDIO

V_MODE0Mode 0 Strap Voltage Range

0

V

0.136 x

VDDIO

0.184 x

VDDIO

V_MODE1Mode 1 Strap Voltage Range

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8.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0.219 x

VDDIO

0.280 x

VDDIO

V_MODE2Mode 2 Strap Voltage Range

V

0.6 x

VDDIO

0.888 x

VDDIO

V_MODE3Mode 3 Strap Voltage Range

BOOTSTRAP DC CHARACTERISTICS (2 Level)

V_MODE0Mode 0 Strap Voltage Range

V

0.18 x

VDDIO

0

V

0.5 x

VDDIO

0.88 x

VDDIO

V_MODE1Mode 1 Strap Voltage Range

IO CHARACTERISTICS

V_IH

V_IL

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

Low Level Output Voltage

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

Low Level Output Voltage

VDDIO = 3.3V ±5%

2

2.4

1.7

2

V

VDDIO = 3.3V ±5%

0.8

0.4

0.7

0.4

V_OH

V_OL

V_IH

V_IL

I_OH= -2mA, VDDIO = 3.3V ±5%

I_OL= 2mA, VDDIO = 3.3V ±5%

VDDIO = 2.5V ±5%

V_OH

V_OL

I_OH= -2mA, VDDIO = 2.5V ±5%

I_OL= 2mA, VDDIO = 2.5V ±5%

0.65*VD

DIO

V_IH

V_IL

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

VDDIO = 1.8V ±5%

V

0.35*VD

DIO

VDDIO = 1.8V ±5%

VDDIO-0

.45

V_OH

I_OH= -2mA, VDDIO = 1.8V ±5%

V_OL

Low Level Output Voltage

Input High Current

I_OL= 2mA, VDDIO = 1.8V ±5%

T_A= -40℃to 125℃, VIN=VDDIO

T_A= -40℃to 125℃, VIN=GND

T_A= -40℃to 125℃, VOUT=VDDIO

T_A= -40℃to 125℃, VOUT=GND

0.45

20

V

I_IH

-20

µA

I_IL

Input Low Current

20

Iozh

Iozl

Tri-state Output High Current

Tri-state Output Low Current

Internal Pull Down Resistor

High Level Input Voltage

Low Level Input Voltage

Input Capacitance XI

-20

20

-20

20

R_pulldn

XI V_IH

XI V_IL

C_IN

6.75

1.2

9

11.25

VDDIO

0.6

kΩ

V

1

5

1

5

pF

C_IN

Input Capacitance INPUT PINS

Output Capacitance XO

Output Capacitance OUTPUT PINS

C_OUT

Integrated MAC Series Termination

Resistor

R_series

RX_D[3:0], RX_ER, RX_DV, RX_CLK

50

Ω

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8.6 Timing Requirements

PARAMETER

MIN

NOM

MAX

UNIT

POWER-UP TIMING (2, 3 supply mode)

T1

T2

Last Supply power up To Reset Release: External or via R-C network

200

ms

Powerup to SMI ready: Post power-up stabilization time prior to MDC

preamble for register access

200

Powerup to Strap latchin: Hardware configuration pins transition to output

drivers

T3

ms

RESET TIMING

Reset to SMI ready: Post reset stabilization time prior to MDC preamble for

register access

T1

30

us

T3

T4

RESET PULSE Width: Miminum Reset pulse width to be able to reset

Reset to FLP

720

ns

ms

us

1750

194

248

235

195

248

Reset to 100M signaling (strapped mode)

Reset to 1G signaling (strapped mode)

Reset to Fiber 100M signaling

Reset to Fiber 1G ANEG signaling

Reset to Fiber 1G Forced signaling

Reset to MAC clock (Cu mode)

Reset to MAC clock (Fi mode)

Reset to MAC clock (S2R)

Reset to MAC clock (R2S)

COPPER LINK TIMING

Loss of Idles to Link LED low in Fast link down mode (100M)

Loss of Idles to Link LED low in Fast link down mode (1000M)

MII TIMING (100M)

4.3

7

10

us

T1

T2

T3

T1

T2

TX_CLK High / Low Time

16

10

0

20

24

ns

TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK

TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK

RX_CLK High / Low Time

16

10

24

30

RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising

RGMII OUTPUT TIMING (1G)

T_skewT

Data to Clock Output Skew (Non-Delay Mode)

-600

1.4

600

2.6

ps

ns

T_skewT(Delay

Data to Clock Output Setup (Delay Mode)

)

T_setupT

T_holdT

T_cyc

Data to Clock Output Setup ( Delay Mode)

Data to Clock Output Hold ( Delay Mode)

Clock Cycle Duration

1.2

7.2

45

ns

%

8

8.8

55

Duty Cycle

50

Rise / Fall Time ( 20% to 80%)

0.75

ns

RGMII INPUT TIMING (1G)

T_setupRTX data to clock input setup (Non-Delay Mode)

T_holdR

1

ns

TX clock to data input hold (Non-Delay Mode)

TX data to clock input setup (Delay Mode, 2ns delay)

TX clock to data input hold (Delay Mode, 2ns delay)

-1

3

SMI TIMING

T1

T2

MDC to MDIO (Output) Delay Time

MDIO (Input) to MDC Setup Time

0

10

ns

10

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8.6 Timing Requirements (continued)

PARAMETER

MIN

NOM

MAX

UNIT

ns

T3

T4

MDIO (Input) to MDC Hold Time

MDC Frequency

10

2.5

25

MHz

OUTPUT CLOCK TIMING (25MHz clockout)

Frequency (PPM)

-100

40

100

60

-

%

Duty Cycle

Rise Time

5000

ps

Fall Time

ps

Frequency

Jitter (Long Term)

25

MHz

ps

375

OUTPUT CLOCK TIMING (SyncE 125/5 MHz recovered clock)

Frequency (PPM)

-100

40

100

60

ppm

%

Duty Cycle

Rise time

2500

1000

ps

Fall Time

ps

Jitter (Long Term)

ps

25MHz INPUT CLOCK tolerance

Frequency Tolerance

-100

40

+100

8

ppm

ns

Rise / Fall Time (10%-90%)

Jitter Tolerance (Accumulated : TIE over 100K cycles)

Duty Cycle

75

ps

60

%

TRANSMIT LATENCY TIMING

RGMII to Cu (100M): Rising edge TX_CLK with assertion TX_CTRL to

SSD symbol on MDI

Copper

169

ns

Copper

RECEIVE LATENCY TIMING

Cu to RGMII (100M): SSD symbol on MDI to a) Rising edge of RX_DV

RGMII to Cu (1G): Roundtrip Latency (Transmit + Receive)

384

Copper

with assertion of RX_CTRL b) Rising edge of RX_DV with assertion of

RX_Dx

192

ns

18

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8.7 Timing Diagrams

VDD

XI clock

T1

Hardware

RESET_N

32

CLOCKS

T2

T3

MDC

INPUT

OUTPUT

Dual Function Pins

Become Enabled As Outputs

图8-1. Power-Up Timing

VDD

XI clock

T1

T3

Hardware

RESET_N

32

CLOCKS

MDC

T2

T4

Dual Function Pins

Become Enabled As Outputs

Signal Output

图8-2. Reset Timing

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tT1t

Idles

PMD

Link LED

(Active High)

图8-3. Copper Link Timing

T1

TX_CLK

T2

T3

TXD[3:0]

TX_EN

Valid Data

图8-4. 100-Mbps MII Transmit Timing

T1

RX_CLK

T2

RXD[3:0]

RX_DV

RX_ER

Valid Data

图8-5. 100-Mbps MII Receive Timing

GTX

(at Transmitter)

TskewT

TXD [8:5][3:0]

TXD [7:4][3:0]

TXD [8:5]

TXD [3:0]

TXD [7:4]

TXD [4]

TXEN

TXD [9]

TXERR

TX_CTL

TskewR

GTX

(at Receiver)

图8-6. RGMII Transmit Multiplexing and Timing Diagram

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RXC

(Source of Data)

RXC with Internal

Delay Added

TsetupT

RXD [8:5][3:0]

RXD [7:4][3:0]

RXD [8:5]

RXD [7:4]

RXD [3:0]

TholdT

RXD [4]

RXDV

RXD [9]

RXERR

RX_CTL

RXC

(at Receiver)

TholdR

TsetupR

图8-7. RGMII Receive Multiplexing and Timing Diagram

MDC

T4

T1

MDIO

(output)

MDC

T2

T3

MDIO

(input)

Valid Data

图8-8. Serial Management Interface Timing

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8.8 Typical Characteristics

Time (4 ns/DIV)

Time (32 ns/DIV)

mV/Div

ns/Div

mV/Div

ns/Div

32 ns

200 mV

4 ns

500 mV

图8-9. 1000Base-T Test Mode 2 Signal

图8-10. 100Base-TX Signal

mV/Div

ns/Div

mV/Div

µs/Div

400 µs

500 mV

80 ns

500 mV

图8-11. 10Base-Te Link Pulse

图8-12. Auto-Negotiation FLP

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9 Detailed Description

9.1 Overview

The DP83869HM is a fully-featured Gigabit Physical Layer transceiver with support for Fiber and Copper

Ethernet standards. It can support IEEE802.3 10BASE-Te, 100BASE-TX, and 1000BASE-T Copper Ethernet

protocols, along with 100BASE-FX and 1000BASE-X Fiber Ethernet protocols.

The DP83869HM is designed for easy implementation of 10-Mbps, 100-Mbps, and 1000-Mbps Ethernet LANs.

In Copper mode, the PHY can interface with twisted-pair media through magnetics. In Fiber Mode, it can

interface with Fiber Optic Transceivers. This device interfaces directly to the MAC layer through the Reduced

GMII (RGMII) or Serial GMII (SGMII). SGMII is available only in copper Ethernet mode. MII mode is supported

for 10M and 100M speeds.

The DP83869HM supports media convertor mode to interface between copper and fiber Ethernet interface.

Media convertor is available for 100M and 1000M speeds.

The DP83869HM can also support bridge mode to interface between SGMII and RGMII.

The DP83869HM offers low latency. It provides IEEE 1588 Start of Frame Delimiter indication. It has option to

provide recovered clock for synchronous Ethernet application.

The DP83869HM has a TDR cable diagnostic feature for fault detection on the Ethernet cable.

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9.2 Functional Block Diagram

RGMII/MII INTERFACE

MGMT INTERFACE

MGNT

& PHY CNTRL

RGMII/MII Interface

SGMII Interface

1000BASE-X Block

100BASE-FX Block

10BASE-Te Block

Wake on

LAN

1000BASE-T Block

100BASE-TX Block

Auto-

Negotiation

Manchester

10 Mbps

PAM-5

17 Level PR Shaped

125 Msymbols/s

MLT-3

100 Mbps

DAC / ADC

SUBSYSTEM

TIMING

DRIVERS / RECEIVERS

DRIVERS /

RECEIVERS

DAC / ADC

TIMING BLOCK

SOP

SON

SIP SIN

Fiber Ethernet PMD Connections

Or

SGMII Connections

Copper Ethernet

PMD Connections

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9.3 Feature Description

9.3.1 WoL (Wake-on-LAN) Packet Detection

Wake-on-LAN provides a mechanism to detect specific frames and notify the connected MAC through either a

register status change, GPIO indication, or an interrupt flag. The WoL feature within the DP83869HM allows for

connected devices placed above the Physical Layer to remain in a low power state until frames with the

qualifying credentials are detected. Supported WoL frame types include: Magic Packet, Magic Packet with

SecureOn, and Custom Pattern Match. When a qualifying WoL frame is received, the DP83869HM WoL logic

circuit is able to generate a user-defined event (either pulses or level change) through any of the GPIO pins or a

status interrupt flag to inform a connected controller that a wake event has occurred.

The Wake-on-LAN feature includes the following functionality:

• Identification of magic packets in all supported speeds

• Wake-up interrupt generation upon receiving a valid magic packet

• CRC checking of magic packets to prevent interrupt generation for invalid packets

In addition to the basic magic packet support, the DP83869HM also supports:

• Magic packets that include a SecureOn password

• Pattern match –one configurable 64-byte pattern of that can wake up the MAC similar to magic packet

• Independent configuration for Wake on Broadcast and Unicast packet types.

9.3.1.1 Magic Packet Structure

When configured for Magic Packet mode, the DP83869HM scans all incoming frames addressed to the node for

a specific data sequence. This sequence identifies the frame as a Magic Packet frame.

备注

The Magic Packet should be byte aligned.

A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as SOURCE

ADDRESS, DESTINATION ADDRESS (which may be the receiving station’s IEEE address or a BROADCAST

address), and CRC.

The specific Magic Packet sequence consists of 16 duplications of the IEEE address of this node, with no breaks

or interruptions, followed by a SecureOn password if security is enabled. This sequence can be located

anywhere within the packet, but must be preceded by a synchronization stream. The synchronization stream is

defined as 6 bytes of FFh.

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DEST (6 bytes)

SRC (6 bytes)

MISC (X bytes, X >= 0)

FF… FF (6 bytes)

MAGIC pattern

DEST * 16

SecureOn Password (6 bytes)

MISC (Y bytes, Y >= 0)

CRC (4 bytes)

Only if Secure-On is enabled

图9-1. Magic Packet Structure

9.3.1.2 Magic Packet Example

The following is an example Magic Packet for a Destination Address of 11h 22h 33h 44h 55h 66h and a

SecureOn Password 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh:

DESTINATION SOURCE MISC FF FF FF FF FF FF 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11

22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44

55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11

22 33 44 55 66 11 22 33 44 55 66 2A 2B 2C 2D 2E 2F MISC CRC

9.3.1.3 Wake-on-LAN Configuration and Status

Wake-on-LAN functionality is configured through the RXFCFG register (address 134h). Wake-on-LAN status is

reported in the RXFSTS register (address 135h).

9.3.2 Start of Frame Detect for IEEE 1588 Time Stamp

The DP83869HM supports an IEEE 1588 indication pulse at the SFD (start frame delimiter) for the receive and

transmit paths. The pulse can be delivered to various pins. The pulse indicates the actual time the symbol is

presented on the lines (for transmit), or the first symbol received (for receive). The exact timing of the pulse can

be adjusted through register. Each increment of phase value is an 8-ns step.

图9-2. IEEE 1588 Message Timestamp Point

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The SFD pulse output can be configured using the GPIO Mux Control register GPIO_MUX_CTRL (register

address 1E0h). The ENHANCED_MAC_SUPPORT bit in RXCFG (register address 134h) must also be set to

allow output of the SFD.

9.3.2.1 SFD Latency Variation and Determinism

Time stamping packet transmission and reception using the RX_CTRL and TX_CTRL signals of RGMII is not

accurate enough for latency sensitive protocols. SFD pulses offers system designers a method to improve the

accuracy of packet time stamping. The SFD pulse, while varying less than RGMII signals inherently, still exhibits

latency variation due to the defined architecture of 1000BASE-T. This section provides a method to determine

when an SFD latency variation has occurred and how to compensate for the variation in system software to

improve timestamp accuracy.

In the following section the terms baseline latency and SFD variation are used. Baseline latency is the time

measured between the TX_SFD pulse to the RX_SFD pulse of a connected link partner, assuming an Ethernet

cable with all 4 pairs perfectly matched in propagation time. In the scenario where all 4 pairs being perfectly

matched, a 1000BASE-T PHY will not have to align the 4 received symbols on the wire and will not introduce

extra latency due to alignment.

TX SFD

Baseline Latency

RX SFD

SFD Variation

图9-3. Baseline Latency and SFD Variation in Latency Measurement

SFD variation is additional time added to the baseline latency before the RX_SFD pulse when the PHY must

introduce latency to align the 4 symbols from the Ethernet cable. Variation can occur when a new link is

established either by cable connection, auto-negotiation restart, PHY reset, or other external system effects.

During a single, uninterrupted link, the SFD variation will remain constant.

The DP83869HM can limit and report the variation applied to the SFD pulse while in the 1000-Mb operating

mode. Before a link is established in 1000-Mb mode, the Sync FIFO Control Register (register address E9h)

must be set to value 0xDF22. The below SFD variation compensation method can only be applied after the Sync

FIFO Control Register has been initialized and a new link has been established. It is acceptable to set the Sync

FIFO Control register value and then perform a software restart by setting the SW_RESTART bit[14] in the

Control Register (register address 1Fh) if a link is already present.

9.3.2.1.1 1000-Mb SFD Variation in Master Mode

When the DP83869HM is operating in 1000-Mb master mode, variation of the RX_SFD pulse can be estimated

using the Skew FIFO Status register (register address 55h) bit[7:4]. The value read from the Skew FIFO Status

register bit[7:4] must be multiplied by 8 ns to estimate the RX_SFD variation added to the baseline latency.

Example: While operating in master 1000-Mb mode, a value of 0x2 is read from the Skew FIFO register bit[7:4].

2 × 8 ns = 16 ns is subtracted from the TX_SFD to RX_SFD measurement to determine the baseline latency.

9.3.2.1.2 1000-Mb SFD Variation in Slave Mode

When the DP83869HM is operating in 1000-Mb slave mode, the variation of the RX_SFD pulse can be

determined using the Skew FIFO Status register (register address 55h) bit[3:0].The value read from the Skew

FIFO Status register bit[3:0] should be multiplied by 8ns to estimate the RX_SFD variation added to the baseline

latency.

Example: While operating in slave 1000-Mb mode, a value of 0x1 is read from the Skew FIFO register bit[3:0].

1 × 8 ns = 8 ns is subtracted from the TX_SFD to RX_SFD measurement to determine the baseline latency.

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9.3.2.1.3 100-Mb SFD Variation

The latency variation in 100-Mb mode of operation is determined by random process and does not require any

register readout or system level compensation of SFD pulses.

9.3.3 Clock Output

The DP83869HM has several internal clocks, including the local reference clock, the Ethernet transmit clock,

and the Ethernet receive clock. An external crystal or oscillator provides the stimulus for the local reference

clock. The local reference clock acts as the central source for all clocking in the device.

The local reference clock is embedded into the transmit network packet traffic and is recovered from the network

packet traffic at the receiver node. The receive clock is recovered from the received Ethernet packet data stream

and is locked to the transmit clock in the partner.

Using the I/O Configuration register (address 170h), the DP83869HM can be configured to output these internal

clocks through the CLK_OUT pin. By default, the output clock is synchronous to the XI oscillator / crystal input.

The default output clock is suitable for use as the reference clock of another DP83869HM device. Through

registers, the output clock can be configured to be synchronous to the receive data at the 125-MHz data rate or

at the divide by 5 rate of 25 MHz. It can also be configured to output the line driver transmit clock. When

operating in 1000Base-T mode, the output clock can be configured for any of the four transmit or receive

channels.

It is important to note that when clock output of DP83869HM is being used as a clock input for another device,

for e.g. two DP83869HM in daisy chain, then the primary DP83869HM should not be reset via the RESET pin. If

reset is required then it should be performed via software. The output clock can be disabled using the

CLK_O_DISABLE bit of the I/O Configuration register.

9.3.4 Loopback Mode

There are several options for Loopback that test and verify various functional blocks within the PHY. Enabling

loopback mode allows in-circuit testing of the digital and analog data paths. Generally, the DP83869HM may be

configured to one of the Near-end loopback modes or to the Far-end (reverse) loopback. MII Loopback is

configured using the BMCR (register address 0h). All other loopback modes are enabled using the

BIST_CONTROL (register address 16h). Except where otherwise noted, loopback modes are supported for all

speeds (10/100/1000) and all MAC interfaces (SGMII and RGMII).

Reverse

Loopback

PCS

Loopback

Analog

Loopback

MAC

MII

Loopback

Digital

Loopback

External

Loopback

Only in 10Base-Te

and 100Base-TX.

图9-4. Loopbacks

9.3.4.1 Near-End Loopback

Near-end loopback provides the ability to loop the transmitted data back to the receiver through the digital or

analog circuitry. The point at which the signal is looped back is selected using loopback control bits with several

options being provided.

When configuring loopback modes, the Loopback Configuration Register (LOOPCR), address FEh, should be

set to 0xE720.

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To maintain the desired operating mode, Auto-Negotiation should be disabled before selecting the Near-End

Loopback mode. This constraint does not apply for external-loopback mode.

Auto-MDIX should be disabled before selecting the Near-End Loopback mode. MDI or MDIX configuration

should be manually configured.

9.3.4.1.1 MII Loopback

MII Loopback is the shallowest loop through the PHY. It is a useful test mode to validate communications

between the MAC and the PHY. While in MII Loopback mode, the data is looped back and can be configured

through the register to transmit onto the media. In 100Base-TX mode after MII loopback is enabled through

register 0h, it is necessary to write 0x4 to register 16h for proper operation of MII Loopback.

9.3.4.1.2 PCS Loopback

PCS Loopback occurs in the PCS layer of the PHY. No signal processing is performed when using PCS

Loopback.

9.3.4.1.3 Digital Loopback

Digital Loopback includes the entire digital transmit – receive path. Data is looped back prior to the analog

circuitry.

9.3.4.1.4 Analog Loopback

Analog Loopback includes the entire analog transmit-receive path. For proper operation in Analog Loopback

mode, attach 100-Ω terminations to the copper side when operating in Copper mode and 100-Ω termination on

fiber side when operating in Fiber mode.

9.3.4.1.5 External Loopback

When operating in 10BASE-Te or 100Base-T mode, signals can be looped back at the RJ-45 connector by

wiring the transmit pins to the receive pins. Due to the nature of the signaling in 1000Base-T mode, this type of

external loopback is not supported. Analog loopback provides a way to loop data back in the analog circuitry

when operating in 1000Base-T mode.

9.3.4.1.6 Far-End (Reverse) Loopback

Far-end (Reverse) Loopback is a special test mode to allow testing the PHY from the link-partner side. In this

mode, data that is received from the link partner passes through the PHY's receiver is looped back at the MAC

interface and is transmitted back to the link partner. While in Reverse Loopback mode, all data signals that come

from the MAC are ignored. Through register configuration, data can also be transmitted onto the MAC Interface.

The availability of Loopback depends on the operational mode of the PHY. The Link Status in these loopback

modes is also affected by the operational mode. 表 9-1 lists out the exceptions where Loopbacks are not

available.

表9-1. Loopback Availability Exception

OP MODE

LOOPBACK

EXCEPTION

10M

Copper

PCS

MII

100M

Fiber

PCS

100M

Analog

PCS

100M, 1000M

10M, 100M, 1000M

Digital

Analog

External

PCS

SGMII to RGMII

RGMII to SGMII

External

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表9-1. Loopback Availability Exception (continued)

OP MODE

LOOPBACK

EXCEPTION

MII

100M, 1000M

Analog

100M on Fiber Interface

Media Convertor

100M on Fiber Interface

External

100M, 1000M on Copper Interface

9.3.5 BIST Configuration

The device incorporates an internal PRBS Built-In Self Test (BIST) circuit to accommodate in-circuit testing or

diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data paths. The BIST

can be performed using both internal loopback (digital or analog) or external loopback using a cable fixture. The

BIST simulates pseudo-random data transfer scenarios in format of real packets and Inter-Packet Gap (IPG) on

the lines. The BIST allows full control of the packet lengths and of the IPG.

The BIST is implemented with independent transmit and receive paths, with the transmit block generating a

continuous stream of a pseudo-random sequence. The device generates a 15-bit pseudo-random sequence for

the BIST. The received data is compared to the generated pseudo-random data by the BIST Linear Feedback

Shift Register (LFSR) to determine the BIST pass or fail status. The number of error bytes that the PRBS

checker received is stored in the PRBS_TX_CHK_CTRL register (39h). The status of whether the PRBS checker

is locked to the incoming receive bit stream, whether the PRBS has lost sync, and whether the packet generator

is busy, can be read from the GEN_STATUS2 register (17h). While the lock and sync indications are required to

identify the beginning of proper data reception, for any link failures or data corruption, the best indication is the

contents of the error counter in the PRBS_TX_CHK_CTRL register (39h). The number of received bytes are

stored in PRBS_TX_CHK_BYTE_CNT (3Ah).

The PRBS test can be put in a continuous mode by using the BIST_CONTROL register (16h). In continuous

mode, when one of the PRBS counters reaches the maximum value, the counter starts counting from zero

again. PRBS mode is not applicable in Bridge Modes and should not be used.

9.3.6 Interrupt

The DP83869HM can be configured to generate an interrupt when changes of internal status occur. The

interrupt allows a MAC to act upon the status in the PHY without polling the PHY registers. The interrupt source

can be selected through the interrupt registers, MICR (12h) and FIBER_INT_EN (C18h). The interrupt status can

be read from ISR (13h) and FIBER_INT_STTS (C19h) registers. Some interrupts are enabled by default and can

be disabled through register access. Both the interrupt status registers must be read in order to clear pending

interrupts. Until the pending interrupts are cleared, new interrupts may not be routed to the interrupt pin.

9.3.7 Power-Saving Modes

DP83869HM supports four power saving modes. The details are provided below.

9.3.7.1 IEEE Power Down

The PHY is powered down but access to the PHY through MDIO-MDC pins is retained. This mode can be

activated by asserting external PWDN pin or by setting bit 11 of BMCR (Register 0h).

The PHY can be taken out of this mode by a power cycle, software reset, or by clearing the bit 11 in BMCR

register. However, the external PWDN pin should be deasserted. If the PWDN pin is kept asserted then the PHY

remains in power down.

9.3.7.2 Active Sleep

In this mode, all the digital and analog blocks are powered down. The PHY is automatically powered up when a

link partner is detected. This mode is useful for saving power when the link partner is down or inactive, but PHY

cannot be powered down. In Active Sleep mode, the PHY still routinely sends NLP to the link partner. This mode

can be active by writing 10b to bits [9:8] for PHYCR (Register 10h). Sleep mode cannot be used when Auto-

MDIX is on.

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9.3.7.3 Passive Sleep

This is just like Active sleep except the PHY does not send NLP. This mode can be activated by writing 11b to

bits [9:8] PHYCR (Register 10h). Sleep mode cannot be used when Auto-MDIX is on.

9.3.8 Mirror Mode

In some applications, the orientation of the cable connector can require Copper PMD traces to cross over each

other. This complicates the board layout. The DP83869HM can resolve this issue by implementing mirroring of

the ports inside the device.

In 10/100 operation, the mapping of the port mirroring is shown in 表 9-2. When using mirror mode in 100-Mbps

mode, TI recommends that the user read register 0xA1 and write the same value in register A0h.

表9-2. Mirror Port Configurations in 10/100 Operation

MDI MODE

MIRROR PORT CONFIGURATION

MDI

A →D

B →C

A →D

B →C

MDIX

In Gigabit operation, the mapping of the port mirroring is shown in 表9-3.

表9-3. Mirror Port Configurations in Gigabit Operation

MDI MODE

MIRROR PORT CONFIGURATION

MDI or MDIX

A →D

B →C

C →B

D →A

Mirror mode can be enabled through strap or through register configuration using the Port Mirror Enable bit in

the CFG4 register (address 31h). In Mirror mode, the polarity of the signals is also reversed.

9.3.9 Speed Optimization

Speed optimization, also known as link downshift, enables fallback to 100M operation after multiple consecutive

failed attempts at Gigabit link establishment. Such a case could occur if cabling with only four wires (two twisted

pairs) were connected instead of the standard cabling with eight wires (four twisted pairs).

The number of failed link attempts before falling back to 100M operation is configurable. By default, four failed

link attempts are required before falling back to 100M.

In enhanced mode, fallback to 100M can occur after one failed link attempt if energy is not detected on the C

and D channels. Speed optimization also supports fallback to 10M if link establishment fails in Gigabit and in

100M mode.

Speed optimization can be enabled through register configuration.

9.3.10 Cable Diagnostics

With the vast deployment of Ethernet devices, the need for reliable, comprehensive and user-friendly cable

diagnostic tool is more important than ever. The wide variety of cables, topologies, and connectors deployed

results in the need to non-intrusively identify and report cable faults. The DP83869HM offers Time Domain

Reflectometry (TDR) for Cable Diagnostics.

9.3.10.1 TDR

The DP83869HM uses Time Domain Reflectometry (TDR) to determine the quality of the cables, connectors,

and terminations in addition to estimating the cable length. Some of the possible problems that can be

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diagnosed include opens, shorts, cable impedance mismatch, bad connectors, termination mismatches, cross

faults, cross shorts, and any other discontinuities along the cable.

The DP83869HM transmits a test pulse of known amplitude down each of the two pairs of an attached cable.

The transmitted signal continues down the cable and reflects from each cable imperfection, fault, bad connector,

and from the end of the cable itself. After the pulse transmission, the DP83869HM measures the return time and

amplitude of all these reflected pulses. This technique enables measuring the distance and magnitude

(impedance) of non-terminated cables (open or short), discontinuities (bad connectors), improperly-terminated

cables, and crossed pairs wires with ±1-m accuracy.

The DP83869HM also uses data averaging to reduce noise and improve accuracy. The DP83869HM can record

up to five reflections within the tested pair. If more than 5 reflections are recorded, the DP83869HM saves the

first 5 of them. If a cross fault is detected, the TDR saves the first location of the cross fault and up to 4

reflections in the tested channel. The DP83869HM TDR can measure cables beyond 100 m in length.

For all TDR measurements, the transformation between time of arrival and physical distance is done by the

external host using minor computations (such as multiplication, addition, and lookup tables). The host must know

the expected propagation delay of the cable, which depends, among other things, on the cable category (for

example, CAT5, CAT5e, or CAT6).

TDR measurement is allowed in the DP83869HM in the following scenarios:

• While Link partner is disconnected –cable is unplugged at the other side

• Link partner is connected but remains quiet (for example, in power-down mode)

• TDR could be automatically activated when the link fails or is dropped by setting bit 7 of register 9h (CFG1).

The results of the TDR run after the link fails are saved in the TDR registers.

Software could read these registers at any time to apply post processing on the TDR results. This mode is

designed for cases when the link is dropped due to cable disconnections. After a link failure, for instance, the

line is quiet to allow a proper function of the TDR.

9.3.11 Fast Link Drop

The DP83869HM includes advanced link-down capabilities that support various real-time applications. The link

down mechanism is configurable and includes enhanced modes that allow extremely fast reaction times to link

drops.

First Link Failure

Occurrence

Valid Data

LOW Quality Data / Link Loss

Signal

Link Drop

T1

Link Loss

Indication

(Link LED)

图9-5. Fast Link Drop Mechanism

As described in 图 9-5, the link loss mechanism is based on a time window search period in which the signal

behavior is monitored. The T1 window is set by default to reduce typical link drops to less than 1 ms in 100M and

0.5 ms in 1000M mode.

The DP83869HM supports enhanced modes that shorten the window called Fast Link Down mode. In this mode,

the T1 window is shortened significantly, in most cases less than 10 μs. In this period of time, there are several

criteria allowed to generate link loss event and drop the link:

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1. Loss of descrambler sync

2. Receive errors

3. MLT3 errors

4. Mean Squared Error (MSE)

5. Energy loss

The Fast Link Down functionality allows the use of each of these options separately or in any combination. Note

that because this mode enables extremely quick reaction time, it is more exposed to temporary bad link quality

scenarios.

9.3.12 Jumbo Frames

Conventional Ethernet frames have a maximum size of about 1518 bytes. Jumbo Frames are special packets

with size higher than 1518 bytes, often ranging into several thousands of bytes. Jumbo frames allow Ethernet

systems to transfer large chunks of data in a single frame reducing the processor overhead and increasing

bandwidth efficiency. DP83869 supports Jumbo frames in 1000Mbps and 100Mbps speeds.

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9.4 Device Functional Modes

9.4.1 Copper Ethernet

9.4.1.1 1000BASE-T

The DP83869HM supports the 1000BASE-T standard as defined by the IEEE 802.3 standard. In 1000M mode,

the PHY will use four MDI channels for communication. The 1000BASE-T can work in Auto-Negotiation mode.

The PHY can be configured in 1000BASE-T through the register settings (节9.4.8) or strap settings (节9.5.1.2).

9.4.1.2 100BASE-TX

The DP83869HM supports the 100BASE-TX standard as defined by the IEEE 802.3 standard. In 100M mode,

the PHY will use two MDI channels for communication. The 100BASE-TX can work in Auto-Negotiation mode or

in force mode. The PHY can be configured in 100BASE-TX through the register settings (节 9.4.8) or strap

settings (节 9.5.1.2). When using DP83869 in force 100Base-TX mode, it is required to enable Robust Auto-

MDIX feature from register 1Eh.

9.4.1.3 10BASE-Te

The DP83869HM supports the 10BASE-Te standard as defined by the IEEE 802.3 standard. In 100M mode, the

PHY will use two MDI channels for communication. The 10BASE-Te can work in Auto-Negotiation mode or in

force mode. The PHY can be configured in 10BASE-Te through the register settings (节 9.4.8) or strap settings

(节9.5.1.2).

9.4.2 Fiber Ethernet

9.4.2.1 1000BASE-X

The DP83869HM supports the 1000Base-X Fiber Ethernet protocol as defined in IEEE 802.3 standard. In

1000M Fiber mode, the PHY will use two differential channels for communication. In fiber mode, the speed is not

decided through auto-negotiation. Both sides of the link must be configured to the same operating speed. The

PHY can be configured to operate in 1000BASE-X through the register settings (节 9.4.8) or strap settings (节

9.5.1.2).

9.4.2.2 100BASE-FX

The DP83869HM supports the 100Base-FX Fiber Ethernet protocol as defined in IEEE 802.3 standard. In 100M

Fiber mode, the PHY will use two differential channels for communication. In fiber mode, the speed is not

decided through auto-negotiation. Both sides of the link must be configured to the same operating speed. The

PHY can be configured to operate in 100BASE-X through register settings (节 9.4.8) or strap settings (节

9.5.1.2).

9.4.3 Serial GMII (SGMII)

The Serial Gigabit Media Independent Interface (SGMII) provides a means of conveying network data and port

speed between a 100/1000 PHY and a MAC with significantly less signal pins (4 or 6 pins) than required for

GMII (24 pins) or RGMII (12 pins). The SGMII interface uses 1.25-Gbps LVDS differential signaling which has

the added benefit of reducing EMI emissions relative to GMII or RGMII.

Because the internal clock and data recovery circuitry (CDR) of DP83869HM can detect the transmit timing of

the SGMII data, TX_CLK is not required. The DP83869HM will support only 4-wire SGMII mode. Two differential

pairs are used for the transmit and receive connections. Clock and data recovery are performed in the MAC and

in the PHY, so no additional differential pair is required for clocking.

The 1.25-Gbps rate of SGMII is excessive for 100-Mbps and 10-Mbps operation. When operating in 100-Mbps

mode, the PHY elongates the frame by replicating each frame byte 10 times and when in 10-Mbps mode the

PHY elongates the frame by replicating each frame byte 100 times. This frame elongation takes place above the

IEEE 802.3 PCS layer, thus the start of frame delimiter only appears once per frame.

The SGMII interface includes Auto-Negotiation capability. Auto-Negotiation provides a mechanism for control

information to be exchanged between the PHY and the MAC. This allows the interface to be automatically

configured based on the media speed mode resolution on the MDI side. In MAC loopback mode, the SGMII

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speed is determined by the MDI speed selection. The SGMII interface works in both Auto-Negotiation and forced

speed mode during the MAC loopback operation. SGMII Auto-Negotiation is the default mode of the operation.

The SGMII Auto-Negotiation process can be disabled and the SGMII speed mode can be forced to the MDI

resolved speed. The SGMII forced speed mode can be enabled with the MDI auto-negotiation or MDI manual

speed mode. SGMII Auto-Negotiation can be disabled through the SGMII_AUTONEG_EN register bit in the

CFG2 register (address 14h).

The 10M_SGMII_RATE_ADAPT bit (bit 7) of 10M_SGMII_CFG register (16Fh) needs to be cleared for enabling

10M SGMII operation.

SGMII is enabled through a resistor strap option. See 节9.5.1 for details.

All SGMII connections must be AC-coupled through an 0.1-µF capacitor.

The connection diagrams for 4-wire SGMII is shown in 图9-6.

备注

MII Isolate (bit 10 in register 0h) will not isolate SGMII pins. SGMII can be disabled through register

1DFh for isolating SGMII pins.

PHY

MAC

0.1 µF

SGMII_SIP

SGMII_SIN

0.1 µF

SGMII_SOP

SGMII_SON

图9-6. SGMII 4-Wire Connections

9.4.4 Reduced GMII (RGMII)

The Reduced Gigabit Media Independent Interface (RGMII) is designed to reduce the number of pins required to

interconnect the MAC and PHY (12 pins for RGMII relative to 24 pins for GMII). To accomplish this goal, the data

paths and all associated control signals are reduced and are multiplexed. Both rising and trailing edges of the

clock are used. For Gigabit operation, the GTX_CLK and RX_CLK clocks are 125 MHz, and for 10- and 100-

Mbps operation, the clock frequencies are 2.5 MHz and 25 MHz, respectively.

For more information about RGMII timing, see the RGMII Interface Timing Budgets application report

(SNLA243).

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9.4.4.1 1000-Mbps Mode Operation

All RGMII signals are positive logic. The 8-bit data is multiplexed by taking advantage of both clock edges. The

lower 4 bits are latched on the positive clock edge and the upper 4 bits are latched on trailing clock edge. The

control signals are multiplexed into a single clock cycle using the same technique.

To reduce power consumption of RGMII interface, (TX_EN - TX_ER) and (RX_DV - RX_ER) are encoded in a

manner that minimizes transitions during normal network operation. TX_CTRL pin will denote TX_EN on rising

edge of GTX_CLK and will denote a logic derivative of TX_EN and TX_ER on the falling edge of GTX_CLK.

RX_CTRL will denote RX_DV on rising edge of RX_CLK and will denote a logic derivative of RX_DV and

RX_ER on the falling edge of RX_CLK. The encoding for the TX_ER and RX_ER is given in 方程式 1 and 方程

式2:

TX_ER = GMII_TX_ER (XOR) GMII_TX_EN

(1)

where

• GMII_TX_ER and GMII_TX_EN are logical equivalent signals in GMII standard.

RX_ER = GMII_RX_ER (XOR) GMII_RX_DV

(2)

where

• GMII_RX_ER, and GMII_RX_DV are logical equivalent signals in GMII standard.

When receiving a valid frame with no error, RX_CTRL = True is generated as a logic high on the rising edge of

RX_CLK and RX_CTRL = False is generated as a logic high at the falling edge of RX_CLK. When no frame is

being received, RX_CTRL = False is generated as a logic low on the rising edge of RX_CLK and RX_CTRL =

False is generated as a logic low on the falling edge of RX_CLK.

The TX_CTRL is treated in a similar manner. During normal frame transmission, the signal stays at a logic high

for both edges of GTX_CLK and during the period between frames where no error is indicated, the signal stays

low for both edges.

9.4.4.2 1000-Mbps Mode Timing

The DP83869HM provides configurable clock skew for the GTX_CLK and RX_CLK to optimize timing across the

interface. The transmit and receive paths can be optimized independently. Both the transmit and receive path

support 16 programmable RGMII delay modes through register configuration.

The timing paths can either be configured for Aligned mode or Shift mode. In Aligned mode, no clock skew is

introduced. In Shift mode, the clock skew can be introduced in 0.5-ns increments or in 0.25-ns increments

(through register configuration). Configuration of the Aligned mode or Shift mode is accomplished through the

RGMII Control Register (RGMIICTL), address 32h. In Shift mode, the clock skew can be adjusted using the

RGMII Delay Control Register (RGMIIDCTL), address 86h. By default RGMII shift mode will be activated. Both

transmit and receive signals will be delayed by 2ns.

9.4.4.3 10- and 100-Mbps Mode

When the RGMII interface is operating in the 100-Mbps mode, the RGMII clock rate is reduced to 25 MHz. For

10-Mbps operation, the clock is further reduced to 2.5 MHz. In the RGMII 10/100 mode, the transmit clock RGMII

TX_CLK is generated by the MAC and the receive clock RGMII RX_CLK is generated by the PHY. During the

packet receiving operation, the RGMII RX_CLK may be stretched on either the positive or negative pulse to

accommodate the transition from the free-running clock to a data synchronous clock domain. When the speed of

the PHY changes, a similar stretching of the positive or negative pulses is allowed. No glitch is allowed on the

clock signals during clock speed transitions.

This interface operates at 10- and 100-Mbps speeds the same way it does at 1000-Mbps mode with the

exception that the data may be duplicated on the falling edge of the appropriate clock.

The MAC holds the RGMII TX_CLK low until it has ensured that it is operating at the same speed as the PHY.

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PHY

MAC

TX_CTRL

GTX_CLK

TX_D [3:0]

RX_CTRL

RX_CLK

RX_D [3:0]

图9-7. RGMII Connections

9.4.5 Media Independent Interface (MII)

DP83869HM also supports MII mode when the PHY is working in 100M and 10M speeds. The user will have to

ensure that the PHY links in either 100-Mbps or 10-Mbps mode. MII mode cannot be used in 1000-Mbps mode.

When using auto-negotiation to resolve MDI speed, TI recommends to turn off the gigabit speed advertisement

through register 0x9 to ensure that the PHY does not link up at 1000-Mbps speed. The Media Independent

Interface is a synchronous 4-bit wide nibble data interface that connects the PHY to the MAC in 100BASE-FX,

100BASE-TX and 10BASE-Te modes. The RX_ER signal must be properly muxed by setting Register 18h to

equal 0xE. The MII is fully compliant with IEEE 802.3-2002 clause 22.

The MII signals are summarized in 表9-4:

表9-4. MII Signals

FUNCTION

PINS

TX_D[3:0]

Data Signals

RX_D[3:0]

TX_EN, TX_ER

RX_DV, RX_ER

Transmit and Receive Signals

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TX_CLK

TX_EN

TX_D[3:0]

RX_CLK

RX_DV

PHY

MAC

RX_ER

RX_D[3:0]

25MHz Clock

图9-8. MII Signaling

9.4.6 Bridge Modes

The DP83869HM supports Bridge modes to translate data between two MAC interface types. Bridge mode is

activated through straps or register configuration. The two types of Bridge mode supported by DP83869HM are:

• RGMII-to-SGMII mode

• SGMII-to-RGMII mode

9.4.6.1 RGMII-to-SGMII Mode

RGMII

SGMII

RX_D[3:0]

RX_CLK

RX_D[3:0]

RX_CLK

SOP

SON

SIP

SIN

RX_CTRL

Ethernet MAC

DP83869

Ethernet PHY

SIP

SIN

SOP

SON

TX_D[3:0]

TX_CLK

TX_D[3:0]

TX_CLK

TX_CTRL

图9-9. DP83869HM RGMII-to-SGMII Bridge

In RGMII-to-SGMII mode Ethernet MAC is connected to the RGMII pins of the DP83869HM and PHY is

connected to the SGMII pins of the DP83869. In this mode, DP83869HM will configure SGMII in Auto Mode. In

Auto mode, the RGMII side will automatically adjust to the link-up speed on the SGMII side. In case where the

PHY is does not have a link, the RGMII clock frequency will default to 2.5 MHz.

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After auto-negotiation is completed on the PHY side, the link capabilities are communicated to DP83869HM over

the SGMII interface. However, this information is conveyed to the Ethernet MAC through RGMII Inband signaling

and RX_CLK adjustment. The MAC can also read this information from the DP83869.

In Bridge mode, the DP83869HM SMI will act as slave mode to MAC.

9.4.6.2 SGMII-to-RGMII Mode

SGMII

RGMII

TX_D[3:0]

TX_CLK

RX_D[3:0]

RX_CLK

SOP

SON

SIP

SIN

TX_CTRL

RX_CTRL

Ethernet MAC

DP83869

Ethernet PHY

SIP

SIN

SOP

SON

RX_D[3:0]

RX_CLK

TX_D[3:0]

TX_CLK

RX_CTRL

TX_CTRL

图9-10. DP83869HM SGMII-to-RGMII Bridge

In SGMII-to-RGMII mode, Ethernet MAC is connected to the SGMII pins of the DP83869HM and PHY is

connected to the RGMII pins of the DP83869. In this mode, DP83869HM will configure SGMII in Auto. In Auto

mode, SGMII will adapt the link speed based on RGMII.

After auto-negotiation is completed on the PHY side, the link capabilities are communicated to DP83869HM over

the RGMII interface. However, this information needs to be conveyed to the Ethernet MAC as well. The MAC can

read this information from the DP83869HM through the registers.

In SGMII-to-RGMII Bridge mode, the DP83869 will act as RGMII MAC for the Ethernet PHY. The DP83869 RX

pins will act as output pins from the DP83869 to the Ethernet PHY TX pins, and the DP83869 TX pins will act as

input pins for the Ethernet PHY RX pins.

In both Bridge modes, PRBS mode of the PHY is not applicable and should not be used.

LEDs, if used, will indicate status on the RGMII side in both Bridge Modes.

9.4.7 Media Convertor Mode

In media convertor mode, DP83869HM will translate data between copper and fiber interface for 1000M and

100M speeds. Media convertor mode can be activated through the straps. The DP83869HM supports

Unmanaged Media Convertor mode.

Copper

Cable

Fiber

Cable

Copper

Link Partner

Fiber

Link Partner

DP83869

图9-11. Media Convertor Mode

In Unmanaged mode, Media Convertor can still be activated via straps but register configuration option are also

used for enhanced features like changing LED configuration, Capabilities programming broadcasted in Auto-Neg

etc may need configuration and are supported through register programming. Register access to the PHY is

retained. This provides additional flexibility to use other features supported by the PHY.

Copper interface will support auto-negotiation, but the user will have to ensure that the speed negotiated on the

copper side matches the speed fixed on the fiber side. In cases of speed mismatch between copper and fiber,

interface data transmission will not be successful.

The DP83869HM also supports Link Loss Pass Through in 100M mode. In a network containing two media

convertors where the link is dropped on one end of the system, a link loss indication is passed through all the

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way to the far end. The Link Loss Pass-Through is enabled or disabled through straps. An example is shown in

图9-12.

1. A fault occurs on copper link at position 1 at Near End Link Partner.

2. Media Converter will disable Fiber TX link at position 2.

3. The Media Converter in the system will lose link at position 3.

4. The second Media Converter disables copper link and the far end link partner loses the copper link.

Copper

Cable

Copper

Cable

2

3

Near End

Link Partner

DP83869

Media Convertor

DP83869

Media Convertor

Far End

Link Partner

1

4

图9-12. Link Loss Pass-Through

9.4.8 Register Configuration for Operational Modes

The operational modes of DP83869HM are configured through the OPMODE[0], OPMODE[1], OPMODE[2]

straps. When operational modes are changed through register access, additional configurations are necessary

apart from 1DFh. The following sections contain necessary information for changing operational modes through

the registers. For modes not listed below, only configuring register 1DFh is sufficient.

9.4.8.1 RGMII-to-Copper Ethernet Mode

Required register configuration when switching to RGMII-to-Copper mode using software:

• Write 0x0040 to register 1DFh // Set Operation Mode to RGMII to Copper

• Write 0x1140 to register 0h // Reset BMCR

• Write 0x01E1 to register 4h // Advertise 100Base-TX and 10Base-T ability

• Write 0x0300 to register 9h // Reset GEN_CFG1

• Write 0x5048 to register 10h // Reset PHY_CONTROL

• Write 0x4000 to register 1Fh // Software Reset

9.4.8.2 RGMII-to-1000Base-X Mode

• Write 0x0041 to register 1DFh // Set Operation Mode to RGMII to 1000Base-X

• Write 0x1140 to register C00h // Reset FX_CTRL

• Write 0x4000 to register 1Fh// Software Reset

9.4.8.3 RGMII-to-100Base-FX Mode

• Write 0x0042 to register 1DFh // Set Operation Mode to RGMII to 100Base-FX

• Write 0x2100 to register C00h // Set Speed to 100 Mbps

• Write 0x4000 to register 1Fh // Software Reset

9.4.8.4 RGMII-to-SGMII Bridge Mode

• Write 0x0043 to register 1DFh // Set Operation Mode to RGMII to SGMII

• Write 0x1140 to register C00h // Reset FX_CTRL

• Write 0x4000 to register 1Fh // Software Reset

9.4.8.5 1000M Media Convertor Mode

• Write 0x0044 to register 1DFh // Set Operation Mode to 1000Base-T to 1000Base-X

• Write 0x1140 to register 0h // Reset BMCR

• Write 0x5048 to register 10h // Reset PHY_CONTROL

• Write 0x1140 to register C00h // Reset FX_CTRL

• Write 0x4000 to register 1Fh // Software Reset

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9.4.8.6 100M Media Convertor Mode

• Write 0x0045 to register 1DFh // Set Operation Mode to 100Base-T to 100Base-FX

• Write 0x1140 to register 0h // Reset BMCR

• Write 0x5048 to register 10h // Reset PHY_CONTROL

• Write 0x000E to register 18h // Mux LED_1 to function as RX_ER

• Write 0x4000 to register 1Fh // Software Reset

9.4.8.7 SGMII-to-Copper Ethernet Mode

• Write 0x0046 to register 1DFh // Set Operation Mode to SGMII to Copper

• Write 0x1140 to register 0h // Reset BMCR

• Write 0xB00 to register 9h // Advertise 1000Base-T ability

• Write 0x5048 to register 10h // Reset PHY_CONTROL

• Write 0x1140 to register C00h // Reset FX_CTRL

• Write 0x4000 to register 1Fh // Software Reset

9.4.9 Serial Management Interface

The Serial Management Interface (SMI), provides access to the DP83869HM internal register space for status

information and configuration. The SMI is compatible with IEEE 802.3-2002 clause 22. The implemented register

set consists of the registers required by the IEEE 802.3, plus several others to provide additional visibility and

controllability of the DP83869HM device.

The SMI includes the MDC management clock input and the management MDIO data pin. The MDC clock is

sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of

25 MHz. MDC is not expected to be continuous, and can be turned off by the external management entity when

the bus is idle.

The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched

on the rising edge of the MDC clock. The MDIO pin requires a pullup resistor (2.2 kΩ) which, during IDLE and

turnaround, pulls MDIO high.

Up to 16 PHYs can share a common SMI bus. To distinguish between the PHYs, a 4-bit address is used. During

power-up reset, the DP83869HM latches the PHY_ADD configuration pins to determine its address.

The management entity must not start an SMI transaction in the first cycle after power-up reset. To maintain valid

operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is deasserted. In normal

MDIO transactions, the register address is taken directly from the management-frame reg_addr field, thus

allowing direct access to 32 16-bit registers (including those defined in IEEE 802.3 and vendor specific). The

data field is used for both reading and writing. The Start code is indicated by a <01> pattern. This pattern makes

sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time

inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no

device may actively drive the MDIO signal during the first bit of turnaround. The addressed DP83869HM drives

the MDIO with a zero for the second bit of turnaround and follows this with the required data. 图 9-13 shows the

timing relationship between MDC and the MDIO as driven and received by the Station (STA) and the

DP83869HM (PHY) for a typical register read access.

For write transactions, the station-management entity writes data to the addressed DP83869, thus eliminating

the requirement for MDIO turnaround. The turnaround time is filled by the management entity by inserting <10>.

图 9-13 shows the timing relationship for a typical MII register write access. The frame structure and general

read and write transactions are shown in 表9-5, 图9-13, and 图9-14.

表9-5. Typical MDIO Frame Format

TYPICAL MDIO FRAME FORMAT

Read Operation

Write Operation

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图9-13. Typical MDC/MDIO Read Operation

图9-14. Typical MDC/MDIO Write Operation

9.4.9.1 Extended Address Space Access

The DP83869HM SMI function supports read or write access to the extended register set using registers

REGCR (Dh) and ADDAR (Eh) and the MDIO Manageable Device (MMD) indirect method defined in IEEE

802.3ah Draft for clause 22 for accessing the clause 45 extended register set.

The standard register set, MDIO registers 0 to 31, is accessed using the normal direct-MDIO access or the

indirect method, except for register REGCR (Dh) and ADDAR (Eh) which is accessed only using the normal

MDIO transaction. The SMI function ignores indirect accesses to these registers.

REGCR (Dh) is the MDIO Manageable MMD access control. In general, register REGCR(4:0) is the device

address DEVAD that directs any accesses of ADDAR (Eh) register to the appropriate MMD.

The DP83869HM supports one MMD device address. The vendor-specific device address DEVAD[4:0] = 11111

is used for general MMD register accesses.

All accesses through registers REGCR and ADDAR must use the correct DEVAD. Transactions with other

DEVAD are ignored. REGCR[15:14] holds the access function: address (00), data with no post increment (01),

data with post increment on read and writes (10) and data with post increment on writes only (11).

• ADDAR is the address and data MMD register. ADDAR is used in conjunction with REGCR to provide the

access to the extended register set. If register REGCR[15:1] is 00, then ADDAR holds the address of the

extended address space register. Otherwise, ADDAR holds the data as indicated by the contents of its

address register. When REGCR[15:14] is set to 00, accesses to register ADDAR modify the extended

register set address register. This address register must always be initialized to access any of the registers

within the extended register set.

• When REGCR[15:14] is set to 01, accesses to register ADDAR access the register within the extended

register set selected by the value in the address register.

• When REGCR[15:14] is set to 10, access to register ADDAR access the register within the extended register

set selected by the value in the address register. After that access is complete, for both reads and writes, the

value in the address register is incremented.

• When REGCR[15:14] is set to 11, access to register ADDAR access the register within the extended register

set selected by the value in the address register. After that access is complete, for write accesses only, the

value in the address register is incremented. For read accesses, the value of the address register remains

unchanged.

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The following sections describe how to perform operations on the extended register set using register REGCR

and ADDAR. The descriptions use the device address for general MMD register accesses (DEVAD[4:0] = 11111).

9.4.9.1.1 Write Address Operation

1. Write the value 0x1F (address function field = 00, DEVAD = 31) to register REGCR.

2. Write the desired register address to register ADDAR.

Subsequent writes to register ADDAR (step 2) continue to write the address register.

9.4.9.1.2 Read Address Operation

To read the address register:

1. Write the value 0x1F (address function field = 00, DEVAD = 31) to register REGCR.

2. Read the register address from register ADDAR.

9.4.9.1.3 Write (No Post Increment) Operation

To write a register in the extended register set:

1. Write the value 0x1F (address function field = 00, DEVAD = 31) to register REGCR.

2. Write the desired register address to register ADDAR.

3. Write the value 0x401F (data, no post increment function field = 01, DEVAD = 31) to register REGCR.

4. Write the content of the desired extended register set register to register ADDAR.

Subsequent writes to register ADDAR (step 4) continue to rewrite the register selected by the value in the

address register.

Note: steps (1) and (2) can be skipped if the address register was previously configured.

9.4.9.1.4 Read (No Post Increment) Operation

To read a register in the extended register set:

1. Write the value 0x1F (address function field = 00, DEVAD = 31) to register REGCR.

2. Write the desired register address to register ADDAR.

3. Write the value 0x401F (data, no post increment function field = 01, DEVAD = 31) to register REGCR.

4. Read the content of the desired extended register set register to register ADDAR.

Subsequent reads from register ADDAR (step 4) continue reading the register selected by the value in the

address register.

Note: steps (1) and (2) can be skipped if the address register was previously configured.

9.4.9.1.5 Write (Post Increment) Operation

1. Write the value 0x1F (address function field = 00, DEVAD = 31) to register REGCR.

2. Write the register address from register ADDAR.

3. Write the value 0x801F (data, post increment on reads and writes function field = 10, DEVAD = 31) or the

value 0xC01F (data, post increment on writes function field = 11. DEVAD = 31) to register REGCR.

4. Write the content of the desired extended register set register to register ADDAR.

Subsequent writes to register ADDAR (step 4) write the next higher addressed data register selected by the

value of the address register. The address register is incremented after each access.

9.4.9.1.6 Read (Post Increment) Operation

To read a register in the extended register set and automatically increment the address register to the next

higher value following the write operation:

1. Write the value 0x1F (address function field = 00, DEVAD = 31) to register REGCR.

2. Write the desired register address to register ADDAR.

3. Write the value 0x801F (data, post increment on reads and writes function field = 10, DEVAD = 31) to

register REGCR.

4. Read the content of the desired extended register set register to register ADDAR.

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Subsequent reads to register ADDAR (step 4) read the next higher addressed data register selected by the

value of the address register. The address register is incremented after each access.

9.4.9.1.7 Example of Read Operation Using Indirect Register Access

Read register 170h.

1. Write register Dh to value 0x1F.

2. Write register Eh to value 0x170

3. Write register Dh to value 0x401F.

4. Read register Eh.

The expected default value is 0xC10.

9.4.9.1.8 Example of Write Operation Using Indirect Register Access

Write register 170h to value 0x0C50.

1. Write register Dh to value 0x1F.

2. Write register Eh to value 0x170

3. Write register Dh to value 0x401F.

4. Write register Eh to value 0xC50.

This write disables the output clock on the CLK_OUT pin.

9.4.10 Auto-Negotiation

All 1000BASE-T PHYs are required to support Auto-Negotiation. The Auto-Negotiation function in 1000BASE-T

has three primary purposes:

• Auto-Negotiation of Speed and Duplex Selection

• Auto-Negotiation of Master or Slave Resolution

• Auto-Negotiation of Pause or Asymetrical Pause Resolution

9.4.10.1 Speed and Duplex Selection - Priority Resolution

The Auto-Negotiation function provides a mechanism for exchanging configuration information between the two

ends of a link segment. This mechanism is implemented by exchanging Fast Link Pulses (FLP). FLPs are burst

pulses that provide the signaling used to communicate the abilities between two devices at each end of a link

segment. For further details regarding Auto-Negotiation, refer to Clause 28 of the IEEE 802.3 specification. The

DP83869HM supports 1000BASE-T, 100BASE-TX, and 1000BASE-T modes of operation. The process of Auto-

Negotiation ensures that the highest performance protocol is selected (that is, priority resolution) based on the

advertised abilities of the Link Partner and the local device.

9.4.10.2 Master and Slave Resolution

If 1000BASE-T mode is selected during the priority resolution, the second goal of Auto-Negotiation is to resolve

Master or Slave configuration. The Master mode priority is given to the device that supports multiport nodes,

such as switches and repeaters. Single node devices such as DTE or NIC card takes lower Master mode priority.

9.4.10.3 Pause and Asymmetrical Pause Resolution

When Full-Duplex operation is selected during priority resolution, the Auto-Negotiation also determines the Flow

Control capabilities of the two link partners. Flow control was originally introduced to force a busy station’s Link

Partner to stop transmitting data in Full-Duplex operation. Unlike Half-Duplex mode of operation where a link

partner could be forced to back off by simply generating collisions, the Full-Duplex operation needed a

mechanism to slow down transmission from a link partner in the event that the receiving station’s buffers are

becoming full. A new MAC control layer was added to handle the generation and reception of Pause Frames.

Each MAC Controller has to advertise whether it is capable of processing Pause Frames. In addition, the MAC

Controller advertises if Pause frames can be handled in both directions, that is, receive and transmit. If the MAC

Controller only generates Pause frames but does not respond to Pause frames generated by a link partner, it is

called Asymmetrical Pause. The advertisement of Pause and Asymmetrical Pause capabilities is enabled by

writing 1 to bits 10 and 11 of ANAR (register address 4h). The link partner’s Pause capabilities is stored in

ANLPAR (register address 5h) bits 10 and 11. The MAC Controller has to read from ANLPAR to determine which

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Pause mode to operate. The PHY layer is not involved in Pause resolution other than simply advertising and

reporting of Pause capabilities.

9.4.10.4 Next Page Support

The DP83869HM supports the Auto-Negotiation Next Page protocol as required by IEEE 802.3 clause

28.2.4.1.7. The ANNPTR 7h allows for the configuration and transmission of the Next Page. Refer to clause 28

of the IEEE 802.3 standard for detailed information regarding the Auto-Negotiation Next Page function.

9.4.10.5 Parallel Detection

The DP83869HM supports the Parallel Detection function as defined in the IEEE 802.3 specification. Parallel

Detection requires the 10/100-Mbps receivers to monitor the receive signal and report link status to the Auto-

Negotiation function. Auto-Negotiation uses this information to configure the correct technology in the event that

the Link Partner does not support Auto-Negotiation, yet is transmitting link signals that the 10BASE-Te or

100BASE-X PMA recognize as valid link signals.

If the DP83869HM completes Auto-Negotiation as a result of Parallel Detection without Next Page operation, bits

5 and 7 of ANLPAR (register address 5h) are set to reflect the mode of operation present in the Link Partner.

Note that bits 4:0 of the ANLPAR are also set to 00001 based on a successful parallel detection to indicate a

valid 802.3 selector field. Software may determine that the negotiation is completed through Parallel Detection

by reading 0 in bit 0 of ANER (register address 6h) after Auto-Negotiation Complete—bit 5 of BMSR (register

address 1h)—is set. If the PHY is configured for parallel detect mode and any condition other than a good link

occurs, the parallel detect fault—bit 4 of ANER (register address 6h)—sets.

9.4.10.6 Restart Auto-Negotiation

If a link is established by successful Auto-Negotiation and then lost, the Auto-Negotiation process resumes to

determine the configuration for the link. This function ensures that a link can be re-established if the cable

becomes disconnected and reconnected. After Auto-Negotiation is completed, it may be restarted at any time by

writing 1 to bit 9 of the BMCR (register address 0h). A restart Auto-Negotiation request from any entity, such as a

management agent, causes DP83869HM to halt data transmission or link pulse activity until the break_link_timer

expires. Consequently, the Link Partner goes into link fail mode and the resume Auto-Negotiation. The

DP83869HM resumes Auto-Negotiation after the break_link_timer has expired by transmitting FLP (Fast Link

Pulse) bursts.

9.4.10.7 Enabling Auto-Negotiation Through Software

If Auto-Negotiation is disabled by MDIO access, and the user desires to restart Auto-Negotiation, this could be

accomplished by software access. Bit 12 of BMCR (register address 0h) should be cleared and then set for

Auto-Negotiation operation to take place.

If Auto-Negotiation is disabled by strap option, Auto-Negotiation cannot be re-enabled.

9.4.10.8 Auto-Negotiation Complete Time

Parallel detection and Auto-Negotiation typically take 2-3 seconds to complete. In addition, Auto-Negotiation with

next page exchange takes approximately 2-3 seconds to complete, depending on the number of next pages

exchanged. Refer to Clause 28 of the IEEE 802.3 standard for a full description of the individual timers related to

Auto-Negotiation.

9.4.10.9 Auto-MDIX Resolution

The DP83869HM can determine if a straight or crossover cable is used to connect to the link partner. It can

automatically re-assign channel A and B to establish link with the link partner, (and channel C and D in

1000BASE-T mode). Auto-MDIX resolution precedes the actual Auto-Negotiation process that involves

exchange of FLPs to advertise capabilities. Automatic MDI/MDIX is described in IEEE 802.3 Clause 40, section

40.8.2. It is not a required implementation for 10BASE-Te and 100BASE-TX.

Auto-MDIX can be enabled or disabled by strap, using the AMDIX Disable strap, or by register configuration,

using bit 6 of the PHYCR register (address 10h). When Auto-MDIX is disabled, the PMA is forced to either MDI

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(straight) or MDIX (crossed). Manual configuration of MDI or MDIX can also be accomplished by strap, using the

Force MDI/X strap, or by register configuration, using bit 5 of the PHYCR register.

For 10/100, Auto-MDIX is independent of Auto-Negotiation. Auto-MDIX works in both Auto-Negotiation mode

and manual forced speed mode.

9.5 Programming

9.5.1 Strap Configuration

The DP83869HM uses many of the functional pins as strap options to place the device into specific modes of

operation. The values of these pins are sampled at power up or hard reset. During software resets, the strap

options are internally reloaded from the values sampled at power up or hard reset. The strap option pin

assignments are defined below.

Configuration of the device may be done through the strap pins or through the management register interface. A

pullup resistor and/or a pulldown resistor of suggested values may be used to set the voltage ratio of the strap

pin input and the supply to select one of the possible selected modes.

The MAC interface pins must support I/O voltages of 3.3 V, 2.5 V, and 1.8 V. As the strap inputs are implemented

on these pins, the straps must also support operation at 3.3-V, 2.5-V, and 1.8-V supplies depending on what

voltage was selected for I/O. RX_D0 and RX_D1 pins are 4 level strap pins. All other strap pins have two levels.

VDDIO

Rhi

V

STRAP

9kꢀ

25%

Rlo

DP83869

图9-15. Strap Circuit

表9-6. 4-Level Strap Resistor Ratio

TARGET VOLTAGE

IDEAL RESISTORS

MODE

Vmin (V)

0

Vtyp (V)

Vmax (V)

Rhi (kΩ)

Rlo (kΩ)

OPEN

2.49

0

1

2

3

0

0.093 × VDDIO

0.184 × VDDIO

0.280 × VDDIO

0.888 × VDDIO

OPEN

10

0.136 × VDDIO

0.219 × VDDIO

0.6 × VDDIO

0.165 × VDDIO

0.255 × VDDIO

0.783 × VDDIO

5.76

2.49

OPEN

表9-7. 2-Level Strap Resistor Ratio

TARGET VOLTAGE

IDEAL RESISTORS

MODE

Vmin (V)

0

Vtyp (V)

Vmax (V)

Rhi (kΩ)

OPEN

2.49

Rlo (kΩ)

2.49

0

1

0.18 x VDDIO

0.88 x VDDIO

0.5 x VDDIO

OPEN

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9.5.1.1 Straps for PHY Address

表9-8. PHY Strap Table

PIN NAME

STRAP NAME

PIN #

DEFAULT

PHY_ADD1

PHY_ADD0

MODE 0

MODE 1

MODE 2

MODE 3

0

RX_D0

PHY_ADD[1:0]

33

00

0

1

0

1

PHY_ADD3

PHY_ADD2

MODE 0

MODE 1

MODE 2

MODE 3

0

1

0

1

0

1

RX_D1

PHY_ADD[3:2]

34

00

9.5.1.2 Strap for DP83869HM Functional Mode Selection

表9-9. Functional Mode Strap Table

OPMO OPMO OPMO

PIN NAME

STRAP NAME

PIN #

DEFAULT

FUNCTIONAL MODES

DE[2]

DE[1]

DE[0]

RGMII to Copper (1000Base-T/

100Base-TX/10Base-Te)

0

JTAG_TDO/

GPIO_1

OPMODE[0]

22

0

1

0

1

0

1

0

1

0

1

RGMII to 1000Base-X

RGMII to 100Base-FX

RX_D3

RX_D2

OPMODE[1]

OPMODE[2]

36

35

0

RGMII-SGMII Bridge Mode

1000Base-T to 1000Base-X

100Base-T to 100Base-FX

SGMII to Copper (1000Base-T/

100Base-TX/10Base-Te)

1

0

1

JTAG for boundary scan

9.5.1.3 LED Default Configuration Based on Device Mode

Based on the straped OP_MODE, the following table summarizes the default of LED0, LED1 and LED2.

表9-10. LED Defaults

OP_MODE[2:0]

Mode Description

LED0 Default

LED1 Default

LED2 Default

000

RGMII to Copper

10/100M/1G Link-up:

1G Link-up: Stable ON

TX and RX Activity

(1000Base-TX/100Base- Stable ON

TX/10-T)

001

010

011

RGMII to 1000Base-X

RGMII to 100Base-FX

RGMII to SGMII

Fiber Link-up: Stable ON RX Activity

RX Activity

SGMII Link-up from

SGMII 1G Link-up: Stable TX and RX Activity

ON

10/100M/1G: Stable ON

100

Copper to 1000Base-X

Copper Link Status Link

established: Stable ON

Fiber Link established:

Stable ON

TX and RX Activity

Link dropped to 100M or

half duplex: LED blink

(error Condition)

101

Copper to 100Base-FX

Copper Link Status Link

established: Stable ON

Fiber Link established:

Stable ON

TX and RX Activity

Link dropped to 100M or

half duplex: LED blink

(error Condition)

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表9-10. LED Defaults (continued)

OP_MODE[2:0]

Mode Description

LED0 Default

LED1 Default

LED2 Default

110

SGMII to Copper

10/100M/1G Link-up:

1G Link-up: Stable ON

TX and RX Activity

(1000Base-TX/100Base- Stable ON

TX/10-T)

9.5.1.4 Straps for RGMII/SGMII to Copper

表9-11. Copper Ethernet Strap Table

PIN NAME

STRAP NAME

PIN #

DEFAULT

ANEG_ ANEGS ANEGS

FUNCTION

DIS

EL_1

EL_0

Auto-negotiation, 1000/100/10

advertised, Auto MDI-X

LED_0

ANEG_DIS

47

0

Auto-negotiation, 1000/100

advertised, Auto MDI-X

0

1

0

Auto-negotiation, 100/10 advertised,

Auto-MDI-X

LED_1

ANEGSEL_0

46

0

1

0

1

0

1

NA

Forced 100M, full duplex, MDI

mode

1

0

1

LED_2

ANEGSEL_1

MIRROR_EN

45

38

0

Forced 100M, full duplex, MDI-X

mode

0

1

Port Mirroring Disabled

Port Mirroring Enabled

RX_CTRL

9.5.1.5 Straps for RGMII to 1000Base-X

表9-12. 1000Base-X Strap Table

PIN NAME

STRAP NAME

PIN #

DEFAULT

0

1

0

1

Fiber Auto-negotiation ON

Fiber Force mode

LED_0

ANEG_DIS

47

46

0

Signal Detect disable on Pin 24

Configure Pin 24 as Signal Detect Pin

LED_1

ANEGSEL_0

0

9.5.1.6 Straps for RGMII to 100Base-FX

表9-13. 100Base-X Strap Table

PIN NAME

STRAP NAME

PIN #

DEFAULT

0

Signal Detect disable on Pin 24

LED_1

ANEGSEL_0

46

0

1

Configure Pin 24 as Signal Detect Pin

9.5.1.7 Straps for Bridge Mode (SGMII-RGMII)

表9-14. Bridge Mode Strap Table

PIN NAME

STRAP NAME

PIN #

DEFAULT

0

1

RGMII to SGMII ( RGMII : MAC I/F, SGMII : Phy I/F)

SGMII to RGMII ( SGMII : MAC I/F, RGMII : Phy I/F)

RX_CTRL

MIRROR_EN

38

0

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9.5.1.8 Straps for 100M Media Convertor

表9-15. 100M Media Convertor Strap Table

STRAP

NAME

PIN NAME

PIN #

DEFAULT

LED_1

ANEGSEL_0

46

0

ANEGSEL_1 ANEGSEL_0

Copper : Auto-negotiation ( 100/10

Advertised), Auto MDIX

0

1

0

1

LED_2

ANEGSEL_1

45

0

Copper : Auto Negotiation ( 100 Advertised),

Auto MDIX

0

1

0

1

Copper: Mirror Disable

Copper: Mirror Enable

RX_CTRL

RX_CLK

MIRROR_EN

LINK_LOSS

38

32

0

Link Loss Pass Thru Enabled

Link Loss Pass Thru Disabled

9.5.1.9 Straps for 1000M Media Convertor

表9-16. 1000M Media Strap Table

STRAP

NAME

PIN NAME

PIN #

DEFAULT

0

Fiber Auto Negotiation

Fiber Force Mode

LED_0

LED_1

ANEG_DIS

47

46

0

1

ANEGSEL_1 ANEGSEL_0

ANEGSEL_0

0

Copper : Auto-negotiation ( 1000/100

Advertised), Auto MDIX

0

1

0

1

LED_2

ANEGSEL_1

45

Copper : Auto Negotiation ( 1000

Advertised), Auto MDIX

RX_CTRL

RX_CLK

MIRROR_EN

LINK_LOSS

38

32

0

1

0

1

Copper: Mirror Disable

Copper: Mirror Enable

Link Loss Pass Thru Enabled

Link Loss Pass Thru Disabled

备注

In 1000M media converter mode, Cu Auto-negotiation will not downgrade to 100 Mbps if LP supports

only 100Mbps and link will fail.

9.5.2 LED Configuration

The DP83869HM supports three configurable Light Emitting Diode (LED) pins: LED_0, LED_1, and LED_2.

Several functions can be multiplexed onto the LEDs for different modes of operation. Based on the strapped

OPMODE[2:0] the default funciton of each LED might change. Please see "LED Default Configuration Based on

Device Mode" for more information. LED operation mode can be selected using the LEDS_CFG1 register

(address 18h).

Because the LED output pins are also used as straps, the external components required for strapping and LED

usage must be considered to avoid contention. Specifically, when the LED outputs are used to drive LEDs

directly, the active state of each output driver is dependent on the logic level sampled by the corresponding AN

input upon power up or reset.

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If a given strap input is resistively pulled low then the corresponding output is configured as an active high driver.

Conversely, if a given strap input is resistively pulled high, then the corresponding output is configured as an

active low driver.

Refer to 图 9-16 for an example of strap connections to external components. In this example, the strapping

results in Mode 0 for LED_0 and Mode 1 for LED_1.

The adaptive nature of the LED outputs helps to simplify potential implementation issues of these dual purpose

pins.

Mode 0

Mode 1

470

VDD

GND

图9-16. Example Strap Connections

The following conditions must be accounted when using LEDs:

• In RGMII-to-SGMII bridge mode with force speeds, Link LED function cannot be used.

• In both Bridge modes, LEDs can be configured to indicate TX only or RX only activity. LED will indicate

activity with respect to RGMII when the PHY is in Bridge mode.

• In 1000-Mbps media convertor mode, the link LED corresponds to 1000M link on Copper interface. If link

speed is changed then Link LED cannot be used.

• In 100-Mbps media convertor mode, the link LED corresponds to 100M link on Copper interface. If link speed

is changed then Link LED cannot be used.

9.5.3 Reset Operation

The DP83869HM needs external control over RESET_N pin during power up. If RESET_N pin is connected to

host controller, then the PHY should be held in reset for a minimum of 200 ms after the last supply powers up as

shown in . If host controller cannot be 图8-1 connected to RESET_N then a 100-Ωresistor and 47-µF capacitor

are required to be connected in series between RESET_N pin and ground as shown in 图 9-17. During normal

operation, the device can be reset by a hardware or software reset.

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RESET_N

100 ꢀ

47 …F

DP83869

图9-17. RESET_N Circuit

9.5.3.1 Hardware Reset

A hardware reset is accomplished by applying a low pulse, with a duration of at least 1 μs, to the RESET_N pin.

This resets the device such that all registers are reinitialized to default values and the hardware configuration

values are re-latched into the device (similar to the power up or reset operation).

9.5.3.2 IEEE Software Reset

An IEEE registers software reset is accomplished by setting the reset bit (bit 15) of the BMCR register (address

0h). This bit resets the IEEE-defined standard registers.

9.5.3.3 Global Software Reset

A global software reset is accomplished by setting bit 15 of register CTRL (address 1Fh) to 1. This bit resets all

the internal circuits in the PHY including IEEE-defined registers and all the extended registers. The global

software resets the device such that all registers are reset to default values and the hardware configuration

values are maintained.

9.5.3.4 Global Software Restart

A global software restart is accomplished by setting bit 14 of register CTRL (1Fh) to 1. This action resets all the

PHY circuits except the registers in the Register File.

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9.6 Register Maps

For Fiber Operations (RGMII-to-1000Base-X and RGMII-to-100Base-FX), Fiber register location 0Cxxh get

mapped to 0xxxxh address location to comply with IEEE Specifications.

9.6.1 DP83869 Registers

DP83869 Registers lists the memory-mapped registers for the DP83869 registers. All register offset addresses

not listed in DP83869 Registers should be considered as reserved locations and the register contents should not

be modified.

表9-17. DP83869 Registers

Offset

0h

Acronym

BMCR

Register Name

Section

Go

Basic Mode Control Register

1h

BMSR

Basic Mode Status Register

Go

2h

PHYIDR1

PHYIDR2

ANAR

PHY Identifier Register #1

Go

3h

PHY Identifier Register #2

Go

4h

Auto-Negotiation Advertisement Register

Auto-Negotiation Link Partner Ability Register

Auto-Negotiate Expansion Register

Auto-Negotiation Next Page Transmit Register

Go

5h

ALNPAR

ANER

Go

6h

Go

7h

ANNPTR

ANLNPTR

Go

8h

Auto-Negotiation Link Partner Next Page Receive

Register

Go

9h

GEN_CFG1

Configuration Register 1

Status Register 1

Go

Ah

GEN_STATUS1

REGCR

Dh

Register Control Register

Address or Data Register

1000BASE-T Status Register

PHY Control Register

Eh

ADDAR

Fh

1KSCR

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Eh

1Fh

25h

2Ch

2Dh

2Eh

31h

32h

33h

37h

39h

3Ah

PHY_CONTROL

PHY_STATUS

PHY Status Register

INTERRUPT_MASK

INTERRUPT_STATUS

GEN_CFG2

MII Interrupt Control Register

Interrupt Status Register

Configuration Register 2

RX_ERR_CNT

BIST_CONTROL

GEN_STATUS2

LEDS_CFG1

BIST Control Register

Status Register 2

LED Configuration Register 1

LED Configuration Register 2

LED Configuration Register 3

Configuration Register 3

Control Register

LEDS_CFG2

LEDS_CFG3

GEN_CFG4

GEN_CTRL

ANALOG_TEST_CTRL

GEN_CFG_ENH_AMIX

GEN_CFG_FLD

GEN_CFG_FLD_THR

GEN_CFG3

Testmode Channel Control Register

Configuration Register 4

RGMII Control Register

RGMII_CTRL

RGMII_CTRL2

SGMII_AUTO_NEG_STATUS

PRBS_TX_CHK_CTRL

PRBS_TX_CHK_BYTE_CNT

SGMII Autonegotiation Status Register

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表9-17. DP83869 Registers (continued)

Offset

43h

Acronym

Register Name

Section

Go

G_100BT_REG0

4Fh

SERDES_SYNC_STS

G_1000BT_PMA_STATUS

STRAP_STS

55h

Skew FIFO Status Register

Strap Status Register

6Eh

86h

ANA_RGMII_DLL_CTRL

RXF_CFG

RGMII Delay Control Register

134h

135h

170h

180h

181h

182h

183h

184h

185h

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

1A4h

1A5h

1A6h

1DFh

1E0h

1ECh

C00h

C01h

C02h

C03h

C04h

C05h

C06h

C07h

C08h

C10h

C18h

C19h

RXF_STATUS

IO_MUX_CFG

TDR_GEN_CFG1

TDR_GEN_CFG2

TDR_SEG_DURATION1

TDR_SEG_DURATION2

TDR_GEN_CFG3

TDR_GEN_CFG4

TDR_PEAKS_LOC_A_0_1

TDR_PEAKS_LOC_A_2_3

TDR_PEAKS_LOC_A_4_B_0

TDR_PEAKS_LOC_B_1_2

TDR_PEAKS_LOC_B_3_4

TDR_PEAKS_LOC_C_0_1

TDR_PEAKS_LOC_C_2_3

TDR_PEAKS_LOC_C_4_D_0

TDR_PEAKS_LOC_D_1_2

TDR_PEAKS_LOC_D_3_4

TDR_GEN_STATUS

TDR_PEAKS_SIGN_A_B

TDR_PEAKS_SIGN_C_D

OP_MODE_DECODE

GPIO_MUX_CTRL

MC_LINK_LOSS

FX_CTRL

Fiber Control Register

FX_STS

Fiber Status Register

FX_PHYID1

Fiber PHYID Register 1

FX_PHYID2

Fiber PHYID Register 2

FX_ANADV

Fiber Autonegotiation Advertisement Register

Fiber Link Partner Ability Register

Fiber Autonegotiation Expansion Register

Fiber LOC Next Page Register

Fiber Link Partner Next Page Register

Fiber Signal Detect

FX_LPABL

FX_ANEXP

FX_LOCNP

FX_LPNP

CFG_FX_CTRL0

FX_INT_EN

Fiber Interrupt Enable Register

Fiber Interrupt Status Register

FX_INT_STS

Complex bit access types are encoded to fit into small table cells. DP83869 Access Type Codes shows the

codes that are used for access types in this section.

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表9-18. DP83869 Access Type Codes

Access Type

Code

Description

Read Type

R

Read

RC

R

C

Read

to Clear

RH

R

H

Read

Set or cleared by hardware

Write Type

W

Write

W1C

W

Write

1C

1 to clear

WoP

W

Write

WtoP

Reset or Default Value

-n

Value after reset or the default

value

9.6.1.1 BMCR Register (Offset = 0h) [Reset = 1140h]

BMCR is shown in BMCR Register Field Descriptions.

Return to the Summary Table.

IEEE defined register to control PHY functionality.

表9-19. BMCR Register Field Descriptions

Bit

Field

Type

Reset

Description

15

RESET

R/W

0h

This bit controls the MII reset function. This bit is self cleared after

reset is completed.

0h = Normal Operation

1h = Reset.

14

13

MII_LOOPBACK

R/W

0h

This bit controls the MII Loopback. When enabled, this will send data

back to the MAC

0h = Disable

1h = Enable

SPEED_SEL_LSB

Speed selection bits LSB[13] and MSB[6] are used to control the

data rate of the ethernet link when auto-negotiation is disabled.

0h = 10Mbps

1h = 100Mbps

2h = 1000Mbps

3h = Reserved

12

11

10

9

AUTONEG_EN

PWD_DWN

R/W

1h

0h

Controls autonegotiation feature

0h = Autonegotiation off

1h = Autonegotiation on

R

Controls IEEE power down feature

0h = Normal Mode

1h = IEEE power down mode

ISOLATE

R/W

Isolate MAC interface pins.

0h = Normal mode

1h = MAC Isolate mode enabled

RSTRT_AUTONEG

RH/WtoP

Restart auto-negotiation

0h = Normal mode

1h = Restart autonegotiation

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表9-19. BMCR Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

8

DUPLEX_EN

R/W

1h

Controls Half and Full duplex mode of the ethernet link

0h = Half Duplex mode

1h = Full Duplex mode

7

COL_TST

R/W

0h

Controls Collision Signal Test

0h = Disable Collision Signal Test

1h = Enable Collision Signal Test

6

SPEED_SEL_MSB

RESERVED

R

1h

0h

Controls data rate of ethernet link when autonegotiation is disabled.

See bit 13 description for morw information.

5-0

Reserved

9.6.1.2 BMSR Register (Offset = 1h) [Reset = 7949h]

BMSR is shown in BMSR Register Field Descriptions.

Return to the Summary Table.

IEEE defined register to show status of PHY

表9-20. BMSR Register Field Descriptions

Bit

15

14

Field

Type

Reset

Description

RESERVED

100M_FDUP

R

0h

Reserved

R

1h

100Base-TX full duplex

0h = PHY not able to perform full duplex 100Base-X

1h = PHY able to perform full duplex 100Base-X

13

12

11

100M_HDUP

10M_FDUP

10M_HDUP

R

1h

100Base-TX halfduplex

0h = PHY not able to perform half duplex 100Base-X

1h = PHY able to perform half duplex 100Base-X

10Base-Te full duplex

0h = PHY not able to operate at 10Mbps in full duplex

1h = PHY able to operate at 10Mbps in full duplex

10Base-Te half duplex

0h = PHY not able to operate at 10Mbps in half duplex

1h = PHY able to operate at 10Mbps in half duplex

10

9

RESERVED

EXT_STS

R

0h

1h

Reserved

8

Extended status for 1000Base T abilities in register 15

1h = Extended status information in register 0x0F

7

6

RESERVED

R

0h

1h

Reserved

MF_PREAMBLE_SUP

Ability to accept management frames with preamble suppressed.

0h = PHY will not accept management frames with preamble

suppressed

1h = PHY will accept management frames with preamble suppressed

5

4

3

AUTONEG_COMP

REMOTE_FAULT

AUTONEG_ABL

R

0h

1h

Status of Autonegotiation

0h = Auto Negotiation process not completed

1h = Auto Negotiation process completed

RC

R

Remote fault detection

0h = No remote fault condition detected

1h = Remote fault condition detected

Autonegotiation ability

0h = PHY is not able to perform Auto-Negotiation

1h = PHY is able to perform Auto-Negotiation

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表9-20. BMSR Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2

LINK_STS1

R

0h

Link Status

This is latch low and needs to be read twice for valid link up

0h = Link down

1h = Link up

1

0

JABBER_DTCT

EXT_CAPBLTY

RC

R

0h

1h

Jabber detected

0h = No jabber detected

1h = Jabber detected

Extended register capabilities

0h = Basic register set capabilities

1h = Extended register set capabilities

9.6.1.3 PHYIDR1 Register (Offset = 2h) [Reset = 2000h]

PHYIDR1 is shown in PHYIDR1 Register Field Descriptions.

Return to the Summary Table.

The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83869. The Identifier consists

of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model

revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if esired. The PHY

Identifier is intended to support network management. Texas Instruments' IEEE assigned OUI is 080028h.

表9-21. PHYIDR1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

OUI_MSB

R

2000h

OUI Most Significant Bits: Bits 3 to 18 of the OUI (080028h,) are

stored in bits 15 to 0 of this register respectively. Bit numbering for

OUI goes from 1 (MSB) to 24(LSB). The most significant two bits of

the OUI are ignored (the IEEE standard refers to these as bits 1 and

2).

9.6.1.4 PHYIDR2 Register (Offset = 3h) [Reset = A0F3h]

PHYIDR2 is shown in PHYIDR2 Register Field Descriptions.

Return to the Summary Table.

表9-22. PHYIDR2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-10

OUI_LSB

R

28h

OUI Least Significant Bits: Bits 19 to 24 of the OUI (080028h) are

mapped from bits 15 to 10 of this register respectively.

9-4

3-0

MODEL_NUM

R

Fh

3h

Model number: The six bits of vendor model number are mapped

from bits 9 to 4 (most significant bit to bit 9).

REVISION_NUM

Revision number: Four bits of the vendor model revision number are

mapped from bits 3 to 0 (most significant bit to bit 3). This field will be

incremented for all major device changes.

9.6.1.5 ANAR Register (Offset = 4h) [Reset = 0001h]

ANAR is shown in ANAR Register Field Descriptions.

Return to the Summary Table.

This register contains the advertised abilities of this device as they will be transmitted to its link partner during

Auto-Negotiation. Any writes to this register prior to completion of Auto-Negotiation (as indicated in the Basic

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Mode Status Register (address 01h) Auto-Negotiation Complete bit, BMSR[5]) should be followed by a

renegotiation. This will ensure that the new values are properly used in the Auto-Negotiation.

表9-23. ANAR Register Field Descriptions

Bit

Field

Type

Reset

Description

15

NEXT_PAGE_1_ADV

R/W

0h

Next Page Advertisement

0h = Do not advertise desire to send additional SW next pages

1h = Advertise desire to send additional SW next pages

14

13

RESERVED

R

0h

Reserved

REMOTE_FAULT_ADV

R/W

Remote Fault Advertisement

0h = Do not advertise remote fault event detection

1h = Advertise remote fault event detection

12

11

ANAR_BIT12

R/W

0h

ASYMMETRIC_PAUSE_A R/W

DV

1b = Advertise asymmetric pause ability 0b = Do not advertise

asymmetric pause ability

10

PAUSE_ADV

R/W

0h

0h = Do not advertise pause ability

1h = Advertise pause ability

9

8

G_100BT_4_ADV

R/W

0h

100BT-4 is not supported

G_100BTX_FD_ADV

100Base-TX Full Duplex. Default depends on strap, non strap default

'1'.

0h = Do not advertise 100Base-TX Full Duplex ability

1h = Advertise 100Base-TX Full Duplex ability

7

G_100BTX_HD_ADV

R/W

0h

100Base-TX Half Duplex. Default depends on strap, non strap

default '1'.

0h = Do not advertise 100Base-TX Half Duplex ability

1h = Advertise 100Base-TX Half Duplex ability

6

5

G_10BT_FD_ADV

G_10BT_HD_ADV

R/W

0h

1h

Default depends on strap, non strap default '1'

0h = Do not advertise 10Base-T Full Duplex ability

1h = Advertise 10Base-T Full Duplex ability

Default depends on strap, non strap default '1'

0h = Do not advertise 10Base-T Half Duplex ability

1h = Advertise 10Base-T Half Duplex ability

4-0

SELECTOR_FIELD_ADV R/W

Technology selector field (802.3 == 00001)

9.6.1.6 ALNPAR Register (Offset = 5h) [Reset = 0000h]

ALNPAR is shown in ALNPAR Register Field Descriptions.

Return to the Summary Table.

This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The

content changes after the successful Auto-Negotiation if Next pages are supported.

表9-24. ALNPAR Register Field Descriptions

Bit

Field

Type

Reset

Description

15

NEXT_PAGE_1_LP

R

0h

0h = Link Partner does not advertise desire to send additional SW

next pages

1h = Link Partner advertises desire to send additional SW next

pages

14

ACKNOWLEDGE_1_LP

R

0h

0h = Link Partner does not acknowledge reception of link partner's

link code word

1h = Link Partner acknowledges reception of link partner's link code

word

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表9-24. ALNPAR Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

13

REMOTE_FAULT_LP

R

0h

0h = Link Partner does not advertise remote fault event detection

1h = Link Partner advertises remote fault event detection

12

11

RESERVED

R

0h

Reserved

ASYMMETRIC_PAUSE_L

P

0h = Link Partner does not advertise asymmetric pause ability

1h = Link Partner advertises asymmetric pause ability

10

9

PAUSE_LP

R

0h

0h = Link Partner does not advertise pause ability

1h = Link Partner advertises pause ability

G_100BT4_LP

0h = Link Partner does not advertise 100Base-T4 ability

1h = Link Partner advertises 100Base-T4 ability

8

G_100BTX_FD_LP

G_100BTX_HD_LP

G_10BT_FD_LP

G_10BT_HD_LP

SELECTOR_FIELD_LP

0h = Link Partner does not advertise 100Base-TX Full Duplex ability

1h = Link Partner advertises 100Base-TX Full Duplex ability

7

0h = Link Partner does not advertise 100Base-TX Half Duplex ability

1h = Link Partner advertises 100Base-TX Half Duplex ability

6

0h = Link Partner does not advertise 10Base-T Full Duplex ability

1h = Link Partner advertises 10Base-T Full Duplex ability

5

0h = Link Partner does not advertise 10Base-T Half Duplex ability

1h = Link Partner advertises 10Base-T Half Duplex ability

4-0

Technology selector field

9.6.1.7 ANER Register (Offset = 6h) [Reset = 0064h]

ANER is shown in ANER Register Field Descriptions.

Return to the Summary Table.

This register contains additional Local Device and Link Partner status information.

表9-25. ANER Register Field Descriptions

Bit

15-7

6

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

RX_NEXT_PAGE_LOC_A R

BLE

1h

0h = Received Next Page storage location is not specified by bit 6.5

1h = Received Next Page storage location is specified by bit 6.5

5

4

RX_NEXT_PAGE_STOR_ R

LOC

1h

0h

0h = Link Partner Next Pages are stored in register 5

1h = Link Partner Next Pages are stored in register 8

PRLL_TDCT_FAULE

RC

THIS STATUS IS LH (Latched-High)

0h = A fault has not been detected during the parallel detection

process

1h = A fault has been detected during the parallel detection process

3

2

1

LP_NP_ABLE

R

0h

1h

0h

0h = Link partner is not able to exchange next pages

1h = Link partner is able to exchange next pages

LOCAL_NP_ABLE

PAGE_RECEIVED_1

R

0h = Local device is not able to exchange next pages

1h = Local device is able to exchange next pages

RC

THIS STATUS IS LH (Latched-High)

0h = A new page has not been received

1h = A new page has been received

0

LP_AUTONEG_ABLE

R

0h

0h = Link partner is not Auto-Negotiation able

1h = Link partner is Auto-Negotiation able

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9.6.1.8 ANNPTR Register (Offset = 7h) [Reset = 2001h]

ANNPTR is shown in ANNPTR Register Field Descriptions.

Return to the Summary Table.

This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.

表9-26. ANNPTR Register Field Descriptions

Bit

Field

Type

Reset

Description

15

NEXT_PAGE_2_ADV

R/W

0h

0h = Do not advertise desire to send additional next pages

1h = Advertise desire to send additional next pages

14

13

RESERVED

R

0h

1h

Reserved

MESSAGE_PAGE

R/W

0h = Current page is an unformatted page

1h = Current page is a message page

12

ACKNOWLEDGE2

R/W

0h

0h = Do not set the ACK2 bit

1h = Set the ACK2 bit

11

TOGGLE

R

0h

1h

Toggles every page. Initial value is !4.11

Contents of the message/unformatted page

10-0

MESSAGE_UNFORMATT R/W

ED

9.6.1.9 ANLNPTR Register (Offset = 8h) [Reset = 2001h]

ANLNPTR is shown in ANLNPTR Register Field Descriptions.

Return to the Summary Table.

This register contains the next page information sent by the Link Partner during Auto-Negotiation.

表9-27. ANLNPTR Register Field Descriptions

Bit

Field

Type

Reset

Description

15

NEXT_PAGE_2_LP

R

0h

0h = Link partner does not advertise desire to send additional next

pages

1h = Link partner advertises desire to send additional next pages

14

13

12

ACKNOWLEDGE_2_LP

MESSAGE_PAGE_LP

ACKNOWLEDGE2_LP

TOGGLE_LP

R

0h

1h

0h

0h = Link partner does not acknowledge reception of link code work

1h = Link partner acknowledges reception of link code word

0h = Received page is an unformatted page

1h = Received page is a message page

0h = Link partner does not set the ACK2 bit

1h = Link partner sets the ACK2 bit

11

0h

1h

Toggles every page. Initial value is !5.11

Contents of the message/unformatted page

10-0

MESSAGE_UNFORMATT R

ED_LP

9.6.1.10 GEN_CFG1 Register (Offset = 9h) [Reset = 0300h]

GEN_CFG1 is shown in GEN_CFG1 Register Field Descriptions.

Return to the Summary Table.

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表9-28. GEN_CFG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-13

TEST_MODE

R/W

0h

0h = Normal Mode

1h = Test Mode 1 - Transmit Waveform Test

2h = Test Mode 2 - Transmit Jitter Test (Master Mode)

3h = Test Mode 3 - Transmit Jitter Test (Slave Mode)

4h = Test Mode 4 - Transmit Distortion Test

5h = Test Mode 5 - Scrambled MLT3 Idles

6h = Test Mode 6 - Repetitive 0001 sequence

7h = Test Mode 7 - Repetitive {Pulse, 63 zeros}

12

11

MASTER_SLAVE_MAN_ R/W

CFG_EN

0h

1b = Enable manual Master/Slave configuration 0b = Do not enable

manual Master/Slave configuration

MASTER_SLAVE_MAN_ R/W

CFG_VAL

1b = Manual configure as Master 0b = Manual configure as Slave

10

9

PORT_TYPE

R/W

0h

1h

1b = Multi-port device 0b = Single-port device

G_1000BT_FD_ADV

Default depends on strap

0h = Do not advertise 1000Base-T Full Duplex ability

1h = Advertise 1000Base-T Full Duplex ability

8

7

G_1000BT_HD_ADV

TDR_AUTO_RUN

RESERVED

R/W

R

1h

0h

Default depends on strap

0h = Do not advertise 1000Base-T Half Duplex ability

1h = Advertise 1000Base-T Half Duplex ability

TDR Auto Run at link down:

0h = Disable automatic execution of TDR

1h = Enable execution of TDR procedure after link down event

6-0

Reserved

9.6.1.11 GEN_STATUS1 Register (Offset = Ah) [Reset = 0000h]

GEN_STATUS1 is shown in GEN_STATUS1 Register Field Descriptions.

Return to the Summary Table.

表9-29. GEN_STATUS1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15

MS_CONFIG_FAULT

RC

0h

1 = Master/Slave configuration fault detected 0 = No Master/Slave

configuration fault detected THIS STATUS IS LH (Latched-High)

14

MS_CONFIG_RES

R

0h

1 = Local PHY configuration resolved to Master 0 = Local PHY

configuration resolved to Slave

13

12

11

LOC_RCVR_STATUS_1

REM_RCVR_STATUS

LP_1000BT_FD_ABILITY

R

0h

1 = Local receiver is OK 0 = Local receiver is not OK

1 = Remote receiver is OK 0 = Remote receiver is not OK

1 = Link partner supports 1000Base-T Full Duplex ability 0 = Link

partner does not support 1000Base-T Full Duplex ability

10

LP_1000BT_HD_ABILITY

R

0h

1 = Link partner supports 1000Base-T Half Duplex ability 0 = Link

partner does not support 1000Base-T Half Duplex ability

9-8

7-0

RESERVED

R

0h

Reserved

IDLE_ERR_COUNT

1000Base-T Idle Error Counter

9.6.1.12 REGCR Register (Offset = Dh) [Reset = 0000h]

REGCR is shown in REGCR Register Field Descriptions.

Return to the Summary Table.

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This register is the MDIO Manageable MMD access control. In general, register REGCR (4:0) is the device

address DEVAD that directs any accesses of the ADDAR (0x000E) register to the appropriate MMD. REGCR

also contains selection bits for auto increment of the data register. This register contains the device address to

be written to access the extended registers. Write 0x1F into bits 4:0 of this register. REGCR also contains

selection bits (15:14) for the address auto-increment mode of ADDAR.

表9-30. REGCR Register Field Descriptions

Bit

Field

Type

Reset

Description

15-14

G_FUNCTION

R/W

0h

00 = Address 01 = Data, no post increment 10 = Data, post

increment on read and write 11 = Data, post increment on write only

13-5

4-0

RESERVED

DEVAD

R

0h

Reserved

R/W

Device Address

9.6.1.13 ADDAR Register (Offset = Eh) [Reset = 0000h]

ADDAR is shown in ADDAR Register Field Descriptions.

Return to the Summary Table.

This register is the address/data MMD register. ADDAR is used in conjunction with REGCR register (0x000D) to

provide the access by indirect read/write mechanism to the extended register set.

表9-31. ADDAR Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

ADDR_DATA

R/W

0h

If register 13.15:14 = 00, holds the MMD DEVAD's address register,

otherwise holds the MMD DEVAD's data register

9.6.1.14 1KSCR Register (Offset = Fh) [Reset = F000h]

1KSCR is shown in 1KSCR Register Field Descriptions.

Return to the Summary Table.

表9-32. 1KSCR Register Field Descriptions

Bit

Field

Type

Reset

Description

15

G_1000BX_FD

R

1h

1 = PHY supports 1000Base-X Full Duplex capability 0 = PHY does

not support 1000Base-X Full Duplex capability

14

13

G_1000BX_HD

G_1000BT_FD

G_1000BT_HD

RESERVED

R

1h

0h

1 = PHY supports 1000Base-X Half Duplex capability 0 = PHY does

not support 1000Base-X Half Duplex capability

1 = PHY supports 1000Base-T Full Duplex capability 0 = PHY does

not support 1000Base-T Full Duplex capability

12

1 = PHY supports 1000Base-T Half Duplex capability 0 = PHY does

not support 1000Base-T Half Duplex capability

11-0

Reserved

9.6.1.15 PHY_CONTROL Register (Offset = 10h) [Reset = 5048h]

PHY_CONTROL is shown in PHY_CONTROL Register Field Descriptions.

Return to the Summary Table.

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表9-33. PHY_CONTROL Register Field Descriptions

Bit

Field

Type

Reset

Description

15-14

TX_FIFO_DEPTH

R/W

1h

FIFO is enabled only in the following modes: 1000BaseT + GMII,

10BaseT/100BaseTX/1000BaseT + SGMII

0h = 3 bytes/nibbles (1000Mbps/Other Speeds)

1h = 4 bytes/nibbles (1000Mbps/Other Speeds)

2h = 6 bytes/nibbles (1000Mbps/Other Speeds)

3h = 8 bytes/nibbles (1000Mbps/Other Speeds)

13-12

RX_FIFO_DEPTH

R/W

1h

FIFO is enabled only when SGMII is used

0h = 3 bytes/nibbles (1000Mbps/Other Speeds)

1h = 4 bytes/nibbles (1000Mbps/Other Speeds)

2h = 6 bytes/nibbles (1000Mbps/Other Speeds)

3h = 8 bytes/nibbles (1000Mbps/Other Speeds)

11

10

RESERVED

R/W

0h

Reserved

FORCE_LINK_GOOD

0h = Do Normal operation

1h = Force Link OK if speed is 1G

9-8

POWER_SAVE_MODE

R/W

0h

0h = Normal mode

1h = Reserved

2h = Active Sleep mode

3h = Passive Sleep mode

7

RESERVED

R/W

0h

2h

Reserved

6-5

MDI_CROSSOVER_MOD R/W

E

Default depends on strap

0h = Manual MDI configuration

1h = Manual MDI-X configuration

Ah = Enable automatic crossover

Bh = Enable automatic crossover

4

DISABLE_CLK_125

R/W

0h

0h = Enable CLK125

1h = Disable CLK125

3

2

1

RESERVED

R/W

1h

0h

Reserved

RESERVED

LINE_DRIVER_INV_EN

This bit is not applicable in Mirror mode

0h = Do not Invert LD transmission

1h = Invert LD transmission

0

DISABLE_JABBER

R/W

0h

0h = Enable Jabber function

1h = Disable Jabber function

9.6.1.16 PHY_STATUS Register (Offset = 11h) [Reset = 0000h]

PHY_STATUS is shown in PHY_STATUS Register Field Descriptions.

Return to the Summary Table.

表9-34. PHY_STATUS Register Field Descriptions

Bit

15-14

13

Field

Type

Reset

Description

SPEED_SEL

R

0h

00 = 10Mbps 01 = 100Mbps 10 = 1000Mbps 11 = Reserved

1 = Full duplex 0 = Half duplex

DUPLEX_MODE_ENV

PAGE_RECEIVED_2

R

0h

12

RC

0h

1 = Page received 0 = Page not received THIS BIT IS LH (Latched-

High), meaning that if this bit detects "Page received," it will hold the

value '1' until the register is read. The second read will be '0' if there

have been no further "Page received."

11

SPEED_DUPLEX_RESOL R

VED

0h

1 = Auto-Negotiation completed or disabled 0 = Auto-Negotiation

enabled and not completed

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表9-34. PHY_STATUS Register Field Descriptions (continued)

Bit

10

9

Field

Type

Reset

Description

LINK_STATUS_2

R

0h

1 = Link is up 0 = Link is down

1 = MDI-X 0 = MDI

MDI_X_MODE_CD_1

MDI_X_MODE_AB_1

SPEED_OPT_STATUS

R

0h

8

R

0h

1 = MDI-X 0 = MDI

7

R

0h

1 = Auto-Negotiation is currently being performed with Speed

Optimization masking 1000BaseT abilities (Valid only during Auto-

Negotiation) 0 = Auto-Negotiation is currently being performed

without Speed Optimization

6

SLEEP_MODE

WIRE_CROSS

R

0h

1 = Sleep 0 = Active

5-2

Indicates channels [D,C,B,A] polarity in 1000BT link 1 = Channel

polarity is reversed 0 = Channel polarity is normal

1

0

DATA_POLARITY

JABBER_DTCT_2

R

0h

1 = 10BT is in normal polarity 0 = 10BT is in reversed polarity

1 = Jabber 0 = No Jabber

9.6.1.17 INTERRUPT_MASK Register (Offset = 12h) [Reset = 0000h]

INTERRUPT_MASK is shown in INTERRUPT_MASK Register Field Descriptions.

Return to the Summary Table.

This register implements the Interrupt PHY Specific Control register. The individual interrupt events must be

enabled by setting bits in the MII Interrupt Control Register (MICR). If the corresponding enable bit in the register

is set, an interrupt is generated if the event occurs.

表9-35. INTERRUPT_MASK Register Field Descriptions

Bit

15

14

13

Field

Type

Reset

Description

AUTONEG_ERR_INT_EN R/W

SPEED_CHNG_INT_EN R/W

0h

1 = Enable interrupt 0 = Disable interrupt

0h

DUPLEX_MODE_CHNG_I R/W

NT_EN

0h

12

11

10

PAGE_RECEIVED_INT_E R/W

N

0h

1 = Enable interrupt 0 = Disable interrupt

AUTONEG_COMP_INT_E R/W

N

LINK_STATUS_CHNG_IN R/W

T_EN

9

8

EEE_ERR_INT_EN

R/W

0h

1 = Enable interrupt 0 = Disable interrupt

FALSE_CARRIER_INT_E R/W

N

7

6

5

4

ADC_FIFO_OVF_UNF_IN R/W

T_EN

0h

1 = Enable interrupt 0 = Disable interrupt

MDI_CROSSOVER_CHN R/W

G_INT_EN

SPEED_OPT_EVENT_IN R/W

T_EN

SLEEP_MODE_CHNG_IN R/W

T_EN

3

2

1

WOL_INT_EN

R/W

0h

1 = Enable interrupt 0 = Disable interrupt

XGMII_ERR_INT_EN

POLARITY_CHNG_INT_E R/W

N

0

JABBER_INT_EN

R/W

0h

1 = Enable interrupt 0 = Disable interrupt

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9.6.1.18 INTERRUPT_STATUS Register (Offset = 13h) [Reset = 0000h]

INTERRUPT_STATUS is shown in INTERRUPT_STATUS Register Field Descriptions.

Return to the Summary Table.

This register contains event status for the interrupt function. If an event has occurred since the last read of this

register, the corresponding status bit will be set. The status indications in this register will be set even if the

interrupt is not enabled.

表9-36. INTERRUPT_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

15

AUTONEG_ERR

RC

0h

1 = Auto-Negotiation error has occurred 0 = Auto-Negotiation error

has not occurred THIS BIT IS LH (Latched-High)

14

13

12

11

10

SPEED_CHNG

RC

0h

1 = Link speed has changed 0 = Link speed has not changed THIS

BIT IS LH (Latched-High)

DUPLEX_MODE_CHNG RC

1 = Duplex mode has changed 0 = Duplex mode has not changed

THIS BIT IS LH (Latched-High)

PAGE_RECEIVED

AUTONEG_COMP

LINK_STATUS_CHNG

RC

1 = Page has been received 0 = Page has not been received THIS

BIT IS LH (Latched-High)

1 = Auto-Negotiation has completed 0 = Auto-Negotiation has not

completed THIS BIT IS LH (Latched-High)

1 = Link status has changed 0 = Link status has not changed THIS

BIT IS LH (Latched-High)

9

8

EEE_ERR_STATUS

FALSE_CARRIER

R

0h

1 = EEE error has been detected

RC

1 = Enable interrupt 0 = Disable interrupt THIS BIT IS LH (Latched-

High)

7

6

5

4

ADC_FIFO_OVF_UNF

RC

0h

1 = Overflow / underflow has been detected in one of ADC's FIFOs

THIS BIT IS LH (Latched-High)

MDI_CROSSOVER_CHN RC

G

1 = MDI crossover has changed 0 = MDI crossover has not changed

THIS BIT IS LH (Latched-High)

SPEED_OPT_EVENT

RC

1 = MDI crossover has changed 0 = MDI crossover has not changed

THIS BIT IS LH (Latched-High)

SLEEP_MODE_CHNG

RC

1 = Sleep mode has changed 0 = Sleep mode has not changed THIS

BIT IS LH (Latched-High)

3

2

WOL_STATUS

R

0h

1 = WoL (or pattern) packet has been received

XGMII_ERR_STATUS

1 = Overflow / underflow has been detected in one of GMII / RGMII /

SGMII buffers NOTE: this indication have issue, recommend to not

put on DS, unless proven otherwise on the lab, CDDS #475

1

0

POLARITY_CHNG

JABBER

R

0h

1 = Data polarity has changed 0 = Data polarity has not changed

THIS BIT IS LH (Latchde-High)

RC

1 = Jabber detected 0 = Jabber not detected THIS BIT IS LH

(Latched-High)

9.6.1.19 GEN_CFG2 Register (Offset = 14h) [Reset = 29C7h]

GEN_CFG2 is shown in GEN_CFG2 Register Field Descriptions.

Return to the Summary Table.

表9-37. GEN_CFG2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15

PD_DETECT_EN

RH/WtoP

0h

0h = Disable PD detection

1h = Enable PD (Powered Device) detection

14

SGMII_TX_ERR_DIS

R/W

0h

0h = Enable SGMII TX Error indication

1h = Disable SGMII TX Error indication

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表9-37. GEN_CFG2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

13

INTERRUPT_POLARITY R/W

1h

0h = Interrupt pin is active high

1h = Interrupt pin is active low

12

SGMII_SOFT_RESET

RH/WtoP

0h

2h

Setting this bit will generate a soft reset pulse of SGMII. This register

is WSC (write-self-clear).

11-10

SPEED_OPT_ATTEMPT_ R/W

CNT

Selects the number of 1G link establishment attempt failures prior to

performing Speed Optimization:

0h = 1 attempt

1h = 2 attempts

2h = 4 attempts

3h = 8 attempts

9

8

SPEED_OPT_EN

R/W

0h

1h

0h = Disable Speed Optimization

1h = Enable Speed Optimization

SPEED_OPT_ENHANCE R/W

D_EN

In enhanced mode, speed is optimized if energy is not detected in

channels C and D

0h = Disable Speed Optimization enhanced mode

1h = Enable Speed Optimization enhanced mode

7

6

SGMII_AUTONEG_EN

SPEED_OPT_10M_EN

R/W

1h

0h = Disable SGMII Auto-Negotiation

1h = Enable SGMII Auto-Negotaition

0h = Disable speed optimization to 10M

1h = Enable speed optimization to 10M (If link establishments of 1G

and 100M fail)

5-4

MII_CLK_CFG

R/W

0h

Selects frequency of GMII_TX_CLK in 1G mode:

0h = 2.5Mhz

1h = 25Mhz

2h = Disabled

3h = Disabled

3

2

COL_FD_EN

R/W

0h

1h

0h = Disable COL indication in full duplex mode

1h = Enable COL indication in full duplex mode

LEGACY_CODING_TXM R/W

ODE_EN

0h = Disable automatic selection of Legacy scrambler mode in 1G,

Master mode

1h = Enable automatic selection of Legacy scrambler mode in 1G,

Master mode

1

0

MASTER_SEMI_CROSS_ R/W

EN

1h

0h = Disable semi-cross mode in 1G Master mode

1h = Enable semi-cross mode in 1G Master mode

SLAVE_SEMI_CROSS_E R/W

N

0h = Disable semi-cross mode in 1G Slave mode

1h = Enable semi-cross mode in 1G Slave mode

9.6.1.20 RX_ERR_CNT Register (Offset = 15h) [Reset = 0000h]

RX_ERR_CNT is shown in RX_ERR_CNT Register Field Descriptions.

Return to the Summary Table.

表9-38. RX_ERR_CNT Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

RX_ERROR_COUNT

R/W1C

0h

Receive Error Counter

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9.6.1.21 BIST_CONTROL Register (Offset = 16h) [Reset = 0000h]

BIST_CONTROL is shown in BIST_CONTROL Register Field Descriptions.

Return to the Summary Table.

This register is used for Build-In Self Test (BIST) configuration. The BIST functionality provides Pseudo Random

Bit Stream (PRBS) mechanism including packet generation generator and checker. Selection of the exact

loopback point in the signal chain is also done in this register.

表9-39. BIST_CONTROL Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

PACKET_GEN_EN_3:0

R/W

0h

These bits along controls PRBS generator.Other values are not

applicable.

0h = Disable PRBS

Fh = Enable Continuous PRBS

11-10

RESERVED

R

0h

Reserved

9

8

7

R/W

REV_LOOP_RX_DATA_C R/W

TRL

Reverse Loopback Receive Data Control: This bit may only be set in

Reverse Loopback mode

0h = Suppress RX packets to MAC in reverse loop

1h = Send RX packets to MAC in reverse loop

6

MII_LOOP_TX_DATA_CT R/W

RL

0h

MII Loopback Transmit Data Control: This bit may only be set in MII

Loopback mode

0h = Suppress data to MDI in MII loop

1h = Transmit data to MDI in MII loop

5-2

LOOP_TX_DATA_MIX

R/W

Loopback Mode Select: PCS loopback must be disabled (Bits[1:0] =

00)

0h = No Loopback

1h = Digital Loopback

2h = Analog Loopback

4h = External Loopback

8h = Reverse Loopback

1-0

LOOPBACK_MODE

R/W

0h

PCS loopback select –When configured in 1000Base-T, X1b : Loop

before 1000Base-T signal processing When configured in 100Base-

TX,

0h = See bits [5:2] 01b = Loop before scrambler 10b = Loop after

scrambler, before MLT3 encoder 11b = Loop after MLT3 encoder (full

TX/RX path)

9.6.1.22 GEN_STATUS2 Register (Offset = 17h) [Reset = 0040h]

GEN_STATUS2 is shown in GEN_STATUS2 Register Field Descriptions.

Return to the Summary Table.

表9-40. GEN_STATUS2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15

PD_PASS

RC

0h

1b = PD (Powered Device) has been successfully detected 0b = PD

has not been detected

14

13

PD_PULSE_DET_ZERO RC

PD_FAIL_WD RC

0h

1b = PD detection mechanism has received no signal 0b = PD

detection mechanism has received signal

1b = PD detection mechanism watchdog has expired 0b = PD

detection mechanism watchdog has not expired

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表9-40. GEN_STATUS2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

12

PD_FAIL_NON_PD

RC

0h

1b = PD detection mechanism has detected a non-powered device

0b = PD detection mechanism has not detected a non-powered

device

11

10

9

PRBS_LOCK

R

0h

1h

0h

1b = PRBS checker is locked sync) on received byte stream 0b =

PRBS checker is not locked

PRBS_SYNC_LOSS

PKT_GEN_BUSY

1b = PRBS checker has lost sync 0b = PRBS checker has not lost

sync LH - clear on read register

1b = Packet generator is in process 0b = Packet generator is not in

process

8

SCR_MODE_MASTER_1

G

1b = 1G PCS (master) is in legacy encoding mode 0b = 1G PCS

(master) is in normal encoding mode

7

SCR_MODE_SLAVE_1G

CORE_PWR_MODE

RESERVED

1b = 1G PCS (slave) is in legacy encoding mode 0b = 1G PCS

(slave) is in normal encoding mode

6

1b = Core is in normal power mode 0b = Core is powered down or in

sleep mode

5-0

Reserved

9.6.1.23 LEDS_CFG1 Register (Offset = 18h) [Reset = X]

LEDS_CFG1 is shown in LEDS_CFG1 Register Field Descriptions.

Return to the Summary Table.

表9-41. LEDS_CFG1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-8

LED_GPIO_SEL

LED_2_SEL

R/W

6h

Source of GPIO LED, same as bits 3:0

R/W

X

See Strap Configuration section for defaults. Source of LED_2 (LED

2) , same as bits 3:0

7-4

3-0

LED_1_SEL

LED_0_SEL

See Strap Configuration section for defaults. Source of LED_1 (LED

1) , same as bits 3:0

See Strap Configuration section for defaults. Source of LED_0 (LED

0)

0h = link OK

1h = RX/TX activity

2h = TX activity

3h = RX activity

4h = collision detected

5h = 1000BT link is up

6h = 100 BTX link is up

7h = 10BT link is up

8h = 10/100BT link is up

9h = 100/1000BT link is up

Ah = full duplex

Bh = link OK + blink on TX/RX activity

Ch = NA

Dh = RX_ER or TX_ER

Eh = RX_ER

9.6.1.24 LEDS_CFG2 Register (Offset = 19h) [Reset = 4444h]

LEDS_CFG2 is shown in LEDS_CFG2 Register Field Descriptions.

Return to the Summary Table.

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表9-42. LEDS_CFG2 Register Field Descriptions

Bit

15

14

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

LED_GPIO_POLARITY

R/W

1h

GPIO LED polarity: Default depends on strap, non strap default

Active High

0h = Active low

1h = Active high

13

12

LED_GPIO_DRV_VAL

LED_GPIO_DRV_EN

R/W

0h

If bit #12 is set, this is the value of GPIO LED

Force value to LED_GPIO as per bit #13

0h = LED_GPIO is in normal operation mode

1h = Force the value of LED_GPIO

11

10

RESERVED

R

0h

1h

Reserved

LED_2_POLARITY

R/W

LED_2 polarity. Default depends on strap, non strap default Active

High

0h = Active low

1h = Active high

9

8

LED_2_DRV_VAL

LED_2_DRV_EN

R/W

0h

If bit #8 is set, this is the value of LED_2

Force value to LED_GPIO as per bit #9

0h = LED_2 is in normal operation mode

1h = Drive the value of LED_2

7

6

RESERVED

R

0h

1h

Reserved

LED_1_POLARITY

R/W

LED_1 polarity: Default depends on strap, non strap default Active

High

0h = Active low

1h = Active high

5

4

LED_1_DRV_VAL

LED_1_DRV_EN

R/W

0h

If bit #4 is set, this is the value of LED_1

Force value to LED_GPIO as per bit #5

0h = LED_1 is in normal operation mode

1h = Drive the value of LED_1

3

2

RESERVED

R

0h

1h

Reserved

LED_0_POLARITY

R/W

LED_0 polarity: Default depends on strap, non strap default Active

High

0h = Active low

1h = Active high

1

0

LED_0_DRV_VAL

LED_0_DRV_EN

R/W

0h

If bit #1 is set, this is the value of LED_0

Force value to LED_GPIO as per bit #1

0h = LED_0 is in normal operation mode

1h = Drive the value of LED_0

9.6.1.25 LEDS_CFG3 Register (Offset = 1Ah) [Reset = 0002h]

LEDS_CFG3 is shown in LEDS_CFG3 Register Field Descriptions.

Return to the Summary Table.

表9-43. LEDS_CFG3 Register Field Descriptions

Bit

15-3

2

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

LEDS_BYPASS_STRETC R/W

HING

0h

2h

0b = Noraml Operation 1b = Bypass LEDs stretching

1-0

LEDS_BLINK_RATE

R/W

00b = 20Hz (50mSec) 01b = 10Hz (100mSec) 10b = 5Hz (200mSec)

11b = 2Hz (500mSec)

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9.6.1.26 GEN_CFG4 Register (Offset = 1Eh) [Reset = 0012h]

GEN_CFG4 is shown in GEN_CFG4 Register Field Descriptions.

Return to the Summary Table.

表9-44. GEN_CFG4 Register Field Descriptions

Bit

15

Field

Type

R/W

Reset

Description

RESERVED

0h

Reserved

14

CFG_FAST_ANEG_EN

0h

Enable Fast ANEG mode

13-12

CFG_FAST_ANEG_SEL_ R/W

VAL

when Fast ANEG mode enabled, value will select short timer

duration 0x0 will be the shortest timers config and 0x2 the longest

11

CFG_ANEG_ADV_FD_E R/W

N

0h

this but enables to declare FD also in parallel detect link, the IEEE

defien on parallel detect to always declare HD, this bit allows also to

declare FD in this scenario

10

9

RESTART_STATUS_BITS R/W

_EN

0h

reset enable 1b = clear all the phy status bits (part of register 0x11)

0b = do not clear the status bit

CFG_ROBUST_AMDIX_E R/W

N

Enable Robust Auto MDI/MDIX resolution

8

7

CFG_FAST_AMDIX_EN

INT_OE

R/W

0h

Enabe Fast Auto MDI-X mode

Interrupt Output Enable: 1b = INTN/PWDNN Pad is an Interrupt

Output 0b = INTN/PWDNN Pad in an Power Down Input

6

5

4

3

FORCE_INTERRUPT

RESERVED

R/W

0h

1h

0h

1b = Assert interrupt pin 0b = Normal interrupt mode

Reserved

RESERVED

FORCE_1G_AUTONEG_ R/W

EN

1b = Invoke Auto-Negotiation with only 1G advertised when manual

speed in register 0x0000 is 1G 0b = Do not invoke Auto-Negotiation

when manual speed in register 0x0000 is 1G

2

1

0

TDR_FAIL

R

0h

1h

0h

TDR_DONE

TDR_START

R

RH/WtoP

1b = Start TDR 0b = TDR Completed

9.6.1.27 GEN_CTRL Register (Offset = 1Fh) [Reset = 0000h]

GEN_CTRL is shown in GEN_CTRL Register Field Descriptions.

Return to the Summary Table.

表9-45. GEN_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

15

SW_RESET

RH/WtoP

0h

Software Reset This will reset the PHY and return registers to their

default values. Registers controlled via strap pins will return back to

their last strapped values.

0h = Normal mode

1h = Reset PHY

14

SW_RESTART

RH/WtoP

0h

Soft Restart Restarts the PHY without affecting registers.

0h = Normal Operation

1h = Software Reset

13

12-7

6-0

RESERVED

R/W

0h

Reserved

9.6.1.28 ANALOG_TEST_CTRL Register (Offset = 25h) [Reset = 0480h]

ANALOG_TEST_CTRL is shown in ANALOG_TEST_CTRL Register Field Descriptions.

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Return to the Summary Table.

表9-46. ANALOG_TEST_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-10

RESERVED

TM7_PULSE_SEL

R

0h

Reserved

R/W

1h

Selects pulse amplitude and polarity for Test Mode 7 (See register

0x9): 00b = +2 01b = -2 10b = +1 11b = -1

9

EXTND_TM7_100BT_MS R/W

B

0h

4h

0h

MSB of configurable length for 100BT extended TM7 For 100BT Test

Mode: repetitive sequence of "1" with configurable number of "0".

Bits { 9,[3:0] } define the number of "0" to follow the "1", from 1 to 31.

0,0001 - 1,1111 : single "0" to 31 zeros. 0,0000 - clear the shiftreg.

8

EXTND_TM7_100BT_EN R/W

Enable extended TM7 for 100M. NOTE1: bit 4 must be "0" for 100BT

TestMode. NOTE2: 100BT testmode must be Clear before appling

new Value. e.g, one need to write 0x0 before configuring new value.

NOTE3: use FORCE100 for 100BT testing, via Reg0x0.

7-5

4-0

STIM_CH_SEL

ANALOG_TEST

R/W

Selects the channel(s) that outputs the test mode: If bit #7 is set, test

mode is driven to all channels. If bit #7 is cleared, test mode is driven

according to bits 6:5 - 00b = Channel A 01b = Channel B 10b =

Channel C 11b = Channel D

Bit [4] enables 10BaseT test modes. Bits [3:0] select the 10BaseT

test pattern, as follows: To operate extended TM7 for 100BT, bits 3:0

shall be configured as well - more details in bit #9 0000b = Single

NLP 0001b = Single Pulse 1 0010b = Single Pulse 0 0011b =

Repetitive 1 0100b = Repetitive 0 0101b = Preamble (repetitive "10")

0110b = Single 1 followed by TP_IDLE 0111b = Single 0 followed by

TP_IDLE 1000b = Repetitive "1001" sequence 1001b = Random

10Base-T data 1010b = TP_IDLE_00 1011b = TP_IDLE_01 1100b =

TP_IDLE_10 1101b = TP_IDLE_11 0110b = Proprietary T.M for

amplitude, RFT, DCD and template for FT on tester (1000) ---> need

to write register 0 0x2000

9.6.1.29 GEN_CFG_ENH_AMIX Register (Offset = 2Ch) [Reset = 141Fh]

GEN_CFG_ENH_AMIX is shown in GEN_CFG_ENH_AMIX Register Field Descriptions.

Return to the Summary Table.

表9-47. GEN_CFG_ENH_AMIX Register Field Descriptions

Bit

Field

Type

Reset

Description

15-14

13-9

RESERVED

R

0h

Reserved

CFG_FLD_WINDW_CNT R/W

Ah

counter to define the wondow in which we lok for fast link down

criteria, default 10usec

8-4

3-0

CFG_FAST_AMDIX_VAL R/W

1h

Fh

timer of the mdi/x switch cuonterin force 100m fast amdix mode, very

fast as it need only to allow far end to detect energy ~4ms in default

CFG_ROBUST_AMDIX_V R/W

AL

the value of the timer that switch mdi/x in robust mode, this shoul be

long timer to allow far end to still do parallel detect witht he IEEE

ANEG timers... default ~0.5s

9.6.1.30 GEN_CFG_FLD Register (Offset = 2Dh) [Reset = 0000h]

GEN_CFG_FLD is shown in GEN_CFG_FLD Register Field Descriptions.

Return to the Summary Table.

表9-48. GEN_CFG_FLD Register Field Descriptions

Bit

Field

Type

Reset

Description

15

CFG_FORCE_DROP_LIN R/W

K_EN

0h

Drop link (stop transmitting) when no signal is received

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表9-48. GEN_CFG_FLD Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

14

FLD_BYPASS_MAX_WAI R/W

T_TIMER

0h

If set, MAX_WAIT_TIMER is skipped (and therefore link is dropped

faster)

13

12-8

7-5

SLICER_OUT_STUCK

FLD_STATUS

R

0h

indicate slicer)out_stuck status

Fast link down status LH - clear on read register

Reserved

RESERVED

4-0

CFG_FAST_LINK_DOWN R/W

_MODES

5 bits for different fast link down option (can all work simultaniously):

bit [0] - energy lost bit [1] - mse bit [2] - mlt3 errors bit [3] - rx_err bit

[4] - descrambler sync loss

9.6.1.31 GEN_CFG_FLD_THR Register (Offset = 2Eh) [Reset = 0221h]

GEN_CFG_FLD_THR is shown in GEN_CFG_FLD_THR Register Field Descriptions.

Return to the Summary Table.

表9-49. GEN_CFG_FLD_THR Register Field Descriptions

Bit

Field

Type

Reset

Description

15-11

10-8

RESERVED

R

0h

Reserved

ENERGY_WINDOW_LEN R/W

_FLD

2h

window length in FLD energy lost mode for energy detection

accumulator

7

RESERVED

R

0h

2h

Reserved

6-4

ENERGY_ON_FLD_THR R/W

energy lost threshold for FLD energy lost mode. energy_detected

indication will be asserted when energy detector accumulator

exceeds this threshold.

3

RESERVED

R

0h

1h

Reserved

2-0

ENERGY_LOST_FLD_TH R/W

R

energy lost threshold for FLD energy lost mode energy_lost

indication will be asserted if energy detector accumulator falls below

this threshold.

9.6.1.32 GEN_CFG3 Register (Offset = 31h) [Reset = 10B0h]

GEN_CFG3 is shown in GEN_CFG3 Register Field Descriptions.

Return to the Summary Table.

表9-50. GEN_CFG3 Register Field Descriptions

Bit

15

14

13

12

11-9

8

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

R/W

R

0h

1h

0h

1h

Reserved

R/W

7

6-5

SGMII_AUTONEG_TIME R/W

R

Selects duration of SGMII Auto-Negotiation timer: 00: 1.6ms 01: 2µs

10: 800µs 11: 11ms

4

3

2

1

RESERVED

R/W

R

1h

0h

Reserved

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表9-50. GEN_CFG3 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

PORT_MIRRORING_MO R/W

DE

0h

Port mirroring mode: 0 - Disabled 1 - Enabled

9.6.1.33 RGMII_CTRL Register (Offset = 32h) [Reset = 00D0h]

RGMII_CTRL is shown in RGMII_CTRL Register Field Descriptions.

Return to the Summary Table.

表9-51. RGMII_CTRL Register Field Descriptions

Bit

15

14

13

12

11

10

9

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

R

0h

1h

2h

Reserved

R

R/W

R

R/W

8

7

6-5

RGMII_RX_HALF_FULL_ R/W

THR

RGMII RX sync FIFO Half-full Threshold Bits 1:0 of the 3-bit

threshold field. Bit2 can be found in Reg 0x33[1]. The default setting

2 will start a FIFO read when the difference between the write and

read pointer is 4. The TX/RX FIFOs have a depth of 8. Increasing the

threshold from 2 to 3 will increase the latency by 1 read cycle; while

decreasing the threshold from 2 to 1 will decrease latency by 1 read

cycle. If the difference between ppm of the read and write clocks is

significant, a half-full threshold can cause either FIFO underflow or

overflow.

4-3

RGMII_TX_HALF_FULL_ R/W

THR

2h

RGMII TX sync FIFO Half-full Thresholds Bits 1:0 of the 3-bit

threshold field. Bit2 can be found in Reg 0x33[0] See

RGMII_RX_HALF_FULL_THR for more details.

2

1

SUPPRESS_TX_ERR_EN R/W

RGMII_TX_CLK_DELAY R/W

0h

RGMII Transmit Clock Delay

0h = RGMII transmit clock is shifted with respect to transmit data.

1h = RGMII transmit clock is aligned with respect to transmit data.

0

RGMII_RX_CLK_DELAY R/W

0h

RGMII Receive Clock Delay

0h = RGMII receive clock is shifted with respect to receive data.

1h = RGMII transmit clock is aligned with respect to receive data.

9.6.1.34 RGMII_CTRL2 Register (Offset = 33h) [Reset = 0000h]

RGMII_CTRL2 is shown in RGMII_CTRL2 Register Field Descriptions.

Return to the Summary Table.

表9-52. RGMII_CTRL2 Register Field Descriptions

Bit

15-5

4

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

RGMII_AF_BYPASS_EN R/W

0h

RGMII Async FIFO Bypass Enable: 1 = Enable RGMII Async FIFO

Bypass. 0 = Normal operation.

3

RGMII_AF_BYPASS_DLY R/W

_EN

0h

RGMII Async FIFO Bypass Delay Enable: 1 = Delay RX_CLK when

operating in 10/100 with RGMII. 0 = Normal operation

72

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表9-52. RGMII_CTRL2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2

LOW_LATENCY_10_100_ R/W

EN

0h

Low Latency 10/100 Enable: 1 = Enable low latency in 10/100

operation. 0 = Normal operation.

1

0

RGMII_RX_HALF_FULL_ R/W

THR_MSB

0h

RGMII RX sync FIFO Half-full Threshold Bit2 of the 3-bit threshold

field. Bits 1:0 can be found in Reg 0x32[6:5], respectively.

RGMII_TX_HALF_FULL_ R/W

THR_MSB

RGMII TX sync FIFO Half-full Threshold Bit2 of the 3-bit threshold

field. Bits 1:0 can be found in Reg 0x32[4:3], respectively.

9.6.1.35 SGMII_AUTO_NEG_STATUS Register (Offset = 37h) [Reset = 0000h]

SGMII_AUTO_NEG_STATUS is shown in SGMII_AUTO_NEG_STATUS Register Field Descriptions.

Return to the Summary Table.

表9-53. SGMII_AUTO_NEG_STATUS Register Field Descriptions

Bit

15-2

1

Field

Type

Reset

Description

RESERVED

SGMII_PAGE_RX

R

0h

Reserved

R

0h

1b = indicate that a new auto-neg page was received

0

SGMII_AUTONEG_COMP R

LETE

0h

1b = Auto-Negotiation process completed 0b = Auto-Negotiation

process not completed

9.6.1.36 PRBS_TX_CHK_CTRL Register (Offset = 39h) [Reset = 0000h]

PRBS_TX_CHK_CTRL is shown in PRBS_TX_CHK_CTRL Register Field Descriptions.

Return to the Summary Table.

表9-54. PRBS_TX_CHK_CTRL Register Field Descriptions

Bit

15

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

14-7

PRBS_TX_CHK_ERR_CN R

T

0h

Holds number of errored bytes that received by the PRBS TX

checker. When TX PRBS Count Mode (see bit [1]) set to 0, count

stops on 0xFF. Notes: Writing bit 7 generates a lock signal for the

PRBS TX counters. Writing bit 8 generates a lock and clear signal for

the PRBS TX counters

6

5

RESERVED

R

0h

Reserved

PRBS_TX_CHK_SYNC_L

OSS

1b = PRBS TX checker has lost sync 0b = PRBS TX checker has not

lost sync This bit is LH

4

PRBS_TX_CHK_LOCK_S R

TS

0h

1b = PRBS TX checker is locked on received byte stream 0b =

PRBS TX checker is not locked

3

2

RESERVED

R

0h

Reserved

PRBS_TX_CHK_BYTE_C

NT_OVF

If set, bytes counter reached overflow

1

0

PRBS_TX_CHK_CNT_M R/W

ODE

0h

PRBS Checker Mode 1b = Continuous mode 0b = Single Mode.

PRBS_TX_CHK_EN

R/W

If set, PRBS TX checker is enabled (PRBS TX checker is used in

external reverse loop)

9.6.1.37 PRBS_TX_CHK_BYTE_CNT Register (Offset = 3Ah) [Reset = 0000h]

PRBS_TX_CHK_BYTE_CNT is shown in PRBS_TX_CHK_BYTE_CNT Register Field Descriptions.

Return to the Summary Table.

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表9-55. PRBS_TX_CHK_BYTE_CNT Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

PRBS_TX_CHK_BYTE_C

NT

R

0h

Holds number of total bytes that received by the PRBS TX checker.

Value in this register is locked when write is done to register

PRBS_TX_CHK_CTRL bit[7]or bit[8]. When PRBS Count Mode set

to zero, count stops on 0xFFFF (see register 0x0016)

9.6.1.38 G_100BT_REG0 Register (Offset = 43h) [Reset = 07A0h]

G_100BT_REG0 is shown in G_100BT_REG0 Register Field Descriptions.

Return to the Summary Table.

表9-56. G_100BT_REG0 Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

15-12

RESERVED

FAST_RX_DV

R

0h

11

10-7

6

R/W

0h

Fh

0h

5

1h

4

0h

3

0h

2

0h

1

0h

0

0h

Enable Fast RX_DV for low latency in 100Mbps mode.

0h = Fast rx dv disable

1h = Fast rx dv enable

9.6.1.39 SERDES_SYNC_STS Register (Offset = 4Fh) [Reset = 0000h]

SERDES_SYNC_STS is shown in SERDES_SYNC_STS Register Field Descriptions.

Return to the Summary Table.

表9-57. SERDES_SYNC_STS Register Field Descriptions

Bit

15-12

11

Field

Type

R/W

R

Reset

Description

Reserved

RESERVED

SYNC_STATUS

0h

10

0h

9

R

0h

8

R

0h

Synchronization Status

0h = No Sync

1h = Sync Established

7-4

3-0

RESERVED

R

0h

Reserved

9.6.1.40 G_1000BT_PMA_STATUS Register (Offset = 55h) [Reset = 0000h]

G_1000BT_PMA_STATUS is shown in G_1000BT_PMA_STATUS Register Field Descriptions.

Return to the Summary Table.

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表9-58. G_1000BT_PMA_STATUS Register Field Descriptions

Bit

15-8

7-4

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

PMA_MASTER_FIFO_CT

RL

R

0h

1000-Mb SFD Variation in Master Mode

3-0

PMA_SLAVE_FIFO_CTRL R

0h

1000-Mb SFD Variation in Slave Mode

9.6.1.41 STRAP_STS Register (Offset = 6Eh) [Reset = 0000h]

STRAP_STS is shown in STRAP_STS Register Field Descriptions.

Return to the Summary Table.

表9-59. STRAP_STS Register Field Descriptions

Bit

15-14

13

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

STRAP_LINK_LOSS_PAS R

S_THRU

0h

Link Loss Pass Through Enable Strap

0h = Enable

1h = Disable

12

STRAP_MIRROR_EN

STRAP_OPMODE

R

Mirror Mode Enable StraP. Refer to strap configuration section as

this strap also decides MAC interface in Bridge Mode applications.

0h = Disable

1h = Enable

11-9

0h

OPMODE Strap

0h = RGMII To Copper

1h = RGMII to 1000Base-X

2h = RGMII to 100Base-FX

3h = RGMII-SGMII Bridge

4h = 1000Base-T to 1000Base-X

5h = 100Base-T to 100Base-FX

6h = SGMII to Copper

7h = JTAG for Boundary Scan

8-4

3-2

STRAP_PHY_ADD

STRAP_ANEGSEL

R

0h

PHY Address Strap

Auto Negotiation Mode Select Strap. Refer to Strap Configuration

Section

1

0

STRAP_ANEG_EN

RESERVED

R

0h

Auto Negotiation Enable Strap

0h = Enable

1h = Disable

Reserved

9.6.1.42 ANA_RGMII_DLL_CTRL Register (Offset = 86h) [Reset = 0077h]

ANA_RGMII_DLL_CTRL is shown in ANA_RGMII_DLL_CTRL Register Field Descriptions.

Return to the Summary Table.

表9-60. ANA_RGMII_DLL_CTRL Register Field Descriptions

Bit

15-10

9

Field

Type

Reset

Description

RESERVED

DLL_EN_FORCE_VAL

R

0h

Reserved

R/W

0h

If dll_en_force_en is set, this is the value of DLL_EN

Force DLL_EN value

8

DLL_EN_FORCE_CTRL R/W

0h

7-4

DLL_TX_DELAY_CTRL_S R/W

L

7h

Steps of 250ps, affects the CLK_90 output. - same behavior as bit

[3:0]

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表9-60. ANA_RGMII_DLL_CTRL Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3-0

DLL_RX_DELAY_CTRL_ R/W

SL

7h

Steps of 250ps, affects the CLK_90 output. b[3], b[2], b[1], b[0], shift,

mode please note - the actual delay is also effected by the shift

mode in reg 0x32

3h = 1.0ns, Shift

5h = 1.5ns, Shift

7h = 2.0 ns, Shift(*) - default

9h = 2.5ns, Shift

Bh = 3.0 ns,Shift

Dh = 3.5ns, Shift

Fh = 0ns, Align(**)

9.6.1.43 RXF_CFG Register (Offset = 134h) [Reset = 1000h]

RXF_CFG is shown in RXF_CFG Register Field Descriptions.

Return to the Summary Table.

表9-61. RXF_CFG Register Field Descriptions

Bit

15-14

13

Field

Type

Reset

Description

RESERVED

R/W

0h

Reserved

RESERVED

R/W

0h

Reserved

12

RESERVED

R/W

1h

Reserved

11

WOL_OUT_CLEAN

WOL_OUT_STRETCH

RH/WoP

R/W

0h

If WOL out is in level mode in bit 8, writing to this bit will clear it.

10-9

0h

If WOL out is in pulse mode in bit 8, this is the pulse length:

0h = 8 clock cycles

1h = 16 clock cycles

2h = 32 clock cycles

3h = 64 clock cycles

8

7

WOL_OUT_MODE

R/W

0h

Mode of the wake up that goes to GPIO pin:

0h = Pulse Mode.

1h = Level Mode

ENHANCED_MAC_SUPP R/W

ORT

Enables enhanced RX features. This bit should be set when using

wakeup abilities, CRC check or RX 1588 indication

6

5

4

3

2

1

RESERVED

R/W

0h

Reserved

RESERVED

Reserved

WAKE_ON_UCAST

RESERVED

If set, issue an interrupt upon reception of unicast packets

Reserved

WAKE_ON_BCAST

WAKE_ON_PATTERN

If set, issue an interrupt upon reception of broadcast packets

If set, issue an interrupt upon reception of a packet with configured

pattern

0

WAKE_ON_MAGIC

R/W

0h

If set, issue an interrupt upon reception of magic packet

9.6.1.44 RXF_STATUS Register (Offset = 135h) [Reset = 0000h]

RXF_STATUS is shown in RXF_STATUS Register Field Descriptions.

Return to the Summary Table.

表9-62. RXF_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

15-8

RESERVED

R

0h

Reserved

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表9-62. RXF_STATUS Register Field Descriptions (continued)

Bit

7

Field

Type

RC

Reset

Description

SFD_ERR

0h

SFD Error Detected

Bad CRC Packet Received

Reserved

6

BAD_CRC

0h

5

RESERVED

0h

4

UCAST_RCVD

RESERVED

0h

Unicast Packet Received

Reserved

3

0h

2

BCAST_RCVD

PATTERN_RCVD

MAGIC_RCVD

0h

Broadcast Packet Received

Pattern Match Packet Received

Magic Packet Received

1

0h

0

0h

9.6.1.45 IO_MUX_CFG Register (Offset = 170h) [Reset = X]

IO_MUX_CFG is shown in IO_MUX_CFG Register Field Descriptions.

Return to the Summary Table.

表9-63. IO_MUX_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

15-13

12-8

RESERVED

CLK_O_SEL

R

0h

Reserved

R/W

Ch

Select clock output source

0h = Channel A receive clock

1h = Channel B receive clock

2h = Channel C receive clock

3h = Channel D receive clock

4h = Channel A receive clock divided by 5

5h = Channel B receive clock divided by 5

6h = Channel C receive clock divided by 5

7h = Channel D receive clock divided by 5

8h = Channel A transmit clock

9h = Channel B transmit clock

Ah = Channel C transmit clock

Bh = Channel D transmit clock

Ch = Reference clock (synchronous to XI input clock)

7

6

RESERVED

R

0h

X

Reserved

CLK_O_DISABLE

R/W

Clock Out Disable

0h = Clock Out Enable

1h = Clock Out Disable

5

RESERVED

R/W

0h

Reserved

4-0

MAC_IMPEDANCE_CTRL R/W

10h

Impedance Control for MAC I/Os: Output impedance approximate

range from 35-70 Ωin 32 steps. Lowest being 11111 and highest

being 00000. Range and Step size will vary with process. Default is

set to 50 Ωby trim but the default register value can vary by

process. Non default values of MAC I/O impedance can be used

based on trace impedance. Mismatch between device and trace

impedance can cause voltage overshoot and undershoot.

9.6.1.46 TDR_GEN_CFG1 Register (Offset = 180h) [Reset = 0752h]

TDR_GEN_CFG1 is shown in TDR_GEN_CFG1 Register Field Descriptions.

Return to the Summary Table.

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表9-64. TDR_GEN_CFG1 Register Field Descriptions

Bit

15-13

12

Field

Type

R/W

Reset

Description

RESERVED

0h

Reserved

TDR_CH_CD_BYPASS

0h

Bypass channel C and D in TDR tests

11

TDR_CROSS_MODE_DI R/W

S

0h

If set, disable cross mode option - never check the cross (Listen only

to the same channel you transmit)

10

TDR_NLP_CHECK

TDR_AVG_NUM

R/W

1h

6h

If set, check for NLPs during silence

9-7

Number Of TDR Cycles to Average: 000b = 1 TDR cycle 001b = 2

TDR cycles 010b = 4 TDR cycles 011b = 8 TDR cycles 100b = 16

TDR cycles 101b = 32 TDR cycles 110b = 64 TDR cycles (default)

111b = Reserved

6-4

3-0

TDR_SEG_NUM

R/W

5h

2h

Number of TDR segments to check

TDR_CYCLE_TIME

Number of micro-seconds in each TDR cycle

9.6.1.47 TDR_GEN_CFG2 Register (Offset = 181h) [Reset = C850h]

TDR_GEN_CFG2 is shown in TDR_GEN_CFG2 Register Field Descriptions.

Return to the Summary Table.

表9-65. TDR_GEN_CFG2 Register Field Descriptions

Bit

15-8

7-6

Field

Type

Reset

C8h

1h

Description

TDR_SILENCE_TH

R/W

Energy detection threshold

TDR_POST_SILENCE_TI R/W

ME

timer for tdr to look for energy after TDR transaction, if energy

detected this is fail tdr

5-4

3-0

TDR_PRE_SILENCE_TIM R/W

E

1h

0h

timer for tdr to look for energy before starting , if energy detected this

is fail tdr

RESERVED

R

Reserved

9.6.1.48 TDR_SEG_DURATION1 Register (Offset = 182h) [Reset = 5326h]

TDR_SEG_DURATION1 is shown in TDR_SEG_DURATION1 Register Field Descriptions.

Return to the Summary Table.

表9-66. TDR_SEG_DURATION1 Register Field Descriptions

Bit

15

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

14-10

TDR_SEG_DURATION_S R/W

EG3

14h

Number of 125MHz clock cycles to run for segment #3

9-5

4-0

TDR_SEG_DURATION_S R/W

EG2

19h

6h

Number of 125MHz clock cycles to run for segment #2

Number of 125MHz clock cycles to run for segment #1

TDR_SEG_DURATION_S R/W

EG1

9.6.1.49 TDR_SEG_DURATION2 Register (Offset = 183h) [Reset = A01Eh]

TDR_SEG_DURATION2 is shown in TDR_SEG_DURATION2 Register Field Descriptions.

Return to the Summary Table.

表9-67. TDR_SEG_DURATION2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-8

TDR_SEG_DURATION_S R/W

EG5

A0h

Number of 125MHz clock cycles to run for segment #5

78

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表9-67. TDR_SEG_DURATION2 Register Field Descriptions (continued)

Bit

7-6

5-0

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

TDR_SEG_DURATION_S R/W

EG4

1Eh

Number of 125MHz clock cycles to run for segment #4

9.6.1.50 TDR_GEN_CFG3 Register (Offset = 184h) [Reset = E976h]

TDR_GEN_CFG3 is shown in TDR_GEN_CFG3 Register Field Descriptions.

Return to the Summary Table.

表9-68. TDR_GEN_CFG3 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

TDR_FWD_SHADOW_SE R/W

G4

Eh

Indicates how much time to wait after max level before declaring we

found a peak in segment #4

11-8

TDR_FWD_SHADOW_SE R/W

G3

9h

Indicates how much time to wait after max level before declaring we

found a peak in segment #3

7

RESERVED

R

0h

7h

Reserved

6-4

TDR_FWD_SHADOW_SE R/W

G2

Indicates how much time to wait after max level before declaring we

found a peak in segment #2

3

RESERVED

R

0h

6h

Reserved

2-0

TDR_FWD_SHADOW_SE R/W

G1

Indicates how much time to wait after max level before declaring we

found a peak in segment #1

9.6.1.51 TDR_GEN_CFG4 Register (Offset = 185h) [Reset = 19CFh]

TDR_GEN_CFG4 is shown in TDR_GEN_CFG4 Register Field Descriptions.

Return to the Summary Table.

表9-69. TDR_GEN_CFG4 Register Field Descriptions

Bit

15-14

13-11

10-9

8

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

TDR_SDW_AVG_LOC

RESERVED

R/W

R

3h

how much to look between segments to search average peak

Reserved

0h

TDR_TX_TYPE_SEG5

TDR_TX_TYPE_SEG4

TDR_TX_TYPE_SEG3

TDR_TX_TYPE_SEG2

TDR_TX_TYPE_SEG1

R/W

1h

the tx type (10/100) for this segment

7

1h

6

1h

5

0h

4

0h

3-0

TDR_FWD_SHADOW_SE R/W

G5

Fh

Indicates how much time to wait after max level before declaring we

found a peak in segment #5

9.6.1.52 TDR_PEAKS_LOC_A_0_1 Register (Offset = 190h) [Reset = 0000h]

TDR_PEAKS_LOC_A_0_1 is shown in TDR_PEAKS_LOC_A_0_1 Register Field Descriptions.

Return to the Summary Table.

表9-70. TDR_PEAKS_LOC_A_0_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-8

TDR_PEAKS_LOC_A_1

R

0h

Found peak location 1 in channel A

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表9-70. TDR_PEAKS_LOC_A_0_1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

7-0

TDR_PEAKS_LOC_A_0

R

0h

Found peak location 0 in channel A

9.6.1.53 TDR_PEAKS_LOC_A_2_3 Register (Offset = 191h) [Reset = 0000h]

TDR_PEAKS_LOC_A_2_3 is shown in TDR_PEAKS_LOC_A_2_3 Register Field Descriptions.

Return to the Summary Table.

表9-71. TDR_PEAKS_LOC_A_2_3 Register Field Descriptions

Bit

15-8

7-0

Field

Type

Reset

Description

TDR_PEAKS_LOC_A_3

TDR_PEAKS_LOC_A_2

R

0h

Found peak location 3 in channel A

Found peak location 2 in channel A

R

0h

9.6.1.54 TDR_PEAKS_LOC_A_4_B_0 Register (Offset = 192h) [Reset = 0000h]

TDR_PEAKS_LOC_A_4_B_0 is shown in TDR_PEAKS_LOC_A_4_B_0 Register Field Descriptions.

Return to the Summary Table.

表9-72. TDR_PEAKS_LOC_A_4_B_0 Register Field Descriptions

Bit

15-8

7-0

Field

Type

Reset

Description

TDR_PEAKS_LOC_B_0

TDR_PEAKS_LOC_A_4

R

0h

Found peak location 0 in channel B

Found peak location 4 in channel A

R

0h

9.6.1.55 TDR_PEAKS_LOC_B_1_2 Register (Offset = 193h) [Reset = 0000h]

TDR_PEAKS_LOC_B_1_2 is shown in TDR_PEAKS_LOC_B_1_2 Register Field Descriptions.

Return to the Summary Table.

表9-73. TDR_PEAKS_LOC_B_1_2 Register Field Descriptions

Bit

15-8

7-0

Field

Type

Reset

Description

TDR_PEAKS_LOC_B_2

TDR_PEAKS_LOC_B_1

R

0h

Found peak location 2 in channel B

Found peak location 1 in channel B

R

0h

9.6.1.56 TDR_PEAKS_LOC_B_3_4 Register (Offset = 194h) [Reset = 0000h]

TDR_PEAKS_LOC_B_3_4 is shown in TDR_PEAKS_LOC_B_3_4 Register Field Descriptions.

Return to the Summary Table.

表9-74. TDR_PEAKS_LOC_B_3_4 Register Field Descriptions

Bit

15-8

7-0

Field

Type

Reset

Description

TDR_PEAKS_LOC_B_4

TDR_PEAKS_LOC_B_3

R

0h

Found peak location 4 in channel B

Found peak location 3 in channel B

R

0h

9.6.1.57 TDR_PEAKS_LOC_C_0_1 Register (Offset = 195h) [Reset = 0000h]

TDR_PEAKS_LOC_C_0_1 is shown in TDR_PEAKS_LOC_C_0_1 Register Field Descriptions.

Return to the Summary Table.

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表9-75. TDR_PEAKS_LOC_C_0_1 Register Field Descriptions

Bit

15-8

7-0

Field

Type

Reset

Description

TDR_PEAKS_LOC_C_1

TDR_PEAKS_LOC_C_0

R

0h

Found peak location 1 in channel C

Found peak location 0 in channel C

R

0h

9.6.1.58 TDR_PEAKS_LOC_C_2_3 Register (Offset = 196h) [Reset = 0000h]

TDR_PEAKS_LOC_C_2_3 is shown in TDR_PEAKS_LOC_C_2_3 Register Field Descriptions.

Return to the Summary Table.

表9-76. TDR_PEAKS_LOC_C_2_3 Register Field Descriptions

Bit

15-8

7-0

Field

Type

Reset

Description

TDR_PEAKS_LOC_C_3

TDR_PEAKS_LOC_C_2

R

0h

Found peak location 3 in channel C

Found peak location 2 in channel C

R

0h

9.6.1.59 TDR_PEAKS_LOC_C_4_D_0 Register (Offset = 197h) [Reset = 0000h]

TDR_PEAKS_LOC_C_4_D_0 is shown in TDR_PEAKS_LOC_C_4_D_0 Register Field Descriptions.

Return to the Summary Table.

表9-77. TDR_PEAKS_LOC_C_4_D_0 Register Field Descriptions

Bit

15-8

7-0

Field

Type

Reset

Description

TDR_PEAKS_LOC_D_0

TDR_PEAKS_LOC_C_4

R

0h

Found peak location 0 in channel D

Found peak location 4 in channel C

R

0h

9.6.1.60 TDR_PEAKS_LOC_D_1_2 Register (Offset = 198h) [Reset = 0000h]

TDR_PEAKS_LOC_D_1_2 is shown in TDR_PEAKS_LOC_D_1_2 Register Field Descriptions.

Return to the Summary Table.

表9-78. TDR_PEAKS_LOC_D_1_2 Register Field Descriptions

Bit

15-8

7-0

Field

Type

Reset

Description

TDR_PEAKS_LOC_D_2

TDR_PEAKS_LOC_D_1

R

0h

Found peak location 2 in channel D

Found peak location 1 in channel D

R

0h

9.6.1.61 TDR_PEAKS_LOC_D_3_4 Register (Offset = 199h) [Reset = 0000h]

TDR_PEAKS_LOC_D_3_4 is shown in TDR_PEAKS_LOC_D_3_4 Register Field Descriptions.

Return to the Summary Table.

表9-79. TDR_PEAKS_LOC_D_3_4 Register Field Descriptions

Bit

15-8

7-0

Field

Type

Reset

Description

TDR_PEAKS_LOC_D_4

TDR_PEAKS_LOC_D_3

R

0h

Found peak location 4 in channel D

Found peak location 3 in channel D

R

0h

9.6.1.62 TDR_GEN_STATUS Register (Offset = 1A4h) [Reset = 0000h]

TDR_GEN_STATUS is shown in TDR_GEN_STATUS Register Field Descriptions.

Return to the Summary Table.

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表9-80. TDR_GEN_STATUS Register Field Descriptions

Bit

15-12

11

Field

Type

Reset

Description

RESERVED

R

0h

Reserved

TDR_P_LOC_CROSS_M

ODE_D

R

0h

Peak found at cross mode in channel D

10

9

8

7

6

5

4

3

2

1

0

TDR_P_LOC_CROSS_M

ODE_C

R

0h

Peak found at cross mode in channel C

Peak found at cross mode in channel B

Peak found at cross mode in channel A

TDR_P_LOC_CROSS_M

ODE_B

TDR_P_LOC_CROSS_M

ODE_A

TDR_P_LOC_OVERFLO

W_D

Total number of peaks in current segment reached max value of 5 in

channel D

TDR_P_LOC_OVERFLO

W_C

Total number of peaks in current segment reached max value of 5 in

channel C

TDR_P_LOC_OVERFLO

W_B

Total number of peaks in current segment reached max value of 5 in

channel B

TDR_P_LOC_OVERFLO

W_A

Total number of peaks in current segment reached max value of 5 in

channel A

TDR_SEG1_HIGH_CROS R

S_D

Peak crossed high threshold of segment #1 in channel D

peak crossed high threshold of segment #1 in channel C

peak crossed high threshold of segment #1 in channel B

peak crossed high threshold of segment #1 in channel A

TDR_SEG1_HIGH_CROS R

S_C

TDR_SEG1_HIGH_CROS R

S_B

TDR_SEG1_HIGH_CROS R

S_A

9.6.1.63 TDR_PEAKS_SIGN_A_B Register (Offset = 1A5h) [Reset = 0000h]

TDR_PEAKS_SIGN_A_B is shown in TDR_PEAKS_SIGN_A_B Register Field Descriptions.

Return to the Summary Table.

表9-81. TDR_PEAKS_SIGN_A_B Register Field Descriptions

Bit

Field

Type

Reset

Description

15-10

RESERVED

R

0h

Reserved

9

8

7

6

5

4

3

2

1

0

TDR_PEAKS_SIGN_B_4

TDR_PEAKS_SIGN_B_3

TDR_PEAKS_SIGN_B_2

TDR_PEAKS_SIGN_B_1

TDR_PEAKS_SIGN_B_0

TDR_PEAKS_SIGN_A_4

TDR_PEAKS_SIGN_A_3

TDR_PEAKS_SIGN_A_2

TDR_PEAKS_SIGN_A_1

TDR_PEAKS_SIGN_A_0

R

0h

found peaks sign 4 in channel B

found peaks sign 3 in channel B

found peaks sign 2 in channel B

found peaks sign 1 in channel B

found peaks sign 0 in channel B

found peaks sign 4 in channel A

found peaks sign 3 in channel A

found peaks sign 2 in channel A

found peaks sign 1 in channel A

found peaks sign 0 in channel A

R

0h

R

0h

R

0h

R

0h

R

0h

R

0h

R

0h

R

0h

R

0h

9.6.1.64 TDR_PEAKS_SIGN_C_D Register (Offset = 1A6h) [Reset = 0000h]

TDR_PEAKS_SIGN_C_D is shown in TDR_PEAKS_SIGN_C_D Register Field Descriptions.

Return to the Summary Table.

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表9-82. TDR_PEAKS_SIGN_C_D Register Field Descriptions

Bit

Field

Type

Reset

Description

15-10

RESERVED

R

0h

Reserved

9

8

7

6

5

4

3

2

1

0

TDR_PEAKS_SIGN_D_4

TDR_PEAKS_SIGN_D_3

TDR_PEAKS_SIGN_D_2

TDR_PEAKS_SIGN_D_1

TDR_PEAKS_SIGN_D_0

TDR_PEAKS_SIGN_C_4

TDR_PEAKS_SIGN_C_3

TDR_PEAKS_SIGN_C_2

TDR_PEAKS_SIGN_C_1

TDR_PEAKS_SIGN_C_0

R

0h

found peaks sign 4 in channel D

found peaks sign 3 in channel D

found peaks sign 2 in channel D

found peaks sign 1 in channel D

found peaks sign 0 in channel D

found peaks sign 4 in channel C

found peaks sign 3 in channel C

found peaks sign 2 in channel C

found peaks sign 1 in channel C

found peaks sign 0 in channel C

R

0h

R

0h

R

0h

R

0h

R

0h

R

0h

R

0h

R

0h

R

0h

9.6.1.65 OP_MODE_DECODE Register (Offset = 1DFh) [Reset = 0040h]

OP_MODE_DECODE is shown in OP_MODE_DECODE Register Field Descriptions.

Return to the Summary Table.

表9-83. OP_MODE_DECODE Register Field Descriptions

Bit

15-9

8-7

6

Field

Type

Reset

Description

Reserved

RESERVED

R

0h

R

0h

BRIDGE_MODE_RGMII_ R/W

MAC

1h

0h = RGMII to SGMII Bridge

1h = SGMII to RGMII Bridge

5

RGMII_MII_SEL

R/W

0h

0h = RGMII

1h = MII

4

3

RESERVED

CFG_OPMODE

R

0h

Reserved

R

2-0

R/W

Operation Mode

0h = RGMII to Copper

1h = RGMII to 1000Base-X

2h = RGMII to 100Base-FX

3h = RGMII to SGMII

4h = 1000Base-T to 1000Base-X

5h = 100Base-T to 100Base-FX

6h = SGMII to Copper

7h = Reserved

9.6.1.66 GPIO_MUX_CTRL Register (Offset = 1E0h) [Reset = 417Ah]

GPIO_MUX_CTRL is shown in GPIO_MUX_CTRL Register Field Descriptions.

Return to the Summary Table.

表9-84. GPIO_MUX_CTRL Register Field Descriptions

Bit

15-12

11-8

7-4

Field

Type

R/W

Reset

Description

Reserved

RESERVED

4h

1h

JTAG_TDO_GPIO_1_CT R/W

RL

7h

See bits [3:0] for GPIO control options. If either type of SFD is

enabled, this pin will be automatically configured to TX_SFD.

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表9-84. GPIO_MUX_CTRL Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3-0

LED_2_GPIO_0_CTRL

R/W

Ah

Following options are available for GPIO control. If either type of

SFD is enabled, this pin will be automatically configured to RX_SFD.

0h = CLK_OUT

1h = RESERVED

2h = INT

3h = Link status

4h = RESERVED

5h = Transmit SFD

6h = Receive SFD

7h = WOL

8h = Energy detect(1000Base-T and 100Base-TX only)

9h = PRBS errors

Ah = LED_2

Bh = LED_GPIO(3)

Ch = CRS

Dh = COL

Eh = constant '0'

Fh = constant '1'

9.6.1.67 MC_LINK_LOSS Register (Offset = 1ECh) [Reset = 1FFDh]

MC_LINK_LOSS is shown in MC_LINK_LOSS Register Field Descriptions.

Return to the Summary Table.

表9-85. MC_LINK_LOSS Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

Reserved

15-13

RESERVED

0h

12-9

8

Fh

1h

7

1h

6

1h

5

1h

4

1h

3

1h

2-1

0

2h

CFG_NO_LINK_LINK_LO R/W

SS_EN

1h

Disables MC link_loss feature when there is no_link for given time.

0h = Enable link loss feature

1h = Disable link loss feature

9.6.1.68 FX_CTRL Register (Offset = C00h) [Reset = 1140h]

FX_CTRL is shown in FX_CTRL Register Field Descriptions.

Return to the Summary Table.

Registers after 0xC00 are common for Fiber, SGMII IP blocks for RGMII-to-SGMII, SGMII-to-RGMII, and Media

Convertor.

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表9-86. FX_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

15

CTRL0_RESET

R/W

0h

Controls reset in Fiber mode. This bit is automatically cleared after

reset is completed.

0h = Normal Operation

1h = Reset.

14

13

CTRL0_LOOPBACK

R/W

0h

100BASE-X, 1000BASE-FX and RGMII-SGMII, SGMII-RGMII MAC

loopback.

0h = Disable MAC loopback

1h = Enable MAC Loopback

CTRL0_SPEED_SEL_LS R/W

B

Speed selection bits LSB[13] and MSB[6] are used to control the

data rate of the ethernet link when in Fiber Ethernet mode. These

bits are also affected by straps.

0h = 10Mbps

1h = 100Mbps

2h = 1000Mbps

3h = Reserved

12

11

10

9

CTRL0_ANEG_EN

CTRL0_PWRDN

R/W

1h

0h

1h

Enable 1000BASE-X, R2S, S2R Bridge mode Auto-negotiation.

Controlled by strap.

0h = Disable

1h = Enable

Power Down SGMII for R2S, S2R, 1000BX, 100FX. Digital is in

reset.

0h = Normal operation

1h = Power Down

CTRL0_ISOLATE

CTRL0_RESTART_AN

Isolate MAC interface. Used in 1000BX, 100FX and RGMII-SGMII

mode. N/A in SGMII-RGMII mode.

0h = Normal operation

1h = Isolate

Writing 1 to this control bit restarts Autoneg in SGMII and 1000B-X

mode. It is self-cleared by hardware.

0h = Normal operation

1h = Restart 1000BASE-X/SGMII Auto-Negotiation Process

8

CTRL0_DUPLEX_MODE R/W

Forced Duplex mode. Applicable only in MII-100FX mode.

0h = Half duplex mode

1h = Full duplex mode

7

6

CTRL0_COL_TEST

R/W

0h

1h

0h

Used to test collision functionality. Settings this bit asserts collision

on just asserting tx_en

CTRL0_SPEED_SEL_MS R/W

B

Forced Speed for SGMII only when Autoneg is disabled. Controlled

by straps. See bit 13 of this register.

5-0

RESERVED

R/W

Reserved

9.6.1.69 FX_STS Register (Offset = C01h) [Reset = 6149h]

FX_STS is shown in FX_STS Register Field Descriptions.

Return to the Summary Table.

表9-87. FX_STS Register Field Descriptions

Bit

15

14

13

12

Field

Type

Reset

Description

STTS_100B_T4

STTS_100B_X_FD

STTS_100B_X_HD

STTS_10B_FD

R

0h

Return Always 0. Device doesn 't support 100BASE-T4 mode

Return Always 1. Device supports 100BASE-FX Full-Duplex

Return Always 1. Device supports 100BASE-FX Half-Duplex

Return Always 0. Device doesn 't support 10Mbps fiber mode

R

1h

R

1h

R

0h

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表9-87. FX_STS Register Field Descriptions (continued)

Bit

11

10

9

Field

Type

Reset

Description

STTS_10B_HD

STTS_100B_T2_FD

STTS_100B_T2_HD

R

0h

Return Always 0. Device doesn 't support 10Mbps fiber mode

Return Always 0. Device doesn 't support 100BASE-T2 mode

Return Always 1. Extended status information in register15

R

0h

R

0h

8

STTS_EXTENDED_STAT

US

R

1h

7

6

RESERVED

R

0h

1h

Reserved

STTS_MF_PREAMBLE_S R

UPRSN

Return Always 1. Phy accepts management frames with preamble

suppressed.

5

4

STTS_ANEG_COMPLET

E

R

0h

1: Auto negotiation process complete

0:Auto negotiation process not complete

STTS_REMOTE_FAULT

R

1: Remote fault condition detected

0:Remote fault condition not detected

3

2

STTS_ANEG_ABILITY

STTS_LINK_STATUS

R

1h

0h

Return Always 1. Device capable of performing Auto-Negotiation

1: link-up 0: link down Indicates 100FX link-up in 100FX and 100FX

MC Mode.

Indicates 1000X link-up in 1000X and 1000X MC mode.

In RGMII-SGMII mode, it indicates SGMII link-up and LP link up if

Autoneg is enabled else(if autoneg disabled) it indicates SGMII link-

up.

In SGMII-RGMII mode, it indicates LP link-up

1

0

STTS_JABBER_DET

R

0h

1h

Return 0.

STTS_EXTENDED_CAPA R

BILITY

Return Always 1. Device supports Extended register capabilities

9.6.1.70 FX_PHYID1 Register (Offset = C02h) [Reset = 2000h]

FX_PHYID1 is shown in FX_PHYID1 Register Field Descriptions.

Return to the Summary Table.

表9-88. FX_PHYID1 Register Field Descriptions

Bit

Field

Type

Reset

0h

2000h

Description

Reserved

Organizationally Unique Identifier Bits 19:6

15-14

13-0

RESERVED

OUI_6_19_FIBER

R

9.6.1.71 FX_PHYID2 Register (Offset = C03h) [Reset = A0F1h]

FX_PHYID2 is shown in FX_PHYID2 Register Field Descriptions.

Return to the Summary Table.

表9-89. FX_PHYID2 Register Field Descriptions

Bit

15-10

9-4

Field

Type

Reset

Description

OUI_0_5_FIBER

MODEL_NUM_FIBER

REVISION_NUM_FIBER

R

28h

Organizationally Unique Identifier Bits 5:0

R

Fh

1h

model number

3-0

revision number

9.6.1.72 FX_ANADV Register (Offset = C04h) [Reset = 0020h]

FX_ANADV is shown in FX_ANADV Register Field Descriptions.

Return to the Summary Table.

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表9-90. FX_ANADV Register Field Descriptions

Bit

Field

Type

Reset

Description

15

BP_NEXT_PAGE

R/W

0h

Set this bit if next page needs to be advertised. 1 = Advertise 0 = Not

advertised

14

13-12

11-9

8

BP_ACK

R

0h

Always return 0

BP_REMOTE_FAULT

RESERVED

R/W

R

00 = LINK_OK 01=OFFLINE 10=LINK_FAILURE 11=AUTO_ERROR

Reserved

BP_ASYMMETRIC_PAUS R/W

E

1 = Asymmetric Pause 0 = No asymmetric Pause

7

6

BP_PAUSE

R/W

R

0h

1h

0h

1 = MAC PAUSE 0 = No MAC PAUSE

1 = Advertise 0 = Not advertised

Reserved. Set to 00000

BP_HALF_DUPLEX

BP_FULL_DUPLEX

BP_RSVD1

5

4-0

9.6.1.73 FX_LPABL Register (Offset = C05h) [Reset = 0000h]

FX_LPABL is shown in FX_LPABL Register Field Descriptions.

Return to the Summary Table.

表9-91. FX_LPABL Register Field Descriptions

Bit

Field

Type

Reset

Description

15

LP_ABILITY_NEXT_PAG

E

R

0h

0h = LP is not capable of next page

1h = LP is capable of next page

14

LP_ABILITY_ACK

R

0h

0h = LP has not acknowledged that it has received link code word

1h = LP acknowledges that it has received link code word

13-12

LP_ABILITY_REMOTE_F

AULT

Received Remote fault from LP.

0h = LINK_OK

1h = OFFLINE

2h = LINK_FAILURE

3h = AUTO_ERROR

11-9

8

RESERVED

R

0h

Reserved

LP_ABILITY_ASYMMETR R

IC_PAUSE

0h = LP does not request asymmetric pause

1h = LP requests of asymmetric pause

7

6

LP_ABILITY_PAUSE

R

0h

0h = LP is not capable of pause operation

1h = LP is capable of pause operation

LP_ABILITY_HALF_DUPL R

EX

0h = LP is not 1000BASE-X Half-duplex capable

1h = LP is 1000BASE-X Half-duplex capable

5

LP_ABILITY_FULL_DUPL R

EX

0h = LP is not 1000BASE-X Full-duplex capable

1h = LP is 1000BASE-X Full-duplex capable

4-0

RESERVED

R

Reserved

9.6.1.74 FX_ANEXP Register (Offset = C06h) [Reset = 0000h]

FX_ANEXP is shown in FX_ANEXP Register Field Descriptions.

Return to the Summary Table.

表9-92. FX_ANEXP Register Field Descriptions

Bit

Field

Type

Reset

Description

15-4

RESERVED

R

0h

Reserved

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表9-92. FX_ANEXP Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3

AN_EXP_LP_NEXT_PAG

E_ABLE

R

0h

1: Link partner is Next page able 0: Link partner is not next page able

Bit is set to 1 when device receives base page with NP bit (bit 15) set

to 1. It is cleared when Autoneg state goes to AN_ENABLE. It is

expected that NP bit will be set to 0 in SGMII mode as SGMII doesn

't supports next page.

2

1

0

AN_EXP_LOCAL_NEXT_

PAGE_ABLE

R

0h

1 : Local device is next page able 0 : Local device is not next page

able This bit is set to 1 in fiber 1000BASE-X mode. it is set to 0 in

SGMII mode.

AN_EXP_PAGE_RECEIV

ED

1 : A new page(base page or next page) has been received 0 : No

new page has been received Status is latched when new page is

received by the device. It is cleared when SW reads this register.

AN_EXP_LP_AUTO_NEG R

_ABLE

1: Link partner is auto negotiation able 0: Link partner is not auto

negotiation able Bit is set to 1 when device receives base page. It is

cleared when Autoneg state goes to AN_ENABLE.

9.6.1.75 FX_LOCNP Register (Offset = C07h) [Reset = 2001h]

FX_LOCNP is shown in FX_LOCNP Register Field Descriptions.

Return to the Summary Table.

表9-93. FX_LOCNP Register Field Descriptions

Bit

15

14

13

Field

Type

Reset

Description

NP_TX_NEXT_PAGE

RESERVED

R/W

0h

0: if last page 1: if there is more pages to transmit

Reserved

R

0h

1h

NP_TX_MESSAGE_PAG R/W

E_MODE

0: unformatted page 1: message page

12

11

NP_TX_ACK_2

R/W

0h

1h

device has the ability to comply with the message 0: cannot comply

with message. 1: comply with message.

NP_TX_TOGGLE

R

0: previous value of the transmitted link codeword equalled logic one.

1: previous value of the transmitted link codeword equalled logic zero

10-0

NP_TX_MESSAGE_FIEL R/W

D

Message code field as defined in IEEE Annex 28C

9.6.1.76 FX_LPNP Register (Offset = C08h) [Reset = 0000h]

FX_LPNP is shown in FX_LPNP Register Field Descriptions.

Return to the Summary Table.

表9-94. FX_LPNP Register Field Descriptions

Bit

15

14

13

Field

Type

Reset

Description

LP_NP_NEXT_PAGE

LP_NP_ACK

R

0h

LP last page 0: if last page 1: if there is more pages to transmit

Reserved

R

0h

LP_NP_MESSAGE_PAG

E_MODE

R

0h

LP message page mode 0: unformatted page 1: message page

12

11

LP_NP_ACK_2

R

0h

LP has the ability to comply with the message 0: cannot comply with

message. 1: comply with message.

LP_NP_TOGGLE

LP Toggle bit 0: previous value of the transmitted link codeword

equalled logic one. 1: previous value of the transmitted link codeword

equalled logic zero

10-0

LP_NP_MESSAGE_FIEL

D

R

0h

LP Message code field as defined in IEEE Annex 28C

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9.6.1.77 CFG_FX_CTRL0 Register (Offset = C10h) [Reset = 0000h]

CFG_FX_CTRL0 is shown in CFG_FX_CTRL0 Register Field Descriptions.

Return to the Summary Table.

表9-95. CFG_FX_CTRL0 Register Field Descriptions

Bit

15-10

9

Field

Type

Reset

Description

RESERVED

CFG_SDIN

R

0h

RESERVED

R/W

0h

0h = Use Signal Detect Pin

1h = Signal Detect Pin is not used

8-0

RESERVED

R

0h

RESERVED

9.6.1.78 FX_INT_EN Register (Offset = C18h) [Reset = 03FFh]

FX_INT_EN is shown in FX_INT_EN Register Field Descriptions.

Return to the Summary Table.

表9-96. FX_INT_EN Register Field Descriptions

Bit

15-10

9

Field

Type

Reset

Description

RESERVED

FEF_FAULT_EN

R

0h

Reserved

R/W

1h

FEF fault received interrupt enable

0h = Disable Interrupt

1h = Enable Interrupt

8

7

6

5

4

3

2

1

0

TX_FIFO_FULL_EN

TX_FIFO_EMPTY_EN

RX_FIFO_FULL_EN

RX_FIFO_EMPTY_EN

Fiber and SGMII Tx FIFO full interrupt enable

0h = Disable Interrupt

1h = Enable Interrupt

Fiber and SGMII Tx FIFO empty interrupt enable

0h = Disable Interrupt

1h = Enable Interrupt

Fiber and SGMII Rx FIFO full interrupt enable

0h = Disable Interrupt

1h = Enable Interrupt

Fiber and SGMII Rx FIFO empty interrupt enable

0h = Disable Interrupt

1h = Enable Interrupt

LINK_STS_CHANGE_EN R/W

Link Status Change Interrupt Enable

0h = Disable Interrupt

1h = Enable Interrupt

LP_FAULT_RX_EN

PRI_RES_FAIL_EN

LP_NP_RX_EN

R/W

Link Partner Remote Fault Interrupt Enable

0h = Disable Interrupt

1h = Enable Interrupt

Priority Resolution Fail Interrupt Enable

0h = Disable Interrupt

1h = Enable Interrupt

Link Partner Next Page Received Interrupt Enable

0h = Disable Interrupt

1h = Enable Interrupt

LP_BP_RX_EN

Link Partner Base Page Received Interrupt Enable

0h = Disable Interrupt

1h = Enable Interrupt

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9.6.1.79 FX_INT_STS Register (Offset = C19h) [Reset = 0000h]

FX_INT_STS is shown in FX_INT_STS Register Field Descriptions.

Return to the Summary Table.

表9-97. FX_INT_STS Register Field Descriptions

Bit

15-10

9

Field

Type

Reset

Description

RESERVED

FEF_FAULT

R

0h

Reserved

RC

0h

FEF fault received interrupt

0h = No Interrupt pending

1h = Interrupt pending, cleared on read

8

7

6

5

4

3

2

1

0

TX_FIFO_FULL

TX_FIFO_EMPTY

RX_FIFO_FULL

RX_FIFO_EMPTY

LINK_STS_CHANGE

LP_FAULT_RX

PRI_RES_FAIL

LP_NP_RX

Fiber Tx FIFO full interrupt

0h = No Interrupt pending

1h = Interrupt pending, cleared on read

Fiber Tx FIFO empty interrupt

0h = No Interrupt pending

1h = Interrupt pending, cleared on read

Fiber Rx FIFO full interrupt

0h = No Interrupt pending

1h = Interrupt pending, cleared on read

Fiber Rx FIFO empty interrupt

0h = No Interrupt pending

1h = Interrupt pending, cleared on read

Link Status Change Interrupt

0h = No Interrupt pending

1h = Interrupt pending, cleared on read

Link Partner Remote Fault Interrupt

0h = No Interrupt pending

1h = Interrupt pending, cleared on read

Priority Resolution Fail Interrupt

0h = No Interrupt pending

1h = Interrupt pending, cleared on read

Link Partner Next Page Received Interrupt

0h = No Interrupt pending

1h = Interrupt pending, cleared on read

LP_BP_RX

Link Partner Base Page Received Interrupt

0h = No Interrupt pending

1h = Interrupt pending, cleared on read

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10 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

10.1 Application Information

The DP83869HM is a 10/100/1000 Copper and Fiber Ethernet PHY. It supports connections to an Ethernet MAC

through SGMII or RGMII. MII is also supported but only for 100M and 10M speeds. For MII to be operate

correctly, 1000M advertisement should be disabled. SGMII is not available in Fiber Ethernet mode and Media

Convertor mode because the SGMII pins are multipurpose pins which carry Fiber Ethernet signals. Connections

to the Ethernet media are made through the IEEE 802.3 defined Media Dependent Interface.

When using the device for Ethernet application, it is necessary to meet certain requirements for normal operation

of the device. The following typical application and design requirements can be used for selecting appropriate

component values for the DP83869.

10.2 Typical Applications

10.2.1 Copper Ethernet Typical Application

10BASE-Te

100BASE-TX

1000BASE-T

RGMII

SGMII

MII

DP83869

10/100/1000 Mbps

Ethernet Physical Layer

Cable

Connector

Ethernet MAC

Magnetics

25 MHz

Crystal or Oscillator

Status

LEDs

图10-1. Typical Copper Ethernet Application

10.2.1.1 Design Requirements

The design requirements for the DP83869HM are:

• VDDA2P5 = 2.5 V

• VDD1P1 = 1.1 V

• VDDIO = 3.3 V, 2.5 V, or 1.8 V

• VDDA1P8_x = 1.8 V (optional)

• Clock Input = 25 MHz

10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Clock Input

Input reference clock requirements are same in all functional modes.

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10.2.1.2.1.1 Crystal Recommendations

A 25-MHz, parallel, 15-pF to 40-pF load crystal resonator should be used if a crystal source is desired. 图 10-2

shows a typical connection for a crystal resonator circuit. The load capacitor values vary with the crystal vendors.

Check with the vendor for the recommended loads.

XI

XO

R1

CL1

CL2

图10-2. Crystal Oscillator Circuit

As a starting point for evaluating the oscillator performance, the value of CL1 and CL2 should each be equal to

2x the specified load capacitance from the crystal vendor’s data sheet. For example, if the specified load

capacitance of the crystal is 10 pF, set CL1 = CL2 = 20 pF. CL1, CL2 value may need to be adjusted based on

the parasitic capacitance. Depending on the crystal drive level, R1 may or may not be needed.

Specification for 25-MHz crystal are listed in 表10-1.

表10-1. 25-MHz Crystal Specifications

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

Frequency

25

MHz

Frequency

Tolerance

Including Operational Temperature, Aging, and

Other Factors

±100

ppm

Load Capacitance

ESR

15

40

50

pF

ohm

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10.2.1.2.1.2 External Clock Source Recommendation

If an external clock oscillator is used, then it should be directly connected to XI. XO should be left floating.

The CMOS 25-MHz oscillator specifications are listed in 表10-2.

表10-2. 25-MHz Oscillator Specifications

PARAMETER

Frequency

TEST CONDITION

MIN

TYP

MAX

UNIT

MHz

ppm

ns

25

Frequency Tolerance

Rise / Fall Time

Symmetry

Operational Temperature, 1 Year Aging

±100

5

20% - 80%

Duty Cycle

40%

60%

10.2.1.2.2 Magnetics Requirements

In applications where copper Ethernet interface is used, magnetic isolation is required. Magnetics can be

discrete or integrated in the Ethernet cable connector. The DP83869HM will operate with discrete and integrate

magnetics if they meet the electrical specifications listed in 表10-3.

表10-3. Magnetics Electrical Specification

PARAMETER

Turns Ratio

TEST CONDITIONS

±2% Tolerance

1-100 MHz

1-30 MHz

TYP

UNIT

-

1:1

Insertion Loss

-1

dB

µH

Vrms

-16

-12

-10

-30

-20

-35

-30

350

1500

Return Loss

30-60 MHz

60-80 MHz

1-50 MHz

Differential to Common

Mode Rejection

60-150 MHz

30 MHz

Crosstalk

60 MHz

Open Circuit Inductance

Isolation

8-mA DC Bias

HPOT

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10.2.1.2.2.1 Magnetics Connection

DP83869

Magnetics

RJ-45 Connector

TD_P_A

Pin 1

TD_M_A

TD_P_B

Pin 2

Pin 3

TD_M_B

TD_P_C

Pin 6

Pin 4

TD_M_C

TD_P_D

Pin 5

Pin 7

TD_M_D

Pin 8

0.1µF

75ꢀ

1nF

2kV

A. Each center tap on the side connected to the PHY, must be isolated from one another and connected to ground via a decoupling

capacitor (0.1 µF recommended).

B. Pulse Electronics part, HX5008FNL is recommended for a discrete magnetics solution.

图10-3. PHY to RJ45 and Magnetics

10.2.1.3 Application Curves

For expected MDI signal, see 表10-4.

表10-4. Table of Graphs

NAME

FIGURE

图8-9

1000Base-T Signal

100Base-TX Signal

10Base-Te Link Pulse

Auto-Negotiation FLP

图8-10

图8-11

图8-12

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10.2.2 Fiber Ethernet Typical Ethernet

100BASE-FX

1000BASE-X

RGMII

MII

DP83869

10/100/1000 Mbps

Ethernet Physical Layer

Fiber

Transceiver

Capacitive

Isolation

Ethernet MAC

25 MHz

Crystal or Oscillator

Status

LEDs

图10-4. Typical Fiber Ethernet Application

10.2.2.1 Design Requirements

The design requirements for the DP83869HM are:

• VDDA2P5 = 2.5 V

• VDD1P1 = 1.1 V

• VDDIO = 3.3 V, 2.5 V, or 1.8 V

• VDDA1P8_x = 1.8 V (optional)

• Clock Input = 25 MHz

10.2.2.2 Detailed Design Procedure

See 节10.2.1.2 for more information.

10.2.2.2.1 Transceiver Connections

DP83869

SFP Fiber Transceiver

SOP

SON

TD+

TD-

SIP

SIN

RD+

RD-

LOS/SD

SD

SFP Fiber Transceiver usually have

integrated AC coupling capacitors. Adding

external capacitors may not be needed.

图10-5. PHY to Fiber Transceiver Connections

10.2.2.3 Application Curves

For expected MDI signal, see 表10-4 in the 节10.2.1.3 section.

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11 Power Supply Recommendations

The DP83869HM is capable of operating with as few as two or three supplies. The I/O power supply can also be

operated independently of the main device power supplies to provide flexibility for the MAC interface. There are

two possible supply configuration that can be used: Two-supply and Three-supply. In Two-supply Configuration,

no power rail is connected to VDDA1P8_x pins (pin 13, 48). When unused, pin 13 and 48 should be left floating

with no components attached to them.

11.1 Two-Supply Configuration

图11-1 shows the connection diagram for a two-supply configuration.

图11-1. Two-Supply Configuration

For a two-supply configuration, both VDDA1P8 pins must be left unconnected.

Place 1-μF and 0.1-μF decoupling capacitors as close as possible to component VDD pins, placing the 0.1-μF

capacitor closest to the pin.

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The strap (SUPPLYMODE_SEL, pin 23) shall be pulled low to set double supply mode. VDDIO may be 3.3 V,

2.5 V, or 1.8 V. VDDIO_SEL strap shall be selected appropriately to VDDIO voltage applied.

For two-supply configuration, the recommendation is to power all supplies together. If that is not possible, then

the following power sequencing must be used.

VDDA2P5

t1

VDD1P1

tt2t

VDDIO

图11-2. Two-Supply Sequence Diagram

表11-1. Two-Supply Sequence

PARAMETER

Supply ramp time

TEST CONDITIONS

MIN

NOM

MAX

UNIT

ms

t1

t2

Applicable to all supplies

0.5

100

Time instance at which VDDIO

starts up

Measured with respect to start of

VDDA2P5 and VDD1P1

ms

50

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11.2 Three-Supply Configuration

图11-3 shows the connection diagram for the three-supply configuration.

图11-3. Three-Supply Configuration

Place 1-μF and 0.1-μF decoupling capacitors as close as possible to component VDD pins, placing the 0.1-μF

capacitor closest to the pin.

备注

The strap (SUPPLYMODE_SEL, pin 23) shall be pulled high to set triple-supply mode. VDDIO may be

3.3 V, 2.5 V, or 1.8 V. VDDIO strap shall be selected appropriately to VDDIO voltage applied.

For three-supply configuration, the recommendation is to power all supplies together. If that is not possible, then

the following power sequencing must be used.

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VDDA2P5

t1

VDD1P1

VDDIO

tt2t

tt3t

VDDA1P8_1

VDDA1P8_2

图11-4. Three-Supply Sequence Diagram

表11-2. Three-Supply Sequence

PARAMETER

Supply ramp time

TEST CONDITIONS

MIN

NOM

MAX

UNIT

t1

t2

Applicable to all supplies

0.5

0

100

ms

Time instance at which VDDIO starts Measured with respect to start of

up

ms

50

VDDA2P5 and VDD1P1

t3

Time instance at which VDDA1P8_x

starts up

Measured with respect to start of

VDDA2P5 and VDD1P1

0

ms

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12 Layout

12.1 Layout Guidelines

12.1.1 Signal Traces

PCB traces are lossy and long traces can degrade the signal quality. Traces must be kept short as possible.

Unless mentioned otherwise, all signal traces should be 50-Ω, single-ended impedance. Differential traces

should be 50-Ω, single-ended and 100-Ω differential. Take care that the impedance is constant throughout.

Impedance discontinuities cause reflections leading to EMI and signal integrity problems. Stubs must be avoided

on all signal traces, especially the differential signal pairs. See 图12-1.

Within the differential pairs, the trace lengths must run parallel to each other and matched in length. Matched

lengths minimize delay differences, avoiding an increase in common-mode noise and increased EMI.

Length matching is also important on MAC interface. All Transmit signal trace lengths must match to each other

and all Receive signal trace lengths must match to each other. When using 1G transmission speeds, the

tolerance for length matching is 50 mils. When using 100/10M, the tolerance for length matching is 100 mils.

Ideally, there should be no crossover or via on the signal paths. Vias present impedance discontinuities and

should be minimized. Route an entire trace pair on a single layer if possible.

图12-1. Avoiding Stubs in a Differential Signal Pair

Signals on different layers should not cross each other without at least one return path plane between them.

Coupling between traces is also an important factor. Unwanted coupling can cause cross talk problems.

Differential pairs on the other hand, should have a constant coupling distance between them.

For convenience and efficient layout process, start by routing the critical signals first.

12.1.1.1 MAC Interface Layout Guidelines

The Media Independent Interface (SGMII / RGMII) connects the DP83869 to the Media Access Controller

(MAC). The MAC may in fact be a discrete device, integrated into a microprocessor, CPU, or FPGA.

12.1.1.1.1 SGMII Layout Guidelines

• All SGMII connections must be AC-coupled through an 0.1-µF capacitor. Series capacitors must be 0.1 µF

and the size should be 0402 or smaller.

• SGMII signals are differential signals.

• Traces must be routed with 100-Ωdifferential impedance.

• Skew matching within a pair must be less than 5 pS, which correlates to 30 mil for standard FR4.

• There is no requirement to match the TX pair to the RX pair.

• SGMII signals must be routed on the same layer.

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• Pairs must be referenced to parallel ground plane.

• When operating in 6-wire mode, the RX pair must match the Clock pair to within 5 pS, which correlates to 30

mil for standard FR4.

12.1.1.1.2 RGMII Layout Guidelines

• RGMII signals are single-ended signals.

• Traces must be routed with impedance of 50 Ωto ground.

• Skew between TXD[3:0] lines should be less than 11 ps, which correlates to 60 mil for standard FR4.

• Skew between RXD[3:0] lines should be less than 11 ps, which correlates to 60 mil for standard FR4.

• Keep trace lengths as short as possible, Traces less than 2 inches is recommended with less than 6 inches

as maximum length.

• Configurable clock skew for GTX_CLK and RX_CLK.

– Clock skew for RX and TX paths can be optimized independently.

– Clock skew is adjustable in 0.25-ns increments (through register).

12.1.1.2 MDI Layout Guidelines

The Media Dependent Interface (MDI) connects the DP83869 to the transformer and the Ethernet network.

• MDI traces must be 50 Ωto ground and 100-Ωdifferential controlled impedance.

• Route MDI traces to transformer on the same layer.

• Use a metal shielded RJ-45 connector, and connect the shield to chassis ground.

• Use magnetics with integrated common-mode choking devices.

• Void supplies and ground beneath magnetics.

• Do not overlap the circuit and chassis ground planes, keep them isolated. Instead, make chassis ground an

isolated island and make a void between the chassis and circuit ground. Connecting circuit and chassis

planes using a size 1206 resistor and capacitor on either side of the connector is a good practice.

12.1.2 Return Path

A general best practice is to have a solid return path beneath all signal traces. This return path can be a

continuous ground or DC power plane. Reducing the width of the return path width can potentially affect the

impedance of the signal trace. This effect is more prominent when the width of the return path is comparable to

the width of the signal trace. Breaks in return path beneath the signal traces should be avoided at all cost. A

signal crossing a plane split may cause unpredictable return path currents and would likely impact signal quality

as well, potentially creating EMI problems. See 图12-2.

图12-2. Differential Signal Pair-Plane Crossing

12.1.3 Transformer Layout

There should be no metal layer running beneath the transformer. Transformers can inject noise in metal beneath

them which can affect the performance of the system.

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12.1.4 Metal Pour

All metal pours which are not signals or power should be tied to ground. There should be no floating metal on

the system. There should be no metal between the differential traces.

12.1.5 PCB Layer Stacking

To meet signal integrity and performance requirements, at minimum a 4-layer PCB should be used. However a

6-layer board is recommended. See 图 12-3 for the recommended layer stack ups for 4, 6, and 8-layer boards.

These are recommendations not requirements, other configurations can be used as per system requirements.

图12-3. Recommended Layer Stack-Up

Within a PCB, it may be desirable to run traces using different methods, microstrip vs. stripline, depending on the

location of the signal on the PCB. For example, it may be desirable to change layer stacking where an isolated

chassis ground plane is used. 图12-4 shows alternative PCB stacking options.

图12-4. Alternative Layer Stack-Up

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12.2 Layout Example

Plane

Coupling

Component

Transformer

RJ45

PHY

Component

(if not

Integrated in

RJ45)

Connector

Plane

Coupling

Component

Note: Power/Ground

Planes Voided under

Transformer

Chassis

Ground

Plane

System Power/

Ground Planes

图12-5. Copper Ethernet Layout Example

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13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation

For related documentation, see the following:

DP83869 1000Base-X Link Detection (SNLA305)

13.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

13.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

13.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

RGZ0048B

VQFN - 1 mm max height

S

C

A

L

E

2

.

0

PLASTIC QUAD FLATPACK - NO LEAD

7.15

6.85

A

B

PIN 1 INDEX AREA

7.15

6.85

1 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

2X 5.5

4.1 0.1

(0.2) TYP

EXPOSED

THERMAL PAD

13

24

44X 0.5

12

25

49

SYMM

2X

5.5

0.30

48X

36

0.18

1

0.1

C B A

48

37

0.05

SYMM

PIN 1 ID

(OPTIONAL)

0.5

0.3

48X

4218795/B 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RGZ0048B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

4.1)

(1.115) TYP

(0.685)

TYP

37

48

48X (0.6)

1

36

48X (0.24)

(1.115)

TYP

44X (0.5)

(0.685)

TYP

SYMM

49

(

0.2) TYP

VIA

(6.8)

(R0.05)

TYP

12

25

13

24

SYMM

(6.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4218795/B 02/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be ﬁlled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RGZ0048B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.37)

TYP

37

48

48X (0.6)

1

36

48X (0.24)

44X (0.5)

(1.37)

TYP

SYMM

49

(R0.05) TYP

(6.8)

9X

1.17)

METAL

TYP

(

12

25

13

24

SYMM

(6.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 49

73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:12X

4218795/B 02/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

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Product Folder Links: DP83869HM

GENERIC PACKAGE VIEW

RGZ 48

7 x 7, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUADFLAT PACK- NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224671/A

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型号：	DP83869HMRGZR
厂家：	TEXAS INSTRUMENTS
描述：	具有铜缆和光纤接口、支持工作温度范围的高抗扰性千兆位以太网 PHY 收发器 \| RGZ \| 48 \| -40 to 125 以太网光纤
文件：	总111页 (文件大小：3276K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DP83869HMRGZR [TI]

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