DP83910A [TI]
DP83910A CMOS SNI Serial Network Interface;
| 型号： | DP83910A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DP83910A CMOS SNI Serial Network Interface |
| 文件： | 总14页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DP83910A
DP83910A CMOS SNI Serial Network Interface
Literature Number: SNLS386
May 1995
DP83910A CMOS SNI
Serial Network Interface
General Description
The DP83910A CMOS Serial Network Interface (SNI) is a
direct-pin equivalent of the bipolar DP8391 SNI and pro-
vides the Manchester data encoding and decoding func-
tions for IEEE 802.3 Ethernet/Thin-Ethernet type local area
networks. The SNI interfaces the DP8390 Network Interface
Controller (NIC) to the DP8392 CTI or an Ethernet transceiv-
er cable. When transmitting, the SNI converts non-return-to-
zero (NRZ) data from the controller into Manchester data
and sends the converted data differentially to the transceiv-
er. Conversely, when receiving, a Phase Lock Loop de-
codes the 10 Mbit/s data from the transceiver into NRZ
data for the controller.
DP83910A, fabricated CMOS, typically consumes less than
70 mA of current. However, as a result of being CMOS, the
DP83910A’s differential signals must be isolated in both
Ethernet and thin wire Ethernet.
Features
Y
Compatible with Ethernet I, IEEE 802.3; 10BASE5,
10BASE2, and 10BASE-T
Y
Designed to interface with 10BASE-T transceivers
Y
Functional and pin-out duplicate of the DP8391
Y
10 Mbits/s Manchester encoding/decoding with receive
clock recovery
The DP83910A operates in conjunction with the DP8392
Coaxial Transceiver Interface (CTI) and the DP8390 Net-
work Interface Controller (NIC) to form a three-chip set that
implements a complete IEEE 802.3 compatible network as
shown below. The DP83910A is a functionally complete
Manchester encoder/decoder including a balanced driver
and receiver, on-board crystal oscillator, collision signal
Y
Requires no precision components
Y
Loopback capability for diagnostics
Y
Externally selectable half or full step modes of opera-
tion at transmit output
Y
Squelch circuitry at the receive and collision inputs to
reject noise
Y
translator, and
a
diagnostic loopback feature. The
TTL/MOS compatible controller interface
1.0 System Diagram
IEEE 802.3 Compatible Ethernet/Thin-Ethernet/10 BaseT
Local Area Network Chip Set
TL/F/9365–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9365
RRD-B30M105/Printed in U. S. A.
2.0 Block Diagram
TL/F/9365–2
3.0 Functional Description
The DP83910A consists of five main logical blocks:
a) The oscillator generates the 10 MHz transmit clock signal
for system timing.
b) The Manchester encoder accepts NRZ data from the
controller, encodes the data to Manchester, and trans-
mits it differentially to the transceiver, through the differ-
ential transmit driver.
c) The Manchester decoder receives Manchester data from
the transceiver, converts it to NRZ data and clock pulses,
and sends it to the controller.
d) The collision translator indicates to the controller the
presence of a valid 10 MHz collision signal to the PLL.
TL/F/9365–15
e) The loopback circuitry, when asserted, routes the data
from the Manchester encoder back to the PLL decoder.
Note 1: The resistor R1 may be required in order to minimize frequency drift
due to changes in the V . See text description.
CC
FIGURE 1. Crystal Connection to DP83910A
(see text for component values)
3.1 OSCILLATOR
The oscillator is controlled by a 20 MHz parallel resonant
crystal connected between X1 and X2 or by an external
clock on X1. The 20 MHz output of the oscillator is divided
by 2 to generate the 10 MHz transmit clock for the control-
ler. The oscillator also provides internal clock signals to the
encoding and decoding circuits.
should be made equal to five times the motional resistance
of the crystal.
The motional resistance of 20 MHz crystals is usually in the
range of 10X to 30X. This implies that a reasonable value
for R1 should be in the range of 50X–150X.
The decision of whether or not to include R1 should be
based upon measured variations of crystal frequency as
each of the circuit parameters is varied.
If a crystal is connected to the DP83910A, it is recommend-
ed that the circuit shown in Figure 1 be used and that the
components used meet the following:
According to the IEEE 802.3 standard, the entire oscillator
circuit (crytsal and amplifier) must be accurate to 0.01%.
When using a crystal, the X1 pin is not guaranteed to pro-
vide a TTL compatible logic output, and should not be used
to drive external standard logic. If additional logic needs to
be driven, then an external oscillator should be used, as
described in the following.
Crystal XT1: AT cut parallel resonant crystal
s
Series Resistance: 10X
Specified Load Capacitance: 13.5 pF
Accuracy: 0.005% (50 ppm)
C1, C2: Load Capacitor, 27 pF.
The resistor, R1, in Figure 1 may be required in order to
supply
minimize frequency drift due to changes in the V
CC
3.2 OSCILLATOR MODULE OPERATION
voltage. If R1 is required, it’s value must be carefully select-
ed. R1 decreases the loop gain. Thus, if R1 is made too
large, the loop gain will be greatly reduced and the crystal
will not oscillate. If R1 is made too small, normal variations
If the designer wishes to use a crystal clock oscillator, one
that provides the following should be employed:
1) TTL or CMOS output with a 0.01% frequency tolerance
2) 40%–60% duty cycle
in the V may cause the oscillation frequency to drift out of
CC
specification. As the first rule of thumb, the value of R1
t
3) 2 TTL load output drive (I
e
3.2 mA)
OL
2
3.0 Functional Description (Continued)
The circuit is shown inFigure 2. (Additional output drive may
be necessary if the oscillator must also drive other compo-
nents.) When using a clock oscillator it is still recommended
that the designer connect the oscillator output to the X1 pin
and tie the X2 pin to ground.
3.4 MANCHESTER DECODER
The decoder consists of a differential receiver and a PLL to
separate Manchester encoded data stream into clock sig-
nals and NRZ data. The differential input must be externally
terminated with two 39X resistors connected in series if the
standard 78X transceiver drop cable is used; in Thin-Ether-
net applications, these resistors are optional. To prevent
noise from falsely triggering the decoder, a squelch circuit at
3.3 MANCHESTER ENCODER AND
DIFFERENTIAL DRIVER
The encoder begins operation when the Transmit Enable
input (TXE) goes high and converts clock and NRZ data to
Manchester data for the transceiver. For the duration of
TXE remaining high, the Transmitted Data (TXD) is encoded
b
the input rejects signals with levels less than 175 mV.
Once the input exceeds the squelch requirements, Carrier
Sense (CRS) is asserted. Receive data (RXD) and receive
clock (RXC) become valid typically within 6 bit times. The
DP83910A may tolerate bit jitter up to 18 ns in the received
data.
g
for the transmit-driver pair (TX ). TXD must be valid on the
rising edge of Transmit Clock (TXC). Transmission ends
when TXE goes low. The last transition is always positive; it
occurs at the center of the bit cell if the last bit is a one, or at
the end of the bit cell if the last bit is a zero.
The decoder detects the end of a frame when no more
midbit transitions are detected. Within one and a half bit
times after the last bit, carrier sense is de-asserted. Receive
clock stays active for five more bit times after CRS goes low
to guarantee the receive timings of the DP8390 NIC.
The differential transmit pair from the secondary of the iso-
lation transformer drives up to 50 meters of twisted pair AUI
cable. These outputs are source followers which require two
270X pull-down resistors to ground.
3.5 COLLISION TRANSLATOR
The DP83910A allows both half-step and full-step to be
compatible with Ethernet I and IEEE 802.3. With the SEL pin
When the Ethernet transceiver (DP8392 CTI) detects a colli-
sion, it generates a 10 MHz signal to the differential collision
a
during idle; with SEL high (for IEEE 802.3),
g
low (for Ethernet I), transmit
b
is positive with respect to
inputs (CD ) of the DP83910A. When these inputs are de-
transmit
tected active, the DP83910A translates the 10 MHz signal
to an active high level for the controller. The controller uses
this signal to back off its current transmission and resched-
ule another one.
a
b
transmit and transmit are equal in the idle state. This
provides zero differential voltage to operate with transform-
er coupled loads.
The collision differential inputs are terminated the same way
as the differential receive inputs. The squelch circuitry is
b
also similar, rejecting pulses with levels less than 175 mV.
3.6 LOOPBACK FUNCTIONS
When the Loopback input (LBK) is asserted high, the
DP83910A redirects its transmitted data back into its re-
ceive path. This feature provides a convenient method for
testing both chip and system level integrity. The transmit
driver and receive input circuitry are disabled in loopback
mode.
TL/F/9365–16
FIGURE 2. DP83910A Connection for Oscillator Module
4.0 Connection Diagrams
TL/F/9365–17
TL/F/9365–18
Top View
Top View
Order Number DP83910AV
See NS Package Number V28A
Order Number DP83910AN
See NS Package Number N24C
3
5.0 Typical Application
4
6.0 Pin Descriptions
24-Pin DIP
28-Pin PCC
Name
I/O
Description
1
1
COL
O
COLLISION DETECT OUTPUT: Generates an active high signal when
10 MHz collision signal is detected.
2
3
2
3
RXD
CRS
O
O
RECEIVE DATA OUTPUT: NRZ data output from the PLL. This signal
must be sampled on the rising edge of receive clock.
CARRIER SENSE: Asserted on the first valid high-to-low transition on
g
the RX pair. Remains active until 1.5 bit times after the last bit in
data.
4
5
4
5
RXC
SEL
O
I
RECEIVE CLOCK: The receive clock from the Manchester data after
the PLL has locked. Remains active 5 bit times after deasserting CRS.
a
b
MODE SELECT: When high, transmit and transmit are the same
voltage in the idle state. When low, transmit is positive with respect
a
b
to transmit in the idle state, at the transformer’s primary.
6
7
8
9
V
SS
V
SS
V
SS
GROUND PIN
7
8
9
10
11
12
LBK
X1
I
I
LOOPBACK: When high, the loopback mode is enabled.
CRYSTAL OR EXTERNAL OSCILLATOR INPUT
X2
O
CRYSTAL FEEDBACK OUTPUT: Used in crystal connections only.
Connected to ground when using an external oscillator.
10
13
TXD
I
TRANSMIT DATA INPUT: NRZ data input from the controller. The
data is combined with the transmit clock to produce Manchester data.
TXD is sampled on the rising edge of transmit clock.
11
12
14
15
TXC
TXE
O
I
TRANSMIT CLOCK: The 10 MHz clock derived from the 20 MHz
oscillator.
TRANSMIT ENABLE: The encoder begins operation when this input is
asserted high.
b
a
13
14
16
17
TX
TX
O
TRANSMIT OUTPUT: Differential line driver which sends the encoded
data to the transceiver. The outputs are source followers which require
270X pull-down resistors.
15
6
NC
NO CONNECTION: This may be tied to V for the PLCC version to be
SS
compatible with the DP8391.
16
17
18
19
NC
NO CONNECTION
TEST
I
FACTORY TEST INPUT: Used to check the chip’s internal functions.
May be tied low or have a 0.01 mf bypass capacitor to ground (for
compatibility with the bipolar DP8391) during normal operation.
18
19
20
21
22
23
V
DD
V
DD
V
DD
V
DD
POWER CONNECTION
20
24
NC
NO CONNECTION
b
21
22
25
26
RX
I
I
RECEIVE INPUT: Differential receive input pair from the transceiver.
a
RX
b
a
23
24
27
28
CD
CD
COLLISION INPUT: Differential collision pair input from the
transceiver.
5
7.0 Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Lead Temperature (Soldering, 10 sec.)
260 C
§
2 kV
t
e
e
120 pF)
ESD (R
1.5 kX, C
ZAP
ZAP
e
(Pin 4
1.5 kV)
b
a
0.5V to 7V
Supply Voltage (V
)
CC
Note: Absolute maximum ratings are those values beyond
which the safety of the device cannot be guaranteed. They
are not meant to imply that the device should be operated at
these limits.
b
b
a
a
DC Input Voltage (V
)
0.5V to V
0.5V to V
0.5V
0.5V
IN
CC
CC
DC Output Voltage (V
)
OUT
b
a
Differential Input Voltage
5.5 to 16V
0 to 16V
*Note: An asterisk following a parameter’s symbol indicates that the param-
eter has been characterized but not tested.
Differential Output Voltage
Power Dissipation
500 mW
Note: All specifications in this datasheet are valid only if the mandatory
isolation is employed and all differential signals are taken to exist at the AUI
side of the pulse transformer.
b
a
65 C to 150 C
§
Storage Temperature
§
e
e
5V 5%
g
8.0 DC Specifications T
0 C to 70 C, V
§
§
A
CC
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Controller Interface Pins (COL, RXD, CRS, RXC, SEL, LBK, TXD, TXC and TXE)
V
V
Input High Voltage
Input Low Voltage
Input Leakage
2.0
V
V
IH
0.8
1.0
IL
e
b
I
V
IN
V or GND
CC
1.0
mA
IN
e
OH
V
OH
Output High Voltage
(TTL) I
2.0 mA
e
3.5
V
V
b
0.1
(CMOS) I
20 mA
V
OH
CC
e
V
OL
Output Low Voltage
(TTL) I
OL
2.0 mA
e
0.4
0.1
V
V
(CMOS) I
20 mA
OL
I
I
Operating V Supply
CC
CCO
CCS
10 Mbit/sec
10 Mbit/sec
70
65
mA
mA
Current (Note 1)
Stand By V Supply
CC
Current (Note 2)
g
g
Differential Pins (TX , RX , and CD
g
)
g
V
Diff. Output Voltage (TX
)
78X Termination, and
OD
g
b
g
1200
550
mV
mV
mV
mV
270X from each to GND(Figure 4)
V
OB
*
Diff. Output Voltage
78X Termination, and
40
g
Imbalance (TX
)
270X from each to GND(Figure 4)
g
V *
U
Undershoot Voltage (TX
)
78X Termination, and
100
270X from each to GND(Figure 4)
V
DS
Diff. Squelch Threshold
b
175
0
300
g
(RX and CD
g
)
V
CM
Diff. Input Common Mode
g
Voltage (RX and CD
g
)
5.5
V
(Note 3)
Oscillator Pins (X1 and X2)
V
X1 Input High Voltage
X1 Input Low Voltage
X1 Input Current
X1 is connected to an oscillator,
and X2 is grounded
IH
2.0
V
V
V
IL
X1 is connected to an oscillator,
and X2 is grounded
0.8
e
e
I
X1
X2
V or GND
CC
GND
OSC
b
a
2
2
mA
Note 1: This measurement was made while the DP83910A was undergoing transmission, reception, and collision detection. Also, this value was not measured
e
e
instantaneously, but averaged over a span of several milliseconds. (V
2.4V or 0.4V and I
0 mA).
IN
o
Note 2: This measurement was made while the DP83910A was sitting idle with TXE low. Also, this value was not measured instantaneously, but averaged over a
e
e
span of several milliseconds. (V
2.4V or 0.4V and I
0 mA).
IN
o
Note 3: This parameter is guaranteed by design and is not tested.
6
e
e
5V 5%
g
9.0 Switching Characteristics T
0 C to 70 C, V
§
§
A
CC
Oscillator Specification
Symbol
Parameter
Min
5
Max
30
Units
ns
t
t
X1 to Transmit Clock High
X1 to Transmit Clock Low
XTH
5
30
ns
XTL
Transmit Timing (Start of Packet)
TL/F/9365–4
Transmit Specifications (Start of Packet)
Symbol
Parameter
Transmit Clock High Time (Note 1)
Transmit Clock Low Time (Note 1)
Min
40
Max
60
Units
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
TCh
40
60
TCl
*
TCc
Transmit Clock Cycle Time (Note 1)
Transmit Clock Rise Time (20% to 80%) (C
Transmit Clock Fall Time (80% to 20%) (C
99.99
100.01
8
e
L
*
TCr
30 pF)
e
L
*
TCf
30 pF)
8
Transmit Enable Setup Time to Rising Edge of TXC (Note 1)
Transmit Data Setup Time from Rising Edge of TXC (Note 1)
20
20
TEs
TDs
TDh
Transmit Data Hold Time
from Rising Edge of TXC
0
ns
t
t
t
t
Transmit Output Delay from Rising Edge of TXC (Note 1)
Transmit Output Fall Time (80% to 20%)
Transmit Output Rise Time (20% to 80%)
Transmit Output Jitter
65
7
ns
ns
ns
ns
TOd
*
TOf
TOr
*
7
*
TOj
0.5 Typical
Note 1: This parameter is measured using the fifty percent point of each clock edge.
7
9.0 Switching Characteristics (Continued)
Transmit Timing (End of Packet)
TL/F/9365–5
Transmit Specifications (End of Packet)
Symbol
Parameter
Min
0
Max
Units
ns
t
t
t
Transmit Enable Hold Time from Rising Edge of TXC
Transmit Output High before Idle (Half Step)
Transmit Output Idle Time (Half Step)
TXEh
200
ns
TOh
*
TOi
8000
ns
Receive Timing (Start of Packet)
TL/F/9365–6
Receiver Specifications (Start of Packet)
Symbol
Parameter
Min
Max
60
Units
%
t
t
t
t
t
t
t
t
t
Receive Clock Duty Cycle (Note 1)
Receive Clock Rise Time (20% to 80%, C
Receive Clock Fall Time (80% to 20%, C
40
RCd
e
TL
*
RCr
30 pF)
7
ns
e
TL
*
RCf
30 pF)
7
ns
Carrier Sense Turn On Delay
Decoder Acquisition Time
Receive Data Output Delay
70
ns
CRSon
DAT
RDd
RDs
Dtor
700
150
ns
ns
Receive Data Output Stable after Going Valid
Differential Inputs Turn-On Pulse (Note 2)
90
30
ns
ns
Receive Data Output Valid from Falling Edge of RXC
10
ns
RDV
Note 1: This parameter is measured using the fifty percent point of each clock edge.
b
Note 2: This parameter was characterized with a differential input of 375 mV on the receive pair inputs.
8
9.0 Switching Characteristics (Continued)
Receive Timing (End of Packet)
TL/F/9365–7
Receiver Specifications (End of Packet)
Symbol
Parameter
Min
Max
Units
ns
t
t
Carrier Sense Turn Off Delay (Note 1)
Minimum Number of RXCs after CRS Low (Note 2)
155
CRSoff
5
Bit Times
RXCh
Note 1: When CRS goes low, it will go low a minimum of 2 receive clocks.
Note 2: The DP8390 Network Interface Controller (NIC) requires a minimum of 5 receive clocks after CRS goes low to function properly.
Collision Timing
TL/F/9365–8
Collision Specifications
Symbol
Parameter
Min
Max
60
Units
ns
t
t
t
Collision Turn On Delay
Collision Turn Off Delay
COLon
COLoff
Dtoc
350
ns
Differential Inputs Turn-On
Pulse (Squelch, Note 1)
30
ns
b
Note 1: This parameter was characterized with a differential input of 375 mV on the collision input pair.
9
9.0 Switching Characteristics (Continued)
Loopback Timing
TL/F/9365–9
Loopback Specifications
Symbol
Parameter
Min
50
Max
Units
ns
t
t
Loopback Setup Time (Note 1)
Loopback Hold Time (Note 1)
LBs
1000
ns
LBh
Note 1: This parameter is guaranteed by design and is not tested.
e
e
AC Timing Test Conditions
All specifications are valid only if the mandatory isolation is
employed and all differential signals are taken to be at the
AUI side of the pulse tranformer.
Capacitance T
25 C, f
§
1 MHz
Typ
A
Symbol
Parameter
Units
C
C
Input Capacitance
Output Capacitance
7
7
pF
pF
IN
Input Pulse Levels (TTL/CMOS)
GND to 3.0V
5 ns
OUT
Input Rise and Fall Times (TTL/CMOS)
Input and Output Reference Levels
(TTL/CMOS)
1.3V
Input Pulse Levels
(Diff.)
b
b
350 to 1315 mV
Input and Output
Reference Levels (Diff.)
50% Point of
the Differential
TL/F/9365–12
FIGURE 4
a
b
Note: In the above diagram, the TX and TX signals are taken from the
AUI side of the isolation (pulse transformer). The pulse transformer used for
all testing is the Pulse Engineering PE64103.
TL/F/9365–10
FIGURE 3
10
Physical Dimensions inches (millimeters)
Molded Dual-In-Line Package (N)
Order Number DP83910AN
NS Package Number N24C
11
Physical Dimensions inches (millimeters) (Continued)
Plastic Chip Carrier (V)
Order Number DP83910AV
NS Package Number V28A
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
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Audio
Applications
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
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Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
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Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
Medical
Security
Logic
Space, Avionics and Defense www.ti.com/space-avionics-defense
Transportation and Automotive www.ti.com/automotive
Power Mgmt
Microcontrollers
RFID
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page
e2e.ti.com
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