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DP83TC811R-Q1

ZHCSHX5A –NOVEMBER 2017–REVISED MARCH 2018

DP83TC811R-Q1 低功耗汽车 PHY

100BASE-T1 汽车以太网物理层收发器

2 应用

1 特性

1

•

符合 100BASE-T1 – IEEE 802.3bw 标准

•

主干网络

网关和车身控制

远程信息处理

–

符合 OPEN Alliance 标准

能够与 BroadR-Reach和 100BASE-T1 PHY 进

行互操作

3 说明

•

符合面向汽车应用的 AEC-Q100 标准：

DP83TC811R-Q1 器件是一款符合 IEEE 802.3bw 标

准的汽车 PHYTER™以太网物理层收发器。它提供通

过单一屏蔽双绞线电缆发送和接收数据所需的所有物理

层功能。该器件具有 xMII 灵活性，支持标准 MII、

RMII 和 RGMII MAC 接口。

–

器件温度等级 1：环境工作温度范围为 –40°C

至 +125°C

–

器件 HBM ESD 分类等级 3A

除引脚 5 之外，其他所有引脚的器件 CDM

ESD 分类等级均为 C5

–

引脚 5 的器件 CDM ESD 分类等级为 C3

该器件包含诊断工具套件，从而提供广泛的实时监控工

具、调试工具和测试模式。该工具套件中包含首款集成

式静电放电 (ESD) 监控工具。它能够对 xMII 和 MDI

上的 ESD 事件进行计数，并且能够通过使用可编程中

断提供实时监控。此外，DP83TC811R-Q1 还包含一

个假随机二进制序列 (PRBS) 帧生成工具，该工具与内

部回送完全兼容，能够在不使用 MAC 的情况下发送和

接收数据。DP83TC811R-Q1 采用 6.00mm ×

引脚 12 和 13 的器件 IEC61000-4-2 ESD 分类

等级为 4：±8kV 接触放电

•

MAC 接口：MII、RMII 和 RGMII

VQFN，可湿侧面封装

支持 IEEE 1588 SFD

符合 AVB/TSN 标准的低发送和接收延迟

低有功功率运行：< 230mW

可配置的 I/O 电压：3.3V、2.5V 和 1.8V

节能特性：

6.00mm、36 引脚 VQFN 可湿侧面封装。

器件信息⁽¹⁾

–

睡眠、待机和禁用

局域网唤醒 (WoL)

器件型号

封装

VQFN (36)

封装尺寸（标称值）

DP83TC811R-Q1

6.00mm x 6.00mm

•

诊断工具套件

–

信号质量指标 (SQI)

时域反射法 (TDR)

静电放电传感器

电压传感器

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

空白

温度传感器

PRBS 内置自检

简化原理图

100BASE-T1

IEEE 802.3bw

MII

RMII

CMC

Automotive

Connector

RGMII

DP83TC811R-Q1

100 Mbps

Automotive Ethernet PHY

CPU/MPU

MAC

CM

Termination

25-MHz

Clock Source

Status

LEDs

GND

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNLS551

DP83TC811R-Q1

ZHCSHX5A –NOVEMBER 2017–REVISED MARCH 2018

www.ti.com.cn

8.3 Feature Description................................................. 23

8.4 Device Functional Modes........................................ 30

8.5 Programming........................................................... 42

8.6 Register Maps......................................................... 46

Application and Implementation ...................... 111

9.1 Application Information.......................................... 111

9.2 Typical Applications .............................................. 111

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

6.1 Pin Multiplexing......................................................... 8

Specifications......................................................... 9

7.1 Absolute Maximum Ratings ...................................... 9

7.2 ESD Ratings.............................................................. 9

7.3 Recommended Operating Conditions....................... 9

7.4 Thermal Information.................................................. 9

7.5 Electrical Characteristics......................................... 10

7.6 Timing Requirements.............................................. 11

7.7 Timing Diagrams..................................................... 14

7.8 Typical Characteristics............................................ 20

Detailed Description ............................................ 21

8.1 Overview ................................................................. 21

8.2 Functional Block Diagram ....................................... 22

9

10 Power Supply Recommendations ................... 117

11 Layout................................................................. 117

11.1 Layout Guidelines ............................................... 117

11.2 Layout Example .................................................. 120

12 器件和文档支持 ................................................... 122

12.1 接收文档更新通知 ............................................... 122

12.2 社区资源.............................................................. 122

12.3 商标..................................................................... 122

12.4 静电放电警告....................................................... 122

12.5 Glossary.............................................................. 122

13 机械、封装和可订购信息..................................... 122

7

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (November 2017) to Revision A

Page

•

将器件状态从“预告信息”更改成了“生产数据” ......................................................................................................................... 1

2

DP83TC811R-Q1

www.ti.com.cn

ZHCSHX5A –NOVEMBER 2017–REVISED MARCH 2018

5 Device Comparison Table

PART

SGMII

OPERATING

NUMBER

SUPPORT

TEMPERATURE

DP83TC811R-Q1

DP83TC811S-Q1

No

–40°C to 125°C

Yes

6 Pin Configuration and Functions

RND Package

36-Pin VQFN

Top View

27

26

25

24

23

22

21

20

19

TX_CLK

TX_EN / TX_CTRL

TX_D3

28

29

30

31

32

33

34

35

36

18

17

16

15

14

13

12

11

10

TDO

TCK

CLKOUT / GPIO_2

RX_DV / CRS_DV

RX_CTRL

TX_D2

TX_D1

GND

RX_ER

TRD_M

TRD_P

VDDA

INH

TX_D0

TX_ER

LED_0 / GPIO_0

MDIO

1

2

3

4

5

6

7

8

9

3

DP83TC811R-Q1

ZHCSHX5A –NOVEMBER 2017–REVISED MARCH 2018

www.ti.com.cn

Pin Functions⁽¹⁾

STATE⁽²⁾

DESCRIPTION

NAME

NO.

MAC INTERFACE

23

RX_D3

RX_D2

RX_D1

RX_D0

Receive Data: Symbols received on the cable are decoded and transmitted out of these pins

synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted. A data

nibble, RX_D[3:0], is transmitted in MII and RGMII modes. 2 bits; RX_D[1:0], are transmitted in RMII

mode. RX_D[3:2] are not used when in RMII mode.

24

25

26

S, PD, O

If the PHY is bootstrapped to RMII Master mode, a 50-MHz clock reference is automatically outputted

on RX_D3. This clock should be fed to the MAC.

Receive Clock: In MII and RGMII modes, the receive clock provides a 25-MHz reference clock.

RX_CLK

27

O

Unused in RMII mode

Receive Error: In MII and RMII modes, this pin indicates a receive error symbol has been detected

within a received packet. In MII mode, RX_ER is asserted high synchronously to the rising edge of

RX_CLK. In RMII mode, RX_ER is asserted high synchronously to the rising edge of the reference

clock. This pin is not required to be used by the MAC in MII or RMII because the PHY will

automatically corrupt data on a receive error.

RX_ER

14

S, PD, O

Unused in RGMII mode

Receive Data Valid: This pin indicates when valid data is presented on RX_D[3:0] for MII mode.

Carrier Sense Data Valid: This pin combines carrier sense and data valid into an asynchronous

signal. When CRS_DV is asserted, data is presented on RX_D[1:0] in RMII mode.

RX_DV

CRS_DV

RX_CTRL

15

28

S, PD, O

RGMII Receive Control: Receive control combines receive data valid indication and receive error

indication into a single signal. RX_DV is presented on the rising edge of RX_CLK and RX_ER is

presented on the falling edge of RX_CLK.

Transmit Clock: In MII mode, the transmit clock is a 25-MHz output and has constant phase

referenced to the reference clock. In RGMII mode, this clock is sourced from the MAC layer to the

PHY. A 25-MHz clock should be provided (not required to have constant phase to the reference clock

unless synchronous RGMII is enabled in ).

TX_CLK

PD, I, O

Unused in RMII mode

Transmit Enable: In MII mode, transmit enable is presented prior to the rising edge of the transmit

clock. TX_EN indicates the presence of valid data inputs on TX_D[3:0]. In RMII mode, transmit

enable is presented prior to the rising edge of the reference clock. TX_EN indicates the presence of

valid data inputs on TX_D[1:0].

TX_EN

TX_CTRL

29

PD, I

RGMII Transmit Control: Transmit control combines transmit enable and transmit error indication

into a single signal. TX_EN is presented prior to the rising edge of TX_CLK; TX_ER is presented

prior to the falling edge of TX_CLK.

TX_D3

TX_D2

30

31

Transmit Data: In MII and RGMII modes, the transmit data nibble, TX_D[3:0], is received from the

MAC prior to the rising edge of TX_CLK. In RMII mode, TX_D[1:0] is received from the MAC prior to

the rising edge of the reference clock. TX_D[3:2] are not used in RMII mode.

PD, I

32

33

TX_D1

TX_D0

Transmit Error: In MII mode, this pin indicates a transmit error symbol has been detected within a

transmitted packet. TX_ER is received prior to the rising edge of TX_CLK.

TX_ER

34

Unused in RMII and RGMII modes

(1) When pins are unused, follow the recommended connection requirements provided in the table above. If pins do not have required

termination, they may be left floating.

(2) Pin Type:

I = Input

O = Output

IO = Input/Output

OD = Open Drain

PD = Internal pulldown

PU = Internal pullup

S = Bootstrap configuration pin (all configuration pins have weak internal pullups or pulldowns)

4

DP83TC811R-Q1

www.ti.com.cn

ZHCSHX5A –NOVEMBER 2017–REVISED MARCH 2018

Pin Functions⁽¹⁾(continued)

STATE⁽²⁾

DESCRIPTION

NAME

NO.

SERIAL MANAGEMENT INTERFACE

Management Data Clock: Synchronous clock to the MDIO serial management input and output

data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock

rate is 25 MHz. There is no minimum clock rate.

MDC

1

I

Management Data Input/Output: Bidirectional management data signal that may be sourced by the

management station or the PHY. This pin requires a pullup resistor.

MDIO

36

IO

Recommended to use a resistor between 2.2 kΩ and 9 kΩ.

CONTROL INTERFACE

Interrupt: Active-LOW output, which will be asserted LOW when an interrupt condition occurs. This

pin has a weak internal pullup. Register access is necessary to enable various interrupt triggers.

Once an interrupt event flag is set, register access is required to clear the interrupt event.

INT

2

PU, OD, O

Note: Power-on-RESET (POR) Done interrupt is enabled by default. POR Done interrupt can be

cleared by reading register INT_STAT3 Register 0x0018 – Interrupt Status Register #3.

This pin can be configured as an Active-HIGH output using register INT_TEST Register 0x0011 –

Interrupt Test Register.

Reset: Active-LOW input, which initializes or reinitializes the DP83TC811R-Q1. Asserting this pin

LOW for at least 1 μs will force a reset process to occur. All internal registers will reinitialize to their

default states as specified for each bit in the Register Maps section. All bootstrap pins are resampled

upon deassertion of reset.

RESET

EN

3

7

PU, I

PD, I

Enable: Active-HIGH input, which will disable the DP83TC811R-Q1 when pulled LOW and power

down all internal blocks. Disable state is equivalent to a power-down state.

This pin can be directly tied to VDDIO; enabling the device.

WAKE: Active-HIGH input, which wakes the PHY from SLEEP. Asserting this pin HIGH at power-up

will prevent the PHY from going to SLEEP.

WAKE

INH

8

PD, I

O

This pin can be directly tied to VDDIO to wake the device.

INH: Active-HIGH output, which will be asserted HIGH when the PHY is in SLEEP or DISABLED.

This pin is LOW for all other PHY states.

10

CLOCK INTERFACE

Reference Clock Input (MII and RGMII): Reference clock 25-MHz ±100 ppm-tolerance crystal or

oscillator input. The device supports either an external crystal resonator connected across pins XI

and XO, or an external CMOS-level oscillator connected to pin XI only and XO left floating.

Reference Clock Input (RMII): Reference clock 50-MHz ±100 ppm-tolerance CMOS-level oscillator

in RMII Slave mode. Reference clock 25-MHz ±100 ppm-tolerance crystal or oscillator in RMII Master

mode.

XI

5

4

I

This is a fail-safe pin. When the PHY is not powered, an external oscillator is allowed to be powered

and driving into this pin. Fail-safe prevents pin back-driving.

Reference Clock Output: XO pin is used for crystal only. This pin should be left floating when a

CMOS-level oscillator is connected to XI.

XO

O

LED/GPIO INTERFACE

LED_0 /

35

S, PD, IO

IO

LED_0: Link Status

GPIO_0

LED_1 /

6

LED_1: Link Status and BLINK for TX/RX Activity

Clock Output: 25-MHz reference clock

GPIO_1

CLKOUT /

16

GPIO_2

MEDIUM DEPENDENT INTERFACE

TRD_M

TRD_P

13

12

Differential Transmit and Receive: Bidirectional differential signaling configured for 100BASE-T1

operation, IEEE 802.3bw compliant.

IO

JTAG (IEEE 1149.1)

Test Clock: Primary clock source for all test logic input and output. This pin is controlled by the

testing entity.

TCK

17

PU, I

This pin can be left unconnected if not used.

5

DP83TC811R-Q1

ZHCSHX5A –NOVEMBER 2017–REVISED MARCH 2018

www.ti.com.cn

Pin Functions⁽¹⁾(continued)

STATE⁽²⁾

DESCRIPTION

NAME

NO.

Test Data Output: Test results are scanned out.

TDO

18

O

This pin can be left unconnected if not used.

Test Mode Select: Sequences the Tap Controller (16-state FSM) to select the desired test

instruction. TI recommends applying three clock cycles with TMS HIGH to reset JTAG.

TMS

TDI

19

20

PU, I

This pin can be left unconnected if not used.

Test Data Input: Test data is scanned into the device.

This pin can be left unconnected if not used.

POWER CONNECTIONS

Core Supply: 3.3 V

VDDA

11

SUPPLY

Recommend using 10-nF, 100-nF, 1-µF, and 10-µF ceramic decoupling capacitors; optional ferrite

bead.

IO Supply: 1.8 V, 2.5 V, or 3.3 V

VDDIO

22

SUPPLY

Recommend using 10-nF, 100-nF, 1-µF, and 10-µF ceramic decoupling capacitors; optional ferrite

bead.

GROUND

DAP

GROUND

Ground

DO NOT CONNECT

DNC

9

DNC: Do not connect (leave floating)

21

6

DP83TC811R-Q1

www.ti.com.cn

ZHCSHX5A –NOVEMBER 2017–REVISED MARCH 2018

Table 1. Pin States⁽¹⁾

POWER-UP / RESET

NORMAL OPERATION: MII / RMII / RGMII

PULL VALUE

NAME

PULL VALUE

PIN STATE

PULL TYPE

PIN STATE

PULL TYPE

(kΩ)

none

9

MDC

INT

I

none

PU

none

9

I

none

PU

I

OD, O

RESET

XO

I

PU

9

I

PU

9

O

none

PD

none

9

O

none

PD

none

500

XI

I

LED_1

EN

HI-Z

O

I

PD

500

none

9

I

WAKE

DNC

I

PD

I

PD

500

FLOAT

none

PD

FLOAT

none

PU

none

9

INH

O

VDDA

TRD_P

TRD_M

RX_ER

RX_DV

CLKOUT

TCK

SUPPLY

IO

HI-Z

O

PD

9

O

none

PU

none

9

O

I

TDO

O

none

PU

none

9

O

none

PU

none

9

TMS

I

TDI

I

PU

9

I

PU

9

DNC

FLOAT

SUPPLY

HI-Z

O

none

PD

none

9

FLOAT

none

VDDIO

RX_D3

RX_D2

RX_D1

RX_D0

RX_CLK

SUPPLY

O

PD

9

PD

9

PD

9

none

O

none

PD⁽²⁾

none

9⁽²⁾

TX_CLK

I

PD

9

I⁽²⁾

TX_EN

TX_D3

TX_D2

TX_D1

TX_D0

TX_ER

LED_0

MDIO

I

PD

9

I

PD

9

I

9

I

PD

9

I

PD

I

PD

9

I

PD

9

I

PD

I

PD

9

I

HI-Z

I

PD

9

I

PD

9

PD

9

O

I

none

(1) Type: I = Input

O = Output

IO = Input/Output

OD = Open Drain

PD = Internal pulldown

PU = Internal pullup

(2) Pin operation only for RGMII operation.

7

DP83TC811R-Q1

ZHCSHX5A –NOVEMBER 2017–REVISED MARCH 2018

www.ti.com.cn

6.1 Pin Multiplexing

GPIOs are controlled using IO_CTRL1 Register 0x0462 – GPIO Control Register #1 and IO_CTRL2 Register

0x0463 – GPIO Control Register #2.

LED:

Pin configured as LED indication. LED_CFG1 Register 0x0460 – LED Configuration Register #1

determines LED function.

CLKOUT: Pin configured as a clock output signal

WoL:

Pin configured to output WoL interrupt

UV:

Pin configured to output undervoltage interrupt

Pin configured to output transmit 1588 SFD indication

1588_TX:

1588_RX: Pin configured to output receive 1588 SFD indication

0s:

1s:

Pin configured LOW (ground)

Pin configured HIGH (VDDIO)

RMII_REF: Pin configured to output RMII 50-MHz reference clock

Table 2. Pin Multiplexing

FIELD

0b000

0b001

0b010

0b011

0b100

0b101

0b110

0b111

STRAP

LED_0 /

GPIO_0

35

LED_0

CLKOUT_0

LED_1 /

GPIO_1

6

LED_1

CLKOUT_1

CLKOUT_2

WoL

UV

Reserved

0s

1s

CLKOUT /

GPIO_2

16

23

LED_2

RX_D3

RMII_REF

8

DP83TC811R-Q1

www.ti.com.cn

ZHCSHX5A –NOVEMBER 2017–REVISED MARCH 2018

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

4.0

UNIT

VDDA

Input voltage

VDDIO

4.0

V

Other pins

4.0

DC output

voltage

All Pins

–0.3

4.0

V

T_J

Junction temperature

Storage temperature

150

°C

T_stg

–65

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT

Human body model (HBM), per

All pins

±4000

AEC Q100-002⁽¹⁾

All pins except XI pin

XI pin⁽²⁾

±750

±250

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per

AEC Q100-011

V

IEC 61000-4-2 contact discharge

TRD_N, TRD_P pins

±8000

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) XI pin is a fail-safe input.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.62

2.25

2.97

–40

NOM

1.8

MAX

1.98

2.75

3.63

125

UNIT

IO Supply Voltage, 1.8V operation

IO Supply Voltage, 2.5V operation

IO Supply Voltage, 3.3V operation

Core Supply Voltage

V_DDIO

2.5

V

3.3

V_DDA

T_A

3.3

V

Operating Free Air Temperature

°C

7.4 Thermal Information

DP83TC811R-Q1

THERMAL METRIC⁽¹⁾

VQFN

36 PINS

31.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

19.3

12.5

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

Y_JB

12.5

R_θJC(bot)

1.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

9

DP83TC811R-Q1

ZHCSHX5A –NOVEMBER 2017–REVISED MARCH 2018

www.ti.com.cn

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

XI pin, WAKE pin and EN pin

V_IH

V_IL

High Level Input Voltage

1.3

V

0.5

3.3V VDDIO⁽¹⁾

V_OH

V_OL

V_IH

V_IL

High Level Output Voltage

IOH = -2mA VDDIO = 3.3 V +/- 10%

IOL = 2mA VDDIO = 3.3 V +/- 10%

VDDIO = 3.3 V +/- 10%

2.4

2

V

Low Level Output Voltage

High Level Input Voltage

Low Level Input Voltage

0.4

0.8

VDDIO = 3.3 V +/- 10%

2.5V VDDIO⁽¹⁾

V_OH

V_OL

V_IH

V_IL

High Level Output Voltage

IOH = -2mA VDDIO = 2.5 V +/- 10%

IOL = 2mA VDDIO = 2.5 V +/- 10%

VDDIO = 2.5 V +/- 10%

2

V

Low Level Output Voltage

High Level Input Voltage

Low Level Input Voltage

0.4

0.7

1.7

VDDIO = 2.5 V +/- 10%

1.8V VDDIO⁽¹⁾

VDDIO

–0.45

V_OH

V_OL

V_IH

High Level Output Voltage

IOH = -2mA VDDIO = 1.8 V +/- 10%

IOL = 2mA VDDIO = 1.8 V +/- 10%

VDDIO = 1.8 V +/- 10%

V

Low Level Output Voltage

High Level Input Voltage

0.45

0.65 *

VDDIO

0.35 *

VDDIO

V_IL

Low Level Input Voltage

VDDIO = 1.8 V +/- 10%

V

DC CHARACTERISTICS

I_IH

I_IL

Input High Current

VIN = VDDIO

-30

-75

30

75

µA

pF

kΩ

Input Low Current

TRI-STATE Output Current⁽²⁾

VIN = GND

I_OZ

VOUT = VDDIO, VOUT = GND

Input pins

5

1

5

1

9

C_IN

Input Capacitance

XI

Output pins

C_OUT

Output Capacitance

XO

R_pull-up

Integrated Pull-Up Resistance

RESET, INT, TCK, TMS and TDI

6.5

12.5

RX_D[3:0], RX_ER, RX_DV, TX_EN,

TX_D[3:0], TX_ER, LED_0 and LED_1

6.75

9

500

50

11.25

kΩ

Ω

R_pull-downIntegrated Pull-Down Resistance

WAKE and EN

Integrated MAC Series Termination

RX_D[3:0], RX_ER, RX_DV and

RX_CLK

R_series

Resistor

CURRENT CONSUMPTION

MII

18

6

22

12

13

17

10

I_DDIO-1V8-IO Supply Current, 1.8V operation,

RMII

RGMII

MII

mA

Active/Normal Mode

ACT

10

13

3

I_DDIO-1V8-IO Supply Current, 1.8V operation,

RMII

RGMII

Standby

STBY

8

I_DDIO-1V8-

RST

IO Supply Current, 1.8V operation, Reset All Interfaces

IO Supply Current, 1.8V operation, Sleep All Interfaces

6

8

10

90

mA

µA

I_DDIO-1V8-

SLP

(1) For pins: MDC, INT_N, RESET_N, XO, LED_1, RX_ER, RX_DV, CLKOUT, TCK, TDO, TMS, TDI, RX_D[3:0], RX_CLK, TX_CLK,

TX_EN, TX_D[3:0], TX_ER, LED_0, and MDIO

(2) For pins: RX_D[3:0], RX_CLK, RX_ER, RX_DV, TX_CLK, MDIO, INT_N, XO, and TDO

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_DDIO-1V8-IO Supply Current, 1.8V operation,

All Interfaces

8

85

µA

Disable

DIS

MII

24

14

12

18

11

10

28

24

17

22

21

13

I_DDIO-2V5-IO Supply Current, 2.5V operation,

RMII

RGMII

MII

mA

Active/Normal Mode

ACT

I_DDIO-2V5-IO Supply Current, 2.5V operation,

RMII

RGMII

Standby

STBY

I_DDIO-2V5-

RST

IO Supply Current, 2.5V operation, Reset All Interfaces

IO Supply Current, 2.5V operation, Sleep All Interfaces

8

11

18

95

93

mA

µA

I_DDIO-2V5-

SLP

I_DDIO-2V5-IO Supply Current, 2.5V operation,

DIS

All Interfaces

Disable

MII

31

22

16

24

19

13

37

36

21

29

33

17

I_DDIO-3V3-IO Supply Current, 3.3V operation,

RMII

RGMII

MII

mA

Active/Normal Mode

ACT

I_DDIO-3V3-IO Supply Current, 3.3V operation,

RMII

RGMII

Standby

STBY

I_DDIO-3V3-

RST

IO Supply Current, 3.3V operation, Reset All Interfaces

IO Supply Current, 3.3V operation, Sleep All Interfaces

15

14

30

100

mA

µA

I_DDIO-3V3-

SLP

I_DDIO-3V3-IO Supply Current, 3.3V operation,

DIS

All Interfaces

Disable

I_DDA-ACT

Active/Normal Mode

Standby

65

20

13

51

110

55

mA

µA

Core Supply Current; MII, RMII, RGMII

I_DDA-STBY

I_DDA-RST

Reset

44

I_DDA-SLPCore Supply Current; All Interfaces

I_DDA-DIS

Sleep

186

185

Disable

µA

MDI CHARACTERISTICS

V_OD-MDI

R_{mdi_diff}

Output Differential Voltage

2.2

V

Integrated Differential MDI Termination

TRD_P and TRD_M

100

0

Ω

BOOTSTRAP DC CHARACTERISTICS

0.08 x

VDDIO

V_{bs_1}

Mode 1

Mode 2

Mode 3

Mode 4

0

V

0.148 x

VDDIO

0.165 x

VDDIO

0.181 x

VDDIO

V_{bs_2}

Bootstrap Threshold

V_{bs_3}

0.235 x

VDDIO

0.252 x

VDDIO

0.277 x

VDDIO

0.694 x

VDDIO

V_{bs_4}

VDDIO

7.6 Timing Requirements

MIN

NOM

MAX

UNIT

MII TIMING

T1.1

T1.2

TX_CLK High / Low Time

TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK

16

10

20

24

ns

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Timing Requirements (continued)

MIN

0

NOM

MAX

UNIT

ns

T1.3

T2.1

T2.2

TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK

RX_CLK High / Low Time

16

14

20

24

26

ns

RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising

ns

RMII SLAVE TIMING

T3.1

Reference Clock Period

20

50

ns

%

Reference Clock Duty Cycle

35

4

65

12

65

T3.2

T3.3

T3.4

TX_D[1:0], TX_ER, TX_EN Setup to XI Clock

TX_D[1:0], TX_ER, TX_EN Hold from XI Clock

RX_D[1:0], RX_ER Delay from XI Clock rising⁽¹⁾

ns

2

3

6

RMII MASTER TIMING⁽²⁾

T3.1

RMII Master Clock Period

20

50

ns

%

RMII Master Clock Duty Cycle

35

4

T3.2

T3.3

T3.4

TX_D[1:0], TX_ER, TX_EN Setup to RMII Master Clock

TX_D[1:0], TX_ER, TX_EN Hold from RMII Master Clock

RX_D[1:0], RX_ER Delay from RMII Master Clock rising⁽¹⁾

ns

2

4

6

12

RGMII TIMING

T_{skew (Align)}RX_D[3:0], RX_CTRL Delay from RX_CLK (Align Mode Enabled)

T_{skew (Shift)}RX_D[3:0], RX_CTRL Delay from RX_CLK (Shift Mode Enabled)

T_{setup (Align)}TX_D[3:0], TX_CTRL Setup to TX_CLK (Align Mode Enabled)

T_{setup (Shift)}TX_D[3:0], TX_CTRL Setup to TX_CLK (Shift Mode Enabled)

T_{hold (Align)}TX_D[3:0], TX_CTRL Hold from TX_CLK (Align Mode Enabled)

T_{hold (Shift)}TX_D[3:0], TX_CTRL Hold from TX_CLK (Shift Mode Enabled)

–600

1.2

1

0

2

600

ps

ns

%

–1

1

3

T_cyc

Clock Cycle Duration

Duty Cycle

36

40

50

44

60

Tr/Tf

Rise / Fall Time (20% - 80%)⁽³⁾

750

1200

ps

SMI TIMING

T4.1

MDC to MDIO (Output) Delay Time

MDIO (Input) to MDC Setup Time

MDIO (Input) to MDC Hold Time

MDC Frequency

0

10

6

12.5

25

ns

T4.2

T4.3

ns

2.5

MHz

POWER-UP TIMING

T5.1

T5.2

T5.3

T5.4

T5.5

T5.6

VDDA ramp rate

0.165

–50

33

50

V/ms

ms

VDDIO ramp rate

VDDA and VDDIO ramp delay offset

Crystal stabilization time post power-up

350

µs

Osillator stabilization time post power-up

Post power-up stabilization-time prior to MDC preamble for register access

Hardware configuration latch-in time from power-up

40

60

ms

Hardware configuration pins transition to functional mode from latch-in

completion

T5.7

T5.8

200

60

ns

PAM3 IDLE Stream from power-up (Master Mode)

ms

RESET TIMING (RESET_N)

T6.1

T6.2

RESET pulse width

1

µs

Post reset stabilization-time prior to MDC preamble for register access

2.5

(1) CRS_DV is an asynchronous signal as defined by the RMII version 1.2 specification.

(2) RMII Master Clock is in reference to the 50-MHz clock output on RX_D3 when the device is configured for RMII Master mode through

hardware bootstrap.

(3) RGMII rise/fall time control register configurable

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Timing Requirements (continued)

MIN

NOM

MAX

UNIT

T6.3

T6.4

T6.5

Hardware configuration latch-in time from reset

700

ns

Hardware configuration pins transition to functional mode from latch-in

completion

200

300

ns

µs

PAM3 IDLE Stream from reset (Master Mode)

TRANSMIT LATENCY TIMING

MII Rising edge TX_CLK with assertion TX_EN to SSD symbol on MDI

140

304

172

372

ns

Slave RMII Rising edge XI clock with assertion TX_EN to SSD symbol on

MDI

Master RMII Rising edge clock with assertion TX_EN to SSD symbol on

MDI

T7.1

322

382

ns

RGMII Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on

MDI

134

401

ns

Bit sequence 0b1101101000 to SSD symbol on MDI

440

RECEIVE LATENCY TIMING

SSD symbol on MDI to MII Rising edge of RX_CLK with assertion of

RX_DV

366

434

438

406

513

525

ns

SSD symbol on MDI to Slave RMII Rising edge of XI clock with assertion of

CRS_DV

T8.1

SSD symbol on MDI to Master RMII Rising edge of Master clock with

assertion of CRS_DV

SSD symbol on MDI to Rising edge of RGMII RX_CLK with assertion of

RX_CTRL

385

582

417

643

ns

SSD symbol on MDI to SFD (/S/) comprising bit sequence 0b1101101000

25 MHz OSCILLATOR REQUIREMENTS

Frequency

25

MHz

ppm

ns

Frequency Tolerance and Stability Over temperature and aging

–100

100

8

Rise / Fall Time (10% - 90%)

Jitter (Short-term, Cycle-to-Cycle)

Jitter (Long-term, Accumulative over 10 ms)

Duty Cycle

150

2

ps

ns

40

60

%

50 MHz OSCILLATOR REQUIREMENTS

Frequency

50

MHz

ppm

ns

Frequency Tolerance and Stability Over temperature and aging

Rise / Fall Time (10% - 90%)

Jitter (Short-term, Cycle-to-Cycle)

Jitter (Long-term, Accumulative over 10 ms)

Duty Cycle

–100

100

4

155

2.5

60

ps

ns

40

%

25 MHz CRYSTAL REQUIREMENTS

Frequency

25

MHz

ppm

Ω

Frequency Tolerance and Stability Over temperature and aging

Equivalent Series Resistance

–100

100

50

OUTPUT CLOCK TIMING (CLKOUT)

Frequency

MHz

%

Duty Cycle

45

55

1

Rise / Fall Time (20% - 80%)

Jitter (Short-term, Cycle-to-Cycle)

Jitter (Long-term, Accumulative over 10 ms)

ns

200

125

ps

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7.7 Timing Diagrams

tT1.1t

Clock

tT1.2t

tT1.3t

Data and

Control

Valid Data

图 1. MII Transmit Timing

tT2.1t

Clock

tT2.2t

Data and

Control

Valid Data

图 2. MII Receive Timing

tT3.1t

Clock

tT3.2t

tT3.3t

Transmit

Data and

Control

Valid Data

tT3.4t

Receive

Data and

Control

Valid Data

图 3. RMII Transmit and Receive Timing

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Timing Diagrams (接下页)

tT_cyc

t

TX_CLK

TX_D[3:0]

TX_CTRL

T_hold(shift)

Valid Data

T_setup(shift)

TX_ER

TX_EN

TX_ER

TX_EN

图 4. RGMII Transmit Timing (Internal Delay Enabled)

tT_cyc

t

TX_CLK

TX_D[3:0]

TX_CTRL

T_hold(align)

Valid Data

T_setup(align)

TX_EN

TX_ER

TX_EN

TX_ER

图 5. RGMII Transmit Timing (Internal Delay Disabled)

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Timing Diagrams (接下页)

tT_cyc

t

RX_CLK

T_skew(shift)

RX_D[3:0]

Valid Data

T_skew(shift)

RX_CTRL

RX_DV

RX_ER

RX_DV

RX_ER

RX_DV

图 6. RGMII Receive Timing (Internal Delay Enabled)

tT_cyc

t

RX_CLK

RX_D[3:0]

RX_CTRL

T_skew(align)

Valid Data

RX_DV

RX_ER

RX_DV

图 7. RGMII Receive Timing (Internal Delay Disabled)

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Timing Diagrams (接下页)

MDC

MDIO

tT4.2t

tT4.3t

Valid Data

tT4.1t

Valid Data

图 8. Serial Management Timing

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Timing Diagrams (接下页)

tT5.3t

XI_(crystal)

tT5.4t

XI_(oscillator)

T5.1

V_DDIO

T5.2

V_DDA

MDC

tT5.5t

tT5.6t

Bootstrap

Latch-in

Active

I/O Pins

tT5.7t

tT5.8t

+1

PAM3

0

(Master)

-1

图 9. Power-Up Timing

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Timing Diagrams (接下页)

V_VDD

XI

tT6.1t

Hardware

RESET_N

MDC

tT6.2t

tT6.3t

Bootstrap

Latch-in

Active

I/O Pins

tT6.4t

tT6.5t

+1

PAM3

0

(Master)

-1

图 10. Reset Timing

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7.8 Typical Characteristics

0.6

0.5

0.4

0.3

0.2

0.1

0

2.5

2

1.5

1

0.5

T_A= 25èC

T_A= -40èC

T_A= 125èC

T_A= 25èC

T_A= -40èC

T_A= 125èC

0

0.002 0.004 0.006 0.008

Load (A)

0.01

0.012 0.014

-0.014

-0.012

-0.01

-0.008

Load (A)

-0.006

-0.004

-0.002

D001

D003

VDDIO = 2.5 V +10%

VDDIO = 2.5 V –10%

图 11. LED_0, LED_1, and CLKOUT VOL (2.5 V)

图 12. LED_0, LED_1, and CLKOUT VOH (2.5 V)

0.6

0.5

0.4

0.3

0.2

0.1

0

3

2.5

2

1.5

1

T_A= 25èC

T_A= -40èC

T_A= 125èC

T_A= 25èC

T_A= -40èC

T_A= 125èC

0.5

0

0.002 0.004 0.006 0.008

Load (A)

0.01

0.012 0.014

-0.014

-0.012

-0.01

-0.008

Load (A)

-0.006

-0.004

-0.002

D002

D004

VDDIO = 3.3 V +10%

VDDIO = 3.3 V –10%

图 13. LED_0, LED_1, and CLKOUT VOL (3.3 V)

图 14. LED_0, LED_1, and CLKOUT VOH (3.3 V)

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8 Detailed Description

8.1 Overview

The DP83TC811R-Q1 is a 100BASE-T1 automotive Ethernet Physical Layer transceiver. It is IEEE 802.3bw

compliant and AEC-Q100 qualified for automotive applications. The DP83TC811R-Q1 is interoperable with both

BroadR-Reach PHYs and 100BASE-T1 PHYs.

This device is specifically designed to operate at 100-Mbps speed while meeting CISPR-25 Level 5 limits. The

DP83TC811R-Q1 transmits PAM3 ternary symbols at 66.667 MHz over unshielded single twisted-pair cable. It is

application flexible; supporting MII, RMII and RGMII in a single 36-pin VQFN wettable flank package.

There is an extensive Diagnostic Tool Kit within the DP83TC811R-Q1 for both in-system use as well as debug,

compliance and system prototyping for bring-up. Not only is the DP83TC811R-Q1 designed for IEC61000-4-2

Level 4 electrostatic discharge limits, but also includes an on-chip ESD sensor for detecting ESD events in real-

time.

The DP83TC811R-Q1 is built for minimal thermal footprint with low active power as well multiple low-power

modes. It supports Wake-on-LAN Magic Packets and Custom Pattern detection, allowing upstream devices an

option for entering into their own low-power state. Additionally, the device can enter into Sleep state and remain

until energy is detected on the MDI or locally woken through the WAKE pin.

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8.2 Functional Block Diagram

MII / RGMII Option

SGMII Option

RMII Option

Serial

Management

MII / RMII / RGMII / SGMII Interface

TX

RX

Data

TX_CLK

Data

RX_CLK

MII

Registers

100BASE-T1

PCS - TX

100BASE-T1

PCS - RX

PHY Control

100BASE-T1

PMA - TX

100BASE-T1

PMA - RX

Transmit Block

Receive Block

BIST

LED

Driver

Cable Diagnostics

Hybrid

TRD±

LEDs

图 15. DP83TC811R-Q1 Functional Block Diagram

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8.3 Feature Description

8.3.1 Wake-on-LAN (WoL) Packet Detection

Wake-on-LAN provides a mechanism to detect specific frames and notify the connected controller through either

register status change, GPIO indication or an interrupt flag. WoL within the DP83TC811R-Q1 allows for

connected devices residing above the Physical Layer to remain in a low-power state until frames with the

qualifying credentials are detected. Supported WoL frame types include: Magic Packet, Magic Packet with

Secure-ON, and Custom Pattern Match. When a qualifying WoL frame is received, the DP83TC811R-Q1 WoL

logic circuit is able to generate a user defined event (either pulses or level change) through any of the GPIO pins

or a status interrupt flag to inform a connected controller that a wake event has occurred. Additionally, the

DP83TC811R-Q1 includes a CRC Gate to prevent invalid packets from triggering a wake-up event.

The WoL feature set includes:

•

Wake-up interrupt generation upon receiving a valid Magic Packet or Pattern

CRC checking of Magic Packets to prevent interrupt generation for invalid packets

Magic Packets with Secure-ON password and 64-byte Custom Pattern Match

8.3.1.1 Magic Packet Structure

When configured for Magic Packet mode, the DP83TC811R-Q1 scans all incoming frames addressed to the

node for a specific sequence. This sequence identifies the frame as a Magic Packet frame.

A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as SOURCE

ADDRESS, DESTINATION ADDRESS (which may be the receiving station’s IEEE address or a BROADCAST

ADDRESS), and CRC. The specific Magic Packet sequence consists of 16 duplications of the IEEE address of

this node, with no breaks or interruptions, followed by Secure-ON password if security is enabled. This sequence

can be located anywhere within the packet, but must be preceded by a synchronization stream. The

synchronization stream is defined as 6-bytes of FFh.

DEST (6 bytes)

SRC (6 bytes)

MISC (X bytes, X >= 0)

FF … FF (6 bytes)

MAGIC Pattern

DEST * 16

Secure-On Password (6 bytes)

MISC (Y bytes, Y >= 0)

CRC (4 bytes)

Only if Secure-On is Enabled

图 16. Magic Packet Structure

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Feature Description (接下页)

8.3.1.2 Magic Packet Example

The following is an example Magic Packet for a Destination Address of 11h 22h 33h 44h 55h 66h and a Secure-

ON password 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh:

DESTINATION SOURCE MISC FF FF FF FF FF FF

11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66

11 22 33 44 55 66 2A 2B 2C 2D 2E 2F MISC CRC

8.3.1.3 Wake-on-LAN Configuration and Status

Wake-on-LAN functionality is configured through the WOL_CFG Register 0x04A0 – WoL Configuration Register.

Wake-on-LAN status is reported in the WOL_STAT Register 0x04A1 – WoL Status Register. Wake-on-LAN

interrupt flag configuration and status is located in the INT_STAT1 Register 0x0012 – Interrupt Status Register

#1.

8.3.2 Start of Frame Detect for IEEE 1588 Time Stamp

IEEE 802.3bw uses 4B3B encoding (3B4B decoding), reducing a 4-bit data path operating at 25 MHz down to a

3-bit data path operating at 33.334 MHz. For frames and inter-packet gaps that are not divisible by three, one to

two stuff bits are added at the end of a transmitted frame. These stuff bits are removed by the link partner before

the data is routed to the MAC, making it completely transparent to layers above the Physical layer. These stuff

bits cause frame jitter.

The DP83TC811R-Q1 supports an IEEE 1588 indication pulse at the SFD (start of frame delimiter) for receive

and transmit paths. The 1588 SFD pulse indicates the actual time the symbol is presented on the lines (for

transmit), or the first symbol received (for receive), which provides a deterministic reference point. The pulse can

be transmitted out of any of the following pins: LED_0 (GPIO_0), LED_1 (GPIO_1), or CLKOUT (GPIO_2).

There are two registers that are able to control the routing of the IEEE 1588 transmit and receive indications. The

IO_CTRL1 Register 0x0462 – GPIO Control Register #1 is able to route both transmit and receive indications to

LED_0 (GPIO_0) and LED_1 (GPIO_1). CLKOUT transmit and receive 1588 SFD indication is found in the

IO_CTRL2 Register 0x0463 – GPIO Control Register #2.

TX_CLK

XI

Master CLK

TX_EN

TX_CTRL

tT7.1t

+1

MDI

0

-1

图 17. Transmit Latency

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Feature Description (接下页)

RX_CLK

XI

Master CLK

RX_DV

RX_CTRL

tT8.1t

+1

MDI

0

-1

图 18. Receive Latency

8.3.3 Diagnostic Tool Kit

The DP83TC811R-Q1 diagnostic tool kit provides mechanisms for monitoring normal operation, device-level

debugging, system-level debugging, fault detection, and compliance testing. This tool kit includes a built-in self-

test with PRBS data, various loopback modes, Signal Quality Indicator (SQI), Time Domain Reflectometry (TDR),

undervoltage monitor, overtemperature monitor, electrostatic discharge monitor, and IEEE 802.3bw test modes.

8.3.3.1 Signal Quality Indicator

When the DP83TC811R-Q1 is active, the Signal Quality Indicator may be used to determine the quality of link

based on SNR readings made by the device. SQI is presented as both a four-level indication and a percentage

based on the calculated SNR value. Signal quality indication is accessible through the SQI Register 0x0198 –

Signal Quality Indication Register. SQI is continuously monitored by the DP83TC811R-Q1 to allow for real-time

link signal quality status.

Bits[9:8] in register 0x198 provide signal quality status. For SQI value, convert bits[7:0] to decimal form.

表 3. Signal Quality Indicator

BIT[9]

BIT[8]

SIGNAL QUALITY STATUS

No Link

SIGNAL QUALITY INDICATION

0

1

0

1

0

1

SQI ≤ 40

Intermittent/Poor Link

Good Link

40 < SQI ≤ 70

Excellent Link

SQI > 70

Signal-to-noise ratio is accessible through the SNR Register 0x0197 – Signal-to-Noise Ratio Result Register. To

convert this binary register field to dB, follow these steps:

1. Convert bits[7:0] in register 0x197 to decimal form

2. Divide decimal value by 10

3. Result is SNR (dB) reading

8.3.3.2 Electrostatic Discharge Sensing

Electrostatic discharge is a serious issue for electronic circuits and if not properly mitigated can create short-term

issues (signal integrity, link drops, packet loss) as well as long-term reliability faults. The DP83TC811R-Q1 has

robust integrated ESD circuitry and offers an ESD sensing architecture. ESD events can be detected on both the

xMII and MDI pins independently for further analysis and debug.

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Additionally, the DP83TC811R-Q1 provides an interrupt status flag; bit[11] in the INT_STAT1 Register 0x0012 –

Interrupt Status Register #1 when an ESD event is logged in the ESDS Register 0x0448 – Electrostatic

Discharge Status Register. Hardware and software resets are ignored by the ESDS register to prevent

unwarranted clearing.

8.3.3.3 Time Domain Reflectometry

Time domain reflectometry helps determine the quality of the cable, connectors and terminations in addition to

estimating OPEN and SHORT faults along a cable. The DP83TC811R-Q1 transmits a test pulse down the

attached twisted-pair cable. Transmitted pulses continue down the cable and reflect from each imperfection and

fault, allowing the device to measure the time to return and strength (amplitude) of all reflections. This technique

enables the DP83TC811R-Q1 to identify cable OPENs and SHORTs.

TDR is activated by setting bit[15] in the TDR Register 0x001E – Time Domain Reflectometry Register. Cable

diagnostic status is obtained by reading bits[1:0] in the TDR register. TDR runs are stored in the TDRR Register

0x016B – TDR Results Register. When more than one fault is present, additional locations are identified by the

TDRLR1 Register 0x0180 – TDR Location Result Register #1 and the TDRPT Register 0x018A – TDR Peak

Type Register.

8.3.3.4 Temperature and Voltage Sensing

Overtemperature and undervoltage monitoring are always active in the DP83TC811R-Q1 by default. If an

overtemperature condition, an undervoltage condition, or both conditions are detected, interrupt status flags are

set in the INT_STAT2 Register 0x0013 – Interrupt Status Register #2. Additionally, temperature and voltage

monitoring cycle period can be adjusted using the MON_CFG1 Register 0x0480 – Monitor Configuration Register

#1 bits[2:0]. By default, sample time is set to 31 ms, but also has a configurable range of 16 ms to 240 ms.

Single-run temperature and voltage monitoring is also supported when bit[1] is set to 0b0 in the MON_CFG2

Register 0x0481 – Monitor Configuration Register #2, disabling period monitoring. To activate a single run, bit[0]

in MON_CFG2 register must be set after disabling period monitoring. Temperature monitor results are available

in the MON_STAT1 Register 0x0483 – Monitor Status Register #1. VDDA and VDDIO supply monitor results are

available in the MON_STAT2 Register 0x0484 – Monitor Status Register #2.

8.3.3.5 Built-In Self-Test

The DP83TC811R-Q1 incorporates an internal PRBS Built-in Self-Test (BIST) circuit to accommodate in-circuit

testing and diagnostics. The BIST circuit can be used to test the integrity of transmit and receive data paths.

BIST can be enabled while using internal loopbacks (MII, PCS or analog) or external loopback when using a Link

Partner configured for Reverse Loopback. BIST simulates pseudo-random data transfer scenarios in format of

real packets and Inter-Packet Gap (IPG) on the lines. It allows full control over packet lengths and IPG.

BIST Packet Length is controlled using bits[10:0] in the BICTSR2 Register 0x001C – BIST Control and Status

Register #2. BIST IPG Length is controlled using bits[7:0] in the BICTSR1 Register 0x001B – BIST Control and

Status Register #1.

BIST is implemented with independent transmit and receive paths, with the transmit clock generating a

continuous stream of a pseudo-random sequence. The device generates a 15-bit pseudo-random sequence for

BIST. Received data is compared to the generated pseudo-random data to determine pass or fail status. The

number of error bytes that the PRBS checker received is stored in bits[15:8] of the BICSR1 register. PRBS lock

status and sync can be read from the BISTCR Register 0x0016 – BIST Control Register.

PRBS test can be put in continuous mode using bit[14] in the BISCR register. In continuous mode, when the

BIST error counter reaches its maximum value, the counter starts counting from zero again. To read the BIST

error count, bit[15] in the BICSR1 register must be set to 0b1. This will lock the current number of BIST errors for

read-back. Note that setting bit[15] also clears the BIST error counter.

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8.3.3.6 Loopback Modes

There are several loopback options within the DP83TC811R-Q1 that test and verify various functional blocks

within the PHY. Loopback modes also provide on-board and system level verification testing and debug.

8.3.3.6.1 xMII Loopback

xMII Loopback is the shallowest loop through the PHY. It is a useful test mode to validate communications

between the MAC and the PHY. When in xMII Loopback, data transmitted from a connected MAC on the TX path

is internally looped back in the DP83TC811R-Q1 to the RX pins where it can be checked by the MAC. There is

no link indication when in xMII loopback.

xMII Loopback is enabled by setting bit[14] in the BMCR Register 0x0000 – Basic Mode Control Register.

xMII Loopback

PMA Receive

PCS Receive

PMA Transmit

PCS Transmit

MDI

MII

图 19. xMII Loopback

8.3.3.6.2 PCS Loopback

PCS Loopback will loop back data prior to it exiting the PCS and entering the PMA. Data received from the MAC

on the transmit path is brought through the digital block within the PHY where it is then routed back to the MAC

through the receive path. The DP83TC811R-Q1 receive PMA circuitry is configured for isolation to prevent

contention.

PCS Loopback is enabled by setting bits[6:2] = 0b0001 in the BISTCR Register 0x0016 – BIST Control Register.

PMA Receive

PCS Receive

PCS Loopback

PMA Transmit

PCS Transmit

MDI

MII

图 20. PCS Loopback

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8.3.3.6.3 Analog Loopback

Analog Loopback uses the echoed signals from the unterminated MDI and decodes these signals in the Hybrid to

return the data to the MAC.

Analog Loopback is enabled by setting bits[6:2] = 0b0010 in the BISTCR register.

PMA Receive

PCS Receive

Open

PMA Transmit

PCS Transmit

MDI

MII

图 21. Analog Loopback

8.3.3.6.4 Reverse Loopback

Reverse Loopback receives data on the MDI and passes it through the entire receive block where it is then

looped back within the PCS layer to the transmit block. The data is transmitted back out on the MDI to the

attached Link Partner. To avoid contention, MAC transmit path is isolated.

Reverse Loopback is enable by setting bits[6:2] = 0b0100 in the BISTCR register.

PMA Receive

PCS Receive

PMA Transmit

PCS Transmit

Reverse

Loopback

MDI

MII

图 22. Reverse Loopback

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8.3.4 Compliance Test Modes

There are four PMA compliance test modes required in IEEE 802.3bw, sub-clause 96.5.2, which are all

supported by the DP83TC811R-Q1. These compliance test modes include: transmitter waveform Power Spectral

Density (PSD) mask, amplitude, distortion, 100BASE-T1 Master jitter, 100BASE-T1 Slave jitter, droop, transmitter

frequency, frequency tolerance, return loss, and mode conversion. Any of the three GPIOs can be used to output

TX_TCLK for the 100BASE-T1 Slave jitter measurement.

8.3.4.1 Test Mode 1

Test mode 1 evaluates transmitter droop. In test mode 1, the DP83TC811R-Q1 transmits ‘+1’ symbols for a

minimum of 600 ns followed by ‘–1’ symbols for a minimum of 600 ns. This pattern is repeated continuously until

the test mode is disabled.

Test mode 1 is enabled by setting bits[15:13] = 0b001 in the TEST_CTRL Register 0x0836 – MMD1 100BASE-

T1 PMA Test Control Register.

Additionally, transmit symbol width can be controlled using bits[9:4] in the TEST_MODE_CTRL Register

0x0497 – Test Mode Control Register.

8.3.4.2 Test Mode 2

Test mode 2 evaluates the transmitter 100BASE-T1 Master mode jitter. In test mode 2, the DP83TC811R-Q1

transmits a {+1,-1} data symbol sequence. The transmitter synchronizes the transmitted symbols from the local

reference clock.

Test mode 2 is enabled by setting bits[15:13] = 0b010 in TEST_CTRL register.

8.3.4.3 Test Mode 4

Test mode 4 evaluates the transmitter distortion. In test mode 4, the DP83TC811R-Q1 transmits the sequence of

symbols generated by 公式 1:

g(x) = 1 + x⁹+ x¹¹

(1)

The bit sequences, x0n and x1n, are generated from combinations of the scrambler in accordance to and :

'x0_n= Scr_n[0]

(2)

(3)

x1_n= Scr_n[1] ^ Scr_n[4]

Example streams of the 3-bit nibbles are shown in 表 4.

表 4. Transmitter Test Mode 4 Symbol Mapping

x1n

0

x0n

0

PAM3 SYMBOL

0

+1

0

1

0

1

–1

Test mode 4 is enabled by setting bits[15:13] = 0b100 in TEST_CTRL register.

8.3.4.4 Test Mode 5

Test mode 5 evaluates the transmitter PSD mask. In test mode 5, the DP83TC811R-Q1 transmits a pseudo-

random sequence of PAM3 symbols.

Test mode 5 is enabled by setting bits[15:13] = 0b101 in TEST_CTRL register.

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8.4 Device Functional Modes

State Change #3

State Change #4

Normal

PHY Enabled

Sleep Request

PHY Enabled

From any state

State

Change #6

EN = LOW

and RESET_N = HIGH

and Power-on

State

Change #5

State

Change #1

State

Change #2

Silent

PHY Disabled

State

Change #7

Disable

PHY Disabled

State

Change #8

WAKE = HIGH

or

Energy detected on MDI

Standby

PHY Disabled

Sleep

PHY Disabled

Reset

EN = HIGH

and RESET_N = HIGH

and Power-on

RESET_N = HIGH

and

POR = complete

RESET_N = LOW

and EN = HIGH

and Power-on

Power-on

Power-off

Reset

PHY Disabled

Power-off

PHY Disabled

From any state

图 23. PHY Operation State Diagram

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Device Functional Modes (接下页)

8.4.1 Power Down

When VDDA is below the POR threshold (1V), the DP83TC811R-Q1 is in a power-down state. All digital IOs will

remain in high impedance states and analog blocks are disabled. PMA termination is not present when powered

down.

8.4.2 Reset

Reset is activated upon power-up, when RESET is pulled LOW (for the minimum reset pulse time) or if hardware

reset is initiated by setting bit[15] in the PHYRCR Register 0x001F – PHY Reset Control Register. All digital

circuitry is cleared along with register settings during reset. Once reset completes, device bootstraps are re-

sampled and associated bootstrap registers are set accordingly. PMA termination is not present in reset.

8.4.3 Disable

To disable the PHY, EN pin must be held LOW. When disabled, the PHY behaves the same as it does in power-

down. PMA termination is not present when the PHY is disabled.

8.4.4 Standby

The device (100BASE-T1 Master mode only) automatically enters into standby post power-up and reset so long

that EN is held HIGH and the device is bootstrapped for managed operation.

In standby, all PHY functions are operational except for PCS and PMA blocks. Link establishment is not possible

in standby and data cannot be transmitted or received. SMI functions are operational and register configurations

are maintained.

If the device is configured for autonomous operation through bootstrap setting, the PHY automatically switches to

normal operation once POR is complete.

8.4.5 Normal

Normal mode can be entered from either autonomous or managed operation. When in autonomous operation,

the PHY will automatically try to establish a link with a valid Link Partner once POR is complete.

In managed operation, SMI access is required to allow the device to exit standby (100BASE-T1 Master mode

only); commands issued through the SMI allow the device to exit standby and enables both the PCS and PMA

blocks. All device features are operational in normal mode.

Autonomous operation can be enabled through SMI access by setting bit[6] in the AUTO_PHY Register

0x018B – Autonomous PHY Control Register.

8.4.6 Sleep Request

Sleep request is entered when switching from normal mode to sleep mode. This is an intermediate state and is

used to for a smooth transition into sleep mode. In sleep request mode, the PHY transmits LPS code-groups,

informing the Link Partner that sleep is requested.

PHY sleep_rqst_timer (default = 1ms) begins once the PHY enters into sleep request mode. LPS decoding at the

Link Partner will trigger the LPS RECEIVED interrupt. Once sleep_rqst_timer expires, the device transitions to

silent mode prior to entering sleep mode. During sleep request, any frame received on the MDI or xMII enables

the DP83TC811R-Q1; the PHY exits sleep request and enters normal mode.

8.4.7 Silent

The DP83TC811R-Q1 enters silent mode once the sleep_rqst_timer expires or the PHY no longer detects

activity on the MDI, indicating that the Link Partner has already moved to silent mode.

Silent mode is only an intermediate state prior to sleep. The PHY sets tx_mode = SEND_Z and (0,0) are

transmitted on the MDI. If sleep enable, bit[1] in the AUTO_PHY Register 0x018B – Autonomous PHY Control

Register, is set and no energy is detected on the MDI for the duration of silent_timer (default = 8 ms), the

DP83TC811R-Q1 will enter sleep mode. However, if energy is detected on the MDI prior to silent_timer

expiration, the PHY enters standby mode.

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Device Functional Modes (接下页)

8.4.8 Sleep

If sleep enable is set, the PHY transitions to sleep mode after silent_timer expires; however, if sleep enable is not

set, the device transitions to standby once silent_timer expires. By default, sleep enable is set. Once in sleep

mode, all PHY blocks are disabled except for energy detection on the MDI. All register configurations are lost in

sleep mode. No link can be established, data cannot be transmitted or received and SMI access is not available

when in sleep mode.

8.4.9 Low-Power Sleep

Low-Power Sleep code-groups are used to inform the Link Partner that sleep mode is requested. The

DP83TC811R-Q1 uses the Sdn[1] scrambler stream for LPS.

Sdn[1] scrambler stream must be set prior to LPS use, found in LPS_CFG Register 0x04E5 – LPS Configuration

Register.

8.4.10 Wake-Up

The user can wake up the DP83TC811R-Q1 remotely through energy detection on the MDI or locally using the

WAKE pin. For local wake, the WAKE pin must be pulled HIGH. If the WAKE pin is tied LOW, the PHY will only

exit sleep if energy is detected on the MDI.

8.4.11 State Transitions

8.4.11.1 State Transition #1 - Standby to Normal

Autonomous Operation: The PHY will automatically transition to Normal state upon POR completion.

Managed Operation: The PHY will transition to Normal state out of Standby if any of the following occurs:

1. Energy detection, when energy is detected on the MDI

2. Register access, enabling Autonomous operation by setting bit[6] in the AUTO_PHY Register 0x018B –

Autonomous PHY Control Register

3. Register access, forcing Normal state by setting bit[0] in the PWRM Register 0x018C – Power Mode Register

8.4.11.2 State Transition #2 - Normal to Standby

This state transition is not supported.

8.4.11.3 State Transition #3 - Normal to Sleep Request

Sleep Request state can be entered when valid LPS code-groups are received on the MDI from a Link Partner.

注

The PHY will not be permitted to transmit LPS code-groups unless the registers below are

set.

To enable LPS code-group transmission, the LPS transmission enable bit[0] must be set in AUTO_PHY Register

0x018B – Autonomous PHY Control Register.

The Sdn[1] scrambler stream must be enabled by setting bits[9:8] = 0b11 in LPS_CFG Register 0x04E5 – LPS

Configuration Register.

LPS code-group identification within the PCS layer must be enabled by setting bit[0] in LPS_CTRL2 Register

0x0487 – LPS Control Register #2.

LPS code-groups are sent once Sleep Request is enabled by setting bit[1] in PWRM Register 0x018C – Power

Mode Register.

8.4.11.4 State Transition #4 - Sleep Request to Normal

Sleep Request can be terminated and the device re-enter Normal state by any of the following methods:

1. Register access, forcing Normal state by setting bit[0] in the PWRM Register 0x018C – Power Mode Register

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Device Functional Modes (接下页)

2. Frame detection, when a valid frame is transmitted or received before sleep_rqst_timer expires

8.4.11.5 State Transition #5 - Sleep Request to Standby

This state transition is not supported.

8.4.11.6 State Transition #6 - Sleep Request to Silent

Silent state can be entered by any of the following methods:

1. Valid LPS code-groups are received on the MDI and sleep_rqst_timer expired

2. Quiet MDI, SEND_Z [ternary symbol vectors of (0,0)] detected on the MDI

8.4.11.7 State Transition #7 - Silent to Standby

Standby state can be entered by any of the following methods:

1. Standby enable, sleep is disabled by setting bit[1] = 0b0 in the AUTO_PHY Register 0x018B – Autonomous

PHY Control Register and silent_timer expired

2. MDI Detection, Non-SEND_Z code-groups detected on the MDI prior to silent_timer expiration

8.4.11.8 State Transition #8 - Silent to Sleep

The PHY will exit Silent state and enter into Sleep state once the silent_timer expires or no activity is detected on

the transmitter or receiver.

8.4.12 Media Dependent Interface

8.4.12.1 100BASE-T1 Master and 100BASE-T1 Slave Configuration

100BASE-T1 Master and 100BASE-T1 Slave are configured using either hardware bootstraps or through register

access.

LED_0 controls the 100BASE-T1 Master and 100BASE-T1 Slave bootstrap configuration. By default, 100BASE-

T1 Slave mode is configured because there is an internal pulldown resistor on LED_0 pin. If 100BASE-T1 Master

mode configuration through hardware bootstrap is preferred, an external pullup resistor is required.

Additionally, bit[14] in the PMA_CTRL2 Register 0x0834 – MMD1 PMA Control Register #2 controls the

100BASE-T1 Master and 100BASE-T1 Slave configuration. When this bit is set, 100BASE-T1 Master mode is

enabled.

8.4.12.2 Auto-Polarity Detection and Correction

During the link training process, the DP83TC811R-Q1 100BASE-T1 Slave device is able to detect polarity

reversal and automatically corrects the error. If polarity reversal is detected, the 100BASE-T1 Slave will invert its

own transmitted signals to account for the error and ensure compatibility with the 100BASE-T1 Master. Polarity

at the 100BASE-T1 Master is always observed as correct because polarity detection and correction is handled

entirely by the 100BASE-T1 Slave.

8.4.12.3 Jabber Detection

The jabber function prevents the PCS Receive state machine from locking up into a DATA state if the End-of-

Stream Delimiters, ESD1 and ESD2, are never detected or received within the rcv_max_timer. When the

maximum receive DATA state timer expires, the PCS Receive state machine is reset and transitions into IDLE

state. IEEE 802.3bw specifies that jabber timeout be set to 1.08 ms ± 54 μs. By default, jabber timeout in the

DP83TC811R-Q1 is set to 1.1 ms. This timer is configurable in JAB_CFG Register 0x0496 – Jabber

Configuration Register.

8.4.12.4 Interleave Detection

The interleave function allows for the DP83TC811R-Q1 to detect and de-interleave the serial stream from a

connected link partner. The two possible interleave sequences of ternary symbols include: (TA_n, TB_n) or (TB_n,

TA_n).

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Device Functional Modes (接下页)

8.4.13 MAC Interfaces

8.4.13.1 Media Independent Interface

The Media Independent Interface (MII) is a synchronous 4-bit wide nibble data interface that connects the PHY to

the MAC. The MII is fully compliant with IEEE 802.3-2015 clause 22.

The MII signals are summarized in 表 5:

表 5. MII Signals

FUNCTION

PINS

TX_D[3:0]

Data Signals

RX_D[3:0]

TX_EN, TX_ER

RX_DV, RX_ER

TX_CLK

Control Signals

Clock Signals

RX_CLK

TX_CLK

TX_ER

TX_EN

TX_D[3:0]

RX_CLK

RX_DV

PHY

MAC

RX_ER

RX_D[3:0]

图 24. MII Signaling

表 6. MII Transmit Encoding

TX_EN

TX_ER

TX_D[3:0]

DESCRIPTION

0

1

0

1

0

1

0000 through 1111

Normal Inter-Frame

Reserved

Normal Data Transmission

Transmit Error Propagation

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表 7. MII Receive Encoding

RX_DV

RX_ER

RX_D[3:0]

0000 through 1111

0000

DESCRIPTION

Normal Inter-Frame

Reserved

0

1

0

1

0

1

0001 through 1101

1110

False Carrier Indication

Reserved

1111

0000 through 1111

Normal Data Reception

Data Reception with Errors

8.4.13.2 Reduced Media Independent Interface

The DP83TC811R-Q1 incorporates the Reduced Media Independent Interface (RMII) as defined in the RMII

Revision 1.2 and 1.0 from the RMII consortium. The purpose of this interface is to provide a reduced pin count

alternative to the IEEE 802.3u MII as specified in Clause 22. Architecturally, the RMII specification provides an

additional reconciliation layer on either side of the MII, but can be implemented in the absence of an MII.

The DP83TC811R-Q1 offers two types of RMII operations: RMII Slave and RMII Master. In RMII Slave Mode, the

DP83TC811R-Q1 operates off a 50-MHz CMOS-level oscillator, which is either provided by the MAC or

synchronous to the MAC's reference clock. In RMII Master operation, the DP83TC811R-Q1 operates off of either

a 25-MHz CMOS-level oscillator connected to XI pin or a 25-MHz crystal connected across XI and XO pins.

When bootstrapping to RMII Master Mode, a 50-MHz output clock will automatically be enabled on RX_D3. This

50-MHz output clock should be routed to the MAC.

The RMII specification has the following characteristics:

•

Single clock reference shared between MAC and PHY

Provides independent 2-bit wide transmit and receive data paths

In this mode, data transfers are two bits for every clock cycle using the 50-MHz reference clock for both transmit

and receive paths.

The RMII signals are summarized in 表 8:

表 8. RMII Signals

FUNCTION

PINS

TX_D[1:0]

RX_D[1:0]

TX_EN

Data Signals

Control Signals

CRS_DV

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TX_EN

TX_D[1:0]

RX_CLK (optional)

RX_DV (optional)

RX_ER (optional)

RX_D[1:0]

PHY

MAC

CRS_DV

图 25. RMII Signaling

表 9. RMII Transmit Encoding

TX_EN

TX_D[1:0]

00 through 11

DESCRIPTION

Normal Inter-Frame

0

1

Normal Data Transmission

表 10. RMII Receive Encoding

CRS_DV

RX_ER

RX_D[1:0]

00 through 11

00

DESCRIPTION

0

1

0

1

0

1

Normal Inter-Frame

Reserved

01 through 11

00 through 11

Normal Data Reception

Data Reception with Errors

RMII Slave: Data on TX_D[1:0] are latched at the PHY with reference to the rising edge of the reference clock at

the XI pin. Data is presented on RX_D[1:0] with reference to the same rising clock edges at the XI pin.

RMII Master: Data on TX_D[1:0] are latched at the PHY with reference to the rising edge of the reference clock

at the RX_D3 pin. Data is presented on RX_D[1:0] with reference to the same rising clock edges at the RX_D3

pin.

The DP83TC811R-Q1 RMII supplies an RX_DV signal, which provides a simpler method to recover receive data

without the need to separate RX_DV from the CRS_DV indication. RX_ER is also supported even though it is not

required by the RMII specification.

RMII includes a programmable FIFO to adjust for the frequency differences between the reference clock and the

recovered clock. The programmable FIFO, located in the , minimizes internal propagation delay based on

expected maximum packet size and clock accuracy.

表 11 indicates how to program the FIFO based on the expected maximum packet size and clock accuracy. This

table is based on the assumption that the local reference clock and link partner reference clock have the same

accuracy.

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表 11. Recommended RMII Packet Sizes

START THRESHOLD

RECOMMENDED PACKET SIZE AT ±100ppm

2-bits

3-bits

4-bits

5-bits

1250 bytes

3750 bytes

6250 bytes

8750 bytes

8.4.13.3 Reduced Gigabit Media Independent Interface

The DP83TC811R-Q1 also supports Reduced Gigabit Media Independent Interface (RGMII) as specified by

RGMII version 2.0 with LVCMOS. RGMII is designed to reduce the number of pins required to connect MAC and

PHY. To accomplish this goal, the control signals are multiplexed. Both rising and falling edges of the clock are

used to sample the control signal pin on transmit and receive paths. Data is samples on just the rising edge of

the clock. For 100-Mbps operation, RX_CLK and TX_CLK operate at 25 MHz.

The RGMII signals are summarized in 表 12:

表 12. RGMII Signals

FUNCTION

PINS

TX_D[3:0]

RX_D[3:0]

TX_CTRL

RX_CTRL

TX_CLK

Data Signals

Control Signals

Clock Signals

RX_CLK

TX_CLK

TX_CTRL

TX_D[3:0]

RX_CLK

PHY

MAC

RX_CTRL

RX_D[3:0]

25-MHz Crystal or

CMOS-level

Oscillator

图 26. RGMII Connections

表 13. RGMII Transmit Encoding

TX_CTRL

(POSITIVE EDGE)

TX_CTRL

(NEGATIVE EDGE)

TX_D[3:0]

DESCRIPTION

0

1

0

1

0

1

0000 through 1111

Normal Inter-Frame

Reserved

Normal Data Transmission

Transmit Error Propagation

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表 14. RGMII Receive Encoding

RX_CTRL

(POSITIVE EDGE)

RX_CTRL

(NEGATIVE EDGE)

RX_D[3:0]

DESCRIPTION

0

1

0

1

0

1

0000 through 1111

0000 through 1101

1110

Normal Inter-Frame

Reserved

False Carrier Indication

Reserved

1111

0000 through 1111

Normal Data Reception

Data Reception with Errors

During packet reception, RX_CLK may be stretched on either the positive or negative pulse to accommodate the

transition from the internal free running clock to a recovered clock (data synchronous). Data may be duplicated

on the falling edge of the clock because double data rate (DDR) is only required for 1-Gbps operation, which is

not supported by the DP83TC811R-Q1.

The DP83TC811R-Q1 supports in-band status indication to help simplify link status detection. Inter-frame signals

on RX_D[3:0] pins as specified in 表 15.

表 15. RGMII In-Band Status

RX_CTRL

RX_D3

RX_D[2:1]

RX_CLK Clock Speed:

00 = 2.5 MHz

RX_D0

00

Duplex Status:

Link Status:

Note:

0 = Half-Duplex

1 = Full-Duplex

01 = 25 MHz

0 = Link not established

1 = Valid link established

In-band status is only valid when

RX_CTRL is low

10 = 125 MHz

11 = Reserved

8.4.14 Serial Management Interface

The Serial Management Interface (SMI) provides access to the DP83TC811R-Q1 internal register space for

status information and configuration. The SMI frames and base registers are compatible with IEEE 802.3 clause

22. The implemented register set consists of the registers required by the IEEE 802.3 plus several others to

provide additional visibility and controllability of the DP83TC811R-Q1. Additionally, the DP83TC811R-Q1

includes control and status registers added to clause 45 as defined by IEEE 802.3bw. Access to clause 45

register field is achieved using clause 22 access.

The SMI includes the management clock (MDC) and the management input and output data pin (MDIO). MDC is

sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of

25 MHz. MDC is not expected to be continuous, and can be turned off by the external management entity when

the bus is idle.

MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched on

the rising edge of the MDC. MDIO pin requires a pullup resistor (2.2 KΩ), which pulls MDIO high during IDLE and

turnaround.

Up to 16 DP83TC811R-Q1 PHYs can share a common SMI bus. To distinguish between the PHYs, a 4-bit

address is used. During power-up-reset, the DP83TC811R-Q1 latches the PHYAD[3:0] configuration pins to

determine its address.

The management entity must not start an SMI transaction in the first cycle after power-up-reset. To maintain valid

operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is deasserted. In normal

MDIO transactions, the register address is taken directly from the management-frame reg_addr field, thus

allowing direct access to 32 16-bit registers (including those defined in IEEE 802.3 and vendor specific). The

data field is used for both reading and writing. The Start code is indicated by a <01> pattern. This pattern makes

sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time

inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no

device may actively drive the MDIO signal during the first bit of turnaround. The addressed DP83TC811R-Q1

drives the MDIO with a zero for the second bit of turnaround and follows this with the required data.

For write transactions, the station-management entity writes data to the addressed DP83TC811R-Q1, thus

eliminating the requirement for MDIO Turnaround. The turnaround time is filled by the management entity by

inserting <10>.

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表 16. SMI Protocol Structure

SMI PROTOCOL

Read Operation

Write Operation

8.4.15 Direct Register Access

Direct register access can be used for the first 31 registers (0x0 through 0x1F).

8.4.16 Extended Register Space Access

The DP83TC811R-Q1 SMI function supports read and write access to the extended register set using registers

REGCR (0xD) and ADDAR (0xE) and the MDIO Manageable Device (MMD) indirect method defined in IEEE

802.3ah Draft for Clause 22 for accessing the Clause 45 extended register set.

REGCR (0xD) is the MDIO Manageable MMD access control. In general, register REGCR[4:0] is the device

address DEVAD that directs any accesses of ADDAR (0xE) register to the appropriate MMD.

The DP83TC811R-Q1 supports two MMD device addresses:

1. The vendor-specific device address DEVAD[4:0] = 11111 is used for general MMD register accesses.

2. DEVAD[4:0] = 00001 is used for 100BASE-T1 PMA MMD register accesses. Register names for registers

accessible at this device address are preceded by MMD1.

All accesses through register REGCR and ADDAR must use the correct DEVAD. Transactions with other

DEVADs are ignored. REGCR[15:14] holds the access function: address (00), data with no post increment (01),

data with post increment on read and writes (10) and data with post increment on writes only (11).

•

ADDAR is the address and data MMD register. ADDAR is used in conjunction with REGCR to provide the

access to the extended register set. If register REGCR[15:14] is (00), then ADDAR holds the address of the

extended address space register. Otherwise, ADDAR holds the data as indicated by the contents of its

address register. When REGCR[15:14] is set to (00), accesses to register ADDAR modify the extended

register set address register. This address register must always be initialized in order to access any of the

registers within the extended register set.

•

When REGCR[15:14] is set to (01), accesses to register ADDAR access the register within the extended

register set selected by the value in the address register.

When REGCR[15:14] is set to (10), access to register ADDAR access the register within the extended

register set selected by the value in the address register. After that access is complete, for both reads and

writes, the value in the address register is incremented.

•

When REGCR[15:14] is set to (11), access to register ADDAR access the register within the extended

register set selected by the value in the address register. After that access is complete, for write access only,

the value in the address register is incremented. For read accesses, the value of the address register remains

unchanged.

The following sections describe how to perform operations on the extended register set using register REGCR

and ADDAR.

8.4.17 Write Address Operation

To set the address register:

1. Write the value 0x1F (address function field = 00, DEVAD = '11111') to register REGCR.

2. Write the register address to register ADDAR.

Subsequent writes to register ADDAR (step 2) continue to write the address register.

8.4.17.1 MMD1 - Write Address Operation

For writing register addresses within MMD1 field:

1. Write the value 0x1 (address function field = 00, DEVAD = '00001') to register REGCR.

2. Write the register address to register ADDAR.

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8.4.18 Read Address Operation

To read the address register:

1. Write the value 0x1F (address function field = 00, DEVAD = '11111') to register REGCR.

2. Read the register address from register ADDAR.

Subsequent reads to register ADDAR (step 2) continue to read the address register.

8.4.18.1 MMD1 - Read Address Operation

For reading register addresses within MMD1 field:

1. Write the value 0x1 (address function field = 00, DEVAD = '00001') to register REGCR.

2. Read the register address from register ADDAR.

8.4.19 Write Operation (No Post Increment)

To write a register in the extended register set:

1. Write the value 0x1F (address function field = 00, DEVAD = '11111') to register REGCR.

2. Write the desired register address to register ADDAR.

3. Write the value 0x401F (data, no post increment function field = 01, DEVAD = '11111') to register REGCR.

4. Write the content of the desired extended register set to register ADDAR.

Subsequent writes to register ADDAR (step 4) continue to rewrite the register selected by the value in the

address register.

注

Steps (1) and (2) can be skipped if the address register was previously configured.

8.4.19.1 MMD1 - Write Operation (No Post Increment)

To write a register in the MMD1 extended register set:

1. Write the value 0x1 (address function field = 00, DEVAD = '00001') to register REGCR.

2. Write the desired register address to register ADDAR.

3. Write the value 0x4001 (data, no post increment function field = 01, DEVAD = '00001') to register REGCR.

4. Write the content of the desired extended register set to register ADDAR.

8.4.20 Read Operation (No Post Increment)

To read a register in the extended register set:

1. Write the value 0x1F (address function field = 00, DEVAD = '11111') to register REGCR.

2. Write the desired register address to register ADDAR.

3. Write the value 0x401F (data, no post increment function field = 01, DEVAD = '11111') to register REGCR.

4. Read the content of the desired extended register set in register ADDAR.

Subsequent reads to register ADDAR (step 4) continue to reading the register selected by the value in the

address register.

注

Steps (1) and (2) can be skipped if the address register was previously configured.

8.4.20.1 MMD1 - Read Operation (No Post Increment)

To read a register in the MMD1 extended register set:

1. Write the value 0x1 (address function field = 00, DEVAD = '00001') to register REGCR.

2. Write the desired register address to register ADDAR.

3. Write the value 0x4001 (data, no post increment function field = 01, DEVAD = '00001') to register REGCR.

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4. Read the content of the desired extended register set in register ADDAR.

8.4.21 Write Operation (Post Increment)

To write a register in the extended register set with post increment:

1. Write the value 0x1F (address function field = 00, DEVAD = '11111') to register REGCR.

2. Write the desired register address to register ADDAR.

3. Write the value 0x801F (data, post increment function field = 10, DEVAD = '11111') or the value 0xC01F

(data, post increment on writes function field = 11, DEVAD = '11111') to register REGCR.

4. Write the content of the desired extended register set to register ADDAR.

Subsequent writes to register ADDAR (step 4) write the next higher addressed data register selected by the

value of the address register; the address register is incremented after each access.

8.4.21.1 MMD1 - Write Operation (Post Increment)

To write a register in the MMD1 extended register set with post increment:

1. Write the value 0x1 (address function field = 00, DEVAD = '00001') to register REGCR.

2. Write the desired register address to register ADDAR.

3. Write the value 0x8001 (data, post increment function field = 10, DEVAD = '00001') or the value 0xC001

(data, post increment on writes function field = 11, DEVAD = '00001') to register REGCR.

4. Write the content of the desired extended register set to register ADDAR.

8.4.22 Read Operation (Post Increment)

To read a register in the extended register set and automatically increment the address register to the next

higher value following the write operation:

1. Write the value 0x1F (address function field = 00, DEVAD = '11111') to register REGCR.

2. Write the desired register address to register ADDAR.

3. Write the value 0x801F (data, post increment function field = 10, DEVAD = '11111') to register REGCR.

4. Read the content of the desired extended register set in register ADDAR.

Subsequent reads to register ADDAR (step 4) read the next higher addressed data register selected by the value

of the address register; the address register is incremented after each access.

8.4.22.1 MMD1 - Read Operation (Post Increment)

To read a register in the MMD1 extended register set and automatically increment the address register to the

next higher value following the write operation:

1. Write the value 0x1 (address function field = 00, DEVAD = '00001') to register REGCR.

2. Write the desired register address to register ADDAR.

3. Write the value 0x8001 (data, post increment function field = 10, DEVAD = '00001') to register REGCR.

4. Read the content of the desired extended register set in register ADDAR.

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8.5 Programming

8.5.1 Strap Configuration

The DP83TC811R-Q1 uses functional pins as strap options to place the device into specific modes of operation.

The values of these pins are sampled at power up and hardware reset (through either the RESET pin or register

access). The strap pins support 4 levels, which are described in greater detail below. Configuration of the device

may be done through 4-level strapping or through serial management interface.

注

Because strap pins are functional pins after reset is deasserted, they should not be

connected directly to VDDIO or GND. Either pullup resistors, pulldown resistors, or both

are required for proper operation.

VDDIO

R_H

9 kΩ

±25%

R_L

图 27. Strap Circuit

表 17. Recommended 4-Level Strap Resistor Ratios⁽¹⁾⁽²⁾

MODE

IDEAL RH (kΩ)

IDEAL RL (kΩ)

OPEN

1

2

3

4

OPEN

10

2.49

5.76

2.49

OPEN

(1) Strap resistors with 1% tolerance are recommended.

(2) Resistor ratios are only a recommendation. Use the bootstrap threshold values contained within the Electrical Characteristics table for

more precise mode selections.

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The following table describes the DP83TC811R-Q1 configuration bootstraps:

表 18. 4-Level Bootstraps

NAME

DEFAULT

MODE

PIN NO.

STRAP FUNCTION

DESCRIPTION

MODE

PHY_AD[0]

PHY_AD[2]

1

0

RX_DV

RX_ER

RX_D0

RX_D1

RX_D2

RX_D3

LED_0

15

1

2

0

1

PHY_AD: PHY Address ID

3

1

4

1

0

MODE

PHY_AD[1]

PHY_AD[3]

1

0

14

26

25

24

23

35

2

0

1

PHY_AD: PHY Address ID

3

1

4

1

0

MODE

MAC[0]

TEST[0]

1

0

MAC: MAC Interface Selection

TEST: Test Mode Selection

2

0

1

3

1

4

1

0

MODE

MAC[1]

TEST[1]

1

0

MAC: MAC Interface Selection

TEST: Test Mode Selection

2

0

1

3

1

4

1

0

MODE

MAC[2]

TEST[2]

1

0

MAC: MAC Interface Selection

TEST: Test Mode Selection

2

3

0

1

4

1

0

MODE

1

RESERVED

0

Reserved

MODE

1

RX_D3 must be strapped to MODE 1

MS

RESERVED

MS: 100BASE-T1 Master & 100BASE-T1

Slave Selection

Note: LED_0 must only be set for bootstrap

MODE 1 or MODE 4.

0

Reserved

4

1

AUTO

0

MODE

1

AUTO: Autonomous Disable

Note 1: LED_1 must only be set for

bootstrap MODE 1 or MODE 4.

Note 2: Autonomous bootstrap is only active

for 100BASE-T1 Master mode PHYs. This

bootstrap is ignored when the PHY is

bootstrapped for 100BASE-T1 Slave mode

operation.

Reserved

LED_1

6

1

4

1

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表 19. 100BASE-T1 Master and 100BASE-T1 Slave Selection Bootstrap

MS

0

DESCRIPTION

100BASE-T1 Slave Configuration

100BASE-T1 Master Configuration

1

表 20. MAC Interface Selection Bootstraps

MAC[2]

MAC[1]

MAC[0]

DESCRIPTION

0

RESERVED

0

1

0

1

0

1

0

1

0

1

0

1

MII

RMII Slave

RMII Master

RGMII (Align Mode)

RGMII (TX Internal Delay Mode)

RGMII (TX and RX Internal Delay Mode)

RGMII (RX Internal Delay Mode)

表 21. Test Mode Bootstraps

TEST[2]

TEST[1]

TEST[0]

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Normal Operation

Test Mode 1

Test Mode 2

RESERVED

Test Mode 4

Test Mode 5

RESERVED

表 22. PHY Address Bootstraps

PHY_AD[3]

PHY_AD[2]

PHY_AD[1]

PHY_AD[0]

DESCRIPTION

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PHY Address: 0b00000 (0)

PHY Address: 0b00001 (1)

PHY Address: 0b00010 (2)

PHY Address: 0b00011 (3)

PHY Address: 0b00100 (4)

PHY Address: 0b00101 (5)

PHY Address: 0b00110 (6)

PHY Address: 0b00111 (7)

PHY Address: 0b01000 (8)

PHY Address: 0b01001 (9)

PHY Address: 0b01010 (10)

PHY Address: 0b01011 (11)

PHY Address: 0b01100 (12)

PHY Address: 0b01101 (13)

PHY Address: 0b01110 (14)

PHY Address: 0b01111 (15)

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表 23. Autonomous Mode Bootstrap

AUTO

DESCRIPTION

0

1

Autonomous Mode, PHY able to establish link after power-up

Managed Mode, PHY must be allowed to establish link after power-up based on register write

8.5.2 LED Configuration

The DP83TC811R-Q1 supports up to three configurable Light Emitting Diode (LED) pins: LED_0, LED_1, and

LED_2 (CLKOUT). Several functions can be multiplexed onto the LEDs for different modes of operation. LED

operations are selected using the LED_CFG1 Register 0x0460 – LED Configuration Register #1.

Because the LED output pins are also used as strap pins, external components required for strapping and the

user must consider the LED usage to avoid contention. Specifically, when the LED outputs are used to drive

LEDs directly, the active state of each output driver is dependent on the logic level sampled by the corresponding

input upon power up or hardware reset.

图 28 shows the two proper ways of connecting LEDs directly to the DP83TC811R-Q1.

Pull-Down

VDDIO

Strap Pin

R_CL

D1

R_P

D1

R_CL

Pull-Up

Strap Pin

图 28. Example Strap Connections

8.5.3 PHY Address Configuration

The DP83TC811R-Q1 can be set to respond to any of 16 possible PHY addresses through bootstrap pins. The

PHY address is latched into the device upon power-up or hardware reset. Each DP83TC811R-Q1 or port sharing

PHY on the serial management bus in the system must have a unique PHY address. The DP83TC811R-Q1

supports PHY address strapping values 0 (<0b00000>) through 15 (<0b01111>).

By default, the DP83TC811R-Q1 will latch to a PHY address of 0 (<0b00000>). This address can be changed by

adding pullup resistors to bootstrap pins found in 表 18.

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8.6 Register Maps

In the register definitions under the ‘TYPE’ heading, the following definitions apply:

COR

Strap

LH

Clear on read

Default value loaded from bootstrap pin after reset

Latched high and held until read

Latched low and held until read

Read only access

LL

RO

RW

SC

Read write access

Register sets on event occurrence and self-clears when event ends

8.6.1 Register Access Summary

There are two different methods for accessing registers within the field. Direct register access method is only

allowed for the first 31 registers (0x0 through 0x1F). Registers beyond 0x1F must be accessed by use of the

Indirect Method (Extended Register Space) described in Extended Register Space Access.

表 24. Register Access Summary

REGISTER FIELD

REGISTER ACCESS METHODS

Direct Access

Indirect Access, MMD1F = '11111'

Example: to read register 0x17 in MMD1F field with no post increment

Step 1) write 0x1F to register 0xD

0x0 through 0x1F

Step 2) write 0x17 to register 0xE

Step 3) write 0x401F to register 0xD

Step 4) read register 0xE

Indirect Access, MMD1F = '11111'

Example: to read register 0x462 in MMD1F field with no post increment

Step 1) write 0x1F to register 0xD

Step 2) write 0x462 to register 0xE

MMD1F Field

0x20 - 0xFFF

Step 3) write 0x401F to register 0xD

Step 4) read register 0xE

Indirect Access, MMD1 = '00001'

Example: to read register 0x7 in MMD1 field with no post increment

Step 1) write 0x1 to register 0xD

Step 2) write 0x7 to register 0xE

MMD1 Field

0x0 - 0xFFF

Step 3) write 0x4001 to register 0xD

Step 4) read register 0xE

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8.6.2 BMCR Register 0x0000 – Basic Mode Control Register

图 29. Basic Mode Control Register (BMCR)

15

14

13

Speed

Selection

12

Auto-

Negotiation

Enable

11

IEEE Power

10

Isolate

9

1

8

0

Reset

xMII Loopback

Reserved

RO-01

Down

RW/SC-0

7

RW-0

6

RO-1

5

RO-0

4

RW-0

3

RW-0

2

Reserved

RO-0

表 25. BMCR Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15

Reset

RW, SC

0

PHY Software Reset:

1 = Initiate software Reset / Reset in Progress

0 = Normal Operation

Writing a 1 to this bit resets the PHY PCS registers. When the

reset operation is done, this bit is cleared to 0 automatically.

PHY Vendor Specific registers will not be cleared.

14

xMII Loopback

RW

0

xMII Loopback:

1 = xMII Loopback enabled

0 = Normal Operation

When xMII loopback mode is activated, the transmitted data

presented on xMII TXD is looped back to xMII RXD internally.

There is no LINK indication generated when xMII loopback is

enabled.

13

12

11

Speed Selection

RO

RW

1

0

Speed Selection: Always 100-Mbps Speed

Auto-Negotiation: Not supported

Auto-Negotiation Enable

IEEE Power Down

Power Down:

1 = IEEE Power Down

0 = Normal Operation

The PHY is powered down after this bit is set. Only register

access is enabled during this power down condition. To control

the power down mechanism, this bit is OR'ed with the input from

the INT/PWDN_N pin. When the active low INT/PWDN_N is

asserted, this bit is set.

10

Isolate

RW

RO

0

Isolate:

1 = Isolates the port from the xMII with the exception of the

serial management interface

0 = Normal Operation

9:0

Reserved

01 0000

0000

Reserved

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8.6.3 BMSR Register 0x0001 – Basic Mode Status Register

图 30. Basic Mode Status Register (BMSR)

15

14

13

12

11

10

9

8

0

100Base-T4

100Base-TX

Full-Duplex

100Base-TX

Half-Duplex

10Base-T Full- 10Base-T Half-

Reserved

Duplex

RO-0

Duplex

RO-0

7

RO-0

6

RO-0

5

RO-0

4

3

2

1

SMI Preamble

Suppression

Auto-

Negotiation

Complete

Remote Fault

Auto-

Negotiation

Ability

Link Status

Jabber Detect

Extended

Capability

RO-1

RO/LH-0

RO-0

RO/LL-1

RO/LH-1

RO-1

表 26. BMSR Field Descriptions

BIT

FIELD

100Base-T4

TYPE

DEFAULT DESCRIPTION

15

RO

0

100Base-T4 Capable:

This protocol is not available. Always reads as 0.

14

13

12

11

100Base-TX Full-Duplex

100Base-TX Half-Duplex

10Base-T Full-Duplex

10Base-T Half-Duplex

RO

0

100Base-TX Full-Duplex Capable:

1 = Device able to perform Full-Duplex 100Base-TX

0 = Device not able to perform Full-Duplex 100Base-TX

0

100Base-TX Half-Duplex Capable:

1 = Device able to perform Half-Duplex 100Base-TX

0 = Device not able to perform Half-Duplex 100Base-TX

10Base-T Full-Duplex Capable:

1 = Device able to perform Full-Duplex 10Base-T

0 = Device not able to perform Full-Duplex 10Base-T

10Base-T Half-Duplex Capable:

1 = Device able to perform Half-Duplex 10Base-T

0 = Device not able to perform Half-Duplex 10Base-T

10:7

6

Reserved

RO

0

1

Reserved

SMI Preamble Suppression

Preamble Suppression Capable:

1 = Device able to perform management transaction with

preamble suppressed

0 = Device not able to perform management transaction with

preambles suppressed

If this bit is set to 1, 32-bits of preamble needed only once after

reset, invalid opcode or invalid turnaround.

5

4

Auto-Negotiation Complete

Remote Fault

RO

1

0

Auto-Negotiation Complete:

1 = Auto-Negotiation process completed

0 = Auto Negotiation process not completed (either still in

process, disabled or reset)

RO, LH

Remote Fault:

1 = Remote fault condition detected

0 = No remote fault condition detected

Far End Fault indication or notification from Link Partner of

Remote Fault. This bit is cleared on read or reset.

3

2

Auto-Negotiation Ability

Link Status

RO

0

Auto-Negotiation Ability:

1 = Device is able to perform Auto-Negotiation

0 = Device is not able to perform Auto-Negotiation

RO, LL

Link Status:

1 = Valid link established (for either 10-Mbps or 100-Mbps

operation)

0 = Link not established

1

0

Jabber Detect

RO, LH

RO

0

1

Jabber Detect:

1 = Jabber condition detected

0 = No jabber condition detected

Extended Capability

Extended Capability:

1 = Extended register capabilities

0 = Basic register set capabilities only

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8.6.4 PHYID1 Register 0x0002 – PHY Identifier Register #1

图 31. PHY Identifier Register #1 (PHYID1)

15

7

14

6

13

5

12

11

10

9

1

8

0

Organizationally Unique Identifier Bits 21:6

RO-0010 0000

4

3

2

Organizationally Unique Identifier Bits 21:6

RO-0010 0000

表 27. PHYID1 Field Descriptions

BIT

15:0

FIELD

TYPE

DEFAULT DESCRIPTION

Organizationally Unique Identifier

Bits 21:6

RO

0010

0000

8.6.5 PHYID2 Register 0x0003 – PHY Identifier Register #2

图 32. PHY Identifier Register #2 (PHYID2)

15

14

13

12

11

10

9

1

8

0

Organizationally Unique Identifier Bits 5:0

RO-1010 00

Model Number

RO-10 0101

7

6

5

4

3

2

Revision Number

RO-0011

表 28. PHYID2 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:10

Organizationally Unique Identifier

Bits 5:0

RO

1010 00

9:4

Model Number

RO

10 0101

0011

Vendor Model Number:

The six bits of vendor model number are mapped from bits 9 to

4

3:0

Revision Number

Model Revision Number:

Four bits of the vendor model revision number are mapped from

bits 3 to 0. This field is incremented for all major device

changes.

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8.6.6 TDR_AUTO Register 0x0009 – TDR Auto-Run Register

图 33. TDR Auto-Run Register (TDR_AUTO)

15

7

14

6

13

5

12

11

3

10

9

1

8

Reserved

RW-0010 000

TDR Auto-Run

RW-0

4

2

0

Reserved

RW-0

表 29. TDR_AUTO Field Descriptions

BIT

FIELD

TYPE

RW

DEFAULT DESCRIPTION

15:9

8

Reserved

0010 000 Reserved

TDR Auto-Run

RW

0

TDR Auto-Run:

1 = TDR will automatically run when link is lost

0 = TDR auto-run disabled

7:0

Reserved

RW

0

Reserved

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8.6.7 REGCR Register 0x000D – Register Control Register

图 34. Register Control Register (REGCR)

15

14

13

5

12

4

11

3

10

9

1

8

0

Extended Register Command

RW-0

Reserved

RO-0

7

6

2

DEVAD

RW-0

表 30. REGCR Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:14

Extended Register Command

RW

0

Extended Register Command:

00 = Address

01 = Data, no post increment

10 = Data, post increment on read and write

11 = Data, post increment on write only

13:5

4:0

Reserved

DEVAD

RO

0

Reserved

RW

Device Address: Bits[4:0] are the device address, DEVAD, that

directs any accesses of ADDAR Register 0x000E –

Address/Data Register to the appropriate MMD. Specifically, the

DP83TC811R-Q1 uses the vendor specific DEVAD [4:0] =

"11111" for accesses to registers 0x04D1 and lower. For MMD1

access, the DEVAD[4:0] = '00001'. All accesses through

registers REGCR and ADDAR should use the DEVAD for either

MMD or MMD1. Transactions with other DEVAD are ignored.

8.6.8 ADDAR Register 0x000E – Address/Data Register

图 35. Address/Data Register (ADDAR)

15

14

13

12

11

10

9

1

8

0

Address/Data

RW-0

7

6

5

4

3

2

Address/Data

RW-0

表 31. ADDAR Field Descriptions

BIT

15:0

FIELD

Address/Data

TYPE

DEFAULT DESCRIPTION

RW

0

If REGCR register 15:14 = '00', holds the MMD DEVAD's

address register, otherwise holds the MMD DEVAD's data.

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8.6.9 INT_TEST Register 0x0011 – Interrupt Test Register

图 36. Interrupt Test Register (INT_TEST)

15

7

14

6

13

5

12

11

10

9

1

8

0

Reserved

RW-0000 0001 0000

4

3

2

Interrupt

Polarity

Test Interrupt

Reserved

RW-11

RW-1

RW-0

表 32. INT_TEST Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:4

Reserved

RW

0000 0001 Reserved

0000

3

Interrupt Polarity

RW

1

0

Interrupt Polarity:

1 = Steady state (normal operation) without an interrupt is logical

1; during interrupt, pin is logical 0

0 = Steady state (normal operation) without an interrupt is logical

0; during interrupt, pin is logical 1

2

Test Interrupt

Test Interrupt:

1 = Generate an interrupt

0 = Do not generate interrupt

Forces the PHY to generate an interrupt to facilitate interrupt

testing. Interrupts will continue to be generated as long as this

bit remains set.

1:0

Reserved

RW

11

Reserved

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8.6.10 INT_STAT1 Register 0x0012 – Interrupt Status Register #1

图 37. Interrupt Status Register #1 (INT_STAT1)

15

14

13

12

11

10

9

8

Link Quality

Interrupt

Energy Detect

Interrupt

Link Status

Changed

Interrupt

WoL Interrupt

ESD Event

Interrupt

100BASE-T1

Master /

100BASE-T1

Slave Training

Complete

False Carrier

Counter Half-

Full Interrupt

Receive Error

Counter Half-

Full Interrupt

Interrupt

RO/LH-0

7

RO/LH-0

6

RO/LH-0

5

RO/LH-0

4

RO/LH-0

3

RO/LH-0

2

RO/LH-0

1

RO/LH-0

0

Link Quality

Interrupt

Enable

Energy Detect

Interrupt

Link Status

Changed

Enable

WoL Interrupt

Enable

ESD Event

Interrupt

MS Training

Complete

Interrupt

False Carrier

HF Enable

Receive Error

HF Enable

Enable

RW-0

表 33. INT_STAT1 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15

Link Quality Interrupt

Energy Detect Interrupt

Link Status Changed Interrupt

WoL Interrupt

RO, LH

0

Change of Link Quality Status Interrupt:

1 = Change of link quality when link is ON

0 = Link quality is Good

14

13

12

11

10

RO, LH

Change of Energy Detection Status Interrupt:

1 = Change of energy detected

0 = No change of energy detected

Change of Link Status Interrupt:

1 = Change of link status interrupt is pending

0 = No change of link status

Detection of WoL Frame Interrupt:

1 = WoL interrupt is pending

0 = No WoL frame detected

ESD Event Interrupt

ESD Interrupt:

1 = ESD event detected

0 = No ESD events detected

100BASE-T1 Master / 100BASE-T1 RO, LH

Slave Training Complete Interrupt

100BASE-T1 Master and 100BASE-T1 Slave Training

Complete Interrupt:

1 = 100BASE-T1 Master and 100BASE-T1 Slave Training

complete interrupt is pending

0 = MS Training is not pending

9

8

False Carrier Counter Half-Full

Interrupt

RO, LH

0

False Carrier Counter Half-Full Interrupt:

1 = False Carrier counter (FCSCR Register 0x0014 – False

Carrier Sense Counter Register) exceeds half-full interrupt is

pending

0 = False Carrier half-full event is not pending

Receive Error Counter Half-Full

Interrupt

Receiver Error Counter Half-Full Interrupt:

1 = Receive Error counter (RECR Register 0x0015 – Receive

Error Count Register) exceeds half-full interrupt is pending

0 = Receive Error half-full event is not pending

7

6

5

4

3

2

Link Quality Interrupt Enable

Energy Detect Interrupt Enable

Link Status Changed Enable

WoL Interrupt Enable

RW

0

Enable interrupt on change of link quality

Enable interrupt on change of energy detection

Enable interrupt on change of link status

Enable Interrupt on WoL frame detection

Enable Interrupt on ESD event detection

ESD Event Interrupt

MS Training Complete Interrupt

Enable Interrupt on 100BASE-T1 Master and 100BASE-T1

Slave Training Completion

1

0

False Carrier HF Enable

Receive Error HF Enable

RW

0

Enable Interrupt on False Carrier Counter Register half-full

event

Enable Interrupt on Receive Error Counter Register half-full

event

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8.6.11 INT_STAT2 Register 0x0013 – Interrupt Status Register #2

图 38. Interrupt Status Register #2 (INT_STAT2)

15

14

13

12

11

10

9

8

Undervoltage

Interrupt

Overvoltage

Interrupt

Reserved

Overtemperatur

e Interrupt

Sleep Mode

Interrupt

Polarity

Change

Interrupt

Jabber Detect

Interrupt

RO/LH-0

7

RO/LH-0

6

RO/LH-0

Reserved

RO/LH-0

3

RO/LH-0

2

RO/LH-0

1

RO/LH-0

0

5

4

Undervoltage

Interrupt

Overvoltage

Interrupt

Enable

Overtemperatur

e Interrupt

Enable

Sleep Mode

Event Enable

Polarity

Change

Interrupt

Enable

Jabber Detect

Interrupt

Enable

RW-0

RO-0

RW-0

表 34. INT_STAT2 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15

Undervoltage Interrupt

RO, LH

0

Undervoltage Interrupt:

1 = Undervoltage event interrupt pending

0 = No undervoltage event pending

14

Overvoltage Interrupt

RO, LH

0

Overvoltage Interrupt:

1 = Overvoltage event interrupt pending

0 = No overvoltage event pending

13:12

11

Reserved

RO, LH

0

Reserved

Overtemperature Interrupt

Overtemperature Interrupt:

1 = Overtemperature event interrupt pending

0 = No overtemperature event pending

10

9

Sleep Mode Interrupt

Polarity Change Interrupt

Jabber Detect Interrupt

RO, LH

0

Sleep Mode Interrupt:

1 = Sleep mode event interrupt is pending

0 = No Sleep mode event pending

Polarity Change Interrupt:

1 = Data polarity change interrupt pending

0 = No Data polarity even pending

8

Jabber Detect Interrupt:

1 = Jabber detect event interrupt pending

0 = No Jabber detect event pending

7

6

Undervoltage Interrupt Enable

Overvoltage Interrupt Enable

Reserved

RW

RO

RW

0

Enable interrupt on undervoltage event

Enable interrupt on overvoltage event

Reserved

5 :4

3

Overtemperature Interrupt Enable

Sleep Mode Event Enable

Polarity Change Interrupt Enable

Jabber Detect Interrupt Enable

Enable interrupt on overtemperature event

Enable Interrupt on sleep mode event

Enable Interrupt on change of polarity status

Enable Interrupt on Jabber detection event

2

1

0

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8.6.12 FCSCR Register 0x0014 – False Carrier Sense Counter Register

图 39. False Carrier Sense Counter Register (FCSCR)

15

7

14

6

13

5

12

4

11

3

10

9

1

8

0

Reserved

RO-0

2

False Carrier Event Counter

RO/COR-0

表 35. FCSCR Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

7:0

Reserved

RO

0

Reserved

False Carrier Event Counter:

False Carrier Event Counter

RO,

COR

This 8-bit counter increments on every false carrier event. This

counter stops when it reaches its maximum count (0xFF). When

the counter exceeds half-full (0x7F), an interrupt event is

generated. This register is cleared on read.

8.6.13 RECR Register 0x0015 – Receive Error Count Register

图 40. Receive Error Count Register (RECR)

15

14

13

12

11

10

9

1

8

0

Receive Error Counter

RO/COR-0

7

6

5

4

3

2

Receive Error Counter

RO/COR-0

表 36. RECR Field Descriptions

BIT

15:0

FIELD

Receive Error Counter

TYPE

DEFAULT DESCRIPTION

RO,

0 RX_ER Counter:

COR

When a valid carrier is presented (only while RX_DV is set), and

there is at least one occurrence of an invalid data symbol, this

16-bit counter increments for each receive error detected. The

RX_ER counter does not count in xMII loopback mode. The

counter stops when it reaches its maximum count (0xFFFF).

When the counter exceeds half-full (0x7FFF), an interrupt is

generated. This register is cleared on read.

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8.6.14 BISTCR Register 0x0016 – BIST Control Register

图 41. BIST Control Register (BISTCR)

15

14

13

12

11

10

9

8

Reserved

BIST Error

Counter Mode

PRBS Packet

Type

Packet

Generation

Enable

PRBS Checker PRBS Checker

Packet

Generator

Status

Reserved

Lock/Sync

Sync Loss

RO-0

7

RW-0

6

RW-0

5

RW-0

RO-0

3

RO/LH-0

2

RO-0

1

RO-10

0

4

Loopback Select

RW-0

Reserved

RW-0

表 37. BISTCR Field Descriptions

BIT

15

FIELD

TYPE

RO

DEFAULT DESCRIPTION

Reserved

0

Reserved

14

BIST Error Counter Mode

RW

BIST Error Counter Mode:

1 = Continuous mode, when the BIST Error counter reaches its

max value, a pulse is generated and the counter starts counting

from zero again.

0 = Single mode, when BIST Error Counter reaches its max

value, PRBS checker stops counting.

13

PRBS Packet Type

RW

0

PRBS Packet Type:

1 = When packet generator is enabled (Bit[12] = '1'), generate

continuous packets with PRBS data. When packet generator is

disabled, PRBS checker is still enabled.

0 = When packet generator is enabled, generate single packet

with constant data. PRBS gen/check is disabled.

12

11

10

9

Packet Generation Enable

PRBS Checker Lock/Sync

PRBS Checker Sync Loss

Packet Generator Status

RW

0

Packet Generation Enable:

1 = Enable packet generator with PRBS data

0 = Disable packet generator

RO

PRBS Checker Lock/Sync Indication:

1 = PRBS checker is locked and synced on received bit stream

0 = PRBS checker is not locked

RO, LH

RO

PRBS Checker Sync Loss Indication:

1 = PRBS checker has lost sync

0 = PRBS checker has not lost sync

Packet Generation Status Indication:

1 = Packet Generator is active and generating packets

0 = Packet Generator is off

8:7

6:2

Reserved

RO

10

0

Reserved

Loopback Select

RW

Loopback Select:

Bits[5:2]

0000 = Normal operation

0001 = PCS Loopback

0010 = Analog Loopback

0100 = Reverse Loopback

1000 = Reserved

Bit[6]:

1 = Transmit data to the MDI in xMII Loopback

0 = Surpress data to the MDI in xMII Loopback

Note: Bit[6] can only can be set in xMII Loopback

1:0

Reserved

RW

0

Reserved

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8.6.15 xMII_CTRL Register 0x0017 – xMII Control Register

图 42. xMII Control Register (xMII_CTRL)

15

14

13

12

11

10

9

8

Reserved

RGMII RX

Clock Internal

Delay

RGMII TX

Clock Internal

Delay

Reserved

RGMII Mode

Reserved

RW-010

RW/Strap

4

RW/Strap

3

RW-0

2

RW/Strap

1

RW-0

0

7

6

5

Clock Select

Reserved

RMII Mode

RMII Revision

Select

RMII Overflow RMII Underflow

RMII Receive Elasticity Buffer

Size

Status

RW/Strap

RW-1

RW/Strap

RW-0

RO/COR-0

RW-01

表 38. xMII_CTRL Field Descriptions

BIT

15:13

12

FIELD

TYPE

RW

DEFAULT

010

DESCRIPTION

Reserved

RGMII RX Clock Internal

Delay

RW

Strap

RGMII RX Clock Internal Delay:

1 = Receive path internal clock delay is enabled

0 = Receive path internal clock delay is disabled

Note: When enabled, receive path internal clock (RX_CLK) is

delayed by 2ns relative to receive data. When disabled, data

and clock are in align mode.

11

RGMII TX Clock Internal

Delay

RW

Strap

RGMII TX Clock Internal Delay:

1 = Transmit path internal clock delay is enabled

0 = Transmit path internal clock delay is disabled

Note: When enabled, transmit path internal clock (TX_CLK) is

delayed by 2ns relative to transmit data. When disabled, data

and clock are in align mode.

10

9

Reserved

RW

0

Reserved

RGMII Mode

Strap

RGMII Mode Enable:

1 = Enable RGMII mode of operation

0 = Mode determined by Bit[5]

8

7

Reserved

RW

0

Reserved

Clock Select

Strap

Reference Clock Select:

Strap determines the clock reference requirement.

1 = 50-MHz clock reference, CMOS-level oscillator

0 = 25-MHz clock reference, crystal or CMOS-level oscillator

6

5

Reserved

RW

1

Reserved

RMII Mode

Strap

RMII Mode Enable:

1 = Enable RMII mode of operation

0 = Enable MII mode of operation

4

RMII Revision Select

RW

0

RMII Revision Select:

1 = RMII Revision 1.0

0 = RMII Revision 1.2

RMII revision 1.0, CRS_DV will remain asserted until final data

is transferred. CRS_DV will not toggle at the end of a packet.

RMII revision 1.2, CRS_DV will toggle at the end of a packet to

indicate de-assertion of CRS.

3

2

RMII Overflow Status

RMII Underflow Status

RO,

COR

0

RX FIFO Overflow Status:

1 = Normal

0 = Overflow detected

RO,

COR

RX FIFO Underflow Status:

1 = Normal

0 = Underflow detected

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表 38. xMII_CTRL Field Descriptions (接下页)

BIT

FIELD

TYPE

DEFAULT

DESCRIPTION

1:0

RMII Receive Elasticity

Buffer Size

RW

01

Receive Elasticity Buffer Size:

This field controls the Receive Elasticity Buffer which allows for

frequency variation tolerance between the 50-MHz RMII clock

and the recovered data. The following values indicate the

tolerance in bits for a single packet. The minimum setting allows

for standard Ethernet frame sizes at ±100ppm accuracy.

00 = 5-bit tolerance (up to 8750 byte packets)

01 = 2-bit tolerance (up to 1250 byte packets)

10 = 3-bit tolerance (up to 3750 byte packets)

11 = 4-bit tolerance (up to 6250 byte packets)

8.6.16 INT_STAT3 Register 0x0018 – Interrupt Status Register #3

图 43. Interrupt Status Register #3 (INT_STAT3)

15

14

13

12

11

10

9

1

8

Reserved

POR Done

Interrupt

No Frame

Detected

Interrupt

Reserved

LPS Interrupt

RO-0

RO/LH-0

4

RO/LH-0

3

RO/LH-0

Reserved

RO/LH-0

0

7

6

5

2

Reserved

POR Done

Interrupt

Enable

No Frame

Detected

Interrupt

Enable

LPS Interrupt

Enable

RO-0

RW-1

RW-0

表 39. INT_STAT3 Field Descriptions

BIT

FIELD

TYPE

RO

DEFAULT DESCRIPTION

15:13

12

Reserved

0

Reserved

POR Done Interrupt:

POR Done Interrupt

RO, LH

1 = POR done event pending

0 = No POR done event pending

11

No Frame Detected Interrupt

RO, LH

0

No Frame Detection Interrupt:

1 = No Frame Detection event interrupt pending

0 = No event pending

10:9

8

Reserved

RO, LH

0

Reserved

LPS Interrupt

LPS Interrupt:

1 = LPS event interrupt is pending

0 = No LPS event pending

7:5

4

Reserved

RO

0

1

0

Reserved

POR Done Interrupt Enable

RW

Enable interrupt on POR Done event.

Enable interrupt on No Frame Detection event

Reserved

3

No Frame Detected Interrupt Enable RW

2:1

0

Reserved

RW

LPS Interrupt Enable

Enable interrupt on LPS event

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8.6.17 BICTSR1 Register 0x001B – BIST Control and Status Register #1

图 44. BIST Control and Status Register #1 (BICTSR1)

15

7

14

6

13

5

12

BIST Error Count

RW-0

11

10

2

9

1

8

0

4

3

BIST IPG Length

RW-0111 1101

表 40. BICTSR1 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

BIST Error Count

RO

0 BIST Error Count:

Holds number of errored bytes received by the PRBS checker.

Value in this register is locked and cleared when write is done to

Bit[15]. When BIST Error Counter Mode is set to '0', count stops

on 0xFF (see register 0x16)

Note: Writing '1' to Bit[15] will lock the counter's value for

successive read operation and clear the BIST Error Counter.

7:0

BIST IPG Length

RW

0111 1101 BIST IPG Length:

Inter Packet Gap (IPG) Length defines the size of the gap (in 4

byte increments) between any 2 successive packets generated

by the BIST.

Default value is 0x7D:

0x7D to decimal conversion = 125

125 * 4 bytes = 500 bytes (default)

8.6.18 BICTSR2 Register 0x001C – BIST Control and Status Register #2

图 45. BIST Control and Status Register #2 (BICTSR2)

15

7

14

6

13

12

11

10

2

9

8

0

Reserved

RO-0

BIST Packet Length

RW-101 1110 1110

5

4

3

1

BIST Packet Length

RW-101 1110 1110

表 41. BICTSR2 Field Description

BIT

FIELD

TYPE

RO

DEFAULT DESCRIPTION

Reserved

101 1110 BIST Packet Length:

15:11

10:0

Reserved

0

BIST Packet Length

RW

1110

Length of the generated BIST packets. The value of this register

defines the size (in bytes) of every packet that is generated by

the BIST. Default value is 0x5EE, which is equal to 1514 bytes.

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8.6.19 TDR Register 0x001E – Time Domain Reflectometry Register

图 46. Time Domain Reflectometry Register (TDR)

15

14

6

13

5

12

4

11

10

9

8

TDR Start

RW/SC-0

Reserved

RO-0

7

3

2

1

0

TDR Status

RO-0

TDR Test Fail

RO-0

表 42. TDR Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15

TDR Start

RW, SC

0

TDR Start:

1 = Start cable measurement

0 = Cable Diagnostic is disabled

14:2

1

Reserved

RO

0

Reserved

TDR Status

TDR Done:

1 = Indication that cable measurement process is complete

0 = Cable Diagnostic had not completed

0

TDR Test Fail

RO

0

TDR Process Fail:

1 = Indication that cable measurement process failed

0 = Cable Diagnostic has not failed

8.6.20 PHYRCR Register 0x001F – PHY Reset Control Register

图 47. PHY Reset Control Register (PHYRCR)

15

14

13

12

11

10

9

1

8

0

Hardware

Reset

Software reset

Reserved

RW-0

RW/SC-0

6

7

5

4

3

2

Standby Mode

RW-0

Reserved

RW-0

表 43. PHYRCR Field Descriptions

BIT

FIELD

Hardware Reset

TYPE

DEFAULT DESCRIPTION

15

RW, SC

0

Hardware Reset:

1 = Reset PHY. This bit is self cleared and has the same effect

as the RESET pin.

0 = Normal Operation

14

Software reset

RW, SC

0

Software Restart:

1 = Restart PHY. This bit is self cleared and resets all PHY

circuitry except registers.

0 = Normal Operation

13:8

7

Reserved

RW

0

Reserved

Standby Mode

Standby Mode:

1 = Standby mode enabled

0 = Normal operation

6:0

Reserved

RW

0

Reserved

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8.6.21 LSR Register 0x0133 – Link Status Results Register

图 48. Link Status Results Register (LSR)

15

7

14

13

5

12

11

3

10

9

8

0

Reserved

RO-0

Link Status

RO-0

Reserved

RO-0101 1110 0

6

4

2

1

Scrambler Lock Local Receiver

Status

Remote

Receiver Status

RO-0

表 44. LSR Field Descriptions

BIT

FIELD

TYPE

RO

DEFAULT DESCRIPTION

15:13

12

Reserved

0

Reserved

Link Status

RO

Unlatched Link Status:

1 = Valid Link Established

0 = No Link

11:3

2

Reserved

RO

0101 1110 Reserved

0

Scrambler Lock

0

Scrambler Lock:

1 = Scrambler Locked

0 = Scrambler Not Locked

1

0

Local Receiver Status

RO

Local Receiver Status:

1 = Local PHY received link valid

0 = Local PHY received link invalid

Remote Receiver Status

Remote Receiver Status:

1 = Remote PHY received link valid

0 = Remote PHY received link invalid

8.6.22 TDRR Register 0x016B – TDR Results Register

图 49. TDR Results Register (TCRR)

15

14

13

12

11

10

2

9

8

Reserved

RO-0

Fault Status

RO-0

Fault Type

RO-0

7

6

5

4

3

1

0

Fault Location

RO-0

表 45. TDRR Field Descriptions

BIT

FIELD

TYPE

RO

DEFAULT DESCRIPTION

15:10

9

Reserved

0

Reserved

Fault Status

RO

Fault Status:

1 = Fault Detected

0 = No Fault Detected

8

Fault Type

RO

0

Fault Type:

1 = SHORT Fault

0 = OPEN Fault

Note: Only valid when bit[9] = 1.

7:0

Fault Location

Fault Location:

To calculate fault location in meters, convert binary field to

decimal form and multiply by 1.5.

Note: Only valid when bit[9] = 1.

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8.6.23 TDRLR1 Register 0x0180 – TDR Location Result Register #1

图 50. TDR Location Result Register #1 (TDRLR1)

15

7

14

6

13

5

12

4

11

3

10

9

1

8

0

Location 2

RO-0

2

Location 1

RO-0

表 46. TDRLR1 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Location 2

RO

0

Location of the Second peak discovered by the TDR

mechanism.

Distance in meters = 1.5 * (convert bit field to decimal - 4)

7:0

Location 1

RO

0

Location of the First peak discovered by the TDR mechanism.

Distance in meters = 1.5 * (convert bit field to decimal - 4)

8.6.24 TDRLR2 Register 0x0181 – TDR Location Result Register #2

图 51. TDR Location Result Register #2

15

7

14

6

13

5

12

4

11

3

10

9

1

8

0

Location 4

RO-0

2

Location 3

RO-0

表 47. TDRLR2 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Location 4

RO

0

Location of the Fourth peak discovered by the TDR mechanism.

Distance in meters = 1.5 * (convert bit field to decimal - 4)

7:0

Location 3

RO

0

Location of the Third peak discovered by the TDR mechanism.

Distance in meters = 1.5 * (convert bit field to decimal - 4)

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8.6.25 TDRPT Register 0x018A – TDR Peak Type Register

图 52. TDR Peak Type Register (TDRPT)

15

14

13

12

11

10

9

8

0

Reserved

RO-0

Peak 4 Type

RO-0

Peak 3 Type

RO-0

Peak 2 Type

RO-0

Peak 1 Type

RO-0

Reserved

RO-0

7

6

5

4

3

2

1

Reserved

RO-0

表 48. TDRPT Field Descriptions

BIT

15

FIELD

TYPE

RO

DEFAULT DESCRIPTION

Reserved

0

Reserved

14

Peak 4 Type

RO

Peak 4 Polarity Detection:

1 = Negative Polarity

0 = Positive Polarity

Negative polarity detection can be caused by a SHORT.

Positive polarity detection can be caused by an OPEN.

Note:only valid when bits[15:8] in register 0x181 is not zero.

13

12

Peak 3 Type

Peak 2 Type

Peak 1 Type

Reserved

RO

0

Peak 3 Polarity Detection:

1 = Negative Polarity

0 = Positive Polarity

Negative polarity detection can be caused by a SHORT.

Positive polarity detection can be caused by an OPEN.

Note:only valid when bits[7:0] in register 0x181 is not zero.

Peak 2 Polarity Detection:

1 = Negative Polarity

0 = Positive Polarity

Negative polarity detection can be caused by a SHORT.

Positive polarity detection can be caused by an OPEN.

Note:only valid when bits[15:8] in register 0x180 is not zero.

11

Peak 1 Polarity Detection:

1 = Negative Polarity

0 = Positive Polarity

Negative polarity detection can be caused by a SHORT.

Positive polarity detection can be caused by an OPEN.

Note:only valid when bits[7:0] in register 0x180 is not zero.

10:0

Reserved

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8.6.26 AUTO_PHY Register 0x018B – Autonomous PHY Control Register

图 53. Autonomous PHY Control Register (AUTO_PHY)

15

7

14

13

5

12

4

11

3

10

2

9

8

0

Reserved

RW-0

6

1

Autonomous

Command

Reserved

Sleep Enable

LPS

Transmission

Enable

RW/COR/Strap

RW-01 10

RW-1

RW-0

表 49. AUTO_PHY Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:7

6

Reserved

RW

0

Reserved

Autonomous Command:

Autonomous Command

RW,

Strap

COR

1 = Device in Autonomous operation

0 = Device in Managed operation

Note: This bit is a one-time event. Once written to or read, the

bit will always read 0b0. Managed mode can only be entered at

power-up or reset when the bootstrap is sampled.

5:2

1

Reserved

RW

01 10

1

Reserved

Sleep Enable

Sleep Enable:

1 = Sleep enabled

0 = Standby enabled

The device will transition to Sleep state after negotiating with a

Link Partner if this bit is set. Otherwise, once LPS negotiation is

complete, the device will transition to Standby.

0

LPS Transmission Enable

RW

0

LPS Transmission Enable:

1 = Device allowed to send LPS code-groups

0 = No LPS code-groups enabled

Device is only allowed to send LPS code-groups when this bit is

set.

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8.6.27 PWRM Register 0x018C – Power Mode Register

图 54. Power Mode Register (PWRM)

15

7

14

6

13

5

12

4

11

10

2

9

1

8

0

Reserved

RW-0

3

Reserved

RW-0

Sleep Request

Command

Normal

Command

RW-0

RW/SC-0

表 50. PWRM Register 0x018C – Power Mode Register

BIT

FIELD

TYPE

RW

DEFAULT DESCRIPTION

15:2

1

Reserved

0

Reserved

Sleep Request Command

RW

Sleep Request Command:

1 = Device will transmit LPS code-groups

0 = Normal operation

0

Normal Command

RW, SC

0

Normal Command:

1 = Device forced to Normal state

0 = Normal operation

Self-cleared only when PHY moves from Standby to Normal

state. Bit is not cleared on any other transition.

8.6.28 SNR Register 0x0197 – Signal-to-Noise Ratio Result Register

图 55. Signal-to-Noise Ratio Result Register (SNR)

15

7

14

6

13

5

12

11

3

10

9

1

8

Reserved

RO-0

SNR

RO-0

4

2

0

SNR

RO-0

表 51. SNR Field Descriptions

BIT

FIELD

Reserved

SNR

TYPE

RO

DEFAULT DESCRIPTION

15:9

8:0

0

Reserved

RO

Signal-to-Noise Ratio:Value contained within bit field contains

10*SNR (dB). To obtain SNR (dB) convert binary value to

decimal form and divide by 10.

Note: Only valid when link is established.

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8.6.29 SQI Register 0x0198 – Signal Quality Indication Register

图 56. Signal Quality Indication Register (SQI)

15

7

14

6

13

5

12

4

11

3

10

9

1

8

0

Reserved

RO-0

SQS

RO-0

2

SQI

RO-0

表 52. SQI Field Descriptions

BIT

FIELD

Reserved

SQS

TYPE

RO

DEFAULT DESCRIPTION

15:10

9:8

0

Reserved

RO

Signal Quality Status:

00 = No Link

01 = Poor Link, Intermittent Link

10 = Good Link quality

11 = Excellent Link quality

7:0

SQI

RO

0

Signal Quality Indication:Value contained within bit field

contains SQI and directly relates to the Signal Quality Status bit

field. Convert binary value to decimal to obtain SQI.

SQI > 70 -- Excellent Link quality

40 < SQI < 70 -- Good Link quality

SQI < 40 -- Intermittent or No Link

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8.6.30 LD_CTRL Register 0x0400 – Line Driver Control Register

图 57. Line Driver Control Register (LD_CTRL)

15

7

14

13

5

12

4

11

3

10

9

1

8

0

Reserved

RW-000

Line Driver Series Termination

RW-1 0000

6

2

Reserved

RW-0000 0000

表 53. LD_CTRL Field Descriptions

BIT

FIELD

Reserved

Line Driver Series Termination

TYPE

RW

DEFAULT DESCRIPTION

15:13

12:8

000

Reserved

RW

1 0000

Line Driver Series Termination Control:

0 0000 = 70 Ω

0 0001 = 67.7 Ω

0 0010 = 65.6 Ω

0 0011 = 63.6 Ω

0 0100 = 61.7 Ω

0 0101 = 60 Ω

0 0110 = 58.3 Ω

0 0111 = 56.7 Ω

0 1000 = 55.2 Ω

0 1001 = 53.8 Ω

0 1010 = 52.5 Ω

0 1011 = 51.2 Ω

0 1100 = 50 Ω

0 1101 = 48.8 Ω

0 1110 = 47.7 Ω

0 1111 = 46.6 Ω

1 0000 = 45.6 Ω (default)

1 0001 = 44.7 Ω

1 0010 = 43.7 Ω

1 0011 = 42.8 Ω

1 0100 = 42 Ω

1 0101 = 41 Ω

1 0110 = 40.4 Ω

1 0111 = 39.6 Ω

1 1000 = 38.9 Ω

1 1001 = 38.2 Ω

1 1010 = 37.5 Ω

1 1011 = 36.8 Ω

1 1100 = 36.2 Ω

1 1101 = 35.6 Ω

1 1110 = 35 Ω

1 1111 = 34.4 Ω

7:0

Reserved

RW

0000 0000 Reserved

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8.6.31 LDG_CTRL1 Register 0x0401 – Line Driver Gain Control Register #1

图 58. Line Driver Gain Control Register (LDG_CTRL1)

15

7

14

6

13

5

12

4

11

3

10

9

1

8

0

Reserved

RW-0

2

Fine Gain Control - MDI

RW-1010

表 54. LDG_CTRL1 Field Descriptions

BIT

FIELD

TYPE

RW

DEFAULT DESCRIPTION

15:4

3:0

Reserved

0

Reserved

Fine Gain Control - MDI

RW

1010

Line Driver Differential Swing Control:

0000 = - 16% change in gain

0001 = - 14% change in gain

0010 = - 12% change in gain

0011 = - 10% change in gain

0100 = - 8% change in gain

0101 = - 6% change in gain

0110 = - 4% change in gain

0111 = - 2% change in gain

1000 = No change in gain

1001 = + 2% change in gain

1010 = + 4% change in gain

1011 = + 6% change in gain

1100 = + 8% change in gain

1101 = + 10% change in gain

1110 = + 12% change in gain

1111 = + 14% change in gain

8.6.32 LDG_CTRL2 Register 0x0402 – Line Driver Control Register #2

图 59. Line Driver Control Register #2 (LDG_CTRL1)

15

7

14

6

13

5

12

11

10

9

1

8

0

Reserved

RW-0000 0011 1000 0

4

3

2

Coarse Gain Control - MDI

RW-011

表 55. LDG_CTRL1 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:3

Reserved

RW

0000 0011 Reserved

1000 0

2:0

Coarse Gain Control - MDI

RW

011

Line Driver Differential Swing Control:

000 = - 60% change in gain

001 = - 40% change in gain

010 = - 20% change in gain

011 = No change in gain

100 = + 20% change in gain

101 = + 40% change in gain

110 = + 60% change in gain

111 = + 80% change in gain

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8.6.33 DLL_CTRL 0x0446 – RGMII DLL Control Register

图 60. RGMII DLL Control Register (DLL_CTRL)

15

7

14

13

12

4

11

10

9

1

8

0

Reserved

RO-0

6

5

3

2

DLL TX Internal Delay Control

RW-0111

DLL RX Internal Delay Control

RW-0111

表 56. DLL_CTRL Field Descriptions

BIT

FIELD

TYPE

RO

DEFAULT DESCRIPTION

15:8

7:4

Reserved

0

Reserved

DLL TX Internal Delay Control

RW

0111

Transmit Internal Delay Control:

Controls the DLL value in 250-ps steps for the transmit path.

Value below is the amount of internal delay on the TX_CLK path

induced.

0000 = 0.25 ns

0001 = 0.50 ns

0010 = 0.75 ns

0011 = 1.00 ns

0100 = 1.25 ns

0101 = 1.50 ns

0110 = 1.75 ns

0111 = 2.00 ns

1000 = 2.25 ns

1001 = 2.50 ns

1010 = 2.75 ns

1011 = 3.00 ns

1100 = 3.25 ns

1101 = 3.50 ns

1110 = 3.75 ns

1111 = 4.00 ns

3:0

DLL RX Internal Delay Control

RW

0111

Receive Internal Delay Control:

Controls the DLL value in 250ps steps for the receive path.

Value below is the amount of internal delay on the RX_CLK path

induced.

0000 = 0.25 ns

0001 = 0.50 ns

0010 = 0.75 ns

0011 = 1.00 ns

0100 = 1.25 ns

0101 = 1.50 ns

0110 = 1.75 ns

0111 = 2.00 ns

1000 = 2.25 ns

1001 = 2.50 ns

1010 = 2.75 ns

1011 = 3.00 ns

1100 = 3.25 ns

1101 = 3.50 ns

1110 = 3.75 ns

1111 = 4.00 ns

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8.6.34 ESDS Register 0x0448 – Electrostatic Discharge Status Register

图 61. Electrostatic Discharge Status Register (ESDS)

15

7

14

6

13

5

12

4

11

10

9

1

8

0

Reserved

RO-0

xMII ESD Event Counter

RO-0

3

2

Reserved

RO-0

MDI ESD Event Counter

RO-0

表 57. ESDS Field Descriptions

BIT

FIELD

TYPE

RO

DEFAULT DESCRIPTION

15:14

13:8

Reserved

0

Reserved

xMII ESD Event Counter

RO

xMII ESD Counter:

When the integrated ESD structure is activated on the xMII

interface, the xMII ESD counter will increment. There is no ESD

dead-time built into the counter, which means that even with a

single pulse event more than one ESD event could be logged.

Counter cleared on power cycle. It cannot be cleared by

hardware reset.

7:6

5:0

Reserved

RO

0

Reserved

MDI ESD Event Counter

MDI ESD Counter:

When the integrated ESD structure is activated on the xMII

interface, the MDI ESD counter will increment. There is no ESD

dead-time built into the counter, which means that even with a

single pulse event more than one ESD event could be logged.

MDI is in reference to the TRD+ and TRD- pins.

Counter cleared on power cycle. It cannot be cleared by

hardware reset.

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8.6.35 LED_CFG1 Register 0x0460 – LED Configuration Register #1

图 62. LED Configuration Register #1 (LED_CFG1)

15

7

14

6

13

12

11

3

10

9

1

8

0

Reserved

RW-0

LED Blink Rate Control

RW-10

LED_2 Control

RW-0110

5

4

2

LED_1 Control

RW-0001

LED_0 Control

RW-0000

表 58. LED_CFG1 Field Descriptions

BIT

FIELD

TYPE

RW

DEFAULT DESCRIPTION

15:14

13:12

Reserved

0

Reserved

LED Blink Rate Control

RW

10

Blink Rate Control:

00 = 20-Hz (50ms)

01 = 10-Hz (100ms)

10 = 5-Hz (200ms)

11 = 2-Hz (500ms)

11:8

7:4

LED_2 Control

LED_1 Control

LED_0 Control

RW

0110

0001

0000

LED_2 Control:

Selects the source for LED_2.

Use same reference as defined by bits [3:0] in this register.

LED_1 Control:

Selects the source for LED_1.

Use same reference as defined by bits [3:0] in this register.

3:0

LED_0 Control:

Selects the source for LED_0.

0000 = LINK OK

0001 = LINK OK + RX/TX Activity

0010 = LINK OK + TX Activity

0011 = LINK OK + RX Activity

0100 = LINK OK + 100BASE-T1 100BASE-T1 Master

0101 = LINK OK + 100BASE-T1 100BASE-T1 Slave

0110 = TX/RX Activity

0111 = Reserved

1000 = Reserved

1001 = Link Lost (remains on until register 0x1 is read)

1010 = Blink for PRBS error (remains ON for single error,

remains until counter is cleared)

1011 = Reserved

1100 = Reserved

1101 = Reserved

1110 = Reserved

1111 = Reserved

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8.6.36 xMII_IMP_CTRL Register 0x0461 – xMII Impedance Control Register

图 63. xMII Impedance Control Register (xMII_IMP_CTRL)

15

7

14

6

13

5

12

11

10

2

9

1

8

Reserved

RW-0000 0100 000

4

3

0

xMII Impedance Control

RW-1 000

Reserved

RW-0

表 59. xMII_IMP_CTRL Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:5

Reserved

RW

0000 0100 Reserved

000

4:1

xMII Impedance Control

RW

1 000

MAC Impedance Control:

MAC Impedance Control sets the series termination value within

the DP83TC811R-Q1. This field controls the following pins:

RX_D[3:0], RX_CLK, RX_ER, and RX_DV.

0 000 = 99 Ω

0 001 = 91 Ω

0 010 = 84 Ω

0 011 = 78 Ω

0 100 = 73 Ω

0 101 = 69 Ω

0 110 = 65 Ω

0 111 = 61 Ω

1 000 = 58 Ω (default)

1 001 = 55 Ω

1 010 = 53 Ω

1 011 = 50 Ω

1 100 = 48 Ω

1 101 = 46 Ω

1 110 = 44 Ω

1 111 = 42 Ω

Note: Individual pin control is not supported.

0

Reserved

RW

0

Reserved

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8.6.37 IO_CTRL1 Register 0x0462 – GPIO Control Register #1

图 64. GPIO Control Register #1 (IO_CTRL1)

15

14

6

13

12

11

10

9

8

0

Reserved

RO-0

LED_1 Clock Select

RW-000

Reserved

RO-0

LED_1 GPIO Select

RW-000

7

5

4

3

2

1

Reserved

RO-0

LED_0 Clock Select

RW-000

Reserved

RO-0

LED_0 GPIO Select

RW-000

表 60. IO_CTRL1 Field Descriptions

BIT

15

FIELD

Reserved

TYPE

RO

DEFAULT DESCRIPTION

0

Reserved

14:12

LED_1 Clock Select

RW

000

LED_1 Clock Select:

000 = XI Clock

001 = TX_TCLK Clock

11

Reserved

RO

0

Reserved

10:8

LED_1 GPIO Select

RW

000

LED_1 GPIO Select:

000 = LED_1

001 = Clock

010 = WoL

011 = Undervoltage Indication

100 = 1588 Transmit

101 = 1588 Receive

110 = Constant '0'

111 = Constant '1'

7

Reserved

RO

0

Reserved

6:4

LED_0 Clock Select

RW

000

LED_0 Clock Select:

000 = XI Clock

001 = TX_TCLK Clock

3

Reserved

RO

0

Reserved

2:0

LED_0 GPIO Select

RW

000

LED_0 GPIO Select:

000 = LED_0

001 = Clock

010 = WoL

011 = Undervoltage Indication

100 = 1588 Transmit

101 = 1588 Receive

110 = Constant '0'

111 = Constant '1'

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8.6.38 IO_CTRL2 Register 0x0463 – GPIO Control Register #2

图 65. GPIO Control Register #2 (IO_CTRL2)

15

7

14

13

12

4

11

3

10

9

8

0

Reserved

RO-0

6

5

2

1

CLKOUT Clock Select

RW-0000

Reserved

RO-0

CLKOUT GPIO Select

RW-001

表 61. IO_CTRL2 Field Descriptions

BIT

FIELD

TYPE

RO

DEFAULT DESCRIPTION

15:8

7:4

Reserved

0

Reserved

CLKOUT Clock Select

RW

0000

CLKOUT Clock Select:

0000 = XI Clock

0001 = TX_TCLK Clock

3

Reserved

RO

0

Reserved

2:0

CLKOUT GPIO Select

RW

001

CLKOUT GPIO Select:

000 = LED_2

001 = Clock

010 = WoL

011 = Undervoltage Indication

100 = 1588 Transmit

101 = 1588 Receive

110 = Constant '0'

111 = Constant '1'

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8.6.39 STRAP Register 0x0467 – Strap Configuration Register

图 66. Strap Configuration Register (STRAP)

15

LED_1 Bootstrap

RO/Strap

14

13

RX_DV Bootstrap

RO/Strap

12

11

RX_ER Bootstrap

RO/Strap

10

9

8

LED_0 Bootstrap

RO/Strap

7

6

5

4

3

2

1

0

RX_D0 Bootstrap

RO/Strap

RX_D1 Bootstrap

RO/Strap

RX_D2 Bootstrap

RO/Strap

RX_D3 Bootstrap

RO/Strap

表 62. STRAP Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:14

LED_1 Bootstrap

RO

Strap

LED_1 Bootstrap Mode:

00 = Mode 1; Autonomous Enabled

01 = Mode 2; RESERVED

10 = Mode 3; RESERVED

11 = Mode 4; Autonomous Disabled

Refer to the strap section in the data sheet for information

regarding PHY configuration.

Note: Bit values ('00', '01', '10', '11') are just used to indicate the

Strap Mode and do not reflect the same bit sequence that is

defined in the strap section of the data sheet.

13:12

11:10

9:8

RX_DV Bootstrap

RX_ER Bootstrap

LED_0 Bootstrap

RX_D0 Bootstrap

RO

RX_DV Bootstrap Mode:

00 = Mode 1; PHY_AD[0] = 0, PHY_AD[2] = 0

01 = Mode 2; PHY_AD[0] = 0, PHY_AD[2] = 1

10 = Mode 3; PHY_AD[0] = 1, PHY_AD[2] = 1

11 = Mode 4; PHY_AD[0] = 1, PHY_AD[2] = 0

Refer to the strap section in the data sheet for information

regarding PHY configuration.

Note: Bit values ('00', '01', '10', '11') are just used to indicate the

Strap Mode and do not reflect the same bit sequence that is

defined in the strap section of the data sheet.

RX_ER Bootstrap Mode:

00 = Mode 1; PHY_AD[1] = 0, PHY_AD[3] = 0

01 = Mode 2; PHY_AD[1] = 0, PHY_AD[3] = 1

10 = Mode 3; PHY_AD[1] = 1, PHY_AD[3] = 1

11 = Mode 4; PHY_AD[1] = 1, PHY_AD[3] = 0

Refer to the strap section in the data sheet for information

regarding PHY configuration.

Note: Bit values ('00', '01', '10', '11') are just used to indicate the

Strap Mode and do not reflect the same bit sequence that is

defined in the strap section of the data sheet.

LED_0 Bootstrap Mode:

00 = Mode 1; 100BASE-T1 Slave Mode

01 = Mode 2; RESERVED

10 = Mode 3; RESERVED

11 = Mode 4; 100BASE-T1 Master Mode

Refer to the strap section in the data sheet for information

regarding PHY configuration.

Note: Bit values ('00', '01', '10', '11') are just used to indicate the

Strap Mode and do not reflect the same bit sequence that is

defined in the strap section of the data sheet.

7:6

RX_D0 Bootstrap Mode:

00 = Mode 1; MAC[0] = 0, TEST[0] = 0

01 = Mode 2; MAC[0] = 0, TEST[0] = 1

10 = Mode 3; MAC[0] = 1, TEST[0] = 1

11 = Mode 4; MAC[0] = 1, TEST[0] = 0

Refer to the strap section in the data sheet for information

regarding PHY configuration.

Note: Bit values ('00', '01', '10', '11') are just used to indicate the

Strap Mode and do not reflect the same bit sequence that is

defined in the strap section of the data sheet.

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表 62. STRAP Field Descriptions (接下页)

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

5:4

RX_D1 Bootstrap

RO

Strap

RX_D1 Bootstrap Mode:

00 = Mode 1; MAC[1] = 0, TEST[1] = 0

01 = Mode 2; MAC[1] = 0, TEST[1] = 1

10 = Mode 3; MAC[1] = 1, TEST[1] = 1

11 = Mode 4; MAC[1] = 1, TEST[1] = 0

Refer to the strap section in the data sheet for information

regarding PHY configuration.

Note: Bit values ('00', '01', '10', '11') are just used to indicate the

Strap Mode and do not reflect the same bit sequence that is

defined in the strap section of the data sheet.

3:2

RX_D2 Bootstrap

RO

RX_D2 Bootstrap Mode:

00 = Mode 1; MAC[2] = 0, TEST[2] = 0

01 = Mode 2; MAC[2] = 0, TEST[2] = 1

10 = Mode 3; MAC[2] = 1, TEST[2] = 1

11 = Mode 4; MAC[2] = 1, TEST[2] = 0

Refer to the strap section in the data sheet for information

regarding PHY configuration.

Note: Bit values ('00', '01', '10', '11') are just used to indicate the

Strap Mode and do not reflect the same bit sequence that is

defined in the strap section of the data sheet.

1:0

RX_D3 Bootstrap

RO

RX_D3 Bootstrap Mode:

00 = Mode 1; Required Strap Mode

01 = Mode 2; RESERVED

10 = Mode 3; RESERVED

11 = Mode 4; RESERVED

Refer to the strap section in the data sheet for information

regarding PHY configuration.

Note: Bit values ('00', '01', '10', '11') are just used to indicate the

Strap Mode and do not reflect the same bit sequence that is

defined in the strap section of the data sheet.

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8.6.40 LED_CFG2 Register 0x0469 – LED Configuration Register #2

图 67. LED Configuration Register #2 (LED_CFG2)

15

14

13

12

11

10

9

8

Reserved

LED_2 Polarity

LED_2

Override Value

LED_2

Override

Enable

RO-0

5

RO-0

1

RO-0

0

7

6

4

3

2

Reserved

LED_1 Polarity

LED_1

Override Value

LED_1

Override

Enable

Reserved

LED_0 Polarity

LED_0

Override Value

LED_0

Override

Enable

RO-0

RW/Strap

RO-0

RW/Strap

RO-0

表 63. LED_CFG2 Field Descriptions

BIT

15:11

10

FIELD

TYPE

RO

DEFAULT DESCRIPTION

Reserved

0

Reserved

LED_2 Polarity

RW

LED_2 Polarity:

1 = Active HIGH

0 = Active LOW

9

8

LED_2 Override Value

LED_2 Override Enable

RW

0

LED_2 Override Value:

1 = Force HIGH

0 = Force LOW

LED_2 Override Enable:

1 = Enable force override

0 = Normal operation

7

6

Reserved

RO

0

Reserved

LED_1 Polarity

RW

Strap

LED_1 Polarity:

1 = Active HIGH

0 = Active LOW

5

4

LED_1 Override Value

LED_1 Override Enable

RW

0

LED_1 Override Value:

1 = Force HIGH

0 = Force LOW

LED_1 Override Enable:

1 = Enable force override

0 = Normal operation

3

2

Reserved

RO

0

Reserved

LED_0 Polarity

RW

Strap

LED_0 Polarity:

1 = Active HIGH

0 = Active LOW

1

0

LED_0 Override Value

LED_0 Override Enable

RW

0

LED_0 Override Value:

1 = Force HIGH

0 = Force LOW

LED_0 Override Enable:

1 = Enable force override

0 = Normal operation

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8.6.41 MON_CFG1 Register 0x0480 – Monitor Configuration Register #1

图 68. Monitor Configuration Register #1 (MON_CFG1)

15

7

14

6

13

5

12

4

11

3

10

9

1

8

0

Reserved

RO-0

2

Monitors Configuration Cycle Period

RW-0010

表 64. MON_CFG1 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:4

3:0

Reserved

RO

0

Reserved

Monitors Configuration Cycle Period RW

0010

Monitors Configuration Cycle Period:

If monitors are set to periodic mode, bits[3:0] determine the

sampling cycle time.

Cycle time has a range of 16ms - 240ms.

Example:

If value of bits[3:0] = 0b0001, sample time is 16ms.

Note: 0b0000 is invalid

8.6.42 MON_CFG2 Register 0x0481 – Monitor Configuration Register #2

图 69. Monitor Configuration Register #2 (MON_CFG2)

15

7

14

6

13

5

12

11

10

2

9

8

Reserved

RO-0000 0000 1010 00

4

3

1

0

Temperature /

Supply Monitor Supply Monitor

Periodic Mode

Start

RW-1

RW/SC-0

表 65. MON_CFG2 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:2

Reserved

RW

0000 0000 Reserved

1010 00

1

Temperature / Supply Monitor

Periodic Mode

RW

1

Temperature and Supply Monitor Periodic Mode:

1 = Temperature and supply monitor are activated periodically

0 = Temperature and supply monitor is a single run

Note: When temperature and supply monitor are activated

periodically, cycle time is determined by bits[3:0] in register

0x480.

0

Temperature / Supply Monitor Start RW, SC

0

Temperature and Supply Monitor Start:

1 = Start temperature and supply monitor function (this bit self-

clears)

0 = Normal operation

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8.6.43 MON_CFG3 Register 0x0482 – Monitor Configuration Register #3

图 70. Monitor Configuration Register #3 (MON_CFG3)

15

14

13

12

11

10

9

8

Reserved

RW-0

Undervoltage Threshold Configuration

RW-111

Reserved

RW-0

Overvoltage Threshold Configuration

RW-000

7

6

5

4

3

2

1

0

Reserved

RW-0

Overtemperature Threshold Configuration

RW-111

表 66. MON_CFG3 Field Descriptions

BIT

15

FIELD

TYPE

RW

DEFAULT DESCRIPTION

Reserved

0

Reserved

14:12

Undervoltage Threshold

Configuration

RW

111

Undervoltage Threshold Configuration:

000 = Voltage > VDD + 9%

001 = VDD + 1.5% < Voltage < VDD + 9%

010 = VDD - 4.5% < Voltage < VDD + 1.5%

011 = VDD - 7.5% < Voltage < VDD - 4.5%

100 = VDD - 10.5% < Voltage < VDD - 7.5%

101 = VDD - 13.5% < Voltage < VDD - 10.5%

110 = VDD - 16.5% < Voltage < VDD - 13.5%

111 = Voltage < VDD - 16.5%

Note 1: VDD = 1.8 V, 2.5 V or 3.3 V

Note 2: VDD +/- X% represents VDD +/- VDD*(X)/100

11

Reserved

RW

0

Reserved

10:8

Overvoltage Threshold

Configuration

000

Overvoltage Threshold Configuration:

000 = Voltage > VDD + 9%

001 = VDD + 1.5% < Voltage < VDD + 9%

010 = VDD - 4.5% < Voltage < VDD + 1.5%

011 = VDD - 7.5% < Voltage < VDD - 4.5%

100 = VDD - 10.5% < Voltage < VDD - 7.5%

101 = VDD - 13.5% < Voltage < VDD - 10.5%

110 = VDD - 16.5% < Voltage < VDD - 13.5%

111 = Voltage < VDD - 16.5%

Note 1: VDD = 1.8 V, 2.5 V or 3.3 V

Note 2: VDD +/- X% represents VDD +/- VDD*(X)/100

7:3

2:0

Reserved

RW

0

Reserved

Overtemperature Threshold

Configuration

111

Overtemperature Threshold Configuration:

000 = Temperature < -40^oC

001 = -40^oC < Temperature < 0^oC

010 = 0^oC < Temperature < 30^oC

011 = 30^oC < Temperature < 70^oC

100 = 70^oC < Temperature < 100^oC

101 = 100^oC < Temperature < 135^oC

110 = 135^oC < Temperature < 165^oC

111 = Temperature > 165^oC

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8.6.44 MON_STAT1 Register 0x0483 – Monitor Status Register #1

图 71. Monitor Status Register #1 (MON_STAT1)

15

7

14

6

13

5

12

4

11

3

10

9

1

8

0

Reserved

RO-0

2

Temperature Monitor Value

RO-000

表 67. MON_STAT1 Field Descriptions

BIT

FIELD

TYPE

RO

DEFAULT DESCRIPTION

15:3

2:0

Reserved

0

Reserved

Temperature Monitor Value

RO

000

Temperature Monitor Value:

000 = Temperature < -40^oC

001 = -40^oC < Temperature < 0^oC

010 = 0^oC < Temperature < 30^oC

011 = 30^oC < Temperature < 70^oC

100 = 70^oC < Temperature < 100^oC

101 = 100^oC < Temperature < 135^oC

110 = 135^oC < Temperature < 165^oC

111 = Temperature > 165^oC

8.6.45 MON_STAT2 Register 0x0484 – Monitor Status Register #2

图 72. Monitor Status Register #2 (MON_STAT2)

15

14

6

13

12

4

11

10

9

8

0

Reserved

RO-0

VDDIO Supply Monitor Value

RO-000

Reserved

RO-0

VDDA Supply Monitor Value

RO-000

7

5

3

2

1

Reserved

RO-0

表 68. MON_STAT2 Field Descriptions

BIT

15

FIELD

TYPE

RO

DEFAULT DESCRIPTION

Reserved

0

Reserved

14:12

VDDIO Supply Monitor Value

RO

000

VDDIO Supply Monitor Value:

000 = Voltage > VDDIO + 9%

001 = VDDIO + 1.5% < Voltage < VDDIO + 9%

010 = VDDIO - 4.5% < Voltage < VDDIO + 1.5%

011 = VDDIO - 7.5% < Voltage < VDDIO - 4.5%

100 = VDDIO - 10.5% < Voltage < VDDIO - 7.5%

101 = VDDIO - 13.5% < Voltage < VDDIO - 10.5%

110 = VDDIO - 16.5% < Voltage < VDDIO - 13.5%

111 = Voltage < VDDIO - 16.5%

Note 1: VDDIO = 1.8 V, 2.5 V or 3.3 V

Note 2: VDDIO +/- X% represents VDDIO +/- VDDIO*(X)/100

11

Reserved

RO

0

Reserved

10:8

VDDA Supply Monitor Value

000

VDDA Supply Monitor Value:

000 = Voltage > VDDA + 9%

001 = VDDA + 1.5% < Voltage < VDDA + 9%

010 = VDDA - 4.5% < Voltage < VDDA + 1.5%

011 = VDDA - 7.5% < Voltage < VDDA - 4.5%

100 = VDDA - 10.5% < Voltage < VDDA - 7.5%

101 = VDDA - 13.5% < Voltage < VDDA - 10.5%

110 = VDDA - 16.5% < Voltage < VDDA - 13.5%

111 = Voltage < VDDA - 16.5%

Note 1: VDDA = 3.3 V

Note 2: VDDA +/- X% represents VDDA +/- VDDA*(X)/100

7:0

Reserved

RO

0

Reserved

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8.6.46 PCS_CTRL1 Register 0x0485 – PCS Control Register #1

图 73. PCS Control Register #1 (PCS_CTRL1)

15

14

13

IPG Scrambler

Lock Check

Disable

12

Link Control

11

10

Reserved

9

1

8

Reserved

RW-0

Link-Up

Descrambler

Lock

Configuration

RW-0

5

RW-1

4

RW-0

2

RW-0111 1000

0

7

6

3

Link-Up Descrambler Lock Configuration

RW-0111 1000

表 69. PCS_CTRL1 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:14

13

Reserved

RW

0

Reserved

IPG Scrambler Lock Check Disable RW

IPG Scrambler Lock Check Diable:

1 = Scrambler lock check is disabled during IPG

0 = Scrambler lock check is enabled during IPG

12

Link Control

RW

1

Link Control:

1 = Enable training and link-up to start

0 = Disable training and link-up

11:9

8:0

Reserved

RO

0

Reserved

Link-Up Descrambler Lock

Configuration

RW

0111 1000 Link-Up Descrambler Lock Configuration:

Determines the number of initial idle symbols to determine

descrambler lock (LINK)

Default set to 120 IDLES

8.6.47 PCS_CTRL2 Register – 0x0486 PCS Control Register #2

图 74. PCS Control Register #2 (PCS_CTRL2)

15

14

13

12

11

10

9

1

8

0

Reserved

RW-00

Descrambler Error Count Configuration

RW-00 1010

7

6

5

4

3

2

Reserved

RW-000

Remote Receiver Configuration

RW-0 0101

表 70. PCS_CTRL2 Field Descriptions

BIT

FIELD

TYPE

RW

DEFAULT DESCRIPTION

15:14

13:9

Reserved

00

Reserved

Descrambler Error Count

Configuration

RW

00 101

Descrambler Error Count Configuration:

Determines the number of error (non-idle) symbols to determine

descrambler loss of lock (no LINK)

Default set to 10 symbols

8:5

4:0

Reserved

RW

0 000

Reserved

Remote Receiver Configuration

0 0101

Remote Receiver Configuration:

Determines the number of error symbols for remote receiver

status to go LOW.

Default set to 5 symbols

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8.6.48 LPS_CTRL2 Register 0x0487 – LPS Control Register #2

图 75. LPS Control Register #2 (LPS_CTRL2)

15

7

14

6

13

5

12

11

10

9

1

8

0

Reserved

RW-0000 1010 0000 000

4

3

2

PCS LPS

Enable

RW--0

表 71. LPS_CTRL2 Register 0x0487 – LPS Control Register #2

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:1

Reserved

RW

0000 1010 Reserved

0000 000

0

PCS LPS Enable

RW

0

PCS LPS Enable:

1 = LPS enabled in PCS

0 = LPS disabled in PCS

Device must have this bit enabled to transmit and receive LPS

code-groups.

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8.6.49 INTER_CFG Register 0x0489 – Interleave Configuration

图 76. Interleave Configuration (INTER_CFG)

15

7

14

6

13

12

11

10

9

1

8

0

Reserved

RO-0

5

4

3

2

Force

Interleave

Enable

Interleave

Detection

Enable

RW-0

RW-1

表 72. INTER_CFG Field Descriptions

BIT

FIELD

TYPE

RO

DEFAULT DESCRIPTION

15:3

2

Reserved

0

Reserved

Force Interleave

RW

Force Interleave:

1 = Force interleave on TX

0 = Normal operation

1

0

Interleave Enable

RW

0

1

Interleave Enable:

1 = Enable interleave on TX if interleave detected on RX

0 = Normal operation

Interleave Detection Enable

Interleave Detection Enable:

1 = Enable interleave detection

0 = Disable interleave detection

8.6.50 LPS_CTRL3 Register 0x0493 – LPS Control Register #3

图 77. LPS Control Register #3 (LPS_CTRL3)

15

14

13

12

11

10

9

1

8

0

Reserved

RW-0

7

6

5

4

3

2

sleep_rqst_timer Setting

RW-01

Reserved

RW-0100

表 73. LPS_CTRL3 Register 0x0493 – LPS Control Register #3

BIT

FIELD

TYPE

RW

DEFAULT DESCRIPTION

15:6

5:4

Reserved

0

Reserved

sleep_rqst_timer

RW

01

sleep_rqst_timer Setting:

00 = 0.4 ms

01 = 1 ms

10 = 4 ms

11 = 8 ms

3:0

Reserved

RW

0100

Reserved

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8.6.51 JAB_CFG Register 0x0496 – Jabber Configuration Register

图 78. Jabber Configuration Register (JAB_CFG)

15

7

14

6

13

12

4

11

3

10

9

8

Reserved

RO-0

Jabber Timout Configuration

RW-100 0100 1100

5

2

1

0

Jabber Timout Configuration

RW-100 0100 1100

表 74. JAB_CFG Field Descriptions

BIT

FIELD

TYPE

RO

DEFAULT DESCRIPTION

Reserved

100 0100 Jabber Timout Configuration:

15:11

10:0

Reserved

0

Jabber Timout Configuration

RW

1100

Sets time to determine a jabber condition.

Default set to 1100us.

Note: Convert value read in this register to decimal format to

find the time in micro seconds

8.6.52 TEST_MODE_CTRL Register 0x0497 – Test Mode Control Register

图 79. Test Mode Control Register (TEST_MODE_CTRL)

15

7

14

6

13

5

12

4

11

3

10

2

9

8

Reserved

Test Mode 1 Symbol Control

RW-01 1100

RO-0000 00

1

0

Reserved

RO-0000

表 75. TEST_MODE_CTRL Field Descriptions

BIT

FIELD

TYPE

RO

DEFAULT DESCRIPTION

15:10

9:4

Reserved

0000 00

01 1100

Reserved

Test Mode 1 Symbol Control:

Test Mode 1 Symbol Control

RW

Sets the number of +1/-1 symbols to send in Test Mode 1

Number of Symbols = (2*FIELD_VALUE + 2)

Example:

FIELD_VALUE = 28

Number of Symbols = (2*28 + 2) = 58

Time = 58*15ns = 870ns

3:0

Reserved

RW

0000

Reserved

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8.6.53 WOL_CFG Register 0x04A0 – WoL Configuration Register

图 80. WoL Configuration Register (WOL_CFG)

15

14

13

12

11

10

9

8

Bit Nibble Swap

SFD Byte

CRC Gate

WoL Level

Change

WoL Pulse Indication Select

WoL Indication

Select

Indication Clear

RW-00

RW-0

5

RW-1

4

W/SC-0

RW-00

RW-0

0

7

6

3

2

1

WoL Enable

Bit Mask Flag

Secure-ON

Enable

Reserved

WoL Pattern

Enable

WoL Magic

Packet Enable

RW-0

表 76. WOL_CFG Field Descriptions

BIT

FIELD

Bit Nibble Swap

TYPE

DEFAULT DESCRIPTION

15:14

RW

00

Bit Nibble Swap:

00 = normal order, no swap (RXD [3:0])

01 = swap bits order (RXD [0:3])

10 = swap nibbles order (RXD [3:0] , RXD [7:4])

11 = swap bits order in each nibble (RXD [4:7] , RXD [0:3])

13

12

SFD Byte

CRC Gate

RW

0

1

SFD Byte Search:

1 = SFD is 0x5D (i.e. Receive module searches for 0x5D)

0 = SFD is 0xD5 (i.e. Receive module searches for 0xD5)

CRC Gate:

1 = Bad CRC gates Magic Packet and Pattern Indications

0 = Disable bad CRC gate

Note: If Bad CRC gate is disabled, there will be no indication

(status, interrupt, GPIO) if the device receives a bad CRC.

11

WoL Level Change Indication Clear W, SC

0

WoL Level Change Indication Clear:

If WoL Indication is set for Level change mode, this bit clears the

level upon a write.

10:9

WoL Pulse Indication Select

RW

00

WoL Pulse Indication Select:

Only valid when WoL Indication is set for Pulse mode.

00 = 8 clock cycles (of 100-MHz clock)

01 = 16 clock cycles

10 = 32 clock cycles

11 = 64 clock cycles

8

7

WoL Indication Select

WoL Enable

RW

0

WoL Indication Select:

1 = Level change mode

0 = Pulse mode

WoL Enable:

1 = Enable Wake-on-LAN (WoL)

0 = normal operation

6

5

Bit Mask Flag

RW

0

Bit Mask Flag

Secure-ON Enable

Reserved

Enable Secure-ON password for Magic Packets

Reserved

4:2

1

WoL Pattern Enable

WoL Magic Packet Enable

Enable Interrupt upon reception of packet with configured pattern

Enable Interrupt upon reception of Magic Packet

0

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8.6.54 WOL_STAT Register 0x04A1 – WoL Status Register

图 81. WoL Status Register (WOL_STAT)

15

14

13

12

11

10

9

1

8

0

Reserved

WoL Interrupt

Source

Reserved

RO-0

RW-0

4

7

6

5

3

2

SFD Error

Bad CRC

Secure-On

Hack Flag

Reserved

WoL Pattern

Status

WoL Magic

Packet Status

RO/LH/SC-0

表 77. WOL_STAT Field Descriptions

BIT

15:13

12

FIELD

Reserved

TYPE

RO

DEFAULT DESCRIPTION

0

Reserved

WoL Interrupt Source:

WoL Interrupt Source

RW

Source of Interrupt for bit [1] of register 0x13.

1 = WoL Interrupt

0 = Data Polarity Interrupt

When enabling WoL, this bit is automatically set to WoL

Interrupt.

11:8

7

Reserved

SFD Error

RO

0

Reserved

RO, LH,

SC

SFD Error:

1 = Packet with SFD error (without the SFD byte indicated in bit

[13] register 0x4A0)

0 = No SFD error

6

5

Bad CRC

RO, LH,

SC

0

Bad CRC:

1 = Bad CRC was received

0 = No bad CRC received

Secure-On Hack Flag

RO, LH,

SC

Secure-ON Hack Flag:

1 = Invalid Password detected in Magic Packet

0 = Valid Secure-ON Password

4:2

1

Reserved

RO, LH,

SC

0

Reserved

WoL Pattern Status

RO, LH,

SC

WoL Pattern Status:

1 = Valid packet with configured pattern received

0 = No valid packet with configured pattern received

0

WoL Magic Packet Status

RO, LH,

SC

0

WoL Magic Packet Status:

1 = Valid Magic Packet received

0 = No valid Magic Packet received

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8.6.55 WOL_DA1 Register 0x04A2 – WoL Destination Address Configuration Register #1

图 82. WoL Destination Address Configuration Register #1 (WOL_DA1)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

MAC Destination Address Byte 4

RW-0

4

3

MAC Destination Address Byte 5

RW-0

表 78. WOL_DA1 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

MAC Destination Address Byte 4

RW

0

Perfect Match Data:

Configured for MAC Destination Address

7:0

MAC Destination Address Byte 5

RW

0

Perfect Match Data:

Configured for MAC Destination Address

8.6.56 WOL_DA2 Register 0x04A3 – WoL Destination Address Configuration Register #2

图 83. WoL Destination Address Configuration Register #2 (WOL_DA2)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

MAC Destination Address Byte 2

RW-0

4

3

MAC Destination Address Byte 3

RW-0

表 79. WOL_DA2 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

MAC Destination Address Byte 2

RW

0

Perfect Match Data:

Configured for MAC Destination Address

7:0

MAC Destination Address Byte 3

RW

0

Perfect Match Data:

Configured for MAC Destination Address

8.6.57 WOL_DA3 Register 0x04A4 – WoL Destination Address Configuration Register #3

图 84. WoL Destination Address Configuration Register #3 (WOL_DA3)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

MAC Destination Address Byte 0

RW-0

4

3

MAC Destination Address Byte 1

RW-0

表 80. WOL_DA3 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

MAC Destination Address Byte 0

RW

0

Perfect Match Data:

Configured for MAC Destination Address

7:0

MAC Destination Address Byte 1

RW

0

Perfect Match Data:

Configured for MAC Destination Address

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8.6.58 RXSOP1 Register 0x04A5 – Receive Secure-ON Password Register #1

图 85. Receive Secure-ON Password Register #1 (RXSOP1)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

Secure-ON Password Byte 1

RW-0

4

3

Secure-ON Password Byte 0

RW-0

表 81. RXSOP1 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Secure-ON Password Byte 1

RW

0

Secure-ON Password Select:

Secure-ON password for Magic Packets

7:0

Secure-ON Password Byte 0

RW

0

Secure-ON Password Select:

Secure-ON password for Magic Packets

8.6.59 RXSOP2 Register 0x04A6 – Receive Secure-ON Password Register #2

图 86. Receive Secure-ON Password Register #2 (RXSOP2)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

Secure-ON Password Byte 3

RW-0

4

3

Secure-ON Password Byte 2

RW-0

表 82. RXSOP2 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Secure-ON Password Byte 3

RW

0

Secure-ON Password Select:

Secure-ON password for Magic Packets

7:0

Secure-ON Password Byte 2

RW

0

Secure-ON Password Select:

Secure-ON password for Magic Packets

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8.6.60 RXSOP3 Register 0x04A7 – Receive Secure-ON Password Register #3

图 87. Receive Secure-ON Password Register #3 (RXSOP3)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

Secure-ON Password Byte 5

RW-0

4

3

Secure-ON Password Byte 4

RW-0

表 83. RXSOP3 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Secure-ON Password Byte 5

RW

0

Secure-ON Password Select:

Secure-ON password for Magic Packets

7:0

Secure-ON Password Byte 4

RW

0

Secure-ON Password Select:

Secure-ON password for Magic Packets

8.6.61 RXPAT1 Register 0x04A8 – Receive Pattern Register #1

图 88. Receive Pattern Register #1 (RXPAT1)

15

14

13

12

11

10

9

1

8

0

Pattern Byte 1

RW-0

7

6

5

4

3

2

Pattern Byte 0

RW-0

表 84. RXPAT1 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 1

RW

0

Pattern Configuration:

Configures byte 1 of the pattern

7:0

Pattern Byte 0

RW

0

Pattern Configuration:

Configures byte 0 of the pattern

89

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8.6.62 RXPAT2 Register 0x04A9 – Receive Pattern Register #2

图 89. Receive Pattern Register #2 (RXPAT2)

15

7

14

6

13

5

12

4

11

3

10

9

1

8

0

Pattern Byte 3

RW-0

2

Pattern Byte 2

RW-0

表 85. RXPAT2 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 3

RW

0

Pattern Configuration:

Configures byte 3 of the pattern

7:0

Pattern Byte 2

RW

0

Pattern Configuration:.

Configures byte 2 of the pattern

8.6.63 RXPAT3 Register 0x04AA – Receive Pattern Register #3

图 90. Receive Pattern Register #3 (RXPAT3)

15

14

13

12

11

10

9

1

8

0

Pattern Byte 5

RW-0

7

6

5

4

3

2

Pattern Byte 4

RW-0

表 86. RXPAT3 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 5

RW

0

Pattern Configuration:

Configures byte 5 of the pattern

7:0

Pattern Byte 4

RW

0

Pattern Configuration:

Configures byte 4 of the pattern

90

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8.6.64 RXPAT4 Register 0x04AB – Receive Pattern Register #4

图 91. Receive Pattern Register #4 (RXPAT4)

15

7

14

6

13

12

11

10

9

1

8

0

Pattern Byte 7

RW-0

5

4

3

2

Pattern Byte 6

RW-0

表 87. RXPAT4 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 7

RW

0

Pattern Configuration:

Configures byte 7 of the pattern

7:0

Pattern Byte 6

RW

0

Pattern Configuration:

Configures byte 6 of the pattern

8.6.65 RXPAT5 Register 0x04AC – Receive Pattern Register #5

图 92. Receive Pattern Register #5 (RXPAT5)

15

14

13

12

11

10

9

1

8

0

Pattern Byte 9

RW-0

7

6

5

4

3

2

Pattern Byte 8

RW-0

表 88. RXPAT5 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 9

RW

0

Pattern Configuration:

Configures byte 9 of the pattern

7:0

Pattern Byte 8

RW

0

Pattern Configuration:

Configures byte 8 of the pattern

91

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8.6.66 RXPAT6 Register 0x04AD – Receive Pattern Register #6

图 93. Receive Pattern Register #6 (RXPAT6)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 11

RW-0

4

3

2

Pattern Byte 10

RW-0

表 89. RXPAT6 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 11

RW

0

Pattern Configuration:

Configures byte 11 of the pattern

7:0

Pattern Byte 10

RW

0

Pattern Configuration:

Configures byte 10 of the pattern

8.6.67 RXPAT7 Register 0x04AE – Receive Pattern Register #7

图 94. Receive Pattern Register #7 (RXPAT7)

15

14

13

12

11

10

9

1

8

0

Pattern Byte 13

RW-0

7

6

5

4

3

2

Pattern Byte 12

RW-0

表 90. RXPAT7 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 13

RW

0

Pattern Configuration:

Configures byte 13 of the pattern

7:0

Pattern Byte 12

RW

0

Pattern Configuration:

Configures byte 12 of the pattern

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8.6.68 RXPAT8 Register 0x04AF – Receive Pattern Register #8

图 95. Receive Pattern Register #8 (RXPAT8)

15

7

14

6

13

12

11

10

9

1

8

0

Pattern Byte 15

RW-0

5

4

3

2

Pattern Byte 14

RW-0

表 91. RXPAT8 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 15

RW

0

Pattern Configuration:

Configures byte 15 of the pattern

7:0

Pattern Byte 14

RW

0

Pattern Configuration:

Configures byte 14 of the pattern

8.6.69 RXPAT9 Register 0x04B0 – Receive Pattern Register #9

图 96. Receive Pattern Register #9 (RXPAT9)

15

14

13

12

11

10

9

1

8

0

Pattern Byte 17

RW-0

7

6

5

4

3

2

Pattern Byte 16

RW-0

表 92. RXPAT9 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 17

RW

0

Pattern Configuration:

Configures byte 17 of the pattern

7:0

Pattern Byte 16

RW

0

Pattern Configuration:

Configures byte 16 of the pattern

93

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8.6.70 RXPAT10 Register 0x04B1 – Receive Pattern Register #10

图 97. Receive Pattern Register #10 (RXPAT10)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 19

RW-0

4

3

2

Pattern Byte 18

RW-0

表 93. RXPAT10 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 19

RW

0

Pattern Configuration:

Configures byte 19 of the pattern

7:0

Pattern Byte 18

RW

0

Pattern Configuration:

Configures byte 18 of the pattern

8.6.71 RXPAT11 Register 0x04B2 Receive Pattern Register #11

图 98. Receive Pattern Register #11 (RXPAT11)

15

14

13

12

11

10

9

1

8

0

Pattern Byte 21

RW-0

7

6

5

4

3

2

Pattern Byte 20

RW-0

表 94. RXPAT11 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 21

RW

0

Pattern Configuration:

Configures byte 21 of the pattern

7:0

Pattern Byte 20

RW

0

Pattern Configuration:

Configures byte 20 of the pattern

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8.6.72 RXPAT12 Register 0x04B3 – Receive Pattern Register #12

图 99. Receive Pattern Register #12 (RXPAT12)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 23

RW-0

4

3

2

Pattern Byte 22

RW-0

表 95. RXPAT12 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 23

RW

0

Pattern Configuration:

Configures byte 23 of the pattern

7:0

Pattern Byte 22

RW

0

Pattern Configuration:

Configures byte 22 of the pattern

8.6.73 RXPAT13 Register 0x04B4 – Receive Pattern Register #13

图 100. Receive Pattern Register #13 (RXPAT13)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 25

RW-0

4

3

2

Pattern Byte 24

RW-0

表 96. RXPAT13 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 25

RW

0

Pattern Configuration:

Configures byte 25 of the pattern

7:0

Pattern Byte 24

RW

0

Pattern Configuration:

Configures byte 24 of the pattern

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8.6.74 RXPAT14 Register 0x04B5 – Receive Pattern Register #14

图 101. Receive Pattern Register #14 (RXPAT14)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 27

RW-0

4

3

2

Pattern Byte 26

RW-0

表 97. RXPAT14 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 27

RW

0

Pattern Configuration:

Configures byte 27 of the pattern

7:0

Pattern Byte 26

RW

0

Pattern Configuration:

Configures byte 26 of the pattern

8.6.75 RXPAT15 Register 0x04B6 – Receive Pattern Register #15

图 102. Receive Pattern Register #15 (RXPAT15)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 29

RW-0

4

3

2

Pattern Byte 28

RW-0

表 98. RXPAT15 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 29

RW

0

Pattern Configuration:

Configures byte 29 of the pattern

7:0

Pattern Byte 28

RW

0

Pattern Configuration:

Configures byte 28 of the pattern

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8.6.76 RXPAT16 Register 0x04B7 – Receive Pattern Register #16

图 103. Receive Pattern Register #16 (RXPAT16)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 31

RW-0

4

3

2

Pattern Byte 30

RW-0

表 99. RXPAT16 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 31

RW

0

Pattern Configuration:

Configures byte 31 of the pattern

7:0

Pattern Byte 30

RW

0

Pattern Configuration:

Configures byte 30 of the pattern

8.6.77 RXPAT17 Register 0x04B8 – Receive Pattern Register #17

图 104. Receive Pattern Register #17 (RXPAT17)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 33

RW-0

4

3

2

Pattern Byte 32

RW-0

表 100. RXPAT17 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 33

RW

0

Pattern Configuration:

Configures byte 33 of the pattern

7:0

Pattern Byte 32

RW

0

Pattern Configuration:

Configures byte 32 of the pattern

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8.6.78 RXPAT18 Register 0x04B9 – Receive Pattern Register #18

图 105. Receive Pattern Register #18 (RXPAT18)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 35

RW-0

4

3

2

Pattern Byte 34

RW-0

表 101. RXPAT18 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 35

RW

0

Pattern Configuration:

Configures byte 35 of the pattern

7:0

Pattern Byte 34

RW

0

Pattern Configuration:

Configures byte 34 of the pattern

8.6.79 RXPAT19 Register 0x04BA Receive Pattern Register #19

图 106. Receive Pattern Register #19 (RXPAT19)

15

14

13

12

11

10

9

1

8

0

Pattern Byte 37

RW-0

7

6

5

4

3

2

Pattern Byte 36

RW-0

表 102. RXPAT19 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 37

RW

0

Pattern Configuration:

Configures byte 37 of the pattern

7:0

Pattern Byte 36

RW

0

Pattern Configuration:

Configures byte 36 of the pattern

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8.6.80 RXPAT20 Register 0x04BB – Receive Pattern Register #20

图 107. Receive Pattern Register #20 (RXPAT20)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 39

RW-0

4

3

2

Pattern Byte 38

RW-0

表 103. RXPAT20 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 39

RW

0

Pattern Configuration:

Configures byte 39 of the pattern

7:0

Pattern Byte 38

RW

0

Pattern Configuration:

Configures byte 38 of the pattern

8.6.81 RXPAT21 Register 0x04BC – Receive Pattern Register #21

图 108. Receive Pattern Register #21 (RXPAT21)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 41

RW-0

4

3

2

Pattern Byte 40

RW-0

表 104. RXPAT21 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 41

RW

0

Pattern Configuration:

Configures byte 41 of the pattern

7:0

Pattern Byte 40

RW

0

Pattern Configuration:

Configures byte 40 of the pattern

99

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8.6.82 RXPAT22 Register 0x04BD – Receive Pattern Register #22

图 109. Receive Pattern Register #22 (RXPAT22)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 43

RW-0

4

3

2

Pattern Byte 42

RW-0

表 105. RXPAT22 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 43

RW

0

Pattern Configuration:

Configures byte 43 of the pattern

7:0

Pattern Byte 42

RW

0

Pattern Configuration:

Configures byte 42 of the pattern

8.6.83 RXPAT23 Register 0x04BE – Receive Pattern Register #23

图 110. Receive Pattern Register #23 (RXPAT23)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 45

RW-0

4

3

2

Pattern Byte 44

RW-0

表 106. RXPAT23 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 45

RW

0

Pattern Configuration:

Configures byte 45 of the pattern

7:0

Pattern Byte 44

RW

0

Pattern Configuration:

Configures byte 44 of the pattern

100

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8.6.84 RXPAT24 Register 0x04BF – Receive Pattern Register #24

图 111. Receive Pattern Register #24 (RXPAT24)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 47

RW-0

4

3

2

Pattern Byte 46

RW-0

表 107. RXPAT24 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 47

RW

0

Pattern Configuration:

Configures byte 47 of the pattern

7:0

Pattern Byte 46

RW

0

Pattern Configuration:

Configures byte 46 of the pattern

8.6.85 RXPAT25 Register 0x04C0 – Receive Pattern Register #25

图 112. Receive Pattern Register #25 (RXPAT25)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 49

RW-0

4

3

2

Pattern Byte 48

RW-0

表 108. RXPAT25 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 49

RW

0

Pattern Configuration:

Configures byte 49 of the pattern

7:0

Pattern Byte 48

RW

0

Pattern Configuration:

Configures byte 48 of the pattern

101

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8.6.86 RXPAT26 Register 0x04C1 – Receive Pattern Register #26

图 113. Receive Pattern Register #26 (RXPAT26)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 51

RW-0

4

3

2

Pattern Byte 50

RW-0

表 109. RXPAT26 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 51

RW

0

Pattern Configuration:

Configures byte 51 of the pattern

7:0

Pattern Byte 50

RW

0

Pattern Configuration:

Configures byte 50 of the pattern

8.6.87 RXPAT27 Register 0x04C2 Receive Pattern Register #27

图 114. Receive Pattern Register #27 (RXPAT27)

15

14

13

12

11

10

9

1

8

0

Pattern Byte 53

RW-0

7

6

5

4

3

2

Pattern Byte 52

RW-0

表 110. RXPAT27 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 53

RW

0

Pattern Configuration:

Configures byte 53 of the pattern

7:0

Pattern Byte 52

RW

0

Pattern Configuration:

Configures byte 52 of the pattern

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8.6.88 RXPAT28 Register 0x04C3 – Receive Pattern Register #28

图 115. Receive Pattern Register #28 (RXPAT28)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 55

RW-0

4

3

2

Pattern Byte 54

RW-0

表 111. RXPAT28 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 55

RW

0

Pattern Configuration:

Configures byte 55 of the pattern

7:0

Pattern Byte 54

RW

0

Pattern Configuration:

Configures byte 54 of the pattern

8.6.89 RXPAT29 Register 0x04C4 – Receive Pattern Register #29

图 116. Receive Pattern Register #29 (RXPAT29)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 57

RW-0

4

3

2

Pattern Byte 56

RW-0

表 112. RXPAT29 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 57

RW

0

Pattern Configuration:

Configures byte 57 of the pattern

7:0

Pattern Byte 56

RW

0

Pattern Configuration:

Configures byte 56 of the pattern

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8.6.90 RXPAT30 Register 0x04C5 – Receive Pattern Register #30

图 117. Receive Pattern Register #30 (RXPAT30)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 59

RW-0

4

3

2

Pattern Byte 58

RW-0

表 113. RXPAT30 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 59

RW

0

Pattern Configuration:

Configures byte 59 of the pattern

7:0

Pattern Byte 58

RW

0

Pattern Configuration:

Configures byte 58 of the pattern

8.6.91 RXPAT31 Register 0x04C6 – Receive Pattern Register #31

图 118. Receive Pattern Register #31 (RXPAT31)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 61

RW-0

4

3

2

Pattern Byte 60

RW-0

表 114. RXPAT31 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 61

RW

0

Pattern Configuration:

Configures byte 61 of the pattern

7:0

Pattern Byte 60

RW

0

Pattern Configuration:

Configures byte 60 of the pattern

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8.6.92 RXPAT32 Register 0x04C7 – Receive Pattern Register #32

图 119. Receive Pattern Register #32 (RXPAT32)

15

7

14

6

13

5

12

11

10

9

1

8

0

Pattern Byte 63

RW-0

4

3

2

Pattern Byte 62

RW-0

表 115. RXPAT32 Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

15:8

Pattern Byte 63

RW

0

Pattern Configuration:

Configures byte 63 of the pattern

7:0

Pattern Byte 62

RW

0

Pattern Configuration:

Configures byte 62 of the pattern

8.6.93 RXPBM1 Register 0x04C8 – Receive Pattern Byte Mask Register #1

图 120. Receive Pattern Byte Mask Register #1 (RXPBM1)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

Mask Bytes 0 to 15

RW-0

4

3

Mask Bytes 0 to 15

RW-0

表 116. RXPBM1 Field Descriptions

BIT

15:0

FIELD

Mask Bytes 0 to 15

TYPE

DEFAULT DESCRIPTION

RW

0 Pattern Byte Mask Configuration:

Configures masks for bytes 0 to 15. For each byte '1' means it is

masked.

105

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8.6.94 RXPBM2 Register 0x04C9 – Receive Pattern Byte Mask Register #2

图 121. Receive Pattern Byte Mask Register #2 (RXPBM2)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

Mask Bytes 16 to 31

RW-0

4

3

Mask Bytes 16 to 31

RW-0

表 117. RXPBM2 Field Descriptions

BIT

15:0

FIELD

Mask Bytes 16 to 31

TYPE

DEFAULT DESCRIPTION

RW

0 Pattern Byte Mask Configuration:

Configures masks for bytes 16 to 31. For each byte '1' means it

is masked.

8.6.95 RXPBM3 Register 0x04CA – Receive Pattern Byte Mask Register #3

图 122. Receive Pattern Byte Mask Register #3 (RXPBM3)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

Mask Bytes 32 to 47

RW-0

4

3

Mask Bytes 32 to 47

RW-0

表 118. RXPBM3 Field Descriptions

BIT

15:0

FIELD

Mask Bytes 32 to 47

TYPE

DEFAULT DESCRIPTION

RW

0 Pattern Byte Mask Configuration:

Configures masks for bytes 32 to 47. For each byte '1' means it

is masked.

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8.6.96 RXPBM4 Register 0x04CB – Receive Pattern Byte Mask Register #4

图 123. Receive Pattern Byte Mask Register #4 (RXPBM4)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

Mask Bytes 48 to 63

RW-0

4

3

Mask Bytes 48 to 63

RW-0

表 119. RXPBM4 Field Descriptions

BIT

15:0

FIELD

Mask Bytes 48 to 63

TYPE

DEFAULT DESCRIPTION

RW

0 Pattern Byte Mask Configuration:

Configures masks for bytes 48 to 63. For each byte '1' means it

is masked.

8.6.97 RXPATC Register 0x04CC – Receive Pattern Control Register

图 124. Receive Pattern Control Register (RXPATC)

15

7

14

6

13

5

12

4

11

10

9

1

8

0

Reserved

RO-0

3

2

Pattern Start Point

RW-0

表 120. RXPATC Field Descriptions

BIT

FIELD

TYPE

RO

DEFAULT DESCRIPTION

15:6

5:0

Reserved

0

Reserved

Pattern Start Point

RW

Pattern Start Point:

Number of bytes after SFD where comparison begins on RX

packets to the configured pattern.

00000 = Start compare on 1st byte after SFD

00001 = Start compare on 2nd byte after SFD

…

01100 = Start compare on 13th byte (Default)

Default setting is 0xC, which means the pattern comparision will

begin after source and destination addresses since they are

each 6 bytes.

107

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8.6.98 RXD3CLK Register 0x04E0 – RX_D3 Clock Control Register

图 125. RX_D3 Clock Control Register (RXD3CLK)

15

7

14

6

13

5

12

4

11

3

10

9

8

0

Reserved

RO-0

2

1

RX_D3 Clock Control

RW-Strap

表 121. RXD3CLK Field Descriptions

BIT

FIELD

TYPE

RW

DEFAULT DESCRIPTION

15:3

2:0

Reserved

0

Reserved

RX_D3 Clock Control

RW

Strap

RX_D3 Control:

000 = RX_D3 operation

011 = 50-MHz output clock (RMII Master mode)

8.6.99 LPS_CFG Register 0x04E5 – LPS Configuration Register

图 126. LPS Configuration Register (LPS_CFG)

15

14

13

12

11

10

9

8

Reserved

LPS Mode Selection

RW-00

RW-0000 00

7

6

5

4

3

2

1

0

Reserved

RW-1100 0011

表 122. LPS_CFG Register 0x04E5 – LPS Configuration Register

BIT

FIELD

TYPE

RW

DEFAULT DESCRIPTION

15:10

9:8

Reserved

0000 00

00

Reserved

LPS Mode Selection

RW

LPS Mode Selection:

00 = Reserved

01 = Reserved

10 = Reserved

11 = Sdn[1] scrambled stream

7:0

Reserved

RW

1100 0011 Reserved

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注

The following registers reside in the MMD1 register field. To access these registers, the

DEVID must be 0x1.

8.6.100 PMA_CTRL1 Register 0x0007 – MMD1 PMA Control Register #1

图 127. MMD1 PMA Control Register #1 (PMA_CTRL1)

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

Reserved

RO-0

PMA / PMD Type

RO-111101

表 123. PMA_CTRL1 Field Descriptions

BIT

FIELD

TYPE

RO

DEFAULT DESCRIPTION

15:6

5:0

Reserved

0

Reserved

PMA / PMD Type

RO

111101

100BASE-T1

8.6.101 PMA_EXT1 Register 0x000B – MMD1 PMA Extended Ability Register #1

图 128. MMD1 PMA Extended Ability Register #1 (PMA_EXT1)

15

14

13

12

11

10

9

8

0

Reserved

RO-0

100BASE-T1

Extended

Abilities

PMA / PMD Type

RO-1

3

RO-0

1

7

6

5

4

2

PMA / PMD Type

RO-0

表 124. PMA_EXT1 Field Descriptions

BIT

FIELD

TYPE

RO

DEFAULT DESCRIPTION

15:12

11

Reserved

0

1

Reserved

100BASE-T1 Extended Abilities

RO

Extended Abilities:

1 = PHY able to perform extended abilities listed in register 0x12

within MMD1

0 = PHY unable to perform extended abilities listed in register

0x12 within MMD1

10:0

PMA / PMD Type

RO

0

Reserved

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8.6.102 PMA_EXT2 Register 0x0012 – MMD1 PMA Extended Ability Register #2

图 129. MMD1 PMA Extended Ability Register #2 (PMA_EXT2)

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

Reserved

RO-0

0

Ability

RO-1

表 125. PMA_EXT2 Field Descriptions

BIT

FIELD

TYPE

RO

DEFAULT DESCRIPTION

15:1

0

Reserved

0

1

Reserved

100BASE-T1 Ability

RO

100BASE-T1 Ability:

1 = PHY supports 100BASE-T1

0 = PHY does not support 100BASE-T1

8.6.103 PMA_CTRL2 Register 0x0834 – MMD1 PMA Control Register #2

图 130. MMD1 PMA Control Register #2 (PMA_CTRL2)

15

14

13

5

12

4

11

3

10

2

9

1

8

0

Reserved

RO-1

Master / Slave

RW/Strap

Reserved

RO-0

7

6

Reserved

RO-0

表 126. PMA_CTRL2 Field Descriptions

BIT

15

FIELD

Reserved

TYPE

DEFAULT DESCRIPTION

RO

1

Reserved

14

100BASE-T1 Master / 100BASE-T1 RW

Slave Configuration

Strap

100BASE-T1 Master / 100BASE-T1 Slave Configuration:

1 = PHY configured as a 100BASE-T1 Master

0 = PHY configured as a 100BASE-T1 Slave

13:0

Reserved

RO

0

Reserved

8.6.104 TEST_CTRL Register 0x0836 – MMD1 100BASE-T1 PMA Test Control Register

图 131. MMD1 100BASE-T1 PMA Test Control Register (TEST_CTRL)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

100BASE-T1 Test Modes

RW/Strap-000

4

3

Reserved

RO-0

表 127. TEST_CTRL Field Descriptions

BIT

FIELD

100BASE-T1 Test Modes

TYPE

DEFAULT DESCRIPTION

15:4

RW

Strap

100BASE-T1 Test Mode Control:

000 = Normal operation

001 = Test Mode 1

010 = Test Mode 2

100 = Test Mode 4

101 = Test Mode 5

3:0

Reserved

RO

0

Reserved

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9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DP83TC811R-Q1 is a single-port 100-Mbps Automotive Ethernet PHY. It supports IEEE 802.3bw and allows

for connections to an Ethernet MAC through MII, RMII, or RGMII. When using the device for Ethernet

applications, it is necessary to meet certain requirements for normal operation. The following subsections are

intended to assist in appropriate component selection and required connections.

9.2 Typical Applications

图 132 through 图 135 show some the typical applications for the DP83TC811R-Q1.

DC

Blocking

TX_CLK

TX_D[3:0]

TX_EN

CMC

4

TRD_P

TRD_N

Automotive

Connector

LPF

ESD

RX_CLK

RX_D[3:0]

RX_DV

(optional) (optional)

CM

Termination

VDDIO

Media Access Controller

DP83TC811

MDIO

MDC

MDI

Coupling

ESD

Shunt

EN

WAKE

INT

GND

图 132. Typical Application (MII)

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Typical Applications (接下页)

DC

Blocking

CMC

2

TRD_P

TRD_N

TX_D[1:0]

TX_EN

Automotive

Connector

LPF

ESD

(optional) (optional)

CM

Termination

RX_D[1:0]

CRS_DV

VDDIO

Media Access Controller

DP83TC811

MDIO

MDC

MDI

Coupling

ESD

Shunt

EN

WAKE

INT

GND

RMII Reference Clock

XI

50-MHz

Reference

Clock

图 133. Typical Application (RMII Slave)

DC

Blocking

CMC

2

TRD_P

TRD_N

TX_D[1:0]

TX_EN

Automotive

Connector

LPF

ESD

(optional) (optional)

CM

Termination

RX_D[1:0]

CRS_DV

VDDIO

Media Access Controller

DP83TC811

MDIO

MDC

MDI

Coupling

ESD

Shunt

EN

WAKE

INT

GND

25-MHz

Reference

Clock

XI

RMII Reference Clock

RX_D3 (50-MHz)

图 134. Typical Application (RMII Master)

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Typical Applications (接下页)

DC

Blocking

TX_CLK

TX_D[3:0]

TX_EN

CMC

4

TRD_P

TRD_N

Automotive

Connector

LPF

ESD

RX_CLK

RX_D[3:0]

RX_DV

4

(optional) (optional)

CM

Termination

VDDIO

Media Access Controller

DP83TC811

MDIO

MDC

MDI

Coupling

ESD

Shunt

EN

WAKE

INT

GND

图 135. Typical Application (RGMII)

An optional external low-pass filter may be added to reduce radiated emissions and improve radiated immunity.

Suggested values are located in 表 128.

GND

C3

R1

R2

C1

C2

L1

L2

TRD+

DP83TC811

To CMC

TRDœ

C4

GND

图 136. MDI Low-Pass Filter

9.2.1 Design Requirements

For these typical applications, use the following as design parameters:

表 128. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

V_DDIO

V_DDA

1.8 V, 2.5 V, or 3.3 V

3.3 V

(1)

Decoupling capacitors V_DDIO

10 nF, 100 nF, 1 μF, 10 μF

1 kΩ at 100 MHz (BLM18AG102SH)

10 nF, 100 nF, 1 μF, 10 μF

1 kΩ at 100 MHz (BLM18AG102SH)

0.1 μF

(Optional) ferrite bead for V_DDIO

(1)

Decoupling capacitors V_DDA

(Optional) ferrite bead for V_DDA

(2)

DC Blocking Capacitors

(1) 10% tolerance components are recommended.

(2) 1% tolerance components are recommended.

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表 128. Design Parameters (接下页)

DESIGN PARAMETER

EXAMPLE VALUE

200 μH

Common-Mode Choke

Common Mode Termination Resistors⁽²⁾

1 kΩ

(1)

MDI Coupling Capacitor

4.7 nF

ESD Shunt⁽¹⁾

(Optional) MDI Low-Pass Filter⁽³⁾

Reference Clock

100 kΩ

120 nH (L1 and L2), 47 pF (C3 and C4), 22 pF (C1

and C2), 27 Ω (R1 and R2)

25 MHz

(3) 2% tolerance components are recommended.

9.2.1.1 Physical Medium Attachment

There must be no metal running beneath the common-mode choke. CMCs can inject noise into metal beneath

them, which can affect the emissions and immunity performance of the system. Because the DP83TC811R-Q1 is

a voltage mode line driver, no external termination resistors are required. The ESD shunt and MDI coupling

capacitor should be connected to ground. Ensure that the common mode termination resistors are 1% tolerance

or better to improve differential coupling.

9.2.1.1.1 Common-Mode Choke Recommendations

The following CMCs have been tested with the DP83TC811R-Q1:

表 129. Recommended CMCs

MANUFACTURER

Pulse Electronics

Murata

PART NUMBER

AE2002

DLW43MH201XK2L

DLW32MH201XK2

ACT45L-201

Murata

TDK

ACT1210L-201

表 130. CMC Electrical Specifications

PARAMETER

TYP

–0.5

–1.0

–26

–20

–24

–42

–25

–70

–50

–24

UNITS

dB

CONDITIONS

1 – 30 MHz

30 – 60 MHz

1 – 30 MHz

30 – 60 MHz

1 MHz

Insertion Loss

dB

Return Loss

dB

Common-Mode Rejection

dB

10 – 100 MHz

400 MHz

dB

1 – 10 MHz

100 MHz

Differential Common-Mode Rejection

dB

1000 MHz

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9.2.2 Detailed Design Procedure

When creating a new system design with an Ethernet PHY, follow this schematic capture procedure:

1. Select desired PHY hardware configurations in 表 18.

2. Use the Electrical Characteristics table and 表 17 to select the correct external bootstrap resistors.

3. If using LEDs, ensure the correct external circuit is applied as shown in 图 28.

4. Select an appropriate clock source that adheres to either the CMOS-level oscillator or crystal resonator

requirements within the Electrical Characteristics table.

5. Select a CMC, a list of recommended CMCs are located in 表 129.

6. Add common-mode termination, DC-blocking capacitors, an MDI-coupling capacitor, and an ESD shunt

found in 表 128.

7. Ensure that there is sufficient supply decoupling on VDDIO and VDDA supply pins.

8. Add an external pullup resistor (tie to VDDIO) on MDIO line.

9. If sleep modes are not desired, WAKE and EN pins should be tied to VDDIO directly or through an external

pullup resistor.

The following layout procedure should be followed:

1. Locate the PHY near the edge of the board so that short MDI traces can be routed to the desired connector.

2. Place the MDI external components: CMC, DC-blocking capacitors, CM termination, MDI-coupling capacitor,

and ESD shunt.

3. Create a top-layer metal pour keepout under the CMC.

4. Ensure that the MDI TRD_M and TRD_P traces are routed such that they are 100-Ω differential.

5. Place the clock source near the XI and XO pins.

6. Ensure that when configured for MII, RMII, or RGMII operation, the xMII pins are routed 50-Ω and are single-

ended with reference to ground.

7. Ensure that transmit path xMII pins are routed such that setup and hold timing does not violate the PHY

requirements.

8. Ensure that receive path xMII pins are routed such that setup and hold timing does not violate the MAC

requirements.

9. Place the MDIO pullup close to the PHY.

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9.2.3 Application Curves

The following curves were obtained using the DP83TC811EVM under nominal conditions.

图 137. MDI IDLE Stream

图 138. MDI IDLE Stream (Variable Persistence)

-35

-40

-45

-50

-55

-60

-65

-70

-10

-15

-20

-25

-30

Limit

Data

Limit

Data

0

20

40

60

80 100 120 140 160 180 200

Frequency (MHz)

0

10

20

30

40

50

60

70

Frequency (MHz)

D001

D002

图 139. MDI Mode Conversion

图 140. MDI Return Loss

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10 Power Supply Recommendations

The DP83TC811R-Q1 is capable of operating with a wide range of IO supply voltages (3.3 V, 2.5 V, or 1.8 V).

No power supply sequencing is required. The recommended power supply de-coupling network is shown in 图

141. For improved conducted emissions, an optional ferrite bead may be placed between the supply and the

PHY de-coupling network.

VDDA

10 nF 100 nF 1 µF 10 µF

DP83TC811

VDDIO

10 µF 1 µF 100 nF 10 nF

图 141. Recommended Supply De-Coupling Network

11 Layout

11.1 Layout Guidelines

11.1.1 Signal Traces

PCB traces are lossy and long traces can degrade signal quality. Traces should be kept short as possible.

Unless mentioned otherwise, all signal traces should be 50-Ω, single-ended impedance. Differential traces should

be 50-Ω single-ended and 100-Ω differential. Take care to ensure impedance is controlled throughout.

Impedance discontinuities will cause reflections leading to emissions and signal integrity issues. Stubs should be

avoided on all signal traces, especially differential signal pairs.

图 142. Differential Signal Trace Routing

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Layout Guidelines (接下页)

Within the differential pairs, trace lengths should be run parallel to each other and matched in length. Matched

lengths minimize delay differences, avoiding an increase in common mode noise and emissions. Length

matching is also important for MAC interface connections. All transmit signal traces should be length matched to

each other and all receive signal traces should be length matched to each other.

Ideally, there should be no crossover or vias on signal path traces. Vias present impedance discontinuities and

should be minimized when possible. Route trace pairs on the same layer. Signals on different layers should not

cross each other without at least one return path plane between them. Differential pairs should always have a

constant coupling distance between them. For convenience and efficiency, TI recommends routing critical signals

first (that is, MDI differential pairs, reference clock, and MAC IF traces).

11.1.2 Return Path

A general best practice is to have a solid return path beneath all signal traces. This return path can be a

continuous ground or DC power plane. Reducing the width of the return path can potentially affect the impedance

of the signal trace. This effect is more prominent when the width of the return path is comparable to the width of

the signal trace. Breaks in return path between the signal traces should be avoided at all cost. A signal crossing

a split plane may cause unpredictable return path currents and could impact signal quality and result in

emissions issues.

图 143. Power and Ground Plane Breaks

11.1.3 Metal Pour

All metal pours that are not signals or power must be tied to ground. There must be no floating metal in the

system, and there must be no metal between differential traces.

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Layout Guidelines (接下页)

11.1.4 PCB Layer Stacking

To meet signal integrity and performance requirements, minimum four-layer PCB is recommended. However, a

six-layer PCB and above should be used when possible.

图 144. Recommended PCB Layer Stack-Up

119

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11.2 Layout Example

There are two evaluation board references for the DP83TC811R-Q1; the DP83TC811EVM is a media converter

board specifically designed for interoperability and bit error rate testing while the DP83TC811SEVM is an xMII

board for MAC interface support and compliance testing.

图 145. DP83TC811R-Q1 MII / RMII / RGMII Layout Recommendation

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Layout Example (接下页)

图 146. MDI Low-Pass Filter Layout Recommendation

121

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12 器件和文档支持

12.1 接收文档更新通知

如需接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收

产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.2 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.3 商标

PHYTER, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

122

PACKAGE OUTLINE

RND0036A

VQFN - 0.9 mm max height

SCALE 2.300

PLASTIC QUAD FLATPACK - NO LEAD

6.1

5.9

A

B

0.15

0.05

0.00

PIN 1 ID

(0.15)

6.1

5.9

DETAIL

A

S

C

A

L

E

2

0

.

0

DETAIL A

TYPICAL

(

5.75)

0.2

0.1

(0.15)

DETAIL

B

S

C

A

L

E

2

0

.

0

DETAIL B

TYPICAL

SEE DETAIL A

0.9 MAX

C

SEATING PLANE

0.08 C

(0.2)

SEE DETAIL B

18

4X (45 X0.42)

10

9

19

4X

SYMM

3.7 0.1

4

1

27

0.3

0.2

32X 0.5

36X

36

28

0.1

C B

A

PIN 1 ID

(R0.2)

SYMM

0.05

C

0.5

36X

0.3

4221715/A 09/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RND0036A

VQFN - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.7)

SYMM

36

28

36X (0.6)

36X (0.25)

1

27

4X

(1.6)

SYMM

(5.8)

32X (0.5)

9

19

(

0.2) TYP

VIA

18

10

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL

UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4221715/A 09/2014

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RND0036A

VQFN - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(5.8)

(1.78)

36

28

36X (0.6)

36X (0.25)

1

27

32X (0.5)

(5.8)

SYMM

(1.78)

METAL

TYP

9

19

4X ( 1.58)

18

10

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

73% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

4221715/A 09/2014

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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型号：	DP83TC811RWRNDRQ1
厂家：	TEXAS INSTRUMENTS
描述：	低功耗 100BASE-T1 汽车 PHYTER™ 以太网物理层收发器 \| RND \| 36 \| -40 to 125 以太网以太网：16GBASE-T 电信电信集成电路
文件：	总128页 (文件大小：1829K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DP83TC811RWRNDRQ1 [TI]

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