DPA02259RVER [TI]
1.5V 至 18V、8A 同步 SWIFT™ 降压转换器 | RVE | 28 | -40 to 85;
| 型号： | DPA02259RVER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.5V 至 18V、8A 同步 SWIFT™ 降压转换器 | RVE | 28 | -40 to 85 转换器 |
| 文件： | 总33页 (文件大小：1852K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS53513
www.ti.com
SLUSBP9A –SEPTEMBER 2013–REVISED DECEMBER 2013
1.5 to 18 V (4.5 to 25 V bias) Input, 8-A Single Synchronous Step-Down SWIFT™
Converter
1
FEATURES
APPLICATIONS
2
•
Integrated 13.8 and 5.9 mΩ MOSFETs With 8-A
Continuous Output Current
•
•
Server and Cloud-Computing POLs
Broadband, Networking, and Optical
Communications Infrastructure
•
•
•
•
Supports All Ceramic Output Capacitors
Reference Voltage 600 mV ±0.5% Tolerance
Output Voltage Range: 0.6 V to 5.5 V
•
•
I/O Supplies
Supported at the WEBENCH™ Design Center
D-CAP3™ Control Mode With Fast Load-Step
Response
DESCRIPTION
The TPS53513 is a small-sized, synchronous buck
converter with an adaptive on-time D-CAP3 control
mode. The device offers ease-of-use and low
external-component count for space-conscious power
systems.
•
•
•
Auto-Skipping Eco-mode™ for High Light-
Load Efficiency
FCCM for Tight Output Ripple and Voltage
Requirements
Eight Selectable Frequency Settings from
200 kHz to 1 MHz
This device features high-performance integrated
MOSFETs, accurate 0.5% 0.6-V reference, and an
integrated boost switch. Competitive features include
very-low external-component count, fast load-
transient response, auto-skip mode operation,
internal soft-start control, and no requirement for
compensation
•
•
•
•
Pre-Charged Startup Capability
Built-in Output Discharge Circuit
Open-Drain Power-Good Output
3.5-mm × 4.5-mm, 28-Pin, QFN Package
A forced continuous conduction mode helps meet
tight voltage regulation accuracy requirements for
performance DSPs and FPGAs. The TPS53513 is
available in a 28-pin QFN package and is specified
from –40°C to 85°C ambient temperature.
PGOOD
VIN
23
22 21 20
19
TPS53513
5
18
17
16
15
24 VO
.
.
PGND 14
PGND 13
PGND 12
PGND 11
PGND 10
25 TRIP
26 DNC
27 GND1
28 GND2
EFFICIENCY
100
1
2
3
4
6
7
8
9
VOUT
90
80
EN
Thermal
Pad
VREG
fSW = 500 KHz, VIN = 12 V, VDD = 5 V
TA = 25°C, L OUT = 1 ꢀH, Mode = Auto-skip
70
60
VOUT = 0.6 V
VOUT = 1 V
VOUT= 1.5 V
V= 1.2 V
OUT
V
OUT
= 1.8 V
V
= 2.5 V
OUT
V
= 3.3 V
V
= 5 V
OUT
OUT
0
2
4
6
8
10
12
Output Current (A)
C003
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
SWIFT, D-CAP3, Eco-mode, WEBENCH are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TPS53513
SLUSBP9A –SEPTEMBER 2013–REVISED DECEMBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
MIN
UNIT
MAX
7.7
30
32
36
6
EN
–0.3
–3
DC
SW
Transient < 10 ns
–5
VBST
–0.3
–0.3
Input voltage range(2)
VBST(3)
V
V
VBST when transient < 10 ns
VDD
38
28
30
6
–0.3
–0.3
–0.3
–0.3
–0.3
–40
VIN
VO, FB, MODE, RF
PGOOD
7.7
6
Output voltage range
Temperature
VREG, TRIP
Junction, TJ
Storage, Tstg
150
150
°C
°C
–55
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) Voltage values are with respect to the SW terminal.
THERMAL INFORMATION
TPS53513
THERMAL METRIC(1)
RVE
28 PINS
37.5
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
34.1
18.1
°C/W
ψJT
1.8
ψJB
18.1
θJCbot
2.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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TPS53513
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SLUSBP9A –SEPTEMBER 2013–REVISED DECEMBER 2013
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
–0.1
–3
MAX
7
UNIT
EN
SW
27
28
5.5
25
18
5.5
7
VBST
VBST(1)
–0.1
–0.1
4.5
Input voltage range
V
VDD
VIN
1.5
VO, FB, MODE, RF
PGOOD
–0.1
–0.1
–0.1
–40
Output voltage range
TA
V
VREG, TRIP
5.5
85
Operating free-air temperature
°C
(1) Voltage values are with respect to the SW pin.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VREG = 5 V, EN = 5 V (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C, No load
Power conversion enabled (no switching)
IVDD
VDD bias current
1350
850
1850
µA
TA = 25°C, No load
Power conversion disabled
IVDDSTBY
IVIN(leak)
VDD standby current
VIN leakage current
1150
0.5
µA
µA
VEN = 0 V
VREF OUTPUT
VVREF
Reference voltage
FB w/r/t GND, TA = 25°C
597
–0.6%
–0.7%
600
603
0.5%
0.5%
mV
FB w/r/t GND, TJ = 0°C to 85°C
FB w/r/t GND, TJ = –40°C to 85°C
VVREFTOL Reference voltage tolerance
OUTPUT VOLTAGE
IFB
FB input current
VFB = 600 mV
50
12
100
15
nA
IVODIS
VO discharge current
VVO = 0.5 V, Power Conversion Disabled
10
mA
SMPS FREQUENCY
VIN = 12 V, VVO = 3.3 V, RDR < 0.041
VIN = 12 V, VVO = 3.3 V, RDR = 0.096
VIN = 12 V, VVO = 3.3 V, RDR = 0.16
VIN = 12 V, VVO = 3.3 V, RDR = 0.229
VIN = 12 V, VVO = 3.3 V, RDR = 0.297
VIN = 12 V, VVO = 3.3 V, RDR = 0.375
VIN = 12 V, VVO = 3.3 V, RDR = 0.461
VIN = 12 V, VVO = 3.3 V, RDR > 0.557
TA = 25°C(2)
250
300
400
500
600
750
850
1000
60
fSW
VO switching frequency(1)
kHz
tON(min)
Minimum on-time
Minimum off-time
ns
ns
tOFF(min)
TA = 25°C
175
240
310
INTERNAL BOOTSTRAP SW
VF
Forward Voltage
VVREG–VBST, TA = 25°C, IF = 10 mA
TA = 25°C, VVBST = 33 V, VSW = 28 V
0.15
0.01
0.25
1.5
V
IVBST
VBST leakage current
µA
(1) Resistor divider ratio (RDR) is described in Equation 1.
(2) Specified by design. Not production tested.
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TPS53513
SLUSBP9A –SEPTEMBER 2013–REVISED DECEMBER 2013
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VREG = 5 V, EN = 5 V (unless otherwise noted)
PARAMETER
LOGIC THRESHOLD
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VENH
EN enable threshold voltage
EN disable threshold voltage
EN hysteresis voltage
1.3
1.1
1.4
1.2
0.22
0
1.5
1.3
V
V
VENL
VENHYST
VENLEAK
V
EN input leakage current
–1
1
µA
SOFT START
tSS
Soft-start time
1
ms
PGOOD COMPARATOR
PGOOD in from higher
104%
89%
113%
80%
4
108%
92%
116%
84%
6
111%
96%
PGOOD in from lower
PGOOD out to higher
PGOOD out to lower
VPGOOD = 0.5 V
VPGTH
VDDQ PGOOD threshold
120%
87%
IPG
PGOOD sink current
PGOOD delay time
mA
ms
µs
Delay for PGOOD going in
Delay for PGOOD coming out
VPGOOD = 5 V
0.8
1.0
2
1.2
1
tPGDLY
IPGLK
PGOOD leakage current
–1
0
µA
CURRENT DETECTION
RTRIP TRIP pin resistance range
20
6.2
50
9.8
kΩ
RTRIP = 34.8 kΩ
RTRIP = 25.5 kΩ
RTRIP = 34.8 kΩ
RTRIP = 25.5 kΩ
8.0
6.2
IOCL
Current limit threshold, valley
A
4.2
8.2
–10.5
–8.7
–7.9
–6.1
0
–5.3
–3.5
Negative current limit threshold,
valley
IOCLN
VZC
A
Zero cross detection offset
mV
PROTECTIONS
Wake-up
3.25
3.00
3.34
3.12
3.41
3.19
VREG undervoltage-lockout
(UVLO) threshold voltage
VVREGUVLO
V
V
Shutdown
Wake-up (default)
Shutdown
4.15
4.25
4.35
VVDDUVLO VDD UVLO threshold voltage
3.95
4.05
4.15
VOVP
Overvoltage-protection (OVP)
threshold voltage
OVP detect voltage
116%
120%
124%
tOVPDLY
VUVP
OVP propagation delay
With 100-mV overdrive
UVP detect voltage
300
ns
Undervoltage-protection (UVP)
threshold voltage
64%
68%
71%
tUVPDLY
UVP delay
UVP filter delay
1
ms
°C
THERMAL SHUTDOWN
Shutdown temperature
Hysteresis
140
40
TSDN
Thermal shutdown threshold(3)
LDO VOLTAGE
VREG
LDO output voltage
VIN = 12 V, ILOAD = 10 mA
VIN = 4.5 V, ILOAD = 30 mA, TA = 25°C
VIN = 12 V, TA = 25°C
4.65
170
5
5.45
365
V
VDOVREG
ILDOMAX
LDO low droop drop-out voltage
LDO over-current limit
mV
mA
200
INTERNAL MOSFETS
RDS(on)H High-side MOSFET on-resistance
RDS(on)L Low-side MOSFET on-resistance
TA = 25°C
TA = 25°C
13.8
5.9
15.5
7.0
mΩ
mΩ
(3) Specified by design. Not production tested.
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TPS53513
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SLUSBP9A –SEPTEMBER 2013–REVISED DECEMBER 2013
DEVICE INFORMATION
RVE PACKAGE
28-PIN
(TOP VIEW)
28
27
26
25
24
1
2
3
4
5
6
7
8
9
23
22
21
20
19
18
17
16
15
RF
PGOOD
EN
FB
GND
MODE
VREG
VDD
NC
VBST
NC
TPS53513
SW
SW
VIN
SW
VIN
Thermal Pad
SW
VIN
10
11
12
13
14
PIN DESCRIPTIONS
PIN
I/O(1) DESCRIPTION
NAME
EN
NO.
3
I
I
The enable pin turns on the DC-DC switching converter.
FB
23
VOUT feedback input. Connect this pin to a resistor divider between the VOUT pin and GND.
This pin is the ground of internal analog circuitry and driver circuitry. Connect GND to the PGND plane
with a short trace (For example, connect this pin to the thermal pad with a single trace and connect the
thermal pad to PGND pins and PGND plane).
GND
22
G
GND1
GND2
27
28
I
I
Connect this pin to ground. GND1 is the input of unused internal circuitry and must connect to ground.
Connect this pin to ground. GND2 is the input of unused internal circuitry and must connect to ground.
The MODE pin sets the forced continuous-conduction mode (FCCM) or Skip-mode operation. It also
selects the ramp coefficient of D-CAP3 mode.
MODE
21
I
5
NC
—
O
Not connected. These pins are floating internally.
18
26
10
11
12
13
14
DNC
Do not connect. This pin is the output of unused internal circuitry and must be floating.
PGND
G
These ground pins are connected to the return of the internal low-side MOSFET.
Open-drain power-good status signal which provides startup delay after the FB voltage falls within the
specified limits. After the FB voltage moves outside the specified limits, PGOOD goes low within 2 µs.
PGOOD
RF
2
1
O
I
RF is the SW-frequency configuration pin. Connect this pin to a resistor divider between VREG and
GND to program different SW frequency settings.
6
7
8
9
SW
I/O SW is the output switching terminal of the power converter. Connect this pin to the output inductor.
(1) I = Input, O = Output, P = Supply, G = Ground
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TPS53513
SLUSBP9A –SEPTEMBER 2013–REVISED DECEMBER 2013
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PIN DESCRIPTIONS (continued)
PIN
I/O(1) DESCRIPTION
NAME
NO.
TRIP is the OCL detection threshold setting pin. ITRIP = 10 µA at room temp, 3000 ppm/°C current is
TRIP
25
I/O sourced and sets the OCL trip voltage. See the Current Sense and Overcurrent Protection section for
detailed OCP setting.
VBST is the supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor
from this pin to the SW node. Internally connected to VREG via bootstrap PMOS switch.
VBST
VDD
4
P
19
15
16
17
20
24
P
P
Power-supply input pin for controller. Input of the VREG LDO. The input range is from 4.5 to 25 V.
VIN is the conversion power-supply input pins.
VIN
VREG
VO
O
I
VREG is the 5-V LDO output. This voltage supplies the internal circuitry and gate driver.
VOUT voltage input to the controller.
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TPS53513
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SLUSBP9A –SEPTEMBER 2013–REVISED DECEMBER 2013
BLOCK DIAGRAM
PGOOD
+
+
0.6 V + 8/16%
0.6 V ± 32%
+
UV
+
Delay
Delay
OV
0.6 V ± 8/16%
0.6 V+20%
VREG
Internal Ramp
Control Logic
RF
0.6 V
SS
UVP / OVP
Logic
+
+
PWM
OCP
VBST
VIN
VFB
10 µA
GND
LL
+
+
1 SHOT
TRIP
SW
XCON
+
ZC
Control
Logic
PGND
PGND
VO
SW
xꢀ On/Off time
xꢀ Minimum On/Off
xꢀ Light load
FCCM / SKIP
RC time Constant
MODE
Fault
Shut Down
LDO
VREG
xꢀ OVP/UVP
xꢀ FCCM/SKIP
xꢀ Soft-Start
+
VREGOK
3.34 V /
3.12 V
+
VDD
DNC
+
EN
VDDOK
THOK
Enable
4.3 V /
4.03 V
1.4 V / 1.2 V
+
GND
GND1
GND2
140°C /
100°C
TPS53513
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TPS53513
SLUSBP9A –SEPTEMBER 2013–REVISED DECEMBER 2013
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APPLICATION CIRCUIT DIAGRAM
R1
PGOOD
6.65 Nꢀ
R2
C3
C4
2 kꢀꢀ
Thermal
R6
1 µF
1 µF
VIN
Pad
150 Nꢀ
CIN
2.2 nF
CIN
3 × 22 µF
23
22
21
20
19
18
17
16
15
24 VO
PGND 14
PGND 13
PGND 12
PGND 11
PGND 10
25 TRIP
26 DNC
27 GND1
28 GND2
R8
34.8 Nꢀ
TPS53513
1
2
3
4
5
6
7
8
9
PIMB065T±1R0MS-63
VOUT
R4
249 Nꢀ
R10
100 Nꢀ
1 µH
R7
C2
R3
3 ꢀ
Thermal Pad
0 ꢀꢀ 0.1 µF
COUT
COUT
4 × 10 µF
6 × 22 µF
R5
105 Nꢀ
VREG
EN
C1
470 pF
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SLUSBP9A –SEPTEMBER 2013–REVISED DECEMBER 2013
TYPICAL CHARACTERISTICS
100
90
100
90
80
80
fSW = 500 KHz, VIN = 12 V, VDD = 5 V
fSW = 500 KHz, VIN = 12 V, VDD = 5 V
TA = 25°C, L OUT = 1 ꢀH, Mode = Auto-skip
TA = 25°C, L OUT = 1 ꢀH, Mode = FCCM
70
70
V
VOUT = 0.6 V
VOUT = 1 V
V
VOUT = 0.6 V
VOUT = 1 V
V= 1.2 V
VOUT= 1.5 V
V= 1.2 V
VOUT= 1.5 V
OUT
OUT
V
OUT
= 1.8 V
V
= 2.5 V
V
OUT
= 1.8 V
V
= 2.5 V
OUT
OUT
V
= 3.3 V
V
= 5 V
V
= 3.3 V
V
= 5 V
OUT
OUT
OUT
OUT
60
60
0
0
0
2
4
6
8
10
12
0
0
0
2
4
6
8
10
12
Output Current (A)
Output Current (A)
C003
C004
Figure 1. Efficiency vs. Output Current
Figure 2. Efficiency vs. Output Current
100
90
80
70
60
50
100
90
80
70
60
50
f
SW = 1 MHz, VIN = 12 V, VDD = 5 V
TA = 25°C, L OUT = 1 ꢀH, Mode = Auto-Skip
f
SW = 1 MHz, VIN = 12 V, VDD = 5 V
TA = 25°C, L OUT = 1 ꢀH, Mode = FCCM
OUT
V = 2.5 V
OUT
VOUT = 0.6 V VOUT = 1 V
VOUT = 0.6 V VOUT = 1 V
= 1.2 V
OUT
V
V
V
= 1.2 V
V
V
V
= 1.5 V
V
V
V
V
= 1.5 V
OUT
= 2.5 V
OUT
= 1.8 V
= 1.8 V
OUT
OUT
OUT
= 3.3 V
= 5 V
= 3.3 V
V
= 5 V
OUT
OUT
OUT
OUT
2
4
6
8
10
12
2
4
6
8
10
12
Output Current (A)
Output Current (A)
C005
C006
Figure 3. Efficiency vs. Output Current
Figure 4. Efficiency vs. Output Current
1.3
1.25
1.2
1.3
1.25
1.2
fSW = 500 KHz
VDD = 5 V
VOUT = 1.2 V
TA = 25°C
LOUT = 1 ꢀH
fSW = 1 MHz
VDD = 5 V
VOUT = 1.2 V
TA = 25°C
LOUT = 1 ꢀH
Mode = Auto-skip
Mode = Auto-skip
1.15
1.1
1.15
1.1
VIN=5V
VIN=5V
VIN = 12 V
VIN = 12 V
VIN = 18 V
VIN = 18 V
10 12
2
4
6
8
10
12
2
4
6
8
Output Current (A)
Output Current (A)
C007
C008
Figure 5. Output Voltage vs. Output Current
Figure 6. Output Voltage vs. Output Current
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TYPICAL CHARACTERISTICS (continued)
1.3
1.25
1.2
1.3
1.25
1.2
fSW = 500 KHz
VDD = 5 V
TA = 25°C
LOUT = 1 ꢀH
Mode = FCCM
VOUT = 1.2 V
fSW = 1 MHz
VDD = 5 V
TA = 25°C
LOUT = 1 ꢀH
Mode = FCCM
VOUT = 1.2 V
1.15
1.1
1.15
1.1
VIN=5V
VIN=5V
VIN = 12 V
VIN = 12 V
VIN = 18 V
VIN = 18 V
0
2
4
6
8
10
12
0
2
4
6
8
10
12
Output Current (A)
Output Current (A)
C009
C010
Figure 7. Output Voltage vs. Output Current
Figure 8. Output Voltage vs. Output Current
1200
1000
800
600
550
500
450
400
fSW = 500 kHz
VDD = 5 V
VOUT = 1.2 V
TA = 25°C
LOUT = 1 ꢀH
Mode = FCCM
VIN = 12 V, VDD = 5 V, TA = 25°C
LOUT = 1 ꢀH, Mode = FCCM, VOUT = 1.2 V
fSW = 250 KHz
fSW=500KHz
fSW=1MHz
600
VIN=5V
400
VIN = 12 V
VIN = 18 V
200
1
2
3
4
5
6
7
8
9
10 11 12
1
2
3
4
5
6
7
8
9
10 11 12
Output Current (A)
Output Current (A)
C011
C012
Figure 9. Switching Frequency vs. Output Current
Figure 10. Switching Frequency vs. Output Current
100
85
100
85
70
70
55
40
25
55
40
25
V
IN = VDD = 18 V
V
IN = VDD = 18 V
VOUT = 1.2 V
fSW = 1 MHz
LOUT = 1 µH
VOUT = 5 V
fSW = 1 MHz
LOUT = 1 µH
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Output Current (A)
Figure 11. Safe Operating Area, VOUT = 1.2 V
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Output Current (A)
Figure 12. Safe Operating Area, VOUT = 5 V
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TYPICAL CHARACTERISTICS (continued)
VIN = 12 V
VIN = 12 V
VOUT = 1.2 V
Fsw = 1 MHz
VOUT = 1.2 V
Fsw = 1 MHz
Mode = Auto-skip
IOUT = 0 A
Mode = FCCM
IOUT = 0 A
Figure 13. Auto-Skip Steady-State Operation
Figure 14. FCCM Steady-State Operation
VIN = 12 V
VIN = 12 V
VOUT = 1.2 V
Fsw = 1 MHz
VOUT = 1.2 V
Fsw = 1 MHz
Mode = Auto-skip
IOUT = 0.1 A
Mode = FCCM
IOUT = 0.1 A
Figure 15. Auto-Skip Steady-State Operation
Figure 16. FCCM Steady-State Operation
VIN = 12 V
VIN = 12 V
VOUT = 1.2 V
Fsw = 1 MHz
VOUT = 1.2 V
Fsw = 1 MHz
Mode = Auto-skip
IOUT = 6 A
Mode = FCCM
IOUT = 6 A
Figure 17. Auto-Skip Steady-State Operation
Figure 18. FCCM Steady-State Operation
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TYPICAL CHARACTERISTICS (continued)
VIN = 12 V
VIN = 12 V
VOUT = 1.2 V
Fsw = 1 MHz
VOUT = 1.2 V
Fsw = 1 MHz
Mode = Auto-skip
Idyn = 0 A to 6 A
Mode = FCCM
Idyn = 0 A to 6 A
Figure 19. Auto-Skip Mode Load Transient
Figure 20.
VIN = 12 V
VIN = 12 V
VOUT = 1.2 V
Fsw = 1 MHz
VOUT = 1.2 V
Fsw = 1 MHz
Mode = Auto-skip
IOUT = 0 A
Mode = FCCM
IOUT = 0 A
Figure 21. Start-Up
Figure 22. Start-Up
VIN = 12 V
VIN = 12 V
VOUT = 1.2 V
Fsw = 1 MHz
VOUT = 1.2 V
Fsw = 1 MHz
Mode = Auto-skip
IOUT = 6 A
Mode = FCCM
IOUT = 6 A
Figure 23. Start-Up
Figure 24. Start-Up
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TYPICAL CHARACTERISTICS (continued)
VIN = 12 V
VIN = 12 V
VOUT = 1.2 V
Fsw = 1 MHz
VOUT = 1.2 V
Fsw = 1 MHz
Mode = Auto-skip
IOUT = 0 A
Mode = FCCM
IOUT = 0 A
Figure 25. Shut-Down Operation
Figure 26. Shut-Down Operation
VIN = 12 V
VIN = 12 V
VOUT = 1.2 V
Fsw = 1 MHz
VOUT = 1.2 V
Fsw = 1 MHz
Mode = Auto-skip
IOUT = 6 A
Mode = FCCM
IOUT = 6 A
Figure 27. Shut-Down Operation
Figure 28. Shut-Down Operation
VIN = 12 V
VOUT = 1.2 V
Fsw = 500 KHz
Mode = Auto-skip
IOUT = 0 A
VIN = 12 V
VOUT = 1.2 V
Fsw = 1 MHz
Mode = Auto-skip
IOUT = 0 A
Pre-bias = 0.6 V
Figure 29. Pre-Bias Operation
Figure 30. Overvoltage Protection
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TYPICAL CHARACTERISTICS (continued)
VIN = 12 V
VOUT = 1.2 V
Fsw = 500 MHz
Mode = FCCM
Figure 31. Overcurrent Protection
.
.
.
THERMAL PERFORMANCE
TA = 23°C, fSW = 500 kHz, VIN = 12 V, VOUT = 1.24 V, IOUT = 8 A, RBOOT= 0 Ω, SNB = 3 Ω + 470 pF
Inductor: LOUT = 1 µH, PIMB103T-1R0MS-63, 10 mm × 11.2 mm × 3 mm, 5.3 mΩ
Figure 32. SP1: 43℃ (TPS53513), SP2: 35.1℃ (Inductor)
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APPLICATION INFORMATION
General Description
The TPS53513 is a high-efficiency, single-channel, synchronous-buck converter. The device suits low-output
voltage point-of-load applications with 8-A or lower output current in computing and similar digital consumer
applications. The TPS53513 features proprietary D-CAP3 mode control combined with adaptive on-time
architecture. This combination builds modern low-duty-ratio and ultra-fast load-step-response DC-DC converters
in an ideal fashion. The output voltage ranges from 0.6 V to 5.5 V. The conversion input voltage ranges from
1.5 V to 18 V and the VDD input voltage ranges from 4.5 V to 25 V. The D-CAP3 mode uses emulated current
information to control the modulation. An advantage of this control scheme is that it does not require a phase-
compensation network outside which makes the device easy-to-use and also allows low-external component
count. Adaptive on-time control tracks the preset switching frequency over a wide range of input and output
voltage while increasing switching frequency as needed during load-step transient.
Frequency Selection
TPS53513 allows users to select the switching frequency by using the RF pin. Table 1 lists the divider ratio and
some example resistor values for the switching frequency selection. The 1% tolerance resistors with a typical
temperature coefficient of ±100 ppm/ºC are recommended. If the design requires a tighter noise margin for more
reliable SW-frequency detection, use higher performance resistors.
Table 1. Switching Frequency Selection
SWITCHING
FREQUENCY
(fSW) (kHz)
RESISTOR
EXAMPLE RF FREQUENCY COMBINATIONS
DIVIDER RATIO(1)
RRF_H (kΩ)
RRF_L (kΩ)
(RDR
)
1000
850
750
600
500
400
300
250
> 0.557
0.461
0.375
0.297
0.229
0.16
1
300
154
120
105
71.5
47.5
27
180
200
249
240
249
255
270
0.096
< 0.041
11.5
(1) Resistor divider ratio (RDR) is described in Equation 1.
space
RDR
RRF _L
=
R
(
+ RRF _H
)
RF _L
where
•
•
RRF_L is the low-side resistance of the RF pin resistor divider
RRF_H is the high-side resistance of the RF pin resistor divider
(1)
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D-CAP3 Control and Mode Selection
RR
SW
To comparator
CR
VOUT
Figure 33. Internal RAMP Generation Circuit
The TPS53513 uses D-CAP3 mode control to achieve fast load transient while maintaining the ease-of-use
feature. An internal RAMP is generated and fed to the VFB pin to reduce jitter and maintain stability. The
amplitude of the ramp is determined by the R-C time-constant as shown in Figure 33. At different switching
frequencies, (fSW) the R-C time-constant varies to maintain relatively constant RAMP amplitude.
D-CAP3 Mode
From small-signal loop analysis, a buck converter using the D-CAP3 mode control architecture can be simplified
as shown in Figure 34.
VO
SW
CC1
RC1
VIN
CC2
RC2
Sample
and Hold
DRVH
PWM
Comparator
Lx
RFBH
Control
Logic
and
G
+
+
VRAMP
VOUT
FB
DRVL
Driver
RCO
+
VREF
RLOAD
COUT
RFBL
Figure 34. D-CAP3 Mode
The D-CAP3 control architecture includes an internal ripple generation network enabling the use of very low-ESR
output capacitors such as multi-layered ceramic capacitors (MLCC). No external current sensing network or
voltage compensators are required with D-CAP3 control architecture. The role of the internal ripple generation
network is to emulate the ripple component of the inductor current information and then combine it with the
voltage feedback signal to regulate the loop operation. For any control topologies supporting no external
compensation design, there is a minimum and/or maximum range of the output filter it can support. The output
filter used with the TPS53513 is a lowpass L-C circuit. This L-C filter has double pole that is described in
Equation 2.
1
f =
P
2´ p´ L
´ C
OUT
OUT
(2)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS53513. The low frequency L-C double pole has a 180 degree in phase. At the output filter
frequency, the gain rolls off at a –40dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40dB to –20dB per
decade and increases the phase to 90 degree one decade above the zero frequency.
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The inductor and capacitor selected for the output filter must be such that the double pole of Equation 2 is
located close enough to the high-frequency zero so that the phase boost provided by the high-frequency zero
provides adequate phase margin for the stability requirement.
Table 2. Locating the Zero
SWITCHING
FREQUENCIES
(fSW) (kHz)
ZERO (fZ) LOCATION (kHz)
250 and 300
400 and 500
600 and 750
850 and 1000
6
7
9
12
After identifying the application requirements, the output inductance should be designed so that the inductor
peak-to-peak ripple current is approximately between 25% and 35% of the ICC(max) (peak current in the
application). Use Table 2 to help locate the internal zero based on the selected switching frequency. In general,
where reasonable (or smaller) output capacitance is desired, Equation 3 can be used to determine the necessary
output capacitance for stable operation.
1
f =
= f
Z
P
2´ p´ L
´ C
OUT
OUT
(3)
If MLCC is used, consider the derating characteristics to determine the final output capacitance for the design.
For example, when using an MLCC with specifications of 10-µF, X5R and 6.3 V, the deratings by DC bias and
AC bias are 80% and 50% respectively. The effective derating is the product of these two factors, which in this
case is 40% and 4-µF. Consult with capacitor manufacturers for specific characteristics of the capacitors to be
used in the system/applications.
Table 3 shows the recommended output filter range for an application design with the following specifications:
•
•
•
Input voltage, VIN = 12 V
Switching frequency, fSW = 600 kHz
Output current, IOUT = 8 A
The minimum output capacitance is verified by the small signal measurement conducted on the EVM using the
following two criteria:
•
•
Loop crossover frequency is less than one-half the switching frequency (300 kHz)
Phase margin at the loop crossover is greater than 50 degrees
For the maximum output capacitance recommendation, simplify the procedure to adopt an unrealistically high
output capacitance for this type of converter design, then verify the small signal response on the EVM using the
following one criteria:
•
Phase margin at the loop crossover is greater than 50 degrees
As indicated by the phase margin, the actual maximum output capacitance (COUT(max)) can continue to go higher.
However, small signal measurement (bode plot) should be done to confirm the design.
Select a MODE pin configuration as shown in Table 3 to double the R-C time-constant option for the maximum
output capacitance design and application. Select a MODE pin configuration to use single R-C time constant
option for the normal (or smaller) output capacitance design and application.
The MODE pin also selects Skip-mode or FCCM-mode operation.
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Table 3. Recommended Component Values
COUT(min) CROSS- PHASE COUT(max) INTERNAL
VOUT RLOWER RUPPER
LOUT
(µH)
INDUCTOR
ΔI/ICC(max)
ICC(max)
(A)
(µF)
OVER
(kHz)
MARGIN
(°)
(µF)
RC SETTING
(µs)
(V)
(kΩ)
(kΩ)
(1)
(1)
3 × 100
9 × 22
4 × 22
3 × 22
2 × 22
247
48
70
62
53
84
57
63
57
59
51
58
40
80
40
80
40
80
40
80
40
80
0.36
0.6
0
33%
33%
34%
33%
28%
PIMB065T-R36MS
30 x 100
30 x 100
30 x 100
30 x 100
30 x 100
207
25
0.68
1.2
2.5
3.3
5.5
10
PIMB065T-R68MS
185
11
1.2
10
31.6
45.3
82.5
8
PIMB065T-1R2MS
185
9
1.5
PIMB065T-1R5MS
185
7
2.2
PIMB065T-2R2MS
(1) All COUT(min) and COUT(max) capacitor specifications are 1206, X5R, 10 V.
For higher output voltage at or above 2.0 V, additional phase boost might be required in order to secure sufficient
phase margin due to phase delay/loss for higher output voltage (large on-time (tON)) setting in a fixed on time
topology based operation.
A feedforward capacitor placing in parallel with RUPPER is found to be very effective to boost the phase margin at
loop crossover. Refer to TI application note SLVA289 for details.
Table 4. Mode Selection and Internal RAMP R-C Time Constant
SWITCHING
FREQUENCIES
fSW (kHz)
MODE
SELECTION
RMODE
(kΩ)
R-C TIME
CONSTANT (µs)
ACTION
60
50
275
and
and
and
325
425
625
850
275
425
625
850
275
425
625
850
275
425
625
850
275
425
625
850
525
750
0
40
30
and 1000
Skip Mode
Pull down to GND
120
100
80
and
and
and
325
525
750
150
20
150
0
60
and 1000
60
and
and
and
325
525
750
50
40
30
and 1000
Connect to
PGOOD
FCCM(1)
120
100
80
and
and
and
325
525
750
60
and 1000
120
100
80
and
and
and
325
525
750
FCCM
Connect to VREG
60
and 1000
(1) Device goes into Forced CCM (FCCM) after PGOOD becomes high.
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Sample and Hold Circuitry
CSP
Sampled_CSP
Buffer 2
C1
C2
Buffer 1
Figure 35. Sample and Hold Logic Circuitry (Patent Pending)
The sample and hold circuitry is the difference between D-CAP3 and D-CAP2. The sample and hold circuitry,
which is an advance control scheme to boost output voltage accuracy higher on the TPS53513, is one of
features of the TPS53513. The sample and hold circuitry generates a new DC voltage of CSN instead of the
voltage which is produced by RC2 and CC2 which allows for tight output-voltage accuracy and makes the
TPS53513 more competitive.
CSP
CSN
CSP
CSN
CSN_NEW
(sample at valley of CSP)
CSN_NEW
(sample at valley of CSP)
Figure 36. Continuous Conduction Mode (CCM)
With Sample and Hold Circuitry
Figure 37. Discontinuous Conduction Mode (DCM)
With Sample and Hold Circuitry
CSP
CSN
CSP
CSN
Figure 38. Continuous Conduction Mode (CCM)
Without Sample and Hold Circuitry
Figure 39. Discontinuous Conduction Mode (DCM)
Without Sample and Hold Circuitry
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1.25
1.25
1.23
1.21
1.19
1.17
1.15
1.23
1.21
VIN = 12 V
1.19
VIN = 12 V
VDD = 5 V
VDD = 5 V
VOUT = 1.2 V
fSW = 500 kHz
TA = 25°C
LOUT = 1 ꢀH
VOUT = 1.2 V
fSW = 500 kHz
TA = 25°C
LOUT = 1 ꢀH
Mode = Auto-skip
1.17
D-CAP3
D-CAP2
D-CAP3
D-CAP2
Mode = FCCM
1.15
1
2
3
4
5
6
7
8
9
10 11 12
1
2
3
4
5
6
7
8
9
10 11 12
Output Current (A)
Output Current (A)
C013
C014
Figure 40. Output Voltage vs Output Current
Figure 41. Output Voltage vs Output Current
Auto-Skip Eco-mode™ Light Load Operation
While the MODE pin is pulled to GND directly or via 150-kΩ resistor, the TPS53513 automatically reduces the
switching frequency at light-load conditions to maintain high efficiency. This section describes the operation in
detail.
As the output current decreases from heavy load condition, the inductor current also decreases until the rippled
valley of the inductor current touches zero level. Zero level is the boundary between the continuous-conduction
and discontinuous-conduction modes. The synchronous MOSFET turns off when this zero inductor current is
detected. As the load current decreases further, the converter runs into discontinuous-conduction mode (DCM).
The on-time is maintained to a level approximately the same as during continuous-conduction mode operation so
that discharging the output capacitor with a smaller load current to the level of the reference voltage requires
more time. The transition point to the light-load operation IO(LL) (for example: the threshold between continuous-
and discontinuous-conduction mode) is calculated as shown in Equation 4.
V
- V
´ V
)
OUT OUT
V
IN
(
1
IN
I
=
´
OUT LL
( )
2´L ´ f
SW
where
•
fSW is the PWM switching frequency
(4)
Using only ceramic capacitors is recommended for Auto-skip mode.
Adaptive Zero-Crossing
The TPS53513 uses an adaptive zero-crossing circuit to perform optimization of the zero inductor-current
detection during skip-mode operation. This function allows ideal low-side MOSFET turn-off timing. The function
also compensates the inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit.
Adaptive zero-crossing prevents SW-node swing-up caused by too-late detection and minimizes diode
conduction period caused by too-early detection. As a result, the device delivers better light-load efficiency.
Forced Continuous-Conduction Mode
When the MODE pin is tied to the PGOOD pin through a resistor, the controller operates in continuous
conduction mode (CCM) during light-load conditions. During CCM, the switching frequency maintained to an
amost constant level over the entire load range which is suitable for applications requiring tight control of the
switching frequency at the cost of lower efficiency.
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Power-Good
The TPS53513 has power-good output that indicates high when switcher output is within the target. The power-
good function is activated after the soft-start operation is complete. If the output voltage becomes within ±8% of
the target value, internal comparators detect the power-good state and the power-good signal becomes high
after a 1-ms internal delay. If the output voltage goes outside of ±16% of the target value, the power-good signal
becomes low after a 2-μs internal delay. The power-good output is an open-drain output and must be pulled-up
externally.
Current Sense and Overcurrent Protection
The TPS53513 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF
state and the controller maintains the OFF state during the period that the inductor current is larger than the
overcurrent trip level. In order to provide good accuracy and a cost-effective solution, the TPS53513 supports
temperature compensated MOSFET RDS(on) sensing. Connect the TRIP pin to GND through the trip-voltage
setting resistor, RTRIP. The TRIP terminal sources ITRIP current, which is 10 μA typically at room temperature, and
the trip level is set to the OCL trip voltage VTRIP as shown in Equation 5.
VTRIP = RTRIP ´ITRIP
where
•
•
•
VTRIP is in mV
RTRIP is in kΩ
ITRIP is in µA
(5)
The inductor current is monitored by the voltage between the GND pin and SW pin so that the SW pin is properly
connected to the drain terminal of the low-side MOSFET. ITRIP has a 3000-ppm/°C temperature slope to
compensate the temperature dependency of RDS(on). The GND pin acts as the positive current-sensing node.
Connect the GND pin to the proper current sensing device, (for example, the source terminal of the low-side
MOSFET.)
Because the comparison occurs during the OFF state, VTRIP sets the valley level of the inductor current. Thus,
the load current at the overcurrent threshold, IOCP, is calculated as shown in Equation 6.
I
V
- V
´ V
)
OUT OUT
V
IN
(
V
V
TRIP
1
IND(ripple)
IN
TRIP
I
=
+
=
+
´
OCP
2
2´L ´ f
8´R
8´R
DS(on)L
SW
(
)
(
)
DS(on)
where
•
•
RDS(on)L is the on-resistance of the low-side MOSFET
RTRIP is in kΩ
(6)
Equation 6 calculates the typical DC OCP level (typical low-side on-resistance [RDS(on)] of 5.9 mΩ should be
used); in order to design for worst case minimum OCP, maximum low-side on-resistance value of 8 mΩ should
be used.
During an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the
output voltage tends to decrease. Eventually, the output voltage crosses the undervoltage-protection threshold
and shuts down.
For the TPS53513, the overcurrent protection maximum is recommended up to 12 A only.
Overvoltage and Undervoltage Protection
The TPS53513 monitors a resistor-divided feedback voltage to detect overvoltage and undervoltage. When the
feedback voltage becomes lower than 68% of the target voltage, the UVP comparator output goes high and an
internal UVP delay counter begins counting. After 1 ms, the TPS53513 latches OFF both high-side and low-side
MOSFETs drivers. The UVP function enables after soft-start is complete.
When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes
high and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching
a negative current limit. Upon reaching the negative current limit, the low-side FET is turned off and the high-side
FET is turned on again for a minimum on-time. The TPS53513 operates in this cycle until the output voltage is
pulled down under the UVP threshold voltage for 1 ms. After the 1-ms UVP delay time, the high-side FET is
latched off and low-side FET is latched on. The fault is cleared with a reset of VDD or by re-toggling EN pin.
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Out-Of-Bounds Operation (OOB)
The TPS53513 has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower
overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault, so
the device is not latched off after an OOB event. OOB protection operates as an early no-fault overvoltage-
protection mechanism. During the OOB operation, the controller operates in forced PWM mode only by turning
on the low-side FET. Turning on the low-side FET beyond the zero inductor current quickly discharges the output
capacitor thus causing the output voltage to fall quickly towards the setpoint. During the operation, the cycle-by-
cycle negative current limit is also activated to ensure the safe operation of the internal FETs.
UVLO Protection
The TPS53513 monitors the voltage on the VDD pin. If the VDD pin voltage is lower than the UVLO off-threshold
voltage, the switch mode power supply shuts off. If the VDD voltage increases beyond the UVLO on-threshold
voltage, the controller turns back on. UVLO is a non-latch protection.
Thermal Shutdown
The TPS53513 monitors internal temperature. If the temperature exceeds the threshold value (typically 140°C),
TPS53513 shuts off. When the temperature falls approximately 40°C below the threshold value, the device turns
on. Thermal shutdown is a non-latch protection.
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External Parts Selection
The external components selection is a simple process using D-CAP3™ Mode. Select the external components
using the following steps
1. CHOOSE THE SW FREQUENCY
The SW frequency is configured by the resistor divider on the RF pin. Select one of eight SW frequencies
from 250 kHz to 1 MHz. Refer Table 1 for the relationship between the SW frequency and resistor-divider
configuration.
2. CHOOSE THE OPERATION MODE
Select the operation mode using Table 4.
3. CHOOSE THE INDUCTOR
Determine the inductance value to set the ripple current at approximately ¼ to ½ of the maximum output
current. Larger ripple current increases output ripple voltage, improves S/N ratio, and helps stable operation.
V
- V
´ V
V
- V
max
)
´ V
OUT
(
IN
OUT
)
)
OUT
(
IN
OUT
)
max
(
)
(
1
3
L =
´
=
´
I
´ f
V
I
´ f
OUT
max
( )
V
IN(max)
SW
IN
SW
IND ripple
max
(
(
)
(7)
The inductor requires a low DCR to achieve good efficiency. The inductor also requires enough room above
peak inductor current before saturation. The peak inductor current is estimated using Equation 8.
V
- V
´ V
OUT
)
)
(
IN
OUT
max
(
)
V
1
TRIP
I
=
+
´
IND peak
(
)
8´R
L ´ f
V
IN
SW
DS on
max
( )
(
(8)
4. CHOOSE THE OUTPUT CAPACITOR
The output capacitor selection is determined by output ripple and transient requirement. When operating in
CCM, the output ripple has two components as shown in Equation 9. Equation 10 and Equation 11 define
these components.
VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR)
(9)
I
L ripple
(
)
V
=
RIPPLE C
( )
8´ C
´ f
SW
OUT
(10)
(11)
VRIPPLE ESR = IL ripple ´ESR
(
)
(
)
5. DETERMINE THE VALUE OF R1 AND R2
The output voltage is programmed by the voltage-divider resistors, R1 and R2, shown in APPLICATION
CIRCUIT DIAGRAM. R1 is connected between the VFB pin and the output, and R2 is connected between
the VFB pin and GND. The recommended R2 value is from 1 kΩ to 20 kΩ. Determine R1 using Equation 12.
VOUT - 0.6
R1=
´R2
(12)
LAYOUT CONSIDERATIONS
Before beginning a design using the TPS53513, consider the following:
•
Place the power components (including input and output capacitors, the inductor, and the TPS53513) on the
solder side of the PCB. In order to shield and isolate the small signal traces from noisy power lines, insert and
connect at least one inner plane to ground.
•
All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE, and RF must be placed
away from high-voltage switching nodes such as SW and VBST to avoid coupling. Use internal layers as
ground planes and shield the feedback trace from power traces and components.
•
•
GND (pin 22) must be connected directly to the thermal pad. Connect the thermal pad to the PGND pins and
then to the GND plane.
The GND1 pin (pin 27) and the GND2 pin (pin 28) are not actual GND pins and neither of these pins should
be used for dedicated ground connection. The recommendation is to connect GND1 pin (pin 27) and the
GND2 pin (pin 28) to the nearby ground.
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TPS53513
SLUSBP9A –SEPTEMBER 2013–REVISED DECEMBER 2013
www.ti.com
•
Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input
AC-current loop.
•
•
Place the feedback resistor near the device to minimize the VFB trace distance.
Place the frequency-setting resistor (RRF), OCP-setting resistor (RTRIP) and mode-setting resistor (RMODE
close to the device. Use the common GND via to connect the resistors to the GND plane if applicable.
)
•
•
•
•
•
•
•
Place the VDD and VREG decoupling capacitors as close to the device as possible. Provide GND vias for
each decoupling capacitor and ensure the loop is as small as possible.
The PCB trace is defined as switch node, which connects the SW pins and high-voltage side of the inductor.
The switch node should be as short and wide as possible.
Use separated vias or trace to connect SW node to the snubber, bootstrap capacitor, and ripple-injection
resistor. Do not combine these connections.
Place one more small capacitor (2.2 nF- 0402 size) between the VIN and PGND pins. This capacitor must be
placed as close to the device as possible.
TI recommends placing a snubber between the SW shape and GND shape for effective ringing reduction.
The value of snubber design starts at 3 Ω + 470 pF.
Consider R,C,Cc network (Ripple injection network) component placement and place the AC coupling
capacitor, Cc, close to the device, and R and C close to the power stage.
See Figure 42 for the layout recommendation.
VIN Shape
To inner GND plane
CIN
HF cap.
Cc
2
3
2
1
2
0
1
9
1
8
1
7
1
6
1
5
To VOUT Shape
VO
TRIP
PGND
PGND
PGND
PGND
PGND
DNC
GND Shape
GND1
GND2
COUT
1
2
3
4
5
6
7
8
9
VOUT Shape
SW Shape
LOUT
To VREG Pin
Cap.
Res.
Trace on bottom layer
Trace of top layer
RCC On Bottom layer
Trace of bottom layer
Trace on inner layer
Figure 42. Layout Recommendation
24
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TPS53513
www.ti.com
SLUSBP9A –SEPTEMBER 2013–REVISED DECEMBER 2013
REVISION HISTORY
Changes from Original (SEPTEMBER 2013) to Revision A
Page
•
•
•
•
•
•
•
•
Added updates to FEATURES, APPLICATIONS, DESCRIPTION and front page graphics ............................................... 1
Changed device dimensions from 3,5 mm × 4,5 mm to 3.5 mm × 4.5 mm ......................................................................... 1
Added updates to Electrical Specifications ........................................................................................................................... 2
Added updates to Electrical Specifications ........................................................................................................................... 3
Added updates to PIN DESCRIPTIONS ............................................................................................................................... 5
Added updates to BLOCK DIAGRAM ................................................................................................................................... 7
Added THERMAL PERFORMANCE section ...................................................................................................................... 14
Added updates to APPLICATION INFORMATION section ................................................................................................ 15
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Nov-2013
PACKAGING INFORMATION
Orderable Device
TPS53513RVER
TPS53513RVET
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
VQFN
VQFN
RVE
28
28
3000 Pb-Free (RoHS
Exempt)
CU NIPDAU
Level-2-260C-1 YEAR
TPS53513
TPS53513
ACTIVE
RVE
250
Pb-Free (RoHS
Exempt)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Nov-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Nov-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS53513RVER
TPS53513RVET
VQFN
VQFN
RVE
RVE
28
28
3000
250
330.0
180.0
12.4
12.4
3.8
3.8
4.8
4.8
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Nov-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS53513RVER
TPS53513RVET
VQFN
VQFN
RVE
RVE
28
28
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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