DRA829JMTGBALFRQ1 [TI]
DRA829 Jacinto⢠Processors Silicon Revisions 1.0 and 1.1;型号: | DRA829JMTGBALFRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | DRA829 Jacinto⢠Processors Silicon Revisions 1.0 and 1.1 |
文件: | 总319页 (文件大小:7092K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DRA829J, DRA829V
SPRSP35J – FEBRUARY 2019 – REVISED AUGUST 2021
DRA829 Jacinto™ Processors
Silicon Revisions 1.0 and 1.1
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Full-HD video, four (1920 × 1080p, 60 fps), or eight
1 Features
(1920 × 1080p, 30 fps) H.264/H.265 decode
Full-HD video, one (1920 × 1080p, 60 fps), or up to
three (1920 × 1080p, 30 fps) H.264 encode
Processor cores:
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Dual 64-bit Arm® Cortex®-A72 microprocessor
subsystem at up to 2.0 GHz
Functional Safety:
– 1MB shared L2 cache per dual-core Arm®
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Functional Safety-Compliant targeted (on select
part numbers)
Cortex®-A72 cluster
– 32KB L1 DCache and 48KB L1 ICache per
Cortex®-A72 Core
– Developed for functional safety applications
– Documentation available to aid ISO 26262
functional safety system design up to ASIL-D/
SIL-3 targeted
– Systematic capability up to ASIL-D/SIL-3
targeted
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Six Arm® Cortex®-R5F MCUs at up to 1.0 GHz
– 16K I-Cache, 16K D-Cache, 64K L2 TCM
– Two Arm® Cortex®-R5F MCUs in isolated MCU
subsystem
– Four Arm® Cortex®-R5F MCUs in general
compute partition
– Hardware integrity up to ASIL-D/SIL-3 targeted
for MCU Domain
– Hardware integrity up to ASIL-B/SIL-2 targeted
for Main Domain
– Safety-related certification
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Deep-learning Matrix Multiply Accelerator (MMA),
up to 8 TOPS (8b) at 1.0 GHz
C7x floating point, vector DSP, up to 1.0 GHz,
80 GFLOPS, 256 GOPS
Two C66x floating point DSP, up to 1.35 GHz,
40 GFLOPS, 160 GOPS
3D GPU PowerVR® Rogue 8XE GE8430, up to
750 MHz, 96 GFLOPS, 6 Gpix/sec
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ISO 26262 planned
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AEC-Q100 qualified on part number variants
ending in Q1
Device security (on select part numbers):
Secure boot with secure runtime support
Customer programmable root key, up to RSA-4K
or ECC-512
Embedded hardware security module
Crypto hardware accelerators – PKA with ECC,
AES, SHA, RNG, DES and 3DES
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Memory subsystem:
Up to 8MB of on-chip L3 RAM with ECC and
coherency
– ECC error protection
– Shared coherent cache
– Supports internal DMA engine
External Memory Interface (EMIF) module with
ECC
– Supports LPDDR4 memory types
– Supports speeds up to 4266 MT/s
– 32-bit data bus with inline ECC up to 14.9GB/s
General-Purpose Memory Controller (GPMC)
512KB on-chip SRAM in MAIN domain, protected
by ECC
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High speed serial interfaces:
Two CSI2.0 4L RX plus one CSI2.0 4L TX
Integrated ethernet switch supporting
(total of 8 external ports)
– Up to eight 2.5Gb SGMII
– Up to eight RMII (10/100) or RGMII
(10/100/1000)
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– Up to two QSGMII
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Up to four PCI-Express® (PCIe) Gen3 controllers
– Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3
(8.0GT/s) operation with auto-negotiation
– Up to two lanes per controller
Display subsystem:
One eDP/DP interface with Multi-Display Support
(MST)
– HDCP1.4/HDCP2.2 high-bandwidth digital
content protection
One DSI TX (up to 2.5K)
Up to two DPI
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Two USB 3.0 dual-role device (DRD) subsystem
– Two enhanced SuperSpeed Gen1 ports
– Each port supports Type-C switching
– Each port independently configurable as USB
host, USB peripheral, or USB DRD
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Video acceleration:
Ultra-HD video, one (3840 × 2160p, 60 fps), or two
(3840 × 2160p, 30 fps) H.264/H.265 decode
Automotive interfaces:
Sixteen Modular Controller Area Network (MCAN)
modules with full CAN-FD support
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRA829J, DRA829V
SPRSP35J – FEBRUARY 2019 – REVISED AUGUST 2021
www.ti.com
Audio interfaces:
Twelve Multichannel Audio Serial Port (MCASP)
modules
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16-nm FinFET technology
24 mm × 24 mm, 0.8-mm pitch, 827-pin FCBGA
(ALF), enables IPC class 3 PCB routing
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Flash memory interfaces:
TPS6594-Q1 Companion Power Management
ICs (PMIC):
Functional Safety support up to ASIL-D
Flexible mapping to support different use cases
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Embedded MultiMediaCard interface ( eMMC™
5.1)
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Universal Flash Storage (UFS 2.1) interface with
two lanes
2 Applications
Two Secure Digital® 3.0/Secure Digital Input
Output 3.0 interfaces (SD3.0/SDIO3.0)
Two simultaneous flash interfaces configured as
– One OSPI and one QSPI flash interfaces
– or one HyperBus™ and one QSPI flash
interface
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Automotive gateway
Body control module
Industrial transport
Industrial robot
High-end PLC
System-on-Chip (SoC) architecture:
3 Description
Jacinto™ 7 DRA829 processors, based on the Arm®v8 64-bit architecture, provide advanced system integration
to enable lower system costs of automotive and industrial applications. The integrated diagnostics and functional
safety features are targeted to ASIL-B/C or SIL-2 certification/requirements. The integrated microcontroller
(MCU) island eliminates the need for an external system MCU. The device features a Gigabit Ethernet switch
and a PCIe® hub which enables networking use cases that require heavy data bandwidth. Up to four Arm®
Cortex®-R5F subsystems manage low level, timing critical processing tasks leaving the Arm® Cortex®-A72’s
unencumbered for applications. A dual-core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS
applications with minimal need for a software hypervisor.
Device Information
PART NUMBER(1)
XDRA829JXXGALF
XDRA829VXXGALF
XJ721EGALF
PACKAGE
FCBGA (827)
FCBGA (827)
FCBGA (827)
BODY SIZE
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
(1) For more information, see Section 11, Mechanical, Packaging, and Orderable Information.
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3.1 Functional Block Diagram
Figure 3-1 is functional block diagram for the device.
DRA829
Navigator Subsystem
C7x DSP
w/ MMA
2×
C66x DSP
Dual Arm®
Cortex®-A72
4× Arm®
Cortex®-R5F
SecProxy
UDMA
PVU
CPTS
Proxy/RA
INTR
Mailbox
MCRC
INTA
Spinlock
PAT
TIMER_MGR
Channelized FW
64K L2 RAM
per Core
3D GPU PowerVR
Rogue 8XE GE8430
1MB Shared L2
Cache with ECC
SMMU
Memory Subsystem
Ethernet Subsystem
Display Subsystem
System Services
Capture Subsystem
Mailboxes UDMA
2× CSI2 4L RX
CSI2 4L TX
MSMC
8MB SRAM with ECC
4K Blend
Scale Convert
Integrated
WWDT
SMMU
GP Timers
Spinlock
Ethernet Switch(B)
(Supporting up to 4
external ports)
ELM
EMIF 32-bit LPDDR4 w/ECC
512KB SRAM
GPMC
DSI
DP/eDP(B)
Debug
MCU Island
Video Acceleration
(H.264 Encode and
H.264/H.265 Decode)
Navigator Subsystem
DMSC
SA2UL
10× GP Timers
2× WWDT
2× Arm®
Proxy
INTA
Cortex®-R5F
(with optional Lockstep)
UDMA
INTR
RA
Security Accelerators
MCRC
AES
RNG
SHA
DES
PKA
3DES
Channelized FW
Safety DTK
SP RAM 512B
1 MB SRAM
Interconnect
Media and Data Storage
Control Interfaces
General Connectivity
High-Speed Serial Interfaces
2× WKUP GPIO(A)
8× GPIO
4× PCIe® 2-Lane Ports
2× USB 3.0 DRD(B)
(B)
eMMC
6× eHRPWM
3× eCAP
2× SD/SDIO
UFS 2L
8× MCSPI
3× MCSPI(A)
2× ADC(A)
10× UART
2× UART (A)
I3C
3× eQEP
1× OSPI or
1× HyperBus(A)(C)
Ethernet Switch(B)
(Up to 8-ports)
QSGMII/SGMII/RGMII/RMII
1× QSPI(A)(C)
7× I2C
Automotive Interfaces
Audio Peripherals
14× CAN-FD
12× MCASP
10/100/1000 Ethernet(A)
2× CAN-FD(A)
3× I2C(A)
2× I3C(A)
intro_001
A. This interface is located on the MCU Island but is available for the full system to access.
B. DP, SGMII, USB3.0, and PCIE[3:0] share total of twelve SerDes lanes.
C. Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus™ and OSPI1.
Figure 3-1. Functional Block Diagram
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................2
3 Description.......................................................................2
3.1 Functional Block Diagram...........................................3
4 Revision History.............................................................. 4
5 Device Comparison.........................................................7
5.1 Related Products........................................................ 9
6 Terminal Configuration and Functions........................10
6.1 Pin Diagram.............................................................. 10
6.2 Pin Attributes.............................................................11
6.3 Signal Descriptions................................................... 79
6.4 Pin Multiplexing.......................................................135
6.5 Connections for Unused Pins................................. 150
7 Specifications.............................................................. 153
7.1 Absolute Maximum Ratings.................................... 153
7.2 ESD Ratings........................................................... 156
7.3 Power-On-Hour (POH) Limits................................. 156
7.4 Recommended Operating Conditions.....................156
7.5 Operating Performance Points................................159
7.6 Power Consumption Summary............................... 159
7.7 Electrical Characteristics.........................................160
7.8 VPP Specifications for One-Time Programmable
7.9 Thermal Resistance Characteristics....................... 169
7.10 Timing and Switching Characteristics................... 170
8 Detailed Description....................................................287
8.1 Overview.................................................................287
8.2 Processor Subsystems........................................... 288
8.3 Accelerators and Coprocessors..............................289
8.4 Other Subsystems.................................................. 290
9 Applications and Implementation..............................299
9.1 Power Supply Mapping...........................................299
9.2 Device Connection and Layout Fundamentals....... 302
9.3 Peripheral- and Interface-Specific Design
Information................................................................ 304
10 Device and Documentation Support........................309
10.1 Device Nomenclature............................................309
10.2 Tools and Software................................................311
10.3 Documentation Support........................................ 312
10.4 Support Resources............................................... 312
10.5 Trademarks...........................................................312
10.6 Electrostatic Discharge Caution............................312
10.7 Glossary................................................................312
11 Mechanical, Packaging, and Orderable
Information.................................................................. 313
11.1 Packaging Information.......................................... 313
(OTP) eFuses............................................................167
4 Revision History
Changes from July 22, 2021 to August 27, 2021 (from Revision I (July 2021) to Revision J
(August 2021))
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Global:: Deleted "DMIPS" references................................................................................................................1
(Device Comparison): Deleted "MCU Island with Lockstep Arm Cortex-R5Fs" row, as info in Lockstep and
Safety Targeted rows. ........................................................................................................................................7
(Pin Attributes): Updated Buffer Type for MCU_PORz and PORz to FS Reset................................................11
Updated USB0/1_RCALIB footnote to specify the pin must be connected to VSS through an external resistor,
even when the pin is unused.......................................................................................................................... 103
Updated REXT pin note to show it should always be connected through an external resistor to VSS, even
when unused.................................................................................................................................................. 103
Added clarification notes to MMC1_SDCD and MMC2_SDCD signals about pulled down requirement....... 109
Updated CSI0/1_RXRCALIB footnote to specify the pin must be connected to VSS through an external
resistor, even when the pin is unused.............................................................................................................125
Updated DSI_TXRCALIB footnote to specify the pin must be connected to VSS through an external resistor,
even when the pin is unused.......................................................................................................................... 125
Showed SERDES[4:0]_REXT balls should be connected to VSS if unused in Connections for Unused Pins.....
150
Showed VMON balls should be connected to PWR if unused in Connections for Unused Pins. Also added
note specifying MMC1_SDCD and MMC2_SDCD should be pulled down to function properly ....................150
Showed CSI[1:0]_RXRCALIB, DSI_TXRCALIB, USB[1:0]_RCALIB pins should be connected to VSS is
unused in Connections for Unused Pins ........................................................................................................150
Added FS Reset Electrical Characteristics table............................................................................................ 160
(SERDES Electrical Characteristics): Added SERDES REFCLK electrical characteristics table. The limits are
only applicable when internal termination is enabled..................................................................................... 166
(GPMC and NOR Flash — Sync Burst Read — 4x16–bit): Updated figure for GPMC_WAIT[j] signal (F21,
F22)................................................................................................................................................................ 227
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•
(GPMC and Multiplexed NOR Flash — Sync Burst Write): Updated figure for GPMC_WAIT[j] signal (F21,
F22)................................................................................................................................................................ 227
(McSPI): Updated output load limit for SPI_CLK............................................................................................257
(Timing and Switching Characteristics): Updated MMC1, MMC2 SDR12, SDR25, SDR50, SDR104 switching
characteristics parameters to show data is launched off of rising edge......................................................... 271
(OSPI Switching Characteristics Table - Data Training): Updated cycle time for CLK to 6 ns (1.8 V) from 6.02
ns and 7.5 ns (3.3 V) from 7.52 ns for both SDR and DDR............................................................................277
(OSPI Switching Characteristics - No Data Training SDR Mode ): Updated 3.3 V cycle time to 7.5 ns from
7.52 ns............................................................................................................................................................278
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Changes from July 19, 2021 to July 21, 2021 (from Revision H (July 2021) to Revision I (July
2021))
Page
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(Nomenclature Description): Added device type "P" and "R"......................................................................... 310
Changes from April 1, 2021 to July 19, 2021 (from Revision G (April 2021) to Revision H (July
2021))
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(Features): Added statement to clarify device security and safety/ASIL are on select part number variants.....1
(Device Comparison): Updated MSMC capacity for DRA829JM to 8MB. Updated Note 7 under Device
Comparison table to be generic. Added rows and footnotes clarifying certain safety and security feature are
available on select part number variants............................................................................................................ 7
(Related Products): Updated link and description to Software Development Kit................................................9
(Pin Attributes): Added the secondary pin multiplexing functions for the SERDES and controlled by
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CTRLMMR regs................................................................................................................................................11
(Signal Descriptions): Added note to clarify CPTS signal connection.............................................................110
(Signal Descriptions): Moved MCU CPTS signals from CPSW2G to CPTS section. Moved SYNCn_OUT
signals from SYSTEM to CPTS section. Updated both sets of signal descriptions........................................ 111
Updated description for VDDA_ADC0/1 to reference internal tie to VREFP.................................................. 131
Added note specifying power balls must be supplied with voltage specified in Recommended Operating
Condition. .......................................................................................................................................................131
(Pin Multiplexing): Updated PADCONFIG register address column to show actual address value and not
address offset value........................................................................................................................................135
(Abs Max Ratings): Added Latch-Up Performance parameter values............................................................153
Updated VDDS_DDR voltage rails min limits to 1.06 V in alignment with JEDEC spec. Updated description
for VDD_CPU AVS range. ............................................................................................................................. 156
(MLB Electrical Characteristics table): Updated IOL/IOH=6 mA; VILSS=0.3*VDDIO; VIH=0.75*VDDIO. Added
slew rate information.......................................................................................................................................160
(Electrical Characteristics tables): Updated eMMC PHY VILSS, VIHSS, VOL, VOH, IOL, IOH limits. ......... 160
(Electrical Characteristics tables): Update ADC leakage for VSS to show negative current..........................160
(Electrical Characteristics tables): Added Section headers to all electrical characteristics tables..................160
Updated Power Supply Sequencing Section..................................................................................................171
(Input and Output Clocks / Oscillators):Updated "Input Clocks Interface" image........................................... 192
(WKUP_OSC0 Crystal Electrical Characteristics): Updated/Changed Cshunt, ESRxtal = 80 Ω from "24MHz" to
now "25 MHz"................................................................................................................................................. 193
(OSC1 Crystal Electrical Characteristics): Updated/Changed Cshunt, ESRxtal = 80 Ω from "24MHz" to now "25
MHz"............................................................................................................................................................... 197
Added WKUP_LFOSC0 startup time limi....................................................................................................... 201
(Device Module Clock Frequencies): Renamed title and added references to TRM/DM sections describing
module clock and frequencies........................................................................................................................ 205
(ATCLK[x] Switching Characteristics): Updated/Changed table information and associated ATCLK[x] Timing
figure...............................................................................................................................................................207
Updated CSI-2 max freq support....................................................................................................................218
(GPMC): Added IOSET information for GPMC0 signals................................................................................ 226
(I3C): Updated parameter names from "D#" to "OD#" and updated images new names and corected/deleted
some timings...................................................................................................................................................250
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(McASP Timing Conditions): Updated td(Trace Delay) parameter limits........................................................253
(McSPI): Added IOSET information for MCU_SPI0 and MCU_SPI1..............................................................257
(MMC1/2 - SD/SDIO Interface): Added UHS-I SDR104 support as well as corresponding Timing Switching
Characteristics................................................................................................................................................267
Added note clarifying I/O timing is not applicable when OSPI is used with data training .............................. 277
(OSPI DDR Timing): Removed internal loopback and internal pad loopback mode limits from OSPI timing
tables.............................................................................................................................................................. 279
(Detailed Description): Added power supply description and described how common power supply types can
be grouped......................................................................................................................................................290
(External Oscillator): Added reference to Clock Specifications section..........................................................302
(20210706): Updated Reset section description.............................................................................................303
(LPDDR4 Board Design and Layout Guidelines): Updated ulink and title to be Jacinto 7 LPDDR guidelines....
304
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(Device and Documentation Support): Added missing Electrostatic Discharge Caution section................... 309
(Nomenclature Description): Removed XJ721EGALF from Note 4 to make the statement generic.............. 310
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5 Device Comparison
Table 5-1 shows the features of the SoC, highlighting the differences.
Table 5-1. Device Comparison
FEATURES(6)
REFERENCE NAME
DRA829JM
DRA829VM
Features
PROCESSORS AND ACCELERATORS
Speed Grades
T
Dual Core
Hexa Core
Optional(1)
Yes
T
Dual Core
Hexa Core
Optional(1)
Yes
Arm Cortex-A72 Microprocessor Subsystem
Arm Cortex-R5F
Arm A72
Arm R5F
Lockstep
DMSC
Device Management Security Controller
Security Accelerators
SA
Yes
Yes
C7x Floating Point, Vector DSP
Deep Learning Accelerator
C7x DSP
MMA
Yes
No
Yes
No
Two C66x Floating Point DSP
C66x DSP
GPU
Dual Core
Yes
No
Graphics Accelerator 3D GPU PowerVR Rogue 8XE
GE8430
No
Depth and Motion Processing Accelerators
Vision Processing Accelerators
Video Encoder / Decoder
DMPAC
No
No
No
No
No
VPAC
VENC/ VDEC
Yes
SAFETY AND SECURITY
Safety Targeted
Safety
Security
Q1
Optional(1)
Optional(2)
Optional(3)
Optional(1)
Optional(2)
Optional(3)
Device Security
AEC-Q100 Qualified
PROGRAM AND DATA STORAGE
On-Chip Shared Memory (RAM) in MAIN Domain
On-Chip Shared Memory (RAM) in MCU Domain
Multicore Shared Memory Controller
OCSRAM
MCU_MSRAM
MSMC
512KB SRAM
1MB SRAM
512KB SRAM
1MB SRAM
8MB (On-Chip SRAM 2MB (On-Chip SRAM with
with ECC)
ECC)
LPDDR4 DDR Subsystem
DDRSS
Up to 8GB (32-bit data)
with inline ECC
Up to 8GB (32-bit data)
with inline ECC
SECDED
GPMC
7-Bit
7-Bit
General-Purpose Memory Controller
PERIPHERALS
Up to 1GB with ECC
Up to 1GB with ECC
Display Subsystem
DSS
Yes
16
Yes
16
Modular Controller Area Network Interface with Full CAN-
FD Support
MCAN
General-Purpose I/O
GPIO
Up to 226
Up to 226
Inter-Integrated Circuit Interface
I2C
10
3
10
3
Improved Inter-Integrated Circuit Interface
Analog-to-Digital Converter
I3C
ADC
2
2
Capture Subsystem with Camera Serial Interface (CSI2)
CSI2.0 4L RX
CSI2.0 4L TX
MCSPI
2
2
1
1
Multichannel Serial Peripheral Interface
11
11
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Table 5-1. Device Comparison (continued)
FEATURES(6)
Multichannel Audio Serial Port
REFERENCE NAME
MCASP0
MCASP1
MCASP2
MCASP3
MCASP4
MCASP5
MCASP6
MCASP7
MCASP8
MCASP9
MCASP10
MCASP11
MMCSD0
MMCSD1
MMCSD2
UFS 2L
DRA829JM
16 Serializers
12 Serializers
6 Serializers
4 Serializers
4 Serializers
4 Serializers
4 Serializers
4 Serializers
4 Serializers
4 Serializers
8 Serializers
8 Serializers
eMMC (8-bits)
SD/SDIO (4-bits)
SD/SDIO (4-bits)
Yes (2 Lanes)
8-bits(5)
DRA829VM
16 Serializers
12 Serializers
6 Serializers
4 Serializers
4 Serializers
4 Serializers
4 Serializers
4 Serializers
4 Serializers
4 Serializers
8 Serializers
8 Serializers
eMMC (8-bits)
SD/SDIO (4-bits)
SD/SDIO (4-bits)
Yes (2 Lanes)
8-bits(5)
MultiMedia Card/ Secure Digital Interface
Universal Flash Storage
Flash Subsystem (FSS)
OSPI0
OSPI1(7)
4-bits
4-bits
HyperBus
PCIE0
Yes(5)
Yes(5)
4x PCI Express Port with Integrated PHY
Up to Two Lanes(4)
Up to Two Lanes(4)
Up to Two Lanes(4)
Up to Two Lanes(4)
No
Up to Two Lanes(4)
Up to Two Lanes(4)
Up to Two Lanes(4)
Up to Two Lanes(4)
No
PCIE1
PCIE2
PCIE3
2x Programmable Real-Time Unit Subsystem and TSN
Communication Subsystem (Ethernet Subsystem)
PRU_ICSSG0
PRU_ICSSG1
CPSW2G
CPSW9G
No
No
Gigabit Ethernet Interface
RMII or RGMII
RMII or RGMII
8 × RMII, 8 × RGMII, 8 × 8 × RMII, 8 × RGMII, 8 ×
SGMII(4)
SGMII(4)
General-Purpose Timers
TIMER
30
6
30
6
Enhanced High Resolution Pulse-Width Modulator Module eHRPWM
Enhanced Capture Module
eCAP
eQEP
UART
USB0
USB1
3
3
Enhanced Quadrature Encoder Pulse Module
Universal Asynchronous Receiver and Transmitter
3
3
12
12
Universal Serial Bus (USB3.1) SuperSpeed Dual-Role-
Device (DRD) Ports with SS PHY
Yes(4)
Yes(4)
Yes(4)
Yes(4)
(1) Safety features including R5F Lockstep and SIL/ASIL ratings are only applicable to select part number variants as indicated by the
Device Type (Y) identifier in the Table 10-1, Nomenclature Description table.
(2) Device security features including Secure Boot and Customer Programmable Keys are applicable to select part number variants as
indicated by the Device Type (Y) identifier in the Table 10-1, Nomenclature Description table.
(3) AEC-Q100 qualification is applicable to select part number variants as indicated by the Automotive Designator (Q1) identifier in the
Table 10-1, Nomenclature Description table.
(4) DP, SGMII, USB3.0, and PCIE[3:0] share total of twelve SerDes lanes.
(5) Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus and OSPI1.
(6) Software should constrain the features used to match the intended production device.
(7) OSPI1 module only pins out 4 pins and is referred to as QSPI in some contexts.
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5.1 Related Products
Companion Products for DRA829 Review products that are frequently purchased or used in conjunction with
this product to complete your design.
Software Development Kit for DRA8x & TDA4x Jacinto™ Processors Processor SDK RTOS (PSDK RTOS)
can be used together with Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX), to form a
multi-processor software development platform for TDA4x and DRA8x SoCs within the TI’s Jacinto™ Processors
platform. The SDK provides a comprehensive set of software tools and components to help users develop
and deploy their applications on supported J7 SoCs. PSDK RTOS and either PSDK Linux or PSDK QNX
can be used together to implement various use-cases in robotics, vision, factory and building automation, and
automotive ADAS and gateway systems.
DRA829 Evaluation Module The DRA829 evaluation module (EVM) platform is based on the Jacinto™
DRA829J, V and is designed to speed up development efforts and reduce time to market for automotive
gateway and vehicle compute systems. The integrated diagnostics and functional safety features are targeted
to ASIL-D/SIL-3 certification/requirements. The integrated microcontroller (MCU) island eliminates the need for
an external system MCU. The device features Gigabit Ethernet ports with integrated switch to meet networking
use cases that require heavy data bandwidth and also includes PCIe hub functionality. CAN-FD and up to UART
interfaces are available on the device. General purpose Arm® Cortex®-R5F subsystems can handle low level,
timing critical processing tasks and leave the Arm® Cortex®-A72’s unencumbered for advanced applications.
This EVM kit features the main CPU board and an Ethernet expansion board option for additional gigabit
Ethernet ports in order to jump start evaluation and development.
Application Notes and White Paper Gateway & vehicle compute application processor.
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6 Terminal Configuration and Functions
6.1 Pin Diagram
Note
The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt
is made to use "ball" only when referring to the physical package.
Figure 6-1 shows the ball locations for the 827-ball flip chip ball grid array (FCBGA) package that are used in
conjunction with Table 6-1 through Figure 6-1 to locate signal names and ball grid numbers.
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29
10 12 14 16 18 20 22 24 26 28
2
4
6
8
Figure 6-1. ALF FCBGA-N827 Pin Diagram (Bottom View)
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6.2 Pin Attributes
Note
MCU_BOOTMODE pins are latched on the rising edge of MCU_PORz_OUT. BOOTMODE pins are latched on the rising edge of PORz_OUT.
Note
Media Local Bus (MLB) is not available on this device. The following balls must be left unconnected if not used in GPIO mode: AE2, AD2, AD3,
AC3, AC1, AD1.
Note
PRU_ICSSG0 and PRU_ICSSG1 are not available on this device. The prg* signals should not be used. Those pins can be used for other
functions.
Table 6-1. Pin Attributes
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
U7
CAP_VDDS0
CAP_VDDS0
CAP
K23
CAP_VDDS0_MCU
CAP_VDDS1
CAP_VDDS0_MCU
CAP_VDDS1
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
I
AB21
J18
CAP_VDDS1_MCU
CAP_VDDS2
CAP_VDDS1_MCU
CAP_VDDS2
Y18
J19
CAP_VDDS2_MCU
CAP_VDDS3
CAP_VDDS2_MCU
CAP_VDDS3
W21
AA22
R22
V22
B20
CAP_VDDS4
CAP_VDDS4
CAP_VDDS5
CAP_VDDS5
CAP_VDDS6
CAP_VDDS6
CSI0_RXCLKN
CSI0_RXCLKN
OFF
1.8 V
1.8 V
1.8 V
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
D-PHY
A21
F16
CSI0_RXCLKP
csi0_rxrcalib
CSI0_RXCLKP
I
OFF
OFF
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
D-PHY
D-PHY
CSI0_RXRCALIB
A
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
F15
B17
A18
B19
D18
D17
E16
A20
C19
C18
E17
B16
D15
csi1_rxrcalib
CSI1_RXRCALIB
CSI1_RXCLKN
CSI1_RXCLKP
CSI0_RXN0
CSI0_RXN1
CSI0_RXN2
CSI0_RXN3
CSI0_RXP0
CSI0_RXP1
CSI0_RXP2
CSI0_RXP3
CSI1_RXN0
CSI1_RXN1
A
I
OFF
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
D-PHY
CSI1_RXCLKN
CSI1_RXCLKP
CSI0_RXN0
CSI0_RXN1
CSI0_RXN2
CSI0_RXN3
CSI0_RXP0
CSI0_RXP1
CSI0_RXP2
CSI0_RXP3
CSI1_RXN0
CSI1_RXN1
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
I
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
I
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
I
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
I
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
I
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
I
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
I
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
I
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
I
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
I
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
I
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
D14
E13
A17
C16
C15
E14
CSI1_RXN2
CSI1_RXN2
CSI1_RXN3
CSI1_RXP0
CSI1_RXP1
CSI1_RXP2
CSI1_RXP3
I
I
I
I
I
I
OFF
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
D-PHY
CSI1_RXN3
CSI1_RXP0
CSI1_RXP1
CSI1_RXP2
CSI1_RXP3
OFF
OFF
OFF
OFF
OFF
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
VDDA_0P8_CSI
RX /
VDDA_1P8_CSI
RX
J1
ddr0_ckn
DDR0_CKN
DDR0_CKP
IO
IO
IO
IO
IO
IO
IO
IO
IO
A
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
H1
K6
G4
H3
K5
J4
ddr0_ckp
ddr0_resetn
ddr0_ca0
DDR0_RESETn
DDR0_CA0
ddr0_ca1
DDR0_CA1
ddr0_ca2
DDR0_CA2
ddr0_ca3
DDR0_CA3
K2
H5
H2
G3
J3
ddr0_ca4
DDR0_CA4
ddr0_ca5
DDR0_CA5
ddr0_cal0
ddr0_cke0
ddr0_cke1
ddr0_csn0_0
ddr0_csn0_1
ddr0_csn1_0
ddr0_csn1_1
ddr0_dm0
ddr0_dm1
ddr0_dm2
ddr0_dm3
DDR0_CAL0
DDR0_CKE0
DDR0_CKE1
DDR0_CSn0_0
DDR0_CSn0_1
DDR0_CSn1_0
DDR0_CSn1_1
DDR0_DM0
DDR0_DM1
DDR0_DM2
DDR0_DM3
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
J5
K3
G5
J2
A3
E4
N1
R5
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
A5
A6
B5
C2
B4
C3
A2
A4
D1
C4
F1
G2
F2
F3
D3
F5
L5
ddr0_dq0
DDR0_DQ0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OFF
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
1.1 V
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
DDR0
ddr0_dq1
DDR0_DQ1
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
ddr0_dq2
DDR0_DQ2
ddr0_dq3
DDR0_DQ3
ddr0_dq4
DDR0_DQ4
ddr0_dq5
DDR0_DQ5
ddr0_dq6
DDR0_DQ6
ddr0_dq7
DDR0_DQ7
ddr0_dq8
DDR0_DQ8
ddr0_dq9
DDR0_DQ9
ddr0_dq10
ddr0_dq11
ddr0_dq12
ddr0_dq13
ddr0_dq14
ddr0_dq15
ddr0_dq16
ddr0_dq17
ddr0_dq18
ddr0_dq19
ddr0_dq20
ddr0_dq21
ddr0_dq22
ddr0_dq23
ddr0_dq24
ddr0_dq25
ddr0_dq26
ddr0_dq27
ddr0_dq28
ddr0_dq29
ddr0_dq30
ddr0_dq31
ddr0_dqs0n
ddr0_dqs0p
ddr0_dqs1n
ddr0_dqs1p
ddr0_dqs2n
ddr0_dqs2p
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ16
DDR0_DQ17
DDR0_DQ18
DDR0_DQ19
DDR0_DQ20
DDR0_DQ21
DDR0_DQ22
DDR0_DQ23
DDR0_DQ24
DDR0_DQ25
DDR0_DQ26
DDR0_DQ27
DDR0_DQ28
DDR0_DQ29
DDR0_DQ30
DDR0_DQ31
DDR0_DQS0N
DDR0_DQS0P
DDR0_DQS1N
DDR0_DQS1P
DDR0_DQS2N
DDR0_DQS2P
M5
N5
L4
L2
L1
N2
N4
T3
T2
P2
P3
P5
R4
T4
T5
B1
B2
E2
E3
M2
M3
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
R1
R2
P6
ddr0_dqs3n
DDR0_DQS3N
IO
IO
I
OFF
1.1 V
1.1 V
1.1 V
VDDS_DDR
VDDS_DDR
DDR0
ddr0_dqs3p
ddr_ret
DDR0_DQS3P
DDR_RET
OFF
OFF
DDR0
DDR0
VDDS_DDR_BI
AS
G6
F7
dp0_auxn
DP0_AUXN
DP0_AUXP
DSI_TXCLKN
IO
IO
O
OFF
OFF
OFF
0.8 V
0.8 V
1.8 V
VDDA_0P8_DP
/
VDDA_1P8_DP
AUX-PHY
AUX-PHY
D-PHY
dp0_auxp
VDDA_0P8_DP
/
VDDA_1P8_DP
E10
DSI_TXCLKN
VDDA_0P8_DSI
TX /
VDDA_1P8_DSI
TX
E11
D11
D12
B13
B14
C12
C13
A14
A15
DSI_TXCLKP
DSI_TXN0
DSI_TXN1
DSI_TXN2
DSI_TXN3
DSI_TXP0
DSI_TXP1
DSI_TXP2
DSI_TXP3
DSI_TXCLKP
DSI_TXN0
DSI_TXN1
DSI_TXN2
DSI_TXN3
DSI_TXP0
DSI_TXP1
DSI_TXP2
DSI_TXP3
O
IO
O
O
O
IO
O
O
O
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
VDDA_0P8_DSI
TX /
VDDA_1P8_DSI
TX
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
VDDA_0P8_DSI
TX /
VDDA_1P8_DSI
TX
VDDA_0P8_DSI
TX /
VDDA_1P8_DSI
TX
VDDA_0P8_DSI
TX /
VDDA_1P8_DSI
TX
VDDA_0P8_DSI
TX /
VDDA_1P8_DSI
TX
VDDA_0P8_DSI
TX /
VDDA_1P8_DSI
TX
VDDA_0P8_DSI
TX /
VDDA_1P8_DSI
TX
VDDA_0P8_DSI
TX /
VDDA_1P8_DSI
TX
VDDA_0P8_DSI
TX /
VDDA_1P8_DSI
TX
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
F12
U2
dsi_txrcalib
DSI_TXRCALIB
A
OFF
1.8 V
VDDA_0P8_DSI
TX /
VDDA_1P8_DSI
TX
D-PHY
ecap0_in_apwm_out
ECAP0_IN_APWM_OUT
SYNC0_OUT
CPTS0_RFT_CLK
SPI2_CS3
0
IO
O
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
0
0/1
1
2
4
5
6
7
0
I
0
1
IO
O
I3C0_SDAPULLEN
SPI7_CS0
IO
IO
IO
1
0
GPIO1_11
C26
B29
emu0
emu1
extintn
EMU0
PU
0
0
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
LVCMOS
LVCMOS
I2C OD FS
PU/PD
PU/PD
1/1
1/1
0/0
EMU1
0
IO
PU
1.8 V/3.3 V VDDSHV0_MC Yes
U
AC18
U3
EXTINTn
0
7
0
1
6
7
0
7
0
7
0
1
7
0
1
7
0
1
2
3
4
5
6
7
8
I
OFF
1.8 V/3.3 V VDDSHV2
Yes
1
0
0
GPIO0_0
IO
I
ext_refclk1
EXT_REFCLK1
SYNC1_OUT
SPI7_CLK
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
0/1
O
IO
IO
0
0
1
0
1
0
1
0
0
1
0
0
1
1
1
1
1
0
0
0
0
GPIO1_12
AC5
AA5
Y6
i2c0_scl
i2c0_sda
i2c1_scl
I2C0_SCL
IOD
IO
IOD
IO
IOD
I
OFF
OFF
OFF
7
7
7
1.8 V/3.3 V VDDSHV0
1.8 V/3.3 V VDDSHV0
1.8 V/3.3 V VDDSHV0
Yes
Yes
Yes
I2C OD FS
I2C OD FS
I2C OD FS
1/0
1/0
1/0
GPIO1_7
I2C0_SDA
GPIO1_8
I2C1_SCL
CPTS0_HW1TSPUSH
GPIO1_9
IO
IOD
I
AA6
W2
i2c1_sda
i3c0_scl
I2C1_SDA
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV0
1.8 V/3.3 V VDDSHV0
Yes
Yes
I2C OD FS
LVCMOS
1/0
0/1
CPTS0_HW2TSPUSH
GPIO1_10
IO
IO
I
I3C0_SCL
PU/PD
MMC2_SDCD
UART9_CTSn
MCAN2_RX
I2C6_SCL
I
I
IOD
I
DP0_HPD
PCIE0_CLKREQn
GPIO1_5
IO
IO
I
UART6_RXD
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
W1
i3c0_sda
I3C0_SDA
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
1
1
0/1
MMC2_SDWP
UART9_RTSn
MCAN2_TX
1
2
3
4
6
7
8
0
4
7
0
4
7
0
1
2
3
4
7
0
1
2
3
4
7
0
0
0
0
0
0
0
0
0
0
0
0
O
O
I2C6_SDA
IOD
IO
IO
O
I
1
0
0
0
1
1
0
PCIE1_CLKREQn
GPIO1_6
UART6_TXD
W5
W6
W3
mcan0_rx
mcan0_tx
mcan1_rx
MCAN0_RX
OFF
OFF
OFF
7
7
7
1.8 V/3.3 V VDDSHV0
1.8 V/3.3 V VDDSHV0
1.8 V/3.3 V VDDSHV0
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
0/1
0/1
0/1
I2C2_SCL
IOD
IO
O
IOD
IO
I
GPIO1_1
MCAN0_TX
I2C2_SDA
1
0
1
1
1
GPIO1_2
MCAN1_RX
UART6_CTSn
UART9_RXD
I
I
USB0_DRVVBUS
USB1_DRVVBUS
GPIO1_3
O
O
IO
O
O
O
O
O
IO
A
0
V4
mcan1_tx
MCAN1_TX
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
0/1
UART6_RTSn
UART9_TXD
USB0_DRVVBUS
USB1_DRVVBUS
GPIO1_4
0
K25
K26
K28
L28
K24
K27
K29
L29
N23
M25
L24
L26
mcu_adc0_ain0
mcu_adc0_ain1
mcu_adc0_ain2
mcu_adc0_ain3
mcu_adc0_ain4
mcu_adc0_ain5
mcu_adc0_ain6
mcu_adc0_ain7
mcu_adc1_ain0
mcu_adc1_ain1
mcu_adc1_ain2
mcu_adc1_ain3
MCU_ADC0_AIN0
MCU_ADC0_AIN1
MCU_ADC0_AIN2
MCU_ADC0_AIN3
MCU_ADC0_AIN4
MCU_ADC0_AIN5
MCU_ADC0_AIN6
MCU_ADC0_AIN7
MCU_ADC1_AIN0
MCU_ADC1_AIN1
MCU_ADC1_AIN2
MCU_ADC1_AIN3
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
0
0
0
0
0
0
0
0
0
0
0
0
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
VDDA_ADC0
VDDA_ADC0
VDDA_ADC0
VDDA_ADC0
VDDA_ADC0
VDDA_ADC0
VDDA_ADC0
VDDA_ADC0
VDDA_ADC1
VDDA_ADC1
VDDA_ADC1
VDDA_ADC1
ADC12B
ADC12B
ADC12B
ADC12B
ADC12B
ADC12B
ADC12B
ADC12B
ADC12B
ADC12B
ADC12B
ADC12B
A
A
A
A
A
A
A
A
A
A
A
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
N24
M24
L25
L27
J26
mcu_adc1_ain4
MCU_ADC1_AIN4
MCU_ADC1_AIN5
MCU_ADC1_AIN6
MCU_ADC1_AIN7
MCU_I2C0_SCL
0
A
A
A
A
OFF
0
1.8 V
1.8 V
1.8 V
1.8 V
VDDA_ADC1
VDDA_ADC1
VDDA_ADC1
VDDA_ADC1
ADC12B
ADC12B
ADC12B
ADC12B
I2C OD FS
mcu_adc1_ain5
mcu_adc1_ain6
mcu_adc1_ain7
mcu_i2c0_scl
0
0
0
0
7
0
7
0
2
4
7
0
2
4
7
0
7
0
7
0
7
0
7
0
1
7
0
1
7
0
1
7
0
7
OFF
OFF
OFF
OFF
0
0
0
0
IOD
IO
IOD
IO
IO
I
1.8 V/3.3 V VDDSHV0_MC Yes
U
1
0
1
0
1
1
0
0
1
1/0
1/0
0/1
WKUP_GPIO0_64
MCU_I2C0_SDA
H25
D26
mcu_i2c0_sda
mcu_i3c0_scl
OFF
OFF
0
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
I2C OD FS
LVCMOS
WKUP_GPIO0_65
MCU_I3C0_SCL
1.8 V/3.3 V VDDSHV0_MC Yes
U
PU/PD
PU/PD
MCU_UART0_CTSn
MCU_TIMER_IO8
WKUP_GPIO0_60
MCU_I3C0_SDA
IO
IO
IO
O
D25
mcu_i3c0_sda
OFF
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
LVCMOS
0/1
MCU_UART0_RTSn
MCU_TIMER_IO9
WKUP_GPIO0_61
MCU_MCAN0_RX
WKUP_GPIO0_59
MCU_MCAN0_TX
WKUP_GPIO0_58
MCU_MDIO0_MDC
WKUP_GPIO0_51
MCU_MDIO0_MDIO
WKUP_GPIO0_50
MCU_OSPI0_CLK
MCU_HYPERBUS0_CK
WKUP_GPIO0_16
MCU_OSPI0_DQS
MCU_HYPERBUS0_RWDS
WKUP_GPIO0_18
MCU_OSPI0_LBCLKO
MCU_HYPERBUS0_CKn
WKUP_GPIO0_17
MCU_OSPI1_CLK
WKUP_GPIO0_29
IO
IO
I
0
0
0
0
C29
D29
F23
E23
E20
mcu_mcan0_rx
mcu_mcan0_tx
mcu_mdio0_mdc
mcu_mdio0_mdio
mcu_ospi0_clk
OFF
OFF
OFF
OFF
OFF
7
7
7
7
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
0/1
0/1
0/1
0/1
0/1
IO
O
1.8 V/3.3 V VDDSHV0_MC Yes
U
IO
O
0
1.8 V/3.3 V VDDSHV2_MC Yes
U
IO
IO
IO
O
0
0
0
1.8 V/3.3 V VDDSHV2_MC Yes
U
1.8 V/3.3 V VDDSHV1_MC Yes
U
O
IO
I
0
0
0
0
0
D21
C21
F22
mcu_ospi0_dqs
mcu_ospi0_lbclko
mcu_ospi1_clk
OFF
OFF
OFF
7
7
7
1.8 V/3.3 V VDDSHV1_MC Yes
U
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
0/1
1/1
0/1
IO
IO
IO
O
1.8 V/3.3 V VDDSHV1_MC Yes
U
IO
O
0
0
1.8 V/3.3 V VDDSHV1_MC Yes
U
IO
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
B23
A23
mcu_ospi1_dqs
MCU_OSPI1_DQS
0
I
OFF
7
1.8 V/3.3 V VDDSHV1_MC Yes
U
LVCMOS
LVCMOS
PU/PD
0
0/1
1/1
MCU_OSPI0_CSn3
MCU_HYPERBUS0_INTn
MCU_OSPI0_ECC_FAIL
WKUP_GPIO0_31
1
2
6
7
0
1
2
6
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
O
I
1
1
0
0
I
IO
IO
O
mcu_ospi1_lbclko
MCU_OSPI1_LBCLKO
MCU_OSPI0_CSn2
MCU_HYPERBUS0_RESETOn
MCU_OSPI0_RESET_OUT0
WKUP_GPIO0_30
OFF
7
1.8 V/3.3 V VDDSHV1_MC Yes
U
PU/PD
I
1
0
O
IO
O
F19
E19
D20
G19
G20
F20
F21
E21
B22
mcu_ospi0_csn0
mcu_ospi0_csn1
mcu_ospi0_d0
mcu_ospi0_d1
mcu_ospi0_d2
mcu_ospi0_d3
mcu_ospi0_d4
mcu_ospi0_d5
mcu_ospi0_d6
MCU_OSPI0_CSn0
MCU_HYPERBUS0_CSn0
WKUP_GPIO0_27
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V VDDSHV1_MC Yes
U
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
O
IO
O
0
MCU_OSPI0_CSn1
MCU_HYPERBUS0_RESETn
WKUP_GPIO0_28
1.8 V/3.3 V VDDSHV1_MC Yes
U
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MCU_OSPI0_D0
1.8 V/3.3 V VDDSHV1_MC Yes
U
MCU_HYPERBUS0_DQ0
WKUP_GPIO0_19
MCU_OSPI0_D1
1.8 V/3.3 V VDDSHV1_MC Yes
U
MCU_HYPERBUS0_DQ1
WKUP_GPIO0_20
MCU_OSPI0_D2
1.8 V/3.3 V VDDSHV1_MC Yes
U
MCU_HYPERBUS0_DQ2
WKUP_GPIO0_21
MCU_OSPI0_D3
1.8 V/3.3 V VDDSHV1_MC Yes
U
MCU_HYPERBUS0_DQ3
WKUP_GPIO0_22
MCU_OSPI0_D4
1.8 V/3.3 V VDDSHV1_MC Yes
U
MCU_HYPERBUS0_DQ4
WKUP_GPIO0_23
MCU_OSPI0_D5
1.8 V/3.3 V VDDSHV1_MC Yes
U
MCU_HYPERBUS0_DQ5
WKUP_GPIO0_24
MCU_OSPI0_D6
1.8 V/3.3 V VDDSHV1_MC Yes
U
MCU_HYPERBUS0_DQ6
WKUP_GPIO0_25
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
G21
mcu_ospi0_d7
MCU_OSPI0_D7
0
IO
IO
IO
O
OFF
7
1.8 V/3.3 V VDDSHV1_MC Yes
U
LVCMOS
PU/PD
0
0
0
0/1
MCU_HYPERBUS0_DQ7
WKUP_GPIO0_26
MCU_OSPI1_CSn0
WKUP_GPIO0_36
MCU_OSPI1_CSn1
MCU_HYPERBUS0_WPn
MCU_TIMER_IO0
MCU_HYPERBUS0_CSn1
MCU_UART0_RTSn
MCU_SPI0_CS2
1
7
0
7
0
1
2
3
4
5
6
7
0
7
0
4
5
7
0
4
5
7
0
4
5
7
C22
E22
mcu_ospi1_csn0
mcu_ospi1_csn1
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV1_MC Yes
U
LVCMOS
LVCMOS
PU/PD
PU/PD
0/1
0/1
IO
O
0
0
1
1.8 V/3.3 V VDDSHV1_MC Yes
U
O
IO
O
O
IO
O
MCU_OSPI0_RESET_OUT1
WKUP_GPIO0_37
MCU_OSPI1_D0
IO
IO
IO
IO
I
0
0
0
0
1
1
0
0
D22
G22
mcu_ospi1_d0
mcu_ospi1_d1
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV1_MC Yes
U
LVCMOS
LVCMOS
PU/PD
PU/PD
0/1
0/1
WKUP_GPIO0_32
MCU_OSPI1_D1
1.8 V/3.3 V VDDSHV1_MC Yes
U
MCU_UART0_RXD
MCU_SPI1_CS1
IO
IO
IO
O
WKUP_GPIO0_33
MCU_OSPI1_D2
D23
C23
mcu_ospi1_d2
mcu_ospi1_d3
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV1_MC Yes
U
LVCMOS
LVCMOS
PU/PD
PU/PD
0/1
0/1
MCU_UART0_TXD
MCU_SPI1_CS2
IO
IO
IO
I
1
0
0
1
1
0
WKUP_GPIO0_34
MCU_OSPI1_D3
1.8 V/3.3 V VDDSHV1_MC Yes
U
MCU_UART0_CTSn
MCU_SPI0_CS1
IO
IO
I
WKUP_GPIO0_35
MCU_PORz
H23
B28
mcu_porz
OFF
OFF
1.8 V
VDDA_WKUP
Yes
FS Reset
LVCMOS
PU/PD
PU/PD
mcu_porz_out
MCU_PORz_OUT
0
0
0
O
0
0
0
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
0/0
0/0
1/1
0/1
C27
D28
C24
mcu_resetstatz
mcu_resetz
MCU_RESETSTATz
MCU_RESETz
O
I
OFF
PU
1.8 V/3.3 V VDDSHV0_MC Yes
U
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
1.8 V/3.3 V VDDSHV0_MC Yes
U
mcu_rgmii1_rxc
MCU_RGMII1_RXC
MCU_RMII1_REF_CLK
WKUP_GPIO0_45
0
1
7
I
OFF
1.8 V/3.3 V VDDSHV2_MC Yes
U
0
0
0
I
IO
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
C25
B26
B27
B24
A24
D24
A25
B25
A26
A27
mcu_rgmii1_rx_ctl
MCU_RGMII1_RX_CTL
0
I
OFF
7
1.8 V/3.3 V VDDSHV2_MC Yes
U
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
0
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
MCU_RMII1_RX_ER
WKUP_GPIO0_39
MCU_RGMII1_TXC
MCU_RMII1_TX_EN
WKUP_GPIO0_44
MCU_RGMII1_TX_CTL
MCU_RMII1_CRS_DV
WKUP_GPIO0_38
MCU_RGMII1_RD0
MCU_RMII1_RXD0
WKUP_GPIO0_49
MCU_RGMII1_RD1
MCU_RMII1_RXD1
WKUP_GPIO0_48
MCU_RGMII1_RD2
MCU_TIMER_IO5
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
3
7
0
1
3
7
0
I
IO
O
O
IO
O
I
mcu_rgmii1_txc
mcu_rgmii1_tx_ctl
mcu_rgmii1_rd0
mcu_rgmii1_rd1
mcu_rgmii1_rd2
mcu_rgmii1_rd3
mcu_rgmii1_td0
mcu_rgmii1_td1
mcu_rgmii1_td2
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V VDDSHV2_MC Yes
U
0
1.8 V/3.3 V VDDSHV2_MC Yes
U
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
I
1.8 V/3.3 V VDDSHV2_MC Yes
U
I
IO
I
1.8 V/3.3 V VDDSHV2_MC Yes
U
I
IO
I
1.8 V/3.3 V VDDSHV2_MC Yes
U
IO
IO
I
WKUP_GPIO0_47
MCU_RGMII1_RD3
MCU_TIMER_IO4
1.8 V/3.3 V VDDSHV2_MC Yes
U
IO
IO
O
O
IO
O
O
IO
O
IO
I
WKUP_GPIO0_46
MCU_RGMII1_TD0
MCU_RMII1_TXD0
WKUP_GPIO0_43
MCU_RGMII1_TD1
MCU_RMII1_TXD1
WKUP_GPIO0_42
MCU_RGMII1_TD2
MCU_TIMER_IO3
1.8 V/3.3 V VDDSHV2_MC Yes
U
0
0
1.8 V/3.3 V VDDSHV2_MC Yes
U
1.8 V/3.3 V VDDSHV2_MC Yes
U
0
0
0
MCU_ADC_EXT_TRIGGER1
WKUP_GPIO0_41
MCU_RGMII1_TD3
MCU_TIMER_IO2
IO
O
IO
I
A28
D27
mcu_rgmii1_td3
OFF
PD
7
0
1.8 V/3.3 V VDDSHV2_MC Yes
U
LVCMOS
LVCMOS
PU/PD
PU/PD
0/1
1/0
0
0
0
MCU_ADC_EXT_TRIGGER0
WKUP_GPIO0_40
MCU_SAFETY_ERRORn
IO
IO
mcu_safety_errorn
1.8 V
VDDA_WKUP
Yes
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
E27
E25
E24
E28
mcu_spi0_clk
MCU_SPI0_CLK
WKUP_GPIO0_52
MCU_BOOTMODE00
MCU_SPI0_CS0
MCU_TIMER_IO1
WKUP_GPIO0_55
MCU_SPI0_D0
WKUP_GPIO0_53
MCU_BOOTMODE01
MCU_SPI0_D1
MCU_TIMER_IO0
WKUP_GPIO0_54
MCU_BOOTMODE02
MDIO0_MDC
0
IO
IO
I
OFF
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
0
0
1/1
0/1
1/1
1/1
7
Bootstrap
mcu_spi0_cs0
mcu_spi0_d0
mcu_spi0_d1
0
IO
IO
IO
IO
IO
I
OFF
OFF
OFF
7
7
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
1
0
0
0
0
4
7
0
1.8 V/3.3 V VDDSHV0_MC Yes
U
7
Bootstrap
0
IO
IO
IO
I
1.8 V/3.3 V VDDSHV0_MC Yes
U
0
0
0
4
7
Bootstrap
V24
V26
mdio0_mdc
mdio0_mdio
0
5
7
8
0
5
7
8
0
7
0
7
0
7
0
7
0
7
0
7
O
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV3
1.8 V/3.3 V VDDSHV3
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
0/1
0/1
TRC_DATA23
GPIO0_110
O
IO
I
0
0
0
GPMC0_WAIT2
MDIO0_MDIO
TRC_DATA22
GPIO0_109
IO
O
IO
I
0
0
GPMC0_WAIT3
MLB0_MLBCN
GPIO1_35
AE2
AD2
AD3
AC3
AC1
AD1
mlb0_mlbcn
mlb0_mlbcp
mlb0_mlbdn
mlb0_mlbdp
mlb0_mlbsn
mlb0_mlbsp
I
OFF
OFF
OFF
OFF
OFF
OFF
0
0
0
0
0
0
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
VDDA_1P8_ML
B
MLB_LVDS
MLB_LVDS
MLB_LVDS
MLB_LVDS
MLB_LVDS
MLB_LVDS
IO
I
0
0
0
0
0
0
MLB0_MLBCP
GPIO1_34
VDDA_1P8_ML
B
IO
IO
IO
IO
IO
IO
IO
IO
IO
A
MLB0_MLBDN
GPIO1_33
VDDA_1P8_ML
B
MLB0_MLBDP
GPIO1_32
VDDA_1P8_ML
B
MLB0_MLBSN
GPIO1_31
VDDA_1P8_ML
B
MLB0_MLBSP
GPIO1_30
VDDA_1P8_ML
B
AE1
AF1
AE3
AE4
mmc0_calpad
mmc0_clk
MMC0_CALPAD
MMC0_CLK
OFF
OFF
OFF
OFF
1.8 V
1.8 V
1.8 V
1.8 V
VDDS_MMC0
VDDS_MMC0
VDDS_MMC0
VDDS_MMC0
eMMCPHY PU/PD
eMMCPHY PU/PD
eMMCPHY PU/PD
eMMCPHY PU/PD
O
mmc0_cmd
mmc0_ds
MMC0_CMD
IO
IO
1
1
MMC0_DS
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
P25
R29
P23
mmc1_clk
MMC1_CLK
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV5
1.8 V/3.3 V VDDSHV5
1.8 V/3.3 V VDDSHV3
Yes
SDIO
PU/PD
PU/PD
PU/PD
0
1
1
0
1
0/1
0/1
0/1
UART8_RXD
I2C4_SCL
1
4
7
0
1
4
7
0
1
2
3
5
6
7
8
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
7
IOD
IO
IO
O
GPIO1_19
mmc1_cmd
mmc1_sdcd
MMC1_CMD
OFF
OFF
7
7
Yes
Yes
SDIO
UART8_TXD
I2C4_SDA
IOD
IO
I
1
0
1
1
1
0
0
0
0
0
1
GPIO1_20
MMC1_SDCD
UART8_CTSn
UART0_DCDn
TIMER_IO2
LVCMOS
I
I
IO
IO
IO
IO
I
EQEP2_I
PCIE2_CLKREQn
GPIO1_21
PRG0_IEP0_EDC_LATCH_IN1
MMC1_SDWP
UART8_RTSn
UART0_DSRn
TIMER_IO3
R28
mmc1_sdwp
I
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0/1
O
I
1
0
0
0
0
0
0
0
IO
IO
IO
IO
IO
O
ECAP2_IN_APWM_OUT
EQEP2_S
PCIE3_CLKREQn
GPIO1_22
PRG0_IEP0_EDC_SYNC_OUT1
MMC2_CLK
T26
mmc2_clk
IO
O
OFF
7
1.8 V/3.3 V VDDSHV6
Yes
SDIO
PU/PD
0/1
USB0_DRVVBUS
USB1_DRVVBUS
TIMER_IO6
O
IO
IOD
I
0
1
1
0
I2C3_SCL
UART3_RXD
GPIO1_27
IO
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
T25
mmc2_cmd
MMC2_CMD
USB0_DRVVBUS
USB1_DRVVBUS
TIMER_IO7
0
IO
O
OFF
7
1.8 V/3.3 V VDDSHV6
Yes
SDIO
PU/PD
1
0/1
1
2
3
4
5
7
O
IO
0
1
I2C3_SDA
IOD
O
UART3_TXD
GPIO1_28
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
0
1
1
1
1
1
1
1
1
1
AG2
AH1
AG3
AF4
AE5
AF3
AG1
AF2
R24
mmc0_dat0
mmc0_dat1
mmc0_dat2
mmc0_dat3
mmc0_dat4
mmc0_dat5
mmc0_dat6
mmc0_dat7
mmc1_dat0
MMC0_DAT0
MMC0_DAT1
MMC0_DAT2
MMC0_DAT3
MMC0_DAT4
MMC0_DAT5
MMC0_DAT6
MMC0_DAT7
MMC1_DAT0
UART7_RTSn
ECAP1_IN_APWM_OUT
TIMER_IO1
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
VDDS_MMC0
VDDS_MMC0
VDDS_MMC0
VDDS_MMC0
VDDS_MMC0
VDDS_MMC0
VDDS_MMC0
VDDS_MMC0
eMMCPHY PU/PD
eMMCPHY PU/PD
eMMCPHY PU/PD
eMMCPHY PU/PD
eMMCPHY PU/PD
eMMCPHY PU/PD
eMMCPHY PU/PD
eMMCPHY
0
1
2
3
5
7
0
1
2
3
5
7
0
1
7
0
1
7
7
1.8 V/3.3 V VDDSHV5
Yes
SDIO
PU/PD
0/1
IO
IO
O
0
0
UART4_TXD
GPIO1_18
IO
IO
I
0
1
1
0
0
1
0
1
P24
mmc1_dat1
MMC1_DAT1
UART7_CTSn
ECAP0_IN_APWM_OUT
TIMER_IO0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
SDIO
PU/PD
0/1
IO
IO
I
UART4_RXD
GPIO1_17
IO
IO
O
R25
R26
mmc1_dat2
mmc1_dat3
MMC1_DAT2
UART7_TXD
GPIO1_16
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV5
1.8 V/3.3 V VDDSHV5
Yes
Yes
SDIO
SDIO
PU/PD
PU/PD
0/1
0/1
IO
IO
I
0
1
1
0
MMC1_DAT3
UART7_RXD
GPIO1_15
IO
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
T24
mmc2_dat0
MMC2_DAT0
0
IO
O
I
OFF
7
1.8 V/3.3 V VDDSHV6
Yes
SDIO
PU/PD
1
0/1
UART9_RTSn
UART0_RIn
1
2
3
4
5
7
8
0
1
2
3
4
5
7
8
0
1
2
4
7
0
1
2
4
7
1
0
TIMER_IO5
IO
O
I
UART6_TXD
EQEP2_B
0
0
0
1
1
GPIO1_26
IO
O
IO
I
PRG0_IEP1_EDC_SYNC_OUT1
MMC2_DAT1
UART9_CTSn
UART0_DTRn
TIMER_IO4
T27
mmc2_dat1
OFF
7
1.8 V/3.3 V VDDSHV6
Yes
SDIO
PU/PD
0/1
O
IO
I
0
1
0
0
0
1
UART6_RXD
EQEP2_A
I
GPIO1_25
IO
I
PRG0_IEP1_EDC_LATCH_IN1
MMC2_DAT2
UART9_TXD
T29
T28
mmc2_dat2
mmc2_dat3
IO
O
I
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV6
Yes
Yes
SDIO
SDIO
PU/PD
PU/PD
0/1
0/1
CPTS0_HW2TSPUSH
I2C5_SDA
0
1
0
1
1
0
1
0
IOD
IO
IO
I
GPIO1_24
MMC2_DAT3
UART9_RXD
CPTS0_HW1TSPUSH
I2C5_SCL
1.8 V/3.3 V VDDSHV6
I
IOD
IO
I
GPIO1_23
P29
osc1_xi
OSC1_XI
OFF
OFF
OFF
1.8 V
1.8 V
0.8 V
VDDS_OSC1
VDDS_OSC1
HFOSC
HFOSC
2-L-PHY
P27
osc1_xo
OSC1_XO
O
AE17
pcie_refclk0n
PCIE_REFCLK0N
IO
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
AD16
AE14
pcie_refclk0p
pcie_refclk1n
PCIE_REFCLK0P
PCIE_REFCLK1N
IO
IO
OFF
OFF
0.8 V
0.8 V
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
2-L-PHY
2-L-PHY
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AD15
pcie_refclk1p
PCIE_REFCLK1P
PCIE_REFCLK2N
PCIE_REFCLK2P
PCIE_REFCLK3N
PCIE_REFCLK3P
IO
IO
IO
IO
IO
OFF
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
2-L-PHY
2-L-PHY
2-L-PHY
2-L-PHY
2-L-PHY
AE11
AD12
AE9
pcie_refclk2n
pcie_refclk2p
pcie_refclk3n
pcie_refclk3p
OFF
OFF
OFF
OFF
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
AD10
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
E26
G23
pmic_power_en0
pmic_power_en1
MCU_I3C0_SDAPULLEN
WKUP_GPIO0_66
PMIC_POWER_EN1
MCU_I3C1_SDAPULLEN
WKUP_GPIO0_67
PORz
0
O
IO
O
O
IO
I
OFF
OFF
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
LVCMOS
LVCMOS
PU/PD
PU/PD
0/0
0/0
7
0
0
0
0
1.8 V/3.3 V VDDSHV0_MC Yes
U
5
7
J24
porz
0
OFF
OFF
OFF
0
0
7
1.8 V
VDDA_WKUP
Yes
Yes
Yes
FS Reset
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
U1
porz_out
PORz_OUT
0
O
O
1.8 V/3.3 V VDDSHV0
1.8 V/3.3 V VDDSHV1
0/0
0/1
AA27
prg0_mdio0_mdc
PRG0_MDIO0_MDC
I2C5_SDA
0
2
IOD
I
1
1
0
0
MCAN13_RX
6
GPIO0_84
7
IO
OZ
O
GPMC0_A0
8
DSS_FSYNC2
MCASP2_ACLKR
MCASP2_AXR5
PRG0_MDIO0_MDIO
I2C5_SCL
10
12
13
0
IO
IO
IO
IOD
O
0
0
1
Y26
prg0_mdio0_mdio
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0/1
2
MCAN13_TX
6
GPIO0_83
7
IO
OZ
O
0
0
GPMC0_A27
8
DSS_FSYNC0
MCASP2_AFSR
MCASP2_AXR4
10
12
13
IO
IO
0
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AF28
AE28
AE27
prg0_pru0_gpo0
PRG0_PRU0_GPO0
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV1
1.8 V/3.3 V VDDSHV1
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
0
0
0
0
0
0/1
0/1
0/1
PRG0_PRU0_GPI0
PRG0_RGMII1_RD0
PRG0_PWM3_A0
RGMII3_RD0
1
2
I
3
IO
I
4
RMII3_RXD1
5
I
GPIO0_43
7
IO
IO
IO
I
MCASP0_AXR0
PRG0_PRU0_GPO1
PRG0_PRU0_GPI1
PRG0_RGMII1_RD1
PRG0_PWM3_B0
RGMII3_RD1
12
0
prg0_pru0_gpo1
OFF
7
Yes
0
0
0
1
0
0
0
1
2
I
3
IO
I
4
RMII3_RXD0
5
I
GPIO0_44
7
IO
IO
IO
I
MCASP0_AXR1
PRG0_PRU0_GPO2
PRG0_PRU0_GPI2
PRG0_RGMII1_RD2
PRG0_PWM2_A0
RGMII3_RD2
12
0
prg0_pru0_gpo2
OFF
7
Yes
0
0
0
0
0
0
0
0
1
2
I
3
IO
I
4
RMII3_CRS_DV
GPIO0_45
5
I
7
IO
I
UART3_RXD
8
MCASP0_ACLKR
PRG0_PRU0_GPO3
PRG0_PRU0_GPI3
PRG0_RGMII1_RD3
PRG0_PWM3_A2
RGMII3_RD3
12
0
IO
IO
I
AD26
prg0_pru0_gpo3
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
0
0
0
0
0
0
0/1
1
2
I
3
IO
I
4
RMII3_RX_ER
5
I
GPIO0_46
7
IO
O
IO
UART3_TXD
8
MCASP0_AFSR
12
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AD25
prg0_pru0_gpo4
PRG0_PRU0_GPO4
PRG0_PRU0_GPI4
PRG0_RGMII1_RX_CTL
PRG0_PWM2_B0
RGMII3_RX_CTL
RMII3_TXD1
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV1
1.8 V/3.3 V VDDSHV1
1.8 V/3.3 V VDDSHV1
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
0
0
0
1
0
0/1
1/1
0/1
0/1
1
2
I
3
IO
I
4
5
O
IO
IO
IO
I
GPIO0_47
7
0
MCASP0_AXR2
PRG0_PRU0_GPO5
PRG0_PRU0_GPI5
PRG0_PWM3_B2
RMII3_TXD0
12
AC29
AE26
AC28
prg0_pru0_gpo5
prg0_pru0_gpo6
prg0_pru0_gpo7
0
OFF
OFF
OFF
7
7
7
Yes
Yes
Yes
0
0
1
1
3
IO
O
IO
IO
IO
I
5
GPIO0_48
7
0
0
GPMC0_AD0
8
MCASP0_AXR3
BOOTMODE2
12
Bootstrap
PRG0_PRU0_GPO6
PRG0_PRU0_GPI6
PRG0_RGMII1_RXC
PRG0_PWM3_A1
RGMII3_RXC
0
IO
I
0
0
0
0
0
1
2
I
3
IO
I
4
RMII3_TX_EN
5
O
IO
IO
IO
I
GPIO0_49
7
0
MCASP0_AXR4
PRG0_PRU0_GPO7
PRG0_PRU0_GPI7
PRG0_IEP0_EDC_LATCH_IN1
PRG0_PWM3_B1
PRG0_ECAP0_SYNC_IN
MCAN9_TX
12
0
0
0
0
1
0
1
2
I
3
IO
I
4
6
O
IO
IO
IO
GPIO0_50
7
0
0
GPMC0_AD1
8
MCASP0_AXR5
12
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AC27
prg0_pru0_gpo8
PRG0_PRU0_GPO8
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
0
1
0
0
0/1
PRG0_PRU0_GPI8
PRG0_PWM2_A1
MCAN9_RX
1
3
IO
I
6
GPIO0_51
7
IO
IO
IO
I
GPMC0_AD2
8
MCASP0_AXR6
UART6_RXD
12
14
0
AB26
prg0_pru0_gpo9
PRG0_PRU0_GPO9
PRG0_PRU0_GPI9
PRG0_UART0_CTSn
PRG0_PWM3_TZ_IN
SPI3_CS1
IO
I
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
1
0
1
0
0/1
1
2
I
3
I
4
IO
IO
O
IO
IO
IO
O
IO
I
PRG0_IEP0_EDIO_DATA_IN_OUT28
MCAN10_TX
5
6
GPIO0_52
7
0
0
GPMC0_AD3
8
MCASP0_ACLKX
UART6_TXD
12
14
0
AB25
prg0_pru0_gpo10
PRG0_PRU0_GPO10
PRG0_PRU0_GPI10
PRG0_UART0_RTSn
PRG0_PWM2_B1
SPI3_CS2
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
0/1
1
2
O
IO
IO
IO
I
3
1
1
0
1
0
0
4
PRG0_IEP0_EDIO_DATA_IN_OUT29
MCAN10_RX
5
6
GPIO0_53
7
IO
IO
IO
IO
I
GPMC0_AD4
8
MCASP0_AFSX
PRG0_PRU0_GPO11
PRG0_PRU0_GPI11
PRG0_RGMII1_TD0
PRG0_PWM3_TZ_OUT
RGMII3_TD0
12
0
AJ28
prg0_pru0_gpo11
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
0/1
1
2
O
O
O
IO
3
4
GPIO0_54
7
0
CLKOUT
9
OZ
IO
MCASP0_AXR7
12
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AH27
prg0_pru0_gpo12
PRG0_PRU0_GPO12
PRG0_PRU0_GPI12
PRG0_RGMII1_TD1
PRG0_PWM0_A0
RGMII3_TD1
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV1
1.8 V/3.3 V VDDSHV1
1.8 V/3.3 V VDDSHV1
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
0
0
0/1
0/1
0/1
0/1
1
2
O
IO
O
IO
O
IO
IO
I
3
0
0
4
GPIO0_55
7
DSS_FSYNC0
10
12
0
MCASP0_AXR8
PRG0_PRU0_GPO13
PRG0_PRU0_GPI13
PRG0_RGMII1_TD2
PRG0_PWM0_B0
RGMII3_TD2
AH29
AG28
AG27
prg0_pru0_gpo13
prg0_pru0_gpo14
prg0_pru0_gpo15
OFF
OFF
OFF
7
7
7
Yes
Yes
Yes
0
0
1
2
O
IO
O
IO
O
IO
IO
I
3
1
0
4
GPIO0_56
7
DSS_FSYNC2
10
12
0
MCASP0_AXR9
PRG0_PRU0_GPO14
PRG0_PRU0_GPI14
PRG0_RGMII1_TD3
PRG0_PWM0_A1
RGMII3_TD3
0
0
1
2
O
IO
O
IO
I
3
0
4
GPIO0_57
7
0
0
UART4_RXD
8
MCASP0_AXR10
PRG0_PRU0_GPO15
PRG0_PRU0_GPI15
PRG0_RGMII1_TX_CTL
PRG0_PWM0_B1
RGMII3_TX_CTL
GPIO0_58
12
0
IO
IO
I
0
0
1
2
O
IO
O
IO
O
O
IO
3
1
4
7
0
0
UART4_TXD
8
DSS_FSYNC3
10
12
MCASP0_AXR11
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AH28
prg0_pru0_gpo16
PRG0_PRU0_GPO16
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
0
0
0
0
0/1
PRG0_PRU0_GPI16
PRG0_RGMII1_TXC
PRG0_PWM0_A2
RGMII3_TXC
1
2
IO
IO
O
IO
O
IO
IO
I
3
4
GPIO0_59
7
DSS_FSYNC1
10
MCASP0_AXR12
PRG0_PRU0_GPO17
PRG0_PRU0_GPI17
PRG0_IEP0_EDC_SYNC_OUT1
PRG0_PWM0_B2
PRG0_ECAP0_SYNC_OUT
GPIO0_60
12
AB24
prg0_pru0_gpo17
0
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
1/1
1
2
O
IO
O
IO
IO
O
IO
I
3
1
4
7
0
0
0
GPMC0_AD5
8
OBSCLK1
9
MCASP0_AXR13
BOOTMODE7
12
Bootstrap
AB29
prg0_pru0_gpo18
PRG0_PRU0_GPO18
PRG0_PRU0_GPI18
PRG0_IEP0_EDC_LATCH_IN0
PRG0_PWM0_TZ_IN
PRG0_ECAP0_IN_APWM_OUT
GPIO0_61
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
0
0
0
0
0
0/1
1
2
I
3
I
4
IO
IO
IO
IO
IO
I
7
GPMC0_AD6
8
MCASP0_AXR14
PRG0_PRU0_GPO19
PRG0_PRU0_GPI19
PRG0_IEP0_EDC_SYNC_OUT0
PRG0_PWM0_TZ_OUT
GPIO0_62
12
0
AB28
prg0_pru0_gpo19
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
0/1
1
2
O
O
IO
IO
IO
3
7
0
0
GPMC0_AD7
8
MCASP0_AXR15
12
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AE29
prg0_pru1_gpo0
PRG0_PRU1_GPO0
PRG0_PRU1_GPI0
PRG0_RGMII2_RD0
RGMII4_RD0
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV1
1.8 V/3.3 V VDDSHV1
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
0
0
0
0
0
0/1
0/1
0/1
1
2
I
4
I
RMII4_RXD0
5
I
GPIO0_63
7
IO
I
UART4_CTSn
8
MCASP1_AXR0
UART5_RXD
12
14
0
IO
I
AD28
prg0_pru1_gpo1
PRG0_PRU1_GPO1
PRG0_PRU1_GPI1
PRG0_RGMII2_RD1
RGMII4_RD1
IO
I
OFF
7
Yes
0
0
0
0
0
0
0
1
2
I
4
I
RMII4_RXD1
5
I
GPIO0_64
7
IO
O
IO
O
IO
I
UART4_RTSn
8
MCASP1_AXR1
UART5_TXD
12
14
0
AD27
prg0_pru1_gpo2
PRG0_PRU1_GPO2
PRG0_PRU1_GPI2
PRG0_RGMII2_RD2
PRG0_PWM2_A2
RGMII4_RD2
OFF
7
Yes
0
0
0
0
0
0
0
0
1
2
I
3
IO
I
4
RMII4_CRS_DV
GPIO0_65
5
I
7
IO
GPMC0_A23
8
OZ
IO
IO
IO
I
MCASP1_ACLKR
MCASP1_AXR10
PRG0_PRU1_GPO3
PRG0_PRU1_GPI3
PRG0_RGMII2_RD3
RGMII4_RD3
12
13
0
0
0
0
0
0
0
0
AC25
prg0_pru1_gpo3
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0/1
1
2
I
4
I
RMII4_RX_ER
5
I
GPIO0_66
7
IO
IO
IO
MCASP1_AFSR
MCASP1_AXR11
12
13
0
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AD29
prg0_pru1_gpo4
PRG0_PRU1_GPO4
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
0
1
0
0/1
PRG0_PRU1_GPI4
PRG0_RGMII2_RX_CTL
PRG0_PWM2_B2
RGMII4_RX_CTL
RMII4_TXD1
1
2
I
3
IO
I
4
5
O
IO
GPIO0_67
7
0
0
GPMC0_A24
8
OZ
IO
IO
I
MCASP1_AXR2
PRG0_PRU1_GPO5
PRG0_PRU1_GPI5
GPIO0_68
12
AB27
prg0_pru1_gpo5
0
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
0
0
1/1
1
7
IO
IO
IO
I
GPMC0_AD8
8
MCASP1_ACLKX
BOOTMODE6
12
Bootstrap
AC26
prg0_pru1_gpo6
PRG0_PRU1_GPO6
PRG0_PRU1_GPI6
PRG0_RGMII2_RXC
RGMII4_RXC
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
0
0
0/1
1
2
I
4
I
RMII4_TXD0
5
O
IO
OZ
IO
IO
I
GPIO0_69
7
0
0
GPMC0_A25
8
MCASP1_AXR3
PRG0_PRU1_GPO7
PRG0_PRU1_GPI7
PRG0_IEP1_EDC_LATCH_IN1
SPI3_CS0
12
0
AA24
prg0_pru1_gpo7
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
0
1
0/1
1
2
I
4
IO
O
IO
IO
IO
O
MCAN11_TX
6
GPIO0_70
7
0
0
GPMC0_AD9
8
MCASP1_AXR4
UART2_TXD
12
14
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AA28
prg0_pru1_gpo8
PRG0_PRU1_GPO8
PRG0_PRU1_GPI8
PRG0_PWM2_TZ_OUT
MCAN11_RX
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
0/1
1
3
O
I
6
1
0
0
GPIO0_71
7
IO
IO
IO
IO
I
GPMC0_AD10
8
MCASP1_AFSX
PRG0_PRU1_GPO9
PRG0_PRU1_GPI9
PRG0_UART0_RXD
SPI3_CS3
12
0
Y24
prg0_pru1_gpo9
prg0_pru1_gpo10
prg0_pru1_gpo11
OFF
OFF
OFF
7
7
7
1.8 V/3.3 V VDDSHV1
Yes
Yes
Yes
LVCMOS
PU/PD
0
0
1
1
0
0
0
0/1
1
2
I
4
IO
IO
IO
IO
O
IO
I
PRG0_IEP0_EDIO_DATA_IN_OUT30
GPIO0_72
6
7
GPMC0_AD11
8
DSS_FSYNC3
10
12
14
0
MCASP1_AXR5
UART8_RXD
AA25
PRG0_PRU1_GPO10
PRG0_PRU1_GPI10
PRG0_UART0_TXD
PRG0_PWM2_TZ_IN
PRG0_IEP0_EDIO_DATA_IN_OUT31
GPIO0_73
IO
I
1.8 V/3.3 V VDDSHV1
LVCMOS
PU/PD
0
0
0/1
1
2
O
I
3
0
0
0
0
0
6
IO
IO
IO
7
GPMC0_AD12
8
CLKOUT
9
OZ
IO
O
MCASP1_AXR6
UART8_TXD
12
14
0
AG26
PRG0_PRU1_GPO11
PRG0_PRU1_GPI11
PRG0_RGMII2_TD0
RGMII4_TD0
IO
I
1.8 V/3.3 V VDDSHV1
LVCMOS
PU/PD
0
0
0/1
1
2
O
4
O
RMII4_TX_EN
5
O
GPIO0_74
7
IO
OZ
IO
0
0
GPMC0_A26
8
MCASP1_AXR7
12
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AF27
AF26
AE25
AF29
prg0_pru1_gpo12
PRG0_PRU1_GPO12
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV1
1.8 V/3.3 V VDDSHV1
1.8 V/3.3 V VDDSHV1
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
0
0
0/1
0/1
0/1
0/1
PRG0_PRU1_GPI12
PRG0_RGMII2_TD1
PRG0_PWM1_A0
RGMII4_TD1
1
2
O
IO
O
IO
IO
I
3
0
0
4
GPIO0_75
7
MCASP1_AXR8
UART8_CTSn
12
14
0
prg0_pru1_gpo13
prg0_pru1_gpo14
prg0_pru1_gpo15
PRG0_PRU1_GPO13
PRG0_PRU1_GPI13
PRG0_RGMII2_TD2
PRG0_PWM1_B0
RGMII4_TD2
IO
I
OFF
OFF
OFF
7
7
7
Yes
Yes
Yes
0
0
1
2
O
IO
O
IO
IO
O
IO
I
3
1
0
4
GPIO0_76
7
MCASP1_AXR9
UART8_RTSn
12
14
0
PRG0_PRU1_GPO14
PRG0_PRU1_GPI14
PRG0_RGMII2_TD3
PRG0_PWM1_A1
RGMII4_TD3
0
0
1
2
O
IO
O
IO
IO
I
3
0
0
4
GPIO0_77
7
MCASP2_AXR0
UART2_CTSn
12
14
0
PRG0_PRU1_GPO15
PRG0_PRU1_GPI15
PRG0_RGMII2_TX_CTL
PRG0_PWM1_B1
RGMII4_TX_CTL
GPIO0_78
IO
I
0
0
1
2
O
IO
O
IO
IO
O
3
1
0
4
7
MCASP2_AXR1
UART2_RTSn
12
14
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AG29
prg0_pru1_gpo16
PRG0_PRU1_GPO16
PRG0_PRU1_GPI16
PRG0_RGMII2_TXC
PRG0_PWM1_A2
RGMII4_TXC
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
0
0
0
0
0/1
1
2
IO
IO
O
IO
IO
IO
I
3
4
GPIO0_79
7
MCASP2_AXR2
PRG0_PRU1_GPO17
PRG0_PRU1_GPI17
PRG0_IEP1_EDC_SYNC_OUT1
PRG0_PWM1_B2
SPI3_CLK
12
Y25
prg0_pru1_gpo17
0
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
1/1
1
2
O
IO
IO
IO
IO
IO
I
3
1
0
0
0
4
GPIO0_80
7
GPMC0_AD13
8
MCASP2_AXR3
BOOTMODE3
12
Bootstrap
AA26
prg0_pru1_gpo18
PRG0_PRU1_GPO18
PRG0_PRU1_GPI18
PRG0_IEP1_EDC_LATCH_IN0
PRG0_PWM1_TZ_IN
SPI3_D0
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
0
0
0
0/1
1
2
I
3
I
4
IO
O
IO
IO
IO
I
MCAN12_TX
6
GPIO0_81
7
0
0
GPMC0_AD14
8
MCASP2_AFSX
UART2_RXD
12
14
0
AA29
prg0_pru1_gpo19
PRG0_PRU1_GPO19
PRG0_PRU1_GPI19
PRG0_IEP1_EDC_SYNC_OUT0
PRG0_PWM1_TZ_OUT
SPI3_D1
IO
I
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
0/1
1
2
O
O
IO
I
3
4
0
1
0
0
MCAN12_RX
6
GPIO0_82
7
IO
IO
IO
GPMC0_AD15
8
MCASP2_ACLKX
12
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AD18
AD19
AC23
prg1_mdio0_mdc
PRG1_MDIO0_MDC
0
O
OFF
7
1.8 V/3.3 V VDDSHV2
1.8 V/3.3 V VDDSHV2
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
0/1
0/1
0/1
SPI1_CS3
1
IO
1
1
0
0
I2C4_SDA
2
IOD
I
RMII_REF_CLK
GPIO0_42
5
7
IO
I
VPFE0_DATA12
MCASP5_AXR3
MCASP5_AFSR
UART3_RTSn
PRG1_MDIO0_MDIO
SPI1_CS2
11
12
13
14
0
IO
IO
O
IO
IO
IOD
IO
O
I
0
0
0
0
1
1
0
prg1_mdio0_mdio
OFF
7
Yes
1
I2C4_SCL
2
GPIO0_41
7
DSS_FSYNC1
VPFE0_DATA11
MCASP5_AXR2
MCASP5_ACLKR
UART3_CTSn
PRG1_PRU0_GPO0
PRG1_PRU0_GPI0
PRG1_RGMII1_RD0
PRG1_PWM3_A0
RGMII1_RD0
10
11
12
13
14
0
IO
IO
I
0
0
0
0
0
0
0
0
0
0
0
prg1_pru0_gpo0
IO
I
OFF
7
Yes
1
2
I
3
IO
I
4
RMII1_RXD0
5
I
GPIO0_1
7
IO
O
I
GPMC0_BE1n
RGMII7_RD0
8
9
MCASP6_ACLKX
UART0_RXD
12
14
IO
I
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AG22
prg1_pru0_gpo1
PRG1_PRU0_GPO1
PRG1_PRU0_GPI1
PRG1_RGMII1_RD1
PRG1_PWM3_B0
RGMII1_RD1
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
1.8 V/3.3 V VDDSHV2
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
0
1
0
0
0
0
0
0/1
0/1
0/1
1
2
I
3
IO
I
4
RMII1_RXD1
5
I
GPIO0_2
7
IO
I
GPMC0_WAIT0
RGMII7_RD1
8
9
I
MCASP6_AFSX
UART0_TXD
12
14
0
IO
O
IO
I
AF22
prg1_pru0_gpo2
PRG1_PRU0_GPO2
PRG1_PRU0_GPI2
PRG1_RGMII1_RD2
PRG1_PWM2_A0
RGMII1_RD2
OFF
7
Yes
0
0
0
0
0
0
0
0
0
1
2
I
3
IO
I
4
RMII1_CRS_DV
GPIO0_3
5
I
7
IO
I
GPMC0_WAIT1
RGMII7_RD2
8
9
I
MCASP6_AXR0
UART1_RXD
12
14
0
IO
I
AJ23
prg1_pru0_gpo3
PRG1_PRU0_GPO3
PRG1_PRU0_GPI3
PRG1_RGMII1_RD3
PRG1_PWM3_A2
RGMII1_RD3
IO
I
OFF
7
Yes
0
0
0
0
0
0
0
0
1
2
I
3
IO
I
4
RMII1_RX_ER
GPIO0_4
5
I
7
IO
O
I
GPMC0_DIR
8
RGMII7_RD3
9
MCASP6_AXR1
UART1_TXD
12
14
IO
O
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AH23
prg1_pru0_gpo4
PRG1_PRU0_GPO4
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0
1
0
0/1
PRG1_PRU0_GPI4
PRG1_RGMII1_RX_CTL
PRG1_PWM2_B0
RGMII1_RX_CTL
RMII1_TXD0
1
2
I
3
IO
I
4
5
O
IO
O
I
GPIO0_5
7
0
0
GPMC0_CSn2
8
RGMII7_RX_CTL
MCASP6_AXR2
MCASP6_ACLKR
UART2_RXD
9
12
IO
IO
I
13
0
0
0
0
1
14
AD20
prg1_pru0_gpo5
PRG1_PRU0_GPO5
PRG1_PRU0_GPI5
PRG1_PWM3_B2
RMII1_TX_EN
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
1/1
1
3
IO
O
IO
O
IO
I
5
GPIO0_6
7
0
0
GPMC0_WEn
8
MCASP3_AXR0
BOOTMODE0
12
Bootstrap
AD22
prg1_pru0_gpo6
PRG1_PRU0_GPO6
PRG1_PRU0_GPI6
PRG1_RGMII1_RXC
PRG1_PWM3_A1
RGMII1_RXC
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0
0
0
0/1
1
2
I
3
IO
I
4
RMII1_TXD1
5
O
IO
IO
O
I
AUDIO_EXT_REFCLK0
GPIO0_7
6
0
0
0
7
GPMC0_CSn3
8
RGMII7_RXC
9
MCASP6_AXR3
MCASP6_AFSR
UART2_TXD
12
13
14
IO
IO
O
0
0
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AE20
prg1_pru0_gpo7
PRG1_PRU0_GPO7
PRG1_PRU0_GPI7
PRG1_IEP0_EDC_LATCH_IN1
PRG1_PWM3_B1
AUDIO_EXT_REFCLK1
MCAN4_TX
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0
1
0
0/1
1
2
I
3
IO
IO
O
IO
IO
IO
I
5
6
GPIO0_8
7
0
MCASP3_AXR1
12
0
AJ20
prg1_pru0_gpo8
PRG1_PRU0_GPO8
PRG1_PRU0_GPI8
PRG1_PWM2_A1
RMII5_RXD0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0
0
1
0
0
0/1
1
3
IO
I
5
MCAN4_RX
6
I
GPIO0_9
7
IO
O
O
IO
IO
I
GPMC0_OEn_REn
VOUT0_DATA22
MCASP3_AXR2
8
10
12
0
AG20
prg1_pru0_gpo9
PRG1_PRU0_GPO9
PRG1_PRU0_GPI9
PRG1_UART0_CTSn
PRG1_PWM3_TZ_IN
SPI6_CS1
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
1
0
1
0
0
0
0/1
1
2
I
3
I
4
IO
I
RMII5_RXD1
5
GPIO0_10
7
IO
O
IO
O
IO
GPMC0_ADVn_ALE
PRG1_IEP0_EDIO_DATA_IN_OUT28
VOUT0_DATA23
MCASP3_ACLKX
8
9
10
12
0
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AD21
AF24
AJ24
prg1_pru0_gpo10
PRG1_PRU0_GPO10
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
1.8 V/3.3 V VDDSHV2
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
0/1
0/1
0/1
PRG1_PRU0_GPI10
PRG1_UART0_RTSn
PRG1_PWM2_B1
SPI6_CS2
1
2
O
IO
IO
I
3
1
1
0
0
0
4
RMII5_CRS_DV
GPIO0_11
5
7
IO
O
IO
O
IO
IO
I
GPMC0_BE0n_CLE
PRG1_IEP0_EDIO_DATA_IN_OUT29
OBSCLK2
8
9
10
12
0
0
MCASP3_AFSX
PRG1_PRU0_GPO11
PRG1_PRU0_GPI11
PRG1_RGMII1_TD0
PRG1_PWM3_TZ_OUT
RGMII1_TD0
prg1_pru0_gpo11
OFF
7
Yes
0
0
1
2
O
O
O
O
IO
O
O
I
3
4
MCAN4_TX
6
GPIO0_12
7
0
RGMII7_TD0
9
VOUT0_DATA16
VPFE0_DATA0
10
11
12
0
MCASP7_ACLKX
PRG1_PRU0_GPO12
PRG1_PRU0_GPI12
PRG1_RGMII1_TD1
PRG1_PWM0_A0
RGMII1_TD1
IO
IO
I
0
0
0
prg1_pru0_gpo12
OFF
7
Yes
1
2
O
IO
O
I
3
0
4
MCAN4_RX
6
1
0
GPIO0_13
7
IO
O
O
I
RGMII7_TD1
9
VOUT0_DATA17
VPFE0_DATA1
10
11
12
MCASP7_AFSX
IO
0
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AG24
prg1_pru0_gpo13
PRG1_PRU0_GPO13
PRG1_PRU0_GPI13
PRG1_RGMII1_TD2
PRG1_PWM0_B0
RGMII1_TD2
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
1.8 V/3.3 V VDDSHV2
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
0/1
0/1
0/1
1
2
O
IO
O
O
IO
O
O
I
3
1
0
4
MCAN5_TX
6
GPIO0_14
7
RGMII7_TD2
9
VOUT0_DATA18
VPFE0_DATA2
MCASP7_AXR0
PRG1_PRU0_GPO14
PRG1_PRU0_GPI14
PRG1_RGMII1_TD3
PRG1_PWM0_A1
RGMII1_TD3
10
11
12
0
IO
IO
I
0
0
0
AD24
prg1_pru0_gpo14
OFF
7
Yes
1
2
O
IO
O
I
3
0
4
MCAN5_RX
6
1
0
GPIO0_15
7
IO
O
O
I
RGMII7_TD3
9
VOUT0_DATA19
VPFE0_DATA3
MCASP7_AXR1
PRG1_PRU0_GPO15
PRG1_PRU0_GPI15
PRG1_RGMII1_TX_CTL
PRG1_PWM0_B1
RGMII1_TX_CTL
MCAN6_TX
10
11
12
0
IO
IO
I
0
0
0
AC24
prg1_pru0_gpo15
OFF
7
Yes
1
2
O
IO
O
O
IO
O
O
I
3
1
0
4
6
GPIO0_16
7
RGMII7_TX_CTL
VOUT0_DATA20
VPFE0_DATA4
MCASP7_AXR2
MCASP7_ACLKR
9
10
11
12
13
IO
IO
0
0
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AE24
prg1_pru0_gpo16
PRG1_PRU0_GPO16
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0
0
0
1
0
0/1
PRG1_PRU0_GPI16
PRG1_RGMII1_TXC
PRG1_PWM0_A2
RGMII1_TXC
1
2
IO
IO
O
I
3
4
MCAN6_RX
6
GPIO0_17
7
IO
O
O
I
RGMII7_TXC
9
VOUT0_DATA21
VPFE0_DATA5
10
11
12
13
0
0
MCASP7_AXR3
MCASP7_AFSR
PRG1_PRU0_GPO17
PRG1_PRU0_GPI17
PRG1_IEP0_EDC_SYNC_OUT1
PRG1_PWM0_B2
RMII5_TXD1
IO
IO
IO
I
0
0
0
0
AJ21
prg1_pru0_gpo17
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0/1
1
2
O
IO
O
O
IO
I
3
1
0
5
MCAN5_TX
6
GPIO0_18
7
VPFE0_DATA6
11
12
0
MCASP3_AXR3
PRG1_PRU0_GPO18
PRG1_PRU0_GPI18
PRG1_IEP0_EDC_LATCH_IN0
PRG1_PWM0_TZ_IN
RMII5_RX_ER
IO
IO
I
0
0
0
0
0
0
1
0
AE21
prg1_pru0_gpo18
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0/1
1
2
I
3
I
5
I
MCAN5_RX
6
I
GPIO0_19
7
IO
I
VPFE0_DATA7
11
12
MCASP4_ACLKX
IO
0
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AH21
prg1_pru0_gpo19
PRG1_PRU0_GPO19
PRG1_PRU0_GPI19
PRG1_IEP0_EDC_SYNC_OUT0
PRG1_PWM0_TZ_OUT
RMII5_TXD0
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
1.8 V/3.3 V VDDSHV2
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
0/1
0/1
0/1
1
2
O
O
O
O
IO
I
3
5
MCAN6_TX
6
GPIO0_20
7
0
VOUT0_EXTPCLKIN
VPFE0_PCLK
10
11
12
0
I
0
0
0
0
0
0
0
0
0
MCASP4_AFSX
PRG1_PRU1_GPO0
PRG1_PRU1_GPI0
PRG1_RGMII2_RD0
RGMII2_RD0
IO
IO
I
AE22
prg1_pru1_gpo0
OFF
7
Yes
1
2
I
4
I
RMII2_RXD0
5
I
GPIO0_21
7
IO
I
RGMII8_RD0
8
VOUT0_DATA0
VPFE0_HD
10
11
12
0
O
I
MCASP8_ACLKX
PRG1_PRU1_GPO1
PRG1_PRU1_GPI1
PRG1_RGMII2_RD1
RGMII2_RD1
IO
IO
I
0
0
0
0
0
0
0
0
AG23
prg1_pru1_gpo1
OFF
7
Yes
1
2
I
4
I
RMII2_RXD1
5
I
GPIO0_22
7
IO
I
RGMII8_RD1
8
VOUT0_DATA1
VPFE0_FIELD
10
11
12
O
I
MCASP8_AFSX
IO
0
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AF23
prg1_pru1_gpo2
PRG1_PRU1_GPO2
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0
0
0
0
0
0
0/1
PRG1_PRU1_GPI2
PRG1_RGMII2_RD2
PRG1_PWM2_A2
RGMII2_RD2
1
2
I
3
IO
I
4
RMII2_CRS_DV
GPIO0_23
5
I
7
IO
I
RGMII8_RD2
8
VOUT0_DATA2
VPFE0_VD
10
11
12
13
0
O
I
MCASP8_AXR0
MCASP3_ACLKR
PRG1_PRU1_GPO3
PRG1_PRU1_GPI3
PRG1_RGMII2_RD3
RGMII2_RD3
IO
IO
IO
I
0
0
0
0
0
0
0
0
0
0
0
AD23
prg1_pru1_gpo3
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0/1
1
2
I
4
I
RMII2_RX_ER
GPIO0_24
5
I
7
IO
I
RGMII8_RD3
8
EQEP1_A
9
I
VOUT0_DATA3
VPFE0_WEN
10
11
12
13
14
O
I
MCASP8_AXR1
MCASP3_AFSR
TIMER_IO2
IO
IO
IO
0
0
0
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AH24
prg1_pru1_gpo4
PRG1_PRU1_GPO4
PRG1_PRU1_GPI4
PRG1_RGMII2_RX_CTL
PRG1_PWM2_B2
RGMII2_RX_CTL
RMII2_TXD0
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0
1
0
0/1
1
2
I
3
IO
I
4
5
O
IO
I
GPIO0_25
7
0
0
0
0
RGMII8_RX_CTL
EQEP1_B
8
9
I
VOUT0_DATA4
VPFE0_DATA13
MCASP8_AXR2
MCASP8_ACLKR
TIMER_IO3
10
11
12
13
14
0
O
I
IO
IO
IO
IO
I
0
0
0
0
0
AG21
prg1_pru1_gpo5
PRG1_PRU1_GPO5
PRG1_PRU1_GPI5
RMII5_TX_EN
MCAN6_RX
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0/1
1
5
O
I
6
1
0
0
GPIO0_26
7
IO
O
IO
O
IO
IO
IO
I
GPMC0_WPn
8
EQEP1_S
9
VOUT0_DATA5
MCASP4_AXR0
TIMER_IO4
10
12
14
0
0
AE23
prg1_pru1_gpo6
PRG1_PRU1_GPO6
PRG1_PRU1_GPI6
PRG1_RGMII2_RXC
RGMII2_RXC
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0
0
0/1
1
2
I
4
I
RMII2_TXD1
5
O
IO
I
GPIO0_27
7
0
0
RGMII8_RXC
8
VOUT0_DATA6
VPFE0_DATA14
MCASP8_AXR3
MCASP8_AFSR
TIMER_IO5
10
11
12
13
14
O
I
IO
IO
IO
0
0
0
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AC21
prg1_pru1_gpo7
PRG1_PRU1_GPO7
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0
1
0
0/1
PRG1_PRU1_GPI7
PRG1_IEP1_EDC_LATCH_IN1
SPI6_CS0
1
2
I
4
IO
I
RMII6_RX_ER
5
MCAN7_TX
6
O
IO
O
I
GPIO0_28
7
0
0
VOUT0_DATA7
VPFE0_DATA15
MCASP4_AXR1
UART3_TXD
10
11
12
14
0
IO
O
IO
I
Y23
prg1_pru1_gpo8
PRG1_PRU1_GPO8
PRG1_PRU1_GPI8
PRG1_PWM2_TZ_OUT
RMII6_RXD0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0/1
1
3
O
I
5
0
1
0
0
MCAN7_RX
6
I
GPIO0_29
7
IO
O
O
IO
I
GPMC0_CSn1
8
VOUT0_DATA8
MCASP4_AXR2
UART3_RXD
10
12
14
0
AF21
prg1_pru1_gpo9
PRG1_PRU1_GPO9
PRG1_PRU1_GPI9
PRG1_UART0_RXD
SPI6_CS3
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
1
1
0
0/1
1
2
I
4
IO
I
RMII6_RXD1
5
MCAN8_TX
6
O
IO
O
IO
O
IO
GPIO0_30
7
0
0
GPMC0_CSn0
8
PRG1_IEP0_EDIO_DATA_IN_OUT30
VOUT0_DATA9
MCASP4_AXR3
9
10
12
0
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AB23
prg1_pru1_gpo10
PRG1_PRU1_GPO10
PRG1_PRU1_GPI10
PRG1_UART0_TXD
PRG1_PWM2_TZ_IN
RMII6_CRS_DV
MCAN8_RX
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0/1
1
2
O
I
3
0
0
1
0
0
5
I
6
I
GPIO0_31
7
IO
O
IO
O
O
IO
IO
I
GPMC0_CLKOUT
PRG1_IEP0_EDIO_DATA_IN_OUT31
VOUT0_DATA10
GPMC0_FCLK_MUX
MCASP5_ACLKX
PRG1_PRU1_GPO11
PRG1_PRU1_GPI11
PRG1_RGMII2_TD0
RGMII2_TD0
8
9
10
11
12
0
0
AJ25
prg1_pru1_gpo11
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0/1
1
2
O
O
O
IO
O
IO
O
IO
IO
I
4
RMII2_TX_EN
5
GPIO0_32
7
0
0
RGMII8_TD0
8
EQEP1_I
9
VOUT0_DATA11
MCASP9_ACLKX
PRG1_PRU1_GPO12
PRG1_PRU1_GPI12
PRG1_RGMII2_TD1
PRG1_PWM1_A0
RGMII2_TD1
10
12
0
0
AH25
prg1_pru1_gpo12
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0/1
1
2
O
IO
O
O
IO
O
O
IO
3
0
4
MCAN7_TX
6
GPIO0_33
7
0
0
RGMII8_TD1
8
VOUT0_DATA12
MCASP9_AFSX
10
12
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AG25
prg1_pru1_gpo13
PRG1_PRU1_GPO13
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0/1
PRG1_PRU1_GPI13
PRG1_RGMII2_TD2
PRG1_PWM1_B0
RGMII2_TD2
1
2
O
IO
O
I
3
1
4
MCAN7_RX
6
1
0
0
GPIO0_34
7
IO
O
O
I
RGMII8_TD2
8
VOUT0_DATA13
VPFE0_DATA8
MCASP9_AXR0
MCASP4_ACLKR
PRG1_PRU1_GPO14
PRG1_PRU1_GPI14
PRG1_RGMII2_TD3
PRG1_PWM1_A1
RGMII2_TD3
10
11
12
13
0
IO
IO
IO
I
0
0
0
0
AH26
prg1_pru1_gpo14
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0/1
1
2
O
IO
O
O
IO
O
O
IO
IO
IO
I
3
0
4
MCAN8_TX
6
GPIO0_35
7
0
0
RGMII8_TD3
8
VOUT0_DATA14
MCASP9_AXR1
MCASP4_AFSR
PRG1_PRU1_GPO15
PRG1_PRU1_GPI15
PRG1_RGMII2_TX_CTL
PRG1_PWM1_B1
RGMII2_TX_CTL
MCAN8_RX
10
12
13
0
0
0
0
AJ27
prg1_pru1_gpo15
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0/1
1
2
O
IO
O
I
3
1
4
6
1
0
0
GPIO0_36
7
IO
O
O
I
RGMII8_TX_CTL
VOUT0_DATA15
VPFE0_DATA9
MCASP9_AXR2
MCASP9_ACLKR
8
10
11
12
13
IO
IO
0
0
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AJ26
prg1_pru1_gpo16
PRG1_PRU1_GPO16
PRG1_PRU1_GPI16
PRG1_RGMII2_TXC
PRG1_PWM1_A2
RGMII2_TXC
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0
0
0
0
0
0
0/1
1
2
IO
IO
O
IO
O
O
O
IO
IO
O
IO
I
3
4
GPIO0_37
7
RGMII8_TXC
8
VOUT0_VP2_HSYNC
VOUT0_HSYNC
9
10
MCASP9_AXR3
12
MCASP9_AFSR
13
0
0
0
0
VOUT0_VP0_HSYNC
PRG1_PRU1_GPO17
PRG1_PRU1_GPI17
PRG1_IEP1_EDC_SYNC_OUT1
PRG1_PWM1_B2
SPI6_CLK
14
AC22
prg1_pru1_gpo17
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
1/1
1
2
O
IO
IO
O
O
IO
O
O
I
3
1
0
4
RMII6_TX_EN
5
PRG1_ECAP0_SYNC_OUT
GPIO0_38
6
7
0
0
VOUT0_VP2_DE
VOUT0_DE
9
10
VPFE0_DATA10
11
MCASP5_AFSX
12
IO
O
I
VOUT0_VP0_DE
BOOTMODE1
14
Bootstrap
AJ22
prg1_pru1_gpo18
PRG1_PRU1_GPO18
PRG1_PRU1_GPI18
PRG1_IEP1_EDC_LATCH_IN0
PRG1_PWM1_TZ_IN
SPI6_D0
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0
0
0
0/1
1
2
I
3
I
4
IO
O
I
RMII6_TXD0
5
PRG1_ECAP0_SYNC_IN
GPIO0_39
6
0
0
7
IO
O
O
IO
O
VOUT0_VP2_VSYNC
VOUT0_VSYNC
9
10
12
14
MCASP5_AXR0
VOUT0_VP0_VSYNC
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AH22
prg1_pru1_gpo19
PRG1_PRU1_GPO19
0
IO
I
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0/1
PRG1_PRU1_GPI19
PRG1_IEP1_EDC_SYNC_OUT0
PRG1_PWM1_TZ_OUT
SPI6_D1
1
2
O
O
IO
O
IO
IO
O
IO
O
I
3
4
0
RMII6_TXD1
5
PRG1_ECAP0_IN_APWM_OUT
GPIO0_40
6
0
0
7
VOUT0_PCLK
10
12
0
MCASP5_AXR1
T6
resetstatz
RESETSTATz
OFF
PU
0
0
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
0/0
1/1
C28
RESET_REQZ
RESET_REQz
0
1.8 V/3.3 V VDDSHV0_MC Yes
U
U25
rgmii5_rxc
RGMII5_RXC
I2C6_SDA
0
I
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
1
0/1
2
IOD
O
VOUT1_DATA7
TRC_DATA5
4
5
O
EHRPWM_TZn_IN1
GPIO0_92
6
I
0
0
0
7
IO
OZ
IO
O
GPMC0_A8
8
MCASP10_AXR3
EHRPWM_SOCA
RGMII5_RX_CTL
RMII7_RX_ER
I2C2_SDA
12
14
0
U26
rgmii5_rx_ctl
I
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
1
0/1
1
I
2
IOD
O
VOUT1_DATA1
TRC_CTL
4
5
O
EHRPWM0_SYNCO
GPIO0_86
6
O
7
IO
OZ
IO
0
0
GPMC0_A2
8
MCASP10_AFSX
12
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
U29
U23
W26
V23
rgmii5_txc
RGMII5_TXC
RMII7_TX_EN
I2C6_SCL
0
O
O
OFF
7
1.8 V/3.3 V VDDSHV3
1.8 V/3.3 V VDDSHV3
1.8 V/3.3 V VDDSHV4
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
0
1
0/1
0/1
0/1
0/1
1
2
IOD
O
VOUT1_DATA6
TRC_DATA4
4
5
O
EHRPWM1_B
GPIO0_91
6
IO
IO
OZ
IO
O
0
0
0
7
GPMC0_A7
8
MCASP10_AXR2
RGMII5_TX_CTL
RMII7_CRS_DV
I2C2_SCL
12
0
rgmii5_tx_ctl
OFF
OFF
OFF
7
7
7
Yes
Yes
Yes
1
I
0
1
2
IOD
O
VOUT1_DATA0
TRC_CLK
4
5
O
EHRPWM0_SYNCI
GPIO0_85
6
I
0
0
0
7
IO
OZ
IO
I
GPMC0_A1
8
MCASP10_ACLKX
RGMII6_RXC
AUDIO_EXT_REFCLK2
VOUT1_DE
12
0
rgmii6_rxc
0
0
3
IO
O
4
TRC_DATA17
EHRPWM4_B
GPIO0_104
5
O
6
IO
IO
OZ
O
0
0
0
7
GPMC0_A20
VOUT1_VP0_DE
MCASP10_AXR7
RGMII6_RX_CTL
RMII8_RX_ER
VOUT1_DATA13
TRC_DATA11
EHRPWM3_A
GPIO0_98
8
9
12
0
IO
I
rgmii6_rx_ctl
0
0
1
I
4
O
5
O
6
IO
IO
OZ
IO
0
0
0
7
GPMC0_A14
MCASP10_AFSR
8
12
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
W29
rgmii6_txc
RGMII6_TXC
0
O
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
0/1
RMII8_TX_EN
SPI5_CLK
1
O
3
IO
O
VOUT1_PCLK
TRC_DATA16
EHRPWM4_A
GPIO0_103
4
5
O
6
IO
IO
0
0
0
7
GPMC0_A19
MCASP10_AXR6
RGMII6_TX_CTL
RMII8_CRS_DV
VOUT1_DATA12
TRC_DATA10
GPIO0_97
8
OZ
IO
O
I
12
0
Y28
rgmii6_tx_ctl
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0/1
1
0
4
O
O
IO
OZ
IO
I
5
7
0
0
GPMC0_A13
MCASP10_ACLKR
RGMII5_RD0
RMII7_RXD0
UART6_RTSn
VOUT1_DATA11
TRC_DATA9
8
12
0
T23
rgmii5_rd0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
0/1
1
I
3
O
O
O
IO
OZ
IO
I
4
5
GPIO0_96
7
0
0
GPMC0_A12
MCASP11_AXR3
RGMII5_RD1
RMII7_RXD1
UART6_CTSn
VOUT1_DATA10
TRC_DATA8
8
12
0
R23
rgmii5_rd1
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
1
0/1
1
I
3
I
4
O
O
I
5
EHRPWM_TZn_IN2
GPIO0_95
6
0
0
0
7
IO
OZ
IO
O
GPMC0_A11
8
MCASP11_AXR2
EHRPWM_SOCB
12
14
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
U24
U27
U28
V27
rgmii5_rd2
RGMII5_RD2
UART3_RTSn
UART6_TXD
VOUT1_DATA9
TRC_DATA7
EHRPWM2_B
GPIO0_94
0
I
OFF
7
1.8 V/3.3 V VDDSHV3
1.8 V/3.3 V VDDSHV3
1.8 V/3.3 V VDDSHV3
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
0
0/1
0/1
0/1
0/1
1
O
O
O
O
IO
IO
3
4
5
6
0
0
0
7
GPMC0_A10
MCASP11_AXR1
RGMII5_RD3
UART3_CTSn
UART6_RXD
VOUT1_DATA8
TRC_DATA6
EHRPWM2_A
GPIO0_93
8
OZ
IO
I
12
0
rgmii5_rd3
rgmii5_td0
rgmii5_td1
OFF
OFF
OFF
7
7
7
Yes
Yes
Yes
0
1
1
1
I
3
I
4
O
5
O
6
IO
IO
OZ
IO
O
0
0
0
7
GPMC0_A9
8
MCASP11_AXR0
RGMII5_TD0
RMII7_TXD0
I2C3_SDA
12
0
1
O
2
IOD
O
1
VOUT1_DATA5
TRC_DATA3
EHRPWM1_A
GPIO0_90
4
5
O
6
IO
IO
OZ
IO
O
0
0
0
7
GPMC0_A6
8
MCASP11_AFSX
RGMII5_TD1
RMII7_TXD1
I2C3_SCL
12
0
1
O
2
IOD
O
1
VOUT1_DATA4
TRC_DATA2
EHRPWM0_B
GPIO0_89
4
5
O
6
IO
IO
OZ
IO
0
0
0
7
GPMC0_A5
8
MCASP11_ACLKX
12
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
V29
V28
W25
W24
rgmii5_td2
RGMII5_TD2
0
O
OFF
7
1.8 V/3.3 V VDDSHV3
1.8 V/3.3 V VDDSHV3
1.8 V/3.3 V VDDSHV4
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
0/1
0/1
0/1
0/1
UART3_TXD
1
O
SYNC3_OUT
VOUT1_DATA3
TRC_DATA1
3
O
4
O
5
O
EHRPWM0_A
GPIO0_88
6
IO
IO
0
0
0
7
GPMC0_A4
8
OZ
IO
O
I
MCASP10_AXR1
RGMII5_TD3
UART3_RXD
SYNC2_OUT
VOUT1_DATA2
TRC_DATA0
12
0
rgmii5_td3
rgmii6_rd0
rgmii6_rd1
OFF
OFF
OFF
7
7
7
Yes
Yes
Yes
1
1
3
O
O
O
I
4
5
EHRPWM_TZn_IN0
GPIO0_87
6
0
0
0
7
IO
OZ
IO
I
GPMC0_A3
8
MCASP10_AXR0
RGMII6_RD0
RMII8_RXD0
SPI5_CS1
12
0
0
0
1
0
1
I
3
IO
IO
O
I
AUDIO_EXT_REFCLK3
TRC_DATA21
EHRPWM_TZn_IN5
GPIO0_108
4
5
6
0
0
0
7
IO
O
IO
I
GPMC0_DIR
8
MCASP11_AXR7
RGMII6_RD1
RMII8_RXD1
SPI5_D1
12
0
0
0
0
0
1
I
3
IO
I
VOUT1_EXTPCLKIN
TRC_DATA20
EHRPWM5_B
GPIO0_107
4
5
O
IO
IO
O
IO
6
0
0
0
7
GPMC0_BE1n
MCASP11_AXR6
8
12
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
Y27
rgmii6_rd2
RGMII6_RD2
UART4_RTSn
UART5_TXD
0
I
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0/1
1
O
O
O
IO
IO
3
TRC_DATA19
EHRPWM5_A
GPIO0_106
5
6
0
0
0
7
GPMC0_A22
8
OZ
IO
I
MCASP11_AXR5
RGMII6_RD3
UART4_CTSn
UART5_RXD
12
0
Y29
rgmii6_rd3
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
1
1
0/1
1
I
3
I
CLKOUT
4
OZ
O
TRC_DATA18
EHRPWM_TZn_IN4
GPIO0_105
5
6
I
0
0
0
7
IO
OZ
IO
O
GPMC0_A21
8
MCASP11_AXR4
RGMII6_TD0
12
0
W27
rgmii6_td0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0/1
RMII8_TXD0
1
O
SPI5_CS0
3
IO
O
1
VOUT1_HSYNC
TRC_DATA15
EHRPWM_TZn_IN3
GPIO0_102
4
5
O
6
I
0
0
0
7
IO
OZ
O
GPMC0_A18
8
VOUT1_VP0_HSYNC
MCASP10_AXR5
RGMII6_TD1
9
12
0
IO
O
V25
rgmii6_td1
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0/1
RMII8_TXD1
1
O
SPI5_D0
3
IO
O
0
VOUT1_VSYNC
TRC_DATA14
EHRPWM3_SYNCO
GPIO0_101
4
5
O
6
O
7
IO
OZ
O
0
0
GPMC0_A17
8
VOUT1_VP0_VSYNC
MCASP10_AXR4
9
12
IO
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
W28
rgmii6_td2
RGMII6_TD2
0
O
O
IO
O
O
I
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0/1
UART4_TXD
1
SPI5_CS2
3
1
VOUT1_DATA15
TRC_DATA13
EHRPWM3_SYNCI
GPIO0_100
4
5
6
0
0
0
7
IO
GPMC0_A16
8
OZ
IO
O
MCASP11_AFSR
RGMII6_TD3
12
0
W23
rgmii6_td3
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0/1
UART4_RXD
1
I
1
1
SPI5_CS3
3
IO
O
VOUT1_DATA14
TRC_DATA12
EHRPWM3_B
GPIO0_99
4
5
O
6
IO
IO
OZ
IO
IO
0
0
0
7
GPMC0_A15
8
MCASP11_ACLKR
SERDES4_REFCLK_N
12
E7
SERDES4_REFCLK_N
serdes0_rext
OFF
OFF
0.8 V
0.8 V
VDDA_0P8_DP
4-L-PHY
2-L-PHY
/
VDDA_1P8_DP
AE18
SERDES0_REXT
SERDES1_REXT
SERDES2_REXT
A
A
A
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
AE13
AD13
serdes1_rext
serdes2_rext
OFF
OFF
0.8 V
0.8 V
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
2-L-PHY
2-L-PHY
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
F9
serdes4_rext
SERDES4_REXT
I
OFF
OFF
OFF
0.8 V
0.8 V
0.8 V
VDDA_0P8_DP
4-L-PHY
4-L-PHY
2-L-PHY
/
VDDA_1P8_DP
E8
SERDES4_REFCLK_P
serdes3_rext
SERDES4_REFCLK_P
SERDES3_REXT
IO
A
VDDA_0P8_DP
/
VDDA_1P8_DP
AE8
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AH19
SERDES0_RX0_N
SERDES0_RX0_N
I
OFF
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
2-L-PHY
2-L-PHY
2-L-PHY
2-L-PHY
2-L-PHY
2-L-PHY
SGMII1_RXN0
PCIE0_RXN0
I
I
I
I
USB0_SSRX2N
SERDES0_RX0_P
AJ18
AH18
AJ17
AF19
AG18
SERDES0_RX0_P
SERDES0_RX1_N
SERDES0_RX1_P
SERDES0_TX0_N
SERDES0_TX0_P
OFF
OFF
OFF
OFF
OFF
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
SGMII1_RXP0
PCIE0_RXP0
I
I
I
I
USB0_SSRX2P
SERDES0_RX1_N
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
SGMII2_RXN0
PCIE0_RXN1
I
I
I
I
USB0_SSRX1N
SERDES0_RX1_P
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
SGMII2_RXP0
PCIE0_RXP1
I
I
USB0_SSRX1P
SERDES0_TX0_N
I
O
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
SGMII1_TXN0
PCIE0_TXN0
O
O
O
O
USB0_SSTX2N
SERDES0_TX0_P
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
SGMII1_TXP0
PCIE0_TXP0
USB0_SSTX2P
O
O
O
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AF18
AG17
AH15
SERDES0_TX1_N
SERDES0_TX1_N
O
OFF
0.8 V
0.8 V
0.8 V
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
2-L-PHY
2-L-PHY
2-L-PHY
SGMII2_TXN0
PCIE0_TXN1
O
O
O
O
USB0_SSTX1N
SERDES0_TX1_P
SERDES0_TX1_P
OFF
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
SGMII2_TXP0
PCIE0_TXP1
O
O
O
I
USB0_SSTX1P
SERDES1_RX0_N
SERDES1_RX0_N
OFF
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
SGMII3_RXN0
I
I
I
I
I
PCIE1_RXN0
USB1_SSRX2N
PRG1_SGMII0_RXN0
SERDES1_RX0_P
AJ14
SERDES1_RX0_P
OFF
0.8 V
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
2-L-PHY
SGMII3_RXP0
I
I
I
I
I
PCIE1_RXP0
USB1_SSRX2P
PRG1_SGMII0_RXP0
SERDES1_RX1_N
AH16
SERDES1_RX1_N
OFF
0.8 V
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
2-L-PHY
SGMII4_RXN0
I
I
I
I
PCIE1_RXN1
USB1_SSRX1N
PRG1_SGMII1_RXN0
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AJ15
SERDES1_RX1_P
SERDES1_RX1_P
I
OFF
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
2-L-PHY
2-L-PHY
2-L-PHY
2-L-PHY
2-L-PHY
SGMII4_RXP0
I
PCIE1_RXP1
I
USB1_SSRX1P
PRG1_SGMII1_RXP0
SERDES1_TX0_N
I
I
AF15
AG14
AF16
AG15
SERDES1_TX0_N
SERDES1_TX0_P
SERDES1_TX1_N
SERDES1_TX1_P
O
OFF
OFF
OFF
OFF
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
SGMII3_TXN0
O
O
O
O
O
PCIE1_TXN0
USB1_SSTX2N
PRG1_SGMII0_TXN0
SERDES1_TX0_P
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
SGMII3_TXP0
O
O
O
O
O
PCIE1_TXP0
USB1_SSTX2P
PRG1_SGMII0_TXP0
SERDES1_TX1_N
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
SGMII4_TXN0
O
O
O
O
O
PCIE1_TXN1
USB1_SSTX1N
PRG1_SGMII1_TXN0
SERDES1_TX1_P
VDDA_0P8_SE
RDES0_1 / VDD
A_1P8_SERDE
S0_1
SGMII4_TXP0
O
O
O
O
PCIE1_TXP1
USB1_SSTX1P
PRG1_SGMII1_TXP0
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AH13
AJ12
AH12
AJ11
AF13
AG12
SERDES2_RX0_N
SERDES2_RX0_N
I
OFF
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
2-L-PHY
2-L-PHY
2-L-PHY
2-L-PHY
2-L-PHY
2-L-PHY
PCIE2_RXN0
I
I
USB1_SSRX2N
PRG1_SGMII0_RXN0
SERDES2_RX0_P
SERDES2_RX0_P
SERDES2_RX1_N
SERDES2_RX1_P
SERDES2_TX0_N
SERDES2_TX0_P
I
OFF
OFF
OFF
OFF
OFF
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
PCIE2_RXP0
I
I
USB1_SSRX2P
PRG1_SGMII0_RXP0
SERDES2_RX1_N
I
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
PCIE2_RXN1
I
I
USB1_SSRX1N
PRG1_SGMII1_RXN0
SERDES2_RX1_P
I
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
PCIE2_RXP1
I
I
USB1_SSRX1P
PRG1_SGMII1_RXP0
SERDES2_TX0_N
O
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
PCIE2_TXN0
O
O
USB1_SSTX2N
PRG1_SGMII0_TXN0
SERDES2_TX0_P
O
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
PCIE2_TXP0
O
O
USB1_SSTX2P
PRG1_SGMII0_TXP0
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AF12
SERDES2_TX1_N
SERDES2_TX1_N
O
OFF
0.8 V
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
2-L-PHY
PCIE2_TXN1
O
O
USB1_SSTX1N
PRG1_SGMII1_TXN0
SERDES2_TX1_P
AG11
SERDES2_TX1_P
O
OFF
0.8 V
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
2-L-PHY
PCIE2_TXP1
O
O
USB1_SSTX1P
PRG1_SGMII1_TXP0
SERDES3_RX0_N
AH9
AJ8
SERDES3_RX0_N
SERDES3_RX0_P
SERDES3_RX1_N
SERDES3_RX1_P
SERDES3_TX0_N
I
OFF
OFF
OFF
OFF
OFF
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
2-L-PHY
2-L-PHY
2-L-PHY
2-L-PHY
2-L-PHY
PCIE3_RXN0
I
I
I
USB0_SSRX2N
SERDES3_RX0_P
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
PCIE3_RXP0
I
I
I
USB0_SSRX2P
SERDES3_RX1_N
AH10
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
PCIE3_RXN1
I
I
I
USB0_SSRX1N
SERDES3_RX1_P
AJ9
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
PCIE3_RXP1
I
USB0_SSRX1P
SERDES3_TX0_N
I
AF9
O
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
PCIE3_TXN0
O
O
USB0_SSTX2N
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AG8
AF10
AG9
SERDES3_TX0_P
SERDES3_TX0_P
O
OFF
0.8 V
0.8 V
0.8 V
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
2-L-PHY
2-L-PHY
2-L-PHY
PCIE3_TXP0
O
O
O
USB0_SSTX2P
SERDES3_TX1_N
SERDES3_TX1_N
SERDES3_TX1_P
OFF
OFF
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
PCIE3_TXN1
O
O
O
USB0_SSTX1N
SERDES3_TX1_P
VDDA_0P8_SE
RDES2_3 / VDD
A_1P8_SERDE
S2_3
PCIE3_TXP1
O
O
I
USB0_SSTX1P
SERDES4_RX0_N
D9
C10
D8
C9
D6
C7
D5
SERDES4_RX0_N
SERDES4_RX0_P
SERDES4_RX1_N
SERDES4_RX1_P
SERDES4_RX2_N
SERDES4_RX2_P
SERDES4_RX3_N
OFF
OFF
OFF
OFF
OFF
OFF
OFF
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
VDDA_0P8_DP
4-L-PHY
4-L-PHY
4-L-PHY
4-L-PHY
4-L-PHY
4-L-PHY
4-L-PHY
/
VDDA_1P8_DP
SGMII5_RXN0
I
I
SERDES4_RX0_P
VDDA_0P8_DP
/
VDDA_1P8_DP
SGMII5_RXP0
I
I
SERDES4_RX1_N
VDDA_0P8_DP
/
VDDA_1P8_DP
SGMII6_RXN0
I
I
SERDES4_RX1_P
VDDA_0P8_DP
/
VDDA_1P8_DP
SGMII6_RXP0
I
I
SERDES4_RX2_N
VDDA_0P8_DP
/
VDDA_1P8_DP
SGMII7_RXN0
I
I
SERDES4_RX2_P
VDDA_0P8_DP
/
VDDA_1P8_DP
SGMII7_RXP0
I
I
SERDES4_RX3_N
VDDA_0P8_DP
/
VDDA_1P8_DP
SGMII8_RXN0
I
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
C6
SERDES4_RX3_P
SERDES4_RX3_P
I
OFF
0.8 V
0.8 V
VDDA_0P8_DP
4-L-PHY
4-L-PHY
/
VDDA_1P8_DP
SGMII8_RXP0
I
B11
SERDES4_TX0_N
SERDES4_TX0_P
SERDES4_TX1_N
SERDES4_TX1_P
SERDES4_TX2_N
SERDES4_TX2_P
SERDES4_TX3_N
SERDES4_TX3_P
SERDES4_TX0_N
O
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
VDDA_0P8_DP
/
VDDA_1P8_DP
DP0_TX0_N
O
O
O
SGMII5_TXN0
SERDES4_TX0_P
A12
B10
A11
B8
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
VDDA_0P8_DP
4-L-PHY
4-L-PHY
4-L-PHY
4-L-PHY
4-L-PHY
4-L-PHY
4-L-PHY
/
VDDA_1P8_DP
DP0_TX0_P
O
O
O
SGMII5_TXP0
SERDES4_TX1_N
VDDA_0P8_DP
/
VDDA_1P8_DP
DP0_TX1_N
O
O
O
SGMII6_TXN0
SERDES4_TX1_P
VDDA_0P8_DP
/
VDDA_1P8_DP
DP0_TX1_P
O
O
O
SGMII6_TXP0
SERDES4_TX2_N
VDDA_0P8_DP
/
VDDA_1P8_DP
DP0_TX2_N
O
O
O
SGMII7_TXN0
SERDES4_TX2_P
A9
VDDA_0P8_DP
/
VDDA_1P8_DP
DP0_TX2_P
O
O
O
SGMII7_TXP0
SERDES4_TX3_N
B7
VDDA_0P8_DP
/
VDDA_1P8_DP
DP0_TX3_N
O
O
O
SGMII8_TXN0
SERDES4_TX3_P
A8
VDDA_0P8_DP
/
VDDA_1P8_DP
DP0_TX3_P
O
O
SGMII8_TXP0
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
U4
soc_safety_errorn
SOC_SAFETY_ERRORn
SPI0_CLK
0
IO
IO
I
PD
0
1.8 V/3.3 V VDDSHV0
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
1/0
0/1
AA1
spi0_clk
0
1
2
7
0
1
2
3
7
8
0
1
7
0
1
2
5
6
7
0
1
2
7
0
2
7
0
1
3
6
7
8
0
1
2
3
7
OFF
7
Yes
0
1
1
0
0
1
1
1
0
0
1
UART1_CTSn
I2C2_SCL
IOD
IO
IO
I
GPIO0_113
Y1
spi1_clk
SPI1_CLK
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
0/1
UART5_CTSn
I2C4_SDA
IOD
I
UART2_RXD
GPIO0_118
IO
O
PRG0_IEP0_EDC_SYNC_OUT0
SPI0_CS0
AA2
Y4
spi0_cs0
spi0_cs1
IO
O
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV0
1.8 V/3.3 V VDDSHV0
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
0/1
0/1
UART0_RTSn
GPIO0_111
IO
IO
O
0
1
SPI0_CS1
CPTS0_TS_COMP
I2C3_SCL
IOD
I
1
0
DP0_HPD
PRG1_IEP0_EDIO_OUTVALID
GPIO0_112
O
IO
IO
O
0
0
AB5
spi0_d0
SPI0_D0
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
0/1
UART1_RTSn
I2C2_SDA
IOD
IO
IO
IOD
IO
IO
I
1
0
0
1
0
1
1
1
GPIO0_114
AA3
Y3
spi0_d1
SPI0_D1
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV0
1.8 V/3.3 V VDDSHV0
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
0/1
0/1
I2C6_SCL
GPIO0_115
spi1_cs0
SPI1_CS0
UART0_CTSn
UART5_RXD
PRG0_IEP0_EDIO_OUTVALID
GPIO0_116
I
O
IO
I
0
0
1
PRG0_IEP0_EDC_LATCH_IN0
SPI1_CS1
W4
spi1_cs1
IO
O
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
0/1
CPTS0_TS_SYNC
I2C3_SDA
IOD
O
1
0
UART5_TXD
GPIO0_117
IO
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
Y5
spi1_d0
SPI1_D0
0
IO
O
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
0
1
0/1
UART5_RTSn
I2C4_SCL
1
2
3
7
8
0
2
7
8
0
IOD
O
UART2_TXD
GPIO0_119
IO
I
0
0
0
1
0
0
PRG0_IEP1_EDC_LATCH_IN0
SPI1_D1
Y2
spi1_d1
IO
IOD
IO
O
OFF
PU
7
0
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
0/1
1/1
I2C6_SDA
GPIO0_120
PRG0_IEP1_EDC_SYNC_OUT0
TCK
E29
tck
I
1.8 V/3.3 V VDDSHV0_MC Yes
U
V1
V3
V6
tdi
TDI
0
I
PU
0
0
7
1.8 V/3.3 V VDDSHV0
1.8 V/3.3 V VDDSHV0
1.8 V/3.3 V VDDSHV0
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
1/1
0/0
1/1
tdo
TDO
0
OZ
IO
IO
O
IO
IO
I
PU
timer_io0
TIMER_IO0
ECAP1_IN_APWM_OUT
SYSCLKOUT0
SPI7_D0
0
OFF
0
0
1
2
6
0
0
GPIO1_13
7
BOOTMODE4
TIMER_IO1
ECAP2_IN_APWM_OUT
OBSCLK0
Bootstrap
V5
timer_io1
0
IO
IO
O
IO
IO
I
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
0
0
1/1
1
2
SPI7_D1
6
0
0
GPIO1_14
7
BOOTMODE5
TMS
Bootstrap
V2
tms
0
0
I
PU
PD
0
0
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
1/1
1/1
F24
trstn
TRSTn
I
1.8 V/3.3 V VDDSHV0_MC Yes
U
AC2
uart0_ctsn
UART0_CTSn
TIMER_IO6
SPI0_CS2
0
1
2
3
4
5
7
8
I
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
1
0
1
1
1
0
0
0
0/1
IO
IO
I
MCAN2_RX
SPI2_CS0
IO
I
EQEP0_A
GPIO0_123
MLB0_MLBSIG
IO
IO
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AB1
uart0_rtsn
UART0_RTSn
0
O
IO
IO
O
IO
I
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
0/1
TIMER_IO7
SPI0_CS3
1
2
3
4
5
7
0
4
7
0
4
6
7
0
1
4
5
7
8
0
1
4
5
7
8
0
6
7
0
5
6
7
0
1
MCAN2_TX
SPI2_CLK
0
0
0
1
1
0
EQEP0_B
GPIO0_124
UART0_RXD
SPI2_CS1
IO
I
AB2
AB3
uart0_rxd
uart0_txd
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV0
1.8 V/3.3 V VDDSHV0
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
0/1
0/1
IO
IO
O
IO
IO
IO
I
GPIO0_121
UART0_TXD
SPI2_CS2
1
1
0
1
1
0
0
0
0
SPI7_CS1
GPIO0_122
UART1_CTSn
MCAN3_RX
SPI2_D0
AC4
uart1_ctsn
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
0/1
I
IO
IO
IO
I
EQEP0_S
GPIO0_127
MLB0_MLBCLK
UART1_RTSn
MCAN3_TX
SPI2_D1
AD5
uart1_rtsn
O
O
IO
IO
IO
IO
I
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
0/1
0
0
0
0
1
1
0
EQEP0_I
GPIO1_0
MLB0_MLBDAT
UART1_RXD
SPI7_CS2
AA4
AB4
uart1_rxd
uart1_txd
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV0
1.8 V/3.3 V VDDSHV0
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
0/1
0/1
IO
IO
O
O
IO
IO
O
GPIO0_125
UART1_TXD
I3C0_SDAPULLEN
SPI7_CS3
1
0
GPIO0_126
UFS0_REF_CLK
AE6
ufs0_ref_clk
OFF
0.8 V
VDDA_0P8_UF
M-PHY
S /
VDDA_1P8_UF
S
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AD6
AH3
AH4
AJ2
AJ3
AG6
AG5
AF7
AF6
AJ5
ufs0_rstn
UFS0_RSTn
O
I
OFF
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
0.8 V
3.3 V
VDDA_0P8_UF
S /
VDDA_1P8_UF
S
M-PHY
M-PHY
M-PHY
M-PHY
M-PHY
M-PHY
M-PHY
M-PHY
M-PHY
USB2PHY
ufs0_rx_dn0
ufs0_rx_dn1
ufs0_rx_dp0
ufs0_rx_dp1
ufs0_tx_dn0
ufs0_tx_dn1
ufs0_tx_dp0
ufs0_tx_dp1
usb0_dm
UFS0_RX_DN0
UFS0_RX_DN1
UFS0_RX_DP0
UFS0_RX_DP1
UFS0_TX_DN0
UFS0_TX_DN1
UFS0_TX_DP0
UFS0_TX_DP1
USB0_DM
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
VDDA_0P8_UF
S /
VDDA_1P8_UF
S
I
VDDA_0P8_UF
S /
VDDA_1P8_UF
S
I
VDDA_0P8_UF
S /
VDDA_1P8_UF
S
I
VDDA_0P8_UF
S /
VDDA_1P8_UF
S
O
O
O
O
IO
VDDA_0P8_UF
S /
VDDA_1P8_UF
S
VDDA_0P8_UF
S /
VDDA_1P8_UF
S
VDDA_0P8_UF
S /
VDDA_1P8_UF
S
VDDA_0P8_UF
S /
VDDA_1P8_UF
S
VDDA_0P8_US
B /
VDDA_1P8_US
B /
VDDA_3P3_US
B
AH6
U6
usb0_dp
USB0_DP
IO
OFF
PD
3.3 V
VDDA_0P8_US
B /
VDDA_1P8_US
B /
VDDA_3P3_US
B
USB2PHY
LVCMOS
usb0_drvvbus
USB0_DRVVBUS
USB1_DRVVBUS
GPIO1_29
0
O
7
1.8 V/3.3 V VDDSHV0
Yes
PU/PD
0/1
1
7
O
IO
0
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AC6
AB6
AC7
AH7
AJ6
usb0_id
USB0_ID
A
OFF
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
VDDA_0P8_US
B /
VDDA_1P8_US
B /
VDDA_3P3_US
B
USB2PHY
USB2PHY
USB2PHY
USB2PHY
USB2PHY
USB2PHY
USB2PHY
USB2PHY
usb0_rcalib
usb0_vbus
usb1_dm
usb1_dp
USB0_RCALIB
USB0_VBUS
USB1_DM
IO
A
OFF
OFF
OFF
OFF
OFF
OFF
OFF
VDDA_0P8_US
B /
VDDA_1P8_US
B /
VDDA_3P3_US
B
VDDA_0P8_US
B /
VDDA_1P8_US
B /
VDDA_3P3_US
B
IO
IO
A
VDDA_0P8_U
SB /
VDDA_1P8_US
B /
VDDA_3P3_US
B
USB1_DP
VDDA_0P8_U
SB /
VDDA_1P8_US
B /
VDDA_3P3_US
B
AD7
AD9
AD8
usb1_id
USB1_ID
VDDA_0P8_U
SB /
VDDA_1P8_US
B /
VDDA_3P3_US
B
usb1_rcalib
usb1_vbus
USB1_RCALIB
USB1_VBUS
VDDAR_CORE
IO
A
VDDA_0P8_U
SB /
VDDA_1P8_US
B /
VDDA_3P3_US
B
VDDA_0P8_U
SB /
VDDA_1P8_US
B /
VDDA_3P3_US
B
L14, V13, V16, VDDAR_CORE
W19
PWR
L11, W12
K19, T19
H17
VDDAR_CPU
vddar_mcu
VDDAR_CPU
vddar_mcu
PWR
PWR
PWR
VDDA_0P8_CSIRX
VDDA_0P8_CSIRX
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
G12, J12
VDDA_0P8_DP
VDDA_0P8_DP
PWR
G14, H13
H15
VDDA_0P8_DP_C
VDDA_0P8_DSITX
VDDA_0P8_DSITX_C
VDDA_0P8_UFS
VDDA_0P8_DP_C
VDDA_0P8_DSITX
VDDA_0P8_DSITX_C
VDDA_0P8_UFS
PWR
PWR
PWR
PWR
PWR
PWR
J16
AB9
AA10
VDDA_0P8_USB
VDDA_0P8_USB
AA15, Y14,
Y16
VDDA_0P8_SERDES0_1
VDDA_0P8_SERDES0_1
AA12, Y11,
Y13
VDDA_0P8_SERDES2_3
VDDA_0P8_SERDES2_3
PWR
AB14, AB15
AB12, AB13
G16
VDDA_0P8_SERDES_C0_1
VDDA_0P8_SERDES_C2_3
VDDA_1P8_CSIRX
VDDA_1P8_DP
VDDA_0P8_SERDES_C0_1
VDDA_0P8_SERDES_C2_3
VDDA_1P8_CSIRX
VDDA_1P8_DP
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
A
H11
J14
VDDA_1P8_DSITX
VDDA_1P8_UFS
VDDA_1P8_DSITX
VDDA_1P8_UFS
AC8
AC9
vdda_1p8_usb
vdda_1p8_usb
AC14, AC15
AC11, AC12
AB10
N22
VDDA_1P8_SERDES0_1
VDDA_1P8_SERDES2_3
vdda_3p3_usb
VDDA_1P8_SERDES0_1
VDDA_1P8_SERDES2_3
vdda_3p3_usb
VDDA_ADC0
VDDA_ADC0
M23
VDDA_ADC1
VDDA_ADC1
N9
VDDA_0P8_PLL_DDR
VDDA_MCU_PLLGRP0
VDDA_MCU_TEMP
VDDA_1P8_MLB
VDDA_0P8_PLL_DDR
VDDA_MCU_PLLGRP0
VDDA_MCU_TEMP
VDDA_1P8_MLB
G18
P21
W7
Y20
VDDA_PLLGRP0
VDDA_PLLGRP1
VDDA_PLLGRP2
VDDA_PLLGRP3
VDDA_PLLGRP4
VDDA_PLLGRP5
VDDA_PLLGRP6
VDDA_0P8_PLL_MLB
vdda_por_wkup
VDDA_PLLGRP0
VDDA_PLLGRP1
VDDA_PLLGRP2
VDDA_PLLGRP3
VDDA_PLLGRP4
VDDA_PLLGRP5
VDDA_PLLGRP6
VDDA_0P8_PLL_MLB
vdda_por_wkup
W17
M17
L12
R11
P9
W18
W8
P22
W15
VDDA_TEMP0_1
VDDA_TEMP2_3
VMON_ER_VSYS
VDDA_TEMP0_1
VDDA_TEMP2_3
VMON_ER_VSYS
H9
M26
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
V19
VMON_IR_VEXT
VMON_IR_VEXT
A
H22
VDDA_WKUP
VDDSHV0
VDDA_WKUP
VDDSHV0
PWR
PWR
PWR
PWR
U8, V7
L22, M22
VDDSHV0_MCU
VDDSHV1
VDDSHV0_MCU
VDDSHV1
AA19, AA20,
AC19, AC20
H19, H21, J20 VDDSHV1_MCU
VDDSHV1_MCU
VDDSHV2
PWR
PWR
AA17, AB16,
AB18, AC17
VDDSHV2
J22, K21
V21, W22
AA21, Y22
T20, T22
U20, U22
VDDSHV2_MCU
VDDSHV3
VDDSHV2_MCU
VDDSHV3
VDDSHV4
VDDSHV5
VDDSHV6
vdds_ddr
PWR
PWR
PWR
PWR
PWR
PWR
VDDSHV4
VDDSHV5
VDDSHV6
A1, G8, J8, K7, vdds_ddr
L8, M7, N8,
P7, R8, T1
H7, J6, R6, T7 vdds_ddr_bias
vdds_ddr_bias
VDDS_DDR_C
vdds_mmc0
PWR
PWR
PWR
PWR
PWR
M9
VDDS_DDR_C
vdds_mmc0
AA8, AB7, Y7
R21
VDDS_OSC1
VDDS_OSC1
VDD_CORE
J10, K11, K13, VDD_CORE
K15, K17, K9,
L10, L16, L18,
M15, N14,
N16, N18, P13,
P15, P17, R14,
R16, R18, R20,
T15, T17, T9,
U14, U16, U18,
V15, V17, V20,
W14
N10, P11, R10, VDD_CPU
R12, U10, V11,
VDD_CPU
PWR
V9, W10
Y9
VDDA_0P8_DLL_MMC0
VDDA_0P8_DLL_MMC0
vdd_mcu
PWR
PWR
L20, M19,
vdd_mcu
M21, N20, P19
AB11
F17
vpp_core
vpp_core
PWR
PWR
VPP_MCU
VPP_MCU
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
AA13, AC10,
AC13, AD11,
AD14, AD17,
AE10, AE12,
AE15, AE16,
AE19, AE7,
AF20, AF25,
AF5, AG4,
vss
vss
GND
AG7, AH2,
AH20, AH5,
AJ4, AJ7, B3,
B6, C1, C5,
D2, D4, E1,
E5, F4, G1,
G7, H4, H6,
K1, K4, L3, M1,
M28, M4, M6,
N27, N29, N3,
P1, P28, P4,
R3, U5
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
A10, A13, A16, VSS
A19, A22, A7,
AA11, AA14,
AA16, AA18,
AA7, AA9,
VSS
GND
AB17, AB19,
AB20, AB22,
AB8, AC16,
AF11, AF14,
AF17, AF8,
AG10, AG13,
AG16, AG19,
AH11, AH14,
AH17, AH8,
AJ10, AJ13,
AJ16, AJ19,
B12, B15, B18,
B21, B9, C11,
C14, C17, C20,
C8, D10, D13,
D16, D19, D7,
E12, E15, E9,
F14, F8, G11,
G13, G15,
G17, H10,
H12, H14, H16,
H18, H20, H8,
J11, J13, J15,
J17, J21, J23,
J7, J9, K10,
K12, K14, K16,
K18, K20, K22,
K8, L13, L15,
L17, L19, L21,
L23, L7, L9,
M10, M14,
M16, M18,
M20, M8, N15,
N17, N19, N21,
N7, P10, P12,
P14, P16, P18,
P20, P8, R13,
R15, R17, R19,
R7, R9, T10,
T14, T16, T18,
T21, T8, U15,
U17, U19, U21,
U9, V10, V12,
V14, V18, V8,
W11, W13,
W16, W20,
W9, Y10, Y12,
Y15, Y17, Y19,
Y21, Y8
F26
wkup_gpio0_0
MCU_SPI1_CLK
MCU_SPI1_CLK
WKUP_GPIO0_0
MCU_BOOTMODE03
0
IO
IO
IO
I
OFF
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
LVCMOS
PU/PD
0
0
0
1/1
1
7
Bootstrap
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
F25
F28
wkup_gpio0_1
MCU_SPI1_D0
0
IO
IO
IO
I
OFF
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
LVCMOS
PU/PD
0
0
0
1/1
MCU_SPI1_D0
1
WKUP_GPIO0_1
7
MCU_BOOTMODE04
MCU_SPI1_D1
Bootstrap
wkup_gpio0_2
0
IO
IO
IO
I
OFF
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
LVCMOS
PU/PD
0
0
0
1/1
MCU_SPI1_D1
1
WKUP_GPIO0_2
7
MCU_BOOTMODE05
MCU_SPI1_CS0
Bootstrap
F27
G25
wkup_gpio0_3
wkup_gpio0_4
0
1
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
4
7
IO
IO
IO
O
O
IO
I
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
LVCMOS
LVCMOS
PU/PD
PU/PD
1
1
0
0/1
0/1
MCU_SPI1_CS0
WKUP_GPIO0_3
MCU_MCAN1_TX
MCU_MCAN1_TX
MCU_SPI0_CS3
1.8 V/3.3 V VDDSHV0_MC Yes
U
1
MCU_ADC_EXT_TRIGGER0
WKUP_GPIO0_4
pad
0
IO
I
G24
F29
G28
G27
wkup_gpio0_5
wkup_gpio0_6
wkup_gpio0_7
wkup_gpio0_8
MCU_MCAN1_RX
MCU_MCAN1_RX
MCU_SPI1_CS3
OFF
OFF
OFF
OFF
7
7
7
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
1
0/1
0/1
0/1
0/1
I
1
IO
I
1
MCU_ADC_EXT_TRIGGER1
WKUP_GPIO0_5
pad
0
IO
I
WKUP_UART0_CTSn
WKUP_UART0_CTSn
MCU_CPTS0_HW1TSPUSH
MCU_I2C1_SCL
1.8 V/3.3 V VDDSHV0_MC Yes
U
1
I
1
I
0
IOD
IO
O
1
WKUP_GPIO0_6
0
WKUP_UART0_RTSn
WKUP_UART0_RTSn
MCU_CPTS0_HW2TSPUSH
MCU_I2C1_SDA
1.8 V/3.3 V VDDSHV0_MC Yes
U
O
I
0
1
0
1
1
IOD
IO
IOD
IOD
O
WKUP_GPIO0_7
MCU_I2C1_SCL
1.8 V/3.3 V VDDSHV0_MC Yes
U
MCU_I2C1_SCL
MCU_CPTS0_TS_SYNC
MCU_I3C1_SCL
IO
IO
IO
1
0
0
MCU_TIMER_IO6
WKUP_GPIO0_8
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
G26
wkup_gpio0_9
MCU_I2C1_SDA
0
IOD
OFF
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
LVCMOS
PU/PD
1
1
0/1
MCU_I2C1_SDA
1
IOD
O
IO
IO
IO
I
MCU_CPTS0_TS_COMP
MCU_I3C1_SDA
2
3
1
0
0
0
0
MCU_TIMER_IO7
4
WKUP_GPIO0_9
7
H26
wkup_gpio0_10
MCU_EXT_REFCLK0
MCU_EXT_REFCLK0
MCU_UART0_TXD
MCU_ADC_EXT_TRIGGER0
MCU_CPTS0_RFT_CLK
MCU_SYSCLKOUT0
WKUP_GPIO0_10
MCU_OBSCLK0
0
OFF
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
LVCMOS
PU/PD
0/1
1
I
2
O
I
3
0
0
4
I
5
O
IO
O
O
I
7
0
H27
wkup_gpio0_11
0
OFF
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
LVCMOS
PU/PD
0/1
MCU_OBSCLK0
1
MCU_UART0_RXD
MCU_ADC_EXT_TRIGGER1
MCU_TIMER_IO1
2
1
0
0
3
I
4
IO
O
OZ
IO
O
O
IO
I
MCU_I3C1_SDAPULLEN
MCU_CLKOUT0
5
6
WKUP_GPIO0_11
MCU_UART0_TXD
MCU_SPI0_CS1
7
0
G29
H28
H29
J27
wkup_gpio0_12
wkup_gpio0_13
wkup_gpio0_14
wkup_gpio0_15
0
OFF
OFF
OFF
OFF
7
7
7
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
1/1
1/1
1/1
1/1
1
WKUP_GPIO0_12
MCU_BOOTMODE08
MCU_UART0_RXD
MCU_SPI1_CS1
7
0
1
0
1
0
Bootstrap
0
I
1.8 V/3.3 V VDDSHV0_MC Yes
U
1
O
IO
I
WKUP_GPIO0_13
MCU_BOOTMODE09
MCU_UART0_CTSn
MCU_SPI0_CS2
7
Bootstrap
0
I
1.8 V/3.3 V VDDSHV0_MC Yes
U
1
O
IO
I
WKUP_GPIO0_14
MCU_BOOTMODE06
MCU_UART0_RTSn
MCU_SPI1_CS2
7
Bootstrap
0
O
O
IO
I
1.8 V/3.3 V VDDSHV0_MC Yes
U
1
WKUP_GPIO0_15
MCU_BOOTMODE07
7
0
Bootstrap
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Table 6-1. Pin Attributes (continued)
BALL
RESET
REL.
BALL
RESET
STATE 6
I/O
VOLTAGE
VALUE 8
PULL UP/
DOWN
TYPE 12
RXACTIVE/
TXDISABL
E 14
BALL
NO. 1
MUXMODE
BUFFER
TYPE 11
BALL NAME 2
SIGNAL NAME 3
TYPE 5
POWER 9
HYS 10
DSIS 13
4
MUXMODE
J25
wkup_i2c0_scl
WKUP_I2C0_SCL
WKUP_GPIO0_62
WKUP_I2C0_SDA
WKUP_GPIO0_63
WKUP_LFOSC0_XI
WKUP_LFOSC0_XO
WKUP_OSC0_XI
0
IOD
OFF
0
1.8 V/3.3 V VDDSHV0_MC Yes
U
I2C OD FS
I2C OD FS
1
0
1
0
1/0
1/0
7
0
7
IO
IOD
IO
I
H24
wkup_i2c0_sda
OFF
0
1.8 V/3.3 V VDDSHV0_MC Yes
U
N28
N26
M29
M27
J29
wkup_lfosc0_xi
wkup_lfosc0_xo
wkup_osc0_xi
wkup_osc0_xo
wkup_uart0_rxd
OFF
OFF
OFF
OFF
OFF
1.8 V
1.8 V
1.8 V
1.8 V
VDDA_WKUP
VDDA_WKUP
VDDA_WKUP
VDDA_WKUP
LFOSC
LFOSC
HFOSC
HFOSC
LVCMOS
O
I
WKUP_OSC0_XO
WKUP_UART0_RXD
WKUP_GPIO0_56
WKUP_UART0_TXD
WKUP_GPIO0_57
O
I
0
7
0
7
7
7
1.8 V/3.3 V VDDSHV0_MC Yes
U
PU/PD
PU/PD
1
0
0/1
0/1
IO
O
IO
J28
wkup_uart0_txd
OFF
1.8 V/3.3 V VDDSHV0_MC Yes
U
LVCMOS
0
The following list describes the table column headers:
1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).
Note
Table 6-1, Pin Attributes, does not take into account the subsystem multiplexing signals. Subsystem multiplexing signals are described in
Section 6.3, Signal Descriptions.
4. MUXMODE: Multiplexing mode number:
a. MUXMODE 0 is the primary muxmode. The primary muxmode is not necessarily the default muxmode.
Note
The default muxmode is the mode at the release of the reset; also see the BALL RESET REL. MUXMODE column.
b. MUXMODE 1 through 7 are possible muxmodes for alternate functions. On each pin, some muxmodes are effectively used for alternate
functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used.
c. MCU_BOOTMODE pins are latched on the rising edge of MCU_PORz_OUT. BOOTMODE pins are latched on the rising edge of PORz_OUT.
d. An empty box means Not Applicable.
5. TYPE: Signal type and direction:
•
•
•
•
I = Input
O = Output
IO = Input or Output
IOD = Open drain terminal - Input or Output
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•
•
•
•
•
•
IOZ = Input, Output or Three-state terminal
OZ = Output or Three-state terminal
A = Analog
PWR = Power
GND = Ground
CAP = LDO Capacitor.
6. BALL RESET STATE: The state of the terminal at power-on reset:
•
•
•
•
•
•
DRIVE 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
DRIVE 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
OFF: High-impedance
PD: High-impedance with an active pulldown resistor
PU: High-impedance with an active pullup resistor
An empty box means Not Applicable.
7. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the rstoutn signal.
An empty box means Not Applicable.
8. I/O VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply).
An empty box means Not Applicable.
9. POWER: The voltage supply that powers the terminal IO buffers.
An empty box means Not Applicable.
10. HYS: Indicates if the input buffer has hysteresis:
•
•
Yes: With hysteresis
No: Without hysteresis
An empty box means No.
For more information, see the hysteresis values in, Electrical Characteristics.
11. BUFFER TYPE: This column describes the associated output buffer type
An empty box means Not Applicable.
For drive strength of the associated output buffer, refer to, Electrical Characteristics.
12. PULL UP/DOWN TYPE: Indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled
via software.
•
•
•
•
PU: Internal pullup
PD: Internal pulldown
PU/PD: Internal pullup and pulldown
An empty box means No pull.
13. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0", logic "1", or "PIN" level) when the peripheral pin
function is not selected by any of the PINCNTLx registers.
•
•
•
0: Logic 0 driven on the input signal port of the peripheral.
1: Logic 1 driven on the input signal port of the peripheral.
An empty box means Not Applicable.
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14. RXACTIVE / TXDISABLE: This column indicates the default value of the RXACTIVE / TXDISABLE bits in the PADCONFIG register.
•
•
•
RXACTIVE: 0 = receiver disabled, 1 = receiver enabled.
TXDISABLE: 0 = driver enabled, 1 = driver disabled.
An empty box means Not Applicable.
Note
Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the
proper software configuration (HiZ mode is not an input signal).
Note
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be
avoided.
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6.3 Signal Descriptions
Many signals are available on multiple pins, according to the software configuration of the pin multiplexing
options.
The following list describes the column headers:
1. SIGNAL NAME: The name of the signal passing through the pin.
Note
In Pin Attributes and Pin Multiplexing are not described the subsystem multiplexing signals.
2. DESCRIPTION: Description of the signal
3. PIN TYPE: Signal direction and type:
•
•
•
•
•
•
•
•
•
•
I = Input
O = Output
IO = Input or Output
IOD = Open drain terminal - Input or Output
IOZ = Input, Output or Three-state terminal
OZ = Output or Three-state terminal
A = Analog
PWR = Power
GND = Ground
CAP = LDO Capacitor
4. BALL: Associated balls bottom
For more information on the I/O cell configurations, see Pad Configuration Registers section of Device
Configuration chapter in the MAIN.
6.3.1 ADC
Note
The ADC can be configured to be used as a GPI. For more information, see Analog-to-Digital
Converter (ADC) section in Peripherals chapter in the device TRM.
6.3.1.1 MCU Domain
Table 6-2. ADC Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_ADC_EXT_TRIGGER0
MCU_ADC_EXT_TRIGGER1
ADC Trigger Input
ADC Trigger Input
I
I
A28, G25, H26
A27, G24, H27
Table 6-3. ADC0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_ADC0_AIN0
MCU_ADC0_AIN1
MCU_ADC0_AIN2
MCU_ADC0_AIN3
MCU_ADC0_AIN4
MCU_ADC0_AIN5
MCU_ADC0_AIN6
MCU_ADC0_AIN7
ADC Analog Input 0
ADC Analog Input 1
ADC Analog Input 2
ADC Analog Input 3
ADC Analog Input 4
ADC Analog Input 5
ADC Analog Input 6
ADC Analog Input 7
A
A
A
A
A
A
A
A
K25
K26
K28
L28
K24
K27
K29
L29
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Table 6-4. ADC1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
MCU_ADC1_AIN0
DESCRIPTION [2]
BALL [4]
[3]
ADC Analog Input 0
ADC Analog Input 1
ADC Analog Input 2
ADC Analog Input 3
ADC Analog Input 4
ADC Analog Input 5
ADC Analog Input 6
ADC Analog Input 7
A
A
A
A
A
A
A
A
N23
M25
L24
L26
N24
M24
L25
L27
MCU_ADC1_AIN1
MCU_ADC1_AIN2
MCU_ADC1_AIN3
MCU_ADC1_AIN4
MCU_ADC1_AIN5
MCU_ADC1_AIN6
MCU_ADC1_AIN7
6.3.2 DDRSS
6.3.2.1 MAIN Domain
Table 6-5. DDRSS Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
DDR_RET
External IO Retention Enable
I
P6
Table 6-6. DDRSS0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
DDR0_CKN
DDR0_CKP
DDRSS Differential Clock (negative)
DDRSS Differential Clock (positive)
DDRSS Reset
IO
IO
IO
IO
IO
IO
IO
IO
IO
A
J1
H1
K6
G4
H3
K5
J4
DDR0_RESETn
DDR0_CA0
DDR0_CA1
DDR0_CA2
DDR0_CA3
DDR0_CA4
DDR0_CA5
DDR0_CAL0(1)
DDR0_CKE0
DDR0_CKE1
DDR0_CSn0_0
DDR0_CSn0_1
DDR0_CSn1_0
DDR0_CSn1_1
DDR0_DM0
DDR0_DM1
DDR0_DM2
DDR0_DM3
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDRSS Command Address
DDRSS Command Address
DDRSS Command Address
DDRSS Command Address
DDRSS Command Address
DDRSS Command Address
IO Pad Calibration Resistor
DDRSS Clock Enable
DDRSS Clock Enable
DDRSS Chip Select
DDRSS Chip Select
DDRSS Chip Select
DDRSS Chip Select
DDRSS Data Mask
K2
H5
H2
G3
J3
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
J5
K3
G5
J2
A3
E4
N1
R5
A5
A6
B5
C2
B4
C3
A2
DDRSS Data Mask
DDRSS Data Mask
DDRSS Data Mask
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
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Table 6-6. DDRSS0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ16
DDR0_DQ17
DDR0_DQ18
DDR0_DQ19
DDR0_DQ20
DDR0_DQ21
DDR0_DQ22
DDR0_DQ23
DDR0_DQ24
DDR0_DQ25
DDR0_DQ26
DDR0_DQ27
DDR0_DQ28
DDR0_DQ29
DDR0_DQ30
DDR0_DQ31
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
A4
D1
C4
F1
G2
F2
F3
D3
F5
L5
M5
N5
L4
L2
L1
N2
N4
T3
T2
P2
P3
P5
R4
T4
T5
B1
B2
E2
E3
M2
M3
R1
R2
DDR0_DQS0N
DDR0_DQS0P
DDR0_DQS1N
DDR0_DQS1P
DDR0_DQS2N
DDR0_DQS2P
DDR0_DQS3N
DDR0_DQS3P
DDRSS Complimentary Data Strobe
DDRSS Data Strobe
DDRSS Complimentary Data Strobe
DDRSS Data Strobe
DDRSS Complimentary Data Strobe
DDRSS Data Strobe
DDRSS Complimentary Data Strobe
DDRSS Data Strobe
(1) An external 240 Ω ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
6.3.3 GPIO
6.3.3.1 MAIN Domain
Table 6-7. GPIO0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
General Purpose Input/Output
BALL [4]
[3]
IO
IO
IO
IO
IO
GPIO0_0
GPIO0_1
GPIO0_2
GPIO0_3
GPIO0_4
AC18
AC23
AG22
AF22
AJ23
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
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Table 6-7. GPIO0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
General Purpose Input/Output
BALL [4]
[3]
GPIO0_5
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AH23
AD20
AD22
AE20
AJ20
AG20
AD21
AF24
AJ24
AG24
AD24
AC24
AE24
AJ21
AE21
W28
V25
GPIO0_6
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
GPIO0_7
GPIO0_8
GPIO0_9
GPIO0_10
GPIO0_11
GPIO0_12
GPIO0_13
GPIO0_14
GPIO0_15
GPIO0_16
GPIO0_17
GPIO0_18
GPIO0_19
GPIO0_100
GPIO0_101
GPIO0_102
GPIO0_103
GPIO0_104
GPIO0_105
GPIO0_106
GPIO0_107
GPIO0_108
GPIO0_109
GPIO0_110
GPIO0_111
GPIO0_112
GPIO0_113
GPIO0_114
GPIO0_115
GPIO0_116
GPIO0_117
GPIO0_118
GPIO0_119
GPIO0_120
GPIO0_121
GPIO0_122
GPIO0_123
GPIO0_124
GPIO0_125
GPIO0_126
GPIO0_127
GPIO0_20
GPIO0_21
W27
W29
W26
Y29
Y27
W24
W25
V26
V24
AA2
Y4
AA1
AB5
AA3
Y3
W4
Y1
Y5
Y2
AB2
AB3
AC2
AB1
AA4
AB4
AC4
AH21
AE22
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Table 6-7. GPIO0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
General Purpose Input/Output
BALL [4]
[3]
GPIO0_22
GPIO0_23
GPIO0_24
GPIO0_25
GPIO0_26
GPIO0_27
GPIO0_28
GPIO0_29
GPIO0_30
GPIO0_31
GPIO0_32
GPIO0_33
GPIO0_34
GPIO0_35
GPIO0_36
GPIO0_37
GPIO0_38
GPIO0_39
GPIO0_40
GPIO0_41
GPIO0_42
GPIO0_43
GPIO0_44
GPIO0_45
GPIO0_46
GPIO0_47
GPIO0_48
GPIO0_49
GPIO0_50
GPIO0_51
GPIO0_52
GPIO0_53
GPIO0_54
GPIO0_55
GPIO0_56
GPIO0_57
GPIO0_58
GPIO0_59
GPIO0_60
GPIO0_61
GPIO0_62
GPIO0_63
GPIO0_64
GPIO0_65
GPIO0_66
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AG23
AF23
AD23
AH24
AG21
AE23
AC21
Y23
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
AF21
AB23
AJ25
AH25
AG25
AH26
AJ27
AJ26
AC22
AJ22
AH22
AD19
AD18
AF28
AE28
AE27
AD26
AD25
AC29
AE26
AC28
AC27
AB26
AB25
AJ28
AH27
AH29
AG28
AG27
AH28
AB24
AB29
AB28
AE29
AD28
AD27
AC25
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Table 6-7. GPIO0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
General Purpose Input/Output
BALL [4]
[3]
GPIO0_67
GPIO0_68
GPIO0_69
GPIO0_70
GPIO0_71
GPIO0_72
GPIO0_73
GPIO0_74
GPIO0_75
GPIO0_76
GPIO0_77
GPIO0_78
GPIO0_79
GPIO0_80
GPIO0_81
GPIO0_82
GPIO0_83
GPIO0_84
GPIO0_85
GPIO0_86
GPIO0_87
GPIO0_88
GPIO0_89
GPIO0_90
GPIO0_91
GPIO0_92
GPIO0_93
GPIO0_94
GPIO0_95
GPIO0_96
GPIO0_97
GPIO0_98
GPIO0_99
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AD29
AB27
AC26
AA24
AA28
Y24
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
AA25
AG26
AF27
AF26
AE25
AF29
AG29
Y25
AA26
AA29
Y26
AA27
U23
U26
V28
V29
V27
U28
U29
U25
U27
U24
R23
T23
Y28
V23
W23
Table 6-8. GPIO1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
GPIO1_0
GPIO1_1
GPIO1_2
GPIO1_3
GPIO1_4
GPIO1_5
GPIO1_6
GPIO1_7
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
AD5
W5
W6
W3
V4
W2
W1
AC5
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Table 6-8. GPIO1 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
General Purpose Input/Output
BALL [4]
[3]
GPIO1_8
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AA5
Y6
GPIO1_9
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
GPIO1_10
GPIO1_11
GPIO1_12
GPIO1_13
GPIO1_14
GPIO1_15
GPIO1_16
GPIO1_17
GPIO1_18
GPIO1_19
GPIO1_20
GPIO1_21
GPIO1_22
GPIO1_23
GPIO1_24
GPIO1_25
GPIO1_26
GPIO1_27
GPIO1_28
GPIO1_29
GPIO1_30
GPIO1_31
GPIO1_32
GPIO1_33
GPIO1_34
GPIO1_35
AA6
U2
U3
V6
V5
R26
R25
P24
R24
P25
R29
P23
R28
T28
T29
T27
T24
T26
T25
U6
AD1
AC1
AC3
AD3
AD2
AE2
6.3.3.2 WKUP Domain
Table 6-9. GPIO0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
WKUP_GPIO0_0
WKUP_GPIO0_1
WKUP_GPIO0_2
WKUP_GPIO0_3
WKUP_GPIO0_4
WKUP_GPIO0_5
WKUP_GPIO0_6
WKUP_GPIO0_7
WKUP_GPIO0_8
WKUP_GPIO0_9
WKUP_GPIO0_10
WKUP_GPIO0_11
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
F26
F25
F28
F27
G25
G24
F29
G28
G27
G26
H26
H27
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Table 6-9. GPIO0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
WKUP_GPIO0_12
DESCRIPTION [2]
General Purpose Input/Output
BALL [4]
[3]
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
G29
H28
H29
J27
WKUP_GPIO0_13
WKUP_GPIO0_14
WKUP_GPIO0_15
WKUP_GPIO0_16
WKUP_GPIO0_17
WKUP_GPIO0_18
WKUP_GPIO0_19
WKUP_GPIO0_20
WKUP_GPIO0_21
WKUP_GPIO0_22
WKUP_GPIO0_23
WKUP_GPIO0_24
WKUP_GPIO0_25
WKUP_GPIO0_26
WKUP_GPIO0_27
WKUP_GPIO0_28
WKUP_GPIO0_29
WKUP_GPIO0_30
WKUP_GPIO0_31
WKUP_GPIO0_32
WKUP_GPIO0_33
WKUP_GPIO0_34
WKUP_GPIO0_35
WKUP_GPIO0_36
WKUP_GPIO0_37
WKUP_GPIO0_38
WKUP_GPIO0_39
WKUP_GPIO0_40
WKUP_GPIO0_41
WKUP_GPIO0_42
WKUP_GPIO0_43
WKUP_GPIO0_44
WKUP_GPIO0_45
WKUP_GPIO0_46
WKUP_GPIO0_47
WKUP_GPIO0_48
WKUP_GPIO0_49
WKUP_GPIO0_50
WKUP_GPIO0_51
WKUP_GPIO0_52
WKUP_GPIO0_53
WKUP_GPIO0_54
WKUP_GPIO0_55
WKUP_GPIO0_56
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
E20
C21
D21
D20
G19
G20
F20
F21
E21
B22
G21
F19
E19
F22
A23
B23
D22
G22
D23
C23
C22
E22
B27
C25
A28
A27
A26
B25
B26
C24
A25
D24
A24
B24
E23
F23
E27
E24
E28
E25
J29
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Table 6-9. GPIO0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
General Purpose Input/Output
BALL [4]
[3]
WKUP_GPIO0_57
WKUP_GPIO0_58
WKUP_GPIO0_59
WKUP_GPIO0_60
WKUP_GPIO0_61
WKUP_GPIO0_62
WKUP_GPIO0_63
WKUP_GPIO0_64
WKUP_GPIO0_65
WKUP_GPIO0_66
WKUP_GPIO0_67
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
J28
D29
C29
D26
D25
J25
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
H24
J26
H25
E26
G23
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6.3.4 I2C
6.3.4.1 MAIN Domain
Table 6-10. I2C0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
I2C0_SCL
I2C0_SDA
I2C Clock
I2C Data
IOD
IOD
AC5
AA5
Table 6-11. I2C1 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
I2C1_SCL
I2C1_SDA
I2C Clock
I2C Data
IOD
IOD
Y6
AA6
Table 6-12. I2C2 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
I2C2_SCL
I2C2_SDA
I2C Clock
I2C Data
IOD
IOD
AA1, U23, W5
AB5, U26, W6
Table 6-13. I2C3 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
I2C3_SCL
I2C3_SDA
I2C Clock
I2C Data
IOD
IOD
T26, V27, Y4
T25, U28, W4
Table 6-14. I2C4 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
I2C4_SCL
I2C4_SDA
I2C Clock
I2C Data
IOD
IOD
AD19, P25, Y5
AD18, R29, Y1
Table 6-15. I2C5 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
I2C5_SCL
I2C5_SDA
I2C Clock
I2C Data
IOD
IOD
T28, Y26
AA27, T29
Table 6-16. I2C6 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
I2C6_SCL
I2C6_SDA
I2C Clock
I2C Data
IOD
IOD
AA3, U29, W2
U25, W1, Y2
6.3.4.2 MCU Domain
Table 6-17. I2C0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_I2C0_SCL
MCU_I2C0_SDA
I2C Clock
I2C Data
IOD
IOD
J26
H25
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Table 6-18. I2C1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_I2C1_SCL
MCU_I2C1_SDA
I2C Clock
I2C Data
IOD
IOD
F29, G27
G26, G28
6.3.4.3 WKUP Domain
Table 6-19. I2C0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
WKUP_I2C0_SCL
WKUP_I2C0_SDA
I2C Clock
I2C Data
IOD
IOD
J25
H24
6.3.5 I3C
6.3.5.1 MAIN Domain
Table 6-20. I3C0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
I3C0_SCL
I3C Clock
IO
IO
O
W2
W1
I3C0_SDA
I3C Data
I3C0_SDAPULLEN
MAIN domain I3C Data Pull Enable
AB4, U2
6.3.5.2 MCU Domain
Table 6-21. I3C0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_I3C0_SCL
I3C Clock
IO
IO
O
D26
D25
E26
MCU_I3C0_SDA
I3C Data
MCU_I3C0_SDAPULLEN
MCU domain I3C Data Pull Enable
Table 6-22. I3C1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_I3C1_SCL
I3C Clock
IO
IO
O
G27
G26
MCU_I3C1_SDA
I3C Data
MCU_I3C1_SDAPULLEN
MCU domain I3C Data Pull Enable
G23, H27
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6.3.6 MCAN
6.3.6.1 MAIN Domain
Table 6-23. MCAN0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
SIGNAL NAME 1
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME 1
SIGNAL NAME 1
SIGNAL NAME [1]
SIGNAL NAME 1
DESCRIPTION [2]
MCAN Receive Data
BALL [4]
[3]
MCAN0_RX
MCAN0_TX
I
W5
W6
MCAN Transmit Data
O
Table 6-24. MCAN1 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN1_RX
MCAN1_TX
MCAN Receive Data
MCAN Transmit Data
I
W3
V4
O
Table 6-25. MCAN2 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN2_RX
MCAN2_TX
MCAN Receive Data
MCAN Transmit Data
I
AC2, W2
AB1, W1
O
Table 6-26. MCAN3 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN3_RX
MCAN3_TX
MCAN Receive Data
MCAN Transmit Data
I
AC4
AD5
O
Table 6-27. MCAN4 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN4_RX
MCAN4_TX
MCAN Receive Data
MCAN Transmit Data
I
AJ20, AJ24
AE20, AF24
O
Table 6-28. MCAN5 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN5_RX
MCAN5_TX
MCAN Receive Data
MCAN Transmit Data
I
AD24, AE21
AG24, AJ21
O
Table 6-29. MCAN6 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN6_RX
MCAN6_TX
MCAN Receive Data
MCAN Transmit Data
I
AE24, AG21
AC24, AH21
O
Table 6-30. MCAN7 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN7_RX
MCAN7_TX
MCAN Receive Data
MCAN Transmit Data
I
AG25, Y23
O
AC21, AH25
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Table 6-31. MCAN8 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
DESCRIPTION [2]
MCAN Receive Data
BALL [4]
[3]
MCAN8_RX
MCAN8_TX
I
AB23, AJ27
AF21, AH26
MCAN Transmit Data
O
Table 6-32. MCAN9 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN9_RX
MCAN9_TX
MCAN Receive Data
MCAN Transmit Data
I
AC27
AC28
O
Table 6-33. MCAN10 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN10_RX
MCAN10_TX
MCAN Receive Data
MCAN Transmit Data
I
AB25
AB26
O
Table 6-34. MCAN11 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN11_RX
MCAN11_TX
MCAN Receive Data
MCAN Transmit Data
I
AA28
AA24
O
Table 6-35. MCAN12 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN12_RX
MCAN12_TX
MCAN Receive Data
MCAN Transmit Data
I
AA29
AA26
O
Table 6-36. MCAN13 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
MCAN13_RX
MCAN13_TX
MCAN Receive Data
MCAN Transmit Data
I
AA27
Y26
O
6.3.6.2 MCU Domain
Table 6-37. MCAN0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_MCAN0_RX
MCU_MCAN0_TX
MCAN Receive Data
MCAN Transmit Data
I
C29
D29
O
Table 6-38. MCAN1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_MCAN1_RX
MCU_MCAN1_TX
MCAN Receive Data
MCAN Transmit Data
I
G24
G25
O
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6.3.7 MCSPI
6.3.7.1 MAIN Domain
Table 6-39. MCSPI0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
SPI0_CLK
SPI0_CS0
SPI0_CS1
SPI0_CS2
SPI0_CS3
SPI0_D0
SPI Clock
IO
IO
IO
IO
IO
IO
IO
AA1
AA2
Y4
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
AC2
AB1
AB5
AA3
SPI0_D1
SPI Data 1
Table 6-40. MCSPI1 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
SPI1_CLK
SPI1_CS0
SPI1_CS1
SPI1_CS2
SPI1_CS3
SPI1_D0
SPI Clock
IO
IO
IO
IO
IO
IO
IO
Y1
Y3
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
W4
AD19
AD18
Y5
SPI1_D1
SPI Data 1
Y2
Table 6-41. MCSPI2 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
SPI2_CLK
SPI2_CS0
SPI2_CS1
SPI2_CS2
SPI2_CS3
SPI2_D0
SPI Clock
IO
IO
IO
IO
IO
IO
IO
AB1
AC2
AB2
AB3
U2
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
AC4
AD5
SPI2_D1
SPI Data 1
Table 6-42. MCSPI3 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
SPI3_CLK
SPI3_CS0
SPI3_CS1
SPI3_CS2
SPI3_CS3
SPI3_D0
SPI Clock
IO
IO
IO
IO
IO
IO
IO
Y25
AA24
AB26
AB25
Y24
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
AA26
AA29
SPI3_D1
SPI Data 1
Table 6-43. MCSPI5 Signal Descriptions
PIN TYPE
DESCRIPTION [2]
BALL [4]
[3]
SPI5_CLK
SPI Clock
IO
W29
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Table 6-43. MCSPI5 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
SPI5_CS0
SPI5_CS1
SPI5_CS2
SPI5_CS3
SPI5_D0
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
IO
IO
IO
IO
IO
IO
W27
W25
W28
W23
V25
SPI5_D1
SPI Data 1
W24
Table 6-44. MCSPI6 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
SPI6_CLK
SPI6_CS0
SPI6_CS1
SPI6_CS2
SPI6_CS3
SPI6_D0
SPI Clock
IO
IO
IO
IO
IO
IO
IO
AC22
AC21
AG20
AD21
AF21
AJ22
AH22
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
SPI6_D1
SPI Data 1
Table 6-45. MCSPI7 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
SPI7_CLK
SPI7_CS0
SPI7_CS1
SPI7_CS2
SPI7_CS3
SPI7_D0
SPI Clock
IO
IO
IO
IO
IO
IO
IO
U3
U2
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
AB3
AA4
AB4
V6
SPI7_D1
SPI Data 1
V5
6.3.7.2 MCU Domain
Table 6-46. MCSPI0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_SPI0_CLK
MCU_SPI0_CS0
MCU_SPI0_CS1
MCU_SPI0_CS2
MCU_SPI0_CS3
MCU_SPI0_D0
MCU_SPI0_D1
SPI Clock
IO
IO
IO
O
E27
E25
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
C23, G29
E22, H29
G25
IO
IO
IO
E24
SPI Data 1
E28
Table 6-47. MCSPI1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_SPI1_CLK
MCU_SPI1_CS0
MCU_SPI1_CS1
SPI Clock
IO
IO
O
F26
F27
SPI Chip Select 0
SPI Chip Select 1
G22, H28
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Table 6-47. MCSPI1 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
MCU_SPI1_CS2
DESCRIPTION [2]
BALL [4]
[3]
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
O
D23, J27
G24
MCU_SPI1_CS3
MCU_SPI1_D0
MCU_SPI1_D1
IO
IO
IO
F25
SPI Data 1
F28
6.3.8 UART
6.3.8.1 MAIN Domain
Table 6-48. UART0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART0_CTSn
UART0_DCDn
UART0_DSRn
UART0_DTRn
UART0_RIn
UART Clear to Send (active low)
UART Data Carrier Detect (active low)
UART Data Set Ready (active low)
UART Data Terminal Ready (active low)
UART Ring Indicator
I
I
AC2, Y3
P23
I
R28
O
I
T27
T24
UART0_RTSn
UART0_RXD
UART0_TXD
UART Request to Send (active low)
UART Receive Data
O
I
AA2, AB1
AB2, AC23
AB3, AG22
UART Transmit Data
O
Table 6-49. UART1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART1_CTSn
UART1_RTSn
UART1_RXD
UART1_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
AA1, AC4
AB5, AD5
AA4, AF22
AB4, AJ23
O
I
UART Transmit Data
O
Table 6-50. UART2 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART2_CTSn
UART2_RTSn
UART2_RXD
UART2_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
AE25
O
I
AF29
AA26, AH23, Y1
AA24, AD22, Y5
UART Transmit Data
O
Table 6-51. UART3 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART3_CTSn
UART3_RTSn
UART3_RXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
O
I
AD19, U27
AD18, U24
AE27, T26, V28, Y23
AC21, AD26, T25,
V29
UART3_TXD
UART Transmit Data
O
Table 6-52. UART4 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
UART4_CTSn
DESCRIPTION [2]
BALL [4]
[3]
UART Clear to Send (active low)
I
AE29, Y29
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Table 6-52. UART4 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART4_RTSn
UART4_RXD
UART4_TXD
UART Request to Send (active low)
UART Receive Data
O
I
AD28, Y27
AG28, P24, W23
AG27, R24, W28
UART Transmit Data
O
Table 6-53. UART5 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART5_CTSn
UART5_RTSn
UART5_RXD
UART5_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
Y1
O
I
Y5
AE29, Y29, Y3
AD28, W4, Y27
UART Transmit Data
O
Table 6-54. UART6 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART6_CTSn
UART6_RTSn
UART6_RXD
UART6_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
R23, W3
T23, V4
O
I
AC27, T27, U27, W2
AB26, T24, U24, W1
UART Transmit Data
O
Table 6-55. UART7 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART7_CTSn
UART7_RTSn
UART7_RXD
UART7_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
P24
R24
R26
R25
O
I
UART Transmit Data
O
Table 6-56. UART8 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART8_CTSn
UART8_RTSn
UART8_RXD
UART8_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
AF27, P23
AF26, R28
P25, Y24
O
I
UART Transmit Data
O
AA25, R29
Table 6-57. UART9 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UART9_CTSn
UART9_RTSn
UART9_RXD
UART9_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
T27, W2
T24, W1
T28, W3
T29, V4
O
I
UART Transmit Data
O
6.3.8.2 MCU Domain
Table 6-58. UART0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_UART0_CTSn
UART Clear to Send (active low)
I
C23, D26, H29
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Table 6-58. UART0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
MCU_UART0_RTSn
DESCRIPTION [2]
BALL [4]
[3]
UART Request to Send (active low)
UART Receive Data
O
I
D25, E22, J27
G22, H27, H28
D23, G29, H26
MCU_UART0_RXD
MCU_UART0_TXD
UART Transmit Data
O
6.3.8.3 WKUP Domain
Table 6-59. UART0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
WKUP_UART0_CTSn
WKUP_UART0_RTSn
WKUP_UART0_RXD
WKUP_UART0_TXD
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
I
F29
G28
J29
J28
O
I
UART Transmit Data
O
6.3.9 MDIO
6.3.9.1 MCU Domain
Table 6-60. MDIO0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_MDIO0_MDC
MCU_MDIO0_MDIO
MDIO Clock
MDIO Data
O
F23
E23
IO
6.3.10 CPSW2G
Note
The subsystem (SS) applies to both CPSW2G and the CPTS. For more details about CPTS signal
characteristics, see the Section 6.3.21, CPTS signal descriptions.
6.3.10.1 MCU Domain
Table 6-61. CPSW2G0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
MCU_RGMII1_RXC
DESCRIPTION [2]
RGMII Receive Clock
BALL [4]
[3]
I
C24
C25
B26
B27
B24
A24
D24
A25
B25
A26
A27
A28
B27
C24
C25
MCU_RGMII1_RX_CTL
MCU_RGMII1_TXC
MCU_RGMII1_TX_CTL
MCU_RGMII1_RD0
MCU_RGMII1_RD1
MCU_RGMII1_RD2
MCU_RGMII1_RD3
MCU_RGMII1_TD0
MCU_RGMII1_TD1
MCU_RGMII1_TD2
MCU_RGMII1_TD3
MCU_RMII1_CRS_DV
MCU_RMII1_REF_CLK
MCU_RMII1_RX_ER
RGMII Receive Control
RGMII Transmit Clock
RGMII Transmit Control
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
RMII Carrier Sense / Data Valid
RMII Reference Clock
RMII Receive Data Error
I
O
O
I
I
I
I
O
O
O
O
I
I
I
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Table 6-61. CPSW2G0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
RMII Transmit Enable
BALL [4]
[3]
MCU_RMII1_TX_EN
MCU_RMII1_RXD0
MCU_RMII1_RXD1
MCU_RMII1_TXD0
MCU_RMII1_TXD1
O
I
B26
B24
A24
B25
A26
RMII Receive Data 0
RMII Receive Data 1
RMII Transmit Data 0
RMII Transmit Data 1
I
O
O
6.3.11 CPSW9G
6.3.11.1 MAIN Domain
Table 6-62. CPSW9G0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
RMII Clock Output (50 MHz). This pin is used for clock
source to the external PHY and must be routed back to
the RMII_REF_CLK pin for proper device operation.
CLKOUT
OZ
AA25, AJ28, Y29
MDIO0_MDC
MDIO Clock
O
IO
I
V24
V26
MDIO0_MDIO
RGMII1_RXC
MDIO Data
RGMII Receive Clock
RGMII Receive Control
RGMII Transmit Clock
RGMII Transmit Control
RGMII Receive Clock
RGMII Receive Control
RGMII Transmit Clock
RGMII Transmit Control
RGMII Receive Clock
RGMII Receive Control
RGMII Transmit Clock
RGMII Transmit Control
RGMII Receive Clock
RGMII Receive Control
RGMII Transmit Clock
RGMII Transmit Control
RGMII Receive Clock
RGMII Receive Control
RGMII Transmit Clock
RGMII Transmit Control
RGMII Receive Clock
RGMII Receive Control
RGMII Transmit Clock
RGMII Transmit Control
RGMII Receive Clock
RGMII Receive Control
RGMII Transmit Clock
RGMII Transmit Control
RGMII Receive Clock
RGMII Receive Control
AD22
AH23
AE24
AC24
AE23
AH24
AJ26
AJ27
AE26
AD25
AH28
AG27
AC26
AD29
AG29
AF29
U25
RGMII1_RX_CTL
RGMII1_TXC
I
O
O
I
RGMII1_TX_CTL
RGMII2_RXC
RGMII2_RX_CTL
RGMII2_TXC
I
O
O
I
RGMII2_TX_CTL
RGMII3_RXC
RGMII3_RX_CTL
RGMII3_TXC
I
O
O
I
RGMII3_TX_CTL
RGMII4_RXC
RGMII4_RX_CTL
RGMII4_TXC
I
O
O
I
RGMII4_TX_CTL
RGMII5_RXC
RGMII5_RX_CTL
RGMII5_TXC
I
U26
O
O
I
U29
RGMII5_TX_CTL
RGMII6_RXC
U23
W26
RGMII6_RX_CTL
RGMII6_TXC
I
V23
O
O
I
W29
RGMII6_TX_CTL
RGMII7_RXC
Y28
AD22
AH23
AE24
AC24
AE23
AH24
RGMII7_RX_CTL
RGMII7_TXC
I
O
O
I
RGMII7_TX_CTL
RGMII8_RXC
RGMII8_RX_CTL
I
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Table 6-62. CPSW9G0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
RGMII8_TXC
DESCRIPTION [2]
RGMII Transmit Clock
BALL [4]
[3]
O
O
I
AJ26
AJ27
AC23
AG22
AF22
AJ23
AF24
AJ24
AG24
AD24
AE22
AG23
AF23
AD23
AJ25
AH25
AG25
AH26
AF28
AE28
AE27
AD26
AJ28
AH27
AH29
AG28
AE29
AD28
AD27
AC25
AG26
AF27
AF26
AE25
T23
RGMII8_TX_CTL
RGMII1_RD0
RGMII1_RD1
RGMII1_RD2
RGMII1_RD3
RGMII1_TD0
RGMII1_TD1
RGMII1_TD2
RGMII1_TD3
RGMII2_RD0
RGMII2_RD1
RGMII2_RD2
RGMII2_RD3
RGMII2_TD0
RGMII2_TD1
RGMII2_TD2
RGMII2_TD3
RGMII3_RD0
RGMII3_RD1
RGMII3_RD2
RGMII3_RD3
RGMII3_TD0
RGMII3_TD1
RGMII3_TD2
RGMII3_TD3
RGMII4_RD0
RGMII4_RD1
RGMII4_RD2
RGMII4_RD3
RGMII4_TD0
RGMII4_TD1
RGMII4_TD2
RGMII4_TD3
RGMII5_RD0
RGMII5_RD1
RGMII5_RD2
RGMII5_RD3
RGMII5_TD0
RGMII5_TD1
RGMII5_TD2
RGMII5_TD3
RGMII6_RD0
RGMII6_RD1
RGMII6_RD2
RGMII Transmit Control
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
I
I
R23
I
U24
I
U27
O
O
O
O
I
U28
V27
V29
V28
W25
I
W24
I
Y27
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Table 6-62. CPSW9G0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
RGMII Receive Data 3
BALL [4]
[3]
RGMII6_RD3
RGMII6_TD0
RGMII6_TD1
RGMII6_TD2
RGMII6_TD3
RGMII7_RD0
RGMII7_RD1
RGMII7_RD2
RGMII7_RD3
RGMII7_TD0
RGMII7_TD1
RGMII7_TD2
RGMII7_TD3
RGMII8_RD0
RGMII8_RD1
RGMII8_RD2
RGMII8_RD3
RGMII8_TD0
RGMII8_TD1
RGMII8_TD2
RGMII8_TD3
I
O
O
O
O
I
Y29
W27
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
RMII Carrier Sense / Data Valid
RMII Receive Data Error
RMII Transmit Enable
V25
W28
W23
AC23
AG22
AF22
AJ23
AF24
AJ24
AG24
AD24
AE22
AG23
AF23
AD23
AJ25
AH25
AG25
AH26
AF22
AJ23
AD20
AF23
AD23
AJ25
AE27
AD26
AE26
AD27
AC25
AG26
AD21
AE21
AG21
AB23
AC21
AC22
U23
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
I
RMII1_CRS_DV
RMII1_RX_ER
RMII1_TX_EN
RMII2_CRS_DV
RMII2_RX_ER
RMII2_TX_EN
RMII3_CRS_DV
RMII3_RX_ER
RMII3_TX_EN
RMII4_CRS_DV
RMII4_RX_ER
RMII4_TX_EN
RMII5_CRS_DV
RMII5_RX_ER
RMII5_TX_EN
RMII6_CRS_DV
RMII6_RX_ER
RMII6_TX_EN
RMII7_CRS_DV
RMII7_RX_ER
RMII7_TX_EN
RMII8_CRS_DV
RMII8_RX_ER
RMII8_TX_EN
I
O
I
RMII Carrier Sense / Data Valid
RMII Receive Data Error
RMII Transmit Enable
I
O
I
RMII Carrier Sense / Data Valid
RMII Receive Data Error
RMII Transmit Enable
I
O
I
RMII Carrier Sense / Data Valid
RMII Receive Data Error
RMII Transmit Enable
I
O
I
RMII Carrier Sense / Data Valid
RMII Receive Data Error
RMII Transmit Enable
I
O
I
RMII Carrier Sense / Data Valid
RMII Receive Data Error
RMII Transmit Enable
I
O
I
RMII Carrier Sense / Data Valid
RMII Receive Data Error
RMII Transmit Enable
I
U26
O
I
U29
RMII Carrier Sense / Data Valid
RMII Receive Data Error
RMII Transmit Enable
Y28
I
V23
O
W29
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Table 6-62. CPSW9G0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
RMII Receive Data 0
BALL [4]
[3]
RMII1_RXD0
RMII1_RXD1
RMII1_TXD0
RMII1_TXD1
RMII2_RXD0
RMII2_RXD1
RMII2_TXD0
RMII2_TXD1
RMII3_RXD0
RMII3_RXD1
RMII3_TXD0
RMII3_TXD1
RMII4_RXD0
RMII4_RXD1
RMII4_TXD0
RMII4_TXD1
RMII5_RXD0
RMII5_RXD1
RMII5_TXD0
RMII5_TXD1
RMII6_RXD0
RMII6_RXD1
RMII6_TXD0
RMII6_TXD1
RMII7_RXD0
RMII7_RXD1
RMII7_TXD0
RMII7_TXD1
RMII8_RXD0
RMII8_RXD1
RMII8_TXD0
RMII8_TXD1
I
I
AC23
AG22
AH23
AD22
AE22
AG23
AH24
AE23
AE28
AF28
AC29
AD25
AE29
AD28
AC26
AD29
AJ20
AG20
AH21
AJ21
Y23
RMII Receive Data 1
RMII Transmit Data 0
RMII Transmit Data 1
RMII Receive Data 0
RMII Receive Data 1
RMII Transmit Data 0
RMII Transmit Data 1
RMII Receive Data 0
RMII Receive Data 1
RMII Transmit Data 0
RMII Transmit Data 1
RMII Receive Data 0
RMII Receive Data 1
RMII Transmit Data 0
RMII Transmit Data 1
RMII Receive Data 0
RMII Receive Data 1
RMII Transmit Data 0
RMII Transmit Data 1
RMII Receive Data 0
RMII Receive Data 1
RMII Transmit Data 0
RMII Transmit Data 1
RMII Receive Data 0
RMII Receive Data 1
RMII Transmit Data 0
RMII Transmit Data 1
RMII Receive Data 0
RMII Receive Data 1
RMII Transmit Data 0
RMII Transmit Data 1
RMII Reference Clock
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
AF21
AJ22
AH22
T23
O
O
I
I
R23
O
O
I
U28
V27
W25
I
W24
O
O
I
W27
V25
RMII_REF_CLK
AD18
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6.3.12 ECAP
6.3.12.1 MAIN Domain
Table 6-63. ECAP0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
Enhanced Capture (ECAP) Input or Auxiliary PWM
(APWM) Ouput
ECAP0_IN_APWM_OUT
IO
P24, U2
Table 6-64. ECAP1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
Enhanced Capture (ECAP) Input or Auxiliary PWM
(APWM) Ouput
ECAP1_IN_APWM_OUT
IO
R24, V6
Table 6-65. ECAP2 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
Enhanced Capture (ECAP) Input or Auxiliary PWM
(APWM) Ouput
ECAP2_IN_APWM_OUT
IO
R28, V5
6.3.13 EQEP
6.3.13.1 MAIN Domain
Table 6-66. EQEP0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EQEP0_A
EQEP0_B
EQEP0_I
EQEP0_S
EQEP Quadrature Input A
EQEP Quadrature Input B
EQEP Index
I
AC2
AB1
AD5
AC4
I
IO
IO
EQEP Strobe
Table 6-67. EQEP1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EQEP1_A
EQEP1_B
EQEP1_I
EQEP1_S
EQEP Quadrature Input A
EQEP Quadrature Input B
EQEP Index
I
AD23
AH24
AJ25
AG21
I
IO
IO
EQEP Strobe
Table 6-68. EQEP2 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EQEP2_A
EQEP2_B
EQEP2_I
EQEP2_S
EQEP Quadrature Input A
EQEP Quadrature Input B
EQEP Index
I
T27
T24
P23
R28
I
IO
IO
EQEP Strobe
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6.3.14 EHRPWM
6.3.14.1 MAIN Domain
Table 6-69. EHRPWM Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
EHRPWM Start of Conversion A
BALL [4]
[3]
EHRPWM_SOCA
EHRPWM_SOCB
O
O
U25
R23
EHRPWM Start of Conversion B
Table 6-70. EHRPWM0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EHRPWM0_A
EHRPWM Output A
IO
IO
I
V29
V27
U23
U26
V28
EHRPWM0_B
EHRPWM Output B
EHRPWM0_SYNCI
EHRPWM0_SYNCO
EHRPWM_TZn_IN0
Sync Input to EHRPWM module from an external pin
Sync Output to EHRPWM module to an external pin
EHRPWM Trip Zone Input 0 (active low)
O
I
Table 6-71. EHRPWM1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EHRPWM1_A
EHRPWM Output A
IO
IO
I
U28
U29
U25
EHRPWM1_B
EHRPWM Output B
EHRPWM_TZn_IN1
EHRPWM Trip Zone Input 1 (active low)
Table 6-72. EHRPWM2 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EHRPWM2_A
EHRPWM Output A
IO
IO
I
U27
U24
R23
EHRPWM2_B
EHRPWM Output B
EHRPWM_TZn_IN2
EHRPWM Trip Zone Input 2 (active low)
Table 6-73. EHRPWM3 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EHRPWM3_A
EHRPWM Output A
IO
IO
I
V23
W23
W28
V25
EHRPWM3_B
EHRPWM Output B
EHRPWM3_SYNCI
EHRPWM3_SYNCO
EHRPWM_TZn_IN3
Sync Input to EHRPWM module from an external pin
Sync Output to EHRPWM module to an external pin
EHRPWM Trip Zone Input 3 (active low)
O
I
W27
Table 6-74. EHRPWM4 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EHRPWM4_A
EHRPWM Output A
IO
IO
I
W29
W26
Y29
EHRPWM4_B
EHRPWM Output B
EHRPWM_TZn_IN4
EHRPWM Trip Zone Input 4 (active low)
Table 6-75. EHRPWM5 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EHRPWM5_A
EHRPWM5_B
EHRPWM Output A
EHRPWM Output B
IO
IO
Y27
W24
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Table 6-75. EHRPWM5 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EHRPWM_TZn_IN5
EHRPWM Trip Zone Input 5 (active low)
I
W25
6.3.15 USB
6.3.15.1 MAIN Domain
Note
USB3 functionality is available on the SERDES pins. For more information, refer to Section 6.3.16,
SERDES.
Table 6-76. USB0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
IO
IO
O
USB0_DM
USB0_DP
USB 2.0 Differential Data (negative)
USB 2.0 Differential Data (positive)
USB VBUS control output (active high)
USB 2.0 Dual-Role Device Role Select
Pin to connect to calibration resistor
USB Level-shifted VBUS Input
AJ5
AH6
USB0_DRVVBUS
USB0_ID
USB0_RCALIB(2)
USB0_VBUS(1)
T25, T26, U6, V4, W3
A
AC6
AB6
AC7
A
A
(1) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 9.3.4, USB
Design Guidelines.
(2) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
Table 6-77. USB1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
IO
IO
O
USB1_DM
USB1_DP
USB 2.0 Differential Data (negative)
USB 2.0 Differential Data (positive)
USB VBUS control output (active high)
USB 2.0 Dual-Role Device Role Select
Pin to connect to calibration resistor
USB Level-shifted VBUS Input
AH7
AJ6
USB1_DRVVBUS
USB1_ID
USB1_RCALIB(2)
USB1_VBUS(1)
T25, T26, U6, V4, W3
A
AD7
AD9
AD8
A
A
(1) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 9.3.4, USB
Design Guidelines.
(2) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
6.3.16 SERDES
6.3.16.1 MAIN Domain
Table 6-78. SERDES0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] (2)
PCIE0_CLKREQn
DESCRIPTION [2]
PCIE Clock Request Signal
BALL [4]
[3]
IO
IO
IO
A
I
W2
PCIE_REFCLK0N
PCIE_REFCLK0P
SERDES0_REXT(1)
SERDES0_RX0_N
SERDES0_RX0_P
SERDES0_RX1_N
SERDES0_RX1_P
PCIE Reference Clock Input/Output (negative)
PCIE Reference Clock Input/Output (positive)
External Calibration Resistor
AE17
AD16
AE18
AH19
AJ18
AH18
AJ17
SERDES Differential Receive Data (negative)
SERDES Differential Receive Data (positive)
SERDES Differential Receive Data (negative)
SERDES Differential Receive Data (positive)
I
I
I
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Table 6-78. SERDES0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1] (2)
SERDES0_TX0_N
DESCRIPTION [2]
BALL [4]
[3]
SERDES Differential Transmit Data (negative)
SERDES Differential Transmit Data (positive)
SERDES Differential Transmit Data (negative)
SERDES Differential Transmit Data (positive)
O
O
O
O
AF19
AG18
AF18
AG17
SERDES0_TX0_P
SERDES0_TX1_N
SERDES0_TX1_P
(1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
(2) The functionality of these pins is controlled by SERDES0_LN[1:0]_CTRL LANE_FUNC_SEL.
Table 6-79. SERDES1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] (2)
PCIE1_CLKREQn
DESCRIPTION [2]
PCIE Clock Request Signal
BALL [4]
[3]
IO
IO
IO
A
I
W1
PCIE_REFCLK1N
PCIE_REFCLK1P
SERDES1_REXT(1)
SERDES1_RX0_N
SERDES1_RX0_P
SERDES1_RX1_N
SERDES1_RX1_P
SERDES1_TX0_N
SERDES1_TX0_P
SERDES1_TX1_N
SERDES1_TX1_P
PCIE Reference Clock Input/Output (negative)
PCIE Reference Clock Input/Output (positive)
External Calibration Resistor
AE14
AD15
AE13
AH15
AJ14
AH16
AJ15
AF15
AG14
AF16
AG15
SERDES Differential Receive Data (negative)
SERDES Differential Receive Data (positive)
SERDES Differential Receive Data (negative)
SERDES Differential Receive Data (positive)
SERDES Differential Transmit Data (negative)
SERDES Differential Transmit Data (positive)
SERDES Differential Transmit Data (negative)
SERDES Differential Transmit Data (positive)
I
I
I
O
O
O
O
(1) The external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
(2) The functionality of these pins is controlled by SERDES1_LN[1:0]_CTRL LANE_FUNC_SEL.
Table 6-80. SERDES2 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] (2)
PCIE2_CLKREQn
DESCRIPTION [2]
PCIE Clock Request Signal
BALL [4]
[3]
IO
IO
IO
A
I
P23
PCIE_REFCLK2N
PCIE_REFCLK2P
SERDES2_REXT(1)
SERDES2_RX0_N
SERDES2_RX0_P
SERDES2_RX1_N
SERDES2_RX1_P
SERDES2_TX0_N
SERDES2_TX0_P
SERDES2_TX1_N
SERDES2_TX1_P
PCIE Reference Clock Input/Output (negative)
PCIE Reference Clock Input/Output (positive)
External Calibration Resistor
AE11
AD12
AD13
AH13
AJ12
AH12
AJ11
AF13
AG12
AF12
AG11
SERDES Differential Receive Data (negative)
SERDES Differential Receive Data (positive)
SERDES Differential Receive Data (negative)
SERDES Differential Receive Data (positive)
SERDES Differential Transmit Data (negative)
SERDES Differential Transmit Data (positive)
SERDES Differential Transmit Data (negative)
SERDES Differential Transmit Data (positive)
I
I
I
O
O
O
O
(1) The external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
(2) The functionality of these pins is controlled by SERDES2_LN[1:0]_CTRL LANE_FUNC_SEL.
Table 6-81. SERDES3 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] (2)
PCIE3_CLKREQn
DESCRIPTION [2]
PCIE Clock Request Signal
BALL [4]
[3]
IO
IO
R28
AE9
PCIE_REFCLK3N
PCIE Reference Clock Input/Output (negative)
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Table 6-81. SERDES3 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1] (2)
DESCRIPTION [2]
BALL [4]
[3]
PCIE_REFCLK3P
SERDES3_REXT(1)
SERDES3_RX0_N
SERDES3_RX0_P
SERDES3_RX1_N
SERDES3_RX1_P
SERDES3_TX0_N
SERDES3_TX0_P
SERDES3_TX1_N
SERDES3_TX1_P
PCIE Reference Clock Input/Output (positive)
External Calibration Resistor
IO
A
I
AD10
AE8
AH9
AJ8
SERDES Differential Receive Data (negative)
SERDES Differential Receive Data (positive)
SERDES Differential Receive Data (negative)
SERDES Differential Receive Data (positive)
SERDES Differential Transmit Data (negative)
SERDES Differential Transmit Data (positive)
SERDES Differential Transmit Data (negative)
SERDES Differential Transmit Data (positive)
I
I
AH10
AJ9
I
O
O
O
O
AF9
AG8
AF10
AG9
(1) The external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
(2) The functionality of these pins is controlled by SERDES3_LN[1:0]_CTRL LANE_FUNC_SEL.
Table 6-82. SERDES4 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] (2)
SERDES4_REFCLK_N
DESCRIPTION [2]
BALL [4]
[3]
IO
IO
A
I
SERDES Reference Differential Clock (negative)
SERDES Reference Differential Clock (positive)
External Calibration Resistor
E7
E8
SERDES4_REFCLK_P
SERDES4_REXT(1)
SERDES4_RX0_N
SERDES4_RX0_P
SERDES4_RX1_N
SERDES4_RX1_P
SERDES4_RX2_N
SERDES4_RX2_P
SERDES4_RX3_N
SERDES4_RX3_P
SERDES4_TX0_N
SERDES4_TX0_P
SERDES4_TX1_N
SERDES4_TX1_P
SERDES4_TX2_N
SERDES4_TX2_P
SERDES4_TX3_N
SERDES4_TX3_P
F9
SERDES Differential Receive Data (negative)
SERDES Differential Receive Data (positive)
SERDES Differential Receive Data (negative)
SERDES Differential Receive Data (positive)
SERDES Differential Receive Data (negative)
SERDES Differential Receive Data (positive)
SERDES Differential Receive Data (negative)
SERDES Differential Receive Data (positive)
SERDES Differential Transmit Data (negative)
SERDES Differential Transmit Data (positive)
SERDES Differential Transmit Data (negative)
SERDES Differential Transmit Data (positive)
SERDES Differential Transmit Data (negative)
SERDES Differential Transmit Data (positive)
SERDES Differential Transmit Data (negative)
SERDES Differential Transmit Data (positive)
D9
C10
D8
C9
D6
C7
D5
C6
B11
A12
B10
A11
B8
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
A9
B7
A8
(1) The external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
(2) The functionality of these pins is controlled by SERDES4_LN[4:0]_CTRL LANE_FUNC_SEL.
6.3.17 OSPI
6.3.17.1 MCU Domain
Table 6-83. OSPI0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
MCU_OSPI0_CLK
DESCRIPTION [2]
BALL [4]
[3]
O
I
OSPI Clock
E20
D21
B23
MCU_OSPI0_DQS
MCU_OSPI0_ECC_FAIL(1)
OSPI Data Strobe (DQS) or Loopback Clock Input
OSPI ECC Status
I
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Table 6-83. OSPI0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
MCU_OSPI0_LBCLKO
DESCRIPTION [2]
OSPI Loopback Clock Output
BALL [4]
[3]
IO
O
C21
F19
E19
A23
B23
D20
G19
G20
F20
F21
E21
B22
G21
A23
E22
MCU_OSPI0_CSn0
MCU_OSPI0_CSn1
MCU_OSPI0_CSn2
MCU_OSPI0_CSn3
MCU_OSPI0_D0
OSPI Chip Select 0 (active low)
OSPI Chip Select 1 (active low)
OSPI Chip Select 2 (active low)
OSPI Chip Select 3 (active low)
OSPI Data 0
O
O
O
IO
IO
IO
IO
IO
IO
IO
IO
O
MCU_OSPI0_D1
OSPI Data 1
MCU_OSPI0_D2
OSPI Data 2
MCU_OSPI0_D3
OSPI Data 3
MCU_OSPI0_D4
OSPI Data 4
MCU_OSPI0_D5
OSPI Data 5
MCU_OSPI0_D6
OSPI Data 6
MCU_OSPI0_D7
OSPI Data 7
MCU_OSPI0_RESET_OUT0
MCU_OSPI0_RESET_OUT1
OSPI Reset
OSPI Reset
O
(1) An external pull-up resistor to corresponting power supply is recommended on this signal.
Table 6-84. OSPI1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
MCU_OSPI1_CLK
DESCRIPTION [2]
BALL [4]
[3]
OSPI Clock
O
I
F22
B23
A23
C22
E22
D22
G22
D23
C23
MCU_OSPI1_DQS
MCU_OSPI1_LBCLKO
MCU_OSPI1_CSn0
MCU_OSPI1_CSn1
MCU_OSPI1_D0
MCU_OSPI1_D1
MCU_OSPI1_D2
MCU_OSPI1_D3
OSPI Data Strobe (DQS) or Loopback Clock Input
OSPI Loopback Clock Output
OSPI Chip Select 0 (active low)
OSPI Chip Select 1 (active low)
OSPI Data 0
IO
O
O
IO
IO
IO
IO
OSPI Data 1
OSPI Data 2
OSPI Data 3
6.3.18 Hyperbus
6.3.18.1 MCU Domain
Table 6-85. HYPERBUS0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_HYPERBUS0_CK
MCU_HYPERBUS0_CKn
MCU_HYPERBUS0_INTn
MCU_HYPERBUS0_RESETn
Hyperbus Differential Clock (positive)
Hyperbus Differential Clock (negative)
Hyperbus Interrupt (active low)
O
O
I
E20
C21
B23
E19
Hyperbus Reset (active low) Output
O
Hyperbus Reset Status Indicator (active low) from
Hyperbus Memory
MCU_HYPERBUS0_RESETOn
I
A23
MCU_HYPERBUS0_RWDS
MCU_HYPERBUS0_WPn
MCU_HYPERBUS0_CSn0
MCU_HYPERBUS0_CSn1
MCU_HYPERBUS0_DQ0
Hyperbus Read-Write Data Strobe
Hyperbus Write Protect (not in use)
Hyperbus Chip Select 0
IO
O
D21
E22
F19
E22
D20
O
Hyperbus Chip Select 1
O
Hyperbus Data 0
IO
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Table 6-85. HYPERBUS0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCU_HYPERBUS0_DQ1
MCU_HYPERBUS0_DQ2
MCU_HYPERBUS0_DQ3
MCU_HYPERBUS0_DQ4
MCU_HYPERBUS0_DQ5
MCU_HYPERBUS0_DQ6
MCU_HYPERBUS0_DQ7
Hyperbus Data 1
Hyperbus Data 2
Hyperbus Data 3
Hyperbus Data 4
Hyperbus Data 5
Hyperbus Data 6
Hyperbus Data 7
IO
IO
IO
IO
IO
IO
IO
G19
G20
F20
F21
E21
B22
G21
6.3.19 GPMC
6.3.19.1 MAIN Domain
Table 6-86. GPMC0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
GPMC0_FCLK_MUX
DESCRIPTION [2]
BALL [4]
AB23
[3]
GPMC functional clock output selected through a mux
logic
O
O
GPMC Address Valid (active low) or Address Latch
Enable
GPMC0_ADVn_ALE
AG20
GPMC0_CLKOUT
GPMC0_DIR
GPMC clock generated for external synchronization
GPMC Data Bus Signal Direction Control
O
O
AB23
AJ23, W25
GPMC Output Enable (active low) or Read Enable
(active low)
GPMC0_OEn_REn
O
AJ20
GPMC0_WEn
GPMC0_WPn
GPMC Write Enable (active low)
O
O
AD20
AG21
GPMC Flash Write Protect (active low)
GPMC Address 0 Output. Only used to effectively
address 8-bit data non-multiplexed memories
GPMC0_A0
GPMC0_A1
GPMC0_A2
GPMC0_A3
GPMC0_A4
GPMC0_A5
GPMC0_A6
GPMC0_A7
GPMC0_A8
GPMC0_A9
GPMC0_A10
GPMC0_A11
GPMC0_A12
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
AA27
U23
U26
V28
V29
V27
U28
U29
U25
U27
U24
R23
T23
GPMC address 1 Output in A/D non-multiplexed mode
and Address 17 in A/D multiplexed mode
GPMC address 2 Output in A/D non-multiplexed mode
and Address 18 in A/D multiplexed mode
GPMC address 3 Output in A/D non-multiplexed mode
and Address 19 in A/D multiplexed mode
GPMC address 4 Output in A/D non-multiplexed mode
and Address 20 in A/D multiplexed mode
GPMC address 5 Output in A/D non-multiplexed mode
and Address 21 in A/D multiplexed mode
GPMC address 6 Output in A/D non-multiplexed mode
and Address 22 in A/D multiplexed mode
GPMC address 7 Output in A/D non-multiplexed mode
and Address 23 in A/D multiplexed mode
GPMC address 8 Output in A/D non-multiplexed mode
and Address 24 in A/D multiplexed mode
GPMC address 9 Output in A/D non-multiplexed mode
and Address 25 in A/D multiplexed mode
GPMC address 10 Output in A/D non-multiplexed mode
and Address 26 in A/D multiplexed mode
GPMC address 11 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 12 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
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Table 6-86. GPMC0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
GPMC address 13 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC0_A13
GPMC0_A14
GPMC0_A15
GPMC0_A16
GPMC0_A17
GPMC0_A18
GPMC0_A19
GPMC0_A20
GPMC0_A21
GPMC0_A22
GPMC0_A23
GPMC0_A24
GPMC0_A25
GPMC0_A26
GPMC0_A27
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
Y28
V23
GPMC address 14 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 15 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
W23
W28
V25
GPMC address 16 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 17 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 18 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
W27
W29
W26
Y29
GPMC address 19 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 20 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 21 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 22 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
Y27
GPMC address 23 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
AD27
AD29
AC26
AG26
Y26
GPMC address 24 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 25 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 26 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 27 in A/D non-multiplexed mode and
Address 27 in A/D multiplexed mode
GPMC Data 0 Input/Output in A/D non-multiplexed mode
and additionally Address 1 Output in A/D multiplexed
mode
GPMC0_AD0
GPMC0_AD1
GPMC0_AD2
GPMC0_AD3
GPMC0_AD4
GPMC0_AD5
GPMC0_AD6
GPMC0_AD7
IO
IO
IO
IO
IO
IO
IO
IO
AC29
AC28
AC27
AB26
AB25
AB24
AB29
AB28
GPMC Data 1 Input/Output in A/D non-multiplexed mode
and additionally Address 2 Output in A/D multiplexed
mode
GPMC Data 2 Input/Output in A/D non-multiplexed mode
and additionally Address 3 Output in A/D multiplexed
mode
GPMC Data 3 Input/Output in A/D non-multiplexed mode
and additionally Address 4 Output in A/D multiplexed
mode
GPMC Data 4 Input/Output in A/D non-multiplexed mode
and additionally Address 5 Output in A/D multiplexed
mode
GPMC Data 5 Input/Output in A/D non-multiplexed mode
and additionally Address 6 Output in A/D multiplexed
mode
GPMC Data 6 Input/Output in A/D non-multiplexed mode
and additionally Address 7 Output in A/D multiplexed
mode
GPMC Data 7 Input/Output in A/D non-multiplexed mode
and additionally Address 8 Output in A/D multiplexed
mode
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Table 6-86. GPMC0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
GPMC Data 8 Input/Output in A/D non-multiplexed mode
and additionally Address 9 Output in A/D multiplexed
mode
GPMC0_AD8
GPMC0_AD9
IO
IO
IO
IO
IO
IO
IO
AB27
GPMC Data 9 Input/Output in A/D non-multiplexed mode
and additionally Address 10 Output in A/D multiplexed
mode
AA24
AA28
Y24
GPMC Data 10 Input/Output in A/D non-multiplexed
mode and additionally Address 11 Output in A/D
multiplexed mode
GPMC0_AD10
GPMC0_AD11
GPMC0_AD12
GPMC0_AD13
GPMC0_AD14
GPMC Data 11 Input/Output in A/D non-multiplexed
mode and additionally Address 12 Output in A/D
multiplexed mode
GPMC Data 12 Input/Output in A/D non-multiplexed
mode and additionally Address 13 Output in A/D
multiplexed mode
AA25
Y25
GPMC Data 13 Input/Output in A/D non-multiplexed
mode and additionally Address 14 Output in A/D
multiplexed mode
GPMC Data 14 Input/Output in A/D non-multiplexed
mode and additionally Address 15 Output in A/D
multiplexed mode
AA26
GPMC Data 15 Input/Output in A/D non-multiplexed
mode and additionally Address 16 Output in A/D
multiplexed mode
GPMC0_AD15
IO
O
AA29
AD21
GPMC Lower-Byte Enable (active low) or Command
Latch Enable
GPMC0_BE0n_CLE
GPMC0_BE1n
GPMC0_CSn0
GPMC0_CSn1
GPMC0_CSn2
GPMC0_CSn3
GPMC0_WAIT0
GPMC0_WAIT1
GPMC0_WAIT2
GPMC0_WAIT3
GPMC Upper-Byte Enable (active low)
GPMC Chip Select 0 (active low)
GPMC Chip Select 1 (active low)
GPMC Chip Select 2 (active low)
GPMC Chip Select 3 (active low)
GPMC External Indication of Wait
GPMC External Indication of Wait
GPMC External Indication of Wait
GPMC External Indication of Wait
O
O
O
O
O
I
AC23, W24
AF21
Y23
AH23
AD22
AG22
AF22
V24
I
I
I
V26
6.3.20 MMC
6.3.20.1 MAIN Domain
Table 6-87. MMC0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MMC0_CALPAD(1)
MMC0_CLK
MMC0_CMD(2)
MMC/SD/SDIO Calibration Resistor
MMC/SD/SDIO Clock
MMC/SD/SDIO Command
MMC Data Strobe
A
AE1
AF1
AE3
AE4
AG2
AH1
AG3
AF4
AE5
O
IO
IO
IO
IO
IO
IO
IO
MMC0_DS
MMC0_DAT0(2)
MMC0_DAT1(2)
MMC0_DAT2(2)
MMC0_DAT3(2)
MMC0_DAT4(2)
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
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Table 6-87. MMC0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
MMC0_DAT5(2)
MMC0_DAT6(2)
MMC0_DAT7(2)
DESCRIPTION [2]
MMC/SD/SDIO Data
BALL [4]
[3]
IO
IO
IO
AF3
AG1
AF2
MMC/SD/SDIO Data
MMC/SD/SDIO Data
(1) An external 10 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
(2) An external pull-up of 10 kΩ ~ 50 kΩ ±1% resistor, as specified in the specification, must be connected to this ball to ensure proper
operation.
Table 6-88. MMC1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
MMC/SD/SDIO Clock
BALL [4]
[3]
IO
IO
I
MMC1_CLK(1)
MMC1_CMD
P25
R29
P23
R28
R24
P24
R25
R26
MMC/SD/SDIO Command
SD Card Detect
MMC1_SDCD(2)
MMC1_SDWP
MMC1_DAT0
MMC1_DAT1
MMC1_DAT2
MMC1_DAT3
SD Write Protect
I
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
IO
IO
IO
IO
(1) For MMC1_CLK signal to work properly, the RXACTIVE bit of the CTRLMMR_PADCONFIG171 register should be set to 0x1 because
of retiming purposes.
(2) For ROM boot to work properly, the MMC1_SDCD pin should be pulled low externally with a resistor.
Table 6-89. MMC2 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
MMC/SD/SDIO Clock
BALL [4]
[3]
IO
IO
I
MMC2_CLK(1)
MMC2_CMD
T26
T25
W2
MMC/SD/SDIO Command
SD Card Detect
MMC2_SDCD(2)
MMC2_SDWP
MMC2_DAT0
MMC2_DAT1
MMC2_DAT2
MMC2_DAT3
SD Write Protect
I
W1
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
IO
IO
IO
IO
T24
T27
T29
T28
(1) For MMC2_CLK signal to work properly, the RXACTIVE bit of the CTRLMMR_PADCONFIG172 register should be set to 0x1 because
of retiming purposes.
(2) For MMC2 module to work properly, the MMC2_SDCD pin should be pulled low.
6.3.21 CPTS
Note
Some CPTS signals are connected directly to CPTS modules within the device. Other CPTS signals
are connected to the Time Sync Router and fanned out to peripherals linked to the router. Input
signals are sent to the peripherals while output signals are sourced from the peripherals. For more
information, see the Time Sync and Compare Events section in the Time Sync chapter in the device
TRM.
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6.3.21.1 MCU Domain
Table 6-90. MCU_CPTS0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
MCU_CPTS0_RFT_CLK
DESCRIPTION [2]
CPTS Reference Clock
BALL [4]
H26
[3]
I
Time Stamp Counter Compare from
MCU_CPSW0_CPTS0
MCU_CPTS0_TS_COMP
MCU_CPTS0_TS_SYNC
MCU_CPTS0_HW1TSPUSH
O
O
I
G26
Time Stamp Counter Bit from MCU_CPSW0_CPTS0
G27
Hardware Time Stamp Push 1 input to Time Sync Router
and MCU_CPSW0_CPTS0
F29
Hardware Time Stamp Push 2 input to Time Sync Router
and MCU_CPSW0_CPTS0
MCU_CPTS0_HW2TSPUSH
I
G28
6.3.21.2 MAIN Domain
Table 6-91. CPTS0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
CPTS0_RFT_CLK
CPTS0_TS_COMP
CPTS0_TS_SYNC
CPTS0_HW1TSPUSH
CPTS0_HW2TSPUSH
SYNC0_OUT
CPTS Reference Clock
I
U2
Y4
Time Stamp Counter Compare from NAVSS0_CPTS0
Time Stamp Counter Bit from NAVSS0_CPTS0
Hardware Time Stamp Push input to Time Sync Router
Hardware Time Stamp Push input to Time Sync Router
Time Stamp Generator Bit 0 from Time Sync Router
Time Stamp Generator Bit 1 from Time Sync Router
Time Stamp Generator Bit 2 from Time Sync Router
Time Stamp Generator Bit 3 from Time Sync Router
O
O
I
W4
T28, Y6
AA6, T29
U2
I
O
O
O
O
SYNC1_OUT
U3
SYNC2_OUT
V28
SYNC3_OUT
V29
6.3.22 UFS
6.3.22.1 MAIN Domain
Table 6-92. UFS0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
UFS0_REF_CLK
UFS0_RSTn
UFS Reference Clock
O
O
I
AE6
AD6
AH3
AJ2
AH4
AJ3
AG6
AF7
AG5
AF6
UFS Reset Out
UFS0_RX_DN0
UFS0_RX_DP0
UFS0_RX_DN1
UFS0_RX_DP1
UFS0_TX_DN0
UFS0_TX_DP0
UFS0_TX_DN1
UFS0_TX_DP1
UFS Lane 0 Differential Receive Data (negative)
UFS Lane 0 Differential Receive Data (positive)
UFS Lane 1 Differential Receive Data (negative)
UFS Lane 1 Differential Receive Data (positive)
UFS Lane 0 Differential Transmit Data (negative)
UFS Lane 0 Differential Transmit Data (positive)
UFS Lane 1 Differential Transmit Data (negative)
UFS Lane 1 Differential Transmit Data (positive)
I
I
I
O
O
O
O
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6.3.23 PRU_ICSSG [Currently Not Supported]
6.3.23.1 MAIN Domain
Table 6-93. PRU_ICSSG0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
PRU_ICSSG Enhanced Capture (ECAP) Input or
Auxiliary PWM (APWM) Ouput
PRG0_ECAP0_IN_APWM_OUT
IO
AB29
PRG0_ECAP0_SYNC_IN
PRU_ICSSG ECAP Sync Input
I
AC28
AB24
Y3
PRG0_ECAP0_SYNC_OUT
PRG0_IEP0_EDIO_OUTVALID
PRU_ICSSG ECAP Sync Output
O
O
PRU_ICSSG Industrial Ethernet Digital I/O Outvalid
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
PRG0_IEP0_EDC_LATCH_IN0
PRG0_IEP0_EDC_LATCH_IN1
PRG0_IEP0_EDC_SYNC_OUT0
PRG0_IEP0_EDC_SYNC_OUT1
PRG0_IEP0_EDIO_DATA_IN_OUT28
PRG0_IEP0_EDIO_DATA_IN_OUT29
PRG0_IEP0_EDIO_DATA_IN_OUT30
PRG0_IEP0_EDIO_DATA_IN_OUT31
PRG0_IEP1_EDC_LATCH_IN0
PRG0_IEP1_EDC_LATCH_IN1
PRG0_IEP1_EDC_SYNC_OUT0
PRG0_IEP1_EDC_SYNC_OUT1
I
AB29, Y3
AC28, P23
AB28, Y1
AB24, R28
AB26
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
O
IO
IO
IO
IO
I
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
AB25
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
Y24
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
AA25
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
AA26, Y5
AA24, T27
AA29, Y2
T24, Y25
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
O
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
PRG0_MDIO0_MDC
PRG0_MDIO0_MDIO
PRG0_PRU0_GPI0
PRG0_PRU0_GPI1
PRG0_PRU0_GPI2
PRG0_PRU0_GPI3
PRG0_PRU0_GPI4
PRG0_PRU0_GPI5
PRG0_PRU0_GPI6
PRG0_PRU0_GPI7
PRG0_PRU0_GPI8
PRG0_PRU0_GPI9
PRG0_PRU0_GPI10
PRG0_PRU0_GPI11
PRG0_PRU0_GPI12
PRG0_PRU0_GPI13
PRG0_PRU0_GPI14
PRU_ICSSG MDIO Clock
O
IO
I
AA27
Y26
PRU_ICSSG MDIO Data
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
AF28
AE28
AE27
AD26
AD25
AC29
AE26
AC28
AC27
AB26
AB25
AJ28
AH27
AH29
AG28
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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Table 6-93. PRU_ICSSG0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
PRU_ICSSG PRU Data Input
BALL [4]
[3]
PRG0_PRU0_GPI15
PRG0_PRU0_GPI16
PRG0_PRU0_GPI17
PRG0_PRU0_GPI18
PRG0_PRU0_GPI19
PRG0_PRU0_GPO0
PRG0_PRU0_GPO1
PRG0_PRU0_GPO2
PRG0_PRU0_GPO3
PRG0_PRU0_GPO4
PRG0_PRU0_GPO5
PRG0_PRU0_GPO6
PRG0_PRU0_GPO7
PRG0_PRU0_GPO8
PRG0_PRU0_GPO9
PRG0_PRU0_GPO10
PRG0_PRU0_GPO11
PRG0_PRU0_GPO12
PRG0_PRU0_GPO13
PRG0_PRU0_GPO14
PRG0_PRU0_GPO15
PRG0_PRU0_GPO16
PRG0_PRU0_GPO17
PRG0_PRU0_GPO18
PRG0_PRU0_GPO19
PRG0_PRU1_GPI0
PRG0_PRU1_GPI1
PRG0_PRU1_GPI2
PRG0_PRU1_GPI3
PRG0_PRU1_GPI4
PRG0_PRU1_GPI5
PRG0_PRU1_GPI6
PRG0_PRU1_GPI7
PRG0_PRU1_GPI8
PRG0_PRU1_GPI9
PRG0_PRU1_GPI10
PRG0_PRU1_GPI11
PRG0_PRU1_GPI12
PRG0_PRU1_GPI13
PRG0_PRU1_GPI14
PRG0_PRU1_GPI15
PRG0_PRU1_GPI16
PRG0_PRU1_GPI17
PRG0_PRU1_GPI18
PRG0_PRU1_GPI19
I
I
AG27
AH28
AB24
AB29
AB28
AF28
AE28
AE27
AD26
AD25
AC29
AE26
AC28
AC27
AB26
AB25
AJ28
AH27
AH29
AG28
AG27
AH28
AB24
AB29
AB28
AE29
AD28
AD27
AC25
AD29
AB27
AC26
AA24
AA28
Y24
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
I
I
I
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
I
I
I
I
I
I
I
I
I
I
AA25
AG26
AF27
AF26
AE25
AF29
AG29
Y25
I
I
I
I
I
I
I
I
AA26
AA29
I
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Table 6-93. PRU_ICSSG0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
PRG0_PRU1_GPO0
DESCRIPTION [2]
PRU_ICSSG PRU Data Output
BALL [4]
[3]
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
AE29
AD28
AD27
AC25
AD29
AB27
AC26
AA24
AA28
Y24
PRG0_PRU1_GPO1
PRG0_PRU1_GPO2
PRG0_PRU1_GPO3
PRG0_PRU1_GPO4
PRG0_PRU1_GPO5
PRG0_PRU1_GPO6
PRG0_PRU1_GPO7
PRG0_PRU1_GPO8
PRG0_PRU1_GPO9
PRG0_PRU1_GPO10
PRG0_PRU1_GPO11
PRG0_PRU1_GPO12
PRG0_PRU1_GPO13
PRG0_PRU1_GPO14
PRG0_PRU1_GPO15
PRG0_PRU1_GPO16
PRG0_PRU1_GPO17
PRG0_PRU1_GPO18
PRG0_PRU1_GPO19
PRG0_PWM0_TZ_IN
PRG0_PWM0_TZ_OUT
PRG0_PWM1_TZ_IN
PRG0_PWM1_TZ_OUT
PRG0_PWM2_TZ_IN
PRG0_PWM2_TZ_OUT
PRG0_PWM3_TZ_IN
PRG0_PWM3_TZ_OUT
PRG0_PWM0_A0
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PWM Trip Zone Input
PRU_ICSSG PWM Trip Zone Output
PRU_ICSSG PWM Trip Zone Input
PRU_ICSSG PWM Trip Zone Output
PRU_ICSSG PWM Trip Zone Input
PRU_ICSSG PWM Trip Zone Output
PRU_ICSSG PWM Trip Zone Input
PRU_ICSSG PWM Trip Zone Output
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output B
AA25
AG26
AF27
AF26
AE25
AF29
AG29
Y25
AA26
AA29
AB29
AB28
AA26
AA29
AA25
AA28
AB26
AJ28
AH27
AG28
AH28
AH29
AG27
AB24
AF27
AE25
AG29
AF26
AF29
Y25
O
I
O
I
O
I
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PRG0_PWM0_A1
PRG0_PWM0_A2
PRG0_PWM0_B0
PRG0_PWM0_B1
PRG0_PWM0_B2
PRG0_PWM1_A0
PRG0_PWM1_A1
PRG0_PWM1_A2
PRG0_PWM1_B0
PRG0_PWM1_B1
PRG0_PWM1_B2
PRG0_PWM2_A0
AE27
AC27
AD27
AD25
AB25
PRG0_PWM2_A1
PRG0_PWM2_A2
PRG0_PWM2_B0
PRG0_PWM2_B1
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Table 6-93. PRU_ICSSG0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
PRU_ICSSG PWM Output B
BALL [4]
[3]
PRG0_PWM2_B2
IO
IO
IO
IO
IO
IO
IO
I
AD29
AF28
AE26
AD26
AE28
AC28
AC29
AE26
AD25
AH28
AG27
AC26
AD29
AG29
AF29
AF28
AE28
AE27
AD26
AJ28
AH27
AH29
AG28
AE29
AD28
AD27
AC25
AG26
AF27
AF26
AE25
AB26
AB25
Y24
PRG0_PWM3_A0
PRU_ICSSG PWM Output A
PRG0_PWM3_A1
PRU_ICSSG PWM Output A
PRG0_PWM3_A2
PRU_ICSSG PWM Output A
PRG0_PWM3_B0
PRU_ICSSG PWM Output B
PRG0_PWM3_B1
PRU_ICSSG PWM Output B
PRG0_PWM3_B2
PRU_ICSSG PWM Output B
PRG0_RGMII1_RXC
PRG0_RGMII1_RX_CTL
PRG0_RGMII1_TXC
PRG0_RGMII1_TX_CTL
PRG0_RGMII2_RXC
PRG0_RGMII2_RX_CTL
PRG0_RGMII2_TXC
PRG0_RGMII2_TX_CTL
PRG0_RGMII1_RD0
PRG0_RGMII1_RD1
PRG0_RGMII1_RD2
PRG0_RGMII1_RD3
PRG0_RGMII1_TD0
PRG0_RGMII1_TD1
PRG0_RGMII1_TD2
PRG0_RGMII1_TD3
PRG0_RGMII2_RD0
PRG0_RGMII2_RD1
PRG0_RGMII2_RD2
PRG0_RGMII2_RD3
PRG0_RGMII2_TD0
PRG0_RGMII2_TD1
PRG0_RGMII2_TD2
PRG0_RGMII2_TD3
PRG0_UART0_CTSn
PRG0_UART0_RTSn
PRG0_UART0_RXD
PRG0_UART0_TXD
PRU_ICSSG RGMII Receive Clock
PRU_ICSSG RGMII Receive Control
PRU_ICSSG RGMII Transmit Clock
PRU_ICSSG RGMII Transmit Control
PRU_ICSSG RGMII Receive Clock
PRU_ICSSG RGMII Receive Control
PRU_ICSSG RGMII Transmit Clock
PRU_ICSSG RGMII Transmit Control
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG UART Clear to Send (active low)
PRU_ICSSG UART Request to Send (active low)
PRU_ICSSG UART Receive Data
PRU_ICSSG UART Transmit Data
I
IO
O
I
I
IO
O
I
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
I
O
I
O
AA25
Table 6-94. PRU_ICSSG1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
PRU_ICSSG Enhanced Capture (ECAP) Input or
Auxiliary PWM (APWM) Ouput
PRG1_ECAP0_IN_APWM_OUT
IO
AH22
PRG1_ECAP0_SYNC_IN
PRU_ICSSG ECAP Sync Input
I
AJ22
AC22
Y4
PRG1_ECAP0_SYNC_OUT
PRG1_IEP0_EDIO_OUTVALID
PRU_ICSSG ECAP Sync Output
O
O
PRU_ICSSG Industrial Ethernet Digital I/O Outvalid
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
PRG1_IEP0_EDC_LATCH_IN0
I
AE21
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Table 6-94. PRU_ICSSG1 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
PRG1_IEP0_EDC_LATCH_IN1
PRG1_IEP0_EDC_SYNC_OUT0
PRG1_IEP0_EDC_SYNC_OUT1
PRG1_IEP0_EDIO_DATA_IN_OUT28
PRG1_IEP0_EDIO_DATA_IN_OUT29
PRG1_IEP0_EDIO_DATA_IN_OUT30
PRG1_IEP0_EDIO_DATA_IN_OUT31
PRG1_IEP1_EDC_LATCH_IN0
PRG1_IEP1_EDC_LATCH_IN1
PRG1_IEP1_EDC_SYNC_OUT0
PRG1_IEP1_EDC_SYNC_OUT1
DESCRIPTION [2]
BALL [4]
[3]
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
AE20
AH21
AJ21
AG20
AD21
AF21
AB23
AJ22
AC21
AH22
AC22
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
O
IO
IO
IO
IO
I
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
O
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
PRG1_MDIO0_MDC
PRG1_MDIO0_MDIO
PRG1_PRU0_GPI0
PRG1_PRU0_GPI1
PRG1_PRU0_GPI2
PRG1_PRU0_GPI3
PRG1_PRU0_GPI4
PRG1_PRU0_GPI5
PRG1_PRU0_GPI6
PRG1_PRU0_GPI7
PRG1_PRU0_GPI8
PRG1_PRU0_GPI9
PRG1_PRU0_GPI10
PRG1_PRU0_GPI11
PRG1_PRU0_GPI12
PRG1_PRU0_GPI13
PRG1_PRU0_GPI14
PRG1_PRU0_GPI15
PRG1_PRU0_GPI16
PRG1_PRU0_GPI17
PRG1_PRU0_GPI18
PRG1_PRU0_GPI19
PRG1_PRU0_GPO0
PRG1_PRU0_GPO1
PRG1_PRU0_GPO2
PRG1_PRU0_GPO3
PRU_ICSSG MDIO Clock
O
AD18
AD19
AC23
AG22
AF22
AJ23
AH23
AD20
AD22
AE20
AJ20
AG20
AD21
AF24
AJ24
AG24
AD24
AC24
AE24
AJ21
AE21
AH21
AC23
AG22
AF22
AJ23
PRU_ICSSG MDIO Data
IO
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
IO
IO
IO
IO
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Table 6-94. PRU_ICSSG1 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
PRU_ICSSG PRU Data Output
BALL [4]
[3]
PRG1_PRU0_GPO4
PRG1_PRU0_GPO5
PRG1_PRU0_GPO6
PRG1_PRU0_GPO7
PRG1_PRU0_GPO8
PRG1_PRU0_GPO9
PRG1_PRU0_GPO10
PRG1_PRU0_GPO11
PRG1_PRU0_GPO12
PRG1_PRU0_GPO13
PRG1_PRU0_GPO14
PRG1_PRU0_GPO15
PRG1_PRU0_GPO16
PRG1_PRU0_GPO17
PRG1_PRU0_GPO18
PRG1_PRU0_GPO19
PRG1_PRU1_GPI0
PRG1_PRU1_GPI1
PRG1_PRU1_GPI2
PRG1_PRU1_GPI3
PRG1_PRU1_GPI4
PRG1_PRU1_GPI5
PRG1_PRU1_GPI6
PRG1_PRU1_GPI7
PRG1_PRU1_GPI8
PRG1_PRU1_GPI9
PRG1_PRU1_GPI10
PRG1_PRU1_GPI11
PRG1_PRU1_GPI12
PRG1_PRU1_GPI13
PRG1_PRU1_GPI14
PRG1_PRU1_GPI15
PRG1_PRU1_GPI16
PRG1_PRU1_GPI17
PRG1_PRU1_GPI18
PRG1_PRU1_GPI19
PRG1_PRU1_GPO0
PRG1_PRU1_GPO1
PRG1_PRU1_GPO2
PRG1_PRU1_GPO3
PRG1_PRU1_GPO4
PRG1_PRU1_GPO5
PRG1_PRU1_GPO6
PRG1_PRU1_GPO7
PRG1_PRU1_GPO8
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
AH23
AD20
AD22
AE20
AJ20
AG20
AD21
AF24
AJ24
AG24
AD24
AC24
AE24
AJ21
AE21
AH21
AE22
AG23
AF23
AD23
AH24
AG21
AE23
AC21
Y23
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Input
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
I
I
I
I
I
I
I
I
I
AF21
AB23
AJ25
AH25
AG25
AH26
AJ27
AJ26
AC22
AJ22
AH22
AE22
AG23
AF23
AD23
AH24
AG21
AE23
AC21
Y23
I
I
I
I
I
I
I
I
I
I
IO
IO
IO
IO
IO
IO
IO
IO
IO
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Table 6-94. PRU_ICSSG1 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
PRG1_PRU1_GPO9
DESCRIPTION [2]
PRU_ICSSG PRU Data Output
BALL [4]
[3]
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
AF21
AB23
AJ25
AH25
AG25
AH26
AJ27
AJ26
AC22
AJ22
AH22
AE21
AH21
AJ22
AH22
AB23
Y23
PRG1_PRU1_GPO10
PRG1_PRU1_GPO11
PRG1_PRU1_GPO12
PRG1_PRU1_GPO13
PRG1_PRU1_GPO14
PRG1_PRU1_GPO15
PRG1_PRU1_GPO16
PRG1_PRU1_GPO17
PRG1_PRU1_GPO18
PRG1_PRU1_GPO19
PRG1_PWM0_TZ_IN
PRG1_PWM0_TZ_OUT
PRG1_PWM1_TZ_IN
PRG1_PWM1_TZ_OUT
PRG1_PWM2_TZ_IN
PRG1_PWM2_TZ_OUT
PRG1_PWM3_TZ_IN
PRG1_PWM3_TZ_OUT
PRG1_PWM0_A0
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PRU Data Output
PRU_ICSSG PWM Trip Zone Input
PRU_ICSSG PWM Trip Zone Output
PRU_ICSSG PWM Trip Zone Input
PRU_ICSSG PWM Trip Zone Output
PRU_ICSSG PWM Trip Zone Input
PRU_ICSSG PWM Trip Zone Output
PRU_ICSSG PWM Trip Zone Input
PRU_ICSSG PWM Trip Zone Output
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output B
PRU_ICSSG RGMII Receive Clock
PRU_ICSSG RGMII Receive Control
O
I
O
I
O
I
AG20
AF24
AJ24
AD24
AE24
AG24
AC24
AJ21
AH25
AH26
AJ26
AG25
AJ27
AC22
AF22
AJ20
AF23
AH23
AD21
AH24
AC23
AD22
AJ23
AG22
AE20
AD20
AD22
AH23
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
PRG1_PWM0_A1
PRG1_PWM0_A2
PRG1_PWM0_B0
PRG1_PWM0_B1
PRG1_PWM0_B2
PRG1_PWM1_A0
PRG1_PWM1_A1
PRG1_PWM1_A2
PRG1_PWM1_B0
PRG1_PWM1_B1
PRG1_PWM1_B2
PRG1_PWM2_A0
PRG1_PWM2_A1
PRG1_PWM2_A2
PRG1_PWM2_B0
PRG1_PWM2_B1
PRG1_PWM2_B2
PRG1_PWM3_A0
PRG1_PWM3_A1
PRG1_PWM3_A2
PRG1_PWM3_B0
PRG1_PWM3_B1
PRG1_PWM3_B2
PRG1_RGMII1_RXC
PRG1_RGMII1_RX_CTL
I
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Table 6-94. PRU_ICSSG1 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
PRG1_RGMII1_TXC
PRG1_RGMII1_TX_CTL
PRG1_RGMII2_RXC
PRG1_RGMII2_RX_CTL
PRG1_RGMII2_TXC
PRG1_RGMII2_TX_CTL
PRG1_RGMII1_RD0
PRG1_RGMII1_RD1
PRG1_RGMII1_RD2
PRG1_RGMII1_RD3
PRG1_RGMII1_TD0
PRG1_RGMII1_TD1
PRG1_RGMII1_TD2
PRG1_RGMII1_TD3
PRG1_RGMII2_RD0
PRG1_RGMII2_RD1
PRG1_RGMII2_RD2
PRG1_RGMII2_RD3
PRG1_RGMII2_TD0
PRG1_RGMII2_TD1
PRG1_RGMII2_TD2
PRG1_RGMII2_TD3
PRG1_UART0_CTSn
PRG1_UART0_RTSn
PRG1_UART0_RXD
PRG1_UART0_TXD
PRU_ICSSG RGMII Transmit Clock
PRU_ICSSG RGMII Transmit Control
PRU_ICSSG RGMII Receive Clock
PRU_ICSSG RGMII Receive Control
PRU_ICSSG RGMII Transmit Clock
PRU_ICSSG RGMII Transmit Control
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG UART Clear to Send (active low)
PRU_ICSSG UART Request to Send (active low)
PRU_ICSSG UART Receive Data
PRU_ICSSG UART Transmit Data
IO
O
I
AE24
AC24
AE23
AH24
AJ26
AJ27
AC23
AG22
AF22
AJ23
AF24
AJ24
AG24
AD24
AE22
AG23
AF23
AD23
AJ25
AH25
AG25
AH26
AG20
AD21
AF21
AB23
I
IO
O
I
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
I
O
I
O
6.3.24 MCASP
6.3.24.1 MAIN Domain
Table 6-95. MCASP0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCASP0_ACLKR
MCASP0_ACLKX
MCASP0_AFSR
MCASP0_AFSX
MCASP0_AXR0
MCASP0_AXR1
MCASP0_AXR2
MCASP0_AXR3
MCASP0_AXR4
MCASP0_AXR5
MCASP0_AXR6
MCASP0_AXR7
MCASP0_AXR8
MCASP Receive Bit Clock
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AE27
AB26
AD26
AB25
AF28
AE28
AD25
AC29
AE26
AC28
AC27
AJ28
AH27
MCASP Transmit Bit Clock
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
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Table 6-95. MCASP0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
MCASP0_AXR9
DESCRIPTION [2]
BALL [4]
[3]
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
IO
IO
IO
IO
IO
IO
IO
AH29
AG28
AG27
AH28
AB24
AB29
AB28
MCASP0_AXR10
MCASP0_AXR11
MCASP0_AXR12
MCASP0_AXR13
MCASP0_AXR14
MCASP0_AXR15
Table 6-96. MCASP1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCASP1_ACLKR
MCASP1_ACLKX
MCASP1_AFSR
MCASP1_AFSX
MCASP1_AXR0
MCASP1_AXR1
MCASP1_AXR2
MCASP1_AXR3
MCASP1_AXR4
MCASP1_AXR5
MCASP1_AXR6
MCASP1_AXR7
MCASP1_AXR8
MCASP1_AXR9
MCASP1_AXR10
MCASP1_AXR11
MCASP Receive Bit Clock
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AD27
AB27
AC25
AA28
AE29
AD28
AD29
AC26
AA24
Y24
MCASP Transmit Bit Clock
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
AA25
AG26
AF27
AF26
AD27
AC25
Table 6-97. MCASP2 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCASP2_ACLKR
MCASP2_ACLKX
MCASP2_AFSR
MCASP2_AFSX
MCASP2_AXR0
MCASP2_AXR1
MCASP2_AXR2
MCASP2_AXR3
MCASP2_AXR4
MCASP2_AXR5
MCASP Receive Bit Clock
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AA27
AA29
Y26
MCASP Transmit Bit Clock
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
AA26
AE25
AF29
AG29
Y25
Y26
AA27
Table 6-98. MCASP3 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCASP3_ACLKR
MCASP3_ACLKX
MCASP Receive Bit Clock
MCASP Transmit Bit Clock
IO
IO
AF23
AG20
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Table 6-98. MCASP3 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
MCASP Receive Frame Sync
BALL [4]
[3]
MCASP3_AFSR
MCASP3_AFSX
MCASP3_AXR0
MCASP3_AXR1
MCASP3_AXR2
MCASP3_AXR3
IO
IO
IO
IO
IO
IO
AD23
AD21
AD20
AE20
AJ20
AJ21
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
Table 6-99. MCASP4 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCASP4_ACLKR
MCASP4_ACLKX
MCASP4_AFSR
MCASP4_AFSX
MCASP4_AXR0
MCASP4_AXR1
MCASP4_AXR2
MCASP4_AXR3
MCASP Receive Bit Clock
IO
IO
IO
IO
IO
IO
IO
IO
AG25
AE21
AH26
AH21
AG21
AC21
Y23
MCASP Transmit Bit Clock
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
AF21
Table 6-100. MCASP5 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCASP5_ACLKR
MCASP5_ACLKX
MCASP5_AFSR
MCASP5_AFSX
MCASP5_AXR0
MCASP5_AXR1
MCASP5_AXR2
MCASP5_AXR3
MCASP Receive Bit Clock
IO
IO
IO
IO
IO
IO
IO
IO
AD19
AB23
AD18
AC22
AJ22
AH22
AD19
AD18
MCASP Transmit Bit Clock
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
Table 6-101. MCASP6 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCASP6_ACLKR
MCASP6_ACLKX
MCASP6_AFSR
MCASP6_AFSX
MCASP6_AXR0
MCASP6_AXR1
MCASP6_AXR2
MCASP6_AXR3
MCASP Receive Bit Clock
IO
IO
IO
IO
IO
IO
IO
IO
AH23
AC23
AD22
AG22
AF22
AJ23
AH23
AD22
MCASP Transmit Bit Clock
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
Table 6-102. MCASP7 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCASP7_ACLKR
MCASP7_ACLKX
MCASP Receive Bit Clock
MCASP Transmit Bit Clock
IO
IO
AC24
AF24
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Table 6-102. MCASP7 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
MCASP7_AFSR
DESCRIPTION [2]
MCASP Receive Frame Sync
BALL [4]
[3]
IO
IO
IO
IO
IO
IO
AE24
AJ24
AG24
AD24
AC24
AE24
MCASP7_AFSX
MCASP7_AXR0
MCASP7_AXR1
MCASP7_AXR2
MCASP7_AXR3
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
Table 6-103. MCASP8 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCASP8_ACLKR
MCASP8_ACLKX
MCASP8_AFSR
MCASP8_AFSX
MCASP8_AXR0
MCASP8_AXR1
MCASP8_AXR2
MCASP8_AXR3
MCASP Receive Bit Clock
IO
IO
IO
IO
IO
IO
IO
IO
AH24
AE22
AE23
AG23
AF23
AD23
AH24
AE23
MCASP Transmit Bit Clock
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
Table 6-104. MCASP9 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCASP9_ACLKR
MCASP9_ACLKX
MCASP9_AFSR
MCASP9_AFSX
MCASP9_AXR0
MCASP9_AXR1
MCASP9_AXR2
MCASP9_AXR3
MCASP Receive Bit Clock
IO
IO
IO
IO
IO
IO
IO
IO
AJ27
AJ25
AJ26
AH25
AG25
AH26
AJ27
AJ26
MCASP Transmit Bit Clock
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
Table 6-105. MCASP10 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
MCASP10_ACLKR
MCASP10_ACLKX
MCASP10_AFSR
MCASP10_AFSX
MCASP10_AXR0
MCASP10_AXR1
MCASP10_AXR2
MCASP10_AXR3
MCASP10_AXR4
MCASP10_AXR5
MCASP10_AXR6
MCASP10_AXR7
MCASP Receive Bit Clock
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Y28
U23
V23
U26
V28
V29
U29
U25
V25
W27
W29
W26
MCASP Transmit Bit Clock
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
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Table 6-106. MCASP11 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
MCASP Receive Bit Clock
BALL [4]
[3]
MCASP11_ACLKR
MCASP11_ACLKX
MCASP11_AFSR
MCASP11_AFSX
MCASP11_AXR0
MCASP11_AXR1
MCASP11_AXR2
MCASP11_AXR3
MCASP11_AXR4
MCASP11_AXR5
MCASP11_AXR6
MCASP11_AXR7
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
W23
V27
W28
U28
U27
U24
R23
T23
Y29
Y27
W24
W25
MCASP Transmit Bit Clock
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
6.3.25 DSS
6.3.25.1 MAIN Domain
Table 6-107. DSS0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
DSS_FSYNC0
DSS_FSYNC1
DSS_FSYNC2
DSS_FSYNC3
VOUT0_DE
Video Output Frame Sync 0
Video Output Frame Sync 1
Video Output Frame Sync 2
Video Output Frame Sync 3
Video Output Data Enable
Video Output External Pixel Clock Input
Video Output Horizontal Sync
Video Output Pixel Clock Output
Video Output Vertical Sync
Video Output Data 0
O
O
O
O
O
I
AH27, Y26
AD19, AH28
AA27, AH29
AG27, Y24
AC22
VOUT0_EXTPCLKIN
VOUT0_HSYNC
VOUT0_PCLK
VOUT0_VSYNC
VOUT0_DATA0
VOUT0_DATA1
VOUT0_DATA2
VOUT0_DATA3
VOUT0_DATA4
VOUT0_DATA5
VOUT0_DATA6
VOUT0_DATA7
VOUT0_DATA8
VOUT0_DATA9
VOUT0_DATA10
VOUT0_DATA11
VOUT0_DATA12
VOUT0_DATA13
VOUT0_DATA14
VOUT0_DATA15
VOUT0_DATA16
VOUT0_DATA17
AH21
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
AJ26
AH22
AJ22
AE22
Video Output Data 1
AG23
Video Output Data 2
AF23
Video Output Data 3
AD23
Video Output Data 4
AH24
Video Output Data 5
AG21
Video Output Data 6
AE23
Video Output Data 7
AC21
Video Output Data 8
Y23
Video Output Data 9
AF21
Video Output Data 10
Video Output Data 11
AB23
AJ25
Video Output Data 12
Video Output Data 13
Video Output Data 14
Video Output Data 15
Video Output Data 16
Video Output Data 17
AH25
AG25
AH26
AJ27
AF24
AJ24
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Table 6-107. DSS0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
VOUT0_DATA18
DESCRIPTION [2]
Video Output Data 18
BALL [4]
[3]
O
O
O
O
O
O
O
O
O
O
O
O
O
I
AG24
AD24
AC24
AE24
AJ20
AG20
AC22
AJ26
AJ22
AC22
AJ26
AJ22
W26
W24
W27
W29
V25
VOUT0_DATA19
VOUT0_DATA20
VOUT0_DATA21
VOUT0_DATA22
VOUT0_DATA23
VOUT0_VP0_DE
VOUT0_VP0_HSYNC
VOUT0_VP0_VSYNC
VOUT0_VP2_DE
VOUT0_VP2_HSYNC
VOUT0_VP2_VSYNC
VOUT1_DE
Video Output Data 19
Video Output Data 20
Video Output Data 21
Video Output Data 22
Video Output Data 23
Video Output Data Enable
Video Output Horizontal Sync
Video Output Vertical Sync
Video Output Data Enable
Video Output Horizontal Sync
Video Output Vertical Sync
Video Output Data Enable
Video Output External Pixel Clock Input
Video Output Horizontal Sync
Video Output Pixel Clock Output
Video Output Vertical Sync
Video Output Data 0
VOUT1_EXTPCLKIN
VOUT1_HSYNC
VOUT1_PCLK
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
VOUT1_VSYNC
VOUT1_DATA0
U23
VOUT1_DATA1
Video Output Data 1
U26
VOUT1_DATA2
Video Output Data 2
V28
VOUT1_DATA3
Video Output Data 3
V29
VOUT1_DATA4
Video Output Data 4
V27
VOUT1_DATA5
Video Output Data 5
U28
VOUT1_DATA6
Video Output Data 6
U29
VOUT1_DATA7
Video Output Data 7
U25
VOUT1_DATA8
Video Output Data 8
U27
VOUT1_DATA9
Video Output Data 9
U24
VOUT1_DATA10
VOUT1_DATA11
VOUT1_DATA12
VOUT1_DATA13
VOUT1_DATA14
VOUT1_DATA15
VOUT1_VP0_DE
VOUT1_VP0_HSYNC
VOUT1_VP0_VSYNC
Video Output Data 10
R23
Video Output Data 11
T23
Video Output Data 12
Y28
Video Output Data 13
V23
Video Output Data 14
W23
W28
W26
W27
V25
Video Output Data 15
Video Output Data Enable
Video Output Horizontal Sync
Video Output Vertical Sync
6.3.26 DP
6.3.26.1 MAIN Domain
Note
DP0_TX functionality is available on the SERDES pins. For more information, refer to Section 6.3.16,
SERDES.
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Table 6-108. DP0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
DP0_AUXN
DP0_AUXP
DP0_HPD
Display port differential auxiliary data (negative)
Display port differential auxiliary data (positive)
Display Port Hot Plugged Display Detect
IO
IO
I
G6
F7
W2, Y4
6.3.27 Camera Streaming Interface Receiver (CSI_RX_IF) Subsystem
6.3.27.1 MAIN Domain
Table 6-109. CSI0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] (2)
CSI0_RXCLKN
DESCRIPTION [2]
BALL [4]
[3]
CSI Differential Receive Clock Input (negative)
CSI Differential Receive Clock Input (positive)
I
I
B20
A21
CSI0_RXCLKP
CSI pin connected to external resistor for on-chip resistor
calibration
CSI0_RXRCALIB(1)
A
F16
CSI0_RXN0
CSI0_RXP0
CSI0_RXN1
CSI0_RXP1
CSI0_RXN2
CSI0_RXP2
CSI0_RXN3
CSI0_RXP3
CSI Differential Receive Input (negative)
CSI Differential Receive Input (positive)
CSI Differential Receive Input (negative)
CSI Differential Receive Input (positive)
CSI Differential Receive Input (negative)
CSI Differential Receive Input (positive)
CSI Differential Receive Input (negative)
CSI Differential Receive Input (positive)
I
I
I
I
I
I
I
I
B19
A20
D18
C19
D17
C18
E16
E17
(1) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
(2) CSI TX functionally is available on the DSI pins. For more information, refer to Section 6.3.28, DSI_TX.
Table 6-110. CSI1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
CSI1_RXCLKN
DESCRIPTION [2]
BALL [4]
[3]
CSI Differential Receive Clock Input (negative)
CSI Differential Receive Clock Input (positive)
I
I
B17
A18
CSI1_RXCLKP
CSI pin connected to external resistor for on-chip resistor
calibration
CSI1_RXRCALIB(1)
A
F15
CSI1_RXN0
CSI1_RXP0
CSI1_RXN1
CSI1_RXP1
CSI1_RXN2
CSI1_RXP2
CSI1_RXN3
CSI1_RXP3
CSI Differential Receive Input (negative)
CSI Differential Receive Input (positive)
CSI Differential Receive Input (negative)
CSI Differential Receive Input (positive)
CSI Differential Receive Input (negative)
CSI Differential Receive Input (positive)
CSI Differential Receive Input (negative)
CSI Differential Receive Input (positive)
I
I
I
I
I
I
I
I
B16
A17
D15
C16
D14
C15
E13
E14
(1) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
6.3.28 DSI_TX
6.3.28.1 MAIN Domain
Table 6-111. DSI_TX0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] (1)
DSI_TXCLKN
DESCRIPTION [2]
BALL [4]
[3]
DSI Differential Transmit Clock Output (positive)
O
E10
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Table 6-111. DSI_TX0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1] (1)
DSI_TXCLKP
DESCRIPTION [2]
BALL [4]
[3]
DSI Differential Transmit Clock Output (negative)
DSI Differential Transmit Output (negative)
DSI Differential Transmit Output (positive)
DSI Differential Transmit Output (negative)
DSI Differential Transmit Output (positive)
DSI Differential Transmit Output (negative)
DSI Differential Transmit Output (positive)
DSI Differential Transmit Output (negative)
DSI Differential Transmit Output (positive)
O
IO
IO
O
O
O
O
O
O
E11
D11
C12
D12
C13
B13
A14
B14
A15
DSI_TXN0
DSI_TXP0
DSI_TXN1
DSI_TXP1
DSI_TXN2
DSI_TXP2
DSI_TXN3
DSI_TXP3
DSI pin connected to external resistor for on-chip resistor
calibration
DSI_TXRCALIB(2)
A
F12
(1) The functionality of these pins is controlled by CTRLMMR_DPHY_TX0_CTRL[1:0] LANE_FUNC_SEL. 0x0 = DSI PPI, 0x1 = CSI0 TX.
(2) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.
6.3.29 VPFE
6.3.29.1 MAIN Domain
Table 6-112. VPFE0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
VPFE0_FIELD
DESCRIPTION [2]
Video Input Field Indicator
BALL [4]
[3]
I
AG23
AE22
AH21
AF23
AD23
AF24
AJ24
AG24
AD24
AC24
AE24
AJ21
AE21
AG25
AJ27
AC22
AD19
AD18
AH24
AE23
AC21
VPFE0_HD
Video Input Horizontal Sync
Video Input Pixel Clock
Video Input Vertical Sync
Video Input Write Enable
Video Input Data
I
VPFE0_PCLK
VPFE0_VD
I
I
VPFE0_WEN
I
VPFE0_DATA0
VPFE0_DATA1
VPFE0_DATA2
VPFE0_DATA3
VPFE0_DATA4
VPFE0_DATA5
VPFE0_DATA6
VPFE0_DATA7
VPFE0_DATA8
VPFE0_DATA9
VPFE0_DATA10
VPFE0_DATA11
VPFE0_DATA12
VPFE0_DATA13
VPFE0_DATA14
VPFE0_DATA15
I
Video Input Data
I
Video Input Data
I
Video Input Data
I
Video Input Data
I
Video Input Data
I
Video Input Data
I
Video Input Data
I
Video Input Data
I
Video Input Data
I
Video Input Data
I
Video Input Data
I
Video Input Data
I
Video Input Data
I
Video Input Data
I
Video Input Data
I
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6.3.30 DMTIMER
6.3.30.1 MAIN Domain
Table 6-113. DMTIMER Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
TIMER_IO0
DESCRIPTION [2]
BALL [4]
P24, V6
[3]
Timer Inputs and Outputs (not tied to single timer
instance)
IO
IO
IO
IO
IO
IO
IO
IO
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO1
R24, V5
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO2
AD23, P23
AH24, R28
AG21, T27
AE23, T24
AC2, T26
AB1, T25
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO3
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO4
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO5
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO6
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO7
6.3.30.2 MCU Domain
Table 6-114. DMTIMER Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
MCU_TIMER_IO0
MCU_TIMER_IO1
MCU_TIMER_IO2
MCU_TIMER_IO3
MCU_TIMER_IO4
MCU_TIMER_IO5
MCU_TIMER_IO6
MCU_TIMER_IO7
MCU_TIMER_IO8
MCU_TIMER_IO9
DESCRIPTION [2]
BALL [4]
E22, E28
E25, H27
A28
[3]
Timer Inputs and Outputs (not tied to single timer
instance)
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Timer Inputs and Outputs (not tied to single timer
instance)
Timer Inputs and Outputs (not tied to single timer
instance)
Timer Inputs and Outputs (not tied to single timer
instance)
A27
Timer Inputs and Outputs (not tied to single timer
instance)
A25
Timer Inputs and Outputs (not tied to single timer
instance)
D24
Timer Inputs and Outputs (not tied to single timer
instance)
G27
Timer Inputs and Outputs (not tied to single timer
instance)
G26
Timer Inputs and Outputs (not tied to single timer
instance)
D26
Timer Inputs and Outputs (not tied to single timer
instance)
D25
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6.3.31 Emulation and Debug
6.3.31.1 MAIN Domain
Table 6-115. JTAG Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
EMU0
EMU1
TCK
Emulation Control 0
Emulation Control 1
IO
C26
B29
E29
V1
IO
JTAG Test Clock Input
JTAG Test Data Input
JTAG Test Data Output
JTAG Test Mode Select Input
JTAG Reset
I
TDI
I
TDO
OZ
V3
TMS
I
I
V2
TRSTn
F24
Table 6-116. Trace Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
TRC_CLK
Trace Clock
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
U23
U26
V28
V29
V27
U28
U29
U25
U27
U24
R23
T23
Y28
V23
W23
W28
V25
W27
W29
W26
Y29
Y27
W24
W25
V26
V24
TRC_CTL
Trace Control
Trace Data 0
Trace Data 1
Trace Data 2
Trace Data 3
Trace Data 4
Trace Data 5
Trace Data 6
Trace Data 7
Trace Data 8
Trace Data 9
Trace Data 10
Trace Data 11
Trace Data 12
Trace Data 13
Trace Data 14
Trace Data 15
Trace Data 16
Trace Data 17
Trace Data 18
Trace Data 19
Trace Data 20
Trace Data 21
Trace Data 22
Trace Data 23
TRC_DATA0
TRC_DATA1
TRC_DATA2
TRC_DATA3
TRC_DATA4
TRC_DATA5
TRC_DATA6
TRC_DATA7
TRC_DATA8
TRC_DATA9
TRC_DATA10
TRC_DATA11
TRC_DATA12
TRC_DATA13
TRC_DATA14
TRC_DATA15
TRC_DATA16
TRC_DATA17
TRC_DATA18
TRC_DATA19
TRC_DATA20
TRC_DATA21
TRC_DATA22
TRC_DATA23
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6.3.32 System and Miscellaneous
6.3.32.1 Boot Mode Configuration
6.3.32.1.1 MAIN Domain
Note
BOOTMODE pins are latched on the rising edge of PORz_OUT.
Table 6-117. Sysboot Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
BOOTMODE0
DESCRIPTION [2]
BALL [4]
[3]
Bootmode pin 0
Bootmode pin 1
Bootmode pin 2
Bootmode pin 3
Bootmode pin 4
Bootmode pin 5
Bootmode pin 6
Bootmode pin 7
I
I
I
I
I
I
I
I
AD20
AC22
AC29
Y25
BOOTMODE1
BOOTMODE2
BOOTMODE3
BOOTMODE4
BOOTMODE5
BOOTMODE6
BOOTMODE7(1)
V6
V5
AB27
AB24
(1) These signals must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low
level.
6.3.32.1.2 MCU Domain
Note
MCU_BOOTMODE pins are latched on the rising edge of MCU_PORz_OUT.
Table 6-118. Sysboot Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
MCU_BOOTMODE00
DESCRIPTION [2]
BALL [4]
[3]
Bootmode pin 00
Bootmode pin 01
Bootmode pin 02
Bootmode pin 03
Bootmode pin 04
Bootmode pin 05
Bootmode pin 06
Bootmode pin 07
Bootmode pin 08
Bootmode pin 09
I
I
I
I
I
I
I
I
I
I
E27
E24
E28
F26
F25
F28
H29
J27
G29
H28
MCU_BOOTMODE01
MCU_BOOTMODE02
MCU_BOOTMODE03
MCU_BOOTMODE04
MCU_BOOTMODE05
MCU_BOOTMODE06
MCU_BOOTMODE07
MCU_BOOTMODE08
MCU_BOOTMODE09
6.3.32.2 Clock
6.3.32.2.1 MAIN Domain
Table 6-119. Clock1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
OSC1_XI
High frequency oscillator input
High frequency oscillator output
I
P29
P27
OSC1_XO
O
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6.3.32.2.2 WKUP Domain
Table 6-120. Clock0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
WKUP_LFOSC0_XI
DESCRIPTION [2]
BALL [4]
[3]
Low frequency (32.768 KHz) oscillator input
Low frequency (32.768 KHz) oscillator output
High frequency oscillator input
I
N28
N26
M29
M27
WKUP_LFOSC0_XO
WKUP_OSC0_XI
WKUP_OSC0_XO
O
I
High frequency oscillator output
O
6.3.32.3 System
6.3.32.3.1 MAIN Domain
Table 6-121. System0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
External clock routed to ATL or MCASP as one of the
selectable input clock sources, or as a output clock
output for ATL or MCASP
AUDIO_EXT_REFCLK0
IO
IO
IO
AD22
External clock routed to ATL or MCASP as one of the
selectable input clock sources, or as a output clock
output for ATL or MCASP
AUDIO_EXT_REFCLK1
AUDIO_EXT_REFCLK2
AE20
W26
External clock routed to ATL or MCASP as one of the
selectable input clock sources, or as a output clock
output for ATL or MCASP
External clock routed to ATL or MCASP as one of the
selectable input clock sources, or as a output clock
output for ATL or MCASP
AUDIO_EXT_REFCLK3
EXTINTn
IO
I
W25
External Interrupt
AC18
External clock input to MAIN domain, routed to Timer
clock muxes as one of the selectable input clock
sources for Timer/WDT modules, or as reference clock
to MAIN_PLL2 (PER1 PLL)
EXT_REFCLK1
I
U3
Observation clock output for test and debug purposes
only
OBSCLK0
OBSCLK1
OBSCLK2
O
O
O
V5
Observation clock output for test and debug purposes
only
AB24
AD21
Observation clock output for test and debug purposes
only
PORz_OUT
MAIN domain POR status output
O
O
U1
T6
U4
RESETSTATz
MAIN domain warm reset status output
Error signal output from MAIN domain ESM
SOC_SAFETY_ERRORn
IO
SYSCLK0 output from MAIN PLL controller (divided by 6)
for test and debug purposes only
SYSCLKOUT0
O
A
A
V6
Voltage Monitor for System supply, requires External
Resistor divider
VMON_ER_VSYS
VMON_IR_VEXT
M26
V19
Voltage Monitor for External 1.8V supply, uses Internal
Resistor divider
6.3.32.3.2 WKUP Domain
Table 6-122. System0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
Reference clock output for Ethernet PHYs (50MHz or
25MHz)
MCU_CLKOUT0
OZ
I
H27
H26
MCU_EXT_REFCLK0
External system clock input
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Table 6-122. System0 Signal Descriptions (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
Observation clock output for test and debug purposes
only
MCU_OBSCLK0
O
H27
MCU_PORz
MCU Domain cold reset
I
O
O
I
H23
B28
C27
D28
D27
MCU_PORz_OUT
MCU_RESETSTATz
MCU_RESETz
MCU Domain POR status output
MCU Domain warm reset status output
MCU Domain warm reset
MCU_SAFETY_ERRORn
Error signal output from MCU Domain ESM
IO
MCU Domain system clock output for test and debug
purposes only
MCU_SYSCLKOUT0
O
H26
PORz
MAIN Domain cold reset
I
I
J24
RESET_REQz
MAIN Domain external warm reset request input
C28
Pin name retained for legacy purposes, not used for
power enable
PMIC_POWER_EN0
PMIC_POWER_EN1
NA
O
E26
G23
Power enable output for MAIN Domain supplies
6.3.32.4 EFUSE
Table 6-123. EFUSE Signal Description
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
VPP_CORE(1)
VPP_MCU(1)
Programming voltage for MAIN Domain efuses
Programming voltage for MCU Domain efuses
PWR
PWR
AB11
F17
(1) This signal is valid only for High-Security devices. For more details, see Section 7.8, VPP Specification for One-Time Programmable
(OTP) eFUSEs. For General-Purpose devices do not connect any signal, test point, or board trace to this signal.
6.3.33 Power Supply
Note
All power balls must be supplied with the voltages specified in Section 7.4, Recommended Operating
Conditions, unless otherwise specified in Section 6.3, Signal Descriptions.
Table 6-124. Power Supply Signal Description
PIN TYPE
SIGNAL NAME [1]
CAP_VDDS0(1)
DESCRIPTION [2]
External capacitor connection for
BALL [4]
[3]
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
PWR
PWR
PWR
PWR
U7
CAP_VDDS0_MCU(1)
CAP_VDDS1(1)
CAP_VDDS1_MCU(1)
CAP_VDDS2(1)
CAP_VDDS2_MCU(1)
CAP_VDDS3(1)
CAP_VDDS4(1)
External capacitor connection for
External capacitor connection for
External capacitor connection for
External capacitor connection for
External capacitor connection for
External capacitor connection for
External capacitor connection for
External capacitor connection for
External capacitor connection for
MAIN domain RAM supply
K23
AB21
J18
Y18
J19
W21
AA22
CAP_VDDS5(1)
CAP_VDDS6(1)
R22
V22
VDDAR_CORE
VDDAR_CPU
L14, V13, V16, W19
L11, W12
K19, T19
H17
CPU RAM supply
VDDAR_MCU
MCUSS RAM supply
VDDA_0P8_CSIRX
CSIRX analog supply low
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Table 6-124. Power Supply Signal Description (continued)
PIN TYPE
SIGNAL NAME [1]
VDDA_0P8_DP
DESCRIPTION [2]
BALL [4]
[3]
Displayport SERDES analog supply low
Displayport SERDES clock supply
DSITX clock supply
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
G12, J12
G14, H13
H15
VDDA_0P8_DP_C
VDDA_0P8_DSITX
VDDA_0P8_DSITX_C
VDDA_0P8_UFS
DSITX clock supply
J16
UFS analog supply low
AB9
VDDA_0P8_USB
USB0-1 0.8 V analog supply
AA10
VDDA_0P8_SERDES0_1
VDDA_0P8_SERDES2_3
VDDA_0P8_SERDES_C0_1
VDDA_0P8_SERDES_C2_3
VDDA_1P8_CSIRX
VDDA_1P8_DP
SERDES0-1 analog supply low
SERDES2-3 analog supply low
SERDES0-1 clock supply
AA15, Y14, Y16
AA12, Y11, Y13
AB14, AB15
AB12, AB13
G16
SERDES2-3 clock supply
CSIRX analog supply high
Displayport SERDES analog supply high
DSITX analog supply high
H11
VDDA_1P8_DSITX
VDDA_1P8_UFS
J14
UFS analog supply high
AC8
VDDA_1P8_USB
USB0-1 1.8 V analog supply
AC9
VDDA_1P8_SERDES0_1
VDDA_1P8_SERDES2_3
VDDA_3P3_USB
SERDES0-1 analog supply high
SERDES2-3 analog supply high
USB0-1 3.3 V analog supply
AC14, AC15
AC11, AC12
AB10
VDDA_ADC0
ADC analog supply and high voltage reference (VREFP)
ADC analog supply and high voltage reference (VREFP)
DDR PLL analog supply
N22
VDDA_ADC1
M23
VDDA_0P8_PLL_DDR
VDDA_MCU_PLLGRP0
VDDA_MCU_TEMP
VDDA_1P8_MLB
N9
Analog supply for MCU PLL Group 0
Analog supply for temperature sensor 0 in MCU domain
MLB IO supply (6-pin interface)
Analog supply for MAIN PLL Group 0
Analog supply for MAIN PLL Group 1
Analog supply for MAIN PLL Group 2
Analog supply for MAIN PLL Group 3
Analog supply for MAIN PLL Group 4
Analog supply for MAIN PLL Group 5 (DDR)
Analog supply for MAIN PLL Group 6
MLB PLL analog supply
G18
P21
W7
VDDA_PLLGRP0
Y20
VDDA_PLLGRP1
W17
VDDA_PLLGRP2
M17
VDDA_PLLGRP3
L12
VDDA_PLLGRP4
R11
VDDA_PLLGRP5
P9
VDDA_PLLGRP6
W18
VDDA_0P8_PLL_MLB
VDDA_POR_WKUP
VDDA_TEMP0_1
W8
WKUP domain analog supply
P22
Analog supply for temperature sensor 0 and 1
Analog supply for temperature sensor 2 and 3
Oscillator supply for WKUP domain
IO supply for MAIN domain general
W15
VDDA_TEMP2_3
H9
VDDA_WKUP
H22
VDDSHV0
U8, V7
IO supply MCUSS general IO group, and MCU and MAIN
domain warm reset pins
VDDSHV0_MCU
PWR
L22, M22
AA19, AA20, AC19,
AC20
VDDSHV1
IO supply for MAIN domain IO group 1
IO supply for MCUSS IO group 1
PWR
PWR
PWR
VDDSHV1_MCU
VDDSHV2
H19, H21, J20
AA17, AB16, AB18,
AC17
IO supply for MAIN domain IO group 2
VDDSHV2_MCU
VDDSHV3
IO supply for MCUSS IO group 2
PWR
PWR
J22, K21
IO supply for MAIN domain IO group 3
V21, W22
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Table 6-124. Power Supply Signal Description (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
VDDSHV4
VDDSHV5
VDDSHV6
IO supply for MAIN domain IO group 4
IO supply for MAIN domain IO group 5
IO supply for MAIN domain IO group 6
PWR
PWR
PWR
AA21, Y22
T20, T22
U20, U22
A1, G8, J8, K7, L8,
M7, N8, P7, R8, T1
VDDS_DDR
DDR inteface power supply
PWR
VDDS_DDR_BIAS
VDDS_DDR_C
VDDS_MMC0
VDDS_OSC1
Bias supply for LPDDR4
PWR
PWR
PWR
PWR
H7, J6, R6, T7
M9
IO power for DDR Memory Clock Bit (MCB) macro
MMC0 IO supply
AA8, AB7, Y7
R21
HFOSC1 supply
J10, K11, K13, K15,
K17, K9, L10, L16,
L18, M15, N14, N16,
N18, P13, P15, P17,
R14, R16, R18, R20,
T15, T17, T9, U14,
U16, U18, V15, V17,
V20, W14
VDD_CORE
MAIN domain core supply
PWR
N10, P11, R10, R12,
U10, V11, V9, W10
VDD_CPU
CPU core supply
PWR
PWR
PWR
VDDA_0P8_DLL_MMC0
VDD_MCU
MMC0 DLL analog supply
MCUSS core supply
Y9
L20, M19, M21, N20,
P19
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Table 6-124. Power Supply Signal Description (continued)
PIN TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
BALL [4]
[3]
AA13, AC10, AC13,
AD11, AD14, AD17,
AE10, AE12, AE15,
AE16, AE19, AE7,
AF20, AF25, AF5,
AG4, AG7, AH2,
AH20, AH5, AJ4, AJ7,
B3, B6, C1, C5, D2,
D4, E1, E5, F4, G1,
G7, H4, H6, K1, K4,
L3, M1, M28, M4,
M6, N27, N29, N3,
P1, P28, P4, R3, U5
A10, A13, A16, A19,
A22, A7, AA11, AA14,
AA16, AA18, AA7,
AA9, AB17, AB19,
AB20, AB22, AB8,
AC16, AF11, AF14,
AF17, AF8, AG10,
AG13, AG16, AG19,
AH11, AH14, AH17,
AH8, AJ10, AJ13,
AJ16, AJ19, B12,
B15, B18, B21, B9,
C11, C14, C17, C20,
C8, D10, D13, D16,
D19, D7, E12, E15,
E9, F14, F8, G11,
G13, G15, G17, H10,
H12, H14, H16, H18,
H20, H8, J11, J13,
J15, J17, J21, J23,
J7, J9, K10, K12,
VSS
Ground
GND
K14, K16, K18, K20,
K22, K8, L13, L15,
L17, L19, L21, L23,
L7, L9, M10, M14,
M16, M18, M20, M8,
N15, N17, N19, N21,
N7, P10, P12, P14,
P16, P18, P20, P8,
R13, R15, R17, R19,
R7, R9, T10, T14,
T16, T18, T21, T8,
U15, U17, U19, U21,
U9, V10, V12, V14,
V18, V8, W11, W13,
W16, W20, W9, Y10,
Y12, Y15, Y17, Y19,
Y21, Y8
(1) This pin must always be connected via a 1-μF capacitor to VSS.
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6.4 Pin Multiplexing
Note
Many device pins support multiple signal functions. Some signal functions are selected via a single layer of multiplexers associated with pins.
Other signal functions are selected via two or more layers of multiplexers, where one layer is associated with the pins and other layers are
associated with peripheral logic functions.
Table 6-125, Pin Multiplexing only describes signal multiplexing at the pins. For more information, related to signal multiplexing at the pins,
see Pad Configuration Registers section in Device Configuration chapter in the device TRM. Refer to the respective peripheral chapter in the
device TRM for information associated with peripheral signal multiplexing.
Note
When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided.
Note
Table 6-125, Pin Multiplexing does not include SerDes signal functions. For more information, refer to the Serializer/Deserializer (SerDes)
chapter in the device TRM.
Note
Table 6-125, Pin Multiplexing does not include DPHY_TX signal functions. For more information, refer to the Shared D-PHY Transmitter
(DPHY_TX) chapter in the device TRM.
For more information on the I/O cell configurations, see Pad Configuration Registers section in Device Configuration chapter in the device TRM.
Table 6-125. Pin Multiplexing
BALL
NUMB
ER
MUXMODE[14:0] SETTINGS
REGISTER
NAME
ADDRESS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x00011C2 PADCONFIG165 AD1
94
MLB0_ML
BSP
GPIO1_30
0x00011C2 PADCONFIG167 AC3
9C
MLB0_ML
BDP
GPIO1_32
GPIO1_29
GPIO1_31
GPIO1_33
GPIO1_34
0x00011C2 PADCONFIG164 U6
90
USB0_DR USB1_DR
VVBUS
VVBUS
0x00011C2 PADCONFIG166 AC1
98
MLB0_ML
BSN
0x00011C2 PADCONFIG168 AD3
A0
MLB0_ML
BDN
0x00011C2 PADCONFIG169 AD2
A4
MLB0_ML
BCP
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Table 6-125. Pin Multiplexing (continued)
BALL
MUXMODE[14:0] SETTINGS
REGISTER
NAME
ADDRESS
NUMB
ER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x00011C2 PADCONFIG170 AE2
A8
MLB0_ML
BCN
GPIO1_35
0x00011C0 PADCONFIG0
00
AC18
AC23
AG22
AF22
AJ23
AH23
EXTINTn
GPIO0_0
GPIO0_1
GPIO0_2
GPIO0_3
GPIO0_4
GPIO0_5
0x00011C0 PADCONFIG1
04
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII1_R RMII1_RX
U0_GPO0 U0_GPI0 MII1_RD0 M3_A0 D0 D0
GPMC0_B RGMII7_R
E1n D0
MCASP6_
ACLKX
UART0_R
XD
0x00011C0 PADCONFIG2
08
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII1_R RMII1_RX
U0_GPO1 U0_GPI1 MII1_RD1 M3_B0 D1 D1
GPMC0_W RGMII7_R
AIT0 D1
MCASP6_
AFSX
UART0_TX
D
0x00011C0 PADCONFIG3
0C
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII1_R RMII1_CR
U0_GPO2 U0_GPI2 MII1_RD2 M2_A0 D2 S_DV
GPMC0_W RGMII7_R
AIT1 D2
MCASP6_
AXR0
UART1_R
XD
0x00011C0 PADCONFIG4
10
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII1_R RMII1_RX
U0_GPO3 U0_GPI3 MII1_RD3 M3_A2 D3 _ER
GPMC0_DI RGMII7_R
D3
MCASP6_
AXR1
UART1_TX
D
R
0x00011C0 PADCONFIG5
14
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII1_R RMII1_TX
U0_GPO4 U0_GPI4
GPMC0_C RGMII7_R
MCASP6_ MCASP6_ UART2_R
MII1_RX_ M2_B0
CTL
X_CTL
D0
Sn2
X_CTL
AXR2
ACLKR
XD
0x00011C0 PADCONFIG6
18
AD20
AD22
PRG1_PR PRG1_PR
U0_GPO5 U0_GPI5
PRG1_PW
M3_B2
RMII1_TX_
EN
GPIO0_6
GPMC0_W
En
MCASP3_
AXR0
BOOTMO
DE0
0x00011C0 PADCONFIG7
1C
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII1_R RMII1_TX AUDIO_EX GPIO0_7
U0_GPO6 U0_GPI6
GPMC0_C RGMII7_R
Sn3
MCASP6_ MCASP6_ UART2_TX
AXR3
MII1_RXC M3_A1
XC
D1
T_REFCLK
0
XC
AFSR
D
0x00011C0 PADCONFIG8
20
AE20
PRG1_PR PRG1_PR PRG1_IEP PRG1_PW
AUDIO_EX MCAN4_T GPIO0_8
MCASP3_
AXR1
U0_GPO7 U0_GPI7
0_EDC_LA M3_B1
TCH_IN1
T_REFCLK
1
X
0x00011C0 PADCONFIG9
24
AJ20
PRG1_PR PRG1_PR
U0_GPO8 U0_GPI8
PRG1_PW
M2_A1
RMII5_RX MCAN4_R GPIO0_9
GPMC0_O
En_REn
VOUT0_D
ATA22
MCASP3_
AXR2
D0
X
0x00011C0 PADCONFIG10
28
AG20
PRG1_PR PRG1_PR PRG1_UA PRG1_PW SPI6_CS1 RMII5_RX
U0_GPO9 U0_GPI9 RT0_CTSn M3_TZ_IN D1
GPIO0_10 GPMC0_A PRG1_IEP VOUT0_D
MCASP3_
ACLKX
DVn_ALE 0_EDIO_D ATA23
ATA_IN_O
UT28
0x00011C0 PADCONFIG11
2C
AD21
PRG1_PR PRG1_PR PRG1_UA PRG1_PW SPI6_CS2 RMII5_CR
GPIO0_11 GPMC0_B PRG1_IEP OBSCLK2
MCASP3_
AFSX
U0_GPO1 U0_GPI10 RT0_RTSn M2_B1
0
S_DV
E0n_CLE
0_EDIO_D
ATA_IN_O
UT29
0x00011C0 PADCONFIG12
30
AF24
AJ24
AG24
AD24
AC24
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII1_T
MCAN4_T GPIO0_12
X
RGMII7_T VOUT0_D VPFE0_DA MCASP7_
D0 ATA16 TA0 ACLKX
U0_GPO11 U0_GPI11 MII1_TD0
M3_TZ_O D0
UT
0x00011C0 PADCONFIG13
34
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII1_T
MCAN4_R GPIO0_13
X
RGMII7_T VOUT0_D VPFE0_DA MCASP7_
D1 ATA17 TA1 AFSX
U0_GPO1 U0_GPI12 MII1_TD1
2
M0_A0
D1
0x00011C0 PADCONFIG14
38
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII1_T
MCAN5_T GPIO0_14
X
RGMII7_T VOUT0_D VPFE0_DA MCASP7_
D2 ATA18 TA2 AXR0
U0_GPO1 U0_GPI13 MII1_TD2
3
M0_B0
D2
0x00011C0 PADCONFIG15
3C
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII1_T
MCAN5_R GPIO0_15
X
RGMII7_T VOUT0_D VPFE0_DA MCASP7_
D3 ATA19 TA3 AXR1
U0_GPO1 U0_GPI14 MII1_TD3
4
M0_A1
D3
0x00011C0 PADCONFIG16
40
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII1_T
U0_GPO1 U0_GPI15 MII1_TX_C M0_B1 X_CTL
TL
MCAN6_T GPIO0_16
X
RGMII7_T VOUT0_D VPFE0_DA MCASP7_ MCASP7_
X_CTL ATA20 TA4 AXR2 ACLKR
5
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Table 6-125. Pin Multiplexing (continued)
BALL
NUMB
ER
MUXMODE[14:0] SETTINGS
REGISTER
NAME
ADDRESS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x00011C0 PADCONFIG17
44
AE24
AJ21
AE21
AH21
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII1_T
MCAN6_R GPIO0_17
X
RGMII7_T VOUT0_D VPFE0_DA MCASP7_ MCASP7_
XC ATA21 TA5 AXR3 AFSR
U0_GPO1 U0_GPI16 MII1_TXC M0_A2
6
XC
0x00011C0 PADCONFIG19
4C
PRG1_PR PRG1_PR PRG1_IEP PRG1_PW
U0_GPO1 U0_GPI17 0_EDC_SY M0_B2
RMII5_TX MCAN5_T GPIO0_18
D1
VPFE0_DA MCASP3_
TA6 AXR3
X
7
NC_OUT1
0x00011C0 PADCONFIG20
50
PRG1_PR PRG1_PR PRG1_IEP PRG1_PW
U0_GPO1 U0_GPI18 0_EDC_LA M0_TZ_IN
RMII5_RX MCAN5_R GPIO0_19
_ER
VPFE0_DA MCASP4_
TA7 ACLKX
X
8
TCH_IN0
0x00011C0 PADCONFIG21
54
PRG1_PR PRG1_PR PRG1_IEP PRG1_PW
U0_GPO1 U0_GPI19 0_EDC_SY M0_TZ_O
RMII5_TX MCAN6_T GPIO0_20
D0
VOUT0_E VPFE0_PC MCASP4_
XTPCLKIN LK AFSX
X
9
NC_OUT0 UT
0x00011C0 PADCONFIG22
58
AE22
AG23
AF23
AD23
AH24
PRG1_PR PRG1_PR PRG1_RG
U1_GPO0 U1_GPI0 MII2_RD0
RGMII2_R RMII2_RX
D0 D0
GPIO0_21 RGMII8_R
D0
VOUT0_D VPFE0_H MCASP8_
ATA0 ACLKX
D
0x00011C0 PADCONFIG23
5C
PRG1_PR PRG1_PR PRG1_RG
U1_GPO1 U1_GPI1 MII2_RD1
RGMII2_R RMII2_RX
D1 D1
GPIO0_22 RGMII8_R
D1
VOUT0_D VPFE0_FI MCASP8_
ATA1 ELD AFSX
0x00011C0 PADCONFIG24
60
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII2_R RMII2_CR
U1_GPO2 U1_GPI2 MII2_RD2 M2_A2 D2 S_DV
GPIO0_23 RGMII8_R
D2
VOUT0_D VPFE0_VD MCASP8_ MCASP3_
ATA2 AXR0 ACLKR
0x00011C0 PADCONFIG25
64
PRG1_PR PRG1_PR PRG1_RG
U1_GPO3 U1_GPI3 MII2_RD3 D3 _ER
RGMII2_R RMII2_RX
GPIO0_24 RGMII8_R EQEP1_A VOUT0_D VPFE0_W MCASP8_ MCASP3_ TIMER_IO
D3 ATA3 EN AXR1 AFSR
2
0x00011C0 PADCONFIG26
68
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII2_R RMII2_TX
GPIO0_25 RGMII8_R EQEP1_B VOUT0_D VPFE0_DA MCASP8_ MCASP8_ TIMER_IO
U1_GPO4 U1_GPI4
MII2_RX_ M2_B2
CTL
X_CTL
D0
X_CTL
ATA4
TA13
AXR2
ACLKR
3
0x00011C0 PADCONFIG27
6C
AG21
AE23
AC21
PRG1_PR PRG1_PR
U1_GPO5 U1_GPI5
RMII5_TX_ MCAN6_R GPIO0_26 GPMC0_W EQEP1_S VOUT0_D
MCASP4_
AXR0
TIMER_IO
4
EN
X
Pn
ATA5
0x00011C0 PADCONFIG28
70
PRG1_PR PRG1_PR PRG1_RG
U1_GPO6 U1_GPI6 MII2_RXC
RGMII2_R RMII2_TX
XC D1
GPIO0_27 RGMII8_R
XC
VOUT0_D VPFE0_DA MCASP8_ MCASP8_ TIMER_IO
ATA6
TA14
AXR3
AFSR
5
0x00011C0 PADCONFIG29
74
PRG1_PR PRG1_PR PRG1_IEP
U1_GPO7 U1_GPI7
SPI6_CS0 RMII6_RX MCAN7_T GPIO0_28
_ER
VOUT0_D VPFE0_DA MCASP4_
ATA7
UART3_TX
D
1_EDC_LA
TCH_IN1
X
TA15
AXR1
0x00011C0 PADCONFIG30
78
Y23
PRG1_PR PRG1_PR
U1_GPO8 U1_GPI8
PRG1_PW
M2_TZ_O
UT
RMII6_RX MCAN7_R GPIO0_29 GPMC0_C
D0 Sn1
VOUT0_D
ATA8
MCASP4_
AXR2
UART3_R
XD
X
0x00011C0 PADCONFIG31
7C
AF21
PRG1_PR PRG1_PR PRG1_UA
U1_GPO9 U1_GPI9 RT0_RXD
SPI6_CS3 RMII6_RX MCAN8_T GPIO0_30 GPMC0_C PRG1_IEP VOUT0_D
MCASP4_
AXR3
D1
X
Sn0
0_EDIO_D ATA9
ATA_IN_O
UT30
0x00011C0 PADCONFIG32
80
AB23
PRG1_PR PRG1_PR PRG1_UA PRG1_PW
U1_GPO1 U1_GPI10 RT0_TXD M2_TZ_IN
0
RMII6_CR MCAN8_R GPIO0_31 GPMC0_C PRG1_IEP VOUT0_D GPMC0_F MCASP5_
S_DV
X
LKOUT
0_EDIO_D ATA10
ATA_IN_O
CLK_MUX ACLKX
UT31
0x00011C0 PADCONFIG33
84
AJ25
AH25
PRG1_PR PRG1_PR PRG1_RG
U1_GPO11 U1_GPI11 MII2_TD0
RGMII2_T RMII2_TX_
GPIO0_32 RGMII8_T EQEP1_I
D0
VOUT0_D
ATA11
MCASP9_
ACLKX
D0
EN
0x00011C0 PADCONFIG34
88
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII2_T
U1_GPO1 U1_GPI12 MII2_TD1
2
MCAN7_T GPIO0_33 RGMII8_T
X D1
VOUT0_D
ATA12
MCASP9_
AFSX
M1_A0
D1
0x00011C0 PADCONFIG35
8C
AG25
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII2_T
MCAN7_R GPIO0_34 RGMII8_T
X D2
VOUT0_D VPFE0_DA MCASP9_ MCASP4_
ATA13 TA8 AXR0 ACLKR
U1_GPO1 U1_GPI13 MII2_TD2
3
M1_B0
D2
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Table 6-125. Pin Multiplexing (continued)
BALL
MUXMODE[14:0] SETTINGS
REGISTER
NAME
ADDRESS
NUMB
ER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x00011C0 PADCONFIG36
90
AH26
AJ27
AJ26
AC22
AJ22
AH22
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII2_T
MCAN8_T GPIO0_35 RGMII8_T
X D3
VOUT0_D
ATA14
MCASP9_ MCASP4_
AXR1 AFSR
U1_GPO1 U1_GPI14 MII2_TD3
4
M1_A1
D3
0x00011C0 PADCONFIG37
94
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII2_T
U1_GPO1 U1_GPI15 MII2_TX_C M1_B1 X_CTL
TL
MCAN8_R GPIO0_36 RGMII8_T
X_CTL
VOUT0_D VPFE0_DA MCASP9_ MCASP9_
ATA15 TA9 AXR2 ACLKR
X
5
0x00011C0 PADCONFIG38
98
PRG1_PR PRG1_PR PRG1_RG PRG1_PW RGMII2_T
GPIO0_37 RGMII8_T VOUT0_V VOUT0_H
MCASP9_ MCASP9_ VOUT0_V
U1_GPO1 U1_GPI16 MII2_TXC M1_A2
6
XC
XC
P2_HSYN SYNC
C
AXR3
AFSR
P0_HSYN
C
0x00011C0 PADCONFIG39
9C
PRG1_PR PRG1_PR PRG1_IEP PRG1_PW SPI6_CLK RMII6_TX_ PRG1_EC GPIO0_38
VOUT0_V VOUT0_D VPFE0_DA MCASP5_
VOUT0_V BOOTMO
P0_DE
U1_GPO1 U1_GPI17 1_EDC_SY M1_B2
NC_OUT1
EN
AP0_SYN
C_OUT
P2_DE
E
TA10
AFSX
DE1
7
0x00011C0 PADCONFIG40
A0
PRG1_PR PRG1_PR PRG1_IEP PRG1_PW SPI6_D0
U1_GPO1 U1_GPI18 1_EDC_LA M1_TZ_IN
RMII6_TX PRG1_EC GPIO0_39
VOUT0_V VOUT0_V
P2_VSYN SYNC
C
MCASP5_
AXR0
VOUT0_V
P0_VSYN
C
D0
AP0_SYN
C_IN
8
TCH_IN0
0x00011C0 PADCONFIG41
A4
PRG1_PR PRG1_PR PRG1_IEP PRG1_PW SPI6_D1
U1_GPO1 U1_GPI19 1_EDC_SY M1_TZ_O
RMII6_TX PRG1_EC GPIO0_40
VOUT0_P
CLK
MCASP5_
AXR1
D1
AP0_IN_A
PWM_OUT
9
NC_OUT0 UT
0x00011C0 PADCONFIG42
A8
AD19
AD18
AF28
AE28
AE27
AD26
AD25
PRG1_MDI SPI1_CS2 I2C4_SCL
O0_MDIO
GPIO0_41
GPIO0_42
GPIO0_43
GPIO0_44
DSS_FSY VPFE0_DA MCASP5_ MCASP5_ UART3_CT
NC1 TA11 AXR2 ACLKR Sn
0x00011C0 PADCONFIG43
AC
PRG1_MDI SPI1_CS3 I2C4_SDA
O0_MDC
RMII_REF
_CLK
VPFE0_DA MCASP5_ MCASP5_ UART3_RT
TA12
AXR3
AFSR
Sn
0x00011C0 PADCONFIG44
B0
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII3_R RMII3_RX
U0_GPO0 U0_GPI0 MII1_RD0 M3_A0 D0 D1
MCASP0_
AXR0
0x00011C0 PADCONFIG45
B4
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII3_R RMII3_RX
U0_GPO1 U0_GPI1 MII1_RD1 M3_B0 D1 D0
MCASP0_
AXR1
0x00011C0 PADCONFIG46
B8
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII3_R RMII3_CR
U0_GPO2 U0_GPI2 MII1_RD2 M2_A0 D2 S_DV
GPIO0_45 UART3_R
XD
MCASP0_
ACLKR
0x00011C0 PADCONFIG47
BC
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII3_R RMII3_RX
U0_GPO3 U0_GPI3 MII1_RD3 M3_A2 D3 _ER
GPIO0_46 UART3_TX
D
MCASP0_
AFSR
0x00011C0 PADCONFIG48
C0
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII3_R RMII3_TX
GPIO0_47
MCASP0_
AXR2
U0_GPO4 U0_GPI4
MII1_RX_ M2_B0
CTL
X_CTL
D1
0x00011C0 PADCONFIG49
C4
AC29
AE26
AC28
PRG0_PR PRG0_PR
U0_GPO5 U0_GPI5
PRG0_PW
M3_B2
RMII3_TX
D0
GPIO0_48 GPMC0_A
D0
MCASP0_
AXR3
BOOTMO
DE2
0x00011C0 PADCONFIG50
C8
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII3_R RMII3_TX_
U0_GPO6 U0_GPI6 MII1_RXC M3_A1 XC EN
GPIO0_49
MCASP0_
AXR4
0x00011C0 PADCONFIG51
CC
PRG0_PR PRG0_PR PRG0_IEP PRG0_PW PRG0_EC
U0_GPO7 U0_GPI7
MCAN9_T GPIO0_50 GPMC0_A
X D1
MCASP0_
AXR5
0_EDC_LA M3_B1
TCH_IN1
AP0_SYN
C_IN
0x00011C0 PADCONFIG52
D0
AC27
AB26
PRG0_PR PRG0_PR
U0_GPO8 U0_GPI8
PRG0_PW
M2_A1
MCAN9_R GPIO0_51 GPMC0_A
D2
MCASP0_
AXR6
UART6_R
XD
X
0x00011C0 PADCONFIG53
D4
PRG0_PR PRG0_PR PRG0_UA PRG0_PW SPI3_CS1 PRG0_IEP MCAN10_ GPIO0_52 GPMC0_A
U0_GPO9 U0_GPI9
MCASP0_
ACLKX
UART6_TX
D
RT0_CTSn M3_TZ_IN
0_EDIO_D TX
ATA_IN_O
UT28
D3
0x00011C0 PADCONFIG54
D8
AB25
PRG0_PR PRG0_PR PRG0_UA PRG0_PW SPI3_CS2 PRG0_IEP MCAN10_ GPIO0_53 GPMC0_A
MCASP0_
AFSX
U0_GPO1 U0_GPI10 RT0_RTSn M2_B1
0
0_EDIO_D RX
ATA_IN_O
UT29
D4
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www.ti.com
Table 6-125. Pin Multiplexing (continued)
BALL
NUMB
ER
MUXMODE[14:0] SETTINGS
REGISTER
NAME
ADDRESS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x00011C0 PADCONFIG55
DC
AJ28
AH27
AH29
AG28
AG27
AH28
AB24
AB29
AB28
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII3_T
GPIO0_54
CLKOUT
MCASP0_
AXR7
U0_GPO11 U0_GPI11 MII1_TD0
M3_TZ_O D0
UT
0x00011C0 PADCONFIG56
E0
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII3_T
GPIO0_55
GPIO0_56
DSS_FSY
NC0
MCASP0_
AXR8
U0_GPO1 U0_GPI12 MII1_TD1
2
M0_A0
D1
0x00011C0 PADCONFIG57
E4
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII3_T
DSS_FSY
NC2
MCASP0_
AXR9
U0_GPO1 U0_GPI13 MII1_TD2
3
M0_B0
D2
0x00011C0 PADCONFIG58
E8
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII3_T
GPIO0_57 UART4_R
XD
MCASP0_
AXR10
U0_GPO1 U0_GPI14 MII1_TD3
4
M0_A1
D3
0x00011C0 PADCONFIG59
EC
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII3_T
U0_GPO1 U0_GPI15 MII1_TX_C M0_B1 X_CTL
TL
GPIO0_58 UART4_TX
D
DSS_FSY
NC3
MCASP0_
AXR11
5
0x00011C0 PADCONFIG60
F0
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII3_T
GPIO0_59
DSS_FSY
NC1
MCASP0_
AXR12
U0_GPO1 U0_GPI16 MII1_TXC M0_A2
6
XC
0x00011C0 PADCONFIG61
F4
PRG0_PR PRG0_PR PRG0_IEP PRG0_PW PRG0_EC
GPIO0_60 GPMC0_A OBSCLK1
D5
MCASP0_
AXR13
BOOTMO
DE7
U0_GPO1 U0_GPI17 0_EDC_SY M0_B2
NC_OUT1
AP0_SYN
C_OUT
7
0x00011C0 PADCONFIG62
F8
PRG0_PR PRG0_PR PRG0_IEP PRG0_PW PRG0_EC
U0_GPO1 U0_GPI18 0_EDC_LA M0_TZ_IN AP0_IN_A
GPIO0_61 GPMC0_A
D6
MCASP0_
AXR14
8
TCH_IN0
PWM_OUT
0x00011C0 PADCONFIG63
FC
PRG0_PR PRG0_PR PRG0_IEP PRG0_PW
U0_GPO1 U0_GPI19 0_EDC_SY M0_TZ_O
GPIO0_62 GPMC0_A
D7
MCASP0_
AXR15
9
NC_OUT0 UT
0x00011C1 PADCONFIG64
00
AE29
AD28
AD27
AC25
AD29
PRG0_PR PRG0_PR PRG0_RG
U1_GPO0 U1_GPI0 MII2_RD0
RGMII4_R RMII4_RX
D0 D0
GPIO0_63 UART4_CT
Sn
MCASP1_
AXR0
UART5_R
XD
0x00011C1 PADCONFIG65
04
PRG0_PR PRG0_PR PRG0_RG
U1_GPO1 U1_GPI1 MII2_RD1
RGMII4_R RMII4_RX
D1 D1
GPIO0_64 UART4_RT
Sn
MCASP1_
AXR1
UART5_TX
D
0x00011C1 PADCONFIG66
08
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII4_R RMII4_CR
U1_GPO2 U1_GPI2 MII2_RD2 M2_A2 D2 S_DV
GPIO0_65 GPMC0_A
23
MCASP1_ MCASP1_
ACLKR AXR10
0x00011C1 PADCONFIG67
0C
PRG0_PR PRG0_PR PRG0_RG
U1_GPO3 U1_GPI3 MII2_RD3 D3 _ER
RGMII4_R RMII4_RX
GPIO0_66
MCASP1_ MCASP1_
AFSR
AXR11
0x00011C1 PADCONFIG68
10
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII4_R RMII4_TX
GPIO0_67 GPMC0_A
24
MCASP1_
AXR2
U1_GPO4 U1_GPI4
MII2_RX_ M2_B2
CTL
X_CTL
D1
0x00011C1 PADCONFIG69
14
AB27
AC26
AA24
PRG0_PR PRG0_PR
U1_GPO5 U1_GPI5
GPIO0_68 GPMC0_A
D8
MCASP1_
ACLKX
BOOTMO
DE6
0x00011C1 PADCONFIG70
18
PRG0_PR PRG0_PR PRG0_RG
U1_GPO6 U1_GPI6 MII2_RXC
RGMII4_R RMII4_TX
GPIO0_69 GPMC0_A
25
MCASP1_
AXR3
XC
D0
0x00011C1 PADCONFIG71
1C
PRG0_PR PRG0_PR PRG0_IEP
U1_GPO7 U1_GPI7
SPI3_CS0
MCAN11_T GPIO0_70 GPMC0_A
X D9
MCASP1_
AXR4
UART2_TX
D
1_EDC_LA
TCH_IN1
0x00011C1 PADCONFIG72
20
AA28
PRG0_PR PRG0_PR
U1_GPO8 U1_GPI8
PRG0_PW
M2_TZ_O
UT
MCAN11_ GPIO0_71 GPMC0_A
RX D10
MCASP1_
AFSX
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DRA829J, DRA829V
SPRSP35J – FEBRUARY 2019 – REVISED AUGUST 2021
www.ti.com
Table 6-125. Pin Multiplexing (continued)
BALL
MUXMODE[14:0] SETTINGS
REGISTER
NAME
ADDRESS
NUMB
ER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x00011C1 PADCONFIG73
24
Y24
PRG0_PR PRG0_PR PRG0_UA
U1_GPO9 U1_GPI9 RT0_RXD
SPI3_CS3
PRG0_IEP GPIO0_72 GPMC0_A
DSS_FSY
NC3
MCASP1_
AXR5
UART8_R
XD
0_EDIO_D
ATA_IN_O
UT30
D11
0x00011C1 PADCONFIG74
28
AA25
PRG0_PR PRG0_PR PRG0_UA PRG0_PW
U1_GPO1 U1_GPI10 RT0_TXD M2_TZ_IN
0
PRG0_IEP GPIO0_73 GPMC0_A CLKOUT
MCASP1_
AXR6
UART8_TX
D
0_EDIO_D
ATA_IN_O
UT31
D12
0x00011C1 PADCONFIG75
2C
AG26
AF27
PRG0_PR PRG0_PR PRG0_RG
U1_GPO11 U1_GPI11 MII2_TD0
RGMII4_T RMII4_TX_
D0 EN
GPIO0_74 GPMC0_A
26
MCASP1_
AXR7
0x00011C1 PADCONFIG76
30
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII4_T
U1_GPO1 U1_GPI12 MII2_TD1
2
GPIO0_75
GPIO0_76
GPIO0_77
GPIO0_78
GPIO0_79
MCASP1_
AXR8
UART8_CT
Sn
M1_A0
D1
0x00011C1 PADCONFIG77
34
AF26
AE25
AF29
AG29
Y25
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII4_T
U1_GPO1 U1_GPI13 MII2_TD2
3
MCASP1_
AXR9
UART8_RT
Sn
M1_B0
D2
0x00011C1 PADCONFIG78
38
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII4_T
U1_GPO1 U1_GPI14 MII2_TD3
4
MCASP2_
AXR0
UART2_CT
Sn
M1_A1
D3
0x00011C1 PADCONFIG79
3C
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII4_T
U1_GPO1 U1_GPI15 MII2_TX_C M1_B1 X_CTL
TL
MCASP2_
AXR1
UART2_RT
Sn
5
0x00011C1 PADCONFIG80
40
PRG0_PR PRG0_PR PRG0_RG PRG0_PW RGMII4_T
U1_GPO1 U1_GPI16 MII2_TXC M1_A2
6
MCASP2_
AXR2
XC
0x00011C1 PADCONFIG81
44
PRG0_PR PRG0_PR PRG0_IEP PRG0_PW SPI3_CLK
U1_GPO1 U1_GPI17 1_EDC_SY M1_B2
GPIO0_80 GPMC0_A
D13
MCASP2_
AXR3
BOOTMO
DE3
7
NC_OUT1
0x00011C1 PADCONFIG82
48
AA26
AA29
PRG0_PR PRG0_PR PRG0_IEP PRG0_PW SPI3_D0
U1_GPO1 U1_GPI18 1_EDC_LA M1_TZ_IN
MCAN12_ GPIO0_81 GPMC0_A
TX D14
MCASP2_
AFSX
UART2_R
XD
8
TCH_IN0
0x00011C1 PADCONFIG83
4C
PRG0_PR PRG0_PR PRG0_IEP PRG0_PW SPI3_D1
U1_GPO1 U1_GPI19 1_EDC_SY M1_TZ_O
MCAN12_ GPIO0_82 GPMC0_A
RX D15
MCASP2_
ACLKX
9
NC_OUT0 UT
0x00011C1 PADCONFIG84
50
Y26
AA27
U23
U26
V28
V29
V27
U28
PRG0_MDI
O0_MDIO
I2C5_SCL
MCAN13_ GPIO0_83 GPMC0_A
TX 27
DSS_FSY
NC0
MCASP2_ MCASP2_
AFSR AXR4
0x00011C1 PADCONFIG85
54
PRG0_MDI
O0_MDC
I2C5_SDA
MCAN13_ GPIO0_84 GPMC0_A
RX
DSS_FSY
NC2
MCASP2_ MCASP2_
0
ACLKR
AXR5
0x00011C1 PADCONFIG86
58
RGMII5_T RMII7_CR I2C2_SCL
X_CTL S_DV
VOUT1_D TRC_CLK EHRPWM0 GPIO0_85 GPMC0_A
ATA0 _SYNCI
MCASP10
_ACLKX
1
0x00011C1 PADCONFIG87
5C
RGMII5_R RMII7_RX I2C2_SDA
X_CTL _ER
VOUT1_D TRC_CTL EHRPWM0 GPIO0_86 GPMC0_A
ATA1 _SYNCO
MCASP10
_AFSX
2
0x00011C1 PADCONFIG88
60
RGMII5_T UART3_R
D3 XD
SYNC2_O VOUT1_D TRC_DATA EHRPWM_ GPIO0_87 GPMC0_A
UT ATA2 TZn_IN0
MCASP10
_AXR0
0
3
0x00011C1 PADCONFIG89
64
RGMII5_T UART3_TX
D2
SYNC3_O VOUT1_D TRC_DATA EHRPWM0 GPIO0_88 GPMC0_A
UT ATA3 _A
MCASP10
_AXR1
D
1
4
0x00011C1 PADCONFIG90
68
RGMII5_T RMII7_TX I2C3_SCL
D1 D1
VOUT1_D TRC_DATA EHRPWM0 GPIO0_89 GPMC0_A
ATA4 _B
MCASP11_
ACLKX
2
5
0x00011C1 PADCONFIG91
6C
RGMII5_T RMII7_TX I2C3_SDA
D0 D0
VOUT1_D TRC_DATA EHRPWM1 GPIO0_90 GPMC0_A
ATA5 _A
MCASP11_
AFSX
3
6
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Table 6-125. Pin Multiplexing (continued)
BALL
NUMB
ER
MUXMODE[14:0] SETTINGS
REGISTER
NAME
ADDRESS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x00011C1 PADCONFIG92
70
U29
U25
U27
U24
R23
T23
Y28
V23
RGMII5_T RMII7_TX_ I2C6_SCL
VOUT1_D TRC_DATA EHRPWM1 GPIO0_91 GPMC0_A
ATA6 _B
MCASP10
_AXR2
XC
EN
4
7
0x00011C1 PADCONFIG93
74
RGMII5_R
XC
I2C6_SDA
VOUT1_D TRC_DATA EHRPWM_ GPIO0_92 GPMC0_A
ATA7 TZn_IN1
MCASP10
_AXR3
EHRPWM_
SOCA
5
8
0x00011C1 PADCONFIG94
78
RGMII5_R UART3_CT
D3 Sn
UART6_R VOUT1_D TRC_DATA EHRPWM2 GPIO0_93 GPMC0_A
XD ATA8 _A
MCASP11_
AXR0
6
9
0x00011C1 PADCONFIG95
7C
RGMII5_R UART3_RT
D2 Sn
UART6_TX VOUT1_D TRC_DATA EHRPWM2 GPIO0_94 GPMC0_A
ATA9 _B 10
MCASP11_
AXR1
D
7
0x00011C1 PADCONFIG96
80
RGMII5_R RMII7_RX
D1 D1
UART6_CT VOUT1_D TRC_DATA EHRPWM_ GPIO0_95 GPMC0_A
MCASP11_
AXR2
EHRPWM_
SOCB
Sn
ATA10
8
TZn_IN2
11
0x00011C1 PADCONFIG97
84
RGMII5_R RMII7_RX
D0 D0
UART6_RT VOUT1_D TRC_DATA
GPIO0_96 GPMC0_A
12
MCASP11_
AXR3
Sn ATA11
9
0x00011C1 PADCONFIG98
88
RGMII6_T RMII8_CR
X_CTL S_DV
VOUT1_D TRC_DATA
ATA12 10
GPIO0_97 GPMC0_A
13
MCASP10
_ACLKR
0x00011C1 PADCONFIG99
8C
RGMII6_R RMII8_RX
X_CTL _ER
VOUT1_D TRC_DATA EHRPWM3 GPIO0_98 GPMC0_A
ATA13 11 _A 14
MCASP10
_AFSR
0x00011C1 PADCONFIG100 W23
90
RGMII6_T UART4_R
D3 XD
SPI5_CS3 VOUT1_D TRC_DATA EHRPWM3 GPIO0_99 GPMC0_A
ATA14 12 _B 15
MCASP11_
ACLKR
0x00011C1 PADCONFIG101 W28
94
RGMII6_T UART4_TX
D2
SPI5_CS2 VOUT1_D TRC_DATA EHRPWM3 GPIO0_10 GPMC0_A
ATA15 13 _SYNCI 16
MCASP11_
AFSR
D
0
0x00011C1 PADCONFIG102 V25
98
RGMII6_T RMII8_TX
D1 D1
SPI5_D0
VOUT1_V TRC_DATA EHRPWM3 GPIO0_10 GPMC0_A VOUT1_V
MCASP10
_AXR4
SYNC
14
_SYNCO
1
17
P0_VSYN
C
0x00011C1 PADCONFIG103 W27
9C
RGMII6_T RMII8_TX
D0 D0
SPI5_CS0 VOUT1_H TRC_DATA EHRPWM_ GPIO0_10 GPMC0_A VOUT1_V
MCASP10
_AXR5
SYNC
15
TZn_IN3
2
18
P0_HSYN
C
0x00011C1 PADCONFIG104 W29
A0
RGMII6_T RMII8_TX_
SPI5_CLK VOUT1_P TRC_DATA EHRPWM4 GPIO0_10 GPMC0_A
CLK 16 _A 19
MCASP10
_AXR6
XC
EN
3
0x00011C1 PADCONFIG105 W26
A4
RGMII6_R
XC
AUDIO_EX VOUT1_D TRC_DATA EHRPWM4 GPIO0_10 GPMC0_A VOUT1_V
MCASP10
_AXR7
T_REFCLK
2
E
17
_B
4
20
P0_DE
0x00011C1 PADCONFIG106 Y29
A8
RGMII6_R UART4_CT
D3 Sn
UART5_R CLKOUT
XD
TRC_DATA EHRPWM_ GPIO0_10 GPMC0_A
18 TZn_IN4 21
MCASP11_
AXR4
5
0x00011C1 PADCONFIG107 Y27
AC
RGMII6_R UART4_RT
D2 Sn
UART5_TX
D
TRC_DATA EHRPWM5 GPIO0_10 GPMC0_A
19 _A 22
MCASP11_
AXR5
6
0x00011C1 PADCONFIG108 W24
B0
RGMII6_R RMII8_RX
D1 D1
SPI5_D1
VOUT1_E TRC_DATA EHRPWM5 GPIO0_10 GPMC0_B
XTPCLKIN 20 _B E1n
MCASP11_
AXR6
7
0x00011C1 PADCONFIG109 W25
B4
RGMII6_R RMII8_RX
SPI5_CS1 AUDIO_EX TRC_DATA EHRPWM_ GPIO0_10 GPMC0_DI
MCASP11_
AXR7
D0
D0
T_REFCLK 21
3
TZn_IN5
8
R
0x00011C1 PADCONFIG110 V26
B8
MDIO0_M
DIO
TRC_DATA
22
GPIO0_10 GPMC0_W
9 AIT3
0x00011C1 PADCONFIG111 V24
BC
MDIO0_M
DC
TRC_DATA
23
GPIO0_11 GPMC0_W
0
AIT2
0x00011C1 PADCONFIG112 AA2
C0
SPI0_CS0 UART0_RT
Sn
GPIO0_111
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Table 6-125. Pin Multiplexing (continued)
BALL
MUXMODE[14:0] SETTINGS
REGISTER
NAME
ADDRESS
NUMB
ER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x00011C1 PADCONFIG113 Y4
C4
SPI0_CS1 CPTS0_TS I2C3_SCL
_COMP
DP0_HPD PRG1_IEP GPIO0_11
0_EDIO_O
UTVALID
2
0x00011C1 PADCONFIG114 AA1
C8
SPI0_CLK UART1_CT I2C2_SCL
Sn
GPIO0_11
3
0x00011C1 PADCONFIG115 AB5
CC
SPI0_D0
UART1_RT I2C2_SDA
Sn
GPIO0_11
4
0x00011C1 PADCONFIG116 AA3
D0
SPI0_D1
I2C6_SCL
GPIO0_11
5
0x00011C1 PADCONFIG117 Y3
D4
SPI1_CS0 UART0_CT
Sn
UART5_R
XD
PRG0_IEP GPIO0_11 PRG0_IEP
0_EDIO_O
UTVALID
6
0_EDC_LA
TCH_IN0
0x00011C1 PADCONFIG118 W4
D8
SPI1_CS1 CPTS0_TS I2C3_SDA UART5_TX
_SYNC
GPIO0_11
7
D
0x00011C1 PADCONFIG119 Y1
DC
SPI1_CLK UART5_CT I2C4_SDA UART2_R
Sn XD
GPIO0_11 PRG0_IEP
8
0_EDC_SY
NC_OUT0
0x00011C1 PADCONFIG120 Y5
E0
SPI1_D0
SPI1_D1
UART5_RT I2C4_SCL UART2_TX
Sn
GPIO0_11 PRG0_IEP
D
9
1_EDC_LA
TCH_IN0
0x00011C1 PADCONFIG121 Y2
E4
I2C6_SDA
GPIO0_12 PRG0_IEP
0
1_EDC_SY
NC_OUT0
0x00011C1 PADCONFIG122 AB2
E8
UART0_R
XD
SPI2_CS1
SPI2_CS2
GPIO0_12
1
0x00011C1 PADCONFIG123 AB3
EC
UART0_TX
D
SPI7_CS1 GPIO0_12
2
0x00011C1 PADCONFIG124 AC2
F0
UART0_CT TIMER_IO SPI0_CS2 MCAN2_R SPI2_CS0 EQEP0_A
Sn
GPIO0_12 MLB0_ML
6
X
3
BSIG
0x00011C1 PADCONFIG125 AB1
F4
UART0_RT TIMER_IO SPI0_CS3 MCAN2_T SPI2_CLK EQEP0_B
GPIO0_12
4
Sn
7
X
0x00011C1 PADCONFIG126 AA4
F8
UART1_R
XD
SPI7_CS2 GPIO0_12
5
0x00011C1 PADCONFIG127 AB4
FC
UART1_TX
D
I3C0_SDA SPI7_CS3 GPIO0_12
PULLEN
6
0x00011C2 PADCONFIG128 AC4
00
UART1_CT MCAN3_R
Sn
SPI2_D0
SPI2_D1
I2C2_SCL
I2C2_SDA
EQEP0_S
GPIO0_12 MLB0_ML
X
7
BCLK
0x00011C2 PADCONFIG129 AD5
04
UART1_RT MCAN3_T
EQEP0_I
GPIO1_0
MLB0_ML
BDAT
Sn
X
0x00011C2 PADCONFIG130 W5
08
MCAN0_R
X
GPIO1_1
GPIO1_2
GPIO1_3
GPIO1_4
0x00011C2 PADCONFIG131 W6
0C
MCAN0_T
X
0x00011C2 PADCONFIG132 W3
10
MCAN1_R UART6_CT UART9_R USB0_DR USB1_DR
Sn XD VVBUS VVBUS
X
0x00011C2 PADCONFIG133 V4
14
MCAN1_T UART6_RT UART9_TX USB0_DR USB1_DR
Sn VVBUS VVBUS
X
D
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Table 6-125. Pin Multiplexing (continued)
BALL
NUMB
ER
MUXMODE[14:0] SETTINGS
REGISTER
NAME
ADDRESS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x00011C2 PADCONFIG134 W2
18
I3C0_SCL MMC2_SD UART9_CT MCAN2_R I2C6_SCL DP0_HPD PCIE0_CL GPIO1_5
UART6_R
XD
CD
Sn
X
KREQn
0x00011C2 PADCONFIG135 W1
1C
I3C0_SDA MMC2_SD UART9_RT MCAN2_T I2C6_SDA
PCIE1_CL GPIO1_6
KREQn
UART6_TX
D
WP Sn
X
0x00011C2 PADCONFIG136 AC5
20
I2C0_SCL
I2C0_SDA
GPIO1_7
GPIO1_8
GPIO1_9
0x00011C2 PADCONFIG137 AA5
24
0x00011C2 PADCONFIG138 Y6
28
I2C1_SCL CPTS0_H
W1TSPUS
H
0x00011C2 PADCONFIG139 AA6
2C
I2C1_SDA CPTS0_H
GPIO1_10
W2TSPUS
H
0x00011C2 PADCONFIG140 U2
30
ECAP0_IN SYNC0_O CPTS0_RF
SPI2_CS3 I3C0_SDA SPI7_CS0 GPIO1_11
PULLEN
_APWM_O UT
UT
T_CLK
0x00011C2 PADCONFIG141 U3
34
EXT_REF SYNC1_O
SPI7_CLK GPIO1_12
CLK1
UT
0x00011C2 PADCONFIG142 V6
38
TIMER_IO ECAP1_IN SYSCLKO
SPI7_D0
SPI7_D1
GPIO1_13
GPIO1_14
BOOTMO
DE4
0
_APWM_O UT0
UT
0x00011C2 PADCONFIG143 V5
3C
TIMER_IO ECAP2_IN OBSCLK0
BOOTMO
DE5
1
_APWM_O
UT
0x00011C2 PADCONFIG144 R26
40
MMC1_DA UART7_R
T3 XD
GPIO1_15
GPIO1_16
GPIO1_17
0x00011C2 PADCONFIG145 R25
44
MMC1_DA UART7_TX
T2
D
0x00011C2 PADCONFIG146 P24
48
MMC1_DA UART7_CT ECAP0_IN TIMER_IO
UART4_R
XD
T1
Sn
_APWM_O
UT
0
0x00011C2 PADCONFIG147 R24
4C
MMC1_DA UART7_RT ECAP1_IN TIMER_IO
UART4_TX
D
GPIO1_18
T0
Sn
_APWM_O
UT
1
0x00011C2 PADCONFIG148 P25
50
MMC1_CL UART8_R
XD
I2C4_SCL
I2C4_SDA
GPIO1_19
GPIO1_20
K
0x00011C2 PADCONFIG149 R29
54
MMC1_CM UART8_TX
D
D
0x00011C2 PADCONFIG150 P23
58
MMC1_SD UART8_CT UART0_D TIMER_IO
CD Sn CDn
EQEP2_I
PCIE2_CL GPIO1_21 PRG0_IEP
2
KREQn
0_EDC_LA
TCH_IN1
0x00011C2 PADCONFIG151 R28
5C
MMC1_SD UART8_RT UART0_D TIMER_IO ECAP2_IN EQEP2_S PCIE3_CL GPIO1_22 PRG0_IEP
WP
Sn
SRn
3
_APWM_O
UT
KREQn
0_EDC_SY
NC_OUT1
0x00011C2 PADCONFIG152 T28
60
MMC2_DA UART9_R CPTS0_H
I2C5_SCL
GPIO1_23
T3
XD
W1TSPUS
H
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Table 6-125. Pin Multiplexing (continued)
BALL
MUXMODE[14:0] SETTINGS
REGISTER
NAME
ADDRESS
NUMB
ER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x00011C2 PADCONFIG153 T29
64
MMC2_DA UART9_TX CPTS0_H
I2C5_SDA
GPIO1_24
T2
D
W2TSPUS
H
0x00011C2 PADCONFIG154 T27
68
MMC2_DA UART9_CT UART0_DT TIMER_IO UART6_R EQEP2_A
T1 Sn Rn XD
GPIO1_25 PRG0_IEP
1_EDC_LA
4
TCH_IN1
0x00011C2 PADCONFIG155 T24
6C
MMC2_DA UART9_RT UART0_RI TIMER_IO UART6_TX EQEP2_B
T0 Sn
GPIO1_26 PRG0_IEP
1_EDC_SY
n
5
D
NC_OUT1
0x00011C2 PADCONFIG156 T26
70
MMC2_CL USB0_DR USB1_DR TIMER_IO I2C3_SCL UART3_R
VVBUS VVBUS XD
GPIO1_27
GPIO1_28
K
6
0x00011C2 PADCONFIG157 T25
74
MMC2_CM USB0_DR USB1_DR TIMER_IO I2C3_SDA UART3_TX
D
VVBUS
VVBUS
7
D
0x00011C2 PADCONFIG158 T6
78
RESETST
ATz
0x00011C2 PADCONFIG159 U1
7C
PORz_OU
T
0x00011C2 PADCONFIG160 U4
80
SOC_SAF
ETY_ERR
ORn
0x00011C2 PADCONFIG161 V1
84
TDI
0x00011C2 PADCONFIG162 V3
88
TDO
TMS
0x00011C2 PADCONFIG163 V2
8C
0x04301C0 WKUP_PADCON E20
MCU_OSP MCU_HYP
WKUP_GP
IO0_16
00
FIG0
I0_CLK
ERBUS0_
CK
0x04301C0 WKUP_PADCON C21
04 FIG1
MCU_OSP MCU_HYP
I0_LBCLK ERBUS0_
WKUP_GP
IO0_17
O
CKn
0x04301C0 WKUP_PADCON D21
08 FIG2
MCU_OSP MCU_HYP
WKUP_GP
IO0_18
I0_DQS
ERBUS0_
RWDS
0x04301C0 WKUP_PADCON D20
0C FIG3
MCU_OSP MCU_HYP
WKUP_GP
IO0_19
I0_D0
ERBUS0_
DQ0
0x04301C0 WKUP_PADCON G19
10 FIG4
MCU_OSP MCU_HYP
WKUP_GP
IO0_20
I0_D1
ERBUS0_
DQ1
0x04301C0 WKUP_PADCON G20
14 FIG5
MCU_OSP MCU_HYP
WKUP_GP
IO0_21
I0_D2
ERBUS0_
DQ2
0x04301C0 WKUP_PADCON F20
18 FIG6
MCU_OSP MCU_HYP
WKUP_GP
IO0_22
I0_D3
ERBUS0_
DQ3
0x04301C0 WKUP_PADCON F21
MCU_OSP MCU_HYP
WKUP_GP
IO0_23
1C
FIG7
I0_D4
ERBUS0_
DQ4
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Table 6-125. Pin Multiplexing (continued)
BALL
NUMB
ER
MUXMODE[14:0] SETTINGS
REGISTER
NAME
ADDRESS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x04301C0 WKUP_PADCON E21
20 FIG8
MCU_OSP MCU_HYP
WKUP_GP
IO0_24
I0_D5
ERBUS0_
DQ5
0x04301C0 WKUP_PADCON B22
24 FIG9
MCU_OSP MCU_HYP
WKUP_GP
IO0_25
I0_D6
ERBUS0_
DQ6
0x04301C0 WKUP_PADCON G21
28 FIG10
MCU_OSP MCU_HYP
WKUP_GP
IO0_26
I0_D7
ERBUS0_
DQ7
0x04301C0 WKUP_PADCON F19
2C FIG11
MCU_OSP MCU_HYP
WKUP_GP
IO0_27
I0_CSn0
ERBUS0_
CSn0
0x04301C0 WKUP_PADCON E19
30 FIG12
MCU_OSP MCU_HYP
WKUP_GP
IO0_28
I0_CSn1
ERBUS0_
RESETn
0x04301C0 WKUP_PADCON F22
34 FIG13
MCU_OSP
I1_CLK
WKUP_GP
IO0_29
0x04301C0 WKUP_PADCON A23
38 FIG14
MCU_OSP MCU_OSP MCU_HYP
MCU_OSP WKUP_GP
I0_RESET IO0_30
_OUT0
I1_LBCLK I0_CSn2
O
ERBUS0_
RESETOn
0x04301C0 WKUP_PADCON B23
3C FIG15
MCU_OSP MCU_OSP MCU_HYP
MCU_OSP WKUP_GP
I0_ECC_F IO0_31
AIL
I1_DQS
I0_CSn3
ERBUS0_I
NTn
0x04301C0 WKUP_PADCON D22
40 FIG16
MCU_OSP
I1_D0
WKUP_GP
IO0_32
0x04301C0 WKUP_PADCON G22
44 FIG17
MCU_OSP
I1_D1
MCU_UAR MCU_SPI1
T0_RXD _CS1
WKUP_GP
IO0_33
0x04301C0 WKUP_PADCON D23
48 FIG18
MCU_OSP
I1_D2
MCU_UAR MCU_SPI1
T0_TXD _CS2
WKUP_GP
IO0_34
0x04301C0 WKUP_PADCON C23
4C FIG19
MCU_OSP
I1_D3
MCU_UAR MCU_SPI0
T0_CTSn _CS1
WKUP_GP
IO0_35
0x04301C0 WKUP_PADCON C22
50 FIG20
MCU_OSP
I1_CSn0
WKUP_GP
IO0_36
0x04301C0 WKUP_PADCON E22
54 FIG21
MCU_OSP MCU_HYP MCU_TIM MCU_HYP MCU_UAR MCU_SPI0 MCU_OSP WKUP_GP
I1_CSn1
ERBUS0_ ER_IO0
WPn
ERBUS0_ T0_RTSn
CSn1
_CS2
I0_RESET IO0_37
_OUT1
0x04301C0 WKUP_PADCON B27
58 FIG22
MCU_RG
MII1_TX_C 1_CRS_D
MCU_RMII
WKUP_GP
IO0_38
TL
V
0x04301C0 WKUP_PADCON C25
5C FIG23
MCU_RG
MII1_RX_ 1_RX_ER
CTL
MCU_RMII
WKUP_GP
IO0_39
0x04301C0 WKUP_PADCON A28
60 FIG24
MCU_RG
MII1_TD3
MCU_TIM
ER_IO2
MCU_ADC
_EXT_TRI
GGER0
WKUP_GP
IO0_40
0x04301C0 WKUP_PADCON A27
64 FIG25
MCU_RG
MII1_TD2
MCU_TIM
ER_IO3
MCU_ADC
_EXT_TRI
GGER1
WKUP_GP
IO0_41
0x04301C0 WKUP_PADCON A26
68 FIG26
MCU_RG
MII1_TD1
MCU_RMII
1_TXD1
WKUP_GP
IO0_42
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Table 6-125. Pin Multiplexing (continued)
BALL
MUXMODE[14:0] SETTINGS
REGISTER
NAME
ADDRESS
NUMB
ER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x04301C0 WKUP_PADCON B25
6C FIG27
MCU_RG
MII1_TD0
MCU_RMII
1_TXD0
WKUP_GP
IO0_43
0x04301C0 WKUP_PADCON B26
70 FIG28
MCU_RG
MII1_TXC 1_TX_EN
MCU_RMII
WKUP_GP
IO0_44
0x04301C0 WKUP_PADCON C24
74 FIG29
MCU_RG MCU_RMII
MII1_RXC 1_REF_CL
K
WKUP_GP
IO0_45
0x04301C0 WKUP_PADCON A25
78 FIG30
MCU_RG
MII1_RD3 ER_IO4
MCU_TIM
WKUP_GP
IO0_46
0x04301C0 WKUP_PADCON D24
7C FIG31
MCU_RG MCU_TIM
MII1_RD2 ER_IO5
WKUP_GP
IO0_47
0x04301C0 WKUP_PADCON A24
80 FIG32
MCU_RG
MII1_RD1 1_RXD1
MCU_RMII
WKUP_GP
IO0_48
0x04301C0 WKUP_PADCON B24
84 FIG33
MCU_RG
MII1_RD0 1_RXD0
MCU_RMII
WKUP_GP
IO0_49
0x04301C0 WKUP_PADCON E23
88 FIG34
MCU_MDI
O0_MDIO
WKUP_GP
IO0_50
0x04301C0 WKUP_PADCON F23
8C FIG35
MCU_MDI
O0_MDC
WKUP_GP
IO0_51
0x04301C0 WKUP_PADCON E27
90 FIG36
MCU_SPI0
_CLK
WKUP_GP
IO0_52
MCU_BOO
TMODE00
0x04301C0 WKUP_PADCON E24
94 FIG37
MCU_SPI0
_D0
WKUP_GP
IO0_53
MCU_BOO
TMODE01
0x04301C0 WKUP_PADCON E28
98 FIG38
MCU_SPI0
_D1
MCU_TIM
ER_IO0
WKUP_GP
IO0_54
MCU_BOO
TMODE02
0x04301C0 WKUP_PADCON E25
9C FIG39
MCU_SPI0
_CS0
MCU_TIM
ER_IO1
WKUP_GP
IO0_55
0x04301C0 WKUP_PADCON J29
A0 FIG40
WKUP_UA
RT0_RXD
WKUP_GP
IO0_56
0x04301C0 WKUP_PADCON J28
A4 FIG41
WKUP_UA
RT0_TXD
WKUP_GP
IO0_57
0x04301C0 WKUP_PADCON D29
A8 FIG42
MCU_MCA
N0_TX
WKUP_GP
IO0_58
0x04301C0 WKUP_PADCON C29
AC FIG43
MCU_MCA
N0_RX
WKUP_GP
IO0_59
0x04301C0 WKUP_PADCON F26
B0 FIG44
MCU_SPI1 MCU_SPI1
WKUP_GP
IO0_0
MCU_BOO
TMODE03
_CLK
_CLK
0x04301C0 WKUP_PADCON F25
B4 FIG45
MCU_SPI1 MCU_SPI1
_D0 _D0
WKUP_GP
IO0_1
MCU_BOO
TMODE04
0x04301C0 WKUP_PADCON F28
B8 FIG46
MCU_SPI1 MCU_SPI1
_D1 _D1
WKUP_GP
IO0_2
MCU_BOO
TMODE05
0x04301C0 WKUP_PADCON F27
BC FIG47
MCU_SPI1 MCU_SPI1
_CS0 _CS0
WKUP_GP
IO0_3
0x04301C0 WKUP_PADCON G25
MCU_MCA MCU_MCA MCU_SPI0 MCU_ADC
WKUP_GP
IO0_4
C0
FIG48
N1_TX
N1_TX
_CS3
_EXT_TRI
GGER0
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Table 6-125. Pin Multiplexing (continued)
BALL
NUMB
ER
MUXMODE[14:0] SETTINGS
REGISTER
NAME
ADDRESS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x04301C0 WKUP_PADCON G24
C4 FIG49
MCU_MCA MCU_MCA MCU_SPI1 MCU_ADC
WKUP_GP
IO0_5
N1_RX
N1_RX
_CS3
_EXT_TRI
GGER1
0x04301C0 WKUP_PADCON F29
C8 FIG50
WKUP_UA WKUP_UA MCU_CPT MCU_I2C1
RT0_CTSn RT0_CTSn S0_HW1T _SCL
SPUSH
WKUP_GP
IO0_6
0x04301C0 WKUP_PADCON G28
CC FIG51
WKUP_UA WKUP_UA MCU_CPT MCU_I2C1
RT0_RTSn RT0_RTSn S0_HW2T _SDA
SPUSH
WKUP_GP
IO0_7
0x04301C0 WKUP_PADCON G27
D0 FIG52
MCU_I2C1 MCU_I2C1 MCU_CPT MCU_I3C1 MCU_TIM
WKUP_GP
IO0_8
_SCL
_SCL
S0_TS_SY _SCL
NC
ER_IO6
0x04301C0 WKUP_PADCON G26
D4 FIG53
MCU_I2C1 MCU_I2C1 MCU_CPT MCU_I3C1 MCU_TIM
WKUP_GP
IO0_9
_SDA
_SDA
S0_TS_CO _SDA
MP
ER_IO7
0x04301C0 WKUP_PADCON H26
D8 FIG54
MCU_EXT MCU_EXT MCU_UAR MCU_ADC MCU_CPT MCU_SYS
_REFCLK0 _REFCLK0 T0_TXD _EXT_TRI S0_RFT_C CLKOUT0
GGER0 LK
WKUP_GP
IO0_10
0x04301C0 WKUP_PADCON H27
DC FIG55
MCU_OBS MCU_OBS MCU_UAR MCU_ADC MCU_TIM MCU_I3C1 MCU_CLK WKUP_GP
CLK0
CLK0
T0_RXD
_EXT_TRI ER_IO1
GGER1
_SDAPULL OUT0
EN
IO0_11
0x04301C0 WKUP_PADCON G29
E0 FIG56
MCU_UAR MCU_SPI0
T0_TXD _CS1
WKUP_GP
IO0_12
MCU_BOO
TMODE08
0x04301C0 WKUP_PADCON H28
E4 FIG57
MCU_UAR MCU_SPI1
T0_RXD _CS1
WKUP_GP
IO0_13
MCU_BOO
TMODE09
0x04301C0 WKUP_PADCON H29
E8 FIG58
MCU_UAR MCU_SPI0
T0_CTSn _CS2
WKUP_GP
IO0_14
MCU_BOO
TMODE06
0x04301C0 WKUP_PADCON J27
EC FIG59
MCU_UAR MCU_SPI1
WKUP_GP
IO0_15
MCU_BOO
TMODE07
T0_RTSn
_CS2
0x04301C0 WKUP_PADCON D26
F0 FIG60
MCU_I3C0
_SCL
MCU_UAR
T0_CTSn
MCU_TIM
ER_IO8
WKUP_GP
IO0_60
0x04301C0 WKUP_PADCON D25
F4 FIG61
MCU_I3C0
_SDA
MCU_UAR
T0_RTSn
MCU_TIM
ER_IO9
WKUP_GP
IO0_61
0x04301C0 WKUP_PADCON J25
F8 FIG62
WKUP_I2C
0_SCL
WKUP_GP
IO0_62
0x04301C0 WKUP_PADCON H24
FC FIG63
WKUP_I2C
0_SDA
WKUP_GP
IO0_63
0x04301C1 WKUP_PADCON J26
00 FIG64
MCU_I2C0
_SCL
WKUP_GP
IO0_64
0x04301C1 WKUP_PADCON H25
04 FIG65
MCU_I2C0
_SDA
WKUP_GP
IO0_65
0x04301C1 WKUP_PADCON E26
08 FIG66
MCU_I3C0
_SDAPULL
EN
WKUP_GP
IO0_66
0x04301C1 WKUP_PADCON G23
0C FIG67
PMIC_PO
WER_EN1
MCU_I3C1
_SDAPULL
EN
WKUP_GP
IO0_67
0x04301C1 WKUP_PADCON D27
10 FIG68
MCU_SAF
ETY_ERR
ORn
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Table 6-125. Pin Multiplexing (continued)
BALL
MUXMODE[14:0] SETTINGS
REGISTER
NAME
ADDRESS
NUMB
ER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x04301C1 WKUP_PADCON D28
14 FIG69
MCU_RES
ETz
0x04301C1 WKUP_PADCON C27
18 FIG70
MCU_RES
ETSTATz
0x04301C1 WKUP_PADCON B28
1C FIG71
MCU_POR
z_OUT
0x04301C1 WKUP_PADCON E29
20 FIG72
TCK
0x04301C1 WKUP_PADCON F24
24 FIG73
TRSTn
EMU0
EMU1
0x04301C1 WKUP_PADCON C26
28 FIG74
0x04301C1 WKUP_PADCON B29
2C FIG75
0x04301C1 WKUP_PADCON K25
30 FIG76
MCU_ADC
0_AIN0
0x04301C1 WKUP_PADCON K26
34 FIG77
MCU_ADC
0_AIN1
0x04301C1 WKUP_PADCON K28
38 FIG78
MCU_ADC
0_AIN2
0x04301C1 WKUP_PADCON L28
3C FIG79
MCU_ADC
0_AIN3
0x04301C1 WKUP_PADCON K24
40 FIG80
MCU_ADC
0_AIN4
0x04301C1 WKUP_PADCON K27
44 FIG81
MCU_ADC
0_AIN5
0x04301C1 WKUP_PADCON K29
48 FIG82
MCU_ADC
0_AIN6
0x04301C1 WKUP_PADCON L29
4C FIG83
MCU_ADC
0_AIN7
0x04301C1 WKUP_PADCON N23
50 FIG84
MCU_ADC
1_AIN0
0x04301C1 WKUP_PADCON M25
54 FIG85
MCU_ADC
1_AIN1
0x04301C1 WKUP_PADCON L24
58 FIG86
MCU_ADC
1_AIN2
0x04301C1 WKUP_PADCON L26
5C FIG87
MCU_ADC
1_AIN3
0x04301C1 WKUP_PADCON N24
60 FIG88
MCU_ADC
1_AIN4
0x04301C1 WKUP_PADCON M24
64 FIG89
MCU_ADC
1_AIN5
0x04301C1 WKUP_PADCON L25
68 FIG90
MCU_ADC
1_AIN6
0x04301C1 WKUP_PADCON L27
MCU_ADC
1_AIN7
6C
FIG91
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Table 6-125. Pin Multiplexing (continued)
BALL
NUMB
ER
MUXMODE[14:0] SETTINGS
REGISTER
NAME
ADDRESS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bootstrap
0x04301C1 WKUP_PADCON C28
70 FIG92
RESET_R
EQz
0x04301C1 WKUP_PADCON J24
74 FIG93
PORz
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6.5 Connections for Unused Pins
This section describes the Unused/Reserved balls connection requirements.
Note
All VMON and power balls must be supplied with the voltages specified in Section 7.4, Recommended
Operating Conditions, unless otherwise specified in Section 6.3, Signal Descriptions.
Note
MMC1_SDCD and MMC2_SDCD must be pulled down for respective MMC modules to work properly.
Table 6-126. Unused Balls Specific Connection Requirements
BALL NUMBER
BALL NAME
CONNECTION REQUIREMENTS
M29
P29
N28
F24
K25
K26
K28
L28
K24
K27
K29
L29
N23
M25
L24
L26
N24
M24
L25
L27
B2
WKUP_OSC0_XI
OSC1_XI
WKUP_LFOSC0_XI
TRSTn
MCU_ADC0_AIN0
MCU_ADC0_AIN1
MCU_ADC0_AIN2
MCU_ADC0_AIN3
MCU_ADC0_AIN4
MCU_ADC0_AIN5
MCU_ADC0_AIN6
MCU_ADC0_AIN7
MCU_ADC1_AIN0
MCU_ADC1_AIN1
MCU_ADC1_AIN2
MCU_ADC1_AIN3
MCU_ADC1_AIN4
MCU_ADC1_AIN5
MCU_ADC1_AIN6
MCU_ADC1_AIN7
DDR0_DQS0P
Each of these balls must be connected to VSS through a
separate external pull resistor to ensure these balls are held
to a valid logic low level if unused.
E3
DDR0_DQS1P
M3
DDR0_DQS2P
R2
DDR0_DQS3P
AE18
AE13
AD13
AE8
F9
SERDES0_REXT
SERDES1_REXT
SERDES2_REXT
SERDES3_REXT
SERDES4_REXT
CSI0_RXRCALIB
CSI1_RXRCALIB
USB0_RCALIB
Each of these balls must be connected to VSS through
appropriate external pull resistor to ensure these balls are
held to a valid logic low level if unused. The resistor value
for the SERDES[4:0]_REXT pins is 3.01 kΩ ±1%, for the
CSI[1:0]_RXRCALIB, USB[1:0]_RCALIB, and DSI_TXRCALIB
pins is 500 Ω ±1%. This is the same connection as during
functional mode.
F16
F15
AB6
AD9
F12
USB1_RCALIB
DSI_TXRCALIB
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Table 6-126. Unused Balls Specific Connection Requirements (continued)
BALL NUMBER
BALL NAME
CONNECTION REQUIREMENTS
D28
H23
J24
E29
V2
MCU_RESETz
MCU_PORz
PORz
TCK
TMS
J25
H24
H25
J26
Y6
WKUP_I2C0_SCL
WKUP_I20_SDA
MCU_I2C0_SDA
MCU_I2C0_SCL
I2C1_SCL
Each of these balls must be connected to the corresponding
power supply through a separate external pull resistor to
AA6
AA5
AC5
AC18
V1
I2C1_SDA
ensure these balls are held to a valid logic high level if unused.
I2C0_SDA
(1)
I2C0_SCL
EXTINTn
TDI
V3
TDO
B29
C26
B1
EMU1
EMU0
DDR0_DQS0N
DDR0_DQS1N
DDR0_DQS2N
DDR0_DQS3N
VPP_CORE
VPP_MCU
MMC0_CALPAD
MLB0_MLBCN
MLB0_MLBCP
MLB0_MLBDN
MLB0_MLBDP
MLB0_MLBSN
MLB0_MLBSP
E2
M2
R1
AB11
F17
AE1
AE2
AD2
AD3
AC3
AC1
AD1
Each of these balls must be left unconnected if unused.
(1) To determine which power supply is associated with any IO refer to Table 6-1, Pin Attributes.
Table 6-127. Reserved Balls Specific Connection Requirements
BALLS
CONNECTION REQUIREMENTS
A29 / AJ1 / U11 / U12 / U13 / T11 / T12 / T13 / M11 / M12 / M13 / N11 / N12 /
N13
These balls do not exist on the package.
These balls must be left unconnected.
N25 / AJ29 / P26 / R27 / AD4 / E18 / F18 / G10 / F11 / N6 / L6 / F6 / E6 / G9 /
F10 / AA23 / F13
Note
All other unused signal balls without Pad Configuration Register can be left unconnected.
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Note
All other unused signal balls with a Pad Configuration Register can be left unconnected with their
multiplexing mode set to GPIO input and internal pulldown resistor enabled.
Unused balls are defined as those which only connect to a PCB solder pad. This is the only use case
where internal pull resistors are allowed as the only source/sink to hold a valid logic level.
Any balls connected to a via, test point, or PCB trace are considered used and must not depend on
the internal pull resistor to hold a valid logic level.
Internal pull resistors are weak and may not source enough current to maintain a valid logic level for
some operating conditions. This may be the case when connected to components with leakage to the
opposite logic level, or when external noise sources couple to signal traces attached to balls which
are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors may be
required to hold a valid logic level on balls with external connections.
If balls are allowed to float between valid logic levels, the input buffer may enter a high-current state
which could damage the IO cell.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
PARAMETER
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
MAX
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
2.2
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDD_CORE
MAIN domain core supply
VDD_MCU
MCUSS core supply
VDD_CPU
CPU core supply
VDDA_0P8_DLL_MMC0
VDDAR_CORE
MMC0 DLL analog supply
MAIN domain RAM supply
VDDAR_MCU
MCUSS RAM supply
VDDAR_CPU
CPU RAM supply
VDDA_0P8_DP
Displayport SERDES analog supply low
Displayport SERDES clock supply
DSITX clock supply
VDDA_0P8_DP_C
VDDA_0P8_DSITX
VDDA_0P8_DSITX_C
VDDA_0P8_CSIRX
VDDA_0P8_SERDES0_1
VDDA_0P8_SERDES2_3
VDDA_0P8_SERDES_C0_1
VDDA_0P8_SERDES_C2_3
VDDA_0P8_USB
VDDA_0P8_UFS
VDDA_0P8_PLL_MLB
VDDA_0P8_PLL_DDR
VDDA_1P8_USB
VDDA_1P8_UFS
VDDA_1P8_DP
DSITX clock supply
CSIRX analog supply low
SERDES0-1 analog supply low
SERDES2-3 analog supply low
SERDES0-1 clock supply
SERDES2-3 clock supply
USB0-1 0.8 V analog supply
UFS analog supply low
MLB PLL analog supply
DDR PLL analog supply
USB0-1 1.8 V analog supply
UFS analog supply high
2.2
Displayport SERDES analog supply high
DSITX analog supply high
2.2
VDDA_1P8_DSITX
VDDA_1P8_CSIRX
VDDA_1P8_SERDES0_1
VDDA_1P8_SERDES2_3
VDDA_3P3_USB
VDDA_MCU_PLLGRP0
VDDA_PLLGRP0
VDDA_PLLGRP1
VDDA_PLLGRP2
VDDA_PLLGRP3
VDDA_PLLGRP4
VDDA_PLLGRP5
VDDA_PLLGRP6
VDDA_WKUP
2.2
CSIRX analog supply high
2.2
SERDES0-1 analog supply high
SERDES2-3 analog supply high
USB0-1 3.3 V analog supply
Analog supply for MCU PLL Group 0
Analog supply for Main PLL Group 0
Analog supply for Main PLL Group 1
Analog supply for Main PLL Group 2
Analog supply for Main PLL Group 3
Analog supply for Main PLL Group 4
Analog supply for MAIN PLL Group 5 (DDR)
Analog supply for MAIN PLL Group 6
Oscillator supply for WKUP domain
ADC analog supply
2.2
2.2
3.8
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
VDDA_ADC0
2.2
VDDA_ADC1
ADC analog supply
2.2
VDDA_MCU_TEMP
VDDA_POR_WKUP
VDDA_1P8_MLB
Analog supply for temperature sensor 0 in MCU domain
WKUP domain analog supply
MLB IO supply (6-pin interface)
2.2
2.2
2.2
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7.1 Absolute Maximum Ratings (continued)
over operating free-air temperature range (unless otherwise noted) (1) (2)
PARAMETER
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
MAX
2.2
2.2
1.2
1.2
1.2
2.2
2.2
2.2
3.8
UNIT
V
VDDA_TEMP_0_1
VDDA_TEMP_2_3
VDDS_DDR
Analog supply for temperature sensor 0
Analog supply for temperature sensor 2
DDR inteface power supply
V
V
VDDS_DDR_BIAS
VDDS_DDR_C
VDDS_MMC0
Bias supply for LPDDR4
V
IO power for DDR Memory Clock Bit (MCB) macro
MMC0 IO supply
V
V
VDDS_OSC1
HFOSC1 supply
V
VDDSHV0_MCU
IO supply MCUSS general IO
group, and MCU and MAIN
domain warm reset pins
1.8 V
3.3 V
V
VDDSHV0
IO supply for MAIN domain
general
1.8 V
3.3 V
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
–0.3
2.2
3.8
2.2
3.8
2.2
3.8
2.2
3.8
2.2
3.8
2.2
3.8
2.2
3.8
2.2
3.8
2.2
3.8
1.89
1.89
3.6
3.6
3.8
V
V
V
V
V
V
V
V
V
VDDSHV1_MCU
VDDSHV1
IO supply for MCUSS IO group 1 1.8 V
3.3 V
IO supply for MAIN domain IO
group 1
1.8 V
3.3 V
VDDSHV2_MCU
VDDSHV2
IO supply for MCUSS IO group 2 1.8 V
3.3 V
IO supply for MAIN domain IO
group 2
1.8 V
3.3 V
1.8 V
3.3 V
1.8 V
3.3 V
1.8 V
3.3 V
1.8 V
3.3 V
VDDSHV3
IO supply for MAIN domain IO
group 3
VDDSHV4
IO supply for MAIN domain IO
group 4
VDDSHV5
IO supply for MAIN domain IO
group 5
VDDSHV6
IO supply for MAIN domain IO
group 6
VPP_CORE
VPP_MCU
Supply voltage range for CORE EFUSE domain
Supply voltage range for MCU EFUSE domain
Voltage range for USB VBUS comparator input
Voltage range for USB VBUS comparator input
V
V
V
V
V
USB0_VBUS(9)
USB1_VBUS(9)
Steady State Max. Voltage at all fail-safe IO pins
I2C0_SCL,
I2C0_SDA,
I2C1_SCL,
I2C1_SDA,
WKUP_I2C0_SCL,
WKUP_I2C0_SDA,
MCU_I2C0_SCL,
MCU_I2C0_SDA,
EXTINTn
MCU_PORz, PORz
VMON_IR_VEXT
-0.3
-0.3
-0.3
3.8
2.2
V
V
V
Steady State Max. Voltage at all other IO pins(3)
VMON_ER_VSYS(7)
1.05
(8)
All other IO pins
–0.3 IO supply voltage + 0.3
V
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7.1 Absolute Maximum Ratings (continued)
over operating free-air temperature range (unless otherwise noted) (1) (2)
PARAMETER
MIN
MAX
UNIT
Transient Overshoot and Undershoot specification at IO pin
20% of IO supply
0.2 × VDD(6)
V
voltage for up to
20% of signal period
(see Figure 7-1,
IO Transient Voltage
Ranges)
Latch-up Performance, Class II (125°C)(4)
I-Test
-100
NA
100
mA
mV
Over-Voltage (OV)
Test
1.5 × VDD(6)
(5)
TSTG
Storage temperature
-55
+150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.4, Recommended
Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to their associated VSS or VSSA_x, unless otherwise noted.
(3) This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For
example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be
–0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used
to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range,
including power supply ramp-up and ramp-down sequences.
(4) For current pulse injection:
Pins stressed per JEDEC JESD78E (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times
maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.
For overvoltage performance:
Supplies stressed per JEDEC JESD78E (Class II) and passed specified voltage injection.
(5) For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. TI recommends returning
to ambient room temperature before usage.
(6) VDD is the voltage on the corresponding power-supply pin(s) for the IO.
(7) An external resistor divider is required to create the VMON input value that triggers with VTH = 0.45 when the VSYS level reaches the
minimum allowed threshold. A series resistor R2 (VMON_ER_VSYS = VSYS × R1 / (R1 + R2)) of at least 10kΩ is recommended to limit
current.
(8) The VMON_ER_VSYS pin provides a way to monitor the system power supply. For more information, see Section 9.3.5 System Power
Supply Monitor Design Guidelines.
(9) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 9.3.4, USB
VBUS Design Guidelines.
Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply
voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO
power supplies are turned off. The I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, DDR_FS_RESETn, and NMIn
are the only fail-safe IO terminals. All other IO terminals are not fail-safe and the voltage applied to them should
be limited to the value defined by the Steady State Max. Voltage at all IO pins parameter in Section 7.1.
Overshoot = 20% of nominal
IO supply voltage
Tovershoot
Tperiod
Tundershoot
Undershoot = 20% of nominal
IO supply voltage
A. Tovershoot + Tundershoot < 20% of Tperiod
Figure 7-1. IO Transient Voltage Ranges
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7.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
All pins
V(ESD)
Electrostatic discharge
V
Corner pins (A1,
AJ29)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Power-On-Hour (POH) Limits
IP(1) (2) (3)
VOLTAGE (V)
(MAX)
FREQUENCY
(MHz) (MAX)
VOLTAGE DOMAIN
Tj(°C)
POH
All
All
All
100%
100%
100%
All
All
All
All Supported OPPs
All Supported OPPs
All Supported OPPs
Automotive -40°C to 125°C(4)
Extended -40°C to 105°C
Commercial 0°C to 90°C
20000
100000
100000
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard
terms and conditions for TI semiconductor products.
(2) Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted
temperatures.
(3) POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH.
(4) Automotive profile is defined as 20000 power on hours with a junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C,
and 10%@125°C.
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
SUPPLY NAME(2)
DESCRIPTION
MIN(1)
0.76
0.76
0.76
NOM
0.8
MAX(1)
0.84
UNIT
VDD_CORE
Boot/Active voltage for MAIN domain core supply
Boot/Active voltage for MCUSS core supply
V
V
V
VDD_MCU
VDD_CPU
0.8
0.89
Boot voltage for CPU core supply, applied at cold
power up event
0.8
0.84
Active voltage for CPU core supply, after AVS mode
enabled in software
AVS(5)-5%
AVS(5) AVS(5)+5%
V
VDD_CPU AVS Range
VDDA_0P8_DLL_MMC0
VDDAR_CORE
AVS valid voltage range for VDD_CPU
MMC PLL analog supply
Main domain RAM supply
MCUSS RAM supply
0.6
0.76
0.81
0.81
0.81
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
1.71
1.71
0.9
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0.8
0.85
0.85
0.85
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
1.8
1.8
0.84
0.89
0.89
0.89
0.84
0.84
0.84
0.84
0.84
0.84
0.84
0.84
0.84
0.84
0.84
1.89
1.89
VDDAR_MCU
VDDAR_CPU
CPU RAM supply
VDDA_0P8_DP
Displayport SERDES clock supply
Displayport SERDES clock supply
DSITX clock supply
VDDA_0P8_DP_C
VDDA_0P8_DSITX
VDDA_0P8_DSITX_C
VDDA_0P8_CSIRX
VDDA_0P8_SERDES0_1
VDDA_0P8_SERDES2_3
VDDA_0P8_SERDES_C0_1
VDDA_0P8_SERDES_C2_3
VDDA_0P8_USB
DSITX clock supply
CSIRX analog supply low
SERDES0-1 analog supply low
SERDES2-3 analog supply low
SERDES0-1 clock supply
SERDES2-3 clock supply
USB0-1 0.8v analog supply
UFS analog supply low
VDDA_0P8_UFS
VDDA_1P8_USB
USB0-1 1.8v analog supply
UFS analog supply high
VDDA_1P8_UFS
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7.4 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
SUPPLY NAME(2)
DESCRIPTION
Displayport SERDES analog supply high
DSITX analog supply high
MIN(1)
1.71
1.71
1.71
1.71
1.71
3.14
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
0.76
1.71
1.71
1.71
0.76
1.71
NOM
1.8
1.8
1.8
1.8
1.8
3.3
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
0.8
1.8
1.8
1.8
0.8
1.8
MAX(1)
1.89
1.89
1.89
1.89
1.89
3.46
1.89
1.89
1.89
1.89
1.89
1.89
1.89
1.89
0.84
1.89
1.89
1.89
0.84
1.89
UNIT
V
VDDA_1P8_DP
VDDA_1P8_DSITX
VDDA_1P8_CSIRX
VDDA_1P8_SERDES0_1
VDDA_1P8_SERDES2_3
VDDA_3P3_USB
VDDA_MCU_PLLGRP0
VDDA_PLLGRP0
VDDA_PLLGRP1
VDDA_PLLGRP2
VDDA_PLLGRP3
VDDA_PLLGRP4
VDDA_PLLGRP5
VDDA_PLLGRP6
VDDA_0P8_PLL_MLB
VDDA_WKUP
V
CSIRX analog supply high
V
SERDES0-1 analog supply high
SERDES2-3 analog supply high
USB0-1 3.3v analog supply
V
V
V
Analog supply for MCU PLL Group 0
Analog supply for Main PLL Group 0
Analog supply for MAIN PLL Group 1
Analog supply for MAIN PLL Group 2
Analog supply for MAIN PLL Group 3
Analog supply for MAIN PLL Group 4
Analog supply for MAIN PLL Group 5 (DDR)
Analog supply for MAIN PLL Group 6
MLB PLL analog supply
V
V
V
V
V
V
V
V
V
Oscillator supply for wkup domain
ADC analog supply
V
VDDA_ADC0
V
VDDA_ADC1
ADC analog supply
V
VDDA_0P8_PLL_DDR
VDDA_MCU_TEMP
DDR PLL analog supply
V
Analog supply for temperature sensor 0 in MCU
domain
V
VDDA_POR_WKUP
VDDA_1P8_MLB
VDDA_TEMP0_1
VDDA_TEMP2_3
VDDS_DDR(3)
WKUP domain analog supply
MLB IO supply (6-pin interface)
Analog supply for temperature sensor 0 and 1
Analog supply for temperature sensor 2 and 3
DDR inteface power supply
1.71
1.71
1.71
1.71
1.06
1.06
1.06
1.71
1.71
1.71
3.14
1.71
3.14
1.8
1.8
1.8
1.8
1.1
1.1
1.1
1.8
1.8
1.8
3.3
1.8
3.3
1.89
1.89
1.89
1.89
1.15
1.15
1.15
1.89
1.89
1.89
3.46
1.89
3.46
V
V
V
V
V
V
V
V
V
V
V
V
V
VDDS_DDR_BIAS
VDDS_DDR_C
VDDS_MMC0
Bias supply for LPDDR4x
IO power for DDR Memory Clock Bit (MCB) macro
MMC0 IO supply
VDDS_OSC1
HFOSC1 supply
VDDSHV0
IO supply for main domain
general
1.8-V operation
3.3-V operation
1.8-V operation
3.3-V operation
VDDSHV0_MCU
IO supply MCUSS general IO
group, and MCU and Main
domain warm reset pins
VDDSHV1
IO supply for main domain IO
group 1
1.8-V operation
3.3-V operation
1.71
3.14
1.71
3.14
1.71
3.14
1.71
3.14
1.71
3.14
1.8
3.3
1.8
3.3
1.8
3.3
1.8
3.3
1.8
3.3
1.89
3.46
1.89
3.46
1.89
3.46
1.89
3.46
1.89
3.46
V
V
V
V
V
V
V
V
V
V
VDDSHV1_MCU
VDDSHV2
IO supply for MCUSS IO group 1 1.8-V operation
3.3-V operation
IO supply for main domain IO
group 2
1.8-V operation
3.3-V operation
VDDSHV2_MCU
VDDSHV3
IO supply for MCUSS IO group 2 1.8-V operation
3.3-V operation
IO supply for main domain IO
group 3
1.8-V operation
3.3-V operation
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7.4 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
SUPPLY NAME(2)
DESCRIPTION
MIN(1)
1.71
3.14
1.71
3.14
1.71
3.14
0
NOM
1.8
MAX(1)
1.89
3.46
1.89
3.46
1.89
3.46
3.46
3.46
UNIT
V
VDDSHV4
IO supply for main domain IO
group 4
1.8-V operation
3.3-V operation
1.8-V operation
3.3-V operation
1.8-V operation
3.3-V operation
3.3
V
VDDSHV5
VDDSHV6
IO supply for main domain IO
group 5
1.8
V
3.3
V
IO supply for main domain IO
group 6
1.8
V
3.3
V
USB0_VBUS
USB1_VBUS
USB0_ID
USB1_ID
VSS
Voltage range for USB VBUS comparator input
Voltage range for USB VBUS comparator input
Voltage range for the USB ID input
Voltage range for the USB ID input
Ground
See (6)
See (6)
See (4)
See (4)
0
V
0
V
V
V
V
TJ
Operating junction temperature
range
Automotive
Extended
-40
-40
0
125
105
90
°C
°C
°C
Commercial
(1) The voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth.
(2) Refer to Power-On-Hour (POH) Limits for limitations.
(3) VDDS_DDR is required to still be powered with LPDDR4 voltage ranges, even If DDR interface is unused.
(4) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the
voltage to determine if the terminal is connected to VSS with a resistance less than 10 Ω or greater than 100 kΩ. The terminal should
be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to any
external voltage source.
(5) The AVS Voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the
VTM_DEVINFO_VDn. For information about VTM_DEVINFO_VDn Registers address, please refer to Voltage and Thermal Manager
section in the device TRM. The power supply should be adjustable over the ranges shown in the VDD_CPU AVS Range entry.
(6) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 9.3.4, USB
VBUS Design Guidelines.
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7.5 Operating Performance Points
This section describes the operating conditions of the device. This section also contains the description of each
Operating Performance Point (OPP) for processor clocks and device core clocks.
Table 7-1 describes the maximum supported frequency per speed grade for the device.
Table 7-1. Speed Grade Maximum Frequency
MAXIMUM FREQUENCY (MHz)
DEVICE
MCU_
R5SS0
A72SS0
C66SS0
C71SS0
R5SS0/1
GPU
CBASS0
DMSC
LPDDR4
DRA829xT
2000
1350
1000
1000
1000
750
500
333
4266 MT/s(1)
(1) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.
7.6 Power Consumption Summary
For information on the device power consumption, contact your TI Sales Representative.
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7.7 Electrical Characteristics
Note
The interfaces or signals described in Section 7.7.1 through Section 7.7.9 correspond to the interfaces
or signals available in multiplexing mode 0 (Primary Function).
All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical
characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC
electrical characteristics are specified for the different multiplexing modes (Functions).
7.7.1 I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: WKUP_I2C0_SDA, WKUP_I2C0_SCL, MCU_I2C0_SDA, MCU_I2C0_SCL, I2C0_SDA, I2C0_SCL, I2C1_SDA,
I2C1_SCL, EXTINTN
BALL NUMBERS:H24 / J25 / H25 / J26 / AA5 / AC5 / AA6 / Y6 / AC18 H24/ J25 / H25 / J26 / AA5 / AC5 / AA6 / Y6 / AC18
1.8-V MODE
VIL
Input low-level threshold
0.3 ×
V
V
VDDSHV(1)
VILSS
VIH
VIHSS
VHYS
Input low-level threshold steady state
Input high-level threshold
0.3 ×
VDDSHV(1)
0.7 ×
V
VDDSHV(1)
Input high-level threshold steady state
Input Hysteresis Voltage
0.7 ×
V
VDDSHV(1)
0.1 ×
mV
VDDSHV(1)
IIN
Input Leakage Current
Output low-level voltage
VI = 1.8 V or 0 V
±10
µA
V
VOL
0.2 ×
VDDSHV(1)
IOL
Low Level Output Current
VOL(MAX)
6
mA
3.3-V MODE
VIL
Input low-level threshold
0.3 ×
V
V
VDDSHV(1)
VILSS
VIH
VIHSS
VHYS
Input low-level threshold steady state
Input high-level threshold
0.25 ×
VDDSHV(1)
0.7 ×
V
VDDSHV(1)
Input high-level threshold steady state
Input Hysteresis Voltage
0.7 ×
V
VDDSHV(1)
0.05 ×
mV
VDDSHV(1)
IIN
Input Leakage Current
Output low-level voltage
VI = 3.3 V or 0 V
±10
µA
V
VOL
0.4 ×
VDDSHV(1)
IOL
Low Level Output Current
VOL(MAX)
6
mA
(1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see
Section 6.2, Pin Attributes, POWER column.
7.7.2 Fail-Safe Reset (FS Reset) Electrical Characteristics
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: MCU_PORz, PORz
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Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BALL NUMBERS:H23 / J24
VIL
Input low-level threshold
0.3 ×
V
V
V
V
VDDSHV(1)
VILSS
VIH
Input low-level threshold steady state
Input high-level threshold
0.3 ×
VDDSHV(1)
0.7 ×
VDDSHV(1)
VIHSS
Input high-level threshold steady state
0.7 ×
VDDSHV(1)
VHYS
IIN
Input Hysteresis Voltage
Input Leakage Current
200
mV
µA
VI = 1.8 V or 0 V
±10
(1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see
Section 6.2, Pin Attributes, POWER column.
7.7.3 HFOSC/LFOSC Electrical Characteristics
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HIGH FREQUENCY OSCILLATOR
BALL NAMES: WKUP_OSC0_XO, WKUP_OSC0_XI, OSC1_XO, OSC1_XI
BALL NUMBERS:M27 / M29 / P27 / P29
VIH
Input high-level threshold
Input low-level threshold
Input Hysteresis Voltage
0.65 ×
V
V
VDDSHV(1)
VIL
0.35 ×
VDDSHV(1)
VHYS
49
mV
LOW FREQUENCY OSCILLATOR
BALL NAMES: WKUP_LFOSC0_XO, WKUP_LFOSC0_XI
BALL NUMBERS:N26 / N28
VIH
Input high-level threshold
Input low-level threshold
Input Hysteresis Voltage
0.65 ×
V
V
VDDA_WKUP
(1)
VIL
0.35 ×
VDDA_WKUP
(1)
VHYS
Active Mode
85
mV
mV
Bypass Mode
324
(1) VDDSHV stands for corresponding power supply. For WKUP_OSC0, the corresponding power supply is VDDA_WKUP. For OSC1_XI,
the corresponding power supply is VDDS_OSC1.
7.7.4 eMMCPHY Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
BALL NAMES in Mode 0: MMC0_DAT[7:0], MMC0_CALPAD, MMC0_CMD, MMC0_DS, MMC0_CLK
BALL NUMBERS:AG2 / AH1 / AG3 / AF4 / AE5 / AF3 / AG1 / AF2 / AE1 / AE3 / AE4 / AF1
VIL
Input low-level threshold
0.35 ×
V
VDDSHV(1)
VILSS
VIH
Input low-level threshold steady state
Input high-level threshold
0.20
V
V
0.65 ×
VDDSHV(1)
VIHSS
Input high-level threshold steady state
1.4
V
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Over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input Leakage Current
Tri-state Output Leakage Current
Pull-up Resistor
TEST CONDITIONS
MIN
NOM
MAX
±10
±10
25
UNIT
µA
µA
kΩ
kΩ
V
IIN
VI = 1.8 V or 0 V
IOZ
VO = 1.8 V or 0 V
RPU
RPD
VOL
VOH
15
15
20
20
Pull-down Resistor
25
Output low-level voltage
Output high-level voltage
0.30
VDDSHV -
0.30(1)
V
IOL
Low Level Output Current
High Level Output Current
Input Slew Rate
VOL(MAX)
VOH(MAX)
2
2
mA
mA
V/s
IOH
SRI
5E +8
(1) VDDSHV stands for corresponding power supply (vddshv8). For more information on the power supply name and the corresponding
ball, see Section 6.2, Pin Attributes, POWER column.
7.7.5 SDIO Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
BALL NAMES in Mode 0: MMC1_CLK, MMC1_CMD, MMC1_DAT[3:0], MMC2_CLK, MMC2_CMD, MMC2_DAT[3:0]
BALL NUMBERS:P25 / R29 / R24 / P24 / R25 / R26 / T26 / T25 / T24 / T27 / T29 / T28
1.8-V MODE
VIL
Input low-level threshold
Input low-level threshold steady state
Input high-level threshold
Input high-level threshold steady state
Input Hysteresis Voltage
Input Leakage Current
0.58
0.58
V
V
VILSS
VIH
1.27
1.7
V
VIHSS
VHYS
IIN
V
150
mV
µA
kΩ
kΩ
V
VI = 1.8 V or 0 V
±10
60
RPU
RPD
VOL
VOH
Pull-up Resistor
40
40
50
50
Pull-down Resistor
60
Output low-level voltage
Output high-level voltage
0.45
VDDSHV-
0.45(1)
V
IOL
Low Level Output Current
High Level Output Current
VOL(MAX)
VOH(MAX)
4
4
mA
mA
IOH
3.3-V Mode
VIL
Input low-level threshold
0.25 ×
V
V
V
V
VDDSHV(1)
VILSS
VIH
Input low-level threshold steady state
Input high-level threshold
0.15 ×
VDDSHV(1)
0.625 ×
VDDSHV(1)
VIHSS
Input high-level threshold steady state
0.625 ×
VDDSHV(1)
VHYS
IIN
Input Hysteresis Voltage
Input Leakage Current
Pull-up Resistor
150
mV
µA
kΩ
kΩ
V
VI = 1.8 V or 0 V
±10
60
RPU
RPD
VOL
40
40
50
50
Pull-down Resistor
60
Output low-level voltage
0.125 ×
VDDSHV(1)
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Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VOH
Output high-level voltage
0.75 ×
V
VDDSHV(1)
IOL
IOH
Low Level Output Current
High Level Output Current
VOL(MAX)
VOH(MAX)
6
mA
mA
10
(1) VDDSHV stands for corresponding power supply (vddshv8). For more information on the power supply name and the corresponding
ball, see Section 6.2, Pin Attributes , POWER column.
7.7.6 CSI2/DSI D-PHY Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
BALL NAMES in Mode 0: CSI0_RXCLKN, CSI0_RXCLKP, CSI0_RXRCALIB, CSI0_RXN[3:0], CSI0_RXP[3:0], CSI1_RXCLKN,
CSI1_RXCLKP, CSI1_RXRCALIB, CSI1_RXN[3:0], CSI1_RXP[3:0], DSI_TXCLKN, DSI_TXCLKP, DSI_TXN[3:0], DSI_TXP [3:0],
DSI_TXRCALIB
BALL NUMBERS: A14 / A15 / A17 / A18 / A20 / A21 / B13 / B14 / B16 / B17 / B19 / B20 / C12 / C13 / C15 / C16 / C18 / C19 / D11 / D12 /
D14 / D15 / D17 / D18 / E10 / E11 / E13 / E14 / E16 / E17 / F12 / F15 / F16
Low-Power Receiver (LP-RX)
VIH
Input high-level threshold
Input low-level threshold
Hysteresis
740
25
mV
mV
mV
VIL
550
300
VHYS
Ultra-Low Power Receiver (ULP-RX)
VITH
Input high-level threshold
Input low-level threshold
Hysteresis
740
25
mV
mV
mV
VITL-ULPM
VHYS
High Speed Receiver (HS-RX)
VIDTH
Differential input high-level threshold
40
mV
mV
mV
mV
mV
mV
VIDTL
Differential input low-level threshold
Maximum differential input voltage
Single-ended input low-level threshold
Single-ended input high-level threshold
Common-mode voltage
-40
-40
70
VIDMAX
VILHS
270
VIHHS
460
330
VCMRXDC
7.7.7 ADC12B Electrical Characteristics
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: MCU_ADC0_AIN[7:0], MCU_ADC1_AIN[7:0]
BALL NUMBERS:K24 / K25 / K26 / K27 / K28 / K29 / L24 / L25 / L26 / L27 / L28 / L29 / M24 / M25 / N23 / N24
Analog Input
VMCU_ADC Full-scale Input Range
VSS
-1
VDDA_ADC0/
1
V
0/1_AIN[7:0]
DNL
INL
Differential Non-Linearity
Integral Non-Linearity
0.5
±1
±2
4
LSB
LSB
LSB
±4
LSBGAIN- Gain Error
ERROR
LSBOFFSE Offset Error
±2
LSB
T-ERROR
CIN
Input Sampling Capacitance
Signal-to-Noise Ratio
5.5
70
pF
dB
SNR
Input Signal: 200
kHz sine wave at
-0.5 dB Full Scale
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Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THD
Total Harmonic Distortion
Input Signal: 200
kHz sine wave at
-0.5 dB Full Scale
73
dB
SFDR
Spurious Free Dynamic Range
Input Signal: 200
kHz sine wave at
-0.5 dB Full Scale
76
69
dB
dB
Ω
SNR(PLUS) Signal-to-Noise Plus Distortion
Input Signal: 200
kHz sine wave at
-0.5 dB Full Scale
RMCU_ADC Input Impedance of MCU_ADC0/1_AIN[7:0] f = input frequency
[1/((65.97 ×
10–-12) ×
0/1_AIN[0:7]
fSMPL_CLK)]
IIN
Input Leakage
MCU_ADC0/1_AIN[7
:0] = VSS
-10
24
μA
μA
MCU_ADC0/1_AIN[7
:0] = VDDA_ADC0/1
Sampling Dynamics
FSMPL_CLK SMPL_CLK Frequency
60
13
MHz
tC
Conversion Time
ADC0/1
SMPL_CL
K Cycles
tACQ
Acquisition time
2
257 ADC0/1
SMPL_CL
K Cycles
TR
Sampling Rate
ADC0/1 SMPL_CLK
= 60 MHz
4
MSPS
CCISO
Channel to Channel Isolation
100
dB
General Purpose Input Mode(1)
VIL
Input low-level threshold
0.35 ×
VDDA_ADC0/
1
V
V
V
V
VILSS
Input high-level threshold steady state
Input high-level threshold
0.35 ×
VDDA_ADC0/
1
VIH
0.65 ×
VDDA_ADC0/
1
VIHSS
Input high-level threshold steady state
0.65 ×
VDDA_ADC0/
1
VHYS
IIN
Input Hysteresis Voltage
Input Leakage Current
200
mV
µA
VI = 1.8 V or 0 V
6
(1) MCU_ADC0/1 can be configured to operate in General Purpose Input mode, where all MCU_ADC0/1_AIN[7:0] inputs are globally
enabled to operate as digital inputs via the ADC0/1_CTRL register (gpi_mode_en = 1).
7.7.8 MLB LVCMOS Electrical Characteristics
Only GPIO mode supported. Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
UNIT
MIN
TYP
MAX
BALL NAMES in Mode 0: MLB0_MLBSN, MLB0_MLBDP, MLB0_MLBSP, MLB0_MLBCP, MLB0_MLBDN, MLB0_MLBCN
BALL NUMBERS:AC1 / AC3 / AD1 / AD2 / AD3 / AE2
VIL
Input Low Voltage
0.3 × VDD(1)
0.3 × VDD(1)
V
V
VILSS
Input Low Voltage Steady State
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Only GPIO mode supported. Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
UNIT
MIN
TYP
MAX
VIH
Input High Voltage
0.7 × VDD(1)
0.75 × VDD(1)
80
V
VIHSS
VHYS
IIN
Input High Voltage Steady State
Input Hysteresis Voltage
Input Leakage Current
Pull-down Resistor
V
mV
VI = 1.8 V or 0 V
±10 µA
RPD
VOL
VOH
IOL
20
53
130 kΩ
0.2 V
V
Output Low Voltage
Output High Voltage
VDD(1) - 0.2
Low Level Output Current
High Level Output Current
VOL(MAX)
6
6
mA
IOH
VOH(MIN)
mA
fop > 100 MHz
fop < 1 MHz
1
V/ns
V/ns
SRI
Input Slew Rate(2)
10
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Section
6.2, Pin Attributes , POWER column.
(2) Slew rate may be further limited, reference Section 7.10for actual slew rate during operation
7.7.9 LVCMOS Electrical Characteristics
Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
BALL NAMES: ALL other IOs
BALL NUMBERS: ALL other IOs
1.8-V MODE
VIL
Input Low Voltage
0.35 × VDD(1)
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
0.3 × VDD(1)
0.65 × VDD(1)
0.85 × VDD(1)
150
V
VIHSS
VHYS
IIN
Input High Voltage Steady State
Input Hysteresis Voltage
Input Leakage Current.
Pull-up Resistor
V
mV
µA
kΩ
kΩ
V
VI = 1.8 V or 0 V
±10
30
RPU
RPD
VOL
VOH
IOL
15
15
22
22
Pull-down Resistor
30
Output Low Voltage
0.45
Output High Voltage
VDD(1) - 0.45
V
Low Level Output Current
High Level Output Current
VOL(MAX)
VOH(MIN)
3
3
mA
mA
IOH
3.3-V MODE
VIL
Input Low Voltage
0.8
0.6
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
2.0
2.0
V
VIHSS
VHYS
IIN
Input High Voltage Steady State
Input Hysteresis Voltage
Input Leakage Current.
Pull-down Resistor
V
150
mV
µA
kΩ
V
VI = 3.3 V or 0 V
±10
30
RPD
VOL
VOH
IOL
15
22
Output Low Voltage
0.4
Output High Voltage
2.4
5
V
Low Level Output Current
VOL(MAX)
mA
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Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IOH
High Level Output Current
VOH(MIN)
6
mA
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Section
6.2, Pin Attributes , POWER column.
7.7.10 USB2PHY Electrical Characteristics
Note
USB0 and USB1 Electrical Characteristics are compliant with Universal Serial Bus Revision 2.0
Specification dated April 27, 2000 including ECNs and Errata as applicable.
7.7.11 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
Note
The PCIe interfaces are compliant with the electrical parameters specified in PCI Express® Base
Specification Revision 4.0, September 27, 2017.
This Device imposes an additional limit on SERDES REFCLK when used in Input mode with internal
termination enabled, as described by parameter VREFCLK_TERM in Table 7-2, 4-L-PHY SERDES
REFCLK Electrical Characteristics. Internal termination is enabled by default and must be disabled
before applying a reference clock signal that exceeds the limits defined by VREFCLK_TERM. External
termination should always be enabled on the source side.
Table 7-2. 4-L-PHY SERDES REFCLK Electrical Characteristics
Only applies when internal termination is enabled. Over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: SERDES4_REFCLK_P, SERDES4_REFCLK_N
BALL NUMBERS:E8 / E7
VREFCLK_TER Single ended voltage threshold at the reference clock
400
mV
Ω
pin when internal termination is enabled
M
RTERM
Internal termination
40
50
62.5
Note
The SerDes USB interfaces are compliant with the USB3.1 SuperSpeed Transmitter and Receiver
Normative Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision
1.0 , July 26, 2013.
Note
The SGMII interfaces electrical characteristics are compliant with 1000BASE-KX per IEEE802.3
Clause 70.
Note
The SGMII 2.5G / XAUI interfaces electrical characteristics are compliant with IEEE802.3 Clause 47.
Note
The QSGMII interface electrical characteristics are compliant with QSGMII Specification revision 1.2.
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Note
The UFS interface electrical characteristics are compliant with MIPI M-PHY Specification v3.1,
February 17, 2014.
Note
The DP interface electrical characteristics are compliant with the VESA DisplayPort (DP) Standard v
1.4 February 23, 2016.
Note
The eDP interface electrical characteristics are compliant with the VESA Embedded DisplayPort
(eDP) Standard v1.4b October 23, 2015.
7.7.14 DDR0 Electrical Characteristics
Note
The DDR interface is compatible with JESD209-4B standard compliant LPDDR4 SDRAM devices.
7.8 VPP Specifications for One-Time Programmable (OTP) eFuses
This section specifies the operating conditions required for programming the OTP eFuses and is applicable only
for High-Security Devices.
7.8.1 Recommended Operating Conditions for OTP eFuse Programming
over operating free-air temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
MIN
NOM
See Section 7.4
MAX
UNIT
VDD_CORE
Supply voltage range for the core domain
during OTP operation; OPP NOM (BOOT)
V
VDD_MCU
Supply voltage range for the core domain
during OTP operation; OPP NOM (BOOT)
See Section 7.4
N/A(2)
V
V
V
VPP_CORE
Supply voltage range for the eFuse ROM
domain during normal operation
Supply voltage range for the eFuse ROM
domain during OTP programming(1)
1.71
1.71
1.8
1.89
1.89
VPP_MCU
Supply voltage range for the eFuse ROM
domain during normal operation
N/A(2)
Supply voltage range for the eFuse ROM
domain during OTP programming(1)
1.8
(1) Supply voltage range includes DC errors and peak-to-peak noise. TI power management solutions TLV70018-Q1 from the TLV707x
family meet the supply voltage range needed for VPP_CORE and VPP_MCU.
(2) N/A stands for Not Applicable.
7.8.2 Hardware Requirements
The following hardware requirements must be met when programming keys in the OTP eFuses:
•
•
The VPP_CORE and VPP_MCU power supplies must be disabled when not programming OTP registers.
The VPP_CORE and VPP_MCU power supplies must be ramped up after the proper device power-up
sequence (for more details, see Section 7.10.2).
7.8.3 Programming Sequence
Programming sequence for OTP eFuses:
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•
•
•
Power on the board per the power-up sequencing. No voltage should be applied on the VPP_CORE and
VPP_MCU terminals during power up and normal operation.
Load the OTP write software required to program the eFuse (contact your local TI representative for the OTP
software package).
Apply the voltage on the VPP_CORE and VPP_MCU terminals according to the specification in Section
7.8.1.
•
•
Run the software that programs the OTP registers.
After validating the content of the OTP registers, remove the voltage from the VPP_CORE and VPP_MCU
terminals.
7.8.4 Impact to Your Hardware Warranty
You recognize and accept at your own risk that your use of eFuse permanently alters the TI device. You
acknowledge that eFuse can fail due to incorrect operating conditions or programming sequence. Such a failure
may render the TI device inoperable and TI will be unable to confirm the TI device conformed to TI device
specifications prior to the attempted eFuse. CONSEQUENTLY, TI WILL HAVE NO LIABILITY FOR ANY TI
DEVICES THAT HAVE BEEN eFUSED.
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7.9 Thermal Resistance Characteristics
This section provides the thermal resistance characteristics used on this device.
For reliability and operability concerns, the maximum junction temperature of the device has to be at or below
the TJ value identified in Section 7.4, Recommended Operating Conditions.
7.9.1 Thermal Resistance Characteristics for ALF Package
It is recommended to perform thermal simulations at the system level with the worst case device power consumption.
ALF PACKAGE
NO.
PARAMETER
DESCRIPTION
AIR FLOW
(m/s)(2)
°C/W(1)(3)
T1
RΘJC
Junction-to-case
Junction-to-board
Junction-to-free air
0.25
2.1
11.5
7.4
6.5
6
N/A
N/A
0
T2
RΘJB
T3
T4
1
RΘJA
T5
Junction-to-moving air
2
T6
3
T7
0.1
0.1
0.1
0.1
1.6
1.7
1.6
1.5
0
T8
1
ΨJT
Junction-to-package top
T9
2
T10
T11
T12
T13
T14
3
0
1
ΨJB
Junction-to-board
2
3
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Packages
(2) m/s = meters per second.
(3) °C/W = degrees Celsius per watt.
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7.10 Timing and Switching Characteristics
Note
The default SLEWRATE settings in each pad configuration register must be used to ensure timings,
unless specific instructions are given otherwise.
7.10.1 Timing Parameters and Information
The timing parameter symbols used in Section 7.10 are created in accordance with JEDEC Standard 100. To
shorten the symbols, some pin names and other related terminologies have been abbreviated in Table 7-3:
Table 7-3. Timing Parameters Subscripts
SYMBOL
PARAMETER
Cycle time (period)
Delay time
c
d
dis
en
h
Disable time
Enable time
Hold time
su
START
t
Setup time
Start bit
Transition time
Valid time
v
w
Pulse duration (width)
Unknown, changing, or don't care level
Fall time
X
F
H
High
L
Low
R
Rise time
V
Valid
IV
AE
FE
LE
Z
Invalid
Active Edge
First Edge
Last Edge
High impedance
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7.10.2 Power Supply Sequencing
This section describes power supply sequencing required to ensure proper device operation. The device can be
operated using either an isolated or combined MCU & Main power distribution network (PDN). Two different
primary power sequences are recommended based upon isolated and combined MCU & Main PDNs. In
addition, the device can be operated in either MCU Only or DDR Retention low power modes. Two different
desired device power supply sequences for entry and exit of low power modes are shown.
The power supply names used in this section are specific to this device and align to names given in the Signal
Descriptions section. Common power supply names may be used across different devices within the Jacinto 7TM
processor family. These common supply names will have very similar if not identical functions across devices.
All power sequencing timing diagrams shown will use the following terminology:
•
•
Primary = Essential power sequences of all voltage domains between off and full active states.
VOPR MIN = Minimum operational voltage level that ensures functionality as specified in Recommended
Operating Conditions
•
•
•
Ramp-up = start of a voltage supply transition time from off condition to Vopr min.
Ramp-down = start of a voltage supply transition time from Vopr to off condition
Supply_“n” = multiple instances of similar power supplies (i.e. VDDSHVn = VDDSHV0, VDDSHV1,
VDDSHV2 … VDDSHV6)
•
•
Supply_“xxx” = multiple instances of similar power supplies used for different signal types (i.e.
VDDA_1P8_xxx = VDDA_1P8_DSITX, VDDA_1P8_USB, VDDA_0P8_DSITX, VDDA_0P8_USB, etc.)
Time stamps = “T#” markers with descriptions and approximate elapsed times for general reference. Specific
timing transitions are dependent upon PDN design (see PDN User Guide for details).
7.10.2.1 Power Supply Slew Rate Requirement
To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the
maximum slew rate of supplies to be less than 100 mV/us, as shown in Figure 7-2. For instance, a 1.8V supply
should have a ramp time > 18 μs to ensure the slew rate < 100mV/us.
Figure 7-2 describes the Power Supply Slew Rate Requirement in the device.
Supply value
t
Slew Rate = ∆V / ∆T
Max Slew Rate < 100 mV / µs or 0.1 V / 1E(-6)s = 1E(+5) V / s
∆Tmin > ∆V / Max Slew Rate or 1.8 V / 1E(+5) V / s
∆Tmin > 18 µs
SPRSP08_ELCH_06
Figure 7-2. Power Supply Slew and Slew Rate
7.10.2.2 Combined MCU and Main Domains Power-Up Sequencing
Figure 7-3 describes the primary power-up sequencing when similar MCU and Main voltage domains are
combined into common power rails. Combining MCU and Main voltage domains simplifies PDN design by
reducing total number of power rails and sources while making MCU and Main processor sub-systems
operational dependent on common power rails. Table 9-1 in Section 9.1, Power Supply Mapping captures
recommended device power supply groups to power rail mapping summary.
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T0
T1
T2
T3
T4
Note 2
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,
VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5(4), VDDSHV6)(2), VDDA_3P3_USB(5)
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,
VDDSHV0, VDDSHV1, VDDSHV2,
VDDSHV3, VDDSHV4, VDDSHV5(4), VDDSHV6)(3),VDDS_MMC0(7)
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,
VDDSHV0, VDDSHV1, VDDSHV2,
VDDSHV3, VDDSHV4, VDDSHV5(4), VDDSHV6)(3),VDDS_MMC0(7)
(VDDA_1P8_CSIRX, VDDA_1P8_UFS, VDDA_1P8_USB,
VDDA_1P8_DP, VDDA_1P8_DSITX, VDDA_1P8_MLB,
VDDA_1P8_SERDES0_1, VDDA_1P8_SERDES2_3)(6)
VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC0,
VDDA_ADC1, VDDA_POR_WKUP, VDDA_WKUP,
VDDS_OSC1, VDDA_PLLGRP0, VDDA_PLLGRP1,
VDDA_PLLGRP2, VDDA_PLLGRP3, VDDA_PLLGRP4, VDDA_PLLGRP5,
VDDA_PLLGRP6, VDDA_TEMP0_1, VDDA_TEMP2_3
VDD_CPU
VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0, VDDA_0P8_PLL_MLB(10)
VDD_MCU(8), VDD_CORE, (VDDA_0P8_SERDES0_1,
VDDA_0P8_SERDES2_3, VDDA_0P8_SERDES_C0_1,
VDDA_0P8_SERDES_C2_3, VDDA_0P8_DP, VDDA_0P8_DP_C,
VDDA_0P8_CSIRX, VDDA_0P8_UFS, VDDA_0P8_USB,
VDDA_0P8_DSITX, VDDA_0P8_DSITX_C)(9)
VDD_MCU(8), VDDAR_CORE, VDDAR_CPU, VDDAR_MCU
VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS
WKUP_OSC0_XI, WKUP_OSC1_XO
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
OSC1_XI, OSC1_XO
(optional)
MCU_BOOTMODE[9:0], BOOTMODE[7:0](11)
PORz, MCU_PORz(11)(12)
Valid Configuration
J7ES_ELCH_01
Figure 7-3. Combined MCU and Main Domains, Primary Power-Up Sequence
1. Time Stamp Markers
T0 – 3.3V voltages start ramp-up to VOPR MIN. (0ms)
T1 – 1.8V voltages start ramp-up to VOPR MIN. (2ms)
T2 – Low voltage core supplies start ramp-up to VOPR MIN. (3ms)
T3 – Low voltage RAM array voltages start ramp-up to VOPR MIN. (4ms)
T4 – OSC1 is stable and PORz/MCU_PORz are de-asserted to release processor from reset. (13ms)
2. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to
support 3.3V digital interfaces. A few supplies could have varying start times between T0 to T1 due to PDN
designs using different power resources with varying turn-on & ramp-up time delays.
3. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to
support 1.8V digital interfaces. When eMMC memories are used, Main 1.8V supplies could have a ramp-up
aligned to T3 due to PDN designs grouping supplies with VDD_MMC0.
4. VDDSHV5 supports MMC1 signaling for SD memory cards. If compliant high-speed SD card operation is
needed, then an independent, dual voltage (3.3V/1.8V) power source and rail are required. The start of
ramp-up to 3.3V will be same as other 3.3V domains as shown. If SD card is not needed or standard data
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rates with fixed 3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a
SD card is capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail.
5. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise,
analog supply is recommended to provide best signal integrity for USB data eye mask compliance. The start
of ramp-up to 3.3V will be same as other 3.3V domains as shown. If USB interface is not needed or data bit
errors can be tolerated, then domain can be grouped with 3.3V digital IO power rail either directly or through
a supply filter.
6. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog
supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of
these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains
can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed.
7. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface. If MMC0 or eMMC0
interface is not needed, then domain can be grouped with digital IO 1.8V power rail with power up time
stamp at T1. However, if MMC0 interface is needed, then VDD_MMC0 must not start ramp-up until time
stamp T3 after VDD_CORE has reached VOPR MIN. Any MCU or Main dual voltage IO operating at 1.8V can
be grouped with VDD_MMC0 into a common power rail with power up time stamp T3.
8. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility,
enabling it to be grouped and ramped-up with either 0.8V VDD_CORE at time stamp T2 or 0.85V RAM array
domains (VDDAR_xxx) at time stamp T3.
9. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry
needing a low noise supply for optimal performance. It is not recommended to combine analog
VDDA_1P8_<phy> domains or digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency
switching noise could negatively impact jitter performance of clock, PLL and DLL signals.
10. VDDA_0P8_<dll/pll> are 0.8V analog domains supporting PLL and DLL circuitry needing a low noise supply
for optimal performance. It is not recommended to combine these domains with any other 0.8V domains
since high frequency switching noise could negatively impact jitter performance of PLL and DLL signals.
11. Minimum set-up and hold times shown with respect to MCU_PORz and PORz asserting high to latch
MCU_BOOTMODEn (referenced to MCU_VDDSHV0) and BOOTMODEn (reference to VDDSHV2) settings
into registers during power up sequence.
12. Minimum elapsed time from crystal oscillator circuitry being energized (VDDS_OSC1 at T1) until stable clock
frequency is reached depends upon on crystal oscillator, capacitor parameters and PCB parasitic values.
A conservative 10ms elapsed time defined by (T4 – T1) time stamps is shown. This could be reduced
depending upon customer’s clock circuit (that is, crystal oscillator or clock generator) and PCB designs.
7.10.2.3 Combined MCU and Main Domains Power- Down Sequencing
Figure 7-4 describes the device power-down sequencing.
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T0
T1
T2
T3
T4
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,
VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5, VDDSHV6)(2), VDDA_3P3_USB(5)
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,
VDDSHV0, VDDSHV1, VDDSHV2,
VDDSHV3, VDDSHV4, VDDSHV5(4), VDDSHV6)(3),VDDS_MMC0(7)
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,
VDDSHV0, VDDSHV1, VDDSHV2,
VDDSHV3, VDDSHV4, VDDSHV5(4), VDDSHV6)(3),VDDS_MMC0(7)
(VDDA_1P8_CSIRX, VDDA_1P8_UFS, VDDA_1P8_USB,
VDDA_1P8_DP, VDDA_1P8_DSITX, VDDA_1P8_MLB,
VDDA_1P8_SERDES0_1, VDDA_1P8_SERDES2_3)(6)
VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC0,
VDDA_ADC1, VDDA_POR_WKUP, VDDA_WKUP,
VDDS_OSC1, VDDA_PLLGRP0, VDDA_PLLGRP1,
VDDA_PLLGRP2, VDDA_PLLGRP3, VDDA_PLLGRP4, VDDA_PLLGRP5,
VDDA_PLLGRP6, VDDA_TEMP0_1, VDDA_TEMP2_3
VDD_CPU
VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0, VDDA_0P8_PLL_MLB
VDD_MCU(8), VDD_CORE, (VDDA_0P8_SERDES0_1,
VDDA_0P8_SERDES2_3, VDDA_0P8_SERDES_C0_1,
VDDA_0P8_SERDES_C2_3, VDDA_0P8_DP, VDDA_0P8_DP_C,
VDDA_0P8_CSIRX, VDDA_0P8_UFS, VDDA_0P8_USB,
VDDA_0P8_DSITX, VDDA_0P8_DSITX_C)(9)
VDD_MCU(8),VDDAR_CORE, VDDAR_MCU, VDDAR_CPU
VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS
OSC1_XI, OSC1_XO
WKUP_OSC0_XI, WKUP_OSC0_XO
(optional)
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
MCU_BOOTMODE[9:0], BOOTMODE[7:0]
PORz, MCU_PORz(10)
TΔ1
J7ES_ELCH_02
Figure 7-4. Combined MCU and Main Domains, Primary Power-Down Sequence
1. Time Stamp Markers
T0 – MCU_PORz & PORz assert low to put all processor resources in safe state. (0ms)
T1 – Main DDR, SRAM Core & SRAM CPU power supplies start ramp-down. (0.5ms)
T2 – Low voltage core supplies start supply ramp-down. (2.5ms)
T3 - 1.8V voltages start supply ramp-down. (3.0ms)
T4 – 3.3V voltages start supply ramp-down. (3.5ms)
2. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to
support 3.3V digital interfaces
3. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to
support 1.8V digital interfaces. When eMMC memories are used, Main 1.8V supplies could have a ramp-
down aligned to T1 due to PDN designs grouping supplies with VDD_MMC0.
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4. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3V/1.8V) power rail is required
for compliant, high-speed SD card operations. If compliant highspeed SD card operation is needed, then
an independent, dual voltage (3.3V/1.8V) power source and rail are required. The start of ramp-down from
3.3V/1.8V will be same as other 3.3V domains as shown. If SD card is not needed or standard data rates
with fixed 3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a SD
card is capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail.
5. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise,
analog supply is recommended to provide best signal integrity for USB data eye mask compliance. The start
of ramp-down from 3.3V will be same as other 3.3V domains as shown. If USB interface is not needed or
data bit errors can be tolerated, then domain can be grouped with 3.3V digital IO power rail either directly or
through a supply filter.
6. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog
supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of
these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains
can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed.
7. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface and must ramp-down at
time stamp T1 before VDD_CORE starts ramp-down. Any MCU or Main dual voltage IO operating at 1.8V
can be grouped with VDD_MMC0 into a common power rail with power down time stamp T1. If MMC0 or
eMMC0 interface is not needed, then domain can be grouped with digital IO 1.8V power rail and ramp-down
at time stamp T3.
8. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility,
enabling it to be grouped and ramped-down with either 0.8V VDD_CORE at time stamp T2 or 0.85V RAM
array domains (VDDAR_xxx) at time stamp T1.
9. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry
needing a low noise supply for optimal performance. It is not recommended to combine analog
VDDA_1P8_<phy> domains or digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency
switching noise could negatively impact jitter performance of clock, PLL and DLL signals.
10. MCU_PORz and PORz must be asserted low for TΔ1 = 200us min to ensure SoC resources enter into safe
state before any voltage begins to ramp down.
7.10.2.4 Isolated MCU and Main Domains Power- Up Sequencing
Isolated MCU and Main voltage domains enable an SoC’s MCU and Main processor sub-systems to operate
independently. There are 2 reasons an SoC’s PDN design may need to support independent MCU and Main
processor functionality. First is to provide flexibility to enable SoC low power modes that can significant reduce
SoC power dissipation when processor operations are not needed. Second is to enable robustness to gain
freedom from interference (FFI) of a single fault impacting both MCU and Main processor sub-systems which
is especially beneficial if using the SoC’s MCU as the system safety monitoring processor. The number of
additional PDN power rails needed is dependent upon number of different MCU IO signaling voltage levels.
If only 1.8V IO signaling is used, the only 2 additional power rails could be required. If both 1.8 and 3.3V IO
signaling is desired, then 4 additional power rails could be needed. Table 9-2 in Section 9.1, Power Supply
Mapping captures recommended device power supplies to power rail mapping summary.
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T0
T1
T2
T3
T4
Note 2
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)(2)
Note 2
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5(4), VDDSHV6)(2),VDDA_3P3_USB(5)
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)(3)
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5(4), VDDSHV6)(3),VDDS_MMC0(7)
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5(4), VDDSHV6)(3),VDDS_MMC0(7)
VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC0,
VDDA_ADC1, VDDA_POR_WKUP, VDDA_WKUP
VDDS_OSC1, VDDA_PLLGRP0,
VDDA_PLLGRP1, VDDA_PLLGRP2,
VDDA_PLLGRP3, VDDA_PLLGRP4, VDDA_PLLGRP5,
VDDA_PLLGRP6, VDDA_TEMP0_1, VDDA_TEMP2_3,
(VDDA_1P8_CSIRX, VDDA_1P8_UFS, VDDA_1P8_USB,
VDDA_1P8_DP, VDDA_1P8_DSITX, VDDA_1P8_MLB,
VDDA_1P8_SERDES0_1, VDDA_1P8_SERDES2_3)(6)
VDD_MCU(8), VDDAR_MCU
VDD_CPU
VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0, VDDA_0P8_PLL_MLB(10)
VDD_CORE, (VDD_MCU, VDDA_0P8_SERDES0_1,
VDDA_0P8_SERDES2_3, VDDA_0P8_SERDES_C0_1,
VDDA_0P8_SERDES_C2_3, VDDA_0P8_DP, VDDA_0P8_DP_C,
VDDA_0P8_CSIRX, VDDA_0P8_UFS, VDDA_0P8_USB,
VDDA_0P8_DSITX, VDDA_0P8_DSITX_C)(9)
VDDAR_CORE, VDDAR_CPU
VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS
OSC1_XI, OSC1_XO
WKUP_OSC0_XI, WKUP_OSC0_XO
(optional)
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
MCU_BOOTMODE[9:0],BOOTMODE[7:0](10)
MCU_PORz(11)(12)
Valid Configuration
PORz(11)(12)
J7ES_ELCH_03
Figure 7-5. Isolated MCU and Main Domains, Primary Power-Up Sequence
1. Time Stamp Markers
T0 – 3.3V voltages start ramp-up to VOPR MIN. (0ms)
T1 – 1.8V voltages startramp-up to VOPR MIN. (2ms)
T2 – Low voltage core supplies start ramp-up to VOPR MIN. (3ms)
T3 – Low voltage RAM array voltages start ramp-up to VOPR MIN. (4ms)
T4 – OSC1 is stable and PORz/MCU_PORz are de-asserted to release processor from reset. (13ms)
2. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to
support 3.3V digital interfaces. A few supplies could have varying start times between T0 to T1 due to PDN
designs using different power resources with varying turn-on & ramp-up time delays.
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3. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to
support 1.8V digital interfaces. When eMMC memories are used, Main 1.8V supplies could have delayed
start times that aligns to T3 due to PDN designs grouping supplies with VDD_MMC0.
4. VDDSHV5 supports MMC1 signaling for SD memory cards. If compliant UHS-I SD card operation is needed,
then an independent, dual voltage (3.3V/1.8V) power source and rail are required. The start of ramp-up to
3.3V will be same as other 3.3V domains as shown. If SD card is not needed or standard data rates with
fixed 3.3V operation is acceptable, then supply can be grouped with digital IO 3.3V power rail. If a SD card is
capable of operating with fixed 1.8V, then supply can be grouped with digital IO 1.8V power rail.
5. VDDA_3P3_USB is 3.3V analog supply used for USB 2.0 differential interface signaling. A low noise, analog
supply is recommended to provide best signal integrity for USB data eye mask compliance. The start of
ramp-up to 3.3V will be same as other 3.3V domains as shown. If USB interface is not needed or data bit
errors can be tolerated, then supply can be grouped with 3.3V digital IO power rail either directly or through a
supply filter.
6. VDDA_1P8_<phy> are 1.8V analog supplies supporting multiple serial PHY interfaces. A low noise, analog
supply is recommended to provide best signal integrity, interface performance and spec compliance. If any
of these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then supplies
can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed.
7. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface and must ramp up at
time stamp T3. Any MCU or Main dual voltage IO operating at 1.8V can be grouped with VDD_MMC0 into
a common power rail with a ramp-up at time stamp T3. If MMC0 or eMMC0 interface is not needed, then
domain can be grouped with digital IO 1.8V power rail with ramp-up at time stamp T1.
8. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility,
enabling it to be grouped and ramped-up with either 0.8V VDD_CORE at time stamp T2 or 0.85V RAM array
domains (VDDAR_xxx) at time stamp T3.
9. VDDA_1P8_<clk/pll/ana> are 1.8V analog supplies supporting clock oscillator, PLL and analog circuitry
needing a low noise supply for optimal performance. It is not recommended to combine analog
VDDA_1P8_<phy> domains or digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency
switching noise could negatively impact jitter performance of clock, PLL and DLL signals.
10. VDDA_0P8_<dll/pll> are 0.8V analog supplies supporting PLL and DLL circuitry needing a low noise supply
for optimal performance. It is not recommended to combine these domains with any other 0.8V domains
since high frequency switching noise could negatively impact jitter performance of PLL and DLL signals.
11. Minimum set-up and hold times shown with respect to MCU_PORz and PORz asserting high to latch
MCU_BOOTMODEn (referenced to MCU_VDDSHV0) and BOOTMODEn (reference to VDDSHV2) settings
into registers during power up sequence.
12. Minimum elapsed time from crystal oscillator circuitry being energized (VDDS_OSC1 at T1) until stable clock
frequency is reached depends upon on crystal oscillator, capacitor parameters and PCB parasitic values.
A conservative 10ms elapsed time defined by (T4 – T1) time stamps is shown. This could be reduced
depending upon customer’s clock circuit (that is, crystal oscillator or clock generator) and PCB designs.
7.10.2.5 Isolated MCU and Main Domains, Primary Power- Down Sequencing
Figure 7-6 describes the device power-down sequencing.
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T4
T0
T1
T2
T3
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)(2)
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5(4), VDDSHV6)(2),VDDA_3P3_USB(5)
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)(3)
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5(4), VDDSHV6)(3), VDDS_MMC0(7)
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5(4), VDDSHV6)(3), VDDS_MMC0(7)
VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC0,
VDDA_ADC1, VDDA_POR_WKUP, VDDA_WKUP
VDDS_OSC1, VDDA_PLLGRP0,
VDDA_PLLGRP1, VDDA_PLLGRP2,
VDDA_PLLGRP3, VDDA_PLLGRP4, VDDA_PLLGRP5,
VDDA_PLLGRP6, VDDA_TEMP0_1, VDDA_TEMP2_3,
(VDDA_1P8_CSIRX, VDDA_1P8_UFS, VDDA_1P8_USB,
VDDA_1P8_DP, VDDA_1P8_DSITX, VDDA_1P8_MLB,
VDDA_1P8_SERDES0_1, VDDA_1P8_SERDES2_3)(6)
(VDD_MCU(8), VDDAR_MCU)
VDD_CPU
VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0, VDDA_0P8_PLL_MLB
VDD_CORE, (VDD_MCU, VDDA_0P8_SERDES0_1,
VDDA_0P8_SERDES2_3, VDDA_0P8_SERDES_C0_1,
VDDA_0P8_SERDES_C2_3, VDDA_0P8_DP, VDDA_0P8_DP_C,
VDDA_0P8_CSIRX, VDDA_0P8_UFS, VDDA_0P8_USB,
VDDA_0P8_DSITX, VDDA_0P8_DSITX_C)(9)
VDDAR_CORE, VDDAR_CPU
VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS
OSC1_XI, OSC1_XO
WKUP_OSC0_XI, WKUP_OSC0_XO
(optional)
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
BOOTMODE[9:0],BOOTMODE[7:0]
MCU_PORz(10)
TΔ1
PORz(10)
J7ES_ELCH_04
Figure 7-6. Isolated MCU and Main Domains, Primary Power- Down Sequencing
1. Time Stamp Markers
T0 – MCU_PORz & PORz assert low to put all processor resources in safe state. (0ms)
T1 – Main DDR, SRAM Core & SRAM CPU power supplies start ramp-down. (0.5ms)
T2 – Low voltage core supplies start supply ramp-down. (2.5ms)
T3 - 1.8V voltages start supply ramp-down. (3.0ms)
T4 – 3.3V voltages start supply ramp-down. (3.5ms)
2. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to
support 3.3V digital interfaces
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3. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to
support 1.8V digital interfaces. When eMMC memories are used, Main 1.8V supplies could have a ramp-
down aligned to T1 due to PDN designs grouping supplies with VDD_MMC0.
4. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3V/1.8V) power rail is required
for compliant, high-speed SD card operations. If compliant highspeed SD card operation is needed, then
an independent, dual voltage (3.3V/1.8V) power source and rail are required. The start of ramp-down from
3.3V/1.8V will be same as other 3.3V domains as shown. If SD card is not needed or standard data rates
with fixed 3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a SD
card is capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail.
5. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise,
analog supply is recommended to provide best signal integrity for USB data eye mask compliance. The start
of ramp-down from 3.3V will be same as other 3.3V domains as shown. If USB interface is not needed or
data bit errors can be tolerated, then domain can be grouped with 3.3V digital IO power rail either directly or
through a supply filter.
6. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog
supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of
these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains
can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed.
7. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface and must ramp-down at
time stamp T1 before VDD_CORE starts ramp-down. Any MCU or Main dual voltage IO operating at 1.8V
can be grouped with VDD_MMC0 into a common power rail with power down time stamp T1. If MMC0 or
eMMC0 interface is not needed, then domain can be grouped with digital IO 1.8V power rail and ramp-down
at time stamp T3.
8. VDD_MCU is a digital voltage supply with a wide operating voltage range and power sequencing flexibility,
enabling it to be grouped and ramped-down with either 0.8V VDD_CORE at time stamp T2 or 0.85V RAM
array domains (VDDAR_xxx) at time stamp T1.
9. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL & analog circuitry
needing a low noise supply for optimal performance. It is not recommended to combine analog
VDDA_1P8_<phy> domains or digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency
switching noise could negatively impact jitter performance of clock, PLL and DLL signals.
10. MCU_PORz and PORz must be asserted low for TΔ1 = 200us min to ensure SoC resources enter into safe
state before any voltage begins to ramp down.
7.10.2.6 Entry and Exit of MCU Only State
Entry into MCU Only lower power state is accomplished by executing a power down sequence except
for the 4 MCU supply groups (VDDSHVx_MCU at 3.3V, VDDSHVx_MCU at 1.8V, VDDA_MCU_PLLGRP0/
VDDA_MCU_TEMP analog supplies at 1.8V, VDD_MCU/VDDAR_MCU at 0.85V) that remain energized. Exit
from MCU Only state is accomplished by executing a power up sequence with the 4 MCU supply groups
remaining energized throughout the sequence. The example diagram shown is for an Isolated MCU & Main PDN
type with eMMC support.
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Entry into MCU only
Active
MCU only
Exit from MCU only
Active
T0
T1
T2
T3
T4
T0
T1
T2
T3
T4
VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU(3)(5a)
VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5, VDDSHV6(3)(5b),VDDA_3P3_USB
VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU(4)
VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5, VDDSHV6(4)
VDDS_MMC0
VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC0,
VDDA_ADC1, VDDA_POR_WKUP, VDDA_WKUP
VDDS_OSC1, VDDA_PLLGRP0,
VDDA_PLLGRP1, VDDA_PLLGRP2,
VDDA_PLLGRP3, VDDA_PLLGRP4, VDDA_PLLGRP5,
VDDA_PLLGRP6, VDDA_TEMP0_1, VDDA_TEMP2_3,
VDDA_1P8_CSIRX, VDDA_1P8_UFS, VDDA_1P8_USB,
VDDA_1P8_DP, VDDA_1P8_DSITX, VDDA_1P8_MLB,
VDDA_1P8_SERDES0_1, VDDA_1P8_SERDES2_3(6)
VDD_MCU, VDDAR_MCU(7)
VDD_CPU
VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0, VDDA_0P8_PLL_MLB
VDD_CORE, VDD_MCU, VDDA_0P8_SERDES0_1,
VDDA_0P8_SERDES2_3, VDDA_0P8_SERDES_C0_1,
VDDA_0P8_SERDES_C2_3, VDDA_0P8_DP, VDDA_0P8_DP_C,
VDDA_0P8_CSIRX, VDDA_0P8_UFS, VDDA_0P8_USB,
VDDA_0P8_DSITX, VDDA_0P8_DSITX_C
VDDAR_CORE, VDDAR_CPU, VDDAR_MCU(7)
VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS
OSC1_XI, OSC1_XO
WKUP_OSC0_XI, WKUP_OSC0_XO
(optional)
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
SYSBOOT[17:0](9)
MCU_PORz(9)(10)
Valid Configuration
PORz(9)(10)
J7ES_ELCH_03
Figure 7-7. Entry and Exit of MCU Only Sequencing
7.10.2.7 Entry and Exit of DDR Retention State
Entry into DDR Retention (Suspend-to-RAM or S2R) state is accomplished by executing a power down
sequence except for the 1 device DDR supply group (VDDS_DDR_BIAS, VDDS_DDR, and VDDS_DDR_C
at 1.1V), and 1 additional discrete SDRAM supply (VDD_LPDDR4_1V8 at 1.8V; not shown in diagram below)
that remain energized. Exit from DDR Retention state is accomplished by executing a power up sequence with
these 2 DDR supply groups remaining energized throughout the sequence. The example diagram shown is for
an Isolated MCU & Main PDN type with eMMC support.
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Entry into MCU only
Active
DDR Retention
Exit from MCU only
Active
T0
T1
T2
T3
T4
T0
T1
T2
T3
T4
VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU(3)(5a)
VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5, VDDSHV6(3)(5b),VDDA_3P3_USB
VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU(4)
VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV5, VDDSHV6(4)
VDDS_MMC0
VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC0,
VDDA_ADC1, VDDA_POR_WKUP, VDDA_WKUP
VDDS_OSC1, VDDA_PLLGRP0,
VDDA_PLLGRP1, VDDA_PLLGRP2,
VDDA_PLLGRP3, VDDA_PLLGRP4, VDDA_PLLGRP5,
VDDA_PLLGRP6, VDDA_TEMP0_1, VDDA_TEMP2_3,
VDDA_1P8_CSIRX, VDDA_1P8_UFS, VDDA_1P8_USB,
VDDA_1P8_DP, VDDA_1P8_DSITX, VDDA_1P8_MLB,
VDDA_1P8_SERDES0_1, VDDA_1P8_SERDES2_3(6)
VDD_MCU, VDDAR_MCU(7)
VDD_CPU
VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0, VDDA_0P8_PLL_MLB
VDD_CORE, VDD_MCU, VDDA_0P8_SERDES0_1,
VDDA_0P8_SERDES2_3, VDDA_0P8_SERDES_C0_1,
VDDA_0P8_SERDES_C2_3, VDDA_0P8_DP, VDDA_0P8_DP_C,
VDDA_0P8_CSIRX, VDDA_0P8_UFS, VDDA_0P8_USB,
VDDA_0P8_DSITX, VDDA_0P8_DSITX_C
VDDAR_CORE, VDDAR_CPU, VDDAR_MCU(7)
VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS
OSC1_XI, OSC1_XO
WKUP_OSC0_XI, WKUP_OSC0_XO
(optional)
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
SYSBOOT[17:0](9)
MCU_PORz(9)(10)
Valid Configuration
PORz(9)(10)
J7ES_ELCH_03
Figure 7-8. Entry and Exit of DDR Retention Sequencing
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7.10.3 System Timing
For more details about features and additional description information on the subsystem multiplexing signals,
see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
Table 7-4. System Timing Conditions
PARAMETER
MIN
0.5
3
MAX UNIT
INPUT CONDITIONS
SRI
Input slew rate
2
V/ns
pF
OUTPUT CONDITIONS
CL
Output load capacitance
30
7.10.3.1 Reset Timing
Tables and figures provided in this section define timing requirements and switching characteristics for reset
related signals.
Table 7-5. MCU_PORz Timing Requirements
see Figure 7-9
NO.
MIN
TYP
MAX UNIT
Hold time, MCU_PORz active (low) at Power-
up after all MCU DOMAIN supplies valid (using
external crystal)
N +
RST1
9500000
ns
1200(2)
th(MCUD_SUPPLIES_VALID - MCU_PORz)
Hold time, MCU_PORz active (low) at Power-
up after all MCU DOMAIN supplies(1) valid and
external clock stable (using external LVCMOS
oscillator)
RST2
1200
1200
ns
ns
Pulse Width minimum, MCU_PORz low after
Power-up (without removal of Power or system
reference clock MCU_OSC0_XI/XO)
RST3 tw(MCU_PORzL)
(1) For definition of the MCU DOMAIN supplies, see the Combined MCU and Main Domains Power-Up sequence.
(2) N = oscillator start-up time
RST1
RST2
RST3
MCU_PORz
MCU DOMAIN
SUPPLIES VALID
MCU_OSC0_XI,
MCU_OSC0_XO
Figure 7-9. MCU_PORz Timing Requirements
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Table 7-6. PORz Timing Requirements
see Figure 7-10
NO.
MIN
1200
1200
MAX UNIT
Hold time, PORz active (low) at Power-up after all MAIN
DOMAIN supplies1 valid
RST4 th(MAIND_SUPPLIES_VALID - PORz)
RST5 tw(PORzL)
ns
ns
Pulse Width minimum, PORz low after Power-up
1. For definition of the MAIN DOMAIN supplies, see the Combined MCU and Main Domains Power-Up
sequence.
RST4
RST5
PORz
MAIN DOMAIN
SUPPLIES VALID
Figure 7-10. PORz Timing Requirements
Table 7-7. MCU_PORz initiates; MCU_PORz_OUT, PORz_OUT, MCU_RESETSTATz, and RESETSTATz
Switching Characteristics
see Figure 7-11
NO.
PARAMETER
MODE
MIN
MAX UNIT
Delay time, MCU_PORz active (low) to
MCU_PORz_OUT active (low)
RST6 td(MCU_PORzL-MCU_PORz_OUTL)
0
ns
Delay time, MCU_PORz inactive (high) to
MCU_PORz_OUT inactive (high)
RST7 td(MCU_PORzH-MCU_PORz_OUTH)
RST8 td(MCU_PORzL-PORz_OUTL)
0
ns
ns
ns
ns
ns
ns
ns
Delay time, MCU_PORz active (low) to
PORz_OUT active (low)
0
1500
Delay time, MCU_PORz inactive (high) to
PORz_OUT inactive (high)
RST9 td(MCU_PORzH-PORz_OUTH)
RST10 td(MCU_PORzL-MCU_RESETSTATzL)
RST11 td(MCU_PORzH-MCU_RESETSTATzH)
RST12 td(MCU_PORzL-RESETSTATzL)
RST13 td(MCU_PORzH-RESETSTATzH)
Delay time, MCU_PORz active (low) to
MCU_RESETSTATz active (low)
0
Delay time, MCU_PORz inactive (high) to
MCU_RESETSTATz inactive (high)
POST
bypass
12000*S(1)
0
Delay time, MCU_PORz active (low) to
RESETSTATz active (low)
Delay time, MCU_PORz inactive (high) to
RESETSTATz inactive (high)
14500*S(1)
Pulse width minimum, MCU_PORz_OUT
active (low)
RST14 tw(MCU_PORz_OUTL)
RST15 tw(PORz_OUTL)
RST16 tw(MCU_RESETSTATzL)
RST17 tw(RESETSTATzL)
1200
2550
ns
ns
ns
ns
Pulse Width Minimum PORz_OUT low
Pulse Width Minimum MCU_RESETSTATz
low
3900*S(1)
2650*S(1)
Pulse Width Minimum RESETSTATz low
(1) S = MCU_OSC0_XI/XO clock period.
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RST12
RST6
RST13
RST7
MCU_PORz
RST14
MCU_PORz_OUT
RST10
RST11
RST16
MCU_RESETSTATz
RST8
RST9
RST15
PORz_OUT
RST17
RESETSTATz
Figure 7-11. MCU_PORz initiates; MCU_PORz_OUT, PORz_OUT, MCU_RESETSTATz, and RESETSTATz
Switching Characteristics
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Table 7-8. PORz Initiates; PORz_OUT and RESETSTATz Switching Characteristics
see Figure 7-12
NO.
PARAMETER
MODE
MIN
MAX UNIT
software control of
POR_RST_ISO_DONE_Z
T(1)
Delay time, PORz active (low) toPORz_OUT
active (low)
RST18 td(PORzL-PORz_OUTL)
CTRLMMR_WKUP_POR_RST
_CTRL[0].POR_RST_ISO_
DONE_Z = 0
0
ns
ns
Delay time, PORz active (high) toPORz_OUT
active (high)
RST19 td(PORzH-PORz_OUTH)
1300
T(1)
td(PORzL-
RST20
Delay time, PORz active (low) to RESETSTATz
active (low)
CTRLMMR_WKUP_POR_RST
_CTRL[0].POR_RST_ISO_
DONE_Z = 0
RESETSTATzL)
0
ns
ns
td(PORzH-
RST21
Delay time, PORz active (high) to RESETSTATz
active (high)
14500*S
(2)
RESETSTATzH)
(1) T = Reset Isolation Time (Software Dependent).
(2) S = MCU_OSC0_XI/XO clock period.
RST18
RST19
PORz
PORz_OUT
RST20
RST21
RESETSTATz
Figure 7-12. PORz initiates; PORz_OUT and RESETSTATz Switching Characteristics
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Table 7-9. MCU_RESETz Timing Requirements
see Figure 7-13
NO.
MIN
MAX UNIT
(1)
RST22 tw(MCU_RESETzL)
Pulse Width minimum, MCU_RESETz active (low)
1200
ns
(1) Timing for MCU_RESETz is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
Table 7-10. MCU_RESETz initiates; MCU_RESETSTATz, and RESETSTATz Switching Characteristics
see Figure 7-13
NO.
PARAMETER
MIN
MAX UNIT
Delay time, MCU_RESETz active (low) to
MCU_RESETSTATz active (low)
RST23 td(MCU_RESETzL-MCU_RESETSTATzL)
800
ns
Delay time, MCU_RESETz inactive (high) to
MCU_RESETSTATz inactive (high)
RST24 td(MCU_RESETzH-MCU_RESETSTATzH)
RST25 td(MCU_RESETzL-RESETSTATzL)
RST26 td(MCU_RESETzH-RESETSTATzH)
(1) S = MCU_OSC0_XI/XO clock period.
3900*S(1)
800
ns
ns
ns
Delay time, MCU_RESETz active (low) to RESETSTATz
active (low)
Delay time, MCU_RESETz inactive (high) to
RESETSTATz inactive (high)
3900*S(1)
RST23
RST24
MCU_RESETz
RST22
MCU_RESETSTATz
RESETSTATz
RST25
RST26
Figure 7-13. MCU_RESETz initiates; MCU_RESETSTATz, and RESETSTATz Timing Requirements and
Switching Characteristics
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Table 7-11. RESET_REQz Timing Requirements
see Figure 7-14
NO.
MIN
MAX UNIT
(1)
RST27 tw(RESET_REQzL)
Pulse Width minimum, RESET_REQz active (low)
1200
ns
(1) Timing for RESET_REQz is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
Table 7-12. RESET_REQz initiates; RESETSTATz Switching Characteristics
see Figure 7-14
NO.
PARAMETER
MODE
MIN
MAX UNIT
software control of
SOC_WARMRST_ISO_DONE
_Z
T(1)
Delay time, RESET_REQz active (low)
to RESETSTATz active (low)
RST28 td(RESET_REQzL-RESETSTATzL)
CTRLMMR_WKUP_MAIN_WA
RM
740
ns
ns
_RST_CTRL[0].SOC_
WARMRST_ISO_DONE_Z = 0
Delay time, RESET_REQz inactive
(high) to RESETSTATz inactive (high)
2650*S
RST29 td(RESET_REQzH-RESETSTATzH)
(2)
(1) T = Reset Isolation Time (Software Dependent).
(2) S = MCU_OSC0_XI/XO clock period.
RST27
RST28
RESET_REQz
RST29
RESETSTATz
Figure 7-14. RESET_REQz initiates; RESETSTATz Timing Requirements and Switching Characteristics
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Table 7-13. EMUx Timing Requirements
see Figure 7-15
NO.
MIN
3*S(1)
10
MAX UNIT
RST30 tsu(EMUx-MCU_PORz)
RST31 th(MCU_PORz - EMUx)
Setup time, EMU[1:0] before MCU_PORz inactive (high)
Hold time, EMU[1:0] after MCU_PORz inactive (high)
ns
ns
(1) S = MCU_OSC0_XI/XO clock period.
RST30
MCU_PORz
EMU[1:0]
RST31
Figure 7-15. EMUx Timing Requirements
Table 7-14. MCU_BOOTMODE Timing Requirements
see Figure 7-16
NO.
MIN
MAX UNIT
Setup time, MCU_BOOTMODE[09:00] before
MCU_PORz_OUT high
RST32 tsu(MCU_BOOTMODE-MCU_PORz_OUT)
RST33 th(MCU_PORz_OUT - MCU_BOOTMODE)
(1) S = MCU_OSC0_XI/XO clock period.
3*S(1)
ns
Hold time, MCU_BOOTMODE[09:00] after MCU_
PORz_OUT high
0
ns
RST32
MCU_PORz_OUT
MCU_BOOTMODE[09:00]
RST33
Figure 7-16. MCU_BOOTMODE Timing Requirements
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Table 7-15. BOOTMODE Timing Requirements
see Figure 7-17
NO.
MIN
3*S(1)
0
MAX UNIT
RST34 tsu(BOOTMODE-PORz_OUT)
RST35 th(PORz_OUT - BOOTMODE)
Setup time, BOOTMODE[7:0] before PORz_OUT high
Hold time, BOOTMODE[7:0] after PORz_OUT high
ns
ns
(1) S = MCU_OSC0_XI/XO clock period.
RST34
PORz_OUT
BOOTMODE[7:0]
RST35
Figure 7-17. BOOTMODE Timing Requirements
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7.10.3.2 Safety Signal Timing
Tables and figures provided in this section define switching characteristics for MCU_SAFETY_ERRORn and
SOC_SAFETY_ERRORn.
Table 7-16. MCU_SAFETY_ERRORn Switching Characteristics
see Figure 7-18
NO.
PARAMETER
MIN
MAX UNIT
Pulse width minimum, MCU_SAFETY_ERRORn active
(PWM mode disabled)
SFTY1 tw(MCU_SAFETY_ERRORn)
P*R(1) (2)
ns
Delay time, ERROR CONDITION to
SFTY2 td (ERROR_CONDITION-MCU_SAFETY_ERRORnL) MCU_SAFETY_ERRORn
active
50*P(1)
ns
(1) P = ESM functional clock (MCU_SYSCLK0 /6).
(2) R = Error Pin Counter Pre-Load Register count value.
Internal Error Condition
(Active High)
SFTY1
SFTY2
MCU_SAFETY_ERRORn
(PWM Mode Disabled)
Figure 7-18. MCU_SAFETY_ERRORn Switching Characteristics
Table 7-17. SOC_SAFETY_ERRORn Switching Characteristics
see Figure 7-19
NO.
PARAMETER
MIN
MAX UNIT
Pulse width minimum,SOC_SAFETY_ERRORn active
(PWM mode disabled)
SFTY3 tw(SOC_SAFETY_ERRORn)
P*R(1) (2)
ns
Delay time, ERROR CONDITION to
SFTY4 td (ERROR_CONDITION-SOC_SAFETY_ERRORnL) SOC_SAFETY_ERRORn
active
50*P(1)
ns
Internal Error Condition
(Active High)
SFTY3
SFTY4
SOC_SAFETY_ERRORn
(PWM Mode Disabled)
Figure 7-19. SOC_SAFETY_ERRORn Switching Characteristics
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7.10.3.3 Clock Timing
Tables and figures provided in this section define timing requirements and switching characteristics for clock
signals.
Table 7-18. Clock Timng Requiements
see Figure 7-20
NO.
MIN
10
MAX UNIT
CLK1 tc(EXT_REFCLK1)
CLK2 tw(EXT_REFCLK1H)
CLK3 tw(EXT_REFCLK1L)
Cycle time minimum, EXT_REFCLK1
ns
Pulse Duration minimum, EXT_REFCLK1 high
Pulse Duration minimum, EXT_REFCLK1 low
E*0.45(1)
E*0.45(1)
E*0.55(1)
E*0.55(1)
ns
ns
(1) E = EXT_REFCLK1 cycle time.
Figure 7-20. Clock Timing Requirements
Table 7-19. Clock Switching Characteristics
see Figure 7-21
NO.
PARAMETER
MIN
8
MAX UNIT
CLK4 tc(SYSCLKOUT0)
CLK5 tw(SYSCLKOUT0H)
CLK6 tw(SYSCLKOUT0L)
CLK7 tc(OBSCLK0)
Cycle time minimum,SYSCLKOUT0
Pulse Duration minimum, SYSCLKOUT0 high
Pulse Duration minimum, SYSCLKOUT0 low
Cycle time minimum, OBSCLK0
ns
A*0.4(1)
A*0.4(1)
5
A*0.6(1)
ns
ns
ns
ns
ns
ns
ns
ns
A*0.6(1)
CLK8 tw(OBSCLK0H)
CLK9 tw(OBSCLK0L)
CLK10 tc(CLKOUT0)
Pulse Duration minimum, OBSCLK0 high
Pulse Duration minimum,OBSCLK0 low
Cycle time minimum, CLKOUT0
B*0.4(2)
B*0.4(2)
20
B*0.6(2)
B*0.6(2)
CLK11 tw(CLKOUT0H)
CLK12 tw(CLKOUT0L)
Pulse Duration minimum, CLKOUT0 high
Pulse Duration minimum,CLKOUT0 low
C*0.4(3)
C*0.4(3)
C*0.6(3)
C*0.6(3)
(1) A = SYSCLKOUT0 cycle time.
(2) B = OBSCLK0 cycle time.
(3) C = CLKOUT0 cycle time.
Figure 7-21. Clock Switching Characteristics
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7.10.4 Clock Specifications
7.10.4.1 Input and Output Clocks / Oscillators
Various external clock inputs/outputs are needed to drive the device. Summary of these input clock signals is as
follows:
•
OSC1_XO/OSC1_XI — Еxternal main crystal interface pins connected to internal oscillator which sources
reference clock and provides reference clock to PLLs within MAIN domain. Also, for audio applications,
high-frequency oscillator 0 is used to provide audio clock frequencies to MCASPs.
High frequency oscillators inputs
•
– OSC1_XO/OSC1_XI — external main crystal interface pins connected to internal oscillator which sources
reference clock. Provides reference clock to PLLs within MCU domain and MAIN domain. This high-
frequency oscillator is used to provide audio clock frequencies to MCASPs.
– WKUP_OSC0_XO/WKUP_OSC0_XI — external main crystal interface pins connected to internal
oscillator which sources reference clock. Provides reference clock to PLLs within WKUP and MAIN
domain.
•
•
Low frequency oscillator input
– WKUP_LFOSC_XO/WKUP_LFOSC_XI — external main crystal interface pins connected to internal
oscillator which sources reference clock provides a clock for low power operation in deeper sleep modes.
General purpose clock inputs
– MCU_EXT_REFCLK0 — optional external. Provides system clock input (MCU domain).
– EXT_REFCLK1 — optional external System clock input (MAIN domain). Optionally PLL2 (PER1) and
MCASP can be sourced by EXT_REFCLK1 (sourced externally).
– SERDES4_REFCLK_P/N — SerDes reference clock input for PCIe or Optional USB3 and SGMII
interfaces.
– PCIE_REFCLK[3:0]N/P — There are 4 differential clock input/output pins to support PCIe devices.
External video pixel clock inputs
– VOUT0_EXTPCLKIN — optional for the DPI0 port of DSS.
– VOUT1_EXTPCLKIN — optional for the DPI1 port of DSS.
External CPTS reference clock inputs
– MCU_CPTS_RFT_CLK — CPTS reference clock inputs for MCU_CPTS_RFT_CLK.
– CPTS_RFT_CLK — CPTS reference clock inputs for CPTS_RFT_CLK.
External audio reference clock input/output pins
•
•
•
– AUDIO_EXT_REFCLK0
– AUDIO_EXT_REFCLK1
– AUDIO_EXT_REFCLK2
– AUDIO_EXT_REFCLK3
Figure 7-22 shows the external input clock sources and the output clocks to peripherals.
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DEVICE
Reference clock output
CLKOUT
MCU_CLKOUT0
Reference clock output for Ethernet PHYs (50MHz or 25MHz)
Selects Main PLL output divide-by-6
SYSCLKOUT0
MCU_SYSCLKOUT0
Optional pins to provide reference clock input to the PLLs.
WKUP_OSC0_XI
External Wake-up crystal interface pins connected to internal oscillator
which provides reference clock to PLLs within MAIN domain, and
audio clock frequencies to MCASPs.
WKUP_OSC0_XO
WKUP_LFOSC0_XI
External Low frequency crystal interface pins connected to internal oscillator
which provides a 32.768 KHz clock for low power operation
in deeper sleep modes.
WKUP_LFOSC0_XO
OSC1_XI
External main crystal interface pins connected to internal oscillator
which provides reference clock to PLLs within MCU domain
and MAIN domain.
OSC1_XO
JTAG Clock Input
TCK
MCU Warm Reset Input / Device Warm Reset Input
MCU_RESETz/ RESET_REQz
MCU_PORz / PORz
BOOTMODE[7:0]
MCU Power ON Reset / Device Power ON Reset
Boot Mode Configuration / devices select
MCU_BOOTMODE[09:00]
DDR0_CKP/DDR0_CKN
MCU Boot Mode system clock speed and fail-safe boot device
DDR Differential Clock outputs
There are 4 differential clock input/output pins to support PCIe devices
PCIE_REFCLK[3:0]N/P
SERDES4_REFCLK_P/N
SerDes reference clock input for PCIe or Optional USB3 and SGMII interfaces
Observation clock outputs for MCU Domain clock / MAIN Domain clocks
External audio reference clock input/output pins
MCU_OBSCLK0 / OBSCLK[2:0]
AUDIO_EXT_REFCLK[3:0]
MCU_EXT_REFCLK0 / EXT_REFCLK1
Optional external System clock inputs - (MCU domain) / (MAIN domain)
VOUT[1:0]_EXTPCLKIN
Optional for the DPI0/1 Ports of DSS
CPTS reference clock input for CPTS_RFT_CLK / MCU_CPTS_RFT_CLK
MCU_CPTS0_RFT_CLK / CPTS0_RFT_CLK
J7ES_CLOCK_01
Figure 7-22. Input Clocks Interface
For more information about Input clock interfaces, see Clocking section in Device Configuration chapter in the
device TRM.
7.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
Figure 7-23 shows the recommended crystal circuit. All discrete components used to implement the oscillator
circuit should be placed as close as possible to the WKUP_OSC0_XI and WKUP_OSC0_XO pins.
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Device
WKUP_OSC0_XO
WKUP_OSC0_XI
Rd
(Optional)
Crystal
(Optional)
Rbias
Cf2
Cf1
PCB Ground
J7ES_WKUP_OSC_INT_02
Figure 7-23. WKUP_OSC0 Crystal Implementation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 7-20 summarizes the
required electrical constraints.
Table 7-20. WKUP_OSC0 Crystal Electrical Characteristics
PARAMETER
Fxtal
MIN
TYP
MAX UNIT
Crystal Parallel Resonance Frequency
Crystal Frequency Stability and Tolerance
19.2, 20, 24, 25, 26, 27
MHz
ppm
Fxtal
Ethernet RGMII and RMII
not used
±100
Ethernet RGMII and RMII
using derived clock
±50
CL1+PCBXI
CL2+PCBXO
CL
Capacitance of CL1 + CPCBXI
Capacitance of CL2 + CPCBXO
Crystal Load Capacitance
12
12
6
24
24
12
pF
pF
pF
pF
Cshunt
Crystal Circuit Shunt Capacitance
ESRxtal = 30 Ω
19.2 MHz, 20 MHz,
24 MHz, 25 MHz, 26 MHz,
27 MHz
7
5
5
ESRxtal = 40 Ω
ESRxtal = 50 Ω
19.2 MHz, 20 MHz,
24 MHz, 25 MHz, 26 MHz,
27 MHz
pF
pF
19.2 MHz, 20 MHz,
24 MHz, 25 MHz, 26 MHz,
27 MHz
ESRxtal = 60 Ω
ESRxtal = 80 Ω
19.2 MHz, 20 MHz, 24 MHz
19.2 MHz, 20 MHz
25 MHz
5
5
pF
pF
pF
pF
Ω
3
ESRxtal = 100 Ω 19.2 MHz, 20 MHz
3
ESRxtal
Crystal Effective Series Resistance
100
When selecting a crystal, the system design must consider the temperature and aging characteristics of a based
on the worst case environment and expected life expectancy of the system.
Table 7-21 details the switching characteristics of the oscillator and the requirements of the input clock.
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Table 7-21. WKUP_OSC0 Switching Characteristics – Crystal Mode
PARAMETER
MIN
TYP
MAX UNIT
1.55
CXI
XI Capacitance
pF
pF
fF
CXO
CXIXO
ts
XO Capacitance
1.35
XI to XO Mutual Capacitance
Maximum Start-up Time
0.9
9.5(1)
ms
(1) TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The
vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device
for optimum startup and operation over temperature/voltage extremes.
VDD_WKUP (min.)
VDD_WKUP
VSS
VDDA_WKUP (min.)
VDDA_WKUP
WKUP_OSC0_XO
VSS
tsX
Time
J7ES_WKUP_OSC_STARTUP_04
Figure 7-24. WKUP_OSC0 Start-up Time
7.10.4.1.1.1 Load Capacitance
The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined
by the crystal manufacturer. The capacitive load, CL, of this circuit is a combination of discrete capacitors
CL1, CL2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to
WKUP_OSC0_XI and WKUP_OSC0_XO have parasitic capacitance to ground, CPCBXI and CPCBXO, where the
PCB designer should be able to extract parasitic capacitance for each signal trace. The WKUP_OSC0 circuits
and device package have combined parasitic capacitance to ground, CPCBXI and CPCBXO, where these parasitic
capacitance values are defined in Table 7-21.
Device
Crystal Circuit
Components
PCB
Signal Traces
WKUP_OSC0_XI
CL1
CPCBXI
CXI
CL2
CPCBXO
CXO
WKUP_OSC0_XO
J7ES_WKUP_OSC_CC_05
Figure 7-25. Load Capacitance
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Load capacitors, CL1 and CL2 in Figure 7-23, should be chosen such that the below equation is satisfied. CL in
the equation is the load specified by the crystal manufacturer.
CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]
To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract the
combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO to
determine the value of CL2. For example, if CL = 10 pF, CPCBXI = 2.9 pF, CXI = 0.5 pF, CPCBXO = 3.7 pF, CXO
=
0.5 pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and CL2 = [(2CL) -
(CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF
7.10.4.1.1.2 Shunt Capacitance
The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for
WKUP_OSC0 operating conditions defined in Table 7-20. Shunt capacitance, Cshunt, of the crystal circuit is a
combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal
circuit components to WKUP_OSC0 have mutual parasitic capacitance to each other, CPCBXIXO, where the
PCB designer should be able to extract mutual parasitic capacitance between these signal traces. The device
package also has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined
in Table 7-21.
PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is
typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can
also be minimized by placing a ground trace between these signals when the layout requires them to be routed
in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as
possible when selecting a crystal.
Device
Crystal Circuit
Components
PCB
Signal Traces
WKUP_OSC0_XI
CPCBXIXO
CXIXO
CO
WKUP_OSC0_XO
J7ES_WKUP_OSC_SC_06
Figure 7-26. Shunt Capacitance
A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt
capacitance specified by the crystal manufacturer.
Cshunt ≥ CO + CPCBXIXO + CXIXO
For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω,
CPCBXIXO = 0.04 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.95 pF.
7.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
Figure 7-27 shows the recommended oscillator connections when WKUP_OSC0_XI is connected to a 1.8-V
LVCMOS square-wave digital clock source.
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Note
A DC steady-state condition is not allowed on WKUP_OSC0_XI when the oscillator is powered up.
This is not allowed because WKUP_OSC0_XI is internally AC coupled to a comparator that may enter
a unknown state when DC is applied to the input. Therefore, application software should power down
WKUP_OSC0 any time WKUP_OSC0_XI is not toggling between logic states.
Device
WKUP_OSC0_XO
WKUP_OSC0_XI
PCB Ground
J7ES_WKUP_OSC_EXT_CLK_05
Figure 7-27. 1.8-V LVCMOS-Compatible Clock Input
7.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
Figure 7-28 shows the recommended crystal circuit. All discrete components used to implement the oscillator
circuit should be placed as close as possible to the OSC1_XI and OSC1_XO pins.
Device
OSC1_XO
OSC1_XI
Rd
(Optional)
Crystal
(Optional)
Rbias
Cf2
Cf1
PCB Ground
J7ES_AUX_OSC_INT_07
Figure 7-28. OSC1 Crystal Implementation
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The crystal must be in the fundamental mode of operation and parallel resonant. Table 7-22 summarizes the
required electrical constraints.
Table 7-22. OSC1 Crystal Electrical Characteristics
PARAMETER
MIN
TYP
MAX UNIT
Fxtal
Fxtal
Crystal Parallel Resonance Frequency
19.2
27
MHz
ppm
Crystal Frequency Stability and Tolerance
Ethernet RGMII and RMII
not used
±100
Ethernet RGMII and RMII
using derived clock
±50
CL1+PCBXI
CL2+PCBXO
CL
Capacitance of CL1 + CPCBXI
Capacitance of CL2 + CPCBXO
Crystal Load Capacitance
12
12
6
24
24
12
7
pF
pF
pF
pF
Cshunt
Crystal Circuit Shunt Capacitance
ESRxtal = 30 Ω
19.2 MHz, 20 MHz,
24 MHz, 25 MHz, 26 MHz,
27 MHz
ESRxtal = 40 Ω
ESRxtal = 50 Ω
19.2 MHz, 20 MHz,
24 MHz, 25 MHz, 26 MHz,
27 MHz
5
5
pF
pF
19.2 MHz, 20 MHz,
24 MHz, 25 MHz, 26 MHz,
27 MHz
ESRxtal = 60 Ω
ESRxtal = 80 Ω
19.2 MHz, 20 MHz, 24 MHz
19.2 MHz, 20 MHz
25 MHz
5
5
pF
pF
pF
pF
Ω
3
ESRxtal = 100 Ω 19.2 MHz, 20 MHz
3
ESRxtal
Crystal Effective Series Resistance
100
When selecting a crystal, the system design must consider the temperature and aging characteristics of a based
on the worst case environment and expected life expectancy of the system.
Table 7-23 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 7-23. OSC1 Switching Characteristics – Crystal Mode
PARAMETER
MIN
TYP
MAX
1.55
1.35
0.9
UNIT
pF
CXI
XI Capacitance
XO Capacitance
CXO
CXIXO
ts
pF
XI to XO Mutual Capacitance
Maximum Start-up Time
fF
9.5(1)
ms
(1) TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The
vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device
for optimum startup and operation over temperature/voltage extremes.
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VDD_CORE (min.)
VSS
VDD_CORE
VDDS_OSC1
VDDS_OSC1 (min.)
OSC1_XO
tsX
VSS
Time
J7ES_AUX_OSC_STARTUP_08
Figure 7-29. OSC1 Start-up Time
7.10.4.1.3.1 Load Capacitance
The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined
by the crystal manufacturer. The capacitive load, CL, of this circuit is a combination of discrete capacitors CL1,
CL2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to OSC1_XI
and OSC1_XO have parasitic capacitance to ground, CPCBXI and CPCBXO, where the PCB designer should
be able to extract parasitic capacitance for each signal trace. The OSC1 circuits and device package have
combined parasitic capacitance to ground, CPCBXI and CPCBXO, where these parasitic capacitance values are
defined in Table 7-23.
Device
Crystal Circuit
Components
PCB
Signal Traces
OSC1_XI
CL1
CPCBXI
CXI
CL2
CPCBXO
CXO
OSC1_XO
J7ES_AUX_OSC_CC_05
Figure 7-30. Load Capacitance
Load capacitors, CL1 and CL2 in Figure 7-28, should be chosen such that the below equation is satisfied. CL in
the equation is the load specified by the crystal manufacturer.
CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]
To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract the
combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO to
determine the value of CL2. For example, if CL = 10 pF, CPCBXI = 2.9 pF, CXI = 0.5 pF, CPCBXO = 3.7 pF, CXO
=
0.5 pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and CL2 = [(2CL) -
(CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF
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7.10.4.1.3.2 Shunt Capacitance
The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance
for OSC1 operating conditions defined in Table 7-22. Shunt capacitance, Cshunt, of the crystal circuit is a
combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal
circuit components to OSC1 have mutual parasitic capacitance to each other, CPCBXIXO, where the PCB designer
should be able to extract mutual parasitic capacitance between these signal traces. The device package also
has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined in Table 7-23.
PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is
typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can
also be minimized by placing a ground trace between these signals when the layout requires them to be routed
in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as
possible when selecting a crystal.
Device
Crystal Circuit
Components
PCB
Signal Traces
OSC1_XI
CPCBXIXO
CXIXO
CO
OSC1_XO
J7ES_AUX_OSC_SC_06
Figure 7-31. Shunt Capacitance
A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt
capacitance specified by the crystal manufacturer.
Cshunt ≥ CO + CPCBXIXO + CXIXO
For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω,
CPCBXIXO = 0.04 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.95 pF.
7.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
Figure 7-32 shows the recommended oscillator connections when OSC1 is connected to a 1.8-V LVCMOS
square-wave digital clock source.
Note
A DC steady-state condition is not allowed on OSC1_XI when the oscillator is powered up. This is not
allowed because OSC1_XI is internally AC coupled to a comparator that may enter a unknown state
when DC is applied to the input. Therefore, application software should power down OSC1 any time
OSC1_XI is not toggling between logic states.
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Device
OSC1_XO
OSC1_XI
PCB Ground
J7ES_AUX_OSC_EXT_09
Figure 7-32. 1.8-V LVCMOS-Compatible Clock Input
7.10.4.1.5 Auxiliary OSC1 Not Used
Figure 7-33 shows the recommended oscillator connections when OSC1 is not used. OSC1_XI must be
connected to VSS through an external pull resistor (Rpd) to ensure this input is held to a valid low level when
unused since the internal pull-down resistor is disabled by default.
Device
OSC1_XO
OSC1_XI
Rpd
NC
PCB Ground
J7ES_AUX_OSC_NOT_USED_11
Figure 7-33. OSC1 Not Used
7.10.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
Figure 7-34 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit board
(PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator
operation when combined with production crystal circuit components. In most cases, Rbias is not required and
Rd is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator
performance with production crystal circuit components installed on preproduction PCBs.
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Device
WKUP_LFOSC0_XO
WKUP_LFOSC0_XI
Rd
Crystal
(Optional)
(Optional)
Rbias
Cf2
Cf1
PCB Ground
J7ES_LF_OSC_INT_12
Figure 7-34. WKUP_LFOSC0 Crystal Implementation
Table 7-24 presents LFXOSC modes of operation.
Table 7-24. LFXOSC Modes of Operation
CLK_O
UT
MODE
BP_C PD_C
XI
XO
DESCRIPTION
ACTIVE
0
0
XTAL
XTAL CLK_OU
T
Active oscillator mode providing 32kHz
PWRDN
BYPASS
0
1
1
X
PD
PD
LOW Output will be pulled down to LOW. PAD to be tri-stated. Active mode disabled
X
CLK
CLK
XI is driven by external clock source. XO is pulled down to LOW. Due to ESD
diode to supply, XI should not be driven unless oscillator supply is present.
Note
User should set CTRLMMR_WKUP_LFXOSC_TRIM[18:16] i_mult = 3b’001 for CL in the range 6pf to
9.5pf. CTRLMMR_WKUP_LFXOSC_TRIM [18:16] i_mult = 3b’010 for CL in the range 8.5pf to 12pf.
Default setting is 3b’010.
Note
The load capacitors, Cf1 and Cf2 in Figure 7-35, should be chosen such that the below equation is
satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components
used to implement the oscillator circuit should be placed as close as possible to the associated
oscillator WKUP_LFOSC0_XI, WKUP_LFOSC0_XO, and VSS pins.
Cf1Cf2
C
= (Cf1+Cf2)
L
J7ES_CL_MATH_03
Figure 7-35. Load Capacitance Equation
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The crystal must be in the fundamental mode of operation and parallel resonant. Table 7-25 summarizes the
required electrical constraints.
Table 7-25. WKUP_LFOSC0 Crystal Electrical Characteristics
NAME
fp
DESCRIPTION
MIN
TYP
MAX UNIT
Parallel resonance crystal frequency
32768
Hz
Cf1
Cf2
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
12
24
24
4
pF
pF
pF
pF
pF
pF
Ω
ESRxtal – 40 Ω
ESRxtal – 60 Ω
ESRxtal – 80 Ω
ESRxtal – 100 Ω
3
Cshunt Shunt capacitance
2
1
ESR
Crystal effective series resistance
100
When selecting a crystal, the system design must consider the temperature and aging characteristics of a based
on the worst case environment and expected life expectancy of the system.
Table 7-26 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 7-26. WKUP_LFOSC0 Switching Characteristics – Crystal Mode
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
Hz
fxtal
tsX
Oscillation frequency
Start-up time
32768
96.5
ms
VDD_WKUP (min.)
VSS
VDD_WKUP
VDDA_WKUP (min.)
VDDA_WKUP
WKUP_LFOSC0_XO
tsX
VSS
Time
J7ES_LF_OSC_STARTUP_13
Figure 7-36. WKUP_LFOSC0 Start-up Time
7.10.4.1.6.1 WKUP_LFOSC0 Not Used
Figure 7-37 shows the recommended oscillator connections when WKUP_LFOSC0 is not used.
WKUP_LFOSC0 may be a no-connect while the oscillator remains disabled since the internal pull-down resistor
is enabled by default.
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Device
WKUP_LFOSC0_XO
WKUP_LFOSC0_XI
NC
NC
J7ES_LF_OSC_NOT_USED_14
Figure 7-37. WKUP_LFOSC0 Not Used
7.10.4.2 Output Clocks
The device provides several system clock outputs. Summary of these output clocks are as follows:
•
MCU_CLKOUT0
– Reference clock output for Ethernet PHYs (50 MHz or 25 MHz)
MCU_SYSCLKOUT0
•
– SYSCLK0 of WKUP_PLLCTRL0 is divided by 6 and then sent out of the device as a LVCMOS clock signal
(MCU_SYSCLKOUT0). This signal can be used to test if the main chip clock is functioning or not.
•
•
MCU_OBSCLK0
– On the clock output MCU_OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug.
SYSCLKOUT0
– SYSCLK0 from the MAIN_PLL controller is divided by 6 and then sent out of the device as a LVCMOS
clock signal (SYSCLKOUT0). This signal can be used to test if the main chip clock is functioning or not.
•
•
CLKOUT
– Reference clock output
OBSCLK[2:0]
– On the clock output OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug.
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7.10.4.3 PLLs
Power is supplied to the Phase-Locked Loop circuitries (PLLs) by internal regulators that derive power from the
off-chip power-supply.
There are total of three PLLs in the device in WKUP and MCU domains:
•
•
•
MCU_PLL0 (MCU R5FSS PLL) with WKUP_PLLCTRL0
MCU_PLL1 (MCU PERIPHERAL PLL)
MCU_PLL2 (MCU CPSW PLL)
There are total of twenty PLLs in the device in MAIN domain:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PLL0 (MAIN PLL) with PLLCTRL0
PLL1 (PER0 PLL)
PLL2 (PER1 PLL)
PLL3 (CPSW9G PLL)
PLL4 (AUDIO0 PLL)
PLL5 (VIDEO PLL)
PLL6 (GPU PLL)
PLL7 (C7x PLL)
PLL8 (ARM0 PLL)
PLL12 (DDR PLL)
PLL13 (C66 PLL)
PLL14 (R5F PLL)
PLL15 (AUDIO1 PLL)
PLL16 (DSS PLL0)
PLL17 (DSS PLL1)
PLL18 (DSS PLL2)
PLL19 (DSS PLL3)
PLL23 (DSS PLL7)
PLL24 (MLB PLL)
PLL25 (VISION PLL)
Note
For more information, see:
•
•
Device Configuration / Clocking / PLLs section in the device TRM.
Peripherals / Display Subsystem Overview section in the device TRM.
Note
The input reference clock (OSC1_XI/OSC1_XO) is specified and the lock time is ensured by the PLL
controller, as documented in the Device Configuration chapter in the device TRM.
7.10.4.4 Module and Peripheral Clocks Frequencies
Section 7.10.5, Peripherals section documents the maximum frequency associated with the peripheral clocks of
the device.
For more details on the clocking structure of each module, reference Device Configurations chapter in the device
TRM.
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7.10.5 Peripherals
7.10.5.1 ATL
The device contains ATL module that can be used for asynchronous sample rate conversion of audio. The ATL
calculates the error between two time bases, such as audio syncs, and optionally generates an averaged clock
using cycle stealing via software.
Note
For more information about ATL, see Audio Tracking Logic (ATL) section in Peripherals chapter in the
device TRM.
Table 7-27 represents ATL timing conditions.
Table 7-27. ATL Timing Conditions
PARAMETER
MODE
MIN
0.5
1
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
External reference CLK
Internal reference CLK
OUTPUT CONDITIONS
CL
Output load capacitance
10
Section 7.10.5.1.1, Section 7.10.5.1.2, Section 7.10.5.1.3, and Section 7.10.5.1.4 present timing requirements
and switching characteristics for ATL.
7.10.5.1.1 ATL_PCLK Timing Requirements
NO.
PARAMETER
MODE
MIN
MAX UNIT
External reference
CLK
D1 tc(pclk)
Cycle time, ATL_PCLK
5
ns
External reference
CLK
D2 tw(pclkL)
Pulse Duration, ATL_PCLK low
Pulse Duration, ATL_PCLK high
0.45 × M(1) + 2.5
0.45 × M(1) + 2.5
ns
ns
External reference
CLK
D3 tw(pclkH)
(1) M = ATL_CLK[x] period
7.10.5.1.2 ATL_AWS[x] Timing Requirements
NO.
MODE
MIN
MAX UNIT
External reference
CLK
D4 tc(aws)
D5 tw(awsL)
D6 tw(awsH)
Cycle Time, ATL_AWS[x](3)
2 × M(1)
ns
External reference
CLK
Pulse Duration, ATL_AWS[x](3) low
Pulse Duration, ATL_AWS[x](3) high
0.45 × A(2) + 2.5
0.45 × A(2) + 2.5
ns
ns
External reference
CLK
(1) M = ATL_CLK[x] period
(2) A = ATL_AWS[x] period
(3) x = 0 to 3
7.10.5.1.3 ATL_BWS[x] Timing Requirements
NO.
MODE
MIN
MAX UNIT
External reference
clock
D7 tc(bws)
Cycle Time, ATL_BWS[x](3)
2 × M(1)
ns
External reference
clock
D8 tw(bwsL)
Pulse Duration, ATL_BWS[x] low(3)
0.45 × B(2) + 2.5
ns
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MODE
MIN
MAX UNIT
External reference
clock
D9 tw(bwsH)
Pulse Duration, ATL_BWS[x] high(3)
0.45 × B(2) + 2.5
ns
(1) M = ATL_CLK[x] period
(2) B = ATL_BWS[x] period
(3) x = 0 to 3
7.10.5.1.4 ATCLK[x] Switching Characteristics
NO.
PARAMETER
MODE
MIN
MAX UNIT
Internal reference
CLK
D10 tc(atclk)
Cycle time, ATCLK[x](3)
20
ns
Internal reference
CLK
D11 tw(atclkL)
D12 tw(atclkH)
Pulse Duration, ATCLK[x] low(3)
Pulse Duration, ATCLK[x] high(3)
0.45 × P(2) - M(1) - 0.3
0.45 × P(2) - M(1) - 0.3
ns
ns
Internal reference
CLK
(1) M = ATL_CLK[x] period
(2) P = ATCLK[x] period
(3) x = 0 to 3
D10
D12
ATCLK[x]
D11
atl_01
Figure 7-38. ATCLK[x] Timing
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7.10.5.2 VPFE
Table 7-28 represents VPFE timnig conditions.
Table 7-28. VPFE Timing Conditions
PARAMETER
MIN
MAX
2.64
50
UNIT
V/ns
ps
INPUT CONDITIONS
SRI
Input slew rate
1.3
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch Delay) Propagation delay mismatch across
all traces
Table 7-29, Figure 7-39, and Figure 7-40 represent timing requirements for VPFE0.
Table 7-29. Timing Requirements for VPFE0
NO.(1)
MIN
6.06(1)
MAX
UNIT
ns
V1
V2
V3
tc(pclk)
Cycle time, VPFE0_PCLK
tw(pclkH)
tw(pclkL)
Pulse duration, VPFE0_PCLK high
Pulse duration, VPFE0_PCLK low
0.45 × P(2)
0.45 × P(2)
ns
ns
Setup time, control signals (VPFE0_HD, VPFE0_VD,
VPFE0_WEN, VPFE0_FIELD) valid before VPFE0_PCLK
transition
V4
V5
V6
tsu(ctrlV-pclkV)
2.12
2.38
ns
ns
ns
Setup time, VPFE0_DATA[15:0] valid before VPFE0_PCLK
transition
tsu(dataV-pclkV)
Hold time, control signals (VPFE0_HD, VPFE0_VD, VPFE0_WEN,
VPFE0_FIELD) and VPFE0_DATA[15:0] valid after VPFE0_PCLK
transition
th(pclkV-ctrlV/dataV)
-0.05
(1) For maximum frequency of 165 MHz.
(2) P = VPFE0_PCLK period.
V2
V1
V3
VPFE0_PCLK
VPFE0_TIMING_01
Figure 7-39. VPFE0 Clock Signal Requirement
VPFE0_PCLK
(Positive-edge clocking)
VPFE0_PCLK
(Negative-edge clocking)
V4
V5
V6
V6
VPFE0_HD, VPFE0_VD,
VPFE0_WEN, VPFE0_FIELD
VPFE0_DATA[15:0]
VPFE0_TIMING_02
Figure 7-40. VPFE0 Timing Requirements
For more information, see Video Processing Front End (VPFE) section in Peripherals chapter in the device TRM.
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7.10.5.3 CPSW2G
For more details about features and additional description information on the device Gigabit Ethernet MAC, see
the corresponding sections within , Section 6.3, Signal Descriptions and Section 8, Detailed Description.
7.10.5.3.1 CPSW2G MDIO Interface Timings
Table 7-30 represents CPSW2G timing conditions.
Table 7-30. CPSW2G MDIO Timing Conditions
PARAMETER
INPUT CONDITIONS
SRI
DESCRIPTION
MIN
0.9
10
MAX
UNIT
V/ns
pF
Input signal slew rate
3.6
OUTPUT CONDITIONS
CL Output load capacitance
470
Table 7-31, Table 7-32, and Figure 7-41 present timing requirements for MDIO.
Table 7-31. CPSW2G MDIO Timing Requirements
NO.
MIN
MAX
UNIT
ns
MDIO1 tsu(mdioV-mdcH)
MDIO2 th(mdcH-mdioV)
Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high
Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high
90
0
ns
Table 7-32. CPSW2G MDIO Switching Characteristics
NO.
PARAMETER
MIN
400
160
160
-150
MAX
UNIT
ns
MDIO3 tc(mdc)
MDIO4 tw(mdcH)
MDIO5 tw(mdcL)
MDIO7 td(mdcL-mdioV)
Cycle time, MDIO[x]_MDC
Pulse Duration, MDIO[x]_MDC high
Pulse Duration, MDIO[x]_MDC low
Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid
ns
ns
150
ns
MDIO3
MDIO4
MDIO5
MDIO[x]_MDC
MDIO1
MDIO2
MDIO[x]_MDIO
(input)
MDIO7
MDIO[x]_MDIO
(output)
CPSW2G_MDIO_TIMING_01
Figure 7-41. CPSW2G MDIO Timing Requirements and Switching Characteristics
Note
x = 0 in MCU domain
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7.10.5.3.2 CPSW2G RMII Timings
Table 7-33, Section 7.10.5.3.2.1, Section 7.10.5.3.2.2, and Section 7.10.5.3.2.3 present timing conditions,
requirements, and switching characteristics for CPSW2G RMII.
Table 7-33. CPSW2G RMII Timing Conditions
PARAMETER
MIN
MAX
UNIT
INPUT CONDITIONS
SRI Input signal slew rate
VDDSHVx(1) = 1.8V
VDDSHVx(1) = 3.3V
0.2
0.8
0.54
1.2
V/ns
V/ns
OUTPUT CONDITIONS
CL Output load capacitance
3
25
pF
(1) x = 0 - 5, where x indicates the respective IO power rail. Refer to Pin Attributes for more information
on IO power rail assinments.
7.10.5.3.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
see Figure 7-42
NO.
MIN
MAX
20.001
13
UNIT
ns
RMII1
RMII2
RMII3
tc(ref_clk)
Cycle time, RMII[x]_REF_CLK
19.999
tw(ref_clkH)
tw(ref_clkL)
Pulse Duration, RMII[x]_REF_CLK high
Pulse Duration, RMII[x]_REF_CLK low
7
7
ns
13
ns
RMII1
RMII2
RMII[x]_REF_CLK
RMII3
A. x = 1 in MCU domain.
Figure 7-42. CPSW2G RMII[x]_REFCLK Timing Requirements – RMII Mode
7.10.5.3.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
NO.
MIN
MAX
UNIT
Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK rising
edge
tsu(rxdV-ref_clkH)
tsu(crs_dvV-ref_clkH)
tsu(rx_erV-ref_clkH)
th(ref_clkH-rxdV)
4
ns
Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK rising
edge
RMII4
4
4
2
ns
ns
ns
Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK rising
edge
Hold time, RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK rising
edge
RMII5
Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK rising
edge
th(ref_clkH-crs_dvV)
th(ref_clkH-rx_erV)
2
2
ns
ns
Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK rising edge
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RMII4
RMII5
RMII[x]_REF_CLK
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RX_ER
Figure 7-43. CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Timing Requirements – RMII
Mode
Section 7.10.5.3.2.3, and Figure 7-44 present switching characteristics for CPSW2G RMII Transmit.
7.10.5.3.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
see Figure 7-44
NO.
PARAMETER
MIN
2
MAX UNIT
td(ref_clkH-txdV)
Delay time, RMII[x]_REF_CLK rising edge to RMII[x]_TXD[1:0] valid
13
13
ns
ns
RMII6
td(ref_clkH-tx_enV) Delay time, RMII[x]_REF_CLK rising edge to RMII[x]_TX_EN valid
2
RMII6
RMII[x]_REF_CLK
RMII[x]_TXD[1:0], RMII[x]_TX_EN
Figure 7-44. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
7.10.5.3.3 CPSW2G RGMII Timings
Section 7.10.5.3.3.1, Section 7.10.5.3.3.2, and Figure 7-46 present timing requirements for receive RGMII
operation.
For more information, see Gigabit Ethernet MAC (MCU_CPSW0) section in Peripherals chapter in the device
TRM.
Table 7-34. CPSW2G RGMII Timing Conditions
PARAMETER
MIN
2.64
2
MAX UNIT
INPUT CONDITIONS
SRI
Input slew rate
5
V/ns
pF
OUTPUT CONDITIONS
CL
Output load capacitance
20
PCB CONNECTIVITY REQUIREMENTS
RGMII[x]_RXC,
RGMII[x]_RD[3:0],
RGMII[x]_RX_CTL
50
50
ps
ps
td(Trace Mismatch
Propagation delay mismatch across all traces
Delay)
RGMII[x]_TXC,
RGMII[x]_TD[3:0],
RGMII[x]_TX_CTL
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7.10.5.3.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
see Figure 7-45
NO.
MODE
10Mbps
MIN
360
36
MAX UNIT
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
RGMII1 tc(rxc)
RGMII2 tw(rxcH)
RGMII3 tw(rxcL)
Cycle time, RGMII[x]_RXC
100Mbps
1000Mbps
10Mbps
7.2
160
16
8.8
240
24
Pulse duration, RGMII[x]_RXC high
Pulse duration, RGMII[x]_RXC low
100Mbps
1000Mbps
10Mbps
3.6
160
16
4.4
240
24
100Mbps
1000Mbps
3.6
4.4
7.10.5.3.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
see Figure 7-45
NO.
MODE
10Mbps
MIN
1
MAX UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Setup time, RGMII[x]_RD[3:0] valid before RGMII[x]_RXC
transition
tsu(rdV-rxcV)
tsu(rx_ctlV-rxcV)
th(rxcV-rdV)
100Mbps
1000Mbps
10Mbps
1
1
RGMII4
1
Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC
transition
100Mbps
1000Mbps
10Mbps
1
1
1
Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC
transition
100Mbps
1000Mbps
10Mbps
1
1
RGMII5
1
Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC
transition
th(rxcV-rx_ctlV)
100Mbps
1000Mbps
1
1
RGMII1
RGMII2
RGMII3
RGMII[x]_RXC(A)
RGMII4
RGMII5
RGMII[x]_RD[3:0](B)
RGMII[x]_RX_CTL(B)
1st Half-byte
RXDV
2nd Half-byte
RXERR
A. RGMII_RXC must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. RGMII_RXD[3:0] carries data bits 3-0 on the rising edge of
RGMII_RXC and data bits 7-4 on the falling edge of RGMII_RXC. Similarly, RGMII_RXCTL carries RXDV on rising edge of RGMII_RXC
and RXERR on falling edge of RGMII_RXC.
Figure 7-45. CPSW2G Receive Interface Timing, RGMII Operation
Section 7.10.5.3.3.3, Section 7.10.5.3.3.4 present switching characteristics for transmit - RGMII for 10 Mbps, 100
Mbps, and 1000 Mbps.
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7.10.5.3.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
NO.
PARAMETER
MODE
10Mbps
MIN
360
36
MAX UNIT
tc(txc)
Cycle time, RGMII[x]_TXC
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
RGMII6
100Mbps
1000Mbps
10Mbps
7.2
160
16
8.8
240
24
tw(txcH)
Pulse duration, RGMII[x]_TXC high
Pulse duration, RGMII[x]_TXC low
RGMII7
RGMII8
100Mbps
1000Mbps
10Mbps
3.6
160
16
4.4
240
24
tw(txcL)
100Mbps
1000Mbps
3.6
4.4
7.10.5.3.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
see Figure 7-46
NO.
PARAMETER
MODE
10Mbps
MIN
1.2
MAX UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC
transition
tosu(tdV-txcV)
tosu(tx_ctlV-txcV)
toh(tdV-txcV)
100Mbps
1000Mbps
10Mbps
1.2
1.05
1.2
RGMII9
Output setup time, RGMII[x]_TX_CTL valid to RGMII[x]_TXC
transition
100Mbps
1000Mbps
10Mbps
1.2
1.05
1.2
Output hold time, RGMII[x]_TD[3:0] valid after RGMII[x]_TXC
transition
100Mbps
1000Mbps
10Mbps
1.2
1.05
1.2
RGMII10
Output hold time, RGMII[x]_TX_CTL valid after
RGMII[x]_TXC transition
toh(tx_ctlV-txcV)
100Mbps
1000Mbps
1.2
1.05
RGMII6
RGMII7
RGMII8
RGMII[x]_TXC(A)
RGMII9
RGMII[x]_TD[3:0](B)
RGMII[x]_TX_CTL(B)
1st Half-byte
TXEN
2nd Half-byte
TXERR
RGMII10
A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.
B. Data and control information is received using both edges of the clocks. RGMII_TD[3:0] carries data bits 3-0 on the rising edge of
RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TX_CTL carries TXDV on rising edge of RGMII_TXC
and RTXERR on falling edge of RGMII_TXC.
Figure 7-46. CPSW2G Transmit Interface Timing RGMII Mode
7.10.5.4 CPSW9G
For more details about features and additional description information on the device Gigabit Ethernet MAC, see
the corresponding sections within , Section 6.3, Signal Descriptions and Section 8, Detailed Description.
Table 7-35 represents CPSW9G timing conditions.
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Table 7-35. CPSW9G Timing Conditions
PARAMETER
INPUT CONDITIONS
SRI Input signal slew rate
OUTPUT CONDITIONS
MIN
0.9
10
MAX
3.6
UNIT
V/ns
pF
CL
Output load capacitance
470
7.10.5.4.1 CPSW9G MDIO Interface Timings
Table 7-36, Table 7-37, and Figure 7-47 present timing requirements and switching characteristics for MDIO.
Table 7-36. CPSW9G MDIO Timing Requirements
NO.
PARAMETER(1)
MIN
90
0
MAX
UNIT
ns
MDIO1 tsu(mdioV-mdcH)
MDIO2 th(mdcH-mdioV)
Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high
Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high
ns
Table 7-37. CPSW9G MDIO Switching Characteristics
NO.
PARAMETER(1)
MIN
400
160
160
-150
MAX
UNIT
ns
MDIO3 tc(mdc)
MDIO4 tw(mdcH)
MDIO5 tw(mdcL)
MDIO7 td(mdcL-mdioV)
Cycle time, MDIO[x]_MDC
Pulse Duration, MDIO[x]_MDC high
ns
Pulse Duration, MDIO[x]_MDC low
ns
Delay time, MDIO[x]_MDC falling edge to MDIO[x]_MDIO valid
150
ns
(1) x = 0
MDIO3
MDIO4
MDIO5
MDIO[x]_MDC
MDIO1
MDIO2
MDIO[x]_MDIO
(input)
MDIO7
MDIO[x]_MDIO
(output)
CPSW2G_MDIO_TIMING_01
Figure 7-47. CPSW9G MDIO Diagrams Receive and Transmit
7.10.5.4.2 CPSW9G RMII Timings
Table 7-38, Section 7.10.5.4.2.1, Section 7.10.5.4.2.2, and Figure 7-48 present timing requirements for
CPSW9G RMII receive.
Table 7-38. CPSW9G RMII Timing Conditions
PARAMETER
MIN
MAX UNIT
INPUT CONDITIONS
VDDSHVx(1) = 1.8V
VDDSHVx(1) = 3.3V
0.108
0.4
0.54 V/ns
1.2 V/ns
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
3
25
pF
(1) x = 0 - 5, where x indicates the respective IO power rail. Refer to Pin Attributes for more information on IO power rail assinments.
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7.10.5.4.2.1 RMII[x]_REF_CLK Timing Requirements – RMII Mode
see Figure 7-48
NO.
MIN
TYP
MAX
20.001
13
UNIT
ns
RMII1 tc(ref_clk)
RMII2 tw(ref_clkH)
RMII3 tw(ref_clkL)
Cycle time, RMII[x]_REF_CLK
19.999
Pulse Duration, RMII[x]_REF_CLK high
Pulse Duration, RMII[x]_REF_CLK low
7
7
ns
13
ns
RMII1
RMII2
RMII[x]_REF_CLK
RMII3
Figure 7-48. RMII[x]_REF_CLK Timing Requirements – RMII Mode
7.10.5.4.2.2 RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
NO.
PARAMETER
tsu(rxdV-ref_clkH)
DESCRIPTION
MIN
TYP
MAX UNIT
RMII4
Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK rising
edge
4
ns
tsu(crs_dvV-ref_clkH)
tsu(rx_erV-ref_clkH)
th(ref_clkH-rxdV)
Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK rising
edge
4
4
2
2
2
ns
ns
ns
ns
ns
Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK rising
edge
RMII5
Hold time, RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK rising
edge
th(ref_clkH-crs_dvV)
th(ref_clkH-rx_erV)
Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK rising
edge
Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK rising edge
RMII4
RMII5
RMII[x]_REF_CLK
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RX_ER
Figure 7-49. CPSW9G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER Timing Requirements – RMII
Mode
Section 7.10.5.4.2.3 and present switching characteristics for CPSW9G RMII transmit.
7.10.5.4.2.3 RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics – RMII Mode
NO.
PARAMETER
MIN
TYP
MAX UNIT
RMII6 td(ref_clkH-txdV)
Delay time, RMII[x]_REF_CLK rising edge to RMII[x]_TXD[1:0]
valid
2
13
ns
td(ref_clkH-tx_enV)
Delay time, RMII[x]_REF_CLK rising edge to RMII[x]_TX_EN
valid
2
13
ns
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RMII6
RMII[x]_REF_CLK
RMII[x]_TXD[1:0], RMII[x]_TX_EN
Figure 7-50. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
7.10.5.4.3 CPSW9G RGMII Timings
Table 7-39, Section 7.10.5.4.3.1, Section 7.10.5.4.3.2, and Figure 7-51 present timing requirements for receive
RGMII operation.
For more information, see Gigabit Ethernet Switch (CPSW0) section in Peripherals chapter in the device TRM.
Table 7-39. CPSW9G RGMII Timing Conditions
PARAMETER
MIN
2.64
2
MAX UNIT
INPUT CONDITIONS
SRI
Input slew rate
5
V/ns
pF
OUTPUT CONDITIONS
CL
Output load capacitance
20
PCB CONNECTIVITY REQUIREMENTS
RGMII[x]_RXC,
RGMII[x]_RD[3:0],
RGMII[x]_RX_CTL
50
50
ps
ps
td(Trace Mismatch
Propagation delay mismatch across all traces
Delay)
RGMII[x]_TXC,
RGMII[x]_TD[3:0],
RGMII[x]_TX_CTL
7.10.5.4.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
360
36
MAX UNIT
10Mbps
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
RGMII1 tc(rxc)
RGMII2 tw(rxcH)
RGMII3 tw(rxcL)
Cycle time, RGMII[x]_RXC
100Mbps
1000Mbps
10Mbps
7.2
160
16
8.8
240
24
Pulse duration, RGMII[x]_RXC high
Pulse duration, RGMII[x]_RXC low
100Mbps
1000Mbps
10Mbps
3.6
160
16
4.4
240
24
100Mbps
1000Mbps
3.6
4.4
7.10.5.4.3.2 RGMII[x]_RD[3:0] and RGMII[x]_RCTL Timing Requirements – RGMII Mode
see Figure 7-51
NO.
MODE
MIN
MAX UNIT
10Mbps
100Mbps
1000Mbps
10Mbps
1
1
1
1
1
1
ns
ns
ns
ns
ns
ns
Setup time, RGMII[x]_RD[3:0] valid before RGMII[x]_RXC
transition
tsu(rdV-rxcV)
RGMII4
Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC
transition
tsu(rx_ctlV-rxcV)
100Mbps
1000Mbps
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see Figure 7-51
NO.
MODE
10Mbps
MIN
1
MAX UNIT
ns
ns
ns
ns
ns
ns
Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC
transition
th(rxcV-rdV)
100Mbps
1000Mbps
10Mbps
1
1
RGMII5
1
Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC
transition
th(rxcV-rx_ctlV)
100Mbps
1000Mbps
1
1
RGMII1
RGMII2
RGMII3
RGMII[x]_RXC(A)
RGMII4
RGMII5
RGMII[x]_RD[3:0](B)
1st Half-byte
RXDV
2nd Half-byte
RXERR
RGMII[x]_RX_CTL(B)
A. RGMII_RXC must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. RGMII_RXD[3:0] carries data bits 3-0 on the rising edge of
RGMII_RXC and data bits 7-4 on the falling edge of RGMII_RXC. Similarly, RGMII_RXCTL carries RXDV on rising edge of RGMII_RXC
and RXERR on falling edge of RGMII_RXC.
Figure 7-51. CPSW9G RGMII[x]_RXC, RGMII[x]_RD[3:0] and RGMII[x]_RCTL Timing Requirements –
RGMII Mode
Section 7.10.5.4.3.3, Section 7.10.5.4.3.4, and Figure 7-52 present switching characteristics for transmit - RGMII
for 10 Mbps, 100 Mbps, and 1000 Mbps.
7.10.5.4.3.3 RGMII[x]_TXC Switching Characteristics – RGMII Mode
see Figure 7-52
NO.
PARAMETER
MODE
10Mbps
MIN
360
36
TYP
MAX UNIT
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
RGMII6 tc(txc)
Cycle time, RGMII[x]_TXC
100Mbps
1000Mbps
10Mbps
7.2
160
16
8.8
240
24
RGMII7 tw(txcH)
Pulse duration, RGMII[x]_TXC high
Pulse duration, RGMII[x]_TXC low
100Mbps
1000Mbps
10Mbps
3.6
160
16
4.4
240
24
RGMII8 tw(txcL)
100Mbps
1000Mbps
3.6
4.4
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7.10.5.4.3.4 RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
see Figure 7-52
NO.
PARAMETER
MODE
10Mbps
MIN
1.2
MAX UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC
transition
tosu(tdV-txcV)
tosu(tx_ctlV-txcV)
toh(tdV-txcV)
100Mbps
1000Mbps
10Mbps
1.2
1.05
1.2
RGMII9
Output setup time, RGMII[x]_TX_CTL valid to
RGMII[x]_TXC transition
100Mbps
1000Mbps
10Mbps
1.2
1.05
1.2
Output hold time, RGMII[x]_TD[3:0] valid after
RGMII[x]_TXC transition
100Mbps
1000Mbps
10Mbps
1.2
1.05
1.2
RGMII1
0
Output hold time, RGMII[x]_TX_CTL valid after
RGMII[x]_TXC transition
toh(tx_ctlV-txcV)
100Mbps
1000Mbps
1.2
1.05
RGMII6
RGMII7
RGMII8
RGMII[x]_TXC(A)
RGMII9
RGMII[x]_TD[3:0](B)
1st Half-byte
TXEN
2nd Half-byte
TXERR
RGMII10
RGMII[x]_TX_CTL(B)
A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.
B. Data and control information is received using both edges of the clocks. RGMII_TD[3:0] carries data bits 3-0 on the rising edge of
RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TX_CTL carries TXDV on rising edge of RGMII_TXC
and RTXERR on falling edge of RGMII_TXC.
Figure 7-52. CPSW9G RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics
- RGMII Mode
7.10.5.5 CSI-2
Note
For more information, see the Camera Streaming Interface Receiver (CSI_RX_IF) chapter in the
device TRM.
The CSI_RX_IF deals with the processing of the pixel data coming from an external image sensor and data from
memory. It is a key component for the following multimedia applications: camera viewfinder, video record, and
still image capture.
The CSI_RX_IF has a primary serial interface (CSI-2 port) compliant with the MIPI D-PHY RX specification v1.2
and the MIPI CSI-2 specification v1.3, with 4 differential data lanes plus 1 differential clock lane in synchronous
mode, double data rate. Refer to the specification for timing details.
•
2.5 Gbps (1.25 GHz) for each lane.
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7.10.5.6 DDRSS
For more details about features and additional description information on the device LPDDR4 Memory
Interfaces, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed
Description.
The device has dedicated interface to LPDDR4. It supports JEDEC JESD209-4B standard compliant LPDDR4
SDRAM devices with the following features:
•
•
32-bit data path to external SDRAM memory
Memory device capacity: Up to 8GB address space available over two chip selects (4GB per rank).
Table 7-40 and Figure 7-53 present switching characteristics for DDRSS.
Table 7-40. Switching Characteristics for DDRSS
NO.
PARAMETER
DDR TYPE
MIN
MAX UNIT
3.003 ns
1
tc(DDR_CKP/DDR_CKN)
Cycle time, DDR0_CKP and DDR0_CKN
LPDDR4
0.536
1
DDR0_CKP
DDR0_CKN
Figure 7-53. DDRSS Memory Interface Clock Timing
For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.
7.10.5.7 DSS
For more details about features and additional description information on the device Display Subsystem – Video
Output Ports, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed
Description.
Table 7-41 represents DPI timing conditions.
Table 7-41. DPI Timing Conditions
PARAMETER
MIN
1.44
1.5
MAX
26.4
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
PCB CONNECTIVITY REQUIREMENTS
Propagation delay mismatch
across all traces
ps
td(Trace Mismatch Delay)
100
Table 7-42, Table 7-43, Figure 7-54 and Figure 7-55 assume testing over the recommended operating conditions
and electrical characteristic conditions.
Table 7-42. DPI Video Output Switching Characteristics
NO.(2)
D1
PARAMETER
MIN
6.06
MAX UNIT
tc(pclk)
Cycle time, VOUT(x)_PCLK
ns
ns
ns
D2
tw(pclkL)
Pulse duration, VOUT(x)_PCLK low
Pulse duration, VOUT(x)_PCLK high
0.475×P(1)
0.475×P(1)
-0.68
D3
tw(pclkH)
td(pclkV-dataV)
D4
Delay time, VOUT(x)_PCLK transition to VOUT(x)_DATA[23:0]
transition
1.78
ns
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Table 7-42. DPI Video Output Switching Characteristics (continued)
NO.(2)
PARAMETER
MIN
MAX UNIT
1.78 ns
D5
td(pclkV-ctrlL)
Delay time, VOUT(x)_PCLK transition to control signals
-0.68
VOUT(x)_VSYNC, VOUT(x)_HSYNC, VOUT(x)_DE falling edge
(1) P = output VOUT(x)_PCLK period in ns.
(2) x in VOUT(x) = 1 or 2
D2
D3
D1
Falling-edge Clock Reference
Rising-edge Clock Reference
VOUT(x)_PCLK
VOUT(x)_PCLK
D5
VOUT(x)_VSYNC
D5
VOUT(x)_HSYNC
D4
VOUT(x)_DATA[23:0]
VOUT(x)_DE
data_1 data_2
D5
data_n
DPI_TIMING_01
A. The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
B. The polarity and the pulse width of VOUT(x)_HSYNC and VOUT(x)_VSYNC are programmable, refer to Display Subsystem (DSS)
section in Peripherals chapter in the device TRM.
C. The VOUT(x)_PCLK frequency can be configured, refer to Display Subsystem section in Peripherals chapter in the device TRM.
D. x in VOUT(x) = 1 or 2.
Figure 7-54. DPI Video Output
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Table 7-43. DPI External Pixel Clock Timing Requirements
NO.(2)
D6
MIN
MAX
UNIT
ns
tc(extpclkin)
Cycle time, VOUT(x)_EXTPCLKIN
6.06
D7
tw(extpclkinL)
tw(extpclkinH)
Pulse duration, VOUT(x)_EXTPCLKIN low
Pulse duration, VOUT(x)_EXTPCLKIN high
0.45×P(1)
0.45×P(1)
ns
D8
ns
(1) P = output VOUT(x)_PCLK period in ns.
(2) x in VOUT(x) = 1 or 2
D7
D8
D6
Falling-edge Clock Reference
Rising-edge Clock Reference
VOUT(x)_EXTPCLKIN
VOUT(x)_EXTPCLKIN
DPI_TIMING_02
Figure 7-55. DPI External Pixel Clock Input
For more information, see Display Subsystem (DSS) and Peripherals section in Peripherals chapter in the device
TRM.
7.10.5.8 eCAP
The supported features by the device ECAP are:
•
•
•
•
•
•
32-bit time base counter
4-event time-stamp registers (each 32 bits)
Independent edge polarity selection for up to four sequenced time-stamp capture events
Interrupt capabilities on any of the four capture events
Input capture signal pre-scaling (from 1 to 16)
Support of different capture modes (single shot capture, continuous mode capture, absolute timestamp
capture or difference mode time-stamp capture)
Table 7-44 represents ECAP timing conditions.
Table 7-44. ECAP Timing Conditions
PARAMETER
MIN
1
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
4
7
OUTPUT CONDITIONS
CL
Output load capacitance
2
Section 7.10.5.8.1 and Section 7.10.5.8.2 present timing and switching characteristics for eCAP (see Figure 7-56
and Figure 7-57).
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7.10.5.8.1 Timing Requirements for eCAP
NO.
PARAMETER
DESCRIPTION
Pulse duration, CAP (asynchronous)
MIN
2 + 2P(1)
MAX
UNIT
CAP1 tw(cap)
ns
(1) P = sysclk
CAP1
CAP
EPERIPHERALS_TIMNG_01
Figure 7-56. eCAP Input Timings
7.10.5.8.2 Switching Characteristics for eCAP
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
CAP2 tw(apwm)
Pulse duration, APWM
-2 + 2P(1)
ns
(1) P = sysclk
CAP2
APWM
EPERIPHERALS_TIMNG_02
Figure 7-57. eCAP Output Timings
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.
7.10.5.9 EPWM
The supported features by the device EPWM are:
•
•
Dedicated 16-bit time-base counter with period and frequency control
Two independent PWM outputs which can be used in different configurations (with single-edge operation,
with dual-edge symmetric operation or one independent PWM output with dual-edge asymmetric operation)
Asynchronous override control of PWM signals during fault conditions
Programmable phase-control support for lag or lead operation relative to other EPWM modules
Dead-band generation with independent rising and falling edge delay control
•
•
•
•
•
Programmable trip zone allocation of both latched and un-latched fault conditions
Events enabling to trigger both CPU interrupts and start of ADC conversions
Table 7-45 represents EPWM timing conditions.
Table 7-45. EPWM Timing Conditions
PARAMETER
DESCRIPTION
MIN
1
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
4
7
OUTPUT CONDITIONS
CL
Output load capacitance
2
Section 7.10.5.9.2, Section 7.10.5.9.1 and present timing and switching characteristics for eHRPWM (see Figure
7-59, Figure 7-60, Figure 7-61, and Figure 7-58).
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7.10.5.9.1 Timing Requirements for eHRPWM
NO.
PARAMETER
DESCRIPTION
Pulse duration, EHRPWM_SYNCI
MIN
2 + 2P(1)
2 + 3P(1)
MAX
UNIT
ns
PWM6 tw(synci)
PWM7 tw(tz)
Pulse duration, EHRPWM_TZn_IN low
ns
(1) P = sysclk
PWM6
EHRPWM_SYNCI
PWM7
EHRPWM_TZn_IN
EPERIPHERALS_TIMNG_07
Figure 7-58. ePWM_SYNCI and ePWM_TZn_IN Output Timings
For more information, see Camera Subsystem section in Peripherals chapter in the device TRM.
7.10.5.9.2 Switching Characteristics for eHRPWM
NO.
PARAMETER
DESCRIPTION
MIN
P-3(1)
P-3(1)
MAX
UNIT
PWM1 tw(pwm)
Pulse duration, EHRPWM_A/B, high or low
ns
ns
ns
ns
PWM2 tw(syncout)
PWM3 td(tzL-pwmV)
PWM4 td(tzL-pwmZ)
Pulse duration, EHRPWM_SYNCO
Delay time, EHRPWM_TZn_IN falling edge to EHRPWM_A/B valid
Delay time, EHRPWM_TZn_IN falling edge to EHRPWM_A/B Hi-Z
11
11
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NO.
PARAMETER
DESCRIPTION
Pulse duration, EHRPWM_SOCA/B
MIN
P-3(1)
MAX
UNIT
PWM5 tw(soc)
ns
(1) P = sysclk
PWM1
EHRPWM_A/B
PWM1
PWM2
EHRPWM_SYNCO
PWM5
EHRPWM_SOCA/B
EPERIPHERALS_TIMNG_04
Figure 7-59. EPWM_A/B_out, ePWM_SYNCO, and ePWM_SOCA/B Input Timings
PWM3
EPWM_A/B
EPQM_TZn_IN
EPERIPHERALS_TIMING_05
Figure 7-60. EPWM_A/B and ePWM_TZn_IN Forced High/Low Input Timings
PWM4
EPWM_A/B
EPQM_TZn_IN
EPERIPHERALS_TIMING_06
Figure 7-61. EPWM_A/B and ePWM_TZn_IN Hi–Z Input Timings
7.10.5.10 eQEP
The supported features by the device eQEP are:
•
•
•
•
•
•
•
Input Synchronization
Three Stage/Six Stage Digital Noise Filter
Quadrature Decoder Unit
Position Counter and Control unit for position measurement
Quadrature Edge Capture unit for low speed measurement
Unit Time base for speed/frequency measurement
Watchdog Timer for detecting stalls
Table 7-46 represents EQEP timing conditions.
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Table 7-46. EQEP Timing Conditions
PARAMETER
MIN
1
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
4
7
OUTPUT CONDITIONS
CL
Output load capacitance
2
Section 7.10.5.10.1 and Section 7.10.5.10.2 present timing requirements and switching characteristics for eQEP
(see Figure 7-62).
7.10.5.10.1 Timing Requirements for eQEP
NO.
MIN
2 + 2P(1)
2 + 2P(1)
2 + 2P(1)
2 + 2P(1)
2 + 2P(1)
MAX UNIT
QEP1
QEP2
QEP3
QEP4
QEP5
tw(qep)
Pulse duration, QEP_A/B
Pulse duration, QEP_I high
Pulse duration, QEP_I low
Pulse duration, QEP_S high
Pulse duration, QEP_S low
ns
ns
ns
ns
ns
tw(qepiH)
tw(qepiL)
tw(qepsH)
tw(qepsL)
(1) P = sysclk
QEP1
QEP_A/B
QEP2
QEP_I
QEP3
QEP4
QEP_S
QEP5
EPERIPHERALS_TIMNG_03
Figure 7-62. eQEP Input Timings
7.10.5.10.2 Switching Characteristics for eQEP
NO.
PARAMETER
Delay time, external clock to counter increment
MIN
MAX UNIT
QEP6
td(QEP-CNTR)
24
ns
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter
in the device TRM.
7.10.5.11 GPIO
The device has ten instances of GPIO modules. The GPIO modules are integrated in three groups.
•
•
•
Group one: WKUP_GPIO0 and WKUP_GPIO1
Group two: GPIO0, GPIO2, GPIO4, and GPIO6
Group three: GPIO1, GPIO3, GPIO5, and GPIO7
Within each group, exactly one module is selected to control the corresponding I/O pins and pin interrupts.
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The GPIO pins are grouped into banks (16 pins per bank), which means that each GPIO module provides up
to 144 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface
supports up to 432 (3 instances × (9 banks × 16 pins)) pins. Since WKUP_GPIOu_[84:143] (u = 0, 1),
GPIOn_[128:143] (n = 0, 2, 4, 6), and GPIOm_[36:143] (m = 1, 3, 5 ,7) are reserved in this device, general
purpose interface supports up to 248 I/O pins.
For more details about features and additional description information on the device General-Purpose Interface,
see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
Note
The general-purpose input/output i (i = 0 to 1) is also referred to as GPIOi.
Table 7-47 represents GPIO timing conditions.
Table 7-47. GPIO Timing Conditions
PARAMETER
BUFFER TYPE
MIN
MAX
UNIT
INPUT CONDITIONS
SRI
Input slew rate
LVCMOS
0.75
6.6
V/ns
OUTPUT CONDITIONS
CL
CL
Output load capacitance
Output load capacitance
LVCMOS
3
3
10
pF
pF
I2C Open Drain
100
Section 7.10.5.11.1 and Section 7.10.5.11.2 present timings and switching characteristics of the GPIO Interface.
7.10.5.11.1 GPIO Timing Requirements
NO.
BUFFER TYPE
LVCMOS
MIN
2P + 2.6(1)
2P + 2.6(1)
MAX UNIT
ns
ns
GPIO1 tw(gpio_in)
Pulse width, GPIOn_x
I2C Open Drain
(1) P = functional clock period in ns.
7.10.5.11.2 GPIO Switching Characteristics
NO.
PARAMETER
BUFFER TYPE
LVCMOS
MIN
0.975P - 3.6 (1)
160
MAX UNIT
ns
ns
GPIO2 tw(gpio_outL)
Pulse width, GPIOn_x low
I2C Open Drain
LVCMOS
0.975P - 3.6 (1)
GPIO3 tw(gpio_outH)
Pulse width, GPIOn_x high
I2C Open Drain
60
ns
(1) P = functional clock period in ns.
For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.
7.10.5.12 GPMC
For more details about features and additional description information on the device General-Purpose Memory
Controller, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed
Description.
Table 7-48 represents GPMC timing conditions.
Note
The IO timings provided in this section are applicable for all combinations of signals for GPMC0.
However, the timings are only valid for GPMC0 if signals within a single IOSET are used. The IOSETs
are defined in the Section 7.10.5.12.4 , GPMC0_IOSET,table.
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Table 7-48. GPMC Timing Conditions
PARAMETER
Input Conditions
tSR
DESCRIPTION
MIN
1.65
5
MAX
4
UNIT
V/ns
pF
Input slew rate
Output Conditions
CLOAD
Output load capacitance
20
7.10.5.12.1 GPMC and NOR Flash — Synchronous Mode
Section 7.10.5.12.1.1 and Section 7.10.5.12.1.2 assume testing over the recommended operating conditions
and electrical characteristic conditions below (see Figure 7-63 through Figure 7-67).
7.10.5.12.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
MIN
100 MHz(4)
MAX
MIN
133 MHz(4)
MAX
NO.
PARAMETER
DESCRIPTION(2)
MODE(3)
UNIT
F12 tsu(dV-clkH)
F13 th(clkH-dV)
F21 tsu(waitV-clkH)
F22 th(clkH-waitV)
Setup time, input data
GPMC_AD[15:0] valid before
output clock GPMC_CLK high
div_by_1_mode;
1.81
1.11
ns
ns
not_div_by_1_mode;
1.06
Hold time, input data
GPMC_AD[15:0] valid after
output clock GPMC_CLK high
div_by_1_mode;
1.78
1.78
2.28
1.11
2.28
ns
ns
not_div_by_1_mode;
Setup time, input wait
div_by_1_mode;
1.81
1.06
ns
ns
GPMC_WAIT[j] valid before
not_div_by_1_mode;
output clock GPMC_CLK high(1)
Hold time, input wait
div_by_1_mode;
1.78
1.78
ns
ns
GPMC_WAIT[j] valid after output
not_div_by_1_mode;
clock GPMC_CLK high(1)
(1) In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
(2) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-
Purpose Memory Controller (GPMC) section in the device TRM.
(3) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
GPMC_CLK frequency = GPMC_FCLK frequency
–
•
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:
GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)
–
(4) For 100 MHz:
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = MAIN_PLL2_HSDIV1_CLKOUT / 3
For 133 MHz:
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT
7.10.5.12.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
MIN
MAX
MIN
MAX
UNI
T
NO.(2) PARAMETER
DESCRIPTION
MODE(19)
100 MHz(20)
133 MHz(20)
F0 tc(clk)
F1 tw(clkH)
Period, output clock GPMC_CLK(18)
div_by_1_mode;
div_by_1_mode
10
7.52
ns
ns
Typical pulse duration, output clock
GPMC_CLK high
0.475*P
0.475*P
(15)- 0.3
(15)- 0.3
F1 tw(clkL)
Typical pulse duration, output clock
GPMC_CLK low
div_by_1_mode
0.475*P
(15)- 0.3
0.475*P
(15)- 0.3
ns
F2 td(clkH-csnV)
Delay time, output clock GPMC_CLK rising
edge to output chip select GPMC_CSn[i]
transition(14)
div_by_1_mode
no extra_delay
F(6)-2.2 F+3.75 F(6)-2.2 F(6)+3.75 ns
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MIN
100 MHz(20)
E(5)-2.2 E(5)+3.75 E(5)-2.2
MAX
MIN
MAX
UNI
T
NO.(2) PARAMETER
DESCRIPTION
MODE(19)
133 MHz(20)
F3 td(clkH-CSn[i]V)
Delay time, output clock GPMC_CLK rising
edge to output chip select GPMC_CSn[i]
invalid(14)
div_by_1_mode
no extra_delay
E
ns
(5)+3.75
F4 td(aV-clk)
Delay time, output address GPMC_A[27:1]
valid to output clock GPMC_CLK first edge
div_by_1_mode
div_by_1_mode;
B(2)-2.3 B(2)+4.5 B(2)-2.3 B(2)+4.5 ns
-2.3 4.5 -2.3 4.5 ns
F5 td(clkH-aIV)
Delay time, output clock GPMC_CLK rising
edge to output address GPMC_A[27:1]
invalid
F6 td(be[x]nV-clk)
Delay time, output lower byte enable and
command latch enable GPMC_BE0n_CLE,
output upper byte enable GPMC_BE1n
valid to output clock GPMC_CLK first edge
div_by_1_mode
div_by_1_mode
B(2)-2.3 B(2)+1.9 B(2)-2.3 B(2)+1.9 ns
F7 td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK rising
edge to output lower byte enable and
command latch enable GPMC_BE0n_CLE,
output upper byte enable GPMC_BE1n
invalid(11)
D(4)-2.3 D(4)+1.9 D(4)-2.3 D(4)+1.9 ns
F7 td(clkL-be[x]nIV)
Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
invalid(12)
div_by_1_mode
div_by_1_mode
D(4)-2.3 D(4)+1.9 D(4)-2.3 D(4)+1.9 ns
D(4)-2.3 D(4)+1.9 D(4)-2.3 D(4)+1.9 ns
G(7)-2.3 G(7)+4.5 G(7)-2.3 G(7)+4.5 ns
D(4)-2.3 D(4)+4.5 D(4)-2.3 D(4)+4.5 ns
H(8)-2.3 H(8)+3.5 H(8)-2.3 H(8)+3.5 ns
E(8)-2.3 E(8)+3.5 E(8)-2.3 E(8)+ 3.5 ns
I(9)- 2.3 I(9)+4.5 I(9)- 2.3 I(9)+4.5 ns
J(10)-2.3 J(10)+2.7 J(10)-2.3 J(10)+2.7 ns
F7 td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
invalid(13)
F8 td(clkH-advn)
F9 td(clkH-advnIV)
F10 td(clkH-oen)
F11 td(clkH-oenIV)
F14 td(clkH-wen)
F15 td(clkH-do)
Delay time, output clock GPMC_CLK rising
edge to output address valid and address
latch enable GPMC_ADVn_ALE transition
div_by_1_mode
no extra_delay
Delay time, output clock GPMC_CLK rising
edge to output address valid and address
latch enable GPMC_ADVn_ALE invalid
div_by_1_mode;
no extra_delay
Delay time, output clock GPMC_CLK rising
edge to output enable GPMC_OEn_REn
transition
div_by_1_mode
no extra_delay
Delay time, output clock GPMC_CLK rising
edge to output enable GPMC_OEn_REn
invalid
div_by_1_mode
no extra_delay
Delay time, output clock GPMC_CLK rising
edge to output write enable GPMC_WEn
transition
div_by_1_mode
no extra_delay
Delay time, output clock GPMC_CLK
rising edge to output data GPMC_AD[15:0]
transition(11)
div_by_1_mode
F15 td(clkL-do)
F15 td(clkL-do).
F17 td(clkH-be[x]n)
Delay time, GPMC_CLK falling edge to
GPMC_AD[15:0] data bus transition(12)
div_by_1_mode
div_by_1_mode
div_by_1_mode
J(10)-2.3 J(10)+2.7 J(10)-2.3 J(10)+2.7 ns
J(10)-2.3 J(10)+2.7 J(10)-2.3 J(10)+2.7 ns
J(10)-2.3 J(10)+1.9 J(10)-2.3 J(10)+1.9 ns
Delay time, GPMC_CLK falling edge to
GPMC_AD[15:0] data bus transition(13)
Delay time, output clock GPMC_CLK rising
edge to output lower byte enable and
command latch enable GPMC_BE0n_CLE
transition(11)
F17 td(clkL-be[x]n)
F17 td(clkL-be[x]n).
F18 tw(csnV)
Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
transition(12)
div_by_1_mode
div_by_1_mode
J(10)-2.3 J(10)+1.9 J(10)-2.3 J(10)+1.9 ns
J(10)-2.3 J(10)+1.9 J(10)-2.3 J(10)+1.9 ns
Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
transition(13)
Pulse duration, output chip select
GPMC_CSn[i] low(14)
Read
Write
A(1)
A(1)
A(1)
A(1)
ns
ns
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MIN
MAX
MIN
MAX
UNI
T
NO.(2) PARAMETER
DESCRIPTION
MODE(19)
100 MHz(20)
C(3)
133 MHz(20)
C(3)
F19 tw(be[x]nV)
Pulse duration, output lower byte
enable and command latch enable
GPMC_BE0n_CLE, output upper byte
enable GPMC_BE1n low
Read
Write
ns
ns
C(3)
C(3)
F20 tw(advnV)
Pulse duration, output address valid and
address latch enable GPMC_ADVn_ALE
low
Read
Write
K(16)
K(16)
K(16)
K(16)
ns
ns
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
With n being the page burst access number.
(2) B = ClkActivationTime × GPMC_FCLK(17)
(3) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
With n being the page burst access number.
(4) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(5) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(6) For csn falling edge (CS activated):
•
Case GPMCFCLKDIVIDER = 0:
F = 0.5 × CSExtraDelay × GPMC_FCLK(17)
Case GPMCFCLKDIVIDER = 1:
–
•
–
F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and
CSOnTime are even)
–
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime) is a multiple of 3)
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
(7) For ADV falling edge (ADV activated):
•
Case GPMCFCLKDIVIDER = 0:
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
Case GPMCFCLKDIVIDER = 1:
–
•
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and
ADVOnTime are even)
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
•
Case GPMCFCLKDIVIDER = 0:
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
Case GPMCFCLKDIVIDER = 1:
–
•
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and
ADVRdOffTime are even)
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
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–
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode:
•
Case GPMCFCLKDIVIDER = 0:
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
Case GPMCFCLKDIVIDER = 1:
–
•
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and
ADVWrOffTime are even)
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
(8) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):
•
Case GPMCFCLKDIVIDER = 0:
H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
Case GPMCFCLKDIVIDER = 1:
–
•
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and
OEOnTime are even)
–
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)
For OE rising edge (OE deactivated):
•
Case GPMCFCLKDIVIDER = 0:
H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
Case GPMCFCLKDIVIDER = 1:
–
•
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and
OEOffTime are even)
–
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
(9) For WE falling edge (WE activated):
•
Case GPMCFCLKDIVIDER = 0:
I = 0.5 × WEExtraDelay × GPMC_FCLK(17)
Case GPMCFCLKDIVIDER = 1:
–
•
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and
WEOnTime are even)
–
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)
For WE rising edge (WE deactivated):
•
Case GPMCFCLKDIVIDER = 0:
I = 0.5 × WEExtraDelay × GPMC_FCLK (17)
Case GPMCFCLKDIVIDER = 1:
–
•
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and
WEOffTime are even)
–
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
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Case GPMCFCLKDIVIDER = 2:
•
–
–
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
(10) J = GPMC_FCLK(17)
(11) First transfer only for CLK DIV 1 mode.
(12) Half cycle; for all data after initial transfer for CLK DIV 1 mode.
(13) Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.
(14) In GPMC_CSn[i], i is equal to 0, 1, 2, or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
(15) P = GPMC_CLK period in ns
(16) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(17) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(18) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the
GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.
(19) For div_by_1_mode:
•
GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:
GPMC_CLK frequency = GPMC_FCLK frequency
For no extra_delay:
–
•
•
•
•
GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed
GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed
GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed
GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed
(20) For 100 MHz:
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = MAIN_PLL2_HSDIV1_CLKOUT / 3
For 133 MHz:
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT
F1
F0
F1
GPMC_CLK
F2
F3
F18
GPMC_CSn[i]
F4
F6
GPMC_A[MSB:1]
Valid Address
F19
F7
GPMC_BE0n_CLE
GPMC_BE1n
F19
F6
F8
F8
F20
F9
GPMC_ADVn_ALE
GPMC_OEn_REn
F10
F11
F13
F12
D 0
GPMC_AD[15:0]
GPMC_WAIT[j]
GPMC_01
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
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B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 7-63. GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0)
F1
F0
F1
GPMC_CLK
GPMC_CSn[i]
GPMCA[MSB:1]
F2
F3
F4
F6
Valid Address
F7
GPMC_BE0n_CLE
GPMC_BE1n
F7
F9
F6
F8
F8
GPMC_ADVn_ALE
GPMC_OEn_REn
F10
F11
F13
F13
F12
D 0
F12
D 3
GPMC_AD[15:0]
GPMC_WAIT[j]
D 1
D 2
F21
F21
F22
F22
GPMC_02
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 7-64. GPMC and NOR Flash — Synchronous Burst Read — 4x16–bit (GPMCFCLKDIVIDER = 0)
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F1
F1
F0
GPMC_CLK
F2
F3
GPMC_CSn[i]
F4
F6
Valid Address
GPMC_A[MSB:1]
F17
F17
F17
F17
F17
GPMC_BE0n_CLE
GPMC_BE1n
F17
F6
F8
F8
F9
GPMC_ADVn_ALE
GPMC_WEn
F14
F14
F15
D 1
F15
D 2
F15
GPMC_AD[15:0]
GPMC_WAIT[j]
D 0
D 3
GPMC_03
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 7-65. GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)
F1
F0
F1
GPMC_CLK
F2
F3
GPMC_CSn[i]
F6
F6
F4
F7
GMPC_BE0n_CLE
Valid
F7
Valid
GPMC_BE1n
GPMC_A[27:17]
Address (MSB)
F5
F12
F13
F4
F12
GPMC_AD[15:0]
Address (LSB)
D0
D1
D2
D3
F8
F8
F9
GPMC_ADVn_ALE
F10
F11
GPMC_OEn_REn
GPMC_WAIT[j]
GPMC_04
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
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B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 7-66. GPMC and Multiplexed NOR Flash — Synchronous Burst Read
F1
F1
F0
GPMC_CLK
F2
F3
F18
GPMC_CSn[i]
F4
F6
F6
GPMC_A[27:17]
Address (MSB)
F17
F17
F17
F17
F17
F17
GPMC_BE1n
BPMC_BE0n_CLE
F8
F8
F20
F9
GPMC_ADVn_ALE
F14
F14
GPMC_WEn
F15
D 1
F15
D 2
F15
GPMC_AD[15:0]
Address (LSB)
D 0
F22
D 3
F21
F22
F21
GPMC_WAIT[j]
GPMC_05
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 7-67. GPMC and Multiplexed NOR Flash — Synchronous Burst Write
7.10.5.12.2 GPMC and NOR Flash — Asynchronous Mode
Section 7.10.5.12.2.1 and Section 7.10.5.12.2.2 assume testing over the recommended operating conditions
and electrical characteristic conditions below (see Figure 7-68 through Figure 7-73).
7.10.5.12.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
NO.
MODE(7)
MIN
MAX UNIT
H(5) ns
P(4) ns
H(5) ns
FA5(1) tacc(d)
Data access time
div_by_1_mode
div_by_1_mode
div_by_1_mode
FA20(2) tacc1-pgmode(d)
FA21(3) tacc2-pgmode(d)
Page mode successive data access time
Page mode first data access time
(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active
functional clock edge. FA5 value must be stored inside the AccessTime register bit field.
(2) The FA20 prameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional
clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by
active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.
(4) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)
(5) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)
(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
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(7) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
GPMC_CLK frequency = GPMC_FCLK frequency
–
7.10.5.12.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
MIN
133 MHz(16)
MAX
NO. PARAMETER
DESCRIPTION
MODE(15)
UNIT
FA0 tw(be[x]nV)
Pulse duration, output lower-byte enable and
command latch enable GPMC_BE0n_CLE, output
upper-byte enable GPMC_BE1n valid time
Read
Write
N(12) ns
N(12)
FA1 tw(csnV)
Pulse duration, output chip select GPMC_CSn[i](13)
low
Read
Write
Read
Write
A(1) ns
A(1)
FA3 td(csnV-advnIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output address valid and address latch
enable GPMC_ADVn_ALE invalid
B(2)-2.55 B(2)+2.65 ns
B(2)-2.55 B(2)+2.65
FA4 td(csnV-oenIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn invalid
(Single read)
div_by_1_mode;
ns
C(3)-2.55 C(3)+2.65
FA9 td(aV-csnV)
Delay time, output address GPMC_A[27:1] valid to
output chip select GPMC_CSn[i](13) valid
div_by_1_mode;
div_by_1_mode;
ns
J(9)-2.55 J(9)+2.65
FA10 td(be[x]nV-csnV)
Delay time, output lower-byte enable and
command latch enable GPMC_BE0n_CLE, output
upper-byte enable GPMC_BE1n valid to output
chip select GPMC_CSn[i](13) valid
ns
J(9)-2.55 J(9)+2.65
FA12 td(csnV-advnV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output address valid and address latch
enable GPMC_ADVn_ALE valid
div_by_1_mode;
ns
K
K(10)-2.55
(10)+2.65
FA13 td(csnV-oenV)
FA16 tw(aIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn valid
div_by_1_mode;
div_by_1_mode;
ns
L(11)-2.55 L(11)+2.65
Pulse duration output address GPMC_A[26:1]
invalid between 2 successive read and write
accesses
ns
G(7)
FA18 td(csnV-oenIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn invalid
(Burst read)
div_by_1_mode;
ns
I(8)-2.55 I(8)+2.65
FA20 tw(aV)
Pulse duration, output address GPMC_A[27:1]
valid - 2nd, 3rd, and 4th accesses
div_by_1_mode;
div_by_1_mode;
div_by_1_mode;
div_by_1_mode;
div_by_1_mode;
div_by_1_mode;
ns
D(4)
FA25 td(csnV-wenV)
FA27 td(csnV-wenIV)
FA28 td(wenV-dV)
FA29 td(dV-csnV)
FA37 td(oenV-aIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output write enable GPMC_WEn valid
ns
E(5)-2.55 E(5)+2.65
Delay time, output chip select GPMC_CSn[i](13)
valid to output write enable GPMC_WEn invalid
ns
F(6)-2.55 F(6)+2.65
Delay time, output write enable GPMC_WEn valid
to output data GPMC_AD[15:0] valid
ns
2.65
Delay time, output data GPMC_AD[15:0] valid to
output chip select GPMC_CSn[i](13) valid
ns
J(9)-2.55 J(9)+2.65
Delay time, output enable GPMC_OEn_REn valid
to output address GPMC_AD[15:0] phase end
ns
2.65
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
with n being the page burst access number
(2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×
GPMC_FCLK(14)
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×
GPMC_FCLK(14)
(3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
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(5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(7) G = Cycle2CycleDelay × GPMC_FCLK(14)
(8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay))
× GPMC_FCLK(14)
(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14)
(10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(15) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
GPMC_CLK frequency = GPMC_FCLK frequency
(16) For 133 MHz:
–
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT
GPMC_FCLK
GPMC_CLK
FA5
FA1
GPMC_CSn[i]
FA9
GPMC_A[MSB:1]
Valid Address
FA0
FA10
Valid
FA0
GPMC_BE0n_CLE
GPMC_BE1n
Valid
FA10
FA3
FA12
GPMC_ADVn_ALE
FA4
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
Data IN 0
Data IN 0
GPMC_WAIT[j]
GPMC_06
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-68. GPMC and NOR Flash — Asynchronous Read — Single Word
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GPMC_FCLK
GPMC_CLK
GPMC_CSn[i]
FA5
FA5
FA1
FA1
FA16
FA9
FA9
Address 0
FA0
Address 1
FA0
GPMC_A[MSB:1]
FA10
FA10
Valid
FA0
Valid
FA0
GPMC_BE0n_CLE
GPMC_BE1n
Valid
Valid
FA10
FA10
FA3
FA3
FA12
FA12
GPMC_ADCn_ALE
FA4
FA4
FA13
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
Data Upper
GPMC_WAIT[j]
GPMC_07
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-69. GPMC and NOR Flash — Asynchronous Read — 32–Bit
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GPMC_FCLK
GPMC_CLK
FA20
Add3
FA20
Add1
FA21
FA20
Add2
FA1
GPMC_CSn[i]
FA9
Add0
Add4
GPMC_A[MSB:1]
FA0
FA10
FA10
GPMC_BE0n_CLE
FA0
GPMC_BE1n
FA12
GPMC_ADVn_ALE
FA18
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
D3
D0
D1
D2
D3
GPMC_WAIT[j]
GPMC_08
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by
active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field.
C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC
functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first
input page data). FA20 value must be stored in PageBurstAccessTime register bits field.
D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-70. GPMC and NOR Flash — Asynchronous Read — Page Mode 4x16–Bit
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GPMC_FCLK
GPMC_CLK
FA1
GPMC_CSn[i]
FA9
GPMC_A[MSB:1]
GPMC_BE0n_CLE
GPMC_BE1n
Valid Address
FA0
FA10
FA10
FA0
FA3
FA12
GPMC_ADVn_ALE
FA27
FA25
GPMC_WEn
GPMC_AD[15:0]
GPMC_WAIT[j]
FA29
Data OUT
GPMC_09
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 7-71. GPMC and NOR Flash — Asynchronous Write — Single Word
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GPMC_FCLK
GPMC_CLK
FA1
FA5
GPMC_CSn[i]
FA9
Address (MSB)
FA0
GPMC_A[27:17]
FA10
GPMC_BE0n_CLE
Valid
FA0
FA10
GPMC_BE1n
Valid
FA3
FA12
GPMC_ADVn_ALE
FA4
FA13
GPMC_OEn_REn
FA29
FA37
Data IN
Data IN
Address (LSB)
GPMC_AD[15:0]
GPMC_WAIT[j]
GPMC_10
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-72. GPMC and Multiplexed NOR Flash — Asynchronous Read — Single Word
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GPMC_FCLK
GPMC_CLK
GPMC_CSn[i]
FA1
FA9
GPMC_A[27:17]
Address (MSB)
FA0
FA10
FA10
GPMC_BE0n_CLE
GPMC_BE1n
FA0
FA3
FA12
GPMC_ADVn_ALE
FA27
FA25
GPMC_WEn
FA29
FA28
GPMC_AD[15:0]
Valid Address (LSB)
Data OUT
GPMC_WAIT[j]
GPMC_11
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 7-73. GPMC and Multiplexed NOR Flash — Asynchronous Write — Single Word
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7.10.5.12.3 GPMC and NAND Flash — Asynchronous Mode
Section 7.10.5.12.3.1 and Section 7.10.5.12.3.2 assume testing over the recommended operating conditions
and electrical characteristic conditions below (see Figure 7-74 through Figure 7-77).
7.10.5.12.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
MIN
MAX
NO.
MODE(4)
Access time, input data GPMC_AD[15:0](3) div_by_1_mode;
UNIT
ns
133 MHz(5)
GNF12(1)
tacc(d)
J(2)
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(4) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
GPMC_CLK frequency = GPMC_FCLK frequency
(5) For 133 MHz:
–
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT
7.10.5.12.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
MIN
133 MHz(16)
MAX
NO.
PARAMETER
MODE(15)
UNIT
ns
GNF0 tw(wenV)
Pulse duration, output write enable GPMC_WEn
valid
div_by_1_mode;
A(1)
GNF1 td(csnV-wenV)
GNF2 tw(cleH-wenV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output write enable GPMC_WEn valid
div_by_1_mode;
div_by_1_mode;
B(2)-2.55 B(2)+2.65 ns
C(3)-2.55 C(3)+2.65 ns
Delay time, output lower-byte enable and
command latch enable GPMC_BE0n_CLE high to
output write enable GPMC_WEn valid
GNF3 tw(wenV-dV)
GNF4 tw(wenIV-dIV)
GNF5 tw(wenIV-cleIV)
Delay time, output data GPMC_AD[15:0] valid to
output write enable GPMC_WEn valid
div_by_1_mode;
div_by_1_mode;
div_by_1_mode;
D(4)-2.55 D(4)+2.65 ns
E(5)-2.55 E(5)+2.65 ns
F(6)-2.55 F(6)+2.65 ns
Delay time, output write enable GPMC_WEn
invalid to output data GPMC_AD[15:0] invalid
Delay time, output write enable GPMC_WEn
invalid to output lower-byte enable and command
latch enable GPMC_BE0n_CLE invalid
GNF6 tw(wenIV-CSn[i]V) Delay time, output write enable GPMC_WEn
invalid to output chip select GPMC_CSn[i](13)
invalid
div_by_1_mode;
div_by_1_mode;
div_by_1_mode;
G(7)-2.55 G(7)+2.65 ns
C(3)-2.55 C(3)+2.65 ns
F(6)-2.55 F(6)+2.65 ns
GNF7 tw(aleH-wenV)
Delay time, output address valid and address latch
enable GPMC_ADVn_ALE high to output write
enable GPMC_WEn valid
GNF8 tw(wenIV-aleIV)
Delay time, output write enable GPMC_WEn
invalid to output address valid and address latch
enable GPMC_ADVn_ALE invalid
GNF9 tc(wen)
Cycle time, write
div_by_1_mode;
div_by_1_mode;
H(8) ns
GNF10 td(csnV-oenV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn valid
I(9)-2.55 I(9)+2.65 ns
GNF13 tw(oenV)
GNF14 tc(oen)
Pulse duration, output enable GPMC_OEn_REn
valid
div_by_1_mode;
K(10) ns
Cycle time, read
div_by_1_mode;
div_by_1_mode;
L(11)
ns
ns
GNF15 tw(oenIV-CSn[i]V) Delay time, output enable GPMC_OEn_REn
invalid to output chip select GPMC_CSn[i](13)
invalid
M(12)-2.55
M
(12)+2.65
(1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
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(2) B = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(3) C = ((WEOnTime - ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - ADVExtraDelay)) × GPMC_FCLK(14)
(4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK(14)
(5) E = ((WrCycleTime - WEOffTime) × (TimeParaGranularity + 1) - 0.5 × WEExtraDelay) × GPMC_FCLK(14)
(6) F = ((ADVWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - WEExtraDelay)) × GPMC_FCLK(14)
(7) G = ((CSWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - WEExtraDelay)) × GPMC_FCLK(14)
(8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)
(9) I = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(10) K = (OEOffTime - OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK(14)
(11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)
(12) M = ((CSRdOffTime - OEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - OEExtraDelay)) × GPMC_FCLK(14)
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(15) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
GPMC_CLK frequency = GPMC_FCLK frequency
(16) For 133 MHz:
–
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT
GPMC_FCLK
GNF1
GNF2
GNF6
GNF5
GPMC_CSn[i]
GPMC_BE0n_CLE
GPMC_ADCn_ALE
GPMC_OEn_REn
GPMC_WEn
GNF0
GNF3
GNF4
GPMC_AD[15:0]
Command
GPMC_12
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
Figure 7-74. GPMC and NAND Flash — Command Latch Cycle
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GPMC_FCLK
GPMC_CSn[i]
GNF1
GNF7
GNF6
GNF8
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GPMC_OEn_REn
GPMC_WEn
GNF9
GNF0
GNF3
GNF4
Address
GPMC_AD[15:0]
GPMC_13
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
Figure 7-75. GPMC and NAND Flash — Address Latch Cycle
GPMC_FCLK
GPMC_CSn[i]
GNF12
GNF10
GNF15
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GNF14
GNF13
GPMC_OEn_REn
GPMC_AD[15:0]
GPMC_WAIT[j]
DATA
GPMC_14
A. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional
clock edge. GNF12 value must be stored inside AccessTime register bits field.
B. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
C. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.
Figure 7-76. GPMC and NAND Flash — Data Read Cycle
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GPMC_FCLK
GNF1
GNF6
GPMC_CSn[i]
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GPMC_OEn_REn
GNF9
GNF0
GPMC_WEn
GNF3
GNF4
GPMC_AD[15:0]
DATA
GPMC_15
A. `In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
Figure 7-77. GPMC and NAND Flash — Data Write Cycle
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in
the device TRM.
7.10.5.12.4 GPMC0 IOSET
Table 7-49 present the specific groupings of signals (IOSET) for use with GPMC0.
Table 7-49. GPMC0 IOSET
Signals
IOSET1
IOSET2
BALL NAME
MUX
8
BALL NAME
MDIO0_MDC
RGMII6_RD1
MUX
8
GPMC0_WAIT2
GPMC0_BE1n
GPMC0_WAIT0
GPMC0_WAIT1
GPMC0_DIR
MDIO0_MDC
PRG1_PRU0_GPO0
PRG1_PRU0_GPO1
PRG1_PRU0_GPO2
PRG1_PRU0_GPO3
PRG1_PRU0_GPO4
PRG1_PRU0_GPO5
PRG1_PRU0_GPO6
PRG1_PRU0_GPO8
PRG1_PRU0_GPO9
PRG1_PRU0_GPO10
PRG1_PRU1_GPO5
PRG1_PRU1_GPO8
PRG1_PRU1_GPO9
PRG1_PRU1_GPO10
PRG0_PRU0_GPO5
PRG0_PRU0_GPO7
PRG0_PRU0_GPO8
PRG0_PRU0_GPO9
PRG0_PRU0_GPO10
PRG0_PRU0_GPO17
8
8
8
PRG1_PRU0_GPO1
PRG1_PRU0_GPO2
PRG1_PRU0_GPO3
PRG1_PRU0_GPO4
PRG1_PRU0_GPO5
PRG1_PRU0_GPO6
PRG1_PRU0_GPO8
PRG1_PRU0_GPO9
PRG1_PRU0_GPO10
PRG1_PRU1_GPO5
PRG1_PRU1_GPO8
PRG1_PRU1_GPO9
PRG1_PRU1_GPO10
PRG0_PRU0_GPO5
PRG0_PRU0_GPO7
PRG0_PRU0_GPO8
PRG0_PRU0_GPO9
PRG0_PRU0_GPO10
PRG0_PRU0_GPO17
8
8
8
8
8
GPMC0_CSn2
GPMC0_WEn
8
8
8
8
GPMC0_CSn3
GPMC0_OEn_REn
GPMC0_ADVn_ALE
GPMC0_BE0n_CLE
GPMC0_WPn
8
8
8
8
8
8
8
8
8
8
GPMC0_CSn1
GPMC0_CSn0
GPMC0_CLKOUT
GPMC0_AD0
8
8
8
8
8
8
8
8
GPMC0_AD1
8
8
GPMC0_AD2
8
8
GPMC0_AD3
8
8
GPMC0_AD4
8
8
GPMC0_AD5
8
8
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Table 7-49. GPMC0 IOSET (continued)
Signals
IOSET1
IOSET2
BALL NAME
MUX
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
BALL NAME
MUX
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
GPMC0_AD6
GPMC0_AD7
GPMC0_AD8
GPMC0_AD9
GPMC0_AD10
GPMC0_AD11
GPMC0_AD12
GPMC0_AD13
GPMC0_AD14
GPMC0_AD15
GPMC0_A0
PRG0_PRU0_GPO18
PRG0_PRU0_GPO19
PRG0_PRU1_GPO5
PRG0_PRU1_GPO7
PRG0_PRU1_GPO8
PRG0_PRU1_GPO9
PRG0_PRU1_GPO10
PRG0_PRU1_GPO17
PRG0_PRU1_GPO18
PRG0_PRU1_GPO19
PRG0_MDIO0_MDC
RGMII5_TX_CTL
RGMII5_RX_CTL
RGMII5_TD3
PRG0_PRU0_GPO18
PRG0_PRU0_GPO19
PRG0_PRU1_GPO5
PRG0_PRU1_GPO7
PRG0_PRU1_GPO8
PRG0_PRU1_GPO9
PRG0_PRU1_GPO10
PRG0_PRU1_GPO17
PRG0_PRU1_GPO18
PRG0_PRU1_GPO19
PRG0_MDIO0_MDC
RGMII5_TX_CTL
RGMII5_RX_CTL
RGMII5_TD3
GPMC0_A1
GPMC0_A2
GPMC0_A3
GPMC0_A4
RGMII5_TD2
RGMII5_TD2
GPMC0_A5
RGMII5_TD1
RGMII5_TD1
GPMC0_A6
RGMII5_TD0
RGMII5_TD0
GPMC0_A7
RGMII5_TXC
RGMII5_TXC
GPMC0_A8
RGMII5_RXC
RGMII5_RXC
GPMC0_A9
RGMII5_RD3
RGMII5_RD3
GPMC0_A10
GPMC0_A11
GPMC0_A12
GPMC0_A13
GPMC0_A14
GPMC0_A15
GPMC0_A16
GPMC0_A17
GPMC0_A18
GPMC0_A19
GPMC0_A20
GPMC0_A21
GPMC0_A22
GPMC0_A23
GPMC0_A24
GPMC0_A25
GPMC0_A26
GPMC0_A27
GPMC0_WAIT3
RGMII5_RD2
RGMII5_RD2
RGMII5_RD1
RGMII5_RD1
RGMII5_RD0
RGMII5_RD0
RGMII6_TX_CTL
RGMII6_RX_CTL
RGMII6_TD3
RGMII6_TX_CTL
RGMII6_RX_CTL
RGMII6_TD3
RGMII6_TD2
RGMII6_TD2
RGMII6_TD1
RGMII6_TD1
RGMII6_TD0
RGMII6_TD0
RGMII6_TXC
RGMII6_TXC
RGMII6_RXC
RGMII6_RXC
RGMII6_RD3
RGMII6_RD3
RGMII6_RD2
RGMII6_RD2
PRG0_PRU1_GPO2
PRG0_PRU1_GPO4
PRG0_PRU1_GPO6
PRG0_PRU1_GPO11
PRG0_MDIO0_MDIO
MDIO0_MDIO
PRG0_PRU1_GPO2
PRG0_PRU1_GPO4
PRG0_PRU1_GPO6
PRG0_PRU1_GPO11
PRG0_MDIO0_MDIO
MDIO0_MDIO
7.10.5.13 HyperBus
For more details about features and additional description information on the device HyperBus, see the
corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
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Section 7.10.5.13.1, Section 7.10.5.13.2, and Section 7.10.5.13.3 assume testing over the recommended
operating conditions and electrical characteristic conditions (see Figure 7-78, Figure 7-79, and Figure 7-80).
Table 7-50 represents HyperBus timing conditions.
Table 7-50. HyperBus Timing Conditions
PARAMETER
DESCRIPTION
MIN
2
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
1.5
10
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch
Propagation delay mismatch between CK and CKn;
ps
ps
10
traces
RWDS and DQ[7:0]
Delay)
CK/CKn and RWDS;
CK/CKn and CSn
200
CK/CKn and DQ[7:0]
RESETn and CSn[1:0]
35
ps
ps
340
7.10.5.13.1 Timing Requirements for HyperBus
NO.
D1
PARAMETER
tw(resetnL)
DESCRIPTION
MODE
MIN
MAX
UNIT
Pulse duration, HYPERBUS0_RESETn low
200
ns
ns
D2
tw(csnL)
Pulse duration, HYPERBUS0_CSn[1:0] low
1000
td(resetnH-csnL)
Delay time, HYPERBUS0_RESETn rising edge to
HYPERBUS0_CSn[1:0] falling edge
D3
D4
200.34
ns
td(csnL-rwdsL)
Delay time, HYPERBUS0_CSn[1:0] falling edge to
HYPERBUS0_RWDS falling edge
166 MHz
100 MHz
166 MHz
100 MHz
186
182
ns
ns
ns
ns
D5
tskn(rwdsV-dV)
Input skew, HYPERBUS0_RWDS transition to
HYPERBUS0_DQ[7:0] valid
-0.46
-0.81
0.46
0.81
LFD5
7.10.5.13.2 HyperBus 166 MHz Switching Characteristics
NO.
D6
D7
D8
D9
PARAMETER
tc(ck/ckn)
DESCRIPTION
Cycle time, HYPERBUS0_CK/CKn
Pulse duration, HYPERBUS0_CK/CKn high or low
MIN
6
MAX
UNIT
ns
tw(ck/ckn)
2.85
6
ns
tw(csnH)
Pulse duration, HYPERBUS0_CSn[1:0] invalid between operations
ns
td(csnL-ckH/cknL)
Delay time, HYPERBUS0_CSn[1:0] falling edge to first
HYPERBUS0_CK rising (HYPERBUS0_CKn falling) edge
-3.28
ns
D10
D11
D12
td(ckL/cknH-csnH)
td(ckV/cknV-rwdsV)
td(ckV-dV)
Delay time, last falling HYPERBUS0_CK (rising HYPERBUS0_Ckn)
edge to HYPERBUS0_CSn[1:0] rising
0.28
0.68
0.71
ns
ns
ns
Delay time, HYPERBUS0_CK/CKn transition to
HYPERBUS0_RWDS valid
2.14
2.3
Delay time, HYPERBUS0_CK/CKn transition to
HYPERBUS0_DQ[7:0] valid
7.10.5.13.3 HyperBus 100 MHz Switching Characteristics
NO.
PARAMETER
tc(ck/ckn)
DESCRIPTION
Cycle time, HYPERBUS0_CK/CKn
MIN
10
MAX
UNIT
ns
LFD6
LFD7
LFD8
LFD9
tw(ck/ckn)
Pulse duration, HYPERBUS0_CK/CKn high or low
4.88
10
ns
tw(csnH)
Pulse duration, HYPERBUS0_CSn[1:0] invalid between operations
ns
td(csnL-ckH/cknL)
Delay time, HYPERBUS0_CSn[1:0] falling edge to first
HYPERBUS0_CK rising (HYPERBUS0_CKn falling) edge
-3.33
ns
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NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
LFD10 td(ckL/cknH-csnH)
LFD11 td(ckV/cknV-rwdsV)
LFD12 td(ckV/cknV-dV)
Delay time, last falling HYPERBUS0_CK (rising HYPERBUS0_Ckn)
edge to HYPERBUS0_CSn[1:0] rising
0.33
ns
Delay time, HYPERBUS0_CK/CKn transition to
HYPERBUS0_RWDS valid
1.13
1.16
3.68
3.84
ns
ns
Delay time, HYPERBUS0_CK/CKn transition to
HYPERBUS0_DQ[7:0] valid
D8/LFD8
D2
CSn
D9/LFD9
D10/LFD10
CK, CKn
D7/LFD7
D6/LFD6
D4
D11/LFD11
RWDS
D12/LFD12
Dn Dn+1 Dn+1
D12/LFD12
Dn
A
39:32 31:24 23:16
7:0
47:40
15:8
DQ[7:0]
B
A
B
CK and Data are center aligned
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Host drives DQ[7:0] and RWDS
HYPERBUS_TIMING_01
Figure 7-78. HyperBus Timing Diagrams – Transmitter Mode
D8/LFD8
D2
CSn
D9/LFD9
D10/LFD10
CK, CKn
D7/LFD7
D4
D6/LFD6
RWDS
D5/LFD5
D12/LFD12
D5/LFD5
Dn+1 Dn+1
Dn
A
Dn
B
39:32 31:24 23:16
7:0
47:40
15:8
DQ[7:0]
A
B
CK and Data are center aligned
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Host drives DQ[7:0] and RWDS
HYPERBUS_TIMING_02
Figure 7-79. HyperBus Timing Diagrams – Receiver Mode
D1
RESETn
D3
CSn
HYPERBUS_TIMING_03
Figure 7-80. HyperBus Timing Diagrams – Reset
For more information, see HyperBus Interface section in Peripherals chapter in the device TRM.
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7.10.5.14 I2C
The Inter-IC module is compliant with the Philips I2C Bus Specification, revision 2.1. Refer to the specification for
timing details for all but rise/fall time parameters.
Philips I2C specification rise/fall timings apply only to MCU_I2C0, WKUP_I2C0, and I2C[0-1]. All other instances
of I2C use standard LVCMOS buffers to emulate open-drain buffers, and their rise/fall times should be
referenced using the device IBIS model.
For more details about features and additional description information on the device Inter-Integrated Circuit, see
the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
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7.10.5.15 I3C
For more details about features and additional description information on the device Inter-Integrated Circuit, see
the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
Table 7-51, Table 7-52 , Table 7-53, Figure 7-81, Table 7-55, Figure 7-82, and Figure 7-83 assume testing over
the recommended operating conditions and electrical characteristic conditions.
Table 7-51. I3C Timing Conditions
PARAMETER
INPUT CONDITIONS
SRI Input slew rate
OUTPUT CONDITIONS
CL Output load capacitance
MIN
MAX UNIT
0.2276
5
V/ns
50 pF
Table 7-52. I3C Open Drain Timing Requirements
see Figure 7-81
NO.
MODE
MIN
MAX UNIT
OD4
tsu(sdaV-sclH)
Setup time, SDA valid before SCL rising edge
Master
3
ns
Table 7-53. I3C Open Drain Switching Characteristics
see Figure 7-81
NO.
PARAMETER
MODE
MIN
MAX UNIT
tw(sclL_od)
tw(sclL_od_dig)
200
ns
OD1
Pulse duration, SCL low
Master
tw(sclL_od)
+
ns
tf(sda_od), min
tw(sclH_od)
tw(sclH_od_dig)
tf(sda_od)
41 ns
OD2
OD3
Pulse duration, SCL high
Fall time, SDA
Master
tw(sclH_od)
+
ns
tf(scl)
Master
tf(scl)
38.4
12 ns
1000 ns
Master, ENTAS0
Master, ENTAS1
Master, ENTAS2
Master, ENTAS3
Master
38.4
100000 ns
2000000 ns
50000000 ns
ns
OD5
td(sclL-START)
Delay time, SCL low after START (S) condition
38.4
38.4
OD6
OD7
td(sclH-STOP)
tw(mmoverlap)
Delay time, SCL high before STOP (P) condition
td(sclV), min / 2
Pulse duration, current master to secondary master
overlap time during handoff
Master
tw(sclL_od_dig)
ns
OD8
OD9
tw(aval)
tw(idle)
Pulse duration, Bus Available condition
Pulse duration, Bus Idle condition
Master
Master
Master
1000
1000000
tw(aval)
ns
ns
ns
OD10 tw(mmlock)
Pulse duration, new master not driving SDA low
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OD3
OD4
OD6
0.7xVDD
SDA
0.3xVDD
OD5
OD2
OD1
0.7xVDD
0.3xVDD
SCL
Stop
Start
Repeated
Start
Stop
- Open drain with weak pull-up
- Open drain with weak pull-up
Figure 7-81. I3C Open Drain Timing Requirements
Table 7-54. I3C Push-Pull Timing Requirements - SDR and HDR-DDR Modes
Figure 7-82 and Figure 7-83
NO.
MODE
Master
Seutp time, SDA valid before SCL transition Master
MIN
tr(scl) + 3 and tf(scl) + 3
3
MAX UNIT
D8
D9
th(sclV-sdaV)
tsu(sdaV-sclV)
Hold time, SDA valid after SCL transition
ns
ns
Table 7-55. I3C Push-Pull Switching Characteristics - SDR and HDR-DDR Modes
see Figure 7-83, Figure 7-82
NO.
PARAMETER
Cycle time, SCL
MODE
Master
MIN
MAX UNIT
D1
tc(scl)
80
100000
ns
ns
ns
ns
ns
ns
ns
ns
tw(sclL)
tw(sclL_dig)
tw(sclH)
tw(sclH_dig)
tr(scl)
24
32
D2
Pulse duration, SCL low
Pulse duration, SCL high
Master
Master
24
D4
32
D6
D7
Rise time, SCL
Fall time, SCL
Master
Master
150 × 1 / tc(scl)
150 × 1 / tc(scl)
td(sclV-START), min
60
60
tf(scl)
D10
td(Sr-sclV)
Delay time, SCL valid after Repeated START (Sr) Master
Delay time, Repeated START (Sr) after SCL valid Master
td(sclV-START),
min / 2
D11
td(sclV-Sr)
ns
0.7xVDD
0.3xVDD
SDA
D11
D10
D1
D2
DD8
D9
D8
D9
0.7xVDD
0.3xVDD
SCL
D4
Stop
Start
Repeated
Start
Stop
Figure 7-82. I3C Push-Pull Timing Requirements - HDR-DDR Mode
0.7xVDD
0.3xVDD
SDA
D11
D10
D1
D2
D8
D9
0.7xVDD
0.3xVDD
SCL
D4
Stop
Start
Repeated
Start
Stop
Figure 7-83. I3C Push-Pull Timing Requirements - SDR Mode
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7.10.5.16 MCAN
For more details about features and additional description information on the device Controller Area Network
Interface, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed
Description.
Note
The device has multiple MCAN modules. MCANn is a generic prefix applied to MCAN signal names,
where n represents the specific MCAN module.
Table 7-56. MCAN Timing Conditions
PARAMETER
MIN
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
2
15
OUTPUT CONDITIONS
CL
Output load capacitance
5
20
Table 7-57. MCAN Switching Characteristics
NO.
PARAMETER
MIN
MAX
10
UNIT
M1
M2
td(MCAN_TX)
td(MCAN_RX)
Delay time, transmit shift register to MCANn_TX pin(1)
Delay time, MCANn_RX pin to receive shift register(1)
ns
ns
10
(1) n is [0:13] in MCANn_* or [0:1] in MCU_MCANn_*
For more information, see Controller Area Network (MCAN) section in Peripherals chapter in the device TRM.
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7.10.5.17 MCASP
For more details about features and additional description information on the device Multichannel Audio Serial
Port, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
Table 7-59 and Figure 7-84 present timing requirements for MCASP0 to MCASP11.
Table 7-58 represents MCASP timing conditions.
Table 7-58. MCASP Timing Conditions
PARAMETER
MIN
0.7
1
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
10
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay)
Propagation delay of each trace
100
1100
100
ps
ps
td(Trace Mismatch Delay)
Propagation delay mismatch across all traces
Table 7-59. MCASP Timing Requirements
NO.
MODE(1)
MIN
15.26
0.5P(2)
MAX UNIT
ASP1 tc(AHCLKRX)
Cycle time, MCASP[x]_AHCLKR/X
ns
ns
-
ASP2 tw(AHCLKRX)
ASP3 tc(ACLKRX)
ASP4 tw(ACLKRX)
Pulse duration, MCASP[x]_AHCLKR/X high or low
Cycle time, MCASP[x]_ACLKR/X
1.53
15.26
ns
ns
0.5R(3)
-
Pulse duration, MCASP[x]_ACLKR/X high or low
1.53
12.3
4
ACLKR/X int
ns
ns
ns
ns
Setup time, MCASP[x]_AFSR/X input valid before
MCASP[x]_ACLKR/X
ASP5 tsu(AFSRX-ACLKRX)
ASP6 th(ACLKRX-AFSRX)
ASP7 tsu(AXR-ACLKRX)
ASP8 th(ACLKRX-AXR)
ACLKR/X ext in/out
ACLKR/X int
-1
Hold time, MCASP[x]_AFSR/X input valid after
MCASP[x]_ACLKR/X
ACLKR/X ext in/out
ACLKR/X int
1.6
12.3
4
Setup time, MCASP[x]_AXR input valid before
MCASP[x]_ACLKR/X
ACLKR/X ext in/out
ACLKR/X int
-1
Hold time, MCASP[x]_AXR input valid after
MCASP[x]_ACLKR/X
ACLKR/X ext in/out
1.6
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
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ASP2
ASP2
ASP1
MCASP[x]_ACLKR/X (Falling Edge Polarity)
MCASP[x]_AHCLKR/X (Rising Edge Polarity)
ASP4
ASP4
ASP3
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(A)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(B)
ASP6
ASP5
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)
ASP8
ASP7
MCASP[x]_AXR[x] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured
for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured
for rising edge (to shift data in).
Figure 7-84. MCASP Input Timing
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Table 7-60 and Figure 7-85 present switching characteristics over recommended operating conditions for
MCASP0 to MCASP11.
Table 7-60. MCASP Switching Characteristics
NO.
PARAMETER
DESCRIPTION
MODE(1)
MIN
MAX UNIT
ASP9 tc(AHCLKRX)
ASP10 tw(AHCLKRX)
ASP11 tc(ACLKRX)
ASP12 tw(ACLKRX)
Cycle time, MCASP[x]_AHCLKR/X
20
ns
ns
ns
ns
Pulse duration, MCASP[x]_AHCLKR/X high or low
Cycle time, MCASP[x]_ACLKR/X
0.5P(2) - 2
20
Pulse duration, MCASP[x]_ACLKR/X high or low
0.5R(3) - 2
ASP13 td(ACLKRX-AFSRX) Delay time, MCASP[x]_ACLKR/X transmit edge to
MCASP[x]_AFSR/X output valid
ACLKR/X int
0
-15.28
0
7.25
12.84
7.25
12.84
7.25
14
ns
ns
ns
ACLKR/X ext in/out
ACLKR/X int
ASP14 td(ACLKX-AXR)
Delay time, MCASP[x]_ACLKX transmit edge to
MCASP[x]_AXR output valid
ACLKR/X ext in/out
ACLKR/X int
-15.28
0
ASP15 tdis(ACLKX-AXR)
Disable time, MCASP[x]_ACLKX transmit edge to
MCASP[x]_AXR output high impedance
ACLKR/X ext in/out
-14.9
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
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ASP10
ASP10
ASP9
MCASP[x]_ACLKR/X (Falling Edge Polarity)
MCASP[x]_AHCLKR/X (Rising Edge Polarity)
ASP12
ASP12
ASP11
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(A)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(B)
ASP13
ASP13
ASP13
ASP13
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)
ASP13
ASP13
ASP13
MCASP[x]_AXR[x] (Data Out/Transmit)
ASP14
ASP15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured
for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured
for falling edge (to shift data in).
Figure 7-85. MCASP Output Timing
For more information, see Multichannel Audio Serial Port (MCASP) section in Peripherals chapter in the device
TRM.
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7.10.5.18 MCSPI
For more details about features and additional description information on the device Serial Port Interface, see
the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the
device TRM.
Table 7-61 represents MCSPI timing conditions.
Note
The IO timings provided in this section are applicable for all combinations of signals for MCU_SPI0
and MCU_SPI1. However, the timings are only valid for MCU_SPI0 and MCU_SPI1 if signals within a
single IOSET are used. The IOSETs are defined in the Table 7-66 and Table 7-67 tables.
Table 7-61. MCSPI Timing Conditions
PARAMETER
MIN
MAX
UNIT
INPUT CONDITIONS
SRI
Input slew rate
2
8.5 V/ns
OUTPUT CONDITIONS
CLK
6
6
24
12
pF
pF
CL
Output load capacitance
D[x], CSi
7.10.5.18.1 MCSPI — Master Mode
Table 7-62, Figure 7-86, Table 7-63, and Figure 7-87 present timing requirements and switching characteristics
for MCSPI – Master Mode.
Table 7-62. MCSPI Timing Requirements - Master Mode
see Figure 7-86
NO.
MIN
MAX
UNIT
tsu(misoV-
SM4
Setup time, SPI_D[x] valid before SPI_CLK active edge
Hold time, SPI_D[x] valid after SPI_CLK active edge
2.8
ns
spiclkV)
th(spiclkV-
SM5
3
ns
misoV)
Table 7-63. MCSPI Switching Characteristics - Master Mode
see Figure 7-87
NO.
PARAMETER
Cycle time, SPI_CLK
MODE
MIN
MAX UNIT
SM1 tc(spiclk)
SM2 tw(spiclkL)
20.8
ns
0.5P -
1(1)
Pulse duration, SPI_CLK low
Pulse duration, SPI_CLK high
ns
ns
0.5P -
1(1)
SM3 tw(spiclkH)
Delay time, SPI_CLK active edge to SPI_D[x]
transition
SM6 td(spiclkV-simoV)
SM7 td(csV-simoV)
SM8 td(csV-spiclk)
-3
2.5
ns
Delay time, SPI_CSi active edge to SPI_D[x] transition
5
B - 4(3)
A - 4(4)
A - 4(4)
B - 4(3)
ns
ns
ns
ns
ns
PHA = 0(2)
PHA = 1 (2)
PHA = 0(2)
PHA = 1(2)
Delay time, SPI_CSi active to SPI_CLK first edge
SM9 td(spiclkV-csV)
Delay time, SPI_CLK last edge to SPI_CSi inactive
(1) P = SPI_CLK period in ns
(2) SPI_CLK phase is programmable with the PHA bit of the MCSPI_CHCONF_0/1/2/3 register
(3) B = (TCS + .5) * TSPICLKREF, where TCSns a bit field of the MCSPI_CHCONF_0/1/2/3 register and Fratio = Even >= 2.
(4) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCSns a bit field of the MCSPI_CHCONF_0/1/2/3 register.
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When P > 20.8 ns, A = (TCS + 0.5) * Fratio * TSPICLKREF, where TCSns a bit field of the MCSPI_CHCONF_0/1/2/3 register.
PHA=0
EPOL=1
SPI_CS[i] (OUT)
SM1
SM3
SM8
SM2
SM9
POL=0
POL=1
SPI_SCLK (OUT)
SM1
SM3
SM2
SPI_SCLK (OUT)
SM5
SM5
SM4
SM4
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
SPI_D[x] (IN)
PHA=1
EPOL=1
SPI_CS[i] (OUT)
SPI_SCLK (OUT)
SM2
SM1
SM8
SM3
SM2
SM9
POL=0
POL=1
SM1
SM3
SPI_SCLK (OUT)
SM5
SM4
SM5
SM4
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
SPI_D[x] (IN)
SPRSP08_TIMING_McSPI_02
Figure 7-86. SPI Master Mode Receive Timing
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PHA=0
EPOL=1
SPI_CS[i] (OUT)
SM1
SM3
SM8
SM2
SM9
POL=0
POL=1
SPI_SCLK (OUT)
SM1
SM3
SM2
SPI_SCLK (OUT)
SPI_D[x] (OUT)
SM7
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[i] (OUT)
SPI_SCLK (OUT)
SM1
SM2
SM8
SM3
SM2
SM9
POL=0
POL=1
SM1
SM3
SPI_SCLK (OUT)
SPI_D[x] (OUT)
SM6
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
SM6
Bit 1
Bit0
SPRSP08_TIMING_McSPI_01
Figure 7-87. MCSPI Master Mode Transmit Timing
7.10.5.18.2 MCSPI — Slave Mode
Table 7-64, Table 7-65, Figure 7-88, and Figure 7-89 present timing requirements and switching characteristics
for MCSPI – Slave Mode.
Table 7-64. MCSPI Timing Requirements - Slave Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
SS1 tc(spiclk)
Cycle time, SPI_CLK
20.8
0.45P(1)
0.45P(1)
ns
ns
ns
ns
ns
ns
ns
SS2 tw(spiclkL)
Pulse duration, SPI_CLK low
SS3 tw(spiclkH)
Pulse duration, SPI_CLK high
SS4 tsu(simoV-spiclkV)
SS5 th(spiclkV-simoV)
SS8 tsu(csV-spiclkV)
SS9 th(spiclkV-csV)
Setup time, SPI_D[x] valid before SPI_CLK active edge
Hold time, SPI_D[x] valid after SPI_CLK active edge
Setup time, SPI_CSi valid before SPI_CLK first edge
Hold time, SPI_CSi valid after SPI_CLK last edge
5
5
5
5
Table 7-65. MCSPI Switching Characteristics - Slave Mode
NO.
SS6
PARAMET DESCRIPTION
ER
MIN
MAX
UNIT
td(spiclkV-
Delay time, SPI_CLK active edge to SPI_D[x] transition
2
17.12
ns
somiV)
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Table 7-65. MCSPI Switching Characteristics - Slave Mode (continued)
NO.
PARAMET DESCRIPTION
ER
MIN
MAX
UNIT
SS7
tsk(csV-somiV) Delay time, SPI_CSi active edge to SPI_D[x] transition
20.95
ns
(1) P = SPI_CLK period in ns.
PHA=0
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
SPI_SCLK (IN)
SS1
SS2
POL=1
SPI_SCLK (IN)
SS5
SS4
SS5
Bit n-2
SS4
Bit n-1
Bit n-3
Bit n-4
Bit 0
SPI_D[x] (IN)
PHA=1
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
SPI_SCLK (IN)
SS1
SS3
POL=1
SPI_SCLK (IN)
SS4
SS5
SS4
SS5
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
SPI_D[x] (IN)
SPRSP08_TIMING_McSPI_04
Figure 7-88. SPI Slave Mode Receive Timing
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PHA=0
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
POL=1
SPI_SCLK (IN)
SS1
SS2
SPI_SCLK (IN)
SPI_D[x] (OUT)
SS7
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[i] (IN)
SPI_SCLK (IN)
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
POL=1
SS1
SS3
SPI_SCLK (IN)
SPI_D[x] (OUT)
SS6
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
SS6
Bit 1
Bit 0
SPRSP08_TIMING_McSPI_03
Figure 7-89. MCSPI Slave Mode Transmit Timing
Table 7-66 and Table 7-67 present the specific groupings of signals (IOSET) for use with MCU_SPI0 and
MCU_SPI1.
Table 7-66. MCU_SPI0 IOSETs
Signals
IOSET1
IOSET2
BALL NAME
BALL NAME
MUX
MUX
MCU_SPI0_CLK
MCU_SPI0_D0
MCU_SPI0_D1
MCU_SPI0_CS0
MCU_SPI0_CS1
MCU_SPI0_CS2
MCU_SPI0_CLK
MCU_SPI0_D0
0
0
0
0
5
5
MCU_SPI0_CLK
MCU_SPI0_D0
0
0
0
0
1
1
MCU_SPI0_D1
MCU_SPI0_D1
MCU_SPI0_CS0
MCU_OSPI1_D3
MCU_OSPI1_CSn1
MCU_SPI0_CS0
WKUP_GPIO0_12
WKUP_GPIO0_14
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Table 7-67. MCU_SPI1 IOSET
Signals
IOSET1
IOSET2
BALL NAME
MUX
BALL NAME
MCU_SPI1_CLK
MCU_SPI1_D0
MCU_SPI1_D1
MCU_SPI1_CS0
WKUP_GPIO0_13
WKUP_GPIO0_15
MUX
MCU_SPI1_CLK
MCU_SPI1_D0
MCU_SPI1_D1
MCU_SPI1_CS0
MCU_SPI1_CS1
MCU_SPI1_CS2
MCU_SPI1_CLK
MCU_SPI1_D0
MCU_SPI1_D1
MCU_SPI1_CS0
MCU_OSPI1_D1
MCU_OSPI1_D2
0
0
0
0
5
5
0
0
0
0
1
1
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the
device TRM.
7.10.5.19 MMCSD
The MMCSD Host Controller provides an interface to embedded Multi-Media Card (MMC), Secure Digital (SD),
and Secure Digital IO (SDIO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO protocol at
transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking
for syntactical correctness.
For more details about MMCSD interfaces, see the corresponding MMC0, MMC1, and MMC2 sections within
Section 6.3, Signal Descriptions and Section 8, Detailed Description.
Note
Some operating modes require software configuration of the MMC DLL delay settings, as shown in
Table 7-68 and Table 7-77.
For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in
the device TRM.
7.10.5.19.1 MMC0 - eMMC Interface
MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and it supports the
following eMMC applications:
•
•
•
•
Legacy speed
High speed SDR
High speed DDR
HS200
Table 7-68 presents the required DLL software configuration settings for MMC0 timing modes.
Table 7-68. MMC0 DLL Delay Mapping for All Timing Modes
REGISTER NAME
BIT FIELD
MMCSD0_SS_PHY_CTRL_4_REG
MMCSD0_SS_PHY_CTRL_5_REG
[31:24]
[20]
[15:12]
[8]
[4:0]
[17:16]
[10:8]
[2:0]
SELDLYTXCLK
SELDLYRXCLK
BIT FIELD NAME
STRBSEL
OTAPDLYENA
OTAPDLYSEL
ITAPDLYENA
ITAPDLYSEL
FRQSEL
CLKBUFSEL
OUTPUT
DELAY
ENABLE
OUTPUT
DELAY
VALUE
INPUT
DELAY
ENABLE
INPUT
DELAY
VALUE
DLL/
DELAY CHAIN
SELECT
DELAY
BUFFER
DURATION
STROBE
DELAY
DLL REF
FREQUENCY
MODE DESCRIPTION
8-bit PHY
Legacy
operating 1.8 V,
SDR
0x0
0x0
0x0
0x0
0x0
0x1
NA
NA
0x5
0x1
0x1
0x1
0x10
0xA
0x3
0x1
0x1
0x0
0x0
0x0
0x4
0x7
0x7
0x7
25 MHz
High
8-bit PHY
Speed operating 1.8 V,
SDR
High
50 MHz
8-bit PHY
Speed operating 1.8 V,
DDR 50 MHz
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Table 7-68. MMC0 DLL Delay Mapping for All Timing Modes (continued)
REGISTER NAME
MMCSD0_SS_PHY_CTRL_4_REG
MMCSD0_SS_PHY_CTRL_5_REG
BIT FIELD
[31:24]
[20]
[15:12]
[8]
[4:0]
[17:16]
[10:8]
[2:0]
SELDLYTXCLK
SELDLYRXCLK
BIT FIELD NAME
STRBSEL
OTAPDLYENA
OTAPDLYSEL
ITAPDLYENA
ITAPDLYSEL
FRQSEL
CLKBUFSEL
OUTPUT
DELAY
ENABLE
OUTPUT
DELAY
VALUE
INPUT
DELAY
ENABLE
INPUT
DELAY
VALUE
DLL/
DELAY CHAIN
SELECT
DELAY
BUFFER
DURATION
STROBE
DELAY
DLL REF
FREQUENCY
MODE DESCRIPTION
8-bit PHY
HS200 operating 1.8 V,
200 MHz
0x0
0x1
0x6
0x1
Tuning
0x0
0x0
0x7
Table 7-69 presents timing conditions for MMC0.
Table 7-69. MMC0 Timing Conditions
PARAMETER
MIN
MAX UNIT
INPUT CONDITIONS
Legacy SDR
0.14
0.3
1.44 V/ns
0.9 V/ns
0.9 V/ns
0.9 V/ns
High Speed SDR
SRI
Input slew rate
High Speed DDR (CMD)
High Speed DDR (DAT[7:0])
0.3
0.45
OUTPUT CONDITIONS
HS200
1
1
6
pF
pF
CL
Output load capacitance
All other modes
12
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay)
Propagation delay of each trace
All modes
126
756
100
8
ps
ps
ps
Legacy SDR, High Speed SDR,
High Speed DDR
td(Trace Mismatch
Propagation delay mismatch across all
traces
Delay)
HS200
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7.10.5.19.1.1 Legacy SDR Mode
Table 7-70, Figure 7-90, Table 7-71, and Figure 7-91 present timing requirements and switching characteristics
for MMC0 – Legacy SDR Mode.
Table 7-70. MMC0 Timing Requirements – Legacy SDR Mode
see Figure 7-90
NO.
MIN
9.69
9.65
9.69
9.65
MAX
UNIT
ns
LSDR1 tsu(cmdV-clkH)
LSDR2 th(clkH-cmdV)
LSDR3 tsu(dV-clkH)
LSDR4 th(clkH-dV)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge
ns
ns
ns
Figure 7-90. MMC0 – Legacy SDR – Receive Mode
Table 7-71. MMC0 Switching Characteristics – Legacy SDR Mode
see Figure 7-91
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
25
LSDR5
LSDR6
LSDR7
LSDR8
LSDR9
tc(clk)
Cycle time, MMC0_CLK
40
18.7
tw(clkH)
Pulse duration, MMC0_CLK high
ns
tw(clkL)
Pulse duration, MMC0_CLK low
18.7
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMC0_CLK falling edge to MMC0_CMD transition
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition
-2.74
-2.74
5.07
5.07
ns
ns
Figure 7-91. MMC0 – Legacy SDR – Transmit Mode
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7.10.5.19.1.2 High Speed SDR Mode
Table 7-72, Figure 7-92, Table 7-73, and Figure 7-93 present timing requirements and switching characteristics
for MMC0 – High Speed SDR Mode.
Table 7-72. MMC0 Timing Requirements – High Speed SDR Mode
see Figure 7-92
NO.
MIN
2.99
2.67
2.99
2.67
MAX
UNIT
ns
HSSDR1 tsu(cmdV-clkH)
HSSDR2 th(clkH-cmdV)
HSSDR3 tsu(dV-clkH)
HSSDR4 th(clkH-dV)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge
ns
ns
ns
Figure 7-92. MMC0 – High Speed SDR Mode – Receive Mode
Table 7-73. MMC0 Switching Characteristics – High Speed SDR Mode
see Figure 7-93
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
50
HSSDR5 tc(clk)
Cycle time, MMC0_CLK
20
9.2
HSSDR6 tw(clkH)
HSSDR7 tw(clkL)
HSSDR8 td(clkL-cmdV)
HSSDR9 td(clkL-dV)
Pulse duration, MMC0_CLK high
ns
Pulse duration, MMC0_CLK low
9.2
ns
Delay time, MMC0_CLK falling edge to MMC0_CMD transition
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition
-0.84
-0.84
3.65
3.65
ns
ns
Figure 7-93. MMC0 – High Speed SDR Mode – Transmit Mode
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7.10.5.19.1.3 High Speed DDR Mode
Table 7-74, Figure 7-94, Table 7-75, and Figure 7-95 present timing requirements and switching characteristics
for MMC0 – High Speed DDR Mode.
Table 7-74. MMC0 Timing Requirements – High Speed DDR Mode
see Figure 7-94
NO.
MIN
2
MAX
UNIT
ns
HSDDR1 tsu(cmdV-clkH)
HSDDR2 th(clkH-cmdV)
HSDDR3 tsu(dV-clkV)
HSDDR4 th(clkV-dV)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition
2.5
ns
0.74
1.67
ns
ns
Figure 7-94. MMC0 – High Speed DDR Mode – Receive Mode
Table 7-75. MMC0 Switching Characteristics – High Speed DDR Mode
see Figure 7-95
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
50
HSDDR5 tc(clk)
Cycle time, MMC0_CLK
20
9.2
9.2
3.4
2.9
HSDDR6 tw(clkH)
HSDDR7 tw(clkL)
HSDDR8 td(clkH-cmdV)
HSDDR9 td(clkV-dV)
Pulse duration, MMC0_CLK high
ns
Pulse duration, MMC0_CLK low
ns
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition
9.72
6.6
ns
ns
Figure 7-95. MMC0 – High Speed DDR Mode – Transmit Mode
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7.10.5.19.1.4 HS200 Mode
Table 7-76 and Figure 7-96 present switching characteristics for MMC0 – HS200 Mode.
Table 7-76. MMC0 Switching Characteristics – HS200 Mode
see Figure 7-96
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
200
HS2005
HS2006
HS2007
HS2008
HS2009
tc(clk)
Cycle time, MMC0_CLK
5
2.08
2.08
1.12
1.12
tw(clkH)
Pulse duration, MMC0_CLK high
ns
tw(clkL)
Pulse duration, MMC0_CLK low
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK rising edge to MMC0_DAT[7:0] transition
3.16
3.16
ns
ns
Figure 7-96. MMC0 – HS200 Mode – Transmit Mode
7.10.5.19.2 MMC1/2 - SD/SDIO Interface
MMC1 and MMC2 interfaces are compliant with the SD Host Controller Standard Specification 4.10 and SD
Physical Layer Specification v3.01 as well as SDIO Specification v3.00 and they support the following SD Card
applications:
•
•
•
•
•
•
•
Default speed
High speed
UHS–I SDR12
UHS–I SDR25
UHS–I SDR50
UHS–I SDR104
UHS–I DDR50
Table 7-77 presents the required DLL software configuration settings for MMC1 timing modes.
Table 7-77. MMC1/2 DLL Delay Mapping for All Timing Modes
REGISTER NAME
BIT FIELD
MMCSD12_SS_PHY_CTRL_4_REG
[15:12] [8]
OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL
MMCSD12_SS_PHY_CTRL_5_REG
[20]
[4:0]
[2:0]
BIT FIELD NAME
CLKBUFSEL
INPUT
DELAY
ENABLE
INPUT
DELAY
VALUE
DELAY
BUFFER
DURATION
DELAY
ENABLE
DELAY
VALUE
MODE
DESCRIPTION
Default
Speed
4-bit PHY operating
3.3 V, 25 MHz
0x0
0x0
0x1
0x1
0x0
0x0
0xF
0xF
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x7
0x7
0x7
0x7
High
Speed
4-bit PHY operating
3.3 V, 50 MHz
UHS-I
SDR12
4-bit PHY operating
1.8 V, 25 MHz
UHS-I
SDR25
4-bit PHY operating
1.8 V, 50 MHz
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Table 7-77. MMC1/2 DLL Delay Mapping for All Timing Modes (continued)
REGISTER NAME
MMCSD12_SS_PHY_CTRL_4_REG
[15:12] [8]
OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL
MMCSD12_SS_PHY_CTRL_5_REG
BIT FIELD
[20]
[4:0]
[2:0]
BIT FIELD NAME
CLKBUFSEL
INPUT
DELAY
ENABLE
INPUT
DELAY
VALUE
DELAY
BUFFER
DURATION
DELAY
ENABLE
DELAY
VALUE
MODE
DESCRIPTION
UHS-I
SDR50
4-bit PHY operating
1.8 V, 100 MHz
0x1
0x1
0x1
0xC
0xC
0x5
0x1
0x1
0x1
Tuning
0x2
0x7
0x7
0x7
UHS-I
DR50
4-bit PHY operating
1.8 V, 50 MHz
UHS-I
SDR104
4-bit PHY operating
1.8, V 200 MHz
Tuning
Table 7-78 presents timing conditions for MMC1.
Table 7-78. MMC1/2 Timing Conditions
PARAMETER
MIN
MAX UNIT
INPUT CONDITIONS
Default Speed, High Speed
0.69
0.34
2.06 V/ns
1.34 V/ns
SRI
Input slew rate
UHS–I SDR12, UHS–I SDR25
OUTPUT CONDITIONS
CL
Output load capacitance
All modes
1
10
pF
PCB CONNECTIVITY REQUIREMENTS
UHS–I DDR50
240
126
1134
1386
20
ps
ps
ps
ps
td(Trace Delay)
Propagation delay of each trace
All other modes
UHS–I DDR50, UHS–I SDR104
All other modes
td(Trace Mismatch
Propagation delay mismatch across all
traces
Delay)
100
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7.10.5.19.2.1 Default Speed Mode
Table 7-79, Figure 7-97, Table 7-80, and Figure 7-98 present timing requirements and switching characteristics
for MMC1/2 – Default Speed Mode.
Table 7-79. MMC1/2 Timing Requirements – Default Speed Mode
see Figure 7-97
NO.
DS1
DS2
DS3
DS4
MIN
2.55
4.65
2.55
4.65
MAX
UNIT
ns
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
th(clkH-dV)
Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge
Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge
Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge
Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge
ns
ns
ns
A. x = 1, 2 for MMC1 and MMC2
B. x = 1, 2 for MMC1 and MMC2
MMC[x]_CLK
MMC[x]_CMD
DS2
DS4
DS1
DS3
MMC[x]_DAT[3:0]
Figure 7-97. MMC1/2 – Default Speed – Receive Mode
Table 7-80. MMC1/2 Switching Characteristics – Default Speed Mode
see Figure 7-98
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC[x]_CLK
25
DS5
DS6
DS7
DS8
DS9
tc(clk)
Cycle time, MMC[x]_CLK
40
18.7
tw(clkH)
Pulse duration, MMC[x]_CLK high
ns
tw(clkL)
Pulse duration, MMC[x]_CLK low
18.7
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMC[x]_CLK falling edge to MMC[x]_CMD transition
Delay time, MMC[x]_CLK falling edge to MMC[x]_DAT[3:0] transition
-2.93
-2.93
3.63
3.63
ns
ns
DS5
DS6
DS7
MMC[x]_CLK
MMC[x]_CMD
DS8
DS9
MMC[x]_DAT[3:0]
Figure 7-98. MMC1/2 – Default Speed – Transmit Mode
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7.10.5.19.2.2 High Speed Mode
Table 7-81, Figure 7-99, Table 7-82, and Figure 7-100 present timing requirements and switching characteristics
for MMC1/2 – High Speed Mode.
Table 7-81. MMC1/2 Timing Requirements – High Speed Mode
see Figure 7-99
NO.
HS1
HS2
HS3
HS4
MIN
2.55
2.67
2.55
2.67
MAX
UNIT
ns
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
th(clkH-dV)
Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge
Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge
Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge
Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge
ns
ns
ns
A. x = 1, 2 for MMC1 and MMC2
B. x = 1, 2 for MMC1 and MMC2
MMC[x]_CLK
MMC[x]_CMD
HS1
HS3
HS2
HS4
MMC[x]_DAT[3:0]
Figure 7-99. MMC1 /2– High Speed – Receive Mode
Table 7-82. MMC1/2 Switching Characteristics – High Speed Mode
see Figure 7-100
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC[x]_CLK
Cycle time. MMC[x]_CLK
50
HS5
HS6
HS7
HS8
HS9
tc(clk)
20
9.2
tw(clkH)
Pulse duration, MMC[x]_CLK high
Pulse duration, MMC[x]_CLK low
ns
tw(clkL)
9.2
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMC[x]_CLK falling edge to MMC[x]_CMD transition
-1.77
-1.77
2.35
2.35
ns
Delay time, MMC[x]_CLK falling edge to MMC[x]_DAT[3:0]
transition
ns
HS5
HS6
HS7
MMC[x]_CLK
HS8
HS9
MMC[x]_CMD
MMC[x]_DAT[3:0]
Figure 7-100. MMC1/2 – High Speed – Transmit Mode
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7.10.5.19.2.3 UHS–I SDR12 Mode
Table 7-83, Figure 7-101, Table 7-84, and Figure 7-102 present timing requirements and switching
characteristics for MMC1/2 – UHS-I SDR12 Mode.
Table 7-83. MMC1/2 Timing Requirements – UHS-I SDR12 Mode
see Figure 7-101
NO.
MIN
21.65
1.67
MAX
UNIT
ns
SDR121 tsu(cmdV-clkH)
SDR122 th(clkH-cmdV)
SDR123 tsu(dV-clkH)
SDR124 th(clkH-dV)
Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge
Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge
Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge
Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge
ns
21.65
1.67
ns
ns
A. x = 1, 2 for MMC1 and MMC2
B. x = 1, 2 for MMC1 and MMC2
MMC[x]_CLK
MMC[x]_CMD
SDR122
SDR124
SDR121
SDR123
MMC[x]_DAT[3:0]
Figure 7-101. MMC1/2 – UHS-I SDR12 – Receive Mode
Table 7-84. MMC1/2 Switching Characteristics – UHS-I SDR12 Mode
see Figure 7-102
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
SDR125 tc(clk)
Operating frequency, MMC[x]_CLK
25
Cycle time, MMC[x]_CLK
40
18.7
18.7
1.2
SDR126 tw(clkH)
SDR127 tw(clkL)
SDR128 td(clkH-cmdV)
SDR129 td(clkH-dV)
Pulse duration, MMC[x]_CLK high
ns
Pulse duration, MMC[x]_CLK low
ns
Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition
Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition
13.69
13.69
ns
1.2
ns
SDR125
SDR126
SDR127
MMC[x]_CLK
SDR128
SDR128
MMC[x]_CMD
SDR129
SDR129
MMC[x]_DAT[3:0]
Figure 7-102. MMC1/2 – UHS-I SDR12 – Transmit Mode
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7.10.5.19.2.4 UHS–I SDR25 Mode
Table 7-85, Figure 7-103, Table 7-86, and Figure 7-104 present timing requirements and switching
characteristics for MMC1/2 – UHS-I SDR25 Mode.
Table 7-85. MMC1/2 Timing Requirements – UHS-I SDR25 Mode
see Figure 7-103
NO.
MIN
2.15
1.67
2.15
1.67
MAX
UNIT
ns
SDR251 tsu(cmdV-clkH)
SDR252 th(clkH-cmdV)
SDR253 tsu(dV-clkH)
SDR254 th(clkH-dV)
Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge
Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge
Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge
Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge
ns
ns
ns
A. x = 1, 2 for MMC1 and MMC2
B. x = 1, 2 for MMC1 and MMC2
MMC[x]_CLK
MMC[x]_CMD
SDR252
SDR254
SDR251
SDR253
MMC[x]_DAT[3:0]
Figure 7-103. MMC1/2 – UHS-I SDR25 – Receive Mode
Table 7-86. MMC1/2 Switching Characteristics – UHS-I SDR25 Mode
see Figure 7-104
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
SDR255 tc(clk)
Operating frequency, MMC[x]_CLK
50
Cycle time, MMC[x]_CLK
20
9.2
9.2
2.4
2.4
SDR256 tw(clkH)
SDR257 tw(clkL)
SDR258 td(clkH-cmdV)
SDR259 td(clkH-dV)
Pulse duration, MMC[x]_CLK high
ns
Pulse duration, MMC[x]_CLK low
ns
Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition
Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition
9.8
9.8
ns
ns
SDR255
SDR256
SDR257
MMC[x]_CLK
SDR258
SDR258
MMC[x]_CMD
SDR259
SDR259
MMC[x]_DAT[3:0]
Figure 7-104. MMC1/2 – UHS-I SDR25 – Transmit Mode
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7.10.5.19.2.5 UHS–I SDR50 Mode
Table 7-87, and Figure 7-105 presents switching characteristics for MMC1/2 – UHS-I SDR50 Mode.
Table 7-87. MMC1/2 Switching Characteristics – UHS-I SDR50 Mode
see Figure 7-105
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC[x]_CLK
100
SDR505 tc(clk)
Cycle time, MMC[x]_CLK
10
4.45
4.45
1.2
SDR506 tw(clkH)
SDR507 tw(clkL)
SDR508 td(clkH-cmdV)
SDR509 td(clkH-dV)
Pulse duration, MMC[x]_CLK high
ns
Pulse duration, MMC[x]_CLK low
ns
Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition
Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition
6.35
6.35
ns
1.2
ns
A. x = 1, 2 for MMC1 and MMC2
SDR505
SDR506
SDR507
MMC[x]_CLK
MMC[x]_CMD
SDR508
SDR508
SDR509
SDR509
MMC[x]_DAT[3:0]
Figure 7-105. MMC1/2 – UHS-I SDR50 – Transmit Mode
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7.10.5.19.2.6 UHS–I DDR50 Mode
Table 7-88 and Figure 7-106 present switching characteristics for MMC1/2 – UHS-I DDR50 Mode.
Table 7-88. MMC1/2 Switching Characteristics – UHS-I DDR50 Mode
see Figure 7-106
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC[x]_CLK
50
DDR505
DDR506
DDR507
DDR508
DDR509
tc(clk)
Cycle time, MMC[x]_CLK
20
9.2
9.2
1.2
1.2
tw(clkH)
tw(clkL)
td(clkH-cmdV)
td(clk-dV)
Pulse duration, MMC[x]_CLK high
ns
Pulse duration, MMC[x]_CLK low
ns
Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition
Delay time, MMC[x]_CLK transition to MMC[x]_DAT[3:0] transition
9.8
ns
6.35
ns
A. x = 1, 2 for MMC1 and MMC2
DDR505
DDR506
DDR507
MMC[x]_CLK
MMC[x]_CMD
DDR508
DDR509
DDR509
MMC[x]_DAT[3:0]
Figure 7-106. MMC1/2 – UHS-I DDR50 – Transmit Mode
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7.10.5.19.2.7 UHS–I SDR104 Mode
Table 7-89, and Figure 7-107 present switching characteristics for MMC1/2 – UHS-I SDR104 Mode.
Table 7-89. MMC1/2 Switching Characteristics – UHS-I SDR104 Mode
see Figure 7-107
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC[x]_CLK
200
SDR1045 tc(clk)
Cycle time, MMC[x]_CLK
5
2.08
2.08
1.12
1.12
SDR1046 tw(clkH)
SDR1047 tw(clkL)
SDR1048 td(clkH-cmdV)
SDR1049 td(clkH-dV)
Pulse duration, MMC[x]_CLK high
ns
Pulse duration, MMC[x]_CLK low
ns
Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition
Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition
3.16
3.16
ns
ns
A. x = 1, 2 for MMC1 and MMC2
SDR1045
SDR1046
SDR1047
MMC[x]_CLK
MMC[x]_CMD
SDR1048
SDR1048
SDR1049
SDR1049
MMC[x]_DAT[3:0]
Figure 7-107. MMC1/2 – UHS-I SDR104 – Transmit Mode
7.10.5.20 CPTS
Table 7-90 represents CPTS timing conditions.
Table 7-90. CPTS Timing Conditions
PARAMETER
DESCRIPTION
MIN
0.5
2
MAX
5
UNIT
INPUT CONDITIONS
SRI
Input slew rate
V/ns
pF
OUTPUT CONDITIONS
CL
Output load capacitance
10
Section 7.10.5.20.1, Section 7.10.5.20.2, Figure 7-108, and Figure 7-109 present timing requirements and
switching characteristics of the CPTS interface.
7.10.5.20.1 CPTS Timing Requirements
see Figure 7-108
NO.
T1
T2
T3
T4
T5
MIN
12P + 2(1)
12P + 2(1)
5
MAX UNIT
tw(HWnTSPUSHH)
tw(HWnTSPUSHL)
tc(RFT_CLK)
Pulse duration, HWnTSPUSH(2) high
Pulse duration, HWnTSPUSH(2) low
Cycle time, RFT_CLK
ns
ns
8
ns
ns
ns
tw(RFT_CLKH)
tw(RFT_CLKL)
Pulse duration, RFT_CLK high
Pulse duration, RFT_CLK low
0.45 * T(3)
0.45 * T(3)
(1) P = functional clock period in ns.
(2) In HWnTSPUSH, n = 1 to 2.
(3) T = RFT_CLK period in ns.
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T1
T2
HWn_TSPUSH
RFT_CLK
T3
T4
T5
Figure 7-108. CPTS Timing Requirements
7.10.5.20.2 CPTS Switching Characteristics
see Figure 7-109
NO.
PARAMETER
SOURCE
MIN
36P - 2(1)
36P - 2(1)
36P - 2(1)
36P - 2(1)
36P - 2(1)
5P - 2(1)
MAX UNIT
T6
T7
T8
T9
tw(TS_COMPH)
Pulse duration, TS_COMP high
Pulse duration, TS_COMP low
Pulse duration, TS_SYNC high
Pulse duration, TS_SYNC low
ns
ns
ns
ns
ns
ns
ns
ns
tw(TS_COMPL)
tw(TS_SYNCH)
tw(TS_SYNCL)
TS_SYNC
T10
T11
tw(SYNC_OUTH)
Pulse duration, SYNCn_OUT(2) high
Pulse duration, SYNCn_OUT(2) low
TS_GENF
TS_SYNC
TS_GENF
36P - 2(1)
5P - 2(1)
tw(SYNC_OUTL)
(1) P = functional clock period in ns.
(2) n = 0 to 3 in SYNCn_OUT
T6
T7
TS_COMP
T8
T9
TS_SYNC
T10
T11
SYNCn_OUT
Figure 7-109. CPTS Switching Characteristics
For more information, see Navigator Subsystem (NAVSS) section in Data Movement Architecture (DMA) chapter
in the device TRM.
7.10.5.21 OSPI
For more details about features and additional description information on the device Octal Serial Peripheral
Interface, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed
Description.
Table 7-91 represents OSPI timing conditions.
Table 7-91. OSPI Timing Conditions
PARAMETER
INPUT CONDITIONS
SRI
MIN
MAX
UNIT
Input slew rate
3.3 V
2
1
6
6
V/ns
V/ns
All other modes
OUTPUT CONDITIONS
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Table 7-91. OSPI Timing Conditions (continued)
PARAMETER
MIN
MAX
UNIT
CL
Output load capacitance
All modes
3
10
pF
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay)
Propagation delay
OSPI_CLK trace
No Loopback;
Internal Pad
Loopback
ps
450
Propagation delay
OSPI_LBCLKO trace
External Board
Loopback
ps
ps
ps
2*L-30(2)
L-30(2)
2*L+30(2)
L+30(2)
Propagation delay
OSPI_DQS trace
DQS
td(Trace Mismatch Delay)
Propagation delay mismatch
OSPI_D[i:0](1), OSPI_CSn
relative to OSPI_CLK
All modes
60
(1) i in D[i:0] = 0 to 7 for OSPI0; i in [i:0] = 3 for OSPI1
(2) L = Propagation delay of OSPI_CLK trace
7.10.5.21.1 OSPI With Data Training
Note
I/O timing requirements and switching characteristics are not applicable when OSPI is used with data
training. Follow the Section 9.3.2, OSPI and QSPI Board Design and Layout Guidelines section to
ensure proper operation.
7.10.5.21.1.1 OSPI Switching Characteristics – Data Training
PARAMETER
DESCRIPTION
MODE
MIN
6
MAX
UNIT
ns
tc(CLK)
Cycle time, CLK
Cycle time, CLK
DDR, 1.8V
DDR, 3.3V
SDR, 1.8V
SDR, 3.3V
7.5
6
ns
tc(CLK)
ns
7.5
ns
7.10.5.21.2 OSPI Without Data Training
Note
The I/O Timings provided in this section are only applicable when data training is not implemented.
Additionally, the I/O Timings are valid only for some OSPI usage modes when the corresponding DLL
Delays are configured as described in Table 7-92 found in this section.
Section 7.10.5.21.2.4, Section 7.10.5.21.2.2, Section 7.10.5.21.2, and Section 7.10.5.21.2 present switching
characteristics for OSPI DDR and SDR Mode.
7.10.5.21.2.1 OSPI Timing Requirements – SDR Mode
Table 7-92. OSPI DLL Delay Mapping - SDR Timing Modes
MODE
OSPI_PHY_CONFIGURATION_REG BIT FIELD
PHY_CONFIG_TX_DLL_DELAY_FLD
PHY_CONFIG_RX_DLL_DELAY_FLD
DELAY VALUE
All modes
0x0
0x0
NO.
PARAMETER
DESCRIPTION
MODE
MIN
-2.19
-1.71
7.62
8.1
MAX
UNIT
ns
O19 tsu(D-CLK)
Setup time, D[i:0] valid before active CLK
edge(1)
1.8V, Internal Loopback
3.3V, Internal Loopback
1.8V, Internal Loopback
3.3V, Internal Loopbacl
ns
O20 th(CLK-D)
Hold time, D[i:0] valid after active CLK
edge(1)
ns
ns
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NO.
PARAMETER
DESCRIPTION
MODE
MIN
-3.1
MAX
UNIT
ns
O21 tsu(D-LBCLK)
Setup time, D[i:0] valid before active LBCLK
input (DQS) edge(1)
1.8V, External Board Loopback
3.3V, External Board Loopback
1.8V, External Board Loopback
3.3V, External Board Loopback
-2.72
3.81
4.33
ns
O22 th(LBCLK-D)
Hold time, D[i:0] valid after active LBCLK
input (DQS) edge(1)
ns
ns
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1
OSPI_CLK
O19
O20
OSPI_D[i:0]
OSPI_TIMING_05
Figure 7-110. OSPI Timing Requirements – SDR, Internal Clock and Internal Pad Loopback Clock
OSPI_DQS
O21
O22
OSPI_D[i:0]
OSPI_TIMING_06
Figure 7-111. OSPI Timing Requirements – SDR, External Loopback Clock
7.10.5.21.2.2 OSPI Switching Characteristics – SDR Mode
NO. PARAMETER
DESCRIPTION
MODE
1.8V
MIN
7
MAX
UNIT
ns
O7 tc(CLK)
Cycle time, CLK
3.3V
7.5
ns
O8 tw(CLKL)
O9 tw(CLKH)
O10 td(CLK-CSn)
Pulse duration, CLK low
-0.3+0.475*P
ns
(2)
Pulse duration, CLK high
-0.3+0.475*P
ns
ns
(2)
Delay time, CLK rising edge to CSn active edge
1.8V
3.3V
1.8V
3.3V
0.475 * P +
0.475 * P +
0.975 * N * R 0.975 * N * R
(2) (3) (5)
+ 1 (3) (3) (5)
0.475 * P +
0.475 * P +
ns
ns
ns
0.975 * N * R 0.975 * N * R
(2) (3) (5)
+ 1 (2) (3) (5)
O11 td(CLK-CSn)
Delay time, CLK rising edge to CSn inactive
edge
0.475 * P +
0.975 * N * R 0.975 * N * R
- 1 (2) (4) (5) + 1 (2) (4) (5)
0.475 * P +
-1+0.475 * P 1+0.475 * P +
+ 0.975 * N * 0.975 * N * R
R (2) (4) (5)
(2) (4) (5)
O12 td(CLK-D)
Delay time, CLK active edge to D[i:0]
transition(1)
1.8V
3.3V
-1.16
-1.33
1.25
1.51
ns
ns
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1
(2) P = CLK cycle time = SCLK period
(3) N = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(4) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(5) R = refclk
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OSPI_CSn
O11
O10
O7
O9
O8
OSPI_CLK
OSPI_D[i:0]
O12
OSPI_TIMING_02
Figure 7-112. OSPI Switching Characteristics – SDR
Section 7.10.5.21.2.3, Section 7.10.5.21.2.1, Section 7.10.5.21.2.2, Section 7.10.5.21.2.2, and Figure 7-111
presents timing requirements for OSPI DDR and SDR Mode.
7.10.5.21.2.3 OSPI Timing Requirements – DDR Mode
Table 7-93. OSPI DLL Delay Mapping - DDR Timing Modes
OSPI_PHY_CONFIGURATION_REG BIT
FIELD
OSPI Instance
MODE
DELAY VALUE
1.8V
PHY_CONFIG_TX_DLL_DELAY_FLD
PHY_CONFIG_TX_DLL_DELAY_FLD
PHY_CONFIG_RX_DLL_DELAY_FLD
PHY_CONFIG_RX_DLL_DELAY_FLD
0x41
0x3D
0x14
0x1F
0x0
3.3V
1.8V DQS
3.3V DQS
All other modes
OSPI0
PHY_CONFIG_TX_DLL_DELAY_FLD
PHY_CONFIG_RX_DLL_DELAY_FLD
1.8V
PHY_CONFIG_TX_DLL_DELAY_FLD
PHY_CONFIG_TX_DLL_DELAY_FLD
PHY_CONFIG_RX_DLL_DELAY_FLD
PHY_CONFIG_RX_DLL_DELAY_FLD
0x42
0x3F
0x16
0x1F
0x0
3.3V
1.8V DQS
3.3V DQS
All other modes
OSPI1
PHY_CONFIG_TX_DLL_DELAY_FLD
PHY_CONFIG_RX_DLL_DELAY_FLD
NO. PARAMETER
DESCRIPTION
MODE
MIN
0.52
1.97
MAX
UNIT
ns
O15 tsu(D-LBCLK)
Setup time, D[i:0] valid before active LBCLK (DQS) 1.8V, External Board Loopback
edge(1)
3.3V, External Board Loopback
ns
O16 th(LBCLK-D)
O17 tsu(D-DQS)
O18 th(DQS-D)
Hold time, D[i:0] valid after active LBCLK (DQS)
edge(1)
1.8V, External Board Loopback 1.24 (2)
3.3V, External Board Loopback 1.44 (2)
ns
ns
Setup time, DQS edge to D[i:0] transition(1)
1.8V, DQS
3.3V, DQS
1.8V, DQS
3.3V, DQS
-0.46
-0.66
3.59
8.89
ns
ns
Hold time, DQS edge to D[i:0] transition(1)
ns
ns
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1
(2) This Hold time requirement is larger than the Hold time provided by a typical flash device. Therefore, the trace length between the
SoC and flash device must be sufficiently long enough to ensure that the Hold time is met at the SoC. Refer to Section 9.3.2 for more
details.
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OSPI_DQS
OSPI_D[i:0]
O15 O16
OSPI_TIMING_04
Figure 7-113. OSPI Timing Requirements – DDR, External Loopback Clock and DQS
7.10.5.21.2.4 OSPI Switching Characteristics – DDR Mode
NO. PARAMETER
DESCRIPTION
MODE
1.8V
MIN
19
MAX
UNIT
ns
O1 tc(CLK)
Cycle time, CLK
3.3V
19
ns
O2 tw(CLKL)
O3 tw(CLKH)
O4 td(CLK-CSn)
Pulse duration, CLK low
0.475*P - 0.3
ns
(2)
Pulse duration, CLK high
0.475*P - 0.3
ns
ns
(2)
Delay time, CSn active edge to CLK rising edge
1.8V
3.3V
1.8V
0.475 * P +
0.475 * P +
0.975 * N * R 0.975 * N * R
(2) (3) (5)
+ 1 (2) (3) (5)
0.475 * P +
0.475 * P +
ns
ns
ns
0.975 * N * R 0.975 * N * R
(2) (3) (5)
+ 1(2) (3) (5)
O5 td(CLK-CSn)
Delay time, CLK rising edge to CSn inactive
edge
0.475 * P +
0.475 * P +
0.975 * N * R 0.975 * N * R
- 7(2) (4) (5)
(2) (4) (5)
3.3V, OSPI0 DDR TX; 0.475 * P +
0.475 * P +
3.3V, OSPI1 DDR TX 0.975 * N * R 0.975 * N * R
- 7(2) (4) (5)
(2) (4) (5)
O6 td(CLK-D)
Delay time, CLK active edge to D[i:0]
transition(1)
1.8V, OSPI0 DDR TX;
1.8V, OSPI1 DDR TX
-7.71
-1.56
-1.56
ns
ns
3.3V, OSPI0 DDR TX;
3.3V, OSPI1 DDR TX
-7.71
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1
(2) P = CLK cycle time = SCLK period
(3) N = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(4) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(5) R = refclk
OSPI_CSn
O4
O3
O5
OSPI_CLK
O2
O1
O6
O6
OSPI_D[i:0]
OSPI_TIMING_01
Figure 7-114. OSPI Switching Characteristics – DDR
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7.10.5.22 OLDI
7.10.5.22.1 OLDI Switching Characteristics
NO.
O1
O2
O3
O4
O5
O6
O7
O8
PARAMETER
MODE
IOSET1
IOSET1
IOSET1
IOSET1
IOSET1
IOSET1
IOSET1
IOSET1
MIN
0.18
0.18
1
MAX
0.5
UNIT
ns
LVDS Low-to-High Transition Time max
LVDS high-to-low Transition Time max
Transmitter Output Bit Width min
0.5
ns
1
UI
Transmitter Pulse Positions – Normalized
Variation in transmitter pulse position across Bit 7:0 pulse positions
TxOut Channel to Channel Skew
0.25
-0.06
0.75
0.06
110
0.035
0.25
ns
ns
ns
Transmitter Jitter Cycle-to-Cycle
0.028
ns
Input Total Jitter Tolerance (Includes data to clock skew, pulse position
variation.)
ns
T
OLDI_CLK
bit 0
bit 1
bit 0
3UI
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
1UI
OLDI_DATA[3:0]
tTPP1
tTPP2
tTPP3
tTPP4
tTPP5
tTPP6
tTPP7
2UI
ΔtTPP
4UI
5UI
6UI
7UI
Figure 7-115. OLDI Transmitter Pulse Positions
Ideal Data
Bit Beginning
Ideal Data
Bit End
Sampling
Window
VTH
OLDI_DATA[3:0]
0 V
VTL
DATA_TOL
Right
DATA_TOL
Left
Ideal Center Position (tBIT/2)
tBIT (1UI)
Figure 7-116. OLDI Data Output Jitter
+VOD
80%
80%
VSS=2|VOD|
OLDI_CLK
0 V
20%
20%
LLHT
-VOD
LLHT
Figure 7-117. LVDS Output Transition Times
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For more information, see Display Subsystem (DSS) and Peripherals section in Peripherals chapter in the device
TRM.
7.10.5.23 PCIE
The PCI-Express Subsystem is compliant with the PCIe® Base Specification, Revision 4.0. Refer to the
specification for timing details.
For more details about features and additional description information on the device Peripheral Component
Interconnect Express, see the corresponding sections within , Section 6.3, Signal Descriptions and Section 8,
Detailed Description.
For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals
chapter in the device TRM.
7.10.5.24 Timers
For more details about features and additional description information on the device Timers, see the
corresponding sections within , Section 6.3, Signal Descriptions and Section 8, Detailed Description.
Table 7-94 represents Timers timing conditions.
Table 7-94. Timers Timing Conditions
PARAMETER
DESCRIPTION
MODE
CAPTURE
PWM
MIN
0.5
2
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
10
Section 7.10.5.24.1, Section 7.10.5.24.2 and Figure 7-118 present timings and switching characteristics of the
Timers.
7.10.5.24.1 Timing Requirements for Timers
NO.
PARAMETER
tw(TINPH)
DESCRIPTION
MODE
MIN
MAX UNIT
T1
Pulse duration, high
Pulse duration, low
CAPTURE
2.5 +
4P(1)
ns
T2
tw(TINPL)
CAPTURE
2.5 +
4P(1)
ns
(1) P = functional clock period in ns.
7.10.5.24.2 Switching Characteristics for Timers
NO.
PARAMETER
tw(TOUTH)
DESCRIPTION
MODE
MIN
MAX
UNIT
T3
Pulse duration, high
Pulse duration, low
PWM
-2.5 +
4P(1)
ns
T4
tw(TOUTL)
PWM
-2.5 +
4P(1)
ns
(1) P = functional clock period in ns.
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T1
T2
TIMER_IOx (inputs)
T3
T4
TIMER_IOx (outputs)
TIMER_01
Figure 7-118. Timer Timing
For more information, see Timers section in Peripherals chapter in the device TRM.
7.10.5.25 UART
For more details about features and additional description information on the device Universal Asynchronous
Receiver Transmitter, see the corresponding sections within , Section 6.3, Signal Descriptions and Section 8,
Detailed Description.
Table 7-95 represents UART timing conditions.
Table 7-95. UART Timing Conditions
PARAMETER
DESCRIPTION
MIN
0.5
1
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
30
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch Delay) Propagation delay mismatch across all traces
100
ps
Section 7.10.5.25.1, Section 7.10.5.25.2, and Figure 7-119 present timing requirements and switching
characteristics for UART interface.
7.10.5.25.1 Timing Requirements for UART
NO.
4
PARAMETER
tw(rxd)
tw(rxdS)
DESCRIPTION
Pulse width, receive data bit, high or low
Pulse width, receive start bit, low
MODE
MIN
MAX
UNIT
ns
0.95U(1) 1.05U(1)
0.95U(1)
5
ns
(1) U = UART baud time = 1/Programmed baud rate
7.10.5.25.2 UART Switching Characteristics
NO.
PARAMETER
fop(baud)
DESCRIPTION
Maximum programmable baud rate
MODE
15 pF
30 pF
MIN
MAX
12
UNIT
MHz
0.115
1
2
3
td(ctsnL-txdV)
tw(txd)
Delay time, receive CTSn bit to transmit data
Pulse width, transmit data bit, high or low
Pulse width, transmit start bit, low
30
U - 2(1)
U - 2(1)
ns
ns
ns
U + 2(1)
tw(txdS)
(1) U = UART baud time = 1/Programmed baud rate
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Figure 7-119. UART Timing
For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter
in the device TRM.
7.10.5.26 USB
The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the
specification for timing details.
The USB 3.1 GEN1 Dual-Role Device Subsystem is compliant with the Universal Serial Bus (USB) 3.1
Specification, revision 1.0. Refer to the specification for timing details.
For more details about features and additional description information on the device Universal Serial Bus
Subsystem (USB), see the corresponding sections within Section 6.3, Signal Descriptions and Section 8,
Detailed Description.
7.10.6 Emulation and Debug
7.10.6.1 Trace
Table 7-96. Trace Timing Conditions
PARAMETER
MIN
MAX
UNIT
OUTPUT CONDITIONS
CL
Output load capacitance
2
5
pF
PCB CONNECTIVITY REQUIREMENTS
Propagation delay mismatch across
all traces
td(Trace Mismatch)
200
ps
Table 7-97 and Figure 7-120 assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 7-97. Trace Switching Characteristics
NO.
PARAMETER
MIN
MAX UNIT
1.8 V Mode
DBTR1 tc(TRC_CLK)
Cycle time, TRC_CLK
6.50
2.50
2.50
0.81
0.81
ns
ns
ns
ns
ns
DBTR2 tw(TRC_CLKH)
Pulse width, TRC_CLK high
DBTR3 tw(TRC_CLKL)
Pulse width, TRC_CLK low
DBTR4 tosu(TRC_DATAV-TRC_CLK)
DBTR5 toh(TRC_CLK-TRC_DATAI)
Output setup time, TRC_DATA valid to TRC_CLK edge
Output hold time, TRC_CLK edge to TRC_DATA invalid
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Table 7-97. Trace Switching Characteristics (continued)
PARAMETER
MIN
0.81
0.81
MAX UNIT
DBTR6 tosu(TRC_CTLV-TRC_CLK)
Output setup time, TRC_CTL valid to TRC_CLK edge
Output hold time, TRC_CLK edge to TRC_CTL invalid
3.3 V Mode
ns
ns
DBTR7 toh(TRC_CLK-TRC_CTLI)
DBTR1 tc(TRC_CLK)
Cycle time, TRC_CLK
9.75
4.13
4.13
1.22
1.22
1.22
1.22
ns
ns
ns
ns
ns
ns
ns
DBTR2 tw(TRC_CLKH)
Pulse width, TRC_CLK high
DBTR3 tw(TRC_CLKL)
Pulse width, TRC_CLK low
DBTR4 tosu(TRC_DATAV-TRC_CLK)
DBTR5 toh(TRC_CLK-TRC_DATAI)
DBTR6 tosu(TRC_CTLV-TRC_CLK)
DBTR7 toh(TRC_CLK-TRC_CTLI)
Output setup time, TRC_DATA valid to TRC_CLK edge
Output hold time, TRC_CLK edge to TRC_DATA invalid
Output setup time, TRC_CTL valid to TRC_CLK edge
Output hold time, TRC_CLK edge to TRC_CTL invalid
DBTR1
DBTR2
DBTR3
TRC_CLK
(Worst Case 1)
(Ideal)
(Worst Case 2)
DBTR4
DBTR6
DBTR5
DBTR7
DBTR4
DBTR6
DBTR5
DBTR7
TRC_DATA
TRC_CTL
SPRSP08_Debug_01
Figure 7-120. Trace Switching Characteristics
7.10.6.2 JTAG
For more details about features and additional description information on the device IEEE 1149.1 Standard–
Test–Access Port, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8,
Detailed Description.
Table 7-98. JTAG Timing Conditions
PARAMETER
MIN
0.25
5
MAX
2.00
15
UNIT
V/ns
pF
Input Conditions
SRI
Input slew rate
Output Conditions
CL
Output load capacitance
7.10.6.2.1 JTAG Electrical Data and Timing
Section 7.10.6.2.1.1, Section 7.10.6.2.1.2, and Figure 7-121 assume testing over the recommended operating
conditions and electrical characteristic conditions.
7.10.6.2.1.1 JTAG Timing Requirements
See Figure 7-121
NO.
MIN
100
40
MAX UNIT
J1
tc(TCK)
Cycle time minimum, TCK
ns
ns
ns
ns
ns
J2
tw(TCKH)
Pulse width minimum, TCK high
J3
tw(TCKL)
Pulse width minimum, TCK low
40
tsu(TDI-TCK)
tsu(TMS-TCK)
Input setup time minimum, TDI valid to TCK high
Input setup time minimum, TMS valid to TCK high
13
J4
13
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See Figure 7-121
NO.
MIN
7.7
MAX UNIT
th(TCK-TDI)
th(TCK-TMS)
Input hold time minimum, TDI valid from TCK high
Input hold time minimum, TMS valid from TCK high
ns
ns
J5
7.7
1. The JTAG signals are split across two IO power domains on the device. Timings parameters defined in
this table only apply when the two IO power domains are operating at the same voltage. Values for these
timing parameters are not defined when operating the two IO power domains at different voltages since
propagation delay through the device IO buffers differ when some are operating at 1.8V while others are
operating at 3.3V. This effectively reduces timing margin beyond the values defined in this table. The JTAG
interface is still expected to function when the two IO power domains are operated at different voltages,
assuming the system designer has implemented appropriate level shifters and the operating frequency is
reduced to accommodate additional delay inserted by the level-shifters and IO buffers operating at different
voltages.
7.10.6.2.1.2 JTAG Switching Characteristics
See Figure 7-121
NO.
PARAMETER
MIN
MAX UNIT
J6
td(TCKL-TDOI)
td(TCKL-TDOV)
Delay time minimum, TCK low to TDO invalid
Delay time maximum, TCK low to TDO valid
0
ns
J7
37.75
ns
1. The JTAG signals are split across two IO power domains on the device. Timings parameters defined in
this table only apply when the two IO power domains are operating at the same voltage. Values for these
timing parameters are not defined when operating the two IO power domains at different voltages since
propagation delay through the device IO buffers differ when some are operating at 1.8V while others are
operating at 3.3V. This effectively reduces timing margin beyond the values defined in this table. The JTAG
interface is still expected to function when the two IO power domains are operated at different voltages,
assuming the system designer has implemented appropriate level shifters and the operating frequency is
reduced to accommodate additional delay inserted by the level-shifters and IO buffers operating at different
voltages.
J1
J2
J3
TCK
TDI / TMS
TDO
J4
J5
J4
J5
J7
J6
Figure 7-121. JTAG Timing Requirements and Switching Characteristics
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8 Detailed Description
8.1 Overview
DRA829 Jacinto™ 7 processors, based on the Arm®v8 64-bit architecture, provide advanced system integration
to enable lower system costs of applications such as Infotainment, Cluster, Premium Audio, and Gateway . The
integrated diagnostics and functional safety features are targeted to ASIL-B/C certification/requirements. The
integrated microcontroller (MCU) island eliminates the need for an external system MCU. The device features a
Gigabit Ethernet switch and a PCIe hub which enables networking use cases that require heavy data bandwidth.
The hardware accelerators allow for vision pre-processing, distance and motion processing with minimal impact
on system performance. Up to six Arm® Cortex®-R5F subsystems manage low level, timing critical processing
tasks leaving the Arm® Cortex®-A72’s unencumbered for applications. A dual-core cluster configuration of
Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor.
Note
For more information on features, subsystems, and architecture of superset device System on Chip
(SoC), see the device TRM.
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8.2 Processor Subsystems
8.2.1 Arm Cortex-A72
The device implements one dual-core Arm® Cortex®-A72 MPU, which is integrated inside the Compute Cluster,
along with other modules. The Cortex-A72 cores are general-purpose processors that can be used for running
customer applications.
The A72SS is built around the Arm Cortex-A72 MPCore (A72 cluster), which is provided by Arm and configured
by TI. It is based on the symmetric multiprocessor (SMP) architecture, and thus it delivers high performance and
optimal power management and debug capabilities.
The A72 processor is a multi-issue out-of-order superscalar execution engine with integrated L1 instruction and
data caches, compatible with Armv8-A architecture. The Armv8-A architecture brings a number of new features.
These include 64-bit data processing, extended virtual addressing and 64-bit general purpose registers.
For more information, see Dual-A72 MPU Subsystem section in Processors and Accelerators chapter in the
device TRM.
8.2.2 Arm Cortex-R5F
The MCU_ARMSS is a dual-core implementation of the Arm® Cortex®-R5F processor configured for split/lock
operation. It also includes accompanying memories (L1 caches and tightly-coupled memories), standard Arm®
CoreSight™ debug and trace architecture, integrated Vectored Interrupt Manager (VIM), ECC Aggregators, and
various wrappers for protocol conversion and address translation for easy integration into the SoC.
For more information, see Dual-R5F MCU Subsystem section in Processors and Accelerators chapter in the
device TRM.
8.2.3 DSP C71x
The TMS320C71x is the next-generation fixed and floating-point DSP platform. The C71x DSP is a new core in
the Texas Instruments' DSP family. The C71x DSP supports vector signal processing, providing significant lift in
DSP processing power over a broad range of general signal processing tasks in comparison to the C6x DSP
family. In addition, the C71x provides several specialized functions which accelerate targeted functions by more
than 30 times. Besides expanding vector processing capabilities, the new C71x core also incorporates advanced
techniques to improve control code efficiency and ease of programming such as branch prediction, protected
pipeline, precise exception and virtual memory management.
For more information, see C71x DSP Subsystem section in Processors and Accelerators chapter in the device
TRM.
8.2.4 DSP C66x
The C66x subsystem is based on the TI's standard TMS320C66x™ DSP CorePac module. It includes
subsystem logic to ease the C66x CorePac integration into the SoC, while maximizing software reuse from
previous devices.
The C66x DSP extends the performance of the C64x+ and C674x DSPs through enhancements and new
features. Many of the new features target increased performance for vector processing. The C64x+ and C674x
DSPs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data. On C66x DSP,
the vector processing capability is improved by extending the width of the SIMD instructions.
The C66x DSP can execute instructions that operate on 128-bit vectors. For example, the QMPY32 instruction
is able to perform the element-to-element multiplication between two vectors of four 32-bit data each. The
C66x DSP also supports SIMD for floating-point operations. Improved vector processing capability (each
instruction can process multiple data in parallel) combined with the natural instruction level parallelism of C6000
architecture (for example, execution of up to eight instructions per cycle) results in a very high level of parallelism
that can be exploited by DSP programmers through the use of TI's optimized C/C++ compiler.
For more information, see C66x DSP Subsystem section in Processors and Accelerators chapter in the device
TRM.
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8.3 Accelerators and Coprocessors
8.3.1 GPU
The Graphics Processing Unit (GPU) accelerates 3-dimensional (3D) and 2-dimensional (2D) graphics and
compute applications.
The GPU module is a scalable architecture which efficiently processes a number of different workload
concurrently:
•
•
•
3D Graphic Workload, which involves vertex data and pixel data processing for rendering of 3D scenes.
2D Graphic Workload, which involves pixel data processing for rendering 2D objects.
Compute Applications Workload, which involves general purpose data processing.
For more information, see Graphics Accelerator (GPU) section in Processors and Accelerators chapter in the
device TRM.
8.3.2 D5520MP2
The DECODER module is a D5520MP2 dual-core PowerVR® VPU (video processor unit).
The D5520MP2 is capable of supporting:
•
•
•
•
1x 4kp60 decode or
2x 4kp30 decodes or
4x 1080p60 decodes or
8x 1080p30 decodes
For more information, see Multi-Standard HD Video Decoder (D5520MP2) section in Processors and
Accelerators chapter in the device TRM.
8.3.3 VXE384MP2
The ENCODER module is a VXE384MP2 core PowerVR® VPU (video processor unit).
The VXE384MP2 is capable of supporting:
•
•
1x 1080p60 video stream encoding or
2x or 3x 1080p30 video stream encodings
For more information, see Multi-Standard HD Video Encoder (VXE384MP2) section in Processors and
Accelerators chapter in the device TRM.
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8.4 Other Subsystems
8.4.1 MSMC
The Multicore Shared Memory Controller (MSMC) forms the heart of the compute cluster
(COMPUTE_CLUSTER0) providing high-bandwidth resource access both to and from all of the connected
processing elements and the rest of the system. MSMC serves as the data-movement backbone of the compute
cluster.
For more information, see Multicore Shared Memory Controller (MSMC) section in Device Configuration chapter
in the device TRM.
8.4.2 NAVSS
8.4.2.1 NAVSS0
Main SoC Navigator Subsystem (NAVSS0) consists of DMA/Queue Management components – UDMA and
Ring Accelerator (UDMASS), Peripherals (Module subsystem [MODSS]), Virtualization translation (VirtSS), and
a North Bridge (NBSS).
8.4.2.2 MCU_NAVSS
MCU Navigator Subsystem (MCU NAVSS) has a subset of the modules of the main NAVSS and is instantiated
in the MCU domain.
MCU Navigator Subsystem consists of DMA/Queue Management components – UDMA and Ring Accelerator
(UDMASS), and Peripherals (Module subsystem [MODSS]).
For more information, see Main Navigator Subsystem (NAVSS) and MCU Navigator Subsystem (MCU NAVSS)
sections in Data Movement Architecture (DMA) chapter in the device TRM.
8.4.3 PDMA Controller
The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer
needs of peripherals, which perform data transfers using memory mapped registers accessed via a standard
non-coherent bus fabric. The PDMA module is intended to be located close to one or more peripherals which
require an external DMA for data movement and is architected to reduce cost by using VBUSP interfaces and
supporting only statically configured Transfer Request (TR) operations.
The PDMA is only responsible for performing the data movement transactions which interact with the peripherals
themselves. Data which is read from a given peripheral is packed by a PDMA source channel into a PSI-L data
stream which is then sent to a remote peer UDMA-P destination channel which then performs the movement of
the data into memory. Likewise, a remote UDMA-P source channel fetches data from memory and transfers it to
a peer PDMA destination channel over PSI-L which then performs the writes to the peripheral.
The PDMA architecture is intentionally heterogeneous (UDMA-P + PDMA) to right size the data transfer
complexity at each point in the system to match the requirements of whatever is being transferred to or
from. Peripherals are typically FIFO based and do not require multi-dimensional transfers beyond their FIFO
dimensioning requirements, so the PDMA transfer engines are kept simple with only a few dimensions (typically
for sample size and FIFO depth), hardcoded address maps, and simple triggering capabilities.
Multiple source and destination channels are provided within the PDMA which allow multiple simultaneous
transfer operations to be ongoing. The DMA controller maintains state information for each of the channels and
employs round-robin scheduling between channels in order to share the underlying DMA hardware.
For more information, see PDMA Controller section in DMA Controllers chapter in the device TRM.
8.4.4 Power Supply
The device requires 6 power supply types and 1 internal LDO connection type, see Power Supply Signal
Descriptions:
•
•
•
Digital IO Voltages
Digital Low Voltages
Digital AVS Voltage
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•
•
•
•
Analog PHY & CLK Voltages
Analog Low Voltages
Efuse Programming Voltages
LDO Bulk Filter Capacitors
Common device power supply input types can be grouped together into power rails. All power rails must be
supplied by power resources designed to support the most strigent power supply voltage specification and total
load current demands. Two recommended Power Distribution Networks (PDNs) have been defined that either
combine or isolate MCU and Main domains, (refer to Section 9.1, Power Supply Mapping).
It is possible that a few power supply inputs may not be needed in some systems. In such cases, all unused
supply inputs, other than VPP_CORE & VPP_MCU, must be connected to a valid power rail with a proper
voltage level in order to ensure device reliability (refer to Section 7.4, Recommended Operating Conditions). The
following examples are given for reference:
1. If MCU Island safety monitor or MCU Only low power processing are not used, then VDD_MCU supply can
be combined with the VDD_CORE supply with compatible operating voltage specification.
2. If UHS-I SD Card or USB2.0 interface is not needed, then VDDSHV5 (MMC1 interface) and
VDDA_USB_3P3 (USB PHY interface) can be combined with VDD_IO_3V3 digital IO power rail.
3. If General Purpose device type is used, then Efuse programming voltages VPP_CORE & VPP_MCU are not
needed and should be left unconnected.
8.4.5 Peripherals
8.4.5.1 ADC
The Analog-to-Digital Converter (ADC) module contains a single 12-bit ADC which can be multiplexed to any 1
of 8 analog inputs (channels).
For more information, see Analog-to-Digital Converter (ADC) section in Peripherals chapter in the device TRM.
8.4.5.2 ATL
The Audio Tracking Logic (ATL) is used by HD Radio™ applications to synchronize the digital audio output to
the baseband clock. This same IP can also be used generically to track errors between two reference signals
(such as frame syncs) and generate a modulated clock output (using software-controlled cycle stealing) which
averages to some desired frequency. This process can be used as a hardware assist for asynchronous sample
rate conversion algorithms.
For more information, see Audio Tracking Logic (ATL) section in Peripherals chapter in the device TRM.
8.4.5.3 CSI
8.4.5.3.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
The integration of the CSI_RX_IF module allows the device to stream video inputs from multiple cameras to
internal memory. The video input may also be retransmitted via the transmitter CSI (CSI_TX_IF) for debug and
test purposes.
For more information, see Camera Streaming Interface (CSI) section in Peripherals chapter in the device TRM.
8.4.5.3.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
The integration of the CSI_TX_IF module allows the device to stream out video data from memory, or retransmit
from the CSI receivers as an optional loopback output for diagnostics, debug, and test purposes.
For more information, see Camera Streaming Interface (CSI) section in Peripherals chapter in the device TRM.
8.4.5.4 CPSW2G
The two-port Gigabit Ethernet MAC (MCU_CPSW0) subsystem provides Ethernet packet communication for the
device and is configured in a similar manner as an Ethernet switch. MCU_CPSW0 features the Reduced Gigabit
Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data
Input/Output (MDIO) interface for physical layer device (PHY) management.
For more information, see Gigabit Ethernet Switch (CPSW0) section in Peripherals chapter in the device TRM.
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8.4.5.5 CPSW9G
The 9-port Gigabit Ethernet Switch (CPSW0) subsystem provides Ethernet packet communication for the device
and can be configured as an Ethernet switch. CPSW0 features the Serial Gigabit Media Independent Interface
(SGMII), Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII)
and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management.
For more information, see Gigabit Ethernet Switch (MCU_CPSW0) section in Peripherals chapter in the device
TRM.
8.4.5.6 DCC
The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time
execution of an application. Specifically, the DCC is designed to detect drifts from the expected clock frequency.
The desired accuracy can be programed based on calculation for each application. The DCC measures the
frequency of a selectable clock source using another input clock as a reference.
For more information, see Dual Clock Comparator (DCC) section in Peripherals chapter in the device TRM.
8.4.5.7 DDRSS
The DDR subsystem in this device comprises DDR controller, DDR PHY and wrapper logic to integrate these
blocks in the device. The DDR subsystem is referred to as DDRSS0 and is used to provide an interface to
external SDRAM devices which can be utilized for storing program or data. DDRSS0 is accessed via MSMC,
and not directly through the system interconnect.
For more information, see DDR Subsystem (DDRSS) section in Peripherals chapter in the device TRM.
8.4.5.8 DSS
The DSS is a flexible composition-enabled display subsystem, that supports multiple high resolution display
outputs. It consists of one Display Controller (DISPC) and one Frame Buffer Decompression Core (FBDC).
The DISPC supports a multi-layer blending and transparency for each of its display outputs. The DISPC also
supports a write-back pipeline with scaling to enable memory-to-memory composition and/or to capture a display
output for Ethernet video encoding.
For more information, see Display Subsystem (DSS) section in Peripherals chapter in the device TRM.
8.4.5.8.1 DSI
The MIPI DSI v1.3.1 Controller (DSITX) implements the stream arbitration and low-level protocol layer
functionalities required by MIPI DSI 1.3 standard. It supports up to 4 x 2.5 Gbps D-PHY data lanes in a single-
link configuration and handles the byte lane mapping per use case (1, 2, 3, or 4-lanes). The accompaning DSI
(Physical Layer) D-PHY module (DPHYTX) provides the video output interfacing by implementing a four-lane
MIPI D-PHY transmitter.
For more information, see Display Subsystem (DSS) and Display Peripherals section in Peripherals chapter in
the device TRM.
8.4.5.8.2 eDP
The VESA DP1.4/eDP1.4 Compliant Transmitter Host Controller (EDP) can output up to 4 video streams
(through Multiple Stream Transport / MST) and one audio stream through the 4-lane accompaning SerDes
module. It provides up to 25.92 Gbps of application bandwidth. An additional eDP (Physical Layer) auxiliary PHY
(AUXPHY) module implements a doubly-terminated differential pair required for 1 Mbps data rates over a long
(15m) cable.
For more information, see Display Subsystem (DSS) and Display Peripherals section in Peripherals chapter in
the device TRM.
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8.4.5.9 VPFE
The Video Processing Front End (VPFE) is an input interface module that receives raw (unprocessed) image/
video data or YUV digital video data from external imaging peripherals (such as image sensors, video decoders,
etc) and performs DMA transfers to store the captured data in the system DDR memory.
For more information, see Video Processing Front End (VPFE) section in Peripherals chapter in the device TRM.
8.4.5.10 eCAP
The enhanced Capture (ECAP) module can be used for:
•
•
•
•
•
Sample rate measurements of audio inputs
Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)
Elapsed time measurements between position sensor pulses
Period and duty cycle measurements of pulse train signals
Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors.
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.
8.4.5.11 EPWM
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU
overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand
and use. The EPWM unit described here addresses these requirements by allocating all needed timing and
control resources on a per PWM channel basis. Cross coupling or sharing of resources has been avoided;
instead, the EPWM is built up from smaller single channel modules with separate resources and that can
operate together as required to form a system. This modular approach results in an orthogonal architecture and
provides a more transparent view of the peripheral structure, helping users to understand its operation quickly.
In the further description the letter x within a signal or module name is used to indicate a generic EPWM instance
on a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from the EPWM_x
instance. Thus, EPWM1A and EPWM1B belong to EPWM1, EPWM2A and EPWM2B belong to EPWM2, and so
forth.
Additionally, the EPWM integration allows this synchronization scheme to be extended to the capture peripheral
modules (ECAP). The number of modules is device-dependent and based on target application needs. Modules
can also operate stand-alone.
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in
the device TRM.
8.4.5.12 ELM
The Error Location Module (ELM) is used with the GPMC. Syndrome polynomials generated on-the-fly when
reading a NAND flash page and stored in GPMC registers are passed to the ELM. A host processor can then
correct the data block by flipping the bits to which the ELM error-location outputs point.
When reading from NAND flash memories, some level of error-correction is required. In the case of NAND
modules with no internal correction capability, sometimes referred to as bare NANDs, the correction process is
delegated to the memory controller. ELM can be also used to support parallel NOR flash or NAND flash.
For more information, see Error Location Module (ELM) section in Peripherals chapter in the device TRM.
8.4.5.13 ESM
The Error Signaling Module (ESM) aggregates safety-related events and/or errors from throughout the device
into one location. It can signal both low and high priority interrupts to a processor to deal with a safety event
and/or manipulate an I/O error pin to signal an external hardware that an error has occurred. Therefore an
external controller is able to reset the device or keep the system in safe, known state.
For more information, see Error Signaling Module (ESM) section in Peripherals chapter in the device TRM.
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8.4.5.14 eQEP
The Enhnanced Quadrature Encoder Pulse (EQEP) peripheral is used for direct interface with a linear or rotary
incremental encoder to get position, direction and speed information from a rotating machine for use in high
performance motion and position control system. The disk of an incremental encoder is patterned with a single
track of slots patterns. These slots create an alternating pattern of dark and light lines. The disk count is
defined as the number of dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second
track is added to generate a signal that occurs once per revolution (index signal: QEPI), which can be used
to indicate an absolute position. Encoder manufacturers identify the index pulse using different terms such as
index, marker, home position and zero reference.
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter
in the device TRM.
8.4.5.15 GPIO
The General-Purpose Input/Output (GPIO) peripheral provides dedicated general-purpose pins that can be
configured as either inputs or outputs. When configured as an output, the user can write to an internal register to
control the state driven on the output pin. When configured as an input, user can obtain the state of the input by
reading the state of an internal register.
In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different
interrupt/event generation modes.
For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.
8.4.5.16 GPMC
The General-Purpose Memory Controller is a unified memory controller dedicated for interfacing with external
memory devices like:
•
•
Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
Asynchronous, synchronous, and page mode (available only in non-multiplexed mode) burst NOR flash
devices
•
•
NAND flash
Pseudo-SRAM devices
For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the
device TRM.
8.4.5.17 Hyperbus
The Hyperbus module is a part of the device Flash Subsystem (FSS).
The Hyperbus module is low pin count memory interface that provides high read/write performance. The
Hyperbus module connects to hyperbus memory (HyperFlash or HyperRAM) and uses simple hyperbus protocol
for read and write transactions.
There is one Hyperbus™ module inside the device. The Hyperbus module includes one Hyperbus Memory
Controller (HBMC).
For more information, see Hyperbus Interface section in Peripherals chapter in the device TRM.
8.4.5.18 I2C
The device contains ten multimaster Inter-Integrated Circuit (I2C) controllers each of which provides an interface
between a local host (LH), such as an Arm or a Digital Signal Processor (DSP), and any I2C-bus-compatible
device that connects via the I2C serial bus. External components attached to the I2C bus can serially transmit
and receive up to 8 bits of data to and from the LH device through the 2-wire I2C interface.
Each multimaster I2C module can be configured to act like a slave or master I2C-compatible device.
The WKUP_I2C0, MCU_I2C0, I2C0, and I2C1 controllers have dedicated I2C compliant open drain buffers, and
support high speed mode (up to 3.4 Mbps in 1.8 V mode and up to 400 kbps in 3.3 V mode). The MCU_I2C1,
I2C2, I2C3, I2C4, I2C5, and I2C6 controllers are multiplexed with standard LVCMOS I/O, connected to emulate
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open drain, and support fast mode (up to 400 kbps in 1.8 V/3.3 V mode). The I2C emulation is achieved by
configuring the LVCMOS buffers to output Hi-Z instead of driving high when transmitting logic 1.
For more information, see Inter-Integrated Circuit (I2C) Interface section in Peripherals chapter in the device
TRM.
8.4.5.19 I3C
The device contains three Improved Inter-Integrated Circuit (I3C) controllers each of which provides an interface
between a local host (LH), such as an Arm, and any I3C-bus-compatible device that connects via the I3C serial
bus.
For more information, see Improved Inter-Integrated Circuit (I3C) Interface section in Peripherals chapter in the
device TRM.
8.4.5.20 MCAN
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed
real-time control. CAN has high immunity to electrical interference. In a CAN network, many short messages are
broadcast to the entire network, which provides for data consistency in every node of the system.
The MCAN module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications. CAN
FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD devices
can coexist on the same network without any conflict.
For more information, see Modular Controller Area Network (MCAN) section in Peripherals chapter in the device
TRM.
8.4.5.21 MCASP
The MCASP functions as a general-purpose audio serial port are optimized to the requirements of various audio
applications. The MCASP module can operate in both transmit and receive modes. The MCASP is useful for
time-division multiplexed (TDM) stream, Inter-IC Sound (I2S) protocols reception and transmission as well as
for an inter-component digital audio interface transmission (DIT). The MCASP has the flexibility to gluelessly
connect to a Sony/Philips digital interface (S/PDIF) transmit physical layer component.
Although inter-component digital audio interface reception (DIR) mode (this is, S/PDIF stream receiving) is not
natively supported by the MCASP module, a specific TDM mode implementation for the MCASP receivers allows
an easy connection to external DIR components (for example, S/PDIF to I2S format converters).
For more information, see Multichannel Audio Serial Port (MCASP) section in Peripherals chapter in the device
TRM.
8.4.5.22 MCRC Controller
VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the
integrity of a memory system. A signature representing the contents of the memory is obtained when the
contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate
the signature for a set of data and then compare the calculated signature value against a predetermined good
signature value. MCRC controller provides four channels to perform CRC calculation on multiple memories in
parallel and can be used on any memory system. Channel 1 can also be put into data trace mode, where MCRC
controller compresses each data being read through CPU read data bus.
For more information, see MCRC Controller section in Interprocessor Communication chapter in the device
TRM.
8.4.5.23 MCSPI
The MCSPI module is a multichannel transmit/receive, master/slave synchronous serial bus.
There are total of eleven MCSPI modules in the device.
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the
device TRM.
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8.4.5.24 MMC/SD
The MMCSD Host Controller provides an interface to eMMC 5.1 (embedded MultiMedia Card), SD 4.10 (Secure
Digital), and SDIO 4.0 (Secure Digital IO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO
protocol at transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion,
and checking for syntactical correctness.
For more information, see Multimedia Card/Secure Digital (MMC/SD) Interface section in Peripherals chapter in
the device TRM.
8.4.5.25 OSPI
The Octal Serial Peripheral Interface (OSPI™) module is a kind of Serial Peripheral Interface (SPI) module
which allows single, dual, quad or octal read and write access to external flash devices.
The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a processor
wishing to execute code directly from external flash memory), or in an indirect mode where the module is set-up
to silently perform some requested operation, signaling its completion via interrupts or status registers.
For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device
TRM.
8.4.5.26 PCIE
The Peripheral Component Interconnect Express (PCIe) subsystem is built around a multi-lane dual-mode PCIe
controller that provides low pin-count, high reliability, and high-speed data transfers at rates of up to 8.0 Gbps
per lane for serial links on backplanes and printed wiring boards.
For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals
chapter in the device TRM.
8.4.5.27 SerDes
SerDes'es goal is to convert device (SoC) parallel data into serialized data that can be output over a highspeed
electrical interface. In the opposite direction, SerDes converts high-speed serial data into parallel data that can
be processed by the device. To this end, the SerDes contains a variety of functional blocks to handle both the
external analog interface as well as the internal digital logic.
For more information, see Serializer/Deserializer (SerDes) section in Peripherals chapter in the device TRM.
8.4.5.28 WWDT
The Windowed Watchdog Timer provides timer functionality for operating systems and for benchmarking code.
The module incorporates several counters, which define the timebases needed for scheduling in the operating
system. The module is implemented with an RTI module, but only WWDT is supported.
This module is specifically designed to fulfill the requirements for OSEK (“Offene Systeme und deren
Schnittstellen für die Elektronik im Kraftfahrzeug”; “Open Systems and the Corresponding Interfaces for
Automotive Electronics”) as well as OSEK/Time compliant operating systems.
For more information, see Real Time Interrupt (RTI) Module section in Peripherals chapter in the device TRM.
8.4.5.29 Timers
All timers include specific functions to generate accurate tick interrupts to the operating system.
Each timer can be clocked from several different independent clocks. The selection of clock source is made from
registers in the MCU_CTRL_MMR0/CTRL_MMR0.
In the MCU domain the device provides 10 timer pins to be used as MCU Timer Capture inputs or as MCU Timer
PWM outputs. In order to provide maximum flexibility, these 10 pins may be used with any of MCU_TIMER0
through MCU_TIMER9 instances. System level muxes are used to control the capture source pin for each
MCU_TIMER[9-0] and the MCU_TIMER[9-0] source for each MCU_TIMER_IO[1-0] PWM output.
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In the MAIN domain the device provides 8 timer pins to be used as Timer Capture inputs or as Timer PWM
outputs. For maximum flexibility, these 8 pins may be used with any of TIMER0 through TIMER19 instances.
System level muxes are used to control the capture source pin for each TIMER[19-0] and the TIMER[19-0]
source for each TIMER_IO[7-0] PWM output.
Each odd numbered timer instance from each of the domains may be optionally cascaded with the previous
even numbered timer instance from the same domain to form up to a 64-bit timer. For example, TIMER1 may be
cascaded to TIMER0, MCU_TIMER1 may be cascaded to MCU_TIMER0, etc.
When cascaded, TIMERi acts as a 32-bit prescaler to TIMERi+1, as well as MCU_TIMERn acts as a 32-bit
prescaler to MCU_TIMERn+1. TIMERi / MCU_TIMERn must be configured to generate a PWM output edge at
the desired rate to increment the TIMERi+1/ MCU_TIMERn+1 counter.
For more information, see Timers section in Peripherals chapter in the device TRM.
8.4.5.30 UART
The UART is a slave peripheral that utilizes the DMA for data transfer or interrupt polling via host CPU. There
are twelve UART modules in the device. All UART modules support IrDA and CIR modes when 48 MHz function
clock is used. Each UART can be used for configuration and data exchange with a number of external peripheral
devices or interprocessor communication between devices.
For more information, see Universal Synchronous/Asynchronous Receiver/Transmitter (UART) section in
Peripherals chapter in the device TRM.
8.4.5.31 USB
Similar to earlier versions of USB bus, USB 3.0 is a general-purpose cable bus, supporting data exchange
between a host device and a wide range of simultaneously accessible peripherals.
The device supports two identical USB subsystems:
•
USB3SS0 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with on-chip SS (USB3.0) PHY
and HS/FS/LS (1) (USB2.0) PHY
•
USB3SS1 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with on-chip SS (USB3.0) PHY
and HS/FS/LS (USB2.0) PHY
For more information, see Universal Serial Bus (USB) Subsystem section in Peripherals chapter in the device
TRM.
8.4.5.32 UFS
The Universal Flash Storage (UFS) interface is a standard-based serial interface engine.
There is one UFS module inside the device - UFS0. The UFS module includes one UFS 2.1 host controller (HC)
with an integrated M-PHY.
The UFS module complies with the standards as listed in Table 8-1.
Table 8-1. UFS Standards
DOCUMENT
JESD220-1A
JESD220-2
VERSION
DESCRIPTION
Universal Flash Storage (UFS) Unified Memory Extension
Universal Flash Storage (UFS) Card Extension
Universal Flash Storage (UFS)
v1.1
v1.0
JESD220C
v2.1, March 2016
v1.1A
JESD223-1B
Universal Flash Storage Host Controller Interface (UFSHCI) Unified Memory
Extension
JESD223C
JESD224
v2.1, March 2016
March 2013
Universal Flash Storage Host Controller Interface (UFSHCI)
Universal Flash Storage (UFS) Test
November, 2001
Federal Information Processing Standards (FIPS) 197 Advanced Encryption Standard
(AES)
v3.1, 2014
MIPI® Alliance Specification for M-PHY
v1.60, 2013
MIPI Alliance Specification for Unified Protocol (UniProSM)
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Table 8-1. UFS Standards (continued)
DOCUMENT
VERSION
DESCRIPTION
Revision 24, August 2010
Revision 27, October 2010
Small Computer System Interface (SCSI) Block Commands - 3
SCSI Primary Commands - 4
For more information, see Universal Flash Storage (UFS) Interface section in Peripherals chapter in the device
TRM.
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9 Applications and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Power Supply Mapping
This Jacinto 7TM processor device can be operated in several different modes of operation depending upon the
number of power resources, power supply groups (i.e. power rails) and control signals available:
•
•
•
•
•
Full Active
MCU Only low power mode
DDR Retention (Suspend-to-RAM or S2R) low power mode
MCU Island safety monitor
Extended MCU safety monitor
Two power distribution networks (PDNs) that support these different operational modes are recommended and
provide optional end product features. To name a few:
•
•
•
•
Dual Voltage (1.8V & 3.3V) IO Interfaces
Compliant UHS-I SD Card
Compliant USB2.0
High Security device type Efuse programming on-board for in-field updates
An Isolated PDN provides independent MCU & Main power resources & rails (see Table 9-2) to support power
rail Freedom From Interference (FFI) as desired to reach end product system functional safety targets. An
isolated PDN is needed to support MCU Only lower power mode or MCU Island safety monitoring. MCU ONLY
can significantly reduce device power by disabling all Main processing while only keeping MCU processor
resources active. A Combined PDN reduces total number of power resources & rails by grouping MCU & Main
supplies into common power rails (see Table 9-1). This PDN can be used for Extended MCU safety processing
but does not allow for MCU Island safety monitor or MCU Only low power modes. The DDR Retention low power
mode can be supported with either an Isolated or Combined PDN scheme.
The TPS6594x & LP8764x Power Management ICs (PMICs) are key power components in the two
recommended PDNs. Additional discrete power components may be added as desired to support optional
system features. TI has optimized recommended PDNs using these PMICs for the following reasons:
•
•
•
•
Full device performance entitlement as validated on TI Evalution boards
Enable all system functional safety features and analysis captured in device safety manual
Support power rail load steps, supply voltage accuracies and maximum load currents with margins
Meet device primary & low power mode supply sequencing requirements (refer to Section 7.10.2, Power
Supply Sequencing)
•
Provide Adaptive Voltage Scaling (AVS) Class 0 device requirements with TI validated software
For full PDN design and operational details, refer to either
1. “Dual TPS6594-Q1 PMIC User Guide for Jacinto 7TM DRA829 and TDA4VM Automotived PDN-0B
(SLVUC32)” for legacy designs aligned to original EVM PDN-0A wishing to minimize SCH & PCB updates
2. “Dual TPS6594-Q1 PMIC User Guide for Jacinto 7TM DRA829 and TDA4VM Automotived PDN-0C
(SLVUC99)" for all new designs
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#
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Table 9-1. Combined MCU and Main Voltage Domain Power Rail Mapping
DOMAIN
GROUPS
TYPES
VOLTAGE [V]
DOMAIN NAMES
POWER RAILS
(VDDSHV0_MCU,
VDDSHV1_MCU,
VDDSHV2_MCU,
VDDSHVn_MC
U,VDDSHVn,
VDDA_3P3_US
B4
Digital IO
3.3
VDDSHV0,VDDSHV1,
VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV53,
VDDSHV6)1, VDDA_3P3_USB4
VDD_IO_3V3
1
(VDDSHV0_MCU,
VDDSHV1_MCU,
VDDSHV2_MCU, VDDSHV0,
VDDSHV1, VDDSHV2,
VDDSHV, VDDSHV4,
VDDSHV53, VDDSHV6)2
VDDSHVn_MC
U2 VDDSHVn3 2
Digital IO
Digital IO
1.8
1.8
VDD_IO_1V8
2
3
VDDS_MMC06
VDDS_MMC06 VDDS_MMC0_1V86
(VDDA_1P8_CSIRX,
VDDA_1P8_USB,
VDDA_1P8_UFS,
VDDA_1P8_DP,
VDDA_1P8_DSITX,
VDDA_1P8_MLB,
VDDA_1P8_SERDES)
VDDA_1P8_<p
VDD_PHY_1V85
hy>5
Analog PHY
1.8
1.8
4
5
VDDA_MCU_PLLGRP0,
VDDA_MCU_TEMP,
VDDA_ADC_MCU,
VDDA_POR_WKUP,
VDDA_WKUP VDDS_OSC1,
VDDA_PLLGRP6:0,
VDDA_TEMP3:0
Analog Clk,
Meas
VDDA_1P8_<cl
VDA_LN_1V8
k/meas>
VDDA_0P8_PLL_MLB,
VDDA_0P8_PLL_DDR,
VDDA_0P8_DLL_MMC0
Analog, low
voltage
VDDA_0P8_DP
VDA_DPLL_0V8
LL
0.80
6
7
Digital, AVS low
voltage
0.77 – 0.84
VDD_CPU
VDD_CPU
VDD_CPU_AVS
VDD_MCU7, VDD_CORE,
(VDDA_0P8_SERDES,
VDDA_0P8_SERDES_C,
VDDA_0P8_DP,
VDD_MCU
VDD_CORE
VDDA_0P8_<p
hy>8
Digital, low
voltage
VDDA_0P8_DP_C,
VDDA_0P8_DSITX,
VDDA_0P8_DSITX_C,
VDDA_0P8_CSIRX,
VDDA_0P8_UFS,
0.80
VDD_PROC_0V8
8
VDDA_0P8_USB) 8
VDDAR_MCU,
Digital, low
voltage
0.85
1.1
VDDAR
VDD_RAM_0V85
VDD_DDR_1V1
9
VDDAR_CORE,
VDDAR_CPU
VDDS_DDR_BIAS,
VDDS_DDR,
VDDS_DDR_C
Digital, low
voltage
VDDS_DDR
10
1. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to
support 3.3V digital interfaces
2. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to
support 1.8V digital interfaces
3. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3/1.8V) power rail is required
for compliant, high-speed SD card operations. If SD card is not needed or standard data rates with fixed
3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a SD card is
capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail.
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4. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise,
analog supply is recommended to provide best signal integrity for USB data eye mask compliance. If USB
interface is not needed or data bit errors can be tolerated, then domain can be grouped with 3.3V digital IO
power rail either directly or through a supply filter.
5. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog
supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of
these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains
can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed.
6. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface. If MMC0 or eMMC0
interface is not needed, then domain can be grouped with digital IO 1.8V power rail. However, if MMC0
interface is needed, then VDD_MMC0 must not start ramp-up until VDD_CORE has reached Vopr min.
7. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility,
enabling it to be grouped and ramped-up with either 0.8V VDD_CORE or 0.85V RAM array domains
(VDDAR_xxx).
8. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry
needing a low noise supply for optimal performance.
Table 9-2. Isolated MCU and Main Voltage Domain Power Rail Mapping
DOMAIN
GROUPS
TYPES
VOLTAGE [V]
DOMAIN NAMES
POWER RAILS
#
(VDDSHV0_MCU,
VDDSHV1_MCU,
VDDSHV2_MCU)1
VDDSHVn_MC
U
Digital IO
3.3
VDD_MCUIO_3V3
1
(VDDSHV0, VDDSHV1,
VDDSHV2, VDDSHV3,
VDDSHVn,
VDDA_3P3_US
B4
Digital IO
Digital IO
3.3
1.8
VDD_IO_3V3
VDD_MCUIO_1V8
VDD_IO_1V8
2
3
VDDSHV4, VDDSHV53,
VDDSHV6)1, VDDA_3P3_USB4
(VDDSHV0_MCU,
VDDSHV1_MCU,
VDDSHV2_MCU)2
VDDSHVn_MC
U2
(VDDSHV0, VDDSHV1,
VDDSHV2, VDDSHV3,
VDDSHV4, VDDSHV53,
VDDSHV6)2
Digital IO
Digital IO
1.8
1.8
VDDSHVn2 3
4
5
VDDS_MMC06
VDDS_MMC06 VDDS_MMC0_1V86
VDDA_MCU_PLLGRP0,
VDDA_MCU_TEMP,
VDDA_ADC_MCU,
VDDA_POR_WKUP,
VDDA_WKUP
Analog Clk,
Meas
VDDA_MCU1P
VDA_MCU_1V8
8_<clk/meas>
1.8
1.8
6
7
VDDS_OSC1,
VDDA_PLLGRP6:0,
VDDA_TEMP3:0
Analog Clk,
Meas
VDDA_1P8_<cl
VDA_DPLL_1V8
k/meas>
(VDDA_1P8_CSIRX,
VDDA_1P8_USB,
VDDA_1P8_UFS,
VDDA_1P8_DP,
VDDA_1P8_DSITX,
VDDA_1P8_MLB,
VDDA_1P8_SERDES)5
VDDA_1P8_<p
VDA_PHY_1V85
hy>5
Analog PHY
1.8
8
9
VDDA_0P8_PLL_MLB,
VDDA_0P8_PLL_DDR,
VDDA_0P8_DLL_MMC0
Analog, low
voltage
VDDA_0P8_DP
VDA_DPLL_0V8
LL
0.80
Digital, low
voltage
VDD_MCU,
0.80
VDD_MCU, VDDAR_MCU
vdd_cpu
VDD_MCU_0V85
VDDAR_MCU
10
11
Digital, AVS low
voltage
0.77 – 0.84
VDD_CPU
VDD_CPU_AVS
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Table 9-2. Isolated MCU and Main Voltage Domain Power Rail Mapping (continued)
DOMAIN
GROUPS
TYPES
VOLTAGE [V]
DOMAIN NAMES
POWER RAILS
#
Digital, low
voltage
0.80
VDD_CORE,
(VDDA_0P8_SERDES,
VDDA_0P8_SERDES_C,
VDDA_0P8_DP,
VDD_CORE,
VDDA_0P8_<p
hy>8
VDD_CORE_0V8
12
VDDA_0P8_DP_C,
VDDA_0P8_DSITX,
VDDA_0P8_DSITX_C,
VDDA_0P8_CSIRX,
VDDA_0P8_UFS,
VDDA_0P8_USB)8
Digital, low
voltage
0.85
1.1
VDDAR_CORE, VDDAR_CPU
VDDAR
VDD_RAM_0V85
VDD_DDR_1V1
13
14
Digital, low
voltage
VDDS_DDR_BIAS,VDDS_DDR,
VDDS_DDR_C
VDDS_DDR
1. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to
support 3.3V digital interfaces
2. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to
support 1.8V digital interfaces
3. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3/1.8V) power rail is required
for compliant, high-speed SD card operations. If SD card is not needed or standard data rates with fixed
3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a SD card is
capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail.
4. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise,
analog supply is recommended to provide best signal integrity for USB data eye mask compliance. If USB
interface is not needed or data bit errors can be tolerated, then domain can be grouped with 3.3V digital IO
power rail either directly or through a supply filter.
5. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog
supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of
these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains
can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed.
6. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface. If MMC0 or eMMC0
interface is not needed, then domain can be grouped with digital IO 1.8V power rail. However, if MMC0
interface is needed, then VDD_MMC0 must not start ramp-up until VDD_CORE has reached VOPR MIN
.
7. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility,
enabling it to be grouped and ramped-up with either 0.8V VDD_CORE or 0.85V RAM array domains
(VDDAR_xxx).
8. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry
needing a low noise supply for optimal performance.
9.2 Device Connection and Layout Fundamentals
9.2.1 Power Supply Decoupling and Bulk Capacitors
9.2.1.1 Power Distribution Network Implementation Guidance
The Jacinto 7 Processor Power Distribution Networks: Implementation and Analysis (SPRACN5) provides
guidance for successful implementation of the power distribution network. This includes PCB stackup guidance
as well as guidance for optimizing the selection and placement of the decoupling capacitors. TI supports only
designs that follow the board design guidelines contained in the application report.
9.2.2 External Oscillator
For more information, see Section 7.10.4.1, Input and output Clocks/Oscillators.
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9.2.3 JTAG and EMU
Texas Instruments supports a variety of eXtended Development System (XDS) JTAG controllers with various
debug capabilities beyond only JTAG support. A summary of this information is available in the XDS Target
Connection Guide.
For more recommendations on EMU routing, see Emulation and Trace Headers Technical Reference Manual
9.2.4 Reset
The device incorporates four external reset pins (MCU_PORz, MCU_RESETz, PORz, and RESET_REQz) and
four reset status pins (MCU_PORz_OUT, MCU_RESETSTATz, PORz_OUT, and RESETSTATz). These pins can
be driven by an external power good circuitry or Power Management IC (PMIC). MCU_PORz and Main PORz
pins should be held active low during the entire power-up phase, and until all power supplies as well as the
HFOSC0 clock are stable.
All MCU domain resets act as master resets to the whole device, whereas Main domain resets only reset Main
domain (MCU domain is reset isolated from all Main domain resets).
9.2.5 Unused Pins
For more information about Unused Pins, see Connections for Unused Pins
9.2.6 Hardware Design Guide for JacintoTM 7 Devices
The Hardware Design Guide for JacintoTM 7 Devices document describes hardware system design
considerations for the JacintoTM 7 family of processors.This design guide is intended to be used as an aid
during the development of application hardware.
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9.3 Peripheral- and Interface-Specific Design Information
9.3.1 LPDDR4 Board Design and Layout Guidelines
The goal of the Jacinto 7 LPDDR4 Board Design and Layout Guidelines is to make the LPDDR4 system
implementation straightforward for all designers. Requirements have been distilled down to a set of layout and
routing rules that allow designers to successfully implement a robust design for the topologies that TI supports.
TI only supports board designs using LPDDR4 memories that follow the guidelines in this document.
9.3.2 OSPI and QSPI Board Design and Layout Guidelines
The following section details the routing guidelines that must be observed when routing the OSPI and QSPI
interfaces.
9.3.2.1 No Loopback and Internal Pad Loopback
•
•
The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
The signal propagation delay from the MCU_OSPI[x]_CLK signal to the flash device must be < 450 ps (~7cm
as stripline or ~8cm as microstrip)
•
•
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 9-1
Propagation delays and matching:
– A to B < 450 ps
– Matching skew: < 60 ps
A
B
R1
0 Ω*
OSPI/QSPI/SPI
device clock input
MCU_OSPI[x]_CLK
MCU_OSPI[x]_D[y],
MCU_OSPI[x]_CSn[z]
OSPI/QSPI/SPI
device IOy, CS#
OSPI_Board_01
* 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed.
Figure 9-1. OSPI Interface High Level Schematic
9.3.2.2 External Board Loopback
•
•
•
The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
The MCU_OSPI[x]_LBCLKO output signal must be looped back into the MCU_OSPI[x]_DQS input
The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B)
should be approximately equal to half of the signal propagation delay from the MCU_OPSI[x]_LBCLKO pin to
the MCU_OSPI[x]_DQS pin ((C to D)/2). See the note below.
•
The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B) must
be approximately equal to the signal propagation delay of the control and data signals between the flash
device and the SoC device (E to F, or F to E)
•
•
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 9-2
Propagation delays and matching:
– A to B = E to F = (C to D) / 2
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– Matching skew: < 60 ps
Note
The OSPI Board Loopback Hold time requirement (described in Section 7.10.5.21, OSPI) is larger
than the Hold time provided by a typical flash device. Therefore, the length of MCU_OPSI[x]_LBCLKO
pin to the MCU_OSPI[x]_DQS pin (C to D) can be shortened to compensate.
A
B
R1
0 Ω*
OSPI/QSPI/SPI
device clock input
MCU_OSPI[x]_CLK
C
R1
0 Ω*
MCU_OSPI[x]_LBCLKO
D
MCU_OSPI[x]_DQS
E
F
MCU_OSPI[x]_D[y],
MCU_OSPI[x]_CSn[z]
OSPI/QSPI/SPI
device IOy, CS#
OSPI_Board_02
* 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK and MCU_OSPI[x]_LBCLKO pins, is a placeholder for fine
tuning, if needed.
Figure 9-2. OSPI Interface High Level Schematic
9.3.2.3 DQS (only available in Octal Flash devices)
•
•
•
The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
The DQS pin of the flash devices must be connected to MCU_OSPI[x]_DQS signal
The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B)
should be approximately equal to the signal propagation delay from the MCU_OSPI[x]_DQS pin to the DQS
output pin (C to D)
•
•
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 9-3
Propagation delays and matching:
– A to B = C to D
– Matching skew: < 60 ps
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A
B
R1
0 Ω*
OSPI/QSPI/SPI
device clock input
MCU_OSPI[x]_CLK
C
D
OSPI device DQS
MCU_OSPI[x]_DQS
E
F
MCU_OSPI[x]_D[y],
MCU_OSPI[x]_CSn[z]
OSPI/QSPI/SPI
device IOy, CS#
J7ES_OSPI_Board_03
* 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is a placeholder for fine tuning, if needed.
Figure 9-3. OSPI Interface High Level Schematic
9.3.3 SERDES REFCLK Design Guidelines
The following section details the routing guidelines that must be observed when terminating the SERDES
REFCLK and is applicable only when SERDES REFCLK is configured to input mode.
1. 50 Ω to GND is recommended on each leg.
2. Internal AC coupling is always enabled, so external biasing is not needed.
9.3.4 USB VBUS Design Guidelines
The USB 3.1 specification allows the VBUS voltage to be as high as 5.5 V for normal operation, and as high as
20 V when the Power Delivery addendum is supported. Some applications require a max voltage to be 30 V.
The device requires the VBUS signal voltage be scaled down using an external resistor divider (as shown in the
Figure 9-4), which limits the voltage applied to the actual device pin (USB0_VBUS, USB1_VBUS). The tolerance
of these external resistors should be equal to or less than 1%, and the leakage current of zener diode at 5 V
should be less than 100 nA.
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Device
USBn_VBUS
16.6 kΩ
1%
3.4 kΩ
1%
VBUS signal
10 kΩ
1%
6.8V
(BZX84C6V8 or equivalent)
VSS
VSS
J7ES_USB_VBUS_01
A. USBn_VBUS, where n = 0 or 1.
Figure 9-4. USB VBUS Detect Voltage Divider / Clamp Circuit
The USB0_VBUS and USB1_VBUS pins can be considered to be fail-safe because the external circuit in Figure
9-4 limits the input current to the actual device pin in a case where VBUS is applied while the device is powered
off.
9.3.5 System Power Supply Monitor Design Guidelines
The VMON_ER_VSYS pin provides a way to monitor a system power supply. This system power supply is
typically a single pre-regulated power source for the entire system. This supply is monitored by comparing
the output of an external voltage divider circuit sourced by this supply with an internal voltage reference, with
a power fail event being triggered when the voltage applied to VMON_ER_VSYS drops below the internal
reference voltage. The actual system power supply voltage trip point is determined by the system designer when
selecting component values used to implement the external resistor voltage divider circuit. When designing the
resistor divider circuit it is important to understand various factors which contribute to variability in the system
power supply monitor trip point. The first thing to consider is the initial accuracy of the VMON_ER_VSYS input
threshold which has a nominal value of 0.45 V, with a variation of ±3%. Precision 1% resistors with similar
thermal coefficient are recommended for implementing the resistor voltage divider. This minimizes variability
contributed by resistor value tolerances. Input leakage current associated with VMON_ER_VSYS must also be
considered since any current flowing into the pin creates a loading error on the voltage divider output. The
VMON_ER_VSYS input leakage current may be in the range of 10 nA to 2.5 μA when applying 0.45 V.
Note
The resistor voltage divider shall be designed such that its output voltage never exceeds themaximum
value defined in Section 7.4 , Recommended Operating Conditions during normal operating
conditions.
Figure 9-5 presents an example, where the system power supply is nominally 5 V and the maximum trigger
threshold is 5 V - 10%, or 4.5 V.
For this example, it is important to understand which variables effect the maximum trigger threshold when
selecting resistor values. It is obvious a device which has a VMON_ER_VSYS input threshold of 0.45 V + 3%
needs to be considered when trying to design a voltage divider that doesn’t trip until the system supply drops
10%. The effect of resistor tolerance and input leakage also needs to be considered, but how these contributions
effect the maximum trigger point may not be obvious. When selecting component values which produce a
maximum trigger voltage, the system designer must consider a condition where the value of R1 is 1% low and
the value of R2 is 1% high combined with a condition where input leakage current for the VMON_ER_VSYS pin
is 2.5 μA. When implementing a resistor divider where R1 = 4.81 KΩ and R2 = 40.2 KΩ, the result is a maximum
trigger threshold of 4.523 V.
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Once component values have been selected to satisfy the maximum trigger voltage as described above, the
system designer can determine the minimum trigger voltage by calculating the applied voltage that produces an
output voltage of 0.45 V - 3% when the value of R1 is 1% high and the value of R2 is 1% low, and the input
leakage current is 10 nA, or zero. Using an input leakage of zero with the resistor values given above, the result
is a minimum trigger threshold of 4.008 V.
This example demonstrates a system power supply voltage trip point that ranges from 4.008 V to 4.523 V.
Approximately 250 mV of this range is introduced by VMON_ER_VSYS input threshold accuracy of ±3%,
approximately 150 mV of this range is introduced by resistor tolerance of ±1%, and approximately 100 mV of this
range is introduced by loading error when VMON_ER_VSYS input leakage current is 2.5 μA.
The resistor values selected in this example produces approximately 100 μA of bias current through the resistor
divider when the system supply is 4.5 V. The 100 mV of loading error mentioned above could be reduced to
about 10 mV by increasing the bias current through the resistor divider to approximately 1 mA. So resistor
divider bias current vs loading error is something the system designer needs to consider when selecting
component values.
The system designer should also consider implementing a noise filter on the voltage divider output since
VMON_ER_VSYS has minimum hysteresis and a high-bandwidth response to transients. This could be done
by installing a capacitor across R1 as shown in Figure 9-5. However, the system designer must determine the
response time of this filter based on system supply noise and expected response to transient events.
Figure 9-5 presents an example, when the system power supply voltage is nominally 5 V and the desired trigger
threshold is -10% or 4.5 V.
Device
VMON_VSYS
R2
VSYS
40.2 kΩ 1%
C1
Value = Determined by system designer
(System Power Supply)
4.81 kΩ
1%
R1
VSS
SPRSP56_VMON_ER_MON_01
Figure 9-5. System Supply Monitor Voltage Divider Circuit
9.3.6 High Speed Differential Signal Routing Guidance
The High Speed Interface Layout Guidelines provides guidance for successful routing of the high speed
differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and
spacing limits. TI supports only designs that follow the board design guidelines contained in the application
report.
9.3.7 Thermal Solution Guidance
The Thermal Design Guide for DSP and ARM Application Processors provides guidance for successful
implementation of a thermal solution for system designs containing this device. This document provides
background information on common terms and methods related to thermal solutions. TI only supports designs
that follow system design guidelines contained in the application report.
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, DRA829). Texas Instruments recommends two of three possible prefix designators for its support
tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
P
Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
null Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
For orderable part numbers of DRA829 devices in the ALF package type, see the Package Option Addendum of
this document, the TI website (ti.com), or contact your TI sales representative.
10.1.1 Standard Package Symbolization
Note
Some devices may have a cosmetic circular marking visible on the top of the device package which
results from the production test process. In addition, some devices may also show a color variation in
the package substrate which results from the substrate manufacturer. These differences are cosmetic
only with no reliability impact.
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xBBBBBBBBzYrPPPcQ1
PIN ONE INDICATOR
XXXXXXX
ZZZ
G1
YYY
O
J7ES_SPRSP35_PACK_01
Figure 10-1. Printed Device Reference
10.1.2 Device Naming Convention
Table 10-1. Nomenclature Description
VALUES
FIELD
PARAMETER
FIELD
DESCRIPTION
DESCRIPTION
MARKING
ORDERABLE
x
Device evolution stage
X
P
Prototype
Preproduction (production test flow, no reliability data)
Production
BLANK
BBBBBBBB(1) Base production part
number
DRA829VM
See Table 5-1, Device Comparison
See Table 5-1, Device Comparison
See Table 7-1, Speed Grade Maximum Frequency)
Alternate speed grade
DRA829JM
z
Device Speed
T
OTHER
Y
Device Type
G
C
0
General purpose (Prototype and Production)
General purpose, R5F Lockstep capable
High Security capable
5
High Security capable, R5F Lockstep capable
High Security Prime capable, R5F Lockstep capable
R
High Security capable, R5F Lockstep capable,
Customer Dev Keys
D
P
High Security Prime capable, R5F Lockstep capable,
Customer Dev Keys
r
Device revision
A or BLANK
SR 1.0
B
SR 1.1
PPP
c
Package Designator
Carrier Designator
ALF
ALF FCBGA-N827 (24 mm × 24 mm) Package
N/A
N/A
BLANK
Tray
R
Tape and Reel
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Table 10-1. Nomenclature Description (continued)
VALUES
FIELD
PARAMETER
FIELD
DESCRIPTION
DESCRIPTION
MARKING ORDERABLE
Q1
Automotive Designator
Not automotive qualified.
Supports TJ = –40°C to 105°C
BLANK
Q1
Meet AEC-Q100 qualification requirements, with
exceptions as specified in this document (data sheet).
Supports TJ = –40°C to 125°C
XXXXXXX
YYY
ZZZ
Lot Trace Code
Production Code
Production Code
Pin One
As Marked
N/A
N/A
N/A
N/A
N/A
Lot Trace Code (LTC)
As Marked
As Marked
As Marked
As Marked
Production Code, for TI use only
Production Code, for TI use only
Pin one designator
O
G1
ECAT
ECAT—Green package designator
(1) Software should constrain the features used to match the intended production device.
Note
BLANK in the symbol or part number is collapsed so there are no gaps between characters.
10.2 Tools and Software
The following products support development for DRA829 platforms:
Development Tools
Clock Tree Tool for Sitara, Jacinto, Vision Analytics, and Digital Signal Processors The Clock Tree
Tool (CTT) for Sitara™ Arm®, Jacinto, and Digital Signal Processors is an interactive clock tree configuration
software that provides information about the clocks and modules in these TI devices. It allows the user to:
•
•
•
•
Visualize the device clock tree
Interact with clock tree elements and view the effect on PRCM registers
Interact with the PRCM registers and view the effect on the device clock tree
View a trace of all the device registers affected by the user interaction with clock tree
Code Composer Studio™ Integrated Development Environment Code Composer Studio (CCS) Integrated
Development Environment (IDE) is a development environment that supports TI's Microcontroller and Embedded
Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded
applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger,
profiler, and many other features. The intuitive IDE provides a single user interface taking you through each
step of the application development flow. Familiar tools and interfaces allow users to get started faster than ever
before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced
embedded debug capabilities from TI resulting in a compelling feature-rich development environment for
embedded developers.
Pin mux tool The Pin MUX Utility is a software tool which provides a Graphical User Interface for configuring
pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs. Results are
output as C header/code files that can be imported into software development kits (SDKs) or used to configure
customer's custom software. Version 4 of the Pin Mux utility adds the capability of automatically selecting a mux
configuration that satisfies the entered requirements.
Power Estimation Tool (PET) Power Estimation Tool (PET) provides users the ability to gain insight in to
the power consumption of select TI processors. The tool includes the ability for the user to choose multiple
application scenarios and understand the power consumption as well as how advanced power saving techniques
can be applied to further reduce overall power consumption.
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments
website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized
distributor.
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10.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
The following documents describe the DRA829 devices.
Technical Reference Manual
J721E DRA829/TDA4VM/AM752x Processors Silicon Revision 1.0 Technical Reference Manual Details the
integration, the environment, the functional description, and the programming models for each peripheral and
subsystem in the DRA829 family of devices.
Errata
J721E DRA829/TDA4VM/AM752x Processors Silicon Revision 1.0 Silicon Errata Describes the known
exceptions to the functional specifications for the device.
10.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.5 Trademarks
eMMC™ is a trademark of MultiMediaCard Association.
Jacinto™ and Code Composer Studio™ are trademarks of TI.
HyperBus™ is a trademark of Mobiveil Inc.
CoreSight™ is a trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
TI E2E™ is a trademark of Texas Instruments.
Arm®, Cortex®, are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
PowerVR® is a registered trademark of Imagination Technologies Limited.
PCI-Express® and PCIe® are registered trademarks of PCI-SIG.
Secure Digital® is a registered trademark of SD Card Association.
MIPI® is a registered trademark of MIPI Alliance, Inc.
All trademarks are the property of their respective owners.
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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11 Mechanical, Packaging, and Orderable Information
11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
250
250
250
(1)
(2)
(3)
(4/5)
(6)
DRA829JMTGBALFR
DRA829JMTGBALFRQ1
DRA829VMTGBALFR
ACTIVE
FCBGA
FCBGA
FCBGA
ALF
827
827
827
RoHS & Green
RoHS & Green
RoHS & Green
Call TI
Level-3-250C-168 HR
Level-3-250C-168 HR
Level-3-250C-168 HR
-40 to 105
-40 to 125
-40 to 105
DRA829JMTGBALF
942
ACTIVE
ACTIVE
ALF
Call TI
Call TI
DRA829JMTGBALFQ1
942
ALF
DRA829VMTGBALF
942
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Nov-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DRA829J, DRA829J-Q1 :
Catalog : DRA829J
•
Automotive : DRA829J-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE OUTLINE
ALF0827A
FCBGA - 2.8 mm max height
SCALE 0.650
PLASTIC BALL GRID ARRAY
24.1
23.9
A
B
BALL A1 CORNER
(
20)
24.1
23.9
(
18)
2.8 MAX
C
SEATING PLANE
0.15 C
0.5
0.3
BALL TYP
TYP
22.4 TYP
SYMM
(0.8) TYP
AJ
AH
AG
AE
AC
AA
W
U
(0.8) TYP
AF
AD
AB
Y
V
SYMM
T
R
22.4
TYP
P
N
M
K
L
J
H
G
835X 0.45-0.55
F
E
0.15
0.08
C A B
C
D
C
B
A
5
7
9
13 15 17 19 21 23 25 27 29
1
3
11
0.8 TYP
BALL A1 CORNER
16 18
20 22 24 26
2
4
6
8
10 12 14
28
0.8 TYP
4224732/B 02/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Pb-Free die bump and Pb-Free solder ball.
www.ti.com
EXAMPLE BOARD LAYOUT
ALF0827A
(0.8) TYP
FCBGA - 2.8 mm max height
PLASTIC BALL GRID ARRAY
SYMM
827X ( 0.4)
A
B
C
D
(0.8) TYP
E
F
G
H
J
K
L
M
N
P
SYMM
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
9
10
16 17
19 20 21 22
27
29
28
2
3
(
4
6
7
8
11 12
14 15
18
23
25 26
24
1
5
13
LAND PATTERN EXAMPLE
SCALE:5X
0.07 MAX
0.07 MIN
METAL UNDER
SOLDER MASK
0.4)
METAL
(
0.4)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4224732/B 02/2019
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
ALF0827A
FCBGA - 2.8 mm max height
PLASTIC BALL GRID ARRAY
SYMM
(0.8) TYP
827X ( 0.4)
A
B
C
D
(0.8)
TYP
E
F
G
H
J
K
L
M
N
P
SYMM
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
1
2
3
4
5
7
8
11 12 13 14 15 16
18
21 22 23 24 25
27 28 29
26
6
9
10
17
19 20
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:5X
4224732/B 02/2019
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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