DRV120_15 [TI]
Power-Saving Current Controlled Solenoid Driver;
| 型号： | DRV120_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Power-Saving Current Controlled Solenoid Driver |
| 文件： | 总16页 (文件大小：659K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV120
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SLVSBG3A –JUNE 2012–REVISED AUGUST 2012
POWER SAVING CURRENT CONTROLLED SOLENOID DRIVER
Check for Samples: DRV120
1
FEATURES
•
Integrated MOSFET With PWM to Control
Solenoid Current
•
Protection
–
–
–
–
Thermal Shutdown
–
Integrated Sense Resistor for Regulating
Solenoid Current
Under Voltage Lockout (UVLO)
Maximum Ramp Time
•
•
•
Fast Ramp-Up of Solenoid Current to
Guarantee Activation
Optional STATUS Output
•
•
Operating Temperature Range: -40ºC to 105ºC
8-Pin and 14-Pin TSSOP Package Options
Solenoid Current is Reduced in Hold Mode for
Lower Power and Thermal Dissipation
Peak Current, Keep Time at Peak Current, Hold
Current and PWM Clock Frequency Can Be Set
Externally. They Can Also Be Operated at
Nominal Values Without External Components.
APPLICATIONS
•
Electromechanical Driver: Solenoids, Valves,
Relays
•
White Goods, Solar, Transportation
•
Internal Supply Voltage Regulation
–
Up to 28-V External Supply
DESCRIPTION
The DRV120 is a PWM current driver for solenoids. It is designed to regulate the current with a well controlled
waveform to guarantee activation and to reduce power dissipation at the same time. The solenoid current is
ramped up fast to ensure opening of the valve or relay. After the initial ramping, solenoid current is kept at peak
value to ensure the correct operation, after which it is reduced to a lower hold level in order to avoid thermal
problems and reduce power dissipation.
The peak current duration is set with an external capacitor. The current ramp peak and hold levels, as well as
PWM frequency can independently be set with external resistors. External setting resistors can also be omitted, if
the default values for the corresponding parameters are suitable for the application.
DRV120 can operate from external 6-V to 28-V supply.
ORDERING INFORMATION(1)
ORDERABLE PART
NUMBER
TOP-SIDE
MARKING
PACKAGE(2)
(TSSOP-8) - PW
(TSSOP-14) - PW
Reel of 2000
Reel of 2000
DRV120PWR
120
DRV120APWR
120A
(1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DRV120
SLVSBG3A –JUNE 2012–REVISED AUGUST 2012
www.ti.com
TYPICAL APPLICATION
Figure 1. Default Configuration With 8-Pin TSSOP Option
Figure 2. External Parameter Setting for 14-Pin TSSOP Option
2
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SLVSBG3A –JUNE 2012–REVISED AUGUST 2012
DEVICE INFORMATION
Functional Block Diagram
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SLVSBG3A –JUNE 2012–REVISED AUGUST 2012
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Table 1. TERMINAL FUNCTIONS
PIN
NAME
PIN
(14-PIN PW)
DESCRIPTION
(8-PIN PW)(1)
NC
6
1
2
-
1, 6, 9, 10, 14
No connect
KEEP
PEAK
HOLD
OSC
VIN
2
3
Keep time set
Peak current set
Hold current set
PWM frequency set
6-V to 28-V supply
Ground
4
3
4
5
7
-
5
7
GND
OUT
STATUS
EN
8
11
12
13
Controlled current sink
Open drain fault indicator
Enable
8
(1) In the 8-pin package, the HOLD pin is not bonded out. For this package, the HOLD mode is configured to default (internal) settings.
xxx
xxx
PW PACKAGE
8-PIN
(TOP VIEW)
PW PACKAGE
14-PIN
(TOP VIEW)
KEEP
PEAK
OSC
VIN
EN
1
2
3
4
8
7
6
5
NC
KEEP
PEAK
HOLD
OSC
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
NC
OUT
NC
EN
STATUS
OUT
NC
GND
NC
VIN
8
GND
4
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SLVSBG3A –JUNE 2012–REVISED AUGUST 2012
ABSOLUTE MAXIMUM RATINGS(1)(2)
VALUE
–0.3 to 28
–0.3 to 7
–0.3 to 28
2000
UNIT
VIN
Input voltage range
V
V
V
Voltage range on EN, STATUS, PEAK, HOLD, OSC, SENSE, RAMP
Voltage range on OUT
HBM (human body model)
ESD rating
V
CDM (charged device model)
500
TJ
Operating virtual junction temperature range
Storage temperature range
–40 to 125
–65 to 150
°C
°C
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
125
26
UNIT
mA
V
IOUT
VIN
CIN
L
Average solenoid DC current
Supply voltage
6
1
12
4.7
1
Input capacitor
µF
H
Solenoid inductance
Operating ambient temperature
TA
-40
105
°C
THERMAL INFORMATION
DRV120
PW
DRV120
THERMAL METRIC
PW
14 PINS
122.6
51.2
UNITS
8 PINS
183.8
69.2
θJA
Junction-to-ambient thermal resistance(1)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance(3)
Junction-to-top characterization parameter(4)
Junction-to-board characterization parameter(5)
Junction-to-case (bottom) thermal resistance(6)
θJCtop
θJB
112.6
10.4
64.3
°C/W
ψJT
6.5
ψJB
110.9
N/A
63.7
θJCbot
N/A
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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SLVSBG3A –JUNE 2012–REVISED AUGUST 2012
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ELECTRICAL CHARACTERISTICS
VIN = 14 V, TA = -40°C to 105°C, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
Standby current
EN = 0, VIN = 14 V
100
300
150
400
IQ
µA
Quiescent current
EN = 1, VIN = 14 V
CURRENT DRIVER
ROUT
fPWM
DMAX
DMIN
OUT to GND resistance
IOUT = 200 mA
OSC = GND
1.7
20
2.5
25
Ω
kHz
%
PWM frequency
15
Maximum PWM duty cycle
Minimum PWM duty cycle
100
9
%
Delay between EN going high until driver
enabled(1), fPWM = 20 kHz
tD
Start-up delay
25
50
µs
CURRENT CONTROLLER, INTERNAL SETTINGS
IPEAK
IHOLD
Peak current
Hold current
PEAK = GND
HOLD = GND
160
40
200
50
240
60
mA
mA
CURRENT CONTROLLER, EXTERNAL SETTINGS
Externally set keep time at peak
current
(2)
tKEEP
CKEEP = 1 µF
75
ms
RPEAK = 50 kΩ
RPEAK = 200 kΩ
RHOLD = 50 kΩ
RHOLD = 200 kΩ
ROSC = 50 kΩ
ROSC = 200 kΩ
250
83
IPEAK
IHOLD
fPWM
Externally set peak current
Externally set hold current
Externally set PWM frequency
mA
100
33
mA
60
kHz
20
LOGIC INPUT LEVELS (EN)
VIL
Input low level
1.3
V
V
VIH
REN
Input high level
1.65
350
Input pull-up resistance
500
kΩ
LOGIC OUTPUT LEVELS (STATUS)
VOL
IIL
Output low level
Pull-down activated, ISTATUS = 2 mA
0.3
1
V
Output leakage current
Pull-down deactivated, V(STATUS) = 5 V
µA
UNDERVOLTAGE LOCKOUT
VUVLO
Undervoltage lockout threshold
4.6
V
THERMAL SHUTDOWN
Junction temperature shutdown
threshold
TTSD
TTSU
160
140
°C
°C
Junction temperature startup
threshold
(1) Logic HIGH between 4 V and 7 V. Note: absolute max voltage rating is 7 V.
(2) Either internal or external tKEEP time setting is selected to be activated during manufacturing of production version of DRV120.
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SLVSBG3A –JUNE 2012–REVISED AUGUST 2012
FUNCTIONAL DESCRIPTION
DRV120 controls the current through the solenoid as shown in Figure 3. Activation starts when EN pin voltage is
pulled high either by an external driver or internal pull-up. In the beginning of activation, DRV120 allows the load
current to ramp up to the peak value IPEAK and it regulates it at the peak value for the time, tKEEP, before reducing
it to IHOLD. The load current is regulated at the hold value as long as the EN pin is kept high. The initial current
ramp-up time depends on the inductance and resistance of the solenoid. Once EN pin is driven to GND, DRV120
allows the solenoid current to decay to zero.
ISOLENOID
IPEAK
IHOLD
t
tKEEP
EN
t
Figure 3. Typical Current Waveform Through the Solenoid
tKEEP is set externally by connecting a capacitor to the KEEP pin. A constant current is sourced from the KEEP
pin that is driven into an external capacitor resulting in a linear voltage ramp. When the KEEP pin voltage
reaches 75 mV, the current regulation reference voltage, VREF, is switched from VPEAK to VHOLD. Dependency of
tKEEP from the external capacitor size can be calculated by:
s
3 é ù
t
s = C F ×75 ×10
KEEP é ù KEEP é ù
ë û ë û
ê ú
F
ë û
(1)
The current control loop regulates, cycle-by-cycle, the solenoid current by using an internal current sensing
resistor and MOSFET switch. During the ON-cycle, current flows from OUT pin to GND pin through the internal
switch as long as voltage over current sensing resistor is less than VREF. As soon as the current sensing voltage
is above VREF, the internal switch is immediately turned off until the next ON-cycle is triggered by the internal
PWM clock signal. In the beginning of each ON-cycle, the internal switch is turned on and stays on for at least
the time determined by the minimum PWM signal duty cycle, DMIN
.
IPEAK and IHOLD depend on fixed resistance values RPEAK and RHOLD as shown in Figure 4. If the PEAK pin is
connected to ground or if RPEAK is below 33.33 kΩ (typ value), then IPEAK is at its default value (internal setting).
The IPEAK value can alternatively be set by connecting an external resistor to ground from the PEAK pin. For
example, if a 50-kΩ (= RPEAK) resistor is connected between PEAK and GND, then the externally set IPEAK level
will be 250 mA. If RPEAK = 200 kΩ is, then the externally set IPEAK level will be 83 mA. HOLD current external
setting, IHOLD, works in the same way, but current levels are 40% of the IPEAK. External settings for IPEAK and
IHOLD are independent of each other. IPEAK and IHOLD values can be calculated by using the formula below.
250mA
IPEAK
=
× 66.67kW;66.67kW < RPEAK < 550kW
RPEAK
(2)
(3)
7
100mA
RHOLD
I
=
× 66.67kW;66.67kW < RHOLD < 250kW
HOLD
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SLVSBG3A –JUNE 2012–REVISED AUGUST 2012
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Figure 4. PEAK and HOLD Mode Current Settings
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SLVSBG3A –JUNE 2012–REVISED AUGUST 2012
Frequency of the internal PWM clock signal, PWMCLK, that triggers each ON-cycle can be adjusted by external
resistor, ROSC, connected between OSC and GND. Frequency as a function of resistor value is shown in
Figure 5. Default frequency is used when OSC is connected to GND directly. PWM frequency as a function of
external fixed adjustment resistor value (greater than 66.67 kΩ) is given below.
60kHz
fPWM
=
× 66.67kW;66.67kW < ROSC < 2MW
ROSC
(4)
Figure 5. PWM Clock Frequency Setting
Open-drain STATUS output is deactivated if either under voltage lockout or thermal shutdown blocks have
triggered.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
DRV120APWR
DRV120PWR
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
14
8
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV120APWR
DRV120PWR
TSSOP
TSSOP
PW
PW
14
8
2000
2000
330.0
330.0
12.4
12.4
6.9
7.0
5.6
3.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV120APWR
DRV120PWR
TSSOP
TSSOP
PW
PW
14
8
2000
2000
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
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