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DRV2604L

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

DRV2604L 用于 LRA 和 ERM 的 2V 至 5.2V 触觉驱动器，

具有内部存储器和智能环路架构

1 特性

DRV2604L 器件集成有足够的 RAM，用户能够预装载

1

超过 100 个定制智能环路架构波形。这些波形可通过

I²C 即时回放，或者也可选择由硬件触发引脚来触发。

•

灵活的触觉和振动驱动器

–

LRA（线性谐振致动器）

ERM（偏轴转动惯量)

此外，主机处理器可利用实时回放模式绕过存储器回放

引擎并通过 I²C 从主机直接播放波形。

•

I²C 控制的数字回放引擎

–

波形序列器和触发器

DRV2604L 器件内部采用智能环路架构，可轻松实现

自动谐振 LRA 驱动，以及优化反馈的 ERM 驱动，从

而提供自动过驱动和制动。这种智能环路架构可构建简

化的输入波形接口，并且能够提供可靠的电机控制和稳

定的电机性能。此外，DRV2604L 器件还能够在

LRA 致动器不产生有效反电动势电压时自动切换至开

环系统。当 LRA 产生有效反电动势电压

通过 I²C 实现的实时回放模式

针对定制波形的内部 RAM

I²C 双模式驱动（开环和闭环）

•

智能环路架构（正在申请专利的控制算法）

–

自动过驱动和制动

自动谐振跟踪和报告（仅限 LRA）

自动致动器诊断

时，DRV2604L 器件会自动与 LRA 同步。 DRV2604L

还可以利用内部生成的 PWM 信号实现开环驱动。

自动级别校准

支持宽泛的致动器型号

•

Immersion TouchSense^®3000 兼容

可在电池放电过程进行驱动补偿

宽工作电压范围（2V 至 5.2V）

高效的差分开关输出驱动

器件信息⁽¹⁾

器件型号

DRV2604L

封装

DSBGA (9)

VSSOP (10)

封装尺寸（最大值）

1.50mm x 1.50mm

3.00mm × 3.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

脉宽调制 (PWM) 输入，占空比可控范围为 0% 至

100%

•

硬件触发输入

简化原理图

快速启动时间

V

DD

RAM

1.8V 兼容、V_DD耐压数字接口

OUT+

Supply

correction

Gate

drive

2 应用

2

SDA

SCL

I

C I/F

LRA

or

ERM

•

手机

Control and

playback engine

Back-EMF

detection

M

EN

平板电脑

IN/TRIG

REG

OUTt

3 说明

Gate

drive

DRV2604L 器件是一款低压触觉驱动器，其闭环致动

器控制系统，可为 ERM 和 LRA 提供高质量的触觉反

馈。此方案有助于提升致动器在加速度稳定性、启动时

间和制动时间方面的性能，通过共用的 I²C 兼容总线或

PWM 输入信号即可触发该方案。

GND

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLOS866

DRV2604L

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

www.ti.com.cn

8.4 Device Functional Modes........................................ 19

8.5 Programming........................................................... 22

8.6 Register Map........................................................... 35

Application and Implementation ........................ 54

9.1 Application Information............................................ 54

9.2 Typical Application .................................................. 55

9.3 Initialization Setup................................................... 58

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Timing Requirements................................................ 6

6.7 Switching Characteristics.......................................... 6

6.8 Typical Characteristics.............................................. 8

Parameter Measurement Information .................. 9

7.1 Test Setup for Graphs............................................... 9

Detailed Description ............................................ 10

8.1 Overview ................................................................. 10

8.2 Functional Block Diagram ....................................... 10

8.3 Feature Description................................................. 11

9

10 Power Supply Recommendations ..................... 59

11 Layout................................................................... 60

11.1 Layout Guidelines ................................................. 60

11.2 Layout Example .................................................... 61

12 器件和文档支持 ..................................................... 62

12.1 文档支持................................................................ 62

12.2 接收文档更新通知 ................................................. 62

12.3 社区资源................................................................ 62

12.4 商标....................................................................... 62

12.5 静电放电警告......................................................... 62

12.6 Glossary................................................................ 62

13 机械、封装和可订购信息....................................... 62

7

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision E (August 2016) to Revision F

Page

•

Changed the DEFAULT value for bit 5-4 of Table 19 From: 1 To 3 ................................................................................... 46

Changed the DEFAULT value for bit 3-2 of Table 19 From: 2 To 1 ................................................................................... 47

Changed the DEFAULT value for bit 1-0 of Table 19 From: 2 To 1 ................................................................................... 48

Changed the typical value of C_(VDD)in Table 29 From: 0.1 µF To: 1 µF .............................................................................. 54

Changes from Revision D (June 2015) to Revision E

Page

•

Table 2, changed 0x00 Bit 4 From: Reserved To: ILLEGAL_ADDR.................................................................................... 35

Status (Address: 0x00), changed 0x00 Bit 4 From: Reserved To: ILLEGAL_ADDR........................................................... 36

Changes from Revision C (September 2014) to Revision D

Page

•

已发布完整版数据表 ............................................................................................................................................................... 1

2

DRV2604L

www.ti.com.cn

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

5 Pin Configuration and Functions

YZF Package

9-Pin DSBGA With 0.5-mm Pitch

(Top View)

1

2

3

EN

REG

OUT+

A

B

C

IN/TRIG

SCL

SDA

VDD

GND

OUTœ

Not to scale

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NO.

A1

NAME

EN

I

Device enable

A2

REG

OUT+

O

The REG pin is the 1.8-V regulator output. A 1-µF capacitor is required.

A3

Positive haptic driver differential output

Multi-mode Input. I²C selectable as PWM, analog, or trigger. If not used, this pin should

be connected to GND

B1

IN/TRIG

I

B2

B3

C1

C3

C2

SDA

GND

SCL

I/O

P

I²C data

Supply ground

I²C clock

I

OUT–

V_DD

O

P

Negative haptic-driver differential output

Supply input (2 to 5.2 V). A 1-µF capacitor is required.

(1) I = input, O = output, I/O = input and output, P = power

3

DRV2604L

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

www.ti.com.cn

DGS Package

10-Pin VSSOP

(Top View)

REG

SCL

1

2

3

4

5

10

9

V

DD

OUTœ

GND

SDA

8

IN/TRIG

EN

7

OUT+

VDD/NC

6

Not to scale

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NO.

1

NAME

REG

SCL

O

I

The REG pin is the 1.8-V regulator output. A 1-µF capacitor required

2

I²C clock

I²C data

3

SDA

I/O

Multi-mode Input. I²C is selectable as PWM, analog, or trigger. If not used, this pin should

be connected to GND

4

IN/TRIG

I

5

EN

V_DD/NC

OUT+

GND

I

Device enable

6

P

O

P

O

P

Optional supply input. This pin should be tied to V_DDor left floating.

Positive haptic driver differential output

Supply ground

7

8

9

OUT–

V_DD

Negative haptic driver differential output

Supply Input (2 V to 5.2 V). A 1-µF capacitor is required.

10

(1) I = input, O = output, I/O = input and output, P = power

4

DRV2604L

www.ti.com.cn

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range, T_A= 25°C (unless otherwise noted)

MIN

–0.3

–40

MAX

5.5

UNIT

V

V_DD

EN

V_DD+ 0.3

85

V

Input voltage

SDA

V

SCL

V

IN/TRIG

V

Operating free-air temperature, T_A

Operating junction temperature, T_J

Storage temperature, T_stg

°C

–40

150

–65

150

6.2 ESD Ratings

VALUE UNIT

9-PIN DSBGA PACKAGE

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾

±1000

V

Electrostatic

discharge

V_(ESD)

±250

10-PIN VSSOP PACKAGE

OUT+, OUT– pins⁽³⁾

Other pins⁽¹⁾

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾

±500

Human body model (HBM), per

ANSI/ESDA/JEDEC JS-001

Electrostatic

V_(ESD)

±1000

±250

V

discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000

V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V

may actually have higher performance.

(3) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2

MAX

5.2

UNIT

V

V_DD

Supply voltage

V_DD

ƒ_(PWM)

Z_L

PWM input frequency⁽¹⁾

Load impedance⁽¹⁾

IN/TRIG Pin

10

8

250

kHz

Ω

V_DD= 5.2 V

V_IL

Digital low-level input voltage

Digital high-level input voltage

Input voltage (analog mode)

LRA Frequency Range⁽¹⁾

EN, IN/TRIG, SDA, SCL

IN/TRIG

0.5

V

V_IH

1.3

0

V

V_I(ANA)

ƒ_(LRA)

1.8

V

125

300

Hz

(1) Ensured by design. Not production tested.

6.4 Thermal Information

DRV2604L

YZF (DSBGA)

(9-PINS)

145.2

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

R_θJC(top)

R_θJB

φ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

0.9

105

Junction-to-top characterization parameter

Junction-to-board characterization parameter

5.1

φ_JB

103.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

5

DRV2604L

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

www.ti.com.cn

6.5 Electrical Characteristics

T_A= 25°C, V_DD= 3.6 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_(REG)

I_IL

Voltage at the REG pin

1.83

V

EN, IN/TRIG, SDA, SCL

V_DD= 5.2 V , V_I= 0 V

Digital low-level input current

1

µA

IN/TRIG, SDA, SCL

V_DD= 5.2 V, V_I= V_DD

I_IH

Digital high-level input current

EN

3.5

0.4

V_DD= 5.2 V, V_I= V_DD

V_OL

Digital low-level output voltage

Digital pull-down resistance

SDAI_OL= 4 mA

V

EN

R_(EN-GND)

2

MΩ

V_DD= 5.2 V , V_I= V_DD

I_(SD)

I_I(standby)

I_Q

Shutdown current

Standby current

Quiescent current

Input impedance

V_(EN)= 0 V

4

4.1

7

µA

mA

kΩ

V_(EN)= 1.8 V, STANDBY = 1

V_(EN)= 1.8 V, STANDBY = 0, no signal

IN/TRIG to V_{(CM_ANA)}

0.5

0.65

Z_I

100

IN/TRIG common-mode voltage

(AC-coupled)

V_{(CM_ANA)}

Z_O(SD)

AC_COUPLE = 1

0.9

15

4

V

kΩ

Ω

Output impedance in shutdown

OUT+ to GND, OUT– to GND

Load impedance threshold for

over-current detection

Z_L(th)

Duty cycle = 90%, LRA mode, no load

Duty cycle = 90%, ERM mode, no load

2.4

2.3

3.5

Average battery current during

operation

I_{(BAT_AV)}

mA

6.6 Timing Requirements

T_A= 25°C, V_DD= 3.6 V (unless otherwise noted)

MIN

NOM

MAX

UNIT

kHz

µs

ƒ_(SCL)

t_w(H)

t_w(L)

Frequency at the SCL pin with no wait states

Pulse duration, SCL high

400

0.6

1.3

100

10

Pulse duration, SCL low

µs

See Figure 1.

See Figure 2.

t_su(1)

t_h(1)

Setup time, SDA to SCL

ns

Hold time, SCL to SDA

ns

Bus free time between stop and start

condition

t_(BUF)

1.3

µs

t_su(2)

t_h(2)

Setup time, SCL to start condition

Hold time, start condition to SCL

Setup time, SCL to stop condition

0.6

µs

t_su(3)

6.7 Switching Characteristics

T_A= 25°C, V_DD= 3.6 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ms

Time from the GO bit or external trigger

command to output signal

0.7

t_(start)

Start-up time

Time from EN high to output signal

(PWM/Analog Modes)

1.5

ƒ_O(PWM)

PWM Output Frequency

19.5

20.5

21.5

kHz

6

DRV2604L

www.ti.com.cn

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

t

w(L)

w(H)

SCL

SDA

t

su(1)

t

h(1)

Figure 1. SCL and SDA Timing

SCL

SDA

t

su(3)

h(2)

su(2)

t

(BUF)

Start Condition

Stop Condition

Figure 2. Timing for Start and Stop Conditions

7

DRV2604L

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

www.ti.com.cn

6.8 Typical Characteristics

IN/TRIG

Acceleration

[OUT+] − [OUT−] (Filtered)

0

40m

80m

120m

Time (s)

160m

200m

0

40m

80m

120m

Time (s)

160m

200m

V_DD= 4.2 V

ERM closed loop

V_DD= 4.2 V

LRA closed loop

External edge trigger

External level trigger

Figure 3. ERM Click with and without Braking (RAM)

Figure 4. LRA Click With and WIthout Braking (RAM)

SDA

Acceleration

[OUT+] − [OUT−] (Filtered)

0

200m

400m

600m

800m

1

0

200m

400m

600m

800m

1

Time (s)

V_DD= 4.2 V

ERM closed loop

Internal trigger

V_DD= 4.2 V

ERM closed loop

Internal trigger

Figure 5. ERM Click-Bounce (RAM)

Figure 6. LRA Transition-Click (RAM)

EN

SDA

IN/TRIG

Acceleration

[OUT+] − [OUT−] (Filtered)

0

40m

80m

120m

Time (s)

160m

200m

0

40m

80m

120m

Time (s)

160m

200m

V_DD= 4.2 V

ERM open loop

RTP Mode

V_DD= 3.6 V

LRA closed loop

PWM Mode

Figure 8. LRA Click With and Without Braking (PWM)

Figure 7. ERM Buzz (RTP)

8

DRV2604L

www.ti.com.cn

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

Typical Characteristics (continued)

100

90

80

70

60

50

ERM mode, R_L= 10 W + 100 µH, 1.3 V

ERM mode, R_L= 25 W + 100 µH, 2 V_(RMS)

SDA

ERM Mode

LRA Mode

0

1m

2m

3m

4m

5m

6m

7m

8m

9m 10m

2

2.4

2.8

3.2

3.6

4

4.4

4.8

5.2

Supply Voltage (V)

Time (s)

D013

V_DD= 4.2 V

Closed loop

No filter

Figure 10. Supply Current vs Supply Voltage (Full Vibration)

Figure 9. Startup Latency for ERM and LRA

7 Parameter Measurement Information

7.1 Test Setup for Graphs

To capture the graphs displayed in the Typical Characteristics section, the following first-order RC-filter setup

was used with the exception of the waveform in Figure 9 which was captured without any output filter. This filter

is recommended when viewing output signals on an oscilloscope because output PWM modulation is present in

all modes. Ensure that effective impedance of the filter is not too low because the closed-loop and auto

resonance-tracking features can be affected. Therefore, TI recommends that this exact filter be used for output

measurement. Most oscilloscopes have an input impedance of 1 MΩ on each channel and therefore have an

approximately 1% loss in measured amplitude because of the voltage-divider effect with the filter.

100 kꢀ

OUT+

LRA

or

ERM

Ch1

Ch2

470 pF

M

Ch1 œ Ch2

(Differential)

100 kꢀ

OUTœ

Oscilloscope

Figure 11. Test Setup

7.1.1 Default Test Conditions

•

V_DD= 3.6 V, unless otherwise noted.

Real actuators (as opposed to modeled actuators) were used as loads for both ERM and LRA modes with

exception of the Supply Voltage vs Supply Current (Full Vibration) waveform in Figure 10, which used passive

RL (resistance in series with an inductance) loads for test repeatability. Real actuators vary widely in supply

currents because of variation in back-EMF voltages. Because real actuators have back EMF, the real supply

current is generally less than what is shown in the waveform because of the reduction in the apparent load

impedance. Therefore, the curve shows the worst-case current.

•

All traces are 2 V/div except for the accelerometer traces

All accelerometer traces are 0.87 g/div except for the LRA Click with and without Braking (PWM) curve in

Figure 8, which is 1.74 g/div.

9

DRV2604L

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

www.ti.com.cn

8 Detailed Description

8.1 Overview

The DRV2604L device is a low-voltage haptic driver that relies on the back-EMF produced by an actuator to

provide a closed-loop system that offers extremely flexible control of LRA and ERM actuators over a shared I²C-

compatible bus or PWM input signal. This schema helps improve actuator performance in terms of acceleration

consistency, start time, and brake time.

The improved smart-loop architecture inside the DRV2604L device provides effortless auto-resonant drive for

LRA, as well as feedback-optimized ERM drive allowing for automatic overdrive and braking. These features

create a simplified input waveform paradigm as well as reliable motor control and consistent motor performance.

The DRV2604L device also features an automatic transition to open-loop operation in the event that an LRA

actuator is not generating a valid back-EMF voltage and automatic synchronization with the LRA when the LRA

is generating a valid back-EMF voltage. The DRV2604L device also allows for open-loop driving by using

internally-generated PWM.

The DRV2604L device includes enough integrated RAM to allow the user to preload over 100 customized

waveforms. The waveforms can be instantly played back through an I²C or can be triggered through a hardware

trigger pin. Additionally, the real-time playback mode allows the host processor to bypass the memory playback

engine and play waveforms directly from the host through the I²C.

The DRV2604L device features a trinary-modulated output stage that provides more efficiency than linear-based

output drivers.

8.2 Functional Block Diagram

V

DD

RAM

OUT+

Supply

correction

Gate

drive

2

SDA

SCL

I C I/F

LRA

or

ERM

Control and

playback engine

Back-EMF

detection

M

EN

IN/TRIG

REG

OUTt

Gate

drive

GND

10

DRV2604L

www.ti.com.cn

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

8.3 Feature Description

8.3.1 Support for ERM and LRA Actuators

The DRV2604L device supports both ERM and LRA actuators. The ERM_LRA bit in register 0x1A must be

configured to select the type of actuator that the device uses.

8.3.2 Smart-Loop Architecture

The smart-loop architecture is an advanced closed-loop system that optimizes the performance of the actuator

and allows for failure detection. The architecture consists of automatic resonance tracking and reporting (for an

LRA), automatic level calibration, accelerated startup and braking, diagnostics routines, and other proprietary

algorithms.

8.3.2.1 Auto-Resonance Engine for LRA

The DRV2604L auto-resonance engine tracks the resonant frequency of an LRA in real time, effectively locking

onto the resonance frequency after half of a cycle. If the resonant frequency shifts in the middle of a waveform

for any reason, the engine tracks the frequency from cycle to cycle. The auto-resonance engine accomplishes

the tracking by constantly monitoring the back-EMF of the actuator. The auto-resonance engine is not affected by

the auto calibration process, which is only used for level calibration. No calibration is required for the auto

resonance engine. See the Auto-Resonance Engine Programming for the LRA section for auto-resonance engine

programming information.

8.3.2.2 Real-Time Resonance-Frequency Reporting for LRA

The smart-loop architecture makes the resonant frequency of the LRA available through I²C (see the LRA

Resonance Period (Address: 0x22) section). Because frequency reporting occurs in real time, the frequency

must be polled while the DRV2604L device synchronizes with the LRA. The data should not be polled when the

actuator is idle or braking.

8.3.2.3 Automatic Switch to Open-Loop for LRA

In the event that an LRA produces a non-valid back-EMF signal, the DRV2604L device automatically switches to

open-loop operation and continues to deliver energy to the actuator in overdrive mode at a default and

configurable frequency. Use Equation 1 to calculate the default frequency. If the LRA begins to produce a valid

back-EMF signal, the auto-resonance engine automatically takes control and continues to track the resonant

frequency in real time. When synchronized, the mode enjoys all of the benefits that the smart-loop architecture

has to offer.

1

ƒ_{(LRA_NO-BEMF)}

ö

2 ì t_{(DRIVE_TIME[4:0])}œ t_{(ZC_DET _ TIME[1:0])}

(

)

(1)

The DRV2604L device offers an automatic transition to open-loop mode without the re-synchronization option.

The feature is enabled by setting the LRA_AUTO_OPEN_LOOP bit in register 0x1F. The transition to open-loop

mode only occurs when the driver fails to synchronize with the LRA. The AUTO_OL_CNT[1:0] bit in register 0x1F

can be adjusted to set the amount of non-synchronized cycles allowed before the transition to the open-loop

mode. Use Equation 2 to calculate the open-loop frequency. The open-loop mode does not receive benefits from

the smart-loop architecture, such as automatic overdrive and braking.

1

ƒ_{(LRA_OL)}

=

OL_LRA_PERIOD[6:0] × 98.49 × 10^œ6

(2)

8.3.2.4 Automatic Overdrive and Braking

A key feature of the DRV2604L is the smart-loop architecture which employs actuator feedback control for both

ERMs and LRAs. The feedback control desensitizes the input waveform from the motor-response behavior by

providing automatic overdrive and automatic braking.

11

DRV2604L

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

www.ti.com.cn

Feature Description (continued)

An open-loop haptic system typically drives an overdrive voltage at startup that is higher than the steady-state

rated voltage of the actuator to decrease the startup latency of the actuator. Likewise, a braking algorithm must

be employed for effective braking. When using an open-loop driver, these behaviors must be contained in the

input waveform data. Figure 12 shows how two different ERMs with different startup behaviors (Motor A and

Motor B) can both be driven optimally by the smart-loop architecture with a simple input for both motors. The

smart-loop architecture works equally well for LRAs with a combination of feedback control and an auto-

resonance engine.

Ideal Open-Loop Waveform for Motor B

Ideal Open-Loop Waveform for Motor A

Same simple input for

both motors

Input and output

Accleration

Feedback provides

optimum output drive

Output with feedback

Figure 12. Waveform Simplification With Smart Loop

8.3.2.4.1 Startup Boost

To reduce the actuator start-time performance, the DRV2604L device has an overdrive boost feature that applies

higher loop gain to transient response of the actuator. The STARTUP_BOOST bit enables the feature.

8.3.2.4.2 Brake Factor

To reduce the actuator brake-time performance, the DRV2604L device provides a means to increase the gain

ratio between braking and driving gain. Higher feedback-gain ratios reduce the brake time, however, the gain

ratios also reduce the stability of the closed-loop system. The FB_BRAKE_FACTOR[2:0] bits can be adjusted to

set the brake factor.

8.3.2.4.3 Brake Stabilizer

To improve brake stability at high brake-factor gain ratios, the DRV2604L device has a brake-stabilizer

mechanism that automatically reduces the loop gain when the braking is near completion. The

BRAKE_STABILIZER bit enables the feature.

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Feature Description (continued)

8.3.2.5 Automatic Level Calibration

The smart-loop architecture uses actuator feedback by monitoring the back-EMF behavior of the actuator. The

level of back-EMF voltage can vary across actuator manufacturers because of the specific actuator construction.

Auto calibration compensates for the variation and also performs scaling for the desired actuator according to the

specified rated voltage and overdrive clamp-register settings. When auto calibration is performed, a 100% signal

level at any of the DRV2604L input interfaces supplies the rated voltage to the actuator at steady-state. The

feedback allows the output level to increase above the rated voltage level for automatic overdrive and braking,

but without allowing the output level to exceed the programmable overdrive clamp voltage.

In the event where the automatic level-calibration routine fails, the DIAG_RESULT bit in register 0x00 is asserted

to flag the problem. Calibration failures are typically fixed by adjusting the registers associated with the automatic

level-calibration routine or, for LRA actuators, the registers associated with the automatic-resonance detection

engine. See the 器件和文档支持 section for automatic-level calibration programming.

8.3.2.5.1 Automatic Compensation for Resistive Losses

The DRV2604L device automatically compensates for resistive losses in the driver. During the automatic level-

calibration routine, the impedance of the actuator is checked and the compensation factor is determined and

stored in the A_CAL_COMP[7:0] bit.

8.3.2.5.2 Automatic Back-EMF Normalization

The DRV2604L device automatically compensates for differences in back-EMF magnitude between actuators.

The compensation factor is determined during the automatic level-calibration routine and the factor is stored in

the A_CAL_BEMF[7:0] bit.

8.3.2.5.3 Calibration Time Adjustment

The duration of the automatic level-calibration routine has an impact on accuracy. The impact is highly

dependent on the start-time characteristic of the actuator. The auto-calibration routine expects the actuator to

have reached a steady acceleration before the calibration factors are calculated. Because the start-time

characteristic can be different for each actuator, the AUTO_CAL_TIME[1:0] bit can change the duration of the

automatic level-calibration routine to optimize calibration performance.

8.3.2.5.4 Loop-Gain Control

The DRV2604L device allows the user to control how fast the driver attempts to match the back-EMF (and thus

motor velocity) and the input signal level. Higher loop-gain (or faster settling) options result in less-stable

operation than lower loop gain (or slower settling). The LOOP_GAIN[1:0] bit controls the loop gain.

8.3.2.5.5 Back-EMF Gain Control

The BEMF_GAIN[1:0] bit sets the analog gain for the back-EMF amplifier. The auto-calibration routine

automatically populates the bit with the most appropriate value for the actuator.

Modifying the SAMPLE_TIME[1:0] bit also adjusts the back-EMF gain. The higher the sample time, the higher

the gain.

By default, the back-EMF is sampled once during a period. In the event that a twice per-period sampling is

desired, assert the LRA_DRIVE_MODE bit.

8.3.2.6 Actuator Diagnostics

The DRV2604L device is capable of determining whether the actuator is not present (open) or shorted. If a fault

is detected during the diagnostic process, the DIAG_RESULT bit is asserted.

8.3.2.7 Automatic Re-Synchronization

For the LRA, the DRV2604L device features an automatic re-synchronization mode which automatically pushes

the actuator in the correct direction when a waveform begins playing while the actuator is moving. If the actuator

is at rest when the waveform begins, the DRV2604L device drives in the default direction.

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Feature Description (continued)

8.3.3 Open-Loop Operation for LRA

In the event that open-loop operation is desired (such as for off-resonance driving) the DRV2604L device

includes an open-loop LRA drive mode that is available through the PWM input or through the digital interface.

When using the PWM input in open-loop mode, the DRV2604L device employs a fixed divider that observes the

PWM signal and commutates the output drive signal at the PWM frequency divided by 128. To accomplish LRA

drive, the host should drive the PWM frequency at 128 times the desired operating frequency.

When activated, the digital open-loop mode is available for pre-stored waveforms as well as for RTP mode. The

OL_LRA_PERIOD bit in register 0x20 programs the operating frequency, which is derived from the PWM output

frequency, ƒ_O(PWM). Use Equation 1 to calculate the driving frequency. The open-loop mode does not receive the

benefits of the smart-loop architecture.

8.3.4 Open-Loop Operation for ERM

The DRV2604L device offers ERM open-loop operation through the PWM input. The output voltage is based on

the duty cycle of the provided PWM signal, where the OD_CLAMP[7:0] bit in register 0x17 sets the full-scale

amplitude. For details see the Rated Voltage Programming section.

8.3.5 Flexible Front-End Interface

The DRV2604L device offers multiple ways to launch and control haptic effects. The MODE[2:0] bit in register

0x01 is used to select the interface mode.

8.3.5.1 PWM Interface

When the DRV2604L device is in PWM interface mode, the device accepts PWM data at the IN/TRIG pin. The

DRV2604L device drives the actuator continuously in PWM interface mode until the user sets the device to

standby mode or to enter another interface mode. In standby mode, the strength of vibration is determined by the

duty cycle.

For the LRA, the DRV2604L device automatically tracks the resonance frequency unless the LRA_OPEN_LOOP

bit in register 0x1D is set. If the LRA_OPEN_LOOP bit is set, the LRA is driven according to the frequency of the

PWM input signal. Specifically, the driving frequency is the PWM frequency divided by 128.

8.3.5.2 Internal Memory Interface

The DRV2604LL device is designed with 2 kB of integrated RAM for waveform storage used by the playback

engine. The data is stored in an efficient way (voltage-time pairs) to maximize the number of waveforms that can

be carried. The playback engine also has the ability to generate smooth ramps (up or down) by relying on the

start-waveform and end-waveform points and by using linear interpolation techniques.

Storing waveforms on the DRV2604LL device instead of the host processor has several advantages including:

•

Offloading processing requirements, such as PWM generation, from the host processor or micro-controller

Improving latency by storing the waveforms on the DRV2604LL device and only requiring a trigger signal

Reducing I²C traffic by eliminating the requirement to transfer waveform data

8.3.5.2.1 Waveform Sequencer

The waveform sequencer queues waveform identifiers for playback. Eight sequence registers queue up to eight

waveforms for sequential playback. A waveform identifier is an integer value referring to the index position of a

waveform in the RAM library. Playback begins at register address 0x04 when the user asserts the GO bit

(register 0x0C). When playback of that waveform ends, the waveform sequencer plays the waveform identifier

held in register 0x05 if the next waveform is non-zero. The waveform sequencer continues in this way until it

reaches an identifier value of zero or until all eight identifiers are played (register addresses 0x04 through 0x0B),

whichever scenario is reached first.

The waveform identifier range is 1 to 127. The MSB of each sequence register can implement a delay between

sequence waveforms. When the MSB is high, bits [6:0] indicate the length of the wait time. The wait time for that

step then becomes WAV_FRM_SEQ[6:0] × 10 ms.

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Feature Description (continued)

8.3.5.2.2 Library Parameterization

The RAM waveforms are augmented by the time offset registers (registers 0x0D to 0x10). The augmentation

occurs only for the RAM waveforms and not for the other interfaces (such as PWM and RTP). The purpose of

the functionality is to add time stretching (or time shrinking) to the waveform. This functionality is useful for

customizing the entire library of waveforms for a specific actuator rise time and fall time.

The time parameters that can be stretched or shrunk include:

ODT

SPT

SNT

BRT

Overdrive time

Sustain positive time

Sustain Negative Time

Brake Time

The time values are additive offsets and are 8-bit signed values. The default offset of the time values is 0.

Positive values add and negative values subtract from the time value of the effect that is currently played. The

most positive value in the waveform is automatically interpreted as the overdrive time, and the most negative

value in the waveform is automatically interpreted as the brake time. The time-offset parameters are applied to

both voltage-time pairs and linear ramps. For linear ramps, linear interpolation is stretched (or shrunk) over the

two operative points for the period (see Equation 3).

t + t_(ofs)

where

•

t_(ofs)is the time offset

(3)

Changing the playback interval can also manipulate the waveforms stored in memory. Each waveform in memory

has a granularity of 5 ms. If the user desires greater granularity, a 1-ms playback interval can be obtained by

asserting the PLAYBACK_INTERVAL bit in register 0x1F.

8.3.5.3 Real-Time Playback (RTP) Interface

The real-time playback mode is a simple, single 8-bit register interface that holds an amplitude value. When real-

time playback is enabled, the real-time playback register is sent directly to the playback engine. The amplitude

value is played until the user sends the device to standby mode or removes the device from RTP mode. The

RTP mode operates exactly like the PWM mode except that the user enters a register value over the I²C rather

than a duty cycle through the input pin. Therefore, any API (application-programming interface) designed for use

with a PWM generator in the host processor can write the data values over the I²C rather than writing the data

values to the host timer. This ability frees a timer in the host while retaining compatibility with the original

software.

For the LRA, the DRV2604L device automatically tracks the resonance frequency unless the LRA_OPEN_LOOP

bit is set (in register 0x1D). If the LRA_OPEN_LOOP bit is set, the LRA is driven according to the open-loop

frequency set in the OL_LRA_PERIOD[6:0] bit in register 0x20.

8.3.5.4 Analog Input Interface

When the DRV2604L device is in analog-input interface mode, the device accepts an analog voltage at the

IN/TRIG pin. The DRV2604L device drives the actuator continuously in analog-input interface mode until the user

sets the device to standby mode or to enter another interface mode. The reference voltage in standby mode is

1.8 V. Therefore, the 1.8-V reference voltage is interpreted as a 100% input value. A reference voltage of 0.9 V

is interpreted as a 50% input value and a reference voltage of 0 V is interpreted as a 0% input value. The input

value in standby mode is analogous to the duty-cycle percentage in PWM mode.

For the LRA, the DRV2604L automatically tracks the resonance frequency unless the LRA_OPEN_LOOP bit is

set (in register 0x1D). If the LRA_OPEN_LOOP bit is set, the LRA is driven according to the open-loop frequency

set in OL_LRA_PERIOD[6:0] bit in register 0x20.

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Feature Description (continued)

8.3.5.5 Input Trigger Option

The DRV2604L device includes continuous haptic modes (such as PWM and RTP mode) as well as triggered

modes (such as the internal memory interface). The haptic effects in the continuous haptic modes begin as soon

as the device enters the mode and stop when the device goes into standby mode or exits the continuous haptic

mode. For the triggered mode, the DRV2604L device has a variety of trigger options that are explained in this

section.

In the continuous haptic modes, the IN/TRIG pin provides external trigger control of the GO bit, which allows

GPIO control to fire RAM waveforms. The external trigger control can provide improved latencies in systems

where a significant delay exists between the desired effect time and the time a GO command can be sent over

the I²C interface.

NOTE

The triggered effect must already be selected to take advantage of the lower latency. This

option works best for accelerating a pre-queued high-priority effect (such as a button

press) or for the repeated firing of the same effect (such as scrolling).

8.3.5.5.1 I²C Trigger

Setting the GO bit (in register 0x0C) launches the waveform. The user can cancel the launching of the waveform

by clearing the GO bit.

8.3.5.5.2 Edge Trigger

A low-to-high transition on the IN/TRIG pin sets the GO bit. The playback sequence indicated in the waveform

sequencer plays as normal. The user can cancel the transaction by clearing the GO bit. An additional low-to-high

transition while the GO bit is high also cancels the transaction which clears and resets the GO bit. Clearing the

trigger pin (high-to-low transition) does nothing, therefore the user can send a short pulse without knowing how

long the waveform is. The pulse width should be at least 1 µs to ensure detection.

Edge Trigger

Haptic Waveform

Edge Trigger

Cancellation

Haptic Waveform

Figure 13. Edge Trigger Mode

8.3.5.5.3 Level Trigger

The actions of the GO bit directly follow the IN/TRIG pin. When the IN/TRIG pin is high, the GO bit is high. When

the IN/TRIG pin goes low, the GO bit clears. Therefore, a falling edge cancels the transaction. The level trigger

can implement a GPIO-controlled buzz on-off controller if an appropriately long waveform is selected. The user

must hold the IN/TRIG high for the entire duration of the waveform to complete the effect.

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Feature Description (continued)

Level Trigger

Haptic Waveform

Level Trigger

Cancellation

Haptic Waveform

Figure 14. Level Trigger Mode

8.3.5.6 Noise Gate Control

When an actuator is driven with an analog or PWM signal, noise in the line can cause the actuator to vibrate

unintentionally. For that reason, the DRV2604L device features a noise gate that filters out any voltage smaller

than a particular threshold. The NG_THRESH[1:0] bit in register 0x1D controls the threshold.

8.3.6 Edge Rate Control

The DRV2604L output driver implements edge rate control (ERC). The ERC ensures that the rise and fall

characteristics of the output drivers do not emit levels of radiation that could interfere with other circuitry common

in mobile and portable platforms. Because of ERC most system do not require external output filters, capacitors,

or ferrite beads.

8.3.7 Constant Vibration Strength

The DRV2604L PWM input uses a digital level-shifter. Therefore, as long as the input voltage meets the V_IHand

V_ILlevels, the vibration strength remains the same even if the digital levels vary. The DRV2604L device also

features power-supply feedback. If the supply voltage drifts over time (because of battery discharge, for

example), the vibration strength remains the same as long as enough supply voltage is available to sustain the

required output voltage.

8.3.8 Battery Voltage Reporting

During playback, the DRV2604L device provides real-time voltage measurement of the V_DDpin. The VBAT[7:0]

bit located in register 0x21 provides this information.

8.3.9 One-Time Programmable (OTP) Memory for Configuration

The DRV2604L device contains nonvolatile, on-chip, OTP memory for specific configuration parameters. When

written, the DRV2604L device retains the device settings in registers 0x16 through 0x1A including after power

cycling. This retention allows the user to account for small variations in actuator manufacturing from unit to unit

as well as to shorten the device-initialization process for device-specific parameters such as actuator type,

actuator-rated voltage, and other parameters. An additional benefit of OTP is that the DRV2604L memory can be

customized at the device-test level without driving changes in the device software.

8.3.10 Low-Power Standby

Setting the device to standby reduces the idle power consumption without resetting the registers. In Low-Power

Standby mode, the DRV2604L device features a fast turnon time when it is requested to play a waveform.

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Feature Description (continued)

8.3.11 I²C Watchdog Timer

If an I²C stops unexpectedly, the possibility exists for the I²C protocol to remain in a hanged state. To allow for

the recovery of the communication without having to power cycle the device, the DRV2604L device includes an

automatic watchdog timer that resets the I²C protocol without user intervention after 4.33 ms. This behavior

happens in all conditions except in standby mode. If the I²C stops unexpectedly during standby mode, the only

way to recover communication is by power-cycling the device.

8.3.12 Device Protection

8.3.12.1 Thermal Protection

The DRV2604L device has thermal protection that causes the device to shut down if it becomes too hot. In the

event where the thermal protection kicks in, the DRV2604L device asserts a flag (bit OVER_TEMP in register

0x00) to notify the host processor.

8.3.12.2 Overcurrent Protection of the Actuator

If the impedance at the output pin of the DRV2604L device is too low, the device latches the over-current flag

(OC_DETECT bit in register 0x00) and shuts down. The device periodically monitors the status of the short and

remains in this condition until the short is removed. When the short is removed, the DRV2604L device restarts in

the default state.

8.3.12.3 Overcurrent Protection of the Regulator

The DRV2604L device has an internal regulator that powers a portion of the system. If a short occurs at the

output of the REG pin, an internal overcurrent protection circuit is enabled and limits the current.

During a REG short, the device is not functional. When the short is removed, the DRV2604L device automatically

resets to default conditions.

8.3.12.4 Brownout Protection

The DRV2604L device has on-chip brownout protection. When activated, a reset signal is issued that returns the

DRV2604L device to the initial default state. If the regulator voltage V_(REG)goes below the brownout protection

threshold (V_(BOT)) the DRV2604L device automatically shuts down. When V_(REG)returns to the typical output

voltage (1.8 V) the DRV2604L device returns to the initial device state. The brownout protection threshold

(V_(BOT)) is typically at 0.84 V.

The previously described behavior has one exception. The brownout circuit is designed to tolerate fast brownout

conditions as shown by Case 1 in Figure 15. If the V_DDramp-up rate is slower than 3.6 kV/s, then the device can

fall into an unknown state. In such a situation, to return to the initial default state the device must be power-

cycled with a V_DDramp-up rate that is faster than 3.6 kV/s.

Case 1

Case 3

Case 4

Case 2

V

DD

Return to

default

state

Return to

default

state

Unknown

state

Unknown

state

2 V

1.8 V

REG

Time

V

(BOT)

0 V

Slew rate > 3.6 kV/s

Slew rate < 3.6 kV/s

Slew rate > 3.6 kV/s

Figure 15. Brownout Behavior

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8.4 Device Functional Modes

8.4.1 Power States

The DRV2604L device has three different power states which allow for different power-consumption levels and

functions. Figure 16 shows the transition in to and out of each state.

EN = 0

EN = 1

Shutdown

Standby

STANDBY = 0

EN = 0

STANDBY = 1

Active

DEV_RESET = 1

Figure 16. Power-State Transition Diagram

8.4.1.1 Operation With V_DD< 2 V (Minimum V_DD

)

Operating the device with a V_DDvalue below 2 V is not recommended.

8.4.1.2 Operation With V_DD> 5.5 V (Absolute Maximum V_DD

)

The DRV2604L device is designed to operate at up to 5.2 V, with an absolute maximum voltage of 5.5 V. If

exposed to voltages above 5.5 V, the device can suffer permanent damage.

8.4.1.3 Operation With EN Control

The EN pin of the DRV2604L device gates the active operation. When the EN pin is logic high, the DRV2604L

device is active. When the EN pin is logic low, the device enters the shutdown state, which is the lowest power

state of the device. The device registers are not reset. The EN pin operation is particularly useful for constant-

source PWM and analog input modes to maintain compatibility with non-I²C device signaling. The EN pin must

be high to write I²C device registers. However, if the EN pin is low the DRV2604L device can still acknowledge

(ACK) during an I²C transaction, however, no read or write is possible. To completely reset the device to the

powerup state, set the DEV_RESET bit in register 0x01.

8.4.1.4 Operation With STANDBY Control

The STANDBY bit in register 0x01 forces the device in an out of the standby state. The STANDBY bit is asserted

by default. When the STANDBY bit is asserted, the DRV2604L device goes into a low-power state. In the

standby state the device retains register values and the ability to have I²C communication. The properties of the

standby state also feature a fast turn, wake up, and play, on-time. Asserting the STANDBY bit has an immediate

effect. For example, if a waveform is played, it immediately stops when the STANDBY bit is asserted.

Clear the STANDBY bit to exit the standby state (and go to the ready state).

8.4.1.5 Operation With DEV_RESET Control

The DEV_RESET bit in register 0x01 performs the equivalent of power cycling the device. Any playback

operations are immediately interrupted, and all registers are reset to the default values. The Dev_Reset bit

automatically-clears after the reset operation is complete.

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Device Functional Modes (continued)

8.4.1.6 Operation in the Active State

In the active state, the DRV2604L device has I²C communication and is capable of playing waveforms, running

calibration, and running diagnostics. These operations are referred to as processes. Figure 17 shows the flow of

starting, or firing, a process. Notice that the GO signal fires the processes. Note that the GO signal is not the

same as the GO bit. Figure 18 shows a diagram of the GO-signal behavior.

Change

Modes

Ready

GO Signal = 1

Process

Done

GO Signal = 1

Optional

Check for

Output

Shorts

Wait 1 s

Run

Process

No Short

Short Found

Note: If an output short is present before a waveform is played, changing modes (with the MODE[2:0] bit in register 0x01) is

required to resume normal playback.

Figure 17. Diagram of Active States

8.4.2 Changing Modes of Operation

The DRV2604L has multiple modes for playing waveforms, as well as a calibration mode and a diagnostic mode.

Table 1 lists the available modes.

Table 1. Mode Selection Table

MODE

Internal trigger mode

External Trigger mode (edge)

External trigger mode (level)

Analog input mode

PWM mode

MODE[2:0]

N_PWM_ANALOG

0

1

2

3

5

6

7

X

0

1

RTP mode

X

Diagnostics mode

Calibration mode

8.4.3 Operation of the GO Bit

The GO bit is the primary way to assert the GO signal, which fires processes in the DRV2604L device. The

primary purpose of the GO bit is to fire the playback of the waveform identifiers in the waveform sequencer

(registers 0x04 to 0x0B). However, The GO bit can also fire the calibration or diagnostics processes.

When using the GO bit to play waveforms in internal trigger mode, the GO bit is asserted by writing 0x01 to

register 0x0C. In this case, the GO bit can be thought of as a software trigger for haptic waveforms. The GO bit

remains high until the playback of the haptic waveform sequence is complete. Clearing the GO bit during

waveform playback cancels the waveform sequence. The GO bit can also be asserted by the external trigger

when in external trigger mode. The GO bit in register 0x0C mirrors the state of the external trigger.

Setting RTP mode or PWM mode also sets the GO bit. However, setting the GO bit in this way has no impact on

the GO bit located in register 0x0C.

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Also accessible

2

(R/W) through I C

MODE[2:0] = 1 (External trigger – edge)

MODE[2:0] = 2 (External trigger – level)

IN/TRIG (Trigger)

GO Bit

MODE[2:0] = 3 (PWM and analog input)

MODE[2:0] = 5 (RTP mode)

GO Signal

Figure 18. GO-Signal Logic

8.4.4 Operation During Exceptional Conditions

This section lists different exceptional conditions and the ways that the DRV2604L device operates during these

conditions. This section also describes how the device goes into and out of these states.

8.4.4.1 Operation With No Actuator Attached

In LRA closed-loop mode, if a waveform is played without an actuator connected to the OUT+ and OUT– pins,

the output pins toggle. However, the toggling frequency is not predictable. In LRA open-loop mode, the output

pins toggle at the specified open-loop frequency.

8.4.4.2 Operation With a Non-Moving Actuator Attached

The model of a non-moving actuator can be simplified as a resistor. If a resistor (with similar loading as an LRA,

such as 25 O) is connected across the OUT+ and OUT– pins, and the DRV2604L device is in LRA closed-loop

mode, the output pins toggle at a default frequency calculated with Equation 1. In LRA open-loop mode the

output pins toggle at the specified open-loop frequency.

8.4.4.3 Operation With a Short at REG Pin

If the REG pin is shorted to GND, the device automatically shuts down and an overcurrent-protection circuit is

enabled and clamps the maximum current supplied by the regulator. When the short is removed, the device

starts in the default condition.

8.4.4.4 Operation With a Short at OUT+, OUT–, or Both

If any of the output pins (OUT+ or OUT–) is shorted to V_DD, GND, or to each other while the device is playing a

waveform, the OC_DETECT bit is asserted and remains asserted until the short is removed. A current-protection

circuit automatically enables to shutdown the current through the short.

If the driver is playing a waveform the DRV2604L device checks for shorts in the output through either a haptic-

playback, auto-calibration, or diagnostics process. If the short occurs when the device is idle, the short is not

detected until the device attempts to run a waveform.

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8.5 Programming

8.5.1 Auto-Resonance Engine Programming for the LRA

8.5.1.1 Drive-Time Programming

The resonance frequency of each LRA actuator varies based on many factors and is generally dominated by

mechanical properties. The auto-resonance engine-tracking system is optimized by providing information about

the resonance frequency of the actuator. The DRIVE_TIME[4:0] bit is used as an initial guess for the half-period

of the LRA. The drive time is automatically and quickly adjusted for optimum drive. For example, if the LRA has a

resonance frequency of 200 Hz, then the drive time should be set to 2.5 ms.

For ERM actuators, the DRIVE_TIME[4:0] bit controls the rate for back-EMF sampling. Lower drive times imply

higher back-EMF sampling frequencies which cause higher peak-to-average ratios in the output signal, and

requires more supply headroom. Higher drive times imply lower back-EMF sampling frequencies which cause the

feedback to react at a slower rate.

8.5.1.2 Current-Dissipation Time Programming

To sense the back-EMF of the actuator, the DRV2604L device goes into high impedance mode. However, before

the device enters high impedance mode, the device must dissipate the current in the actuator. The DRV2604L

device controls the time allocated for dissipation-current through the IDISS_TIME[3:0] bit.

8.5.1.3 Blanking Time Programming

After the current in the actuator dissipates, the DRV2604L device waits for a blanking time of the signal to settle

before the back-EMF analog-to-digital (AD) conversion converts. The BLANKING_TIME[3:0] bit controls this time.

8.5.1.4 Zero-Crossing Detect-Time Programming

When the blanking time expires, the back-EMF AD monitors for zero crossings. The ZC_DET_TIME[1:0] bit

controls the minimum time allowed for detecting zero crossings.

8.5.2 Automatic-Level Calibration Programming

8.5.2.1 Rated Voltage Programming

The rated voltage is the driving voltage that the driver will output during steady state. However, in closed-loop

drive mode, temporarily having an output voltage that is higher than the rated voltage is possible. See the

Overdrive Voltage-Clamp Programming section for details.

The RATED_VOLTAGE[7:0] bit in register 0x16 sets the rated voltage for the closed-loop drive modes. For the

ERM, Equation 4 calculates the average steady-state voltage when a full-scale input signal is provided. For the

LRA, Equation 5 calculates the root-mean-square (RMS) voltage when driven to steady state with a full-scale

input signal.

V

_{(ERM-CL_AV)}= 21.18 ×10^œ3RATED_VOLTAGE[7:0]

(4)

20.58 × 10^œ3× RATED_VOLTAGE[7:0]

1 œ (4 þ t_{(SAMPLE_TIME)}+ 300 ì 10^œ6) þ ƒ_(LRA)

V

=

(LRA-CL_RMS)

(5)

In open-loop mode, the RATED_VOLTAGE[7:0] bit is ignored. Instead, the OD_CLAMP[7:0] bit (in register 0x17)

is used to set the rated voltage for the open-loop drive modes. For the ERM, Equation 6 calculates the rated

voltage with a full-scale input signal. For the LRA, Equation 7 calculates the RMS voltage with a full-scale input

signal.

V

_{(ERM-OL_AV)}= 21.59 × 10^œ3OD_CLAMP[7:0]

(6)

V

_{(LRA-OL_RMS)}= 21.32 þ 10^œ3þ OD_CLAMP[7:0] þ 1 œ ƒ_(LRA)þ 800 þ 10^œ6

(7)

The auto-calibration routine uses the RATED_VOLTAGE[7:0] and OD_CLAMP[7:0] bits as inputs and therefore

these registers must be written before calibration is performed. Any modification of this register value should be

followed by calibration to appropriately set A_CAL_BEMF[7:0].

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Programming (continued)

8.5.2.2 Overdrive Voltage-Clamp Programming

During closed-loop operation, the actuator feedback allows the output voltage go above the rated voltage during

the automatic overdrive and automatic braking periods. The OD_CLAMP[7:0] bit (in Register 0x17) sets a clamp

so that the automatic overdrive is bounded. The OD_CLAMP[7:0] bit also serves as the full-scale reference

voltage for open-loop operation. The OD_CLAMP[7:0] bit always represents the maximum peak voltage that is

allowed, regardless of the mode.

NOTE

If the supply voltage (V_DD) is less than the overdrive clamp voltage, the output driver is

unable to reach the clamp voltage value because the output voltage cannot exceed the

supply voltage. If the rated voltage exceeds the overdrive clamp voltage, the overdrive

clamp voltage has priority over the rated voltage.

In ERM mode, use Equation 8 to calculate the allowed maximum voltage. In LRA mode, use Equation 9 to

calculate the maximum peak voltage.

21.64 þ 10^œ3þ OD_CLAMP[7:0] þ (t_{(DRIVE_TIME)}œ300 þ 10^œ6

)

V

=

(ERM_ clamp)

t_{(DRIVE_TIME)}+ t_{(IDISS_TIME)}+ t_{(BLANKING_TIME)}

(8)

(9)

V

_{(LRA_clamp)}= 21.22 × 10^œ3× OD_CLAMP[7:0]

8.5.3 I²C Interface

8.5.3.1 General I²C Operation

The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a

system. The bus transfers data serially, one bit at a time. The 8-bit address and data bytes are transferred with

the most-significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving

device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition

on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the

data pin (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on the

SDA signal indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur

within the low time of the clock period. Figure 19 shows a typical sequence. The master device generates the 7-

bit slave address and the read-write (R/W) bit to start communication with a slave device. The master device

then waits for an acknowledge condition. The slave device holds the SDA signal low during the acknowledge

clock period to indicate acknowledgment. When this acknowledgment occurs, the master transmits the next byte

of the sequence. Each device is addressed by a unique 7-bit slave address plus a R/W bit (1 byte). All

compatible devices share the same signals through a bidirectional bus using a wired-AND connection.

The number of bytes that can be transmitted between start and stop conditions is not limited. When the last word

transfers, the master generates a stop condition to release the bus. Figure 19 shows a generic data-transfer

sequence.

Use external pullup resistors for the SDA and SCL signals to set the logic-high level for the bus. Pullup resistors

with values between 660 Ω and 4.7 kΩ are recommended. Do not allow the SDA and SCL voltages to exceed

the DRV2604L supply voltage, V_DD

.

NOTE

The DRV2604L slave address is 0x5A (7-bit), or 1011010 in binary.

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Programming (continued)

8-bit register data for address

7-bit slave address

A

8-bit register address (N)

A

R/W

(N)

b₇b₆b₅b₄b₃b₂b₁b₀

Start

Stop

Figure 19. Typical I²C Sequence

The DRV2604L device operates as an I²C-slave 1.8-V logic thresholds, but can operate up to the V_DDvoltage.

The device address is 0x5A (7-bit), or 1011010 in binary which is equivalent to 0xB4 (8-bit) for writing and 0xB5

(8-bit) for reading.

8.5.3.2 Single-Byte and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte R/W operations for all registers.

During multiple-byte read operations, the DRV2604L device responds with data one byte at a time and beginning

at the signed register. The device responds as long as the master device continues to respond with

acknowledges.

The DRV2604L supports sequential I²C addressing. For write transactions, a sequential I²C write transaction has

taken place if a register is issued followed by data for that register as well as the remaining registers that follow.

For I²C sequential-write transactions, the register issued then serves as the starting point and the amount of data

transmitted subsequently before a stop or start is transmitted determines how many registers are written.

8.5.3.3 Single-Byte Write

As shown in Figure 20, a single-byte data-write transfer begins with the master device transmitting a start

condition followed by the I²C device address and the read-write bit. The read-write bit determines the direction of

the data transfer. For a write-data transfer, the read-write bit must be set to 0. After receiving the correct I²C

device address and the read-write bit, the DRV2604L responds with an acknowledge bit. Next, the master

transmits the register byte corresponding to the DRV2604L internal-memory address that is accessed. After

receiving the register byte, the device responds again with an acknowledge bit. Finally, the master device

transmits a stop condition to complete the single-byte data-write transfer.

Acknowledge

A7 A6 A5

A6 A5 A4 A3 A2 A1 A0

W

ACK

A4 A3 A2 A0 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

2

Stop

condition

Subaddress

Data byte

Start

condition

I C device address

and R/W bit

Figure 20. Single-Byte Write Transfer

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Programming (continued)

8.5.3.4 Multiple-Byte Write and Incremental Multiple-Byte Write

A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes

are transmitted by the master device to the DRV2604L device as shown in Figure 21. After receiving each data

byte, the DRV2604L device responds with an acknowledge bit.

Acknowledge

A1 A0

W

ACK A7 A6

A1 A0 ACK D7 D6

D1 D0 ACK D7

D0 ACK D7

D0 ACK

Stop

condition

2

Start

condition

Subaddress

First data byte

Other data bytes

Last data byte

I C device address

and R/W bit

Figure 21. Multiple-Byte Write Transfer

8.5.3.5 Single-Byte Read

Figure 22 shows that a single-byte data-read transfer begins with the master device transmitting a start condition

followed by the I²C device address and the read-write bit. For the data-read transfer, both a write followed by a

read actually occur. Initially, a write occurs to transfer the address byte of the internal memory address to be

read. As a result, the read-write bit is set to 0.

After receiving the DRV2604L address and the read-write bit, the DRV2604L device responds with an

acknowledge bit. The master then sends the internal memory address byte, after which the device issues an

acknowledge bit. The master device transmits another start condition followed by the DRV2604L address and the

read-write bit again. This time, the read-write bit is set to 1, indicating a read transfer. Next, the DRV2604L

device transmits the data byte from the memory address that is read. After receiving the data byte, the master

device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.

See the note in the General I²C Operation section.

Acknowledge

ACK

A6 A5

A1 A0

W

A7 A6

A1 A0

A6 A5

A0

R

D7

D0 ACK

2

Start

Condition

Subaddress

Repeat start

condition

Data Byte

Stop

Condition

I C device address and

R/W bit

I C device address and

R/W bit

Figure 22. Single-Byte Read Transfer

8.5.3.6 Multiple-Byte Read

A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes

are transmitted by the DRV2604L device to the master device as shown in Figure 23. With the exception of the

last data byte, the master device responds with an acknowledge bit after receiving each data byte.

Acknowledge

A6

A0

W

ACK A7 A6

A1 A0 ACK

A6 A5

2

A0

R

ACK D7

D0 ACK D7

D0 ACK

2

Stop

Repeat start

Start

Subaddress

First data byte Other data byte Last data byte

I C device address

and R/W bit

I C device address

and R/W bit

condition

Figure 23. Multiple-Byte Read Transfer

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Programming (continued)

8.5.4 Programming for Open-Loop Operation

The DRV2604L device can be used in open-loop mode and closed-loop mode. If open-loop operation is desired,

the first step is to determine which actuator type is to use, either ERM or LRA.

8.5.4.1 Programming for ERM Open-Loop Operation

To configure the DRV2604L device in ERM open-loop operation, the ERM must be selected by writing the

N_ERM_LRA bit to 0 (in register 0x1A), and the ERM_OPEN_LOOP bit to 1 in register 0x1D.

8.5.4.2 Programming for LRA Open-Loop Operation

To configure the DRV2604L device in LRA open-loop operation, the LRA must be selected by writing the

N_ERM_LRA bit to 1 in register 0x1A, and the LRA_OPEN_LOOP bit to 1 in register 0x1D. If PWM interface is

used, the open-loop frequency is given by the PWM frequency divided by 128. If PWM interface is not used, the

open-loop frequency is given by the OL_LRA_PERIOD[6:0] bit in register 0x20.

8.5.5 Programming for Closed-Loop Operation

For closed-loop operation, the device must be calibrated according to the actuator selection. When calibrated

accordingly, the user is only required to provide the desired waveform. The DRV2604L device automatically

adjusts the level and, for the LRA, automatically adjusts the driving frequency.

8.5.6 Auto Calibration Procedure

The calibration engine requires a number of bits as inputs before the engine can be executed (see Figure 24).

When the inputs are configured, the calibration routine can be executed. After calibration execution occurs, the

output parameters are written over the specified register locations. Figure 24 shows all of the required inputs and

generated outputs. To ensure proper auto-resonance operation, the LRA actuator type requires more input

parameters than the ERM. The LRA parameters are ignored when the device is in ERM mode.

Inputs

Outputs

ERM_LRA

BEMF_GAIN[1:0]

A_CAL_COMP[7:0]

A_CAL_BEMF[7:0]

DIAG_RESULT

FB_BRAKE_FACTOR[2:0]

LOOP_GAIN[1:0]

RATED_VOLTAGE[7:0]

OD_CLAMP[7:0]

AUTO_CAL_TIME[1:0]

DRIVE_TIME[4:0]

Auto-calibration engine

SAMPLE_TIME[1:0]

BLANKING_TIME[3:0]

IDISS_TIME[3:0]

LRA

only

ZC_DET_TIME[1:0]

Figure 24. Calibration-Engine Functional Diagram

Variation occurs between different actuators even if the actuators are of the same model. To ensure optimal

results, TI recommends that the calibration routine be run at least once for each actuator. The OTP feature of the

DRV2604L device can store the calibration values. Because of the stored values, the calibration procedure does

not have run every time. Having a single set of calibration register values that can be loaded during the system

initialization is possible.

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Programming (continued)

The following instructions list the step-by-step register configuration for auto-calibration. For additional details see

the Register Map section.

1. Apply the supply voltage to the DRV2604L device, and pull the EN pin high. The supply voltage should allow for

adequate drive voltage of the selected actuator.

2. Write a value of 0x07 to register 0x01. This value moves the DRV2604L device out of STANDBY and places the

MODE[2:0] bits in auto-calibration mode.

3. Populate the input parameters required by the auto-calibration engine:

a. ERM_LRA — selection will depend on desired actuator.

b. FB_BRAKE_FACTOR[2:0] — A value of 2 is valid for most actuators.

c. LOOP_GAIN[1:0] — A value of 2 is valid for most actuators.

d. RATED_VOLTAGE[7:0] — See the Rated Voltage Programming section for calculating the correct register value.

e. OD_CLAMP[7:0] — See the Overdrive Voltage-Clamp Programming section for calculating the correct register value.

f. AUTO_CAL_TIME[1:0] — A value of 3 is valid for most actuators.

g. DRIVE_TIME[3:0] — See the Drive-Time Programming for calculating the correct register value.

h. SAMPLE_TIME[1:0] — A value of 3 is valid for most actuators.

i. BLANKING_TIME[3:0] — A value of 1 is valid for most actuators.

j. IDISS_TIME[3:0] — A value of 1 is valid for most actuators.

k. ZC_DET_TIME[1:0] — A value of 0 is valid for most actuators.

4. Set the GO bit (write 0x01 to register 0x0C) to start the auto-calibration process. When auto calibration is complete, the

GO bit automatically clears. The auto-calibration results are written in the respective registers as shown in Figure 24.

5. Check the status of the DIAG_RESULT bit (in register 0x00) to ensure that the auto-calibration routine is complete

without faults.

6. Evaluate system performance with the auto-calibrated settings. Note that the evaluation should occur during the final

assembly of the device because the auto-calibration process can affect actuator performance and behavior. If any

adjustment is required, the inputs can be modified and this sequence can be repeated. If the performance is satisfactory,

the user can do any of the following:

a. Repeat the calibration process upon subsequent power ups.

b. Store the auto-calibration results in host processor memory and rewrite them to the DRV2604L device upon

subsequent power ups. The device retains these settings when in STANDBY mode or when the EN pin is low.

c. Program the results permanently in nonvolatile, on-chip OTP memory. Even when a device power cycle occurs, the

device retains the auto-calibration settings. See the Programming On-Chip OTP Memory section for additional

information.

8.5.7 Programming On-Chip OTP Memory

The OTP memory can only be written once. To permanently program the OTP memory in registers 0x16 through

0x1A, use the following steps:

1. Write registers 0x16 through 0x1A with the desired configuration and calibration values which provide satisfactory

performance.

2. Ensure that the supply voltage (V_DD) is between 4 V and 4.4 V. This voltage is required for the nonvolatile memory to

program properly.

3. Set the OTP_PROGRAM bit by writing a value of 0x01 to register 0x1E. When the OTP memory is written which can only

occur once in the device, the OTP_STATUS bit (in register 0x1E) only reads 1.

4. Reset the device by power cycling the device or setting the DEV_RESET bit in register 0x01, and then read registers

0x16 to 0x1A to ensure that the programmed values were retained.

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Programming (continued)

8.5.8 Waveform Playback Programming

8.5.8.1 Data Formats for Waveform Playback

The DRV2604L smart-loop architecture has three modes of operation. Each of the modes can drive either ERM

or LRA devices.

1. Open-loop mode

2. Closed-loop mode (unidirectional)

3. Closed-loop mode (bidirectional)

Each mode has different advantages and disadvantages. The DRV2604L device brings new cutting-edge

actuator control with closed-loop operation around the back-EMF for automatic overdrive and braking. However,

some existing haptic implementations already include overdrive and braking that are embedded in the waveform

data. Open-loop mode is used to preserve compatibility with such systems.

The following sections show how the input data for each DRV2604L interface is translated to the output drive

signal.

8.5.8.1.1 Open-Loop Mode

In open-loop mode, the reference level for full-scale drive is set by the OD_CLAMP[7:0] bit in Register 0x17. A

mid-scale input value gives no drive signal, and a less-than mid-scale gives a negative drive value. For an ERM,

a negative drive value results in counter-rotation, or braking. For an LRA, a negative drive value results in a 180-

degree phase shift in commutation.

The RTP mode has 8 bits of resolution over the I²C bus. The RTP data can either be in a signed (2s

complement) or unsigned format as defined by the DATA_FORMAT_RTP bit.

Steady-State

Output Magnitude

Open Loop

ERM_OPEN_LOOP = 1 OR LRA_OPEN_LOOP = 1

OD_CLAMP[7:0]

0 V

-OD_CLAMP[7:0]

Input

Input Interface

0%

50%

0x00

0x7F

100%

0x7F

0xFF

PWM

RTP (8-bit) DATA_FORMAT_RTP = 0

0x81

0x00

RTP (8-bit) DATA_FORMAT_RTP = 1

Figure 25.

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Programming (continued)

8.5.8.1.2 Closed-Loop Mode, Unidirectional

In closed-loop unidirectional mode, the DRV2604L device provides automatic overdrive and braking for both

ERM and LRA actuators. Closed-loop unidirectional mode is the easiest mode to use and understand. Closed-

loop unidirectional mode uses the full 8-bit resolution of the driver. Closed-loop unidirectional mode offers the

best performance; however, the data format is not physically compatible with the open-loop mode data that can

be used in some existing systems

The reference level for steady-state full-scale drive is set by the RATED_VOLTAGE[7:0] bit (when auto-

calibration is performed). The output voltage can momentarily exceed the rated voltage for automatic overdrive

and braking, but does not exceed the OD_CLAMP[7:0] voltage. Braking occurs automatically based on the input

signal when the back-EMF feedback determines that braking is necessary.

Because the system is unidirectional in closed-loop unidirectional mode, only unsigned data should be used. The

RTP mode has 8 bits of resolution over the I²C bus. Setting the DATA_FORMAT_RTP bit to 0 (signed) is not

recommended for closed-loop unidirectional mode.

Steady-State

Output Magnitude

Closed Loop, BIDIR_INPUT = 0

RATED_VOLTAGE[7:0]

½ RATED_VOLTAGE[7:0]

Full Braking

Input

Input Interface

PWM

0%

50%

100%

0xFF

RTP (8-bit) DATA_FORMAT_RTP = 1

0x00

0x7F

Figure 26.

For the RTP interface, set the DATA_FORMAT_RTP bit to 1 (unsigned).

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Programming (continued)

8.5.8.1.3 Closed-Loop Mode, Bidirectional

In closed-loop bidirectional mode, the DRV2604L device provides automatic overdrive and braking for both ERM

and LRA devices. Closed-loop bidirectional mode preserves compatibility with data created in open-loop

signaling by maintaining zero drive-strength at the mid-scale value. When input values less than the mid-scale

value are given, the DRV2604L device interprets them as the same as the mid-scale with zero drive.

The reference level for steady-state full-scale drive is set by the RATED_VOLTAGE[7:0] bit (when auto

calibration is performed). The output voltage can momentarily exceed the rated voltage for automatic overdrive

and braking, but does not exceed the OD_CLAMP[7:0] voltage. Braking occurs automatically based on the input

signal when the back-EMF feedback determines that braking is necessary. Although the Closed-Loop mode

preserves compatibility with existing device data formats, it provides closed loop benefits and is the default

configuration at power up.

The RTP mode has 8 bits of resolution over the I²C bus. The RTP data can either be in signed (2s complement)

or unsigned format as defined by the DATA_FORMAT_RTP bit.

Steady-State

Output Magnitude

Closed Loop, BIDIR_INPUT = 1

RATED_VOLTAGE[7:0]

½ RATED_VOLTAGE[7:0]

Full Braking

Input

Input Interface

0%

50%

0x00

0x7F

75%

0x3F

0xBF

100%

0x7F

0xFF

PWM

RTP (8-bit) DATA_FORMAT_RTP = 0

0x81

0x00

RTP (8-bit) DATA_FORMAT_RTP = 1

Figure 27.

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Programming (continued)

8.5.8.2 Waveform Setup and Playback

Playback of a haptic effect can occur in multiple ways. Using the PWM mode, RTP mode, and analog-input

mode can provide the waveform in real time. The waveforms can also be played from the RAM in which case the

waveform playback engine is used and the waveform is either played by an internal GO bit (register 0x0C), or by

an external trigger.

8.5.8.2.1 Waveform Playback Using RTP Mode

The user can enter the RTP mode by writing the MODE[2:0] bit to 5 in register 0x01. When in RTP mode, the

DRV2604L device drives the actuator continuously with the amplitude specified in the RTP_INPUT[7:0] bit (in

register 0x02). Because the amplitude tracks the value specified in the RTP_INPUT[7:0] bit, the I²C bus can

stream waveforms.

8.5.8.2.2 Waveform Playback Using the Analog-Input Mode

The user can enter the analog-input mode by setting the MODE[2:0] bit to 3 in register 0x01 and by setting the

N_PWM_ANALOG bit to 1 in register 0x1D. When in analog-input mode, the DRV2604L device accepts an

analog voltage at the IN/TRIG pin. The DRV2604L device drives the actuator continuously in analog-input mode

until the user sets the device into STANDBY mode or enters another interface mode. The reference voltage in

analog-input mode is 1.8 V. Therefore a 1.8-V reference voltage is interpreted as a 100% input value, a 0.9-V

reference voltage is interpreted as 50%, and a 0-V reference voltage is interpreted as 0%. The input value is

analogous to the duty-cycle percentage in PWM mode. The interpretation of these percentages varies according

to the selected mode of operation. See the Data Formats for Waveform Playback section for details.

8.5.8.2.3 Waveform Playback Using PWM Mode

The user can enter the PWM mode by setting the MODE[2:0] bit to 3 in register 0x01 and by setting the

N_PWM_ANALOG bit to 0 in register 0x1D. When in PWM mode, the DRV2604L device accepts PWM data at

the IN/TRIG pin. The DRV2604L device drives the actuator continuously in PWM mode until the user sets the

device to STANDBY mode or to enter another interface mode. The interpretation of the duty-cycle information

varies according to the selected mode of operation. See the Data Formats for Waveform Playback section for

details.

8.5.8.2.4 Loading Data to RAM

The DRV2604LL device contains 2 kB of integrated RAM to store customer waveforms. The waveforms are

represented as time-amplitude pairs. Using the playback engine, the waveforms can be recalled, sequenced, and

played through the I²C or an external GPIO trigger.

A library consists of a revision byte (should be set to 0), a header section, and the waveform data content. The

library header defines the data boundaries for each effect ID in the data field, and the waveform data contains a

sequence of time-value pairs that define the effects.

RAM

0x000

Revision

Header

Waveform Data

0x7FF

Figure 28. RAM Memory Structure

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Programming (continued)

8.5.8.2.4.1 Header Format

The header block consist of N-boundary definition blocks of 3 bytes each. N is the number of effects stored in the

RAM. Each of the boundary definition blocks contain the start address (2 bytes) and a configuration byte.

The start address contains the location in the memory where the waveform data associated with this effect

begins. The position of the effect pointer in the header becomes the effect ID. The first effect boundary definition

points to the ID for effect 1, the second definition points to the ID for effect 2, and so on. This resulting effect ID

is the effect ID that is used in the waveform sequencer.

Memory location

Header

Effect ID

0x000

Revision

Start address

upper byte

Start address

lower byte

0x001

0x004

0x007

Configuration byte

Effect 1

Effect 2

Effect 3

Start address

upper byte

Start address

lower byte

Start address

upper byte

Start address

lower byte

Start address

upper byte

Start address

lower byte

(N œ 1) × 3 + 1

Configuration byte

Effect N

Figure 29. Header Structure

The configuration byte contains the following two parameters:

•

The effect size contains the amount of bytes that define the waveform data. An effect size of 0 is an error

state. Any odd-number effect size is an error state because the waveform data is defined as time-value (2

bytes). Therefore, the effect size must be an even number between 2 and 30.

The WAVEFORM_REPEATS[2:0] bit is used to select the number of times the complete waveform is be

played when it is called by the waveform sequencer. A value of 0 is no repeat and the waveform is played

once. A value of 1 means 1 repeat and the waveform is played twice. A value of 7 means infinite repeat until

the GO bit is cleared.

During waveform design, ensure that the appropriate amount of drive time is at zero amplitude on the end of the

waveform so that the waveform stored in the RAM is repeated smoothly.

Configuration byte

Waveform repeats [2:0]

Effect size [4:0]

Figure 30. Header Configuration Byte Structure

8.5.8.2.4.2 RAM Waveform Data Format

The library data contents can take two forms which are voltage-time pair and linear ramp. The voltage-time pair

method implements a set and wait protocol, which is an efficient method of actuator control for most types of

waveforms. This method becomes inefficient when ramping waveforms is desired, therefore a linear ramp

method is also supported which linearly interpolates a set of voltages between two amplitude values. Both

methods require only two bytes of data per set point. The linear ramp method uses a minimum of four bytes so

that linear interpolation can be done to the next set point. The most significant bit of the voltage value is reserved

to indicate the linear ramping mode.

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Programming (continued)

Waveform data

Voltage [6:0]

Time [7:0]

Voltage [6:0]

Time [7:0]

Ramp

Voltage [6:0]

Time [7:0]

Figure 31. Waveform Data Structure

Data is stored as interleaved voltage-time pairs. Voltage in the voltage-time pair is a 7-bit signed number with

range –63 to 63 when in bidirectional mode (BIDIR_INPUT = 1), and a 7-bit unsigned number with a range of 0

to 127 when in unidirectional mode (BIDIR_INPUT = 0). The MSB of the voltage byte is reserved for the linear

ramping mode.

The Time value is the number of ticks that the Voltage will last. The size of the tick depends on the

PLAYBACK_INTERVAL bit (in register 0x1F). If PLAYBACK_INTERVAL = 0 the absolute time is number of ticks

× 5 ms. If PLAYBACK_INTERVAL = 1 the absolute time is number ticks × 1 ms.

When the most significant bit of the Voltage is high, the engine interprets a linear interpolation between that

voltage and the following voltage point. The following voltage point can either be a part of a regular voltage-time

pair, or a subsequent ramp. The following lists the sequence of bytes:

1. Byte1 — Voltage1 (MSB High)

2. Byte2 — Time1

3. Byte3 — Voltage2

4. Byte4 — Time2

The engine creates a linear interpolation between Voltage1 and Voltage2 over the time period Time1, where

Time1 is a number of 5-ms ticks. The start value for the ramp is the 7-bit value contained in Voltage1. The end

amplitude is the 7-bit value contained in Voltage2. The MSB in Voltage2 can indicate a following voltage-time

pair or the starting point in a subsequent ramp.

8.5.8.2.5 Waveform Sequencer

If the user uses pre-stored effects, the effects must first be loaded into the waveform sequencer, and then the

effects can be launched by using any of the trigger options (see the Waveform Triggers section for details).

The waveform sequencer (see the Waveform Sequencer (Address: 0x04 to 0x0B) section) queues waveform-

library identifiers for playback. Eight sequence registers queue up to eight library waveforms for sequential

playback. A waveform identifier is an integer value referring to the index position of a waveform in the RAM

library. Playback begins at register address 0x04 when the user asserts the GO bit (register 0x0C). When

playback of that waveform ends, the waveform sequencer plays the next waveform identifier held in register

0x05, if the next waveform is non-zero. The waveform sequencer continues in this way until the sequencer

reaches an identifier value of zero or until all eight identifiers are played (register addresses 0x04 through 0x0B),

whichever comes first.

The waveform identifier range is 1 to 127. The MSB of each sequence register can be used to implement a delay

between sequence waveforms. When the MSB is high, bits 6-0 indicate the length of the wait time. The wait time

for that step then becomes WAV_FRM_SEQ[6:0] × 10 ms.

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Programming (continued)

GO

Waveform Sequencer

WAV_FRM_SEQ0[7:0]

WAV_FRM_SEQ1[7:0]

WAV_FRM_SEQ2[7:0]

WAV_FRM_SEQ3[7:0]

WAV_FRM_SEQ4[7:0]

WAV_FRM_SEQ5[7:0]

WAV_FRM_SEQ6[7:0]

WAV_FRM_SEQ7[7:0]

RAM

Effect 1

Effect 2

Effect 3

Effect 4

Effect 5

Effect N

Figure 32. Waveform Sequencer Programming

8.5.8.2.6 Waveform Triggers

When the waveform sequencer has the effect (or effects) loaded, the waveform sequencer can be triggered by

an internal trigger, external trigger (edge), or external trigger (level). To trigger using the internal trigger set the

MODE[2:0] bit to 0 in register 0x01. To trigger using the external trigger (edge), set the MODE[2:0] bit to 1 and

then follow the trigger instructions listed in the Edge Trigger section. To trigger using the external trigger (level),

set the MODE[2:0] bit to 2 and then follow the trigger instructions listed in the Level Trigger section.

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8.6.1 Status (Address: 0x00)

Figure 33. Status Register

7

6

5

4

3

2

1

0

DEVICE_ID[2:0]

RO-1

ILLEGAL_ADDR

RO-0

DIAG_RESULT

RO-0

Reserved

OVER_TEMP

RO-0

OC_DETECT

RO-0

RO-1

RO-0

Table 3. Status Register Field Descriptions

BIT FIELD

TYPE

DEFAULT

DESCRIPTION

7-5 DEVICE_ID[2:0]

RO

6

Device identifier. The DEVICE_ID bit indicates the part number to the user.

The user software can ascertain the device capabilities by reading this

register.

3: DRV2605 (contains licensed ROM library, does not contain RAM)

4: DRV2604 (contains RAM, does not contain licensed ROM library)

6: DRV2604L (low-voltage version of the DRV2604 device)

7: DRV2605L (low-voltage version of the DRV2605 device)

4

3

ILLEGAL_ADDR

DIAG_RESULT

RO

0

This flag will indicate if a user programming error to the RAM has occurred.

The bit is set when the user tries to read or write memory outside of the

RAM address range, or if the user instructs the device to play an odd

number of bytes

This flag stores the result of the auto-calibration routine and the diagnostic

routine. The flag contains the result for whichever routine was executed

last. The flag clears upon read. Test result is not valid until the GO bit self-

clears at the end of the routine.

Auto-calibration mode:

0: Auto-calibration passed (optimum result converged)

1: Auto-calibration failed (result did not converge)

Diagnostic mode:

0: Actuator is functioning normally

1: Actuator is not present or is shorted, timing out, or giving

out–of-range back-EMF

2

1

Reserved

OVER_TEMP

RO

0

Latching overtemperature detection flag. If the device becomes too hot, it

shuts down. This bit clears upon read.

0: Device is functioning normally

1: Device has exceeded the temperature threshold

0

OC_DETECT

Latching overcurrent detection flag. If the load impedance is below the

load-impedance threshold, the device shuts down and periodically attempts

to restart until the impedance is above the threshold.

0: No overcurrent event is detected

1: Overcurrent event is detected

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8.6.2 Mode (Address: 0x01)

Figure 34. Mode Register

7

6

5

4

3

2

1

0

DEV_RESET

R/W-0

STANDBY

R/W-1

Reserved

MODE[2:0]

R/W-0

Table 4. Mode Register Field Descriptions

BIT FIELD

TYPE

DEFAULT

DESCRIPTION

7

DEV_RESET

R/W

0

Device reset. Setting this bit performs the equivalent operation of power

cycling the device. Any playback operations are immediately interrupted,

and all registers are reset to the default values. The DEV_RESET bit self-

clears after the reset operation is complete.

6

STANDBY

R/W

1

0

Software standby mode

0: Device ready

1: Device in software standby

5-3 Reserved

2-0 MODE

0: Internal trigger

Waveforms are fired by setting the GO bit in register 0x0C.

1: External trigger (edge mode)

A rising edge on the IN/TRIG pin sets the GO Bit. A second rising

edge on the IN/TRIG pin cancels the waveform if the second rising

edge occurs before the GO bit has cleared.

2: External trigger (level mode)

The GO bit follows the state of the external trigger. A rising edge on

the IN/TRIG pin sets the GO bit, and a falling edge sends a cancel. If

the GO bit is already in the appropriate state, no change occurs.

3: PWM input and analog input

A PWM or analog signal is accepted at the IN/TRIG pin and used as

the driving source. The device actively drives the actuator while in

this mode. The PWM or analog input selection occurs by using the

N_PWM_ANALOG bit.

4: Reserved.

5: Real-time playback (RTP mode)

The device actively drives the actuator with the contents of the

RTP_INPUT[7:0] bit in register 0x02.

6: Diagnostics

Set the device in this mode to perform a diagnostic test on the

actuator. The user must set the GO bit to start the test. The test is

complete when the GO bit self-clears. Results are stored in the

DIAG_RESULT bit in register 0x00.

7: Auto calibration

Set the device in this mode to auto calibrate the device for the

actuator. Before starting the calibration, the user must set the all

required input parameters. The user must set the GO bit to start the

calibration. Calibration is complete when the GO bit self-clears. For

more information see the Auto Calibration Procedure section.

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8.6.3 Real-Time Playback Input (Address: 0x02)

Figure 35. Real-Time Playback Input Register

7

6

5

4

3

2

1

0

RTP_INPUT[7:0]

R/W-0

Table 5. Real-Time Playback Input Register Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

7-0

RTP_INPUT[7:0]

R/W

0

This field is the entry point for real-time playback (RTP) data. The

DRV2604L playback engine drives the RTP_INPUT[7:0] value to the load

when MODE[2:0] = 5 (RTP mode). The RTP_INPUT[7:0] value can be

updated in real-time by the host controller to create haptic waveforms. The

RTP_INPUT[7:0] value is interpreted as signed by default, but can be set to

unsigned by the DATA_FORMAT_RTP bit in register 0x1D. When the

haptic waveform is complete, the user can idle the device by setting

MODE[2:0] = 0, or alternatively by setting STANDBY = 1.

8.6.4 HI_Z (Address: 0x03)

Figure 36. HI_Z Register

7

6

5

4

3

2

1

0

Reserved

HI_Z

R/W-0

Reserved

Table 6. HI_Z Register Field Descriptions

BIT FIELD

TYPE

DEFAULT

DESCRIPTION

7-5 Reserved

4

HI_Z

R/W

0

This bit sets the output driver into a true high-impedance state. The device

must be enabled to go into the high-impedance state. When in hardware

shutdown or standby mode, the output drivers have 15 kO to ground. When

the HI_Z bit is asserted, the hi-Z functionality takes effect immediately, even

if a transaction is taking place.

3-0 Reserved

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8.6.5 Waveform Sequencer (Address: 0x04 to 0x0B)

Figure 37. Waveform Sequencer Register

7

6

5

4

3

2

1

0

WAIT

R/W-0

WAV_FRM_SEQ[6:0]

R/W-0

Table 7. Waveform Sequencer Register Field Descriptions

BIT FIELD

TYPE

DEFAULT

DESCRIPTION

7

WAIT

R/W

0

When this bit is set, the WAV_FRM_SEQ[6:0] bit is interpreted as a wait

time in which the playback engine idles. This bit is used to insert timed

delays between sequentially played waveforms.

Delay time = 10 ms × WAV_FRM_SEQ[6:0]

If WAIT = 0, then WAV_FRM_SEQ[6:0] is interpreted as a waveform

identifier for sequence playback.

6-0 WAV_FRM_SEQ

R/W

0

Waveform sequence value. This bit holds the waveform identifier of the

waveform to be played. A waveform identifier is an integer value referring

to the index position of a waveform in the RAM library. Playback begins at

register address 0x04 when the user asserts the GO bit (register 0x0C).

When playback of that waveform ends, the waveform sequencer plays the

next waveform identifier held in register 0x05, if the next waveform

identifier is non-zero. The waveform sequencer continues in this way until

the sequencer reaches an identifier value of zero, or all eight identifiers are

played (register addresses 0x04 through 0x0B), whichever comes first.

8.6.6 GO (Address: 0x0C)

Figure 38. GO Register

7

6

5

4

3

2

1

0

Reserved

GO

R/W-0

Table 8. GO Register Field Descriptions

BIT

7-1

0

FIELD

Reserved

GO

TYPE

DEFAULT

DESCRIPTION

R/W

0

This bit is used to fire processes in the DRV2604L device. The process

fired by the GO bit is selected by the MODE[2:0] bit (register 0x01). The

primary function of this bit is to fire playback of the waveform identifiers in

the waveform sequencer (registers 0x04 to 0x0B), in which case, this bit

can be thought of a software trigger for haptic waveforms. The GO bit

remains high until the playback of the haptic waveform sequence is

complete. Clearing the GO bit during waveform playback cancels the

waveform sequence. Using one of the external trigger modes can cause

the GO bit to be set or cleared by the external trigger pin. This bit can also

be used to fire the auto-calibration process or the diagnostic process.

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8.6.7 Overdrive Time Offset (Address: 0x0D)

Figure 39. Overdrive Time Offset Register

7

6

5

4

3

2

1

0

ODT[7:0]

R/W-0

Table 9. Overdrive Time Offset Register Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

7-0

ODT

R/W

0

This bit adds

a time offset to the overdrive portion of the library

waveforms. Some motors require more overdrive time than others,

therefore this register allows the user to add or remove overdrive time

from the library waveforms. The maximum voltage value in the library

waveform is automatically determined to be the overdrive portion. This

register is only useful in open-loop mode. Overdrive is automatic for

closed-loop mode. The offset is interpreted as 2s complement, therefore

the time offset can be positive or negative.

Overdrive Time Offset (ms) = ODT[7:0] × PLAYBACK_INTERVAL

8.6.8 Sustain Time Offset, Positive (Address: 0x0E)

Figure 40. Sustain Time Offset, Positive Register

7

6

5

4

3

2

1

0

SPT[7:0]

R/W-0

Table 10. Sustain Time Offset, Positive Register Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

7-0

SPT

R/W

0

This bit adds a time offset to the positive sustain portion of the library

waveforms. Some motors have a faster or slower response time than

others, therefore this register allows the user to add or remove positive

sustain time from the library waveforms. Any positive voltage value other

than the overdrive portion is considered as a sustain positive value. The

offset is interpreted as 2s complement, therefore the time offset can positive

or negative.

Sustain-Time Positive Offset (ms) = SPT[7:0] ×

PLAYBACK_INTERVAL

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8.6.9 Sustain Time Offset, Negative (Address: 0x0F)

Figure 41. Sustain Time Offset, Negative Register

7

6

5

4

3

2

1

0

SNT[7:0]

R/W-0

Table 11. Sustain Time Offset, Negative Register Field Descriptions

BIT

FIELD

TYPE

DEFAULT

DESCRIPTION

7-0

SNT

R/W

0

This bit adds a time offset to the negative sustain portion of the library

waveforms. Some motors have a faster or slower response time than

others, therefore this register allows the user to add or remove negative

sustain time from the library waveforms. Any negative voltage value other

than the overdrive portion is considered as a sustaining negative value. The

offset is interpreted as two’s complement, therefore the time offset can be

positive or negative.

Sustain-Time Negative Offset (ms) = SNT[7:0] ×

PLAYBACK_INTERVAL

8.6.10 Brake Time Offset (Address: 0x10)

Figure 42. Brake Time Offset Register

7

6

5

4

3

2

1

0

BRT[7:0]

R/W-0

Table 12. Brake Time Offset Register Field Descriptions

BIT

FIELD

TYPE

DEFAULT DESCRIPTION

7-0

BRT

R/W

0

This bit adds a time offset to the braking portion of the library waveforms.

Some motors require more braking time than others, therefore this register

allows the user to add or take away brake time from the library waveforms.

The most negative voltage value in the library waveform is automatically

determined to be the braking portion. This register is only useful in open-loop

mode. Braking is automatic for closed-loop mode. The offset is interpreted as

2s complement, therefore the time offset can be positive or negative.

Brake Time Offset (ms) = BRT[7:0] × PLAYBACK_INTERVAL

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8.6.11 Rated Voltage (Address: 0x16)

Figure 43. Rated Voltage Register

7

6

5

4

3

2

1

0

RATED_VOLTAGE[7:0]

R/W-0

R/W-1

R/W-0

Table 13. Rated Voltage Register Field Descriptions

BIT FIELD

TYPE

DEFAULT

DESCRIPTION

7-0 RATED_VOLTAGE[7:0]

R/W

0x3E

This bit sets the reference voltage for full-scale output during closed-loop

operation. The auto-calibration routine uses this register as an input, therefore

this register must be written with the rated voltage value of the motor before

calibration is performed. This register is ignored for open-loop operation

because the overdrive voltage sets the reference for that case. Any

modification of this register value should be followed by calibration to set

A_CAL_BEMF appropriately.

See the Rated Voltage Programming section for calculating the correct register

value.

8.6.12 Overdrive Clamp Voltage (Address: 0x17)

Figure 44. Overdrive Clamp Voltage Register

7

6

5

4

3

2

1

0

OD_CLAMP[7:0]

R/W-1

R/W-0

R/W-1

R/W-0

R/W-1

Table 14. Overdrive Clamp Voltage Register Field Descriptions

BIT

FIELD

OD_CLAMP[7:0]

TYPE

DEFAULT

DESCRIPTION

7

R/W

0x9B

During closed-loop operation the actuator feedback allows the output voltage

to go above the rated voltage during the automatic overdrive and automatic

braking periods. This register sets a clamp so that the automatic overdrive is

bounded. This bit also serves as the full-scale reference voltage for open-loop

operation.

See the Overdrive Voltage-Clamp Programming section for calculating the

correct register value.

8.6.13 Auto-Calibration Compensation Result (Address: 0x18)

Figure 45. Auto-Calibration Compensation-Result Register

7

6

5

4

3

2

1

0

A_CAL_COMP[7:0]

R/W-0

R/W-1

R/W-0

Table 15. Auto-Calibration Compensation-Result Register Field Descriptions

BIT

FIELD

A_CAL_COMP[7:0]

TYPE

DEFAULT

DESCRIPTION

7-0

R/W

0x0C

This register contains the voltage-compensation result after execution of auto

calibration. The value stored in the A_CAL_COMP bit compensates for any

resistive losses in the driver. The calibration routine checks the impedance of

the actuator to automatically determine an appropriate value. The auto-

calibration compensation-result value is multiplied by the drive gain during

playback.

Auto-calibration compensation coefficient = 1 + A_CAL_COMP[7:0] / 255

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8.6.14 Auto-Calibration Back-EMF Result (Address: 0x19)

Figure 46. Auto-Calibration Back-EMF Result Register

7

6

5

4

3

2

1

0

A_CAL_BEMF[7:0]

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

Table 16. Auto-Calibration Back-EMF Result Register Field Descriptions

BIT FIELD

TYPE

DEFAULT

DESCRIPTION

7-0 A_CAL_BEMF[7:0]

R/W

0x6C

This register contains the rated back-EMF result after execution of auto

calibration. The A_CAL_BEMF[7:0] bit is the level of back-EMF voltage that the

actuator gives when the actuator is driven at the rated voltage. The DRV2604L

playback engine uses this the value stored in this bit to automatically determine

the appropriate feedback gain for closed-loop operation.

Auto-calibration back-EMF (V) = (A_CAL_BEMF[7:0] / 255) × 1.22 V /

BEMF_GAIN[1:0]

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8.6.15 Feedback Control (Address: 0x1A)

Figure 47. Feedback Control Register

7

6

5

4

3

2

1

0

N_ERM_LRA

R/W-0

FB_BRAKE_FACTOR[2:0]

R/W-1

LOOP_GAIN[1:0]

BEMF_GAIN[1:0]

R/W-0

R/W-1

R/W-0

R/W-1

Table 17. Feedback Control Register Field Descriptions

BIT FIELD

TYPE

DEFAULT

DESCRIPTION

7

N_ERM_LRA

R/W

0

This bit sets the DRV2604L device in ERM or LRA mode. This bit should be set

prior to running auto calibration.

0: ERM Mode

1: LRA Mode

6-4 FB_BRAKE_FACTOR[2:0]

R/W

3

This bit selects the feedback gain ratio between braking gain and driving gain.

In general, adding additional feedback gain while braking is desirable so that the

actuator brakes as quickly as possible. Large ratios provide less-stable

operation than lower ones. The advanced user can select to optimize this

register. Otherwise, the default value should provide good performance for most

actuators. This value should be set prior to running auto calibration.

0: 1x

1: 2x

2: 3x

3: 4x

4: 6x

5: 8x

6: 16x

7: Braking disabled

3-2 LOOP_GAIN[1:0]

R/W

1

This bit selects a loop gain for the feedback control. The LOOP_GAIN[1:0] bit

sets how fast the loop attempts to make the back-EMF (and thus motor velocity)

match the input signal level. Higher loop-gain (faster settling) options provide

less-stable operation than lower loop gain (slower settling). The advanced user

can select to optimize this register. Otherwise, the default value should provide

good performance for most actuators. This value should be set prior to running

auto calibration.

0: Low

1: Medium (default)

2: High

3: Very High

1-0 BEMF_GAIN[1:0]

R/W

2

This bit sets the analog gain of the back-EMF amplifier. This value is interpreted

differently between ERM mode and LRA mode. Auto calibration automatically

populates the BEMF_GAIN bit with the most appropriate value for the actuator.

ERM Mode

0: 0.255x

1: 0.7875x

2: 1.365x (default)

3: 3.0x

LRA Mode

0: 3.75x

1: 7.5x

2: 15x (default)

3: 22.5x

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8.6.16 Control1 (Address: 0x1B)

Figure 48. Control1 Register

7

6

5

4

3

2

1

0

STARTUP_BOOST

R/W-1

Reserved

AC_COUPLE

R/W-0

DRIVE_TIME[4:0]

R/W-0

R/W-1

R/W-0

R/W-1

Table 18. Control1 Register Field Descriptions

BIT FIELD

TYPE

DEFAULT DESCRIPTION

7

STARTUP_BOOST

R/W

1

This bit applies higher loop gain during overdrive to enhance actuator transient

response.

6

5

Reserved

AC_COUPLE

R/W

0

This bit applies a 0.9-V common mode voltage to the IN/TRIG pin when an AC-

coupling capacitor is used. This bit is only useful for analog input mode. This bit

should not be asserted for PWM mode or external trigger mode.

0: Common-mode drive disabled for DC-coupling or digital inputs modes

1: Common-mode drive enabled for AC coupling

4-0 DRIVE_TIME[4:0]

R/W

0x13

LRA Mode: Sets initial guess for LRA drive-time in LRA mode. Drive time is

automatically adjusted for optimum drive in real time; however, this register

should be optimized for the approximate LRA frequency. If the bit is set too low,

it can affect the actuator startup time. If the bit is set too high, it can cause

instability.

Optimum drive time (ms) ≈ 0.5 × LRA Period

Drive time (ms) = DRIVE_TIME[4:0] × 0.1 ms + 0.5 ms

ERM Mode: Sets the sample rate for the back-EMF detection. Lower drive times

cause higher peak-to-average ratios in the output signal, requiring more supply

headroom. Higher drive times cause the feedback to react at a slower rate.

Drive Time (ms) = DRIVE_TIME[4:0] × 0.2 ms + 1 ms

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8.6.17 Control2 (Address: 0x1C)

Figure 49. Control2 Register

7

6

5

4

3

2

1

0

BIDIR_INPUT

BRAKE_STABILIZE

R

SAMPLE_TIME[1:0]

R/W-1

BLANKING_TIME[1:0]

IDISS_TIME[1:0]

R/W-1

R/W-0

R/W-1

R/W-0

R/W-1

Table 19. Control2 Register Field Descriptions

BIT FIELD

TYPE

DEFAULT

DESCRIPTION

7

BIDIR_INPUT

R/W

1

The BIDIR_INPUT bit selects how the engine interprets data.

0: Unidirectional input mode

Braking is automatically determined by the feedback conditions and is

applied when required. Use of this mode also recovers an additional bit

of vertical resolution. This mode should only be used for closed-loop

operation.

Examples::

0% Input ? No output signal

50% Input ? Half-scale output signal

100% Input ? Full-scale output signal

1: Bidirectional input mode (default)

This mode is compatible with traditional open-loop signaling and also

works well with closed-loop mode. When operating closed-loop, braking

is automatically determined by the feedback conditions and applied

when required. When operating open-loop modes, braking is only

applied when the input signal is less than 50%.

Open-loop mode (ERM and LRA) examples:

0% Input ? Negative full-scale output signal (braking)

25% Input ? Negative half-scale output signal (braking)

50% Input ? No output signal

75% Input ? Positive half-scale output signal

100% Input ? Positive full-scale output signal

Closed-loop mode (ERM and LRA) examples:

0% to 50% Input ? No output signal

50% Input ? No output signal

75% Input ? Half-scale output signal

100% Input ? Full-scale output signal

6

BRAKE_STABILIZER

R/W

1

3

When this bit is set, loop gain is reduced when braking is almost complete to

improve loop stability

5-4 SAMPLE_TIME[1:0]

LRA auto-resonance sampling time (Advanced use only)

0: 150 µs

1: 200 µs

2: 250 µs

3: 300 µs

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Table 19. Control2 Register Field Descriptions (continued)

BIT FIELD

TYPE

DEFAULT

DESCRIPTION

3-2 BLANKING_TIME[1:0]

R/W

1

Blanking time before the back-EMF AD makes a conversion. (Advanced use only)

Blanking time for LRA has an additional 2 bits (BLANKING_TIME[3:2]) located in

register 0x1F. Depending on the status of N_ERM_LRA the blanking time

represents different values.

N_ERM_LRA = 0 (ERM mode)

0: 45 µs

1: 75 µs

2: 150 µs

3: 225 µs

N_ERM_LRA = 1(LRA mode)

0: 15 µs

1: 25 µs

2: 50 µs

3: 75 µs

4: 90 µs

5: 105 µs

6: 120 µs

7: 135 µs

8: 150 µs

9: 165 µs

10: 180 µs

11: 195 µs

12: 210 µs

13: 235 µs

14: 260 µs

15: 285 µs

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Table 19. Control2 Register Field Descriptions (continued)

BIT FIELD

TYPE

DEFAULT

DESCRIPTION

1-0 IDISS_TIME[1:0]

R/W

1

Current dissipation time. This bit is the time allowed for the current to dissipate

from the actuator between PWM cycles for flyback mitigation. (Advanced use

only)

the current dissipation time for LRA has an additional 2 bits (IDISS_TIME[3:2])

located in register 0x1F. Depending on the status of N_ERM_LRA the idiss time

represents different values

N_ERM_LRA = 0 (ERM mode)

0: 45 µs

1: 75 µs

2: 150 µs

3: 225 µs

N_ERM_LRA = 1(LRA mode)

0: 15 µs

1: 25 µs

2: 50 µs

3: 75 µs

4: 90 µs

5: 105 µs

6: 120 µs

7: 135 µs

8: 150 µs

9: 165 µs

10: 180 µs

11: 195 µs

12: 210 µs

13: 235 µs

14: 260 µs

15: 285 µs

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8.6.18 Control3 (Address: 0x1D)

Figure 50. Control3 Register

7

6

5

4

3

2

1

0

NG_THRESH[1:0]

ERM_OPEN_LOOP

SUPPLY_COMP_DI DATA_FORMAT_RT LRA_DRIVE_MODE

N_PWM_ANALOG

LRA_OPEN_LOOP

S

P

R/W-1

R/W-0

Table 20. Control3 Register Field Descriptions

BIT

FIELD

TYPE

DEFAULT

DESCRIPTION

7-6 NG_THRESH[1:0]

R/W

2

0

This bit is the noise-gate threshold for PWM and analog inputs.

0: Disabled

1: 2%

2: 4% (Default)

3: 8%

5

4

ERM_OPEN_LOOP

This bit selects mode of operation while in ERM mode. Closed-loop operation is

usually desired for because of automatic overdrive and braking properties.

However, many existing waveform libraries were designed for open-loop

operation, therefore open-loop operation can be required for compatibility.

0: Closed Loop

1: Open Loop

SUPPLY_COMP_DIS

This bit disables supply compensation. The DRV2604L device generally

provides constant drive output over variation in the power supply input (V_DD). In

some systems, supply compensation can have already been implemented

upstream, therefore disabling the DRV2604L supply compensation can be

useful.

0: Supply compensation enabled

1: Supply compensation disabled

3

2

DATA_FORMAT_RTP

LRA_DRIVE_MODE

R/W

0

This bit selects the input data interpretation for RTP (Real-Time Playback)

mode.

0: Signed

1: Unsigned

This bit selects the drive mode for the LRA algorithm. This bit determines how

often the drive amplitude is updated. Updating once per cycle provides a

symmetrical output signal, while updating twice per cycle provides more precise

control.

0: Once per cycle

1: Twice per cycle

1

0

N_PWM_ANALOG

R/W

0

This bit selects the input mode for the IN/TRIG pin when MODE[2:0] = 3. In

PWM input mode, the duty cycle of the input signal determines the amplitude of

the waveform. In analog input mode, the amplitude of the input determines the

amplitude of the waveform.

0: PWM Input

1: Analog Input

LRA_OPEN_LOOP

This bit selects an open-loop drive option for LRA Mode. When asserted, the

playback engine drives the LRA at the selected frequency independently of the

resonance frequency. In PWM input mode, the playback engine recovers the

LRA commutation frequency from the PWM input, dividing the frequency by

128. Therefore the PWM input frequency must be equal to 128 times the

resonant frequency of the LRA.

In RTP, RAM mode, the frequency is set by the OL_LRA_PERIOD[6:0] bit.

Open-loop mode is not supported if analog input mode is selected.

0: Auto-resonance mode

1: LRA open-loop mode

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8.6.19 Control4 (Address: 0x1E)

Figure 51. Control4 Register

7

6

5

4

3

2

OTP_STATUS

R-0

1

0

ZC_DET_TIME[1]

R/W-0

ZC_DET_TIME[0]

R/W-0

AUTO_CAL_TIME[1:0]

Reserved

OTP_PROGRAM

R/W-0

R/W-1

R/W-0

Table 21. Control4 Register Field Descriptions

BIT

7-6

FIELD

TYPE

DEFAULT

DESCRIPTION

ZC_DET_TIME[1:0]

R/W

0

This bit sets the minimum length of time devoted for detecting a zero crossing

(advanced use only).

0: 100 µs

1: 200 µs

2: 300 µs

3: 390 µs

5-4

AUTO_CAL_TIME[1:0]

R/W

2

This bit sets the length of the auto calibration time. The AUTO_CAL_TIME[1:0]

bit should be enough time for the motor acceleration to settle when driven at the

RATED_VOLTAGE[7:0] value.

0: 150 ms (minimum), 350 ms (maximum)

1: 250 ms (minimum), 450 ms (maximum)

2: 500 ms (minimum), 700 ms (maximum)

3: 1000 ms (minimum), 1200 ms (maximum)

3

2

Reserved

OTP_STATUS

R

0

OTP Memory status

0: OTP Memory has not been programmed

1: OTP Memory has been programmed

1

0

Reserved

OTP_PROGRAM

R/W

This bit launches the programming process for one-time programmable (OTP)

memory which programs the contents of register 0x16 through 0x1A into

nonvolatile memory. This process can only be executed one time per device.

See the Programming On-Chip OTP Memory section for details.

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8.6.20 Control5 (Address: 0x1F)

Figure 52. Control5 Register

7

6

5

4

3

2

1

0

AUTO_OL_CNT[1:0]

LRA_AUTO_OPEN_ PLAYBACK_INTER

BLANKING_TIME[3:2]

IDISS_TIME[3:2]

LOOP

VAL

R/W-1

R/W-0

RW-0

Table 22. Control5 Register Field Descriptions

BIT

FIELD

TYPE

DEFAULT

DESCRIPTION

7-6

AUTO_OL_CNT[1:0]

R/W

2

This bit selects number of cycles required to attempt synchronization before

transitioning to open loop when the LRA_AUTO_OPEN_LOOP bit is asserted,

0: 3 attempts

1: 4 attempts

2: 5 attempts

3: 6 attempts

5

4

LRA_AUTO_OPEN_LOOP

PLAYBACK_INTERVAL

R/W

0

This bit selects the automatic transition to open-loop drive when a back-EMF

signal is not detected (LRA only).

0: Never transitions to open loop

1: Automatically transitions to open loop

This bit selects the memory playback interval.

0: 5 ms

1: 1 ms

3-2

1-0

BLANKING_TIME[3:2]

IDISS_TIME[3:2]

R/W

0

This bit sets the MSB for the BLANKING_TIME[3:0]. See the

BLANKING_TIME[3:0] bit in the Control2 (Address: 0x1C) section for details.

Advanced use only.

This bit sets the MSB for IDISS_TIME[3:0]. See the IDISS_TIME[1:0] bit in the

Control2 (Address: 0x1C) section for details. Advanced use only.

8.6.21 LRA Open Loop Period (Address: 0x20)

Figure 53. LRA Open Loop Period Register

7

6

5

4

3

2

1

0

Reserved

OL_LRA_PERIOD[6:0]

R/W-0

Table 23. LRA Open Loop Period Register Field Descriptions

BIT

FIELD

TYPE

R/W

DEFAULT

DESCRIPTION

7-0 OL_LRA_PERIOD[6:0]

0

This bit sets the period to be used for driving an LRA when open-loop mode is

selected.

LRA open-loop period (µs) = OL_LRA_PERIOD[6:0] × 98.46 µs

8.6.22 V_(BAT)Voltage Monitor (Address: 0x21)

Figure 54. V_(BAT)Voltage-Monitor Register

7

6

5

4

3

2

1

0

VBAT[7:0]

R/W-0

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Table 24. V_(BAT)Voltage-Monitor Register Field Descriptions

BIT

FIELD

TYPE

DEFAULT

DESCRIPTION

7-0

VBAT[7:0]

R/W

0

This bit provides a real-time reading of the supply voltage at the V_DDpin. The

device must be actively sending a waveform to take a reading.

V_DD(V) = VBAT[7:0] × 5.6V / 255

8.6.23 LRA Resonance Period (Address: 0x22)

Figure 55. LRA Resonance-Period Register

7

6

5

4

3

2

1

0

LRA_PERIOD[7:0]

R/W-0

Table 25. LRA Resonance-Period Register Field Descriptions

BIT

FIELD

TYPE

DEFAULT

DESCRIPTION

7-0

LRA_PERIOD[7:0]

R/W

0

This bit reports the measurement of the LRA resonance period. The device must

be actively sending a waveform to take a reading.

LRA period (us) = LRA_Period[7:0] × 98.46 µs

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8.6.24 RAM-Address Upper Byte (Address: 0xFD)

Figure 56. RAM-Address Upper-Byte Register

7

6

5

4

3

2

1

0

RAM_ADDR_UB[7:0]

R/W-0

Table 26. RAM-Address Upper-Byte Register Field Descriptions

BIT FIELD

TYPE

DEFAULT

DESCRIPTION

7-0 RAM_ADDR_UB[7:0]

R/W

0

The content of this bit is the upper byte for the waveform RAM Address entry.

8.6.25 RAM-Address Lower Byte (Address: 0xFE)

Figure 57. RAM-Address Lower Byte Register

7

6

5

4

3

2

1

0

RAM_ADDR_LB[7:0]

R/W-0

Table 27. RAM Address Lower Byte Register Field Descriptions

BIT

FIELD

TYPE

DEFAULT

DESCRIPTION

7-0

RAM_ADDR_LB[7:0]

R/W

0

The content of this bit is the lower byte for the waveform RAM address entry.

8.6.26 RAM Data Byte (Address: 0xFF)

Figure 58. RAM-Data Byte Register

7

6

5

4

3

2

1

0

RAM_DATA[7:0]

R/W-0

Table 28. RAM-Data Byte Register Field Descriptions

BIT

FIELD

TYPE

DEFAULT

DESCRIPTION

7-0

RAM_DATA[7:0]

R/W

0

Data entry to waveform RAM interface. The user can perform single-byte writes

or multi-byte writes to this register. The controller starts the write at the address

(RAM_ADDR_UB:RAM_ADDR_LB). For both single-byte and multi-byte writes,

the controller automatically increments the RAM address register for each byte

written to the RAM data register.

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The typical application for a haptic driver is in a touch-enabled system that already has an application processor

which makes the decision on when to execute haptic effects.

The DRV2604L device can be used fully with I²C communications (either using RTP or the memory interface). A

system designer can chose to use external triggers to play low-latency effects (such as from a physical button) or

can decide to use the PWM interface. Figure 59 shows a typical haptic system implementation. The system

designer should not use the internal regulator (REG) to power any external load.

DRV2604L

Application

Processor

OUT+

REG

C

(REG)

LRA or

ERM

SCL

SDA

EN

M

SDA

GPIO

OUTœ

2 V œ 5.2 V

V

DD

C

(VDD)

PWM/GPIO

IN/TRIG

GND

Figure 59. I²C Control with Optional PWM Input or External Trigger

Table 29. Recommended External Components

COMPONENT

C_(VDD)

DESCRIPTION

SPECIFICATION

Capacitance

Resistance

TYPICAL VALUE

Input capacitor

1 µF

C_(REG)

Regulator capacitor

Pullup resistor

R_(PU)

2.2 kΩ

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9.2 Typical Application

A typical application of the DRV2604L device is in a system that has external buttons which fire different haptic

effects when pressed. Figure 60 shows a typical schematic of such a system. The buttons can be physical

buttons, capacitive-touch buttons, or GPIO signals coming from the touch-screen system.

Effects in this type of system are programmable.

TPS73633

OUT

IN

NR/FB

EN

GND

C

(LDO)

1 µF

R

(PU)

2.2 kΩ

(PU)

2.2 kΩ

DRV2604L

MSP430G2553

OUT+

REG

C

(REG)

1 µF

LRA or

M

ERM

AVCC

DVCC

P1.6/SCL

P1.7/SDA

P3.1

SCL

C

(VCC)

0.1 µF

R

(SBW)

9.76 kΩ

SDA

OUT–

SBWTDIO

SBWTCK

Programming

EN

V

DD

C

(VDD)

1 µF

Li-ion

Captouch

Buttons

P2.0

P2.1

IN/TRIG

GND

AVSS

DVSS

Figure 60. Typical Application Schematic

9.2.1 Design Requirements

For this design example, use the values listed in Table 30 as the input parameters.

Table 30. Design Parameters

DESIGN PARAMETER

Interface

EXAMPLE VALUE

I²C, external trigger

Actuator type

LRA, ERM

Input power source

Li-ion/Li-polymer, 5-V boost

9.2.2 Detailed Design Procedure

9.2.2.1 Actuator Selection

The actuator decision is based on many factors including cost, form factor, vibration strength, power-

consumption requirements, haptic sharpness requirements, reliability, and audible noise performance. The

actuator selection is one of the most important design considerations of a haptic system and therefore the

actuator should be the first component to consider when designing the system. The following sections list the

basics of ERM and LRA actuators.

9.2.2.1.1 Eccentric Rotating-Mass Motors (ERM)

Eccentric rotating-mass motors (ERMs) are typically DC-controlled motors of the bar or coin type. ERMs can be

driven in the clockwise direction or counter-clockwise direction depending on the polarity of voltage across the

two pins. Bidirectional drive is made possible in a single-supply system by differential outputs that are capable of

sourcing and sinking current. The bidirectional drive feature helps eliminate long vibration tails which are

undesirable in haptic feedback systems.

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I

L

I

L

OUT+

+

œ

Motor-spin

direction

Motor-spin

direction

V

O

œ

+

OUTœ

I

L

I

L

Figure 61. Motor Spin Direction in ERM Motors

Another common approach to driving DC motors is the concept of overdrive voltage. To overcome the inertia of

the mass of the motor, the DC motors are often overdriven for a short amount of time before returning to the

rated voltage of the motor to sustain the rotation of the motor. Overdrive is also used to stop (or brake) a motor

quickly. Refer to the data sheet of the particular motor used with the DRV2604L device for safe and reliable

overdrive voltage and duration.

9.2.2.1.2 Linear Resonance Actuators (LRA)

Linear resonant actuators (LRAs) vibrate optimally at the resonant frequency. LRAs have a high-Q frequency

response because of a rapid drop in vibration performance at the offsets of 3 to 5 Hz from the resonant

frequency. Many factors also cause a shift or drift in the resonant frequency of the actuator such as temperature,

aging, the mass of the product to which the LRA is mounted, and in the case of a portable product, the manner in

which the product is held. Furthermore, as the actuator is driven to the maximum allowed voltage, many LRAs

will shift several hertz in frequency because of mechanical compression. All of these factors make a real-time

tracking auto-resonant algorithm critical when driving LRA to achieve consistent, optimized performance.

Frequency (Hz)

ƒ

(RESONANCE)

Figure 62. Typical LRA Response

9.2.2.1.2.1 Auto-Resonance Engine for LRA

The DRV2604L auto-resonance engine tracks the resonant frequency of an LRA in real time effectively locking

into the resonance frequency after half a cycle. If the resonant frequency shifts in the middle of a waveform for

any reason, the engine tracks the frequency from cycle to cycle. The auto resonance engine accomplishes this

tracking by constantly monitoring the back-EMF of the actuator. Note that the auto resonance engine is not

affected by the auto-calibration process which is only used for level calibration. No calibration is required for the

auto resonance engine.

9.2.2.2 Capacitor Selection

The DRV2604L device has a switching output stage which pulls transient currents through the V_DDpin. TI

recommends placing a 0.1-µF low equivalent-series-resistance (ESR) supply-bypass capacitor of the X5R or

X7R type near the V_DDsupply pin for proper operation of the output driver and the digital portion of the device.

Place a 1-µF X5R or X7R-type capacitor from the REG pin to ground.

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9.2.2.3 Interface Selection

The I²C interface is required to configure the device. The device can be used fully with the I²C interface and with

either RTP or internal memory. The advantage of using the I²C interface is that no additional GPIO (for the

IN/TRIG pin) is required for firing effects, and no PWM signal is required to be generated. Therefore the IN/TRIG

pin can be connected to GND. Using the external trigger pin has the advantage that no I²C transaction is

required to fire the pre-loaded effect, which is a good choice for interfacing with a button. The PWM interface is

available for backward compatibility.

9.2.2.4 Power Supply Selection

The DRV2604L device supports a wide range of voltages in the input. Ensuring that the battery voltage is high

enough to support the desired vibration strength with the selected actuator is an important design consideration.

The typical application uses Li-ion or Li-polymer batteries which provide enough voltage headroom to drive most

common actuators.

If very strong vibrations are desired, a boost converter can be placed between the power supply and the V_DDpin

to provide a constant voltage with a healthy headroom (5-V rails are common in some systems) which is

particularly true if two AA batteries in series are being used to power the system.

9.2.3 Application Curves

IN/TRIG

Acceleration

[OUT+] − [OUT−] (Filtered)

0

40m

80m

120m

Time (s)

160m

200m

0

40m

80m

120m

Time (s)

160m

200m

V_DD= 3.6 V ERM open loop

V_DD= 3.6 V LRA closed loop

Strong click

- 60%

External edge

trigger

Strong click -

100%

External level

trigger

Figure 63. ERM Click with and without Braking

Figure 64. LRA Click With and Without Braking

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9.3 Initialization Setup

9.3.1 Initialization Procedure

1. After powerup, wait at least 250 µs before the DRV2604L device accepts I²C commands.

2. Assert the EN pin (logic high). The EN pin can be asserted any time during or after the 250-µs wait period.

3. Write the MODE register (address 0x01) to value 0x00 to remove the device from standby mode.

4. If the nonvolatile auto-calibration memory has been programmed as described in the Auto Calibration

Procedure section, skip Step 5 and proceed to Step 6.

5. Perform the steps as described in the Auto Calibration Procedure section. Alternatively, rewrite the results

from a previous calibration.

6. If using the embedded RAM memory, populate the RAM with waveforms at this time as described in the

Loading Data to RAM section. Use registers 0xFD to 0xFF to access the RAM as described in the Table 2

procedure.

7. The default setup is closed-loop bidirectional mode. To use other modes and features, write Control1 (0x1B),

Control2 (0x1C), and Control3 (0x1D) as required.

8. Put the device in standby mode or deassert the EN pin, whichever is the most convenient. Both settings are

low-power modes. The user can select the desired MODE (address 0x01) at the same time the STANDBY

bit is set.

9.3.2 Typical Usage Examples

9.3.2.1 Play a Waveform or Waveform Sequence from the RAM Waveform Memory

1. Initialize the device as listed in the Initialization Procedure section.

2. Assert the EN pin (active high) if it was previously deasserted.

3. If register 0x01 already holds the desired value and the STANDBY bit is low, the user can skip this step.

Select the desired MODE[2:0] value of 0 (internal trigger), 1 (external edge trigger), or 2 (external level

trigger) in the MODE register (address 0x01). If the STANDBY bit was previously asserted, this bit should be

deasserted (logic low) at this time.

4. Select the waveform index to be played and write it to address 0x04. Alternatively, a sequence of waveform

indices can be written to register 0x04 through 0x0B. See the Waveform Sequencer section for details.

5. If using the internal trigger mode, set the GO bit (in register 0x0C) to fire the effect or sequence of effects. If

using an external trigger mode, send an appropriate trigger pulse to the IN/TRIG pin. See the Waveform

Triggers section for details.

6. If desired, the user can repeat Step 5 to fire the effect or sequence again.

7. Put the device in low-power mode by deasserting the EN pin or setting the STANDBY bit.

9.3.2.2 Play a Real-Time Playback (RTP) Waveform

1. Initialize the device as shown in the Initialization Procedure section.

2. Assert the EN pin (active high) if it was previously deasserted.

3. Set the MODE[2:0] value to 5 (RTP Mode) at address 0x01. If the STANDBY bit was previously asserted,

this bit should be deasserted (logic low) at this time. If register 0x01 already holds the desired value and the

STANDBY bit is low, the user can skip this step.

4. Write the desired drive amplitude to the real-time playback input register (address 0x02).

5. When the desired sequence of drive amplitudes is complete, put the device in low-power mode by

deasserting the EN pin or setting the STANDBY bit.

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Initialization Setup (continued)

9.3.2.3 Play a PWM or Analog Input Waveform

1. Initialize the device as shown in the Initialization Procedure section.

2. Assert the EN pin (active high) if it was previously deasserted.

3. If register 0x01 already holds the desired value and the STANDBY bit is low, the user can skip this step. Set

the MODE value to 3 (PWM/Analog Mode) at address 0x01. If the STANDBY bit was previously asserted,

this bit should be deasserted (logic low) at this time.

4. Select the input mode (PWM or analog) in the Control3 register (address 0x1D). If this mode was selected

during the initialization procedure, the user can skip this step.

5. Send the desired PWM or analog input waveform sequence from the external source. See the Data Formats

for Waveform Playback section for drive amplitude scaling.

6. When the desired drive sequence is complete, put the device in low-power mode by deasserting the EN pin

or setting the STANDBY bit.

10 Power Supply Recommendations

The DRV2604L device is designed to operate from an input-voltage supply range between 2 V to 5.2 V. The

decoupling capacitor for the power supply should be placed closed to the device pin.

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11 Layout

11.1 Layout Guidelines

Use the following guidelines for the DRV2604L layout:

•

The decoupling capacitor for the power supply (V_DD) should be placed closed to the device pin.

The filtering capacitor for the regulator (REG) should be placed close to the device REG pin.

When creating the pad size for the WCSP pins, TI recommends that the PCB layout use nonsolder mask-

defined (NSMD) land. With this method, the solder mask opening is made larger than the desired land area

and the opening size is defined by the copper pad width. Figure 65 shows and Table 31 lists appropriate

diameters for a wafer-chip scale package (WCSP) layout.

Copper

Trace Width

Solder

Pad Width

Solder Mask

Opening

Copper Trace

Thickness

Solder Mask

Thickness

Figure 65. Land Pattern Dimensions

Table 31. Land Pattern Dimensions

SOLDER PAD

DEFINITIONS

SOLDER MASK

OPENING

COPPER

THICKNESS

STENCIL

OPENING

STENCIL

THICKNESS

COPPER PAD

Nonsolder mask

defined (NSMD)

275 µm

(0, –25 µm)

375 µm

(0, –25 µm)

275 µm × 275 µm²

(rounded corners)

1-oz maximum (32 µm)

125-µm thick

1. Circuit traces from NSMD defined PWB lands should be 75-µm to 100-µm wide in the exposed area inside the solder

mask opening. Wider trace widths reduce device stand-off and impact reliability.

2. The recommended solder paste is Type 3 or Type 4.

3. The best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the

range of the intended application.

4. For a PWB using a Ni/Au surface finish, the gold thickness should be less than 0.5 µm to avoid a reduction in thermal

fatigue performance.

5. Solder mask thickness should be less than 20 µm on top of the copper circuit pattern.

6. The best solder stencil performance is achieved using laser-cut stencils with electro polishing. Use of chemically-etched

stencils results in inferior solder paste volume control.

7. Trace routing away from the WCSP device should be balanced in X and Y directions to avoid unintentional component

movement because of solder-wetting forces.

60

DRV2604L

www.ti.com.cn

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

11.1.1 Trace Width

The recommended trace width at the solder pins is 75 µm to 100 µm to prevent solder wicking onto wider PCB

traces. Maintain this trace width until the pin pattern has escaped, then the trace width can be increased for

improved current flow. The width and length of the 75-µm to 100-µm traces should be as symmetrical as possible

around the device to provide even solder reflow on each of the pins.

11.2 Layout Example

C_(REG)

EN

IN

REG

SDA

OUT+

GND

Via

Via should connect

to a ground plane

V

SCL

OUTt

DD

C_(VDD)

Figure 66. DRV2604L Layout Example DSBGA

C_(REG)

C_(VDD)

REG

SCL

SDA

VDD

OUT-

GND

Via

IN/TRIG

EN

OUT+

Via should connect

to a ground plane

VDD/NC

Figure 67. DRV2604L Layout Example VSSOP

61

DRV2604L

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

www.ti.com.cn

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

如需相关文档，请参阅：

•

《触觉能耗》，SLOA194

《关于移动设备和可穿戴设备的触觉实现注意事项》，SLOA207

《LRA 致动器：如何移动它们？》，SLOA209

《DRV2604L ERM、LRA 触觉驱动器评估套件》，SLOU390

《DRV2604LDGS 触觉驱动器迷你板》，SLOU397

12.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。请单击右上角的提醒我进行注册，即可每周接收

产品信息更改摘要。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。

12.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.4 商标

E2E is a trademark of Texas Instruments.

TouchSense is a registered trademark of Immersion Corporation.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

62

PACKAGE OUTLINE

DGS0010A

VSSOP - 1.1 mm max height

S

C

A

L

E

3

.

2

0

SMALL OUTLINE PACKAGE

C

SEATING PLANE

0.1 C

5.05

4.75

TYP

PIN 1 ID

AREA

A

8X 0.5

10

1

3.1

2.9

NOTE 3

2X

2

5

6

0.27

0.17

10X

3.1

2.9

1.1 MAX

0.1

C A

B

NOTE 4

0.23

0.13

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.7

0.4

0 - 8

DETAIL A

TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187, variation BA.

www.ti.com

EXAMPLE BOARD LAYOUT

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

(R0.05)

TYP

SYMM

10X (0.3)

1

5

10

SYMM

6

8X (0.5)

(4.4)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221984/A 05/2015

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

SYMM

(R0.05) TYP

10X (0.3)

8X (0.5)

1

5

10

SYMM

6

(4.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4221984/A 05/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

YZF0009

DSBGA - 0.625 mm max height

SCALE 8.000

DIE SIZE BALL GRID ARRAY

A

B

E

BALL A1

CORNER

D

C

0.625 MAX

SEATING PLANE

0.05 C

BALL TYP

0.35

0.15

1 TYP

SYMM

C

1

TYP

SYMM

B

A

D: Max = 1.47 mm, Min = 1.41 mm

E: Max = 1.47 mm, Min = 1.41 mm

0.5

TYP

3

1

2

0.35

0.25

9X

0.015

0.5 TYP

C A B

4219558/A 10/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

YZF0009

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.5) TYP

9X ( 0.245)

(0.5) TYP

1

2

3

A

SYMM

B

C

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 40X

0.05 MIN

0.05 MAX

METAL UNDER

SOLDER MASK

(

0.245)

METAL

(

0.245)

EXPOSED

METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4219558/A 10/2018

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

YZF0009

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.5) TYP

(R0.05) TYP

3

9X ( 0.25)

1

2

A

B

(0.5) TYP

SYMM

METAL

TYP

C

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE: 40X

4219558/A 10/2018

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DRV2604LYZFR
厂家：	TEXAS INSTRUMENTS
描述：	具有 2V 工作电压、波形存储器和自动谐振跟踪功能的 ERM/LRA 触觉驱动器 \| YZF \| 9 \| -40 to 85 驱动接口集成电路存储驱动器
文件：	总73页 (文件大小：2899K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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