DRV401-Q1 [TI]
适用于闭环应用的汽车类磁通门磁传感器信号调节 IC;
| 型号： | DRV401-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于闭环应用的汽车类磁通门磁传感器信号调节 IC 传感器 |
| 文件： | 总39页 (文件大小：2112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DRV401-Q1
ZHCSFT7 –DECEMBER 2016
适用于闭环磁电流传感器的
DRV401-Q1 传感器信号调节器件
1 特性
3 说明
1
•
•
汽车电子 应用认证
具有符合 AEC-Q100 标准的下列结果：
DRV401-Q1 器件完全符合汽车 应用要求 并适用于电
机控制驱动和电池监测系统。
–
–
–
器件温度 1 级：-40℃ 至 +125℃ 的环境运行温
度范围
与磁传感器搭配使用时，DRV401-Q1 能够以高精确度
监测交流和直流电流。
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
1C
可提供的功能包括：探头激励、探头信号的信号调节、
信号环路放大器、补偿线圈的 H 桥驱动器和提供与初
级电流成正比的输出电压的模拟信号输出级。它具有过
载和故障检测功能，以及瞬态噪声抑制功能。
器件带电器件模型 (CDM) ESD 分类等级 C6
•
•
•
•
•
•
•
•
•
•
单电源：5V
电源输出：H 桥
专为驱动电感负载而设计
出色的直流精度
宽系统带宽
DRV401-Q1 器件可直接驱动补偿线圈或与外部电源驱
动器连接。因此，DRV401-Q1 与传感器相结合，可用
于测量各种大小的电流。
高分辨率、低温漂移
内置去磁系统
为维持最高精度，DRV401-Q1 可在加电时根据需要对
传感器进行去磁。
丰富的故障检测功能
外部高功率驱动器选项
紧凑型封装
器件信息(1)
器件型号
封装
VQFN-20
封装尺寸（标称值）
DRV401-Q1
5.00mm × 5.00mm
2 应用
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
•
•
•
•
•
•
•
•
汽车
汽车中的电机控制 应用
磁通门电流感应
发电机和交流发电机监测和控制
频率和电压逆变器
电机驱动控制器
系统功耗
光伏系统
闭环磁感应
Patents Pending
Compensation
RS
ICOMP1
ICOMP2
PWM PWM
Compensation Winding
Primary Winding
DRV401-Q1
Diff
Magnetic Core
Amp
Field Probe
IS2
IS1
IP
VOUT
REFIN
Probe
Interface
Integrator
Filter
H-Bridge
Driver
Timing, Error Detection,
and Power Control
VREF
Degauss
VREF
+5 V GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS814
DRV401-Q1
ZHCSFT7 –DECEMBER 2016
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
8
9
Application and Implementation ........................ 24
8.1 Application Information............................................ 24
8.2 Typical Application ................................................. 26
Power Supply Recommendations...................... 28
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 8
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 23
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Example .................................................... 30
10.3 Power Dissipation ................................................. 30
11 器件和文档支持 ..................................................... 30
11.1 器件支持................................................................ 30
11.2 文档支持 ............................................................... 31
11.3 接收文档更新通知 ................................................. 31
11.4 社区资源................................................................ 31
11.5 商标....................................................................... 31
11.6 静电放电警告......................................................... 31
11.7 Glossary................................................................ 32
12 机械、封装和可订购信息....................................... 33
12.1 散热焊盘................................................................ 33
7
4 修订历史记录
日期
修订版本
注释
2016 年 12 月
*
首次发布。
2
Copyright © 2016, Texas Instruments Incorporated
DRV401-Q1
www.ti.com.cn
ZHCSFT7 –DECEMBER 2016
5 Pin Configuration and Functions
RGW Package
20-Pin VQFN With Exposed Thermal Pad
Top View
VDD1
ERROR
DEMAG
GAIN
1
2
3
4
5
15
14
13
12
11
Exposed
Thermal Pad
on Underside,
Connect
OVER-RANGE
CCdiag
REFOUT
REFIN
VDD2
to GND1
ICOMP1
Pin Functions
PIN
I/O
DESCRIPTION
NAME
CCdiag
DEMAG
ERROR
GAIN
GND1
GND2
IAIN1
NO.
13
2
I
I
Control input for wire-break detection: high = enable
Control input; See the Demagnetization section.
Error flag: open-drain output. See the Error Conditions section.
Control input for open-loop gain: low = normal, high = −8 dB
Ground connection
1
O
I
3
17
9
—
—
I
Ground connection. Connect to GND1.
Inverting input of differential amplifier
Noninverting input of differential amplifier
Output 1 of compensation coil driver
Output 2 of compensation coil driver
Probe connection 1
8
IAIN2
7
I
ICOMP1
ICOMP2
IS1
11
10
18
16
O
O
I/O
I/O
IS2
Probe connection 2
OVER-
RANGE
14
O
Open-drain output for overrange indication: low = overrange
PWM
19
20
4
O
O
O
I
PWM output from probe circuit (inverted)
PWM output from probe circuit
PWM
REFOUT
REFIN
Output for internal 2.5-V reference voltage
Input for zero reference to differential amplifier
5
Thermal
pad
—
—
Exposed thermal pad. Connect to GND1.
Supply voltage
VDD1
VDD2
VOUT
15
12
6
—
—
O
Supply voltage. Connect to VDD1
.
Output for differential amplifier
Copyright © 2016, Texas Instruments Incorporated
3
DRV401-Q1
ZHCSFT7 –DECEMBER 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted).(1)
MIN
MAX
7
UNIT
Supply voltage
Voltage
Signal input pin
−0.5
–10
–75
–25
0
VDD + 0.5
10
V
Differential amplifier
Current
Signal input pin
Signal input pin, IS1 and IS2
Pins other than IS1 and IS2
ICOMP short circuit
Operating, TA
75
25
mA
°C
250
150
150
150
–50
Temperature
Junction, TJ
Storage, Tstg
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±1000
±5000
±1000
±1000
UNIT
Pins IAIN1 and IAIN2
All other pins
All pins
(1)
Human-body model (HBM), per AEC Q100-002
Electrostatic
discharge
V(ESD)
V
Charged-device model (CDM), per AEC Q100-011
Corner pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
5
MAX
5.5
UNIT
Power supply voltage, VDD1, VDD2
Specified temperature range
V
–40
25
+125
°C
6.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
DRV401-Q1
RGW
(VQFN)
THERMAL METRIC(1)
UNIT
20 PINS
34.1
22.8
12.1
0.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
12.0
3.5
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2016, Texas Instruments Incorporated
DRV401-Q1
www.ti.com.cn
ZHCSFT7 –DECEMBER 2016
6.5 Electrical Characteristics
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
±0.01
±0.1
MAX
±0.1
±1
UNIT
mV
DIFFERENTIAL AMPLIFIER
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
Gain = 4 V/V
VOS
Offset voltage, RTO(1)(2)
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
TA = –40°C to 125°C
ICOMP = 0 mA
dVOS/dT Offset voltage drift, RTO(2)
µV/°C
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
−1 V to 6 V, VREF = 2.5 V
Offset voltage vs common-mode,
CMRR
RTO
±50
±4
±250
±50
µV/V
µV/V
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
VREF not included
Offset voltage vs power supply,
PSRR
RTO
SIGNAL INPUT
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
Common-mode voltage range
SIGNAL OUTPUT
–1
(VDD) + 1
V
RL = 10 kΩ to 2.5 V, VREFIN = 2.5 V,
Signal overrange indication (OVER-
RANGE), delay(2)
TA = –40°C to 125°C, ICOMP = 0 mA,
2.5 to 3.5
48
µs
(2)
VIN = 1-V step. See
Voltage output swing from negative RL = 10 kΩ to 2.5 V
rail(2)
OVER-RANGE trip level
,
VREFIN = 2.5 V
85
mV
mV
mA
mA
V/V
I = 2.5 mA, CMP trip level
Voltage output swing from positive RL = 10 kΩ to 2.5 V
rail(2)
,
VREFIN = 2.5 V
VDD – 85
VDD – 48
–18
OVER-RANGE trip level
I = −2.5 mA, CMP trip level
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
VOUT connected to GND
ISC
Short-circuit current(2)
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
20
VOUT connected to VDD
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
TA = –40°C to 125°C
Gain, VOUT/VIN_DIFF
Gain error
4
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
±0.02%
±0.3%
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
TA = –40°C to 125°C
ICOMP = 0 mA
Gain error drift
Linearity error
±0.1
10
ppm/°C
ppm
VREFIN = 2.5 V
RL = 1 kΩ
FREQUENCY RESPONSE
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
BW–3 dB Bandwidth(2)
2
MHz
V/µs
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
SR
Slew rate(2)
6.5
CMVR = −1 V to 4 V
(1) Parameter value referred-to-output (RTO).
(2) θJP = 结至焊盘热阻
Copyright © 2016, Texas Instruments Incorporated
5
DRV401-Q1
ZHCSFT7 –DECEMBER 2016
www.ti.com.cn
Electrical Characteristics (continued)
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
Settling time, large-signal(2)
0.9
µs
dV ±2 V to 1%, no external filter
tS
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
Settling time(2)
14
µs
dV ±0.4 V to 0.01%
INPUT RESISTANCE
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
Differential
16.5
41
20
50
50
23.5
59
kΩ
kΩ
kΩ
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
Common-mode
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
External reference input
41
59
NOISE
RL = 10 kΩ to 2.5 V
VREFIN = 2.5 V
f = 1 kHz, compensation loop disabled
Output voltage noise density,
RTO(2)
en
170
nV/√Hz
COMPENSATION LOOP
DC STABILITY
Probe f = 250 kHz, RLOAD = 20 Ω,
deviation from 50% PWM,
pin gain = L
(3)
Offset error
0.03%
7.5
Probe f = 250 kHz, RLOAD = 20 Ω,
deviation from 50% PWM,
(2)
Offset error drift
ppm/°C
pin gain = L, TA = –40°C to 125°C
Probe f = 250 kHz, RLOAD = 20 Ω, pin gain
= L,
(2)
Gain
–200
25
200 ppm/V
ppm/V
|VICOMP1| – |VICOMP2
|
PSRR
Power-supply rejection ratio
Probe f = 250 kHz, RLOAD = 20 Ω
500
FREQUENCY RESPONSE
Probe f = 250 kHz, RLOAD = 20 Ω, two
modes, 7.8 kHz
Open-loop gain
24/32
dB
PROBE COIL LOOP
–0.7 to
VDD + 0.7
Input voltage clamp range
Field probe current < 50 mA
V
59
Internal resistor, IS1 or IS2 to VDD1
RHIGH
RLOW
47
60
71
90
Ω
Ω
(2)
Internal resistor, IS1 or IS2 to
75
(2)
GND1
Resistance mismatch between IS1
and IS2
ppm of RHIGH + RLOW
300
134
1500
200
ppm
Ω
(2)
TA = –40°C to 125°C
ICOMP = 0 mA
Total input resistance
Comparator threshold current
22
250
250
28
34
mA
ns
(2)
Minimum probe loop half-cycle
280
310
Probe loop minimum frequency
kHz
No oscillation detect (error)
suppression
35
µs
COMPENSATION COIL DRIVER, H-BRIDGE
V
ICOMP1 − VICOMP2 = 4 VPP
(2)
Peak current
TA = –40°C to 125°C
ICOMP = 0 mA
250
mA
Voltage swing
20-Ω load
4.2
VPP
(3) For VAC sensors, 0.2% of PWM offset approximately corresponds to 10-mA primary current per offset per winding.
6
Copyright © 2016, Texas Instruments Incorporated
DRV401-Q1
www.ti.com.cn
ZHCSFT7 –DECEMBER 2016
Electrical Characteristics (continued)
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
57
UNIT
VOCM
Output common-mode voltage
Wire break detect, threshold
VDD2 / 2
V
33
mA
(4)
current
VOLTAGE REFERENCE
(2)
Voltage
No load
2.495
2.5
±5
2.505
V
No load, TA = – 40°C to 125°C
ICOMP = 0 mA
(2)
Voltage drift
±50 ppm/°C
PSRR
Power-supply rejection ratio(2)
Load regulation(2)
±15
0.15
±200
µV/V
Load to GND and VDD
dI = 0 mA to 5 mA
mV/mA
REFOUT connected to VDD
REFOUT connected to GND
20
mA
mA
ISC
Short-circuit current
–18
DEMAGNETIZATION
Duration
At TA = –40°C to 125°C
ICOMP = 0 mA; see the Demagnetization
section
106
130
ms
DIGITAL I/O
LOGIC INPUTS (DEMAG, GAIN, and CCdiag PINS)
Pull-up high current (CCdiag)
Pull-up low current (CCdiag)
Logic input leakage current
Logic level, input: L/H
CMOS-type levels, 3.5 < VIN < VDD
160
5
µA
µA
µA
CMOS-type levels, 0 < VIN < 1.5
CMOS-type levels, 0 < VIN < VDD
CMOS-type levels
0.01
2.1/2.8
0.7
Hysteresis
CMOS-type levels
OUTPUTS (ERROR AND OVER-RANGE PINS)
Logic level, output: L
4-mA sink
0.3
V
No
internal
pull-up
Logic level, input: H
OUTPUTS (PWM AND PWM PINS)
Logic level L
Push-pull type, 4-mA sink
0.2
V
V
Logic level H
Push-pull type, 4-mA source
VDD – 0.4
POWER SUPPLY
TA = –40°C to 125°C
ICOMP = 0 mA
VDD
Specified voltage range
Power-on reset threshold
4.5
5
5.5
6.8
V
V
VRST
IQ
1.8
Quiescent current [I(VDD1) +
I(VDD2)]
ICOMP = 0 mA, sensor not connected
mA
Brownout voltage level
4
V
Brownout indication delay
135
µs
TEMPERATURE RANGE
TJ
TJ
Specified range
Operating range
–40
–50
125
150
°C
°C
(4) See the Compensation Driver subsection in the Detailed Description section.
版权 © 2016, Texas Instruments Incorporated
7
DRV401-Q1
ZHCSFT7 –DECEMBER 2016
www.ti.com.cn
6.6 Typical Characteristics
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth, (unless otherwise noted)
100
0.04
0.03
0.02
0.01
0
60-Hz Line Frequency and Multiples
(measured in a 60-Hz environment)
M4645-X211
Divided Field
Probe Frequency
10
M4645-X080
-0.01
-0.02
-0.03
-0.04
0.1
0.1
1
10
100
1k
10k
100k
4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 5.7 5.9 6.1
VDD (V)
Frequency (Hz)
Sensor M4645−X080, RSHUNT = 10 Ω, Mode = Low
图 2. DRV401-Q1 Device and Sensor: Output Voltage Noise
图 1. DRV401-Q1 Device and Sensor: Offset vs Supply
Density
Voltage
1.20
0.3
DRV401-Q1 with M4645-X600 Sensor
T = -50°C
T = 25°C
T = 85°C
T = 125°C
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
DRV401-Q1 with M4645-X211 Sensor
DRV401-Q1 with M4645-X080 Sensor
0.2
0.1
0
-0.1
-0.2
-0.3
TC (RSHUNT) ±25 ppm/°C
-200 -100
-300
0
100
200
300
10
100
1 k
10 k
100 k
1 M
Primary Current (A)
Frequency (Hz)
Soldered DWP−20 with 1-in2 copper pad. Measurements by
Vacuumschmelze GmbH.
图 4. Gain Flatness vs Frequency
图 3. DRV401-Q1 Device and Sensor: Absolute Error
RTO
Over-Range
Over-Range
VOUT
VOUT
ERROR
ERROR
IPRIM
IPRIM
NOTE: IPRIM = 3000 A corresponds to ICOMP = 3 A
0
20
40
60
80 100 120 140 160 180 200
Time (ms)
Voltage Offset (mV)
Measurements by Vacuumschmelze GmbH.
Measurements by Vacuumschmelze GmbH.
图 6. Differential Amplifier: Voltage Offset Production
图 5. 3-A ICOMP Overload Recovery
Distribution
8
版权 © 2016, Texas Instruments Incorporated
DRV401-Q1
www.ti.com.cn
ZHCSFT7 –DECEMBER 2016
Typical Characteristics (接下页)
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth, (unless otherwise noted)
20
20
16
12
8
15
10
5
4
Sample Average
0
0
-4
-8
-12
-16
-20
-5
-10
-15
-20
-50
-25
0
25
50
75
100
125
150
10
100
1 k
10 k
100 k
1 M
10 M
Temperature (°C)
Frequency (Hz)
图 7. Differential Amplifier: Offset Voltage vs Temperature,
图 8. Differential Amplifier: Gain vs Frequency
RTO
120
5.0
4.9
4.8
-40°C
25°C
PSRR
100
125°C
CMRR
80
85°C
4.7
0.3
60
40
20
0
85°C
125°C
0.2
0.1
0
-40°C
25°C
10
100
1 k
10 k
100 k
1 M 2 M
0
1
2
3
4
5
6
7
8
9
10
Load Current (mA)
Frequency (Hz)
图 10. Differential Amplifier: Output Voltage vs Output
图 9. Differential Amplifier: PSRR and CMRR vs Frequency
Current
25
1000
VOUT Shorted to 5 V
20
15
10
5
0
100
-5
-10
Autozero Frequency = 69 kHz
Sensor Not Running
en = 162 nV/ÖHz
-15
-20
-25
VOUT Shorted to 0 V
-50 -25
(average over 250 Hz to 50 kHz)
10
0
25
50
75
100
125
150
100
1 k
10 k
100 k
1 M
Temperature (°C)
Frequency (Hz)
图 12. Differential Amplifier: Short-Circuit Current vs
图 11. Differential Amplifier: Output Noise Density
Temperature
版权 © 2016, Texas Instruments Incorporated
9
DRV401-Q1
ZHCSFT7 –DECEMBER 2016
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth, (unless otherwise noted)
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1 ms/div
1 ms/div
TA = −50°C
TA = 25°C
图 13. Differential Amplifier: Large-Signal Step Response
3.8
图 14. Differential Amplifier: Large-Signal Step Response
3.5
At 5.0 V
VIN Step 0 V to ±1 V
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
3.4
3.3
3.2
Negative Over-Range
3.1
3.0
2.9
Positive Over-Range
2.8
2.7
2.6
2.5
-50
-25
0
25
50
75
100
125
150
1 ms/div
Temperature (°C)
TA = 150°C
图 15. Differential Amplifier: Large-Signal Step Response
图 16. Differential Amplifier: Overrange Delay vs
Temperature
7.5
-6.5
-6.6
-6.7
-6.8
-6.9
-7.0
-7.1
-7.2
-7.3
-7.4
-7.5
At 5.0 V
At 5.0 V
7.4
7.3
7.2
7.1
7.0
6.9
6.8
6.7
6.6
6.5
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
图 17. Differential Amplifier: Positive Slew Rate vs
图 18. Differential Amplifier: Negative Slew Rate vs
Temperature
Temperature
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Typical Characteristics (接下页)
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth, (unless otherwise noted)
50.250
70
60
50.125
50
50.000
49.875
49.750
49.625
Pin Gain = Low
40
30
20
10
0
Pin Gain = High
-50
-25
0
25
50
75
100
125
150
100
1 k
10 k
100 k
Temperature (°C)
Frequency (Hz)
图 19. Differential Amplifier: REFIN Resistance vs
图 20. Compensation Loop: Small-Signal Gain
ICOMP1 - VICOMP2 = 4.2 V
Temperature
2000
1500
1000
500
V
ILOAD = 210 mA
Gain Pin Low
0
At 250 kHz, 5.0 V
At 400 kHz, 5.0 V
-500
-1000
-1500
-2000
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Gain (ppm/V)
图 21. Compensation Loop: Duty Cycle Error vs
图 22. Compensation Loop: DC Gain: Duty Cycle Error
Temperature
Change
5.00
4.75
4.50
4.25
35.0
-50°C
125°C
25°C
32.5
30.0
27.5
25.0
4.00
1.00
0.75
0.50
0.25
0
25°C
125°C
-50°C
0
50
100
150
200
250
300
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Output Current (mA)
图 24. Probe Comparator Threshold Current vs Temperature
图 23. ICOMP Output Swing to Rail vs Output Current
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Typical Characteristics (接下页)
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth, (unless otherwise noted)
0.10
0.08
0.06
0.04
0.02
0
90
85
80
75
70
65
60
55
50
45
Driver L
Driver H
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
图 25. Probe Driver: Internal Resistor vs Temperature
2.5010
图 26. Output Impedance Mismatch of IS1 and IS2 vs
Temperature
2.5008
2.5006
2.5004
2.5002
2.5000
2.4998
2.4996
2.4994
2.4992
2.4990
-6
-4
-2
0
2
4
6
ILOAD (mA)
VREF (V)
图 28. Voltage Reference Production Distribution
图 27. Voltage Reference vs Load Current
2.525
2.520
2.515
2.510
2.505
2.500
2.495
2.490
2.485
2.480
2.475
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Voltage Reference Drift (ppm/°C)
图 30. Voltage Reference vs Temperature
图 29. Voltage Reference Drift Production Distribution
12
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Typical Characteristics (接下页)
at TA = 25°C and VDD1 = VDD2 = 5 V with external 100-kHz filter bandwidth, (unless otherwise noted)
PSR (mV/V)
Minimum Probe Loop Half-Cycle (ns)
图 31. Voltage Reference Power-Supply Rejection
图 32. Oscillator Production Distribution <
Production Distribution
310
305
300
295
290
285
280
275
270
265
260
255
250
310
305
300
295
290
285
280
275
270
265
260
255
250
-50
-25
0
25
50
75
100
125
150
4.3
4.6
4.9
5.2
5.5
5.8
6.0
Temperature (°C)
VDD (V)
图 33. Oscillator vs Temperature
图 34. Oscillator vs Supply Voltage
4.20
4.15
4.10
4.05
4.00
3.95
3.90
3.85
3.80
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
图 35. Brownout Voltage vs Temperature
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7 Detailed Description
7.1 Overview
Closed-loop current sensors measure current over wide frequency ranges, including dc. These types of devices
offer a contact-free method, as well as excellent galvanic isolation performance combined with high resolution,
accuracy, and reliability. The DRV401-Q1 is a complete sensor signal conditioning circuit that directly connects to
the current sensor, providing all necessary functions for the sensor operation.
7.2 Functional Block Diagram
Compensation
RS
ICOMP1
ICOMP2
Compensation Winding
Primary Winding
DRV401-Q1
Diff
Magnetic Core
Field Probe
Amp
IS2
IS1
IP
VOUT
REFIN
Probe
Interface
Integrator
Filter
H-Bridge
Driver
Timing, Error Detection,
and Power Control
VREF
Degauss
VREF
5 V GND
Copyright © 2016, Texas Instruments Incorporated
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7.3 Feature Description
The DRV401-Q1 operates from a single 5-V supply. The DRV401-Q1 is a complete sensor signal conditioning
circuit that directly connects to the current sensor, providing all necessary functions for the sensor operation. The
DRV401-Q1 device provides magnetic field probe excitation, signal conditioning, and compensation coil driver
amplification. In addition, the device detects error conditions and handles overload situations. A precise
differential amplifier allows translation of the compensation current into an output voltage using a small shunt
resistor. A buffered voltage reference is used for comparator, analog-to-digital converter (ADC), or bipolar zero
reference voltages.
Dynamic error correction ensures high dc precision over temperature and long-term accuracy. The DRV401-Q1
uses analog signal conditioning, and the internal loop filter and integrator are switched capacitor-based circuits.
Therefore, the DRV401-Q1 device allows combination with high-precision sensors for exceptional accuracy and
resolution.
A demagnetization cycle initiates on demand or on power-up. The cycle reduces offset and restores high
performance after a strong overload condition. An internal clock and counter logic generate the degauss function.
The same clock controls power-up, overload detection and recovery, error, and time-out conditions.
The DRV401-Q1 device is built on a highly reliable CMOS process. Unique protection cells at critical connections
enable the design to handle inductive energy.
7.3.1 Magnetic Probe (Sensor) Interface
The magnetic field probe consists of an inductor wound on a soft magnetic core. The probe is connected
between pins IS1 and IS2 of the probe driver that applies approximately 5 V (the supply voltage) through
resistors across the probe coil, as shown in 图 36.
Typically, the probe core reaches saturation at a current of 28 mA, as shown in 图 36. The comparator is
connected to VREF by approximately 0.5 V. A current comparator detects the saturation and inverts the excitation
voltage polarity, causing the probe circuit to oscillate in a frequency range of 250 kHz to 550 kHz. The oscillating
frequency is a function of the magnetic properties of the probe core and the coil.
VDD1
Probe
55 W
55 W
IS2
IS1
PWM
CMP
18 W
VREF = 0.5 V
NOTE: MOS components function as switches only.
Copyright © 2016, Texas Instruments Incorporated
The probe is connected between S1 and S2.
图 36. Magnetic Probe, Hysteresis, and Duty Cycle: Simplified Probe Circuit
The current rise rate is a function of the coil inductance: dI = L × V × dT. However, the inductance of the field
probe is low while the core material is in saturation (the horizontal part of the hysteresis curve) and is high at the
vertical part of the hysteresis curve. The resulting inductance and the series resistance determine the output
voltage and current versus time performance characteristic.
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Feature Description (接下页)
Without external magnetic influence, the duty cycle is exactly 50% because of the inherent symmetry of the
magnetic hysteresis; the probe inductor is driven from −B saturation through the high inductance range to +B
saturation and back again in a time-symmetric manner, as shown in 图 37.
B
H
V (IS1)
V (PWM)/10
500 ns/div
Without an external magnetic field, the hysteresis curve is symmetrical and the probe loop generates 50% duty cycle.
图 37. Magnetic Probe, Hysteresis, and Duty Cycle: No External Magnetic Field
16
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ZHCSFT7 –DECEMBER 2016
Feature Description (接下页)
If the core material is magnetized in one direction, a long and a short charge time result because the probe
current through the inductors generates a field that subtracts or adds to the flux in the probe core, driving the
probe core out of saturation or further into saturation, as shown in 图 38. The current into the probe is limited by
the voltage drops across the probe driver resistors.
B
H
V (IS1)
V (PWM)/10
500 ns/div
An external magnetic flux (H) generated from the primary current (IPRIM) shifts the hysteresis curve of the magnetic
field probe in the H-axis and the probe loop generates a nonsymmetrical duty cycle.
图 38. Magnetic Probe, Hysteresis, and Duty Cycle With External Magnetic Field
The DRV401-Q1 device continuously monitors the logic magnetic flux polarity state. In the case of distortion
noise and excessive overload that can fully saturate the probe, the overload control circuit recovers the probe
loop. During an overload condition, the probe oscillation frequency increases to approximately 1.6 MHz until
limited by the internal timing control.
In an overload condition, the compensation current (ICOMP) driver cannot deliver enough current into the sensor
secondary winding, so the magnetic flux in the sensor main core becomes uncompensated.
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Feature Description (接下页)
The transition from normal operation to overload happens slowly because the inherent sensor transformer
characteristics induce the initial primary current step, as shown in 图 39. As the transformer-induced secondary
current starts to decay, the compensation feedback driver increases the output voltage to maintain the sensor
core flux compensation at zero.
Sensor: 4 x 100
V(1 W ´ IPRIM/10)
RSH = 10 W
1
Step Response
ICOMP1
2 kHz In
3
V(Gain) = Low
4
ICOMP2
Channel 1: 2 V/div
Channels 2 through 4: 500 mV/div
VOUT
2
50 ms/div
A current pulse of 0 A to 18 A (channel 1) generates the two ICOMP signals (channel 3 and channel 4). Channel 2
shows the resulting output signal (VOUT). This test uses the M4645-X030 sensor with no bandwidth limitation, and a
20-sample average.
图 39. Primary Current Step Response
When the system compensation loop reaches the driving limit, the rising magnetic flux causes one of the probe
pulse-width modulator (PWM) half-periods to become shorter. The minimum half-period of the probe oscillation is
limited by the internal timing to 280 ns, based on the properties of the VAC magnetic sensors. After three
consecutive cycles of the same half-period being shorter than 280 ns, the DRV401-Q1 device enters overload-
latch mode. The device stores the ICOMP driver output signal polarity and continues producing the skewed-duty
cycle PWM signal. This action prevents the loss of compensation signal polarity information during strong
overloads. In this case, both PWM half-periods are short and approximately equal, because the field probe stays
completely in one of the saturated regions.
The overload-latch condition is removed after the primary current goes low enough for the ICOMP driver to
compensate, and both half-periods of the probe driver oscillation become longer than 280 ns (the field probe
comes out of the saturated region).
Peak voltages and currents generate during normal operations and overload conditions. Both probe connection
pins are internally protected against coupled energy from the magnetic core. Wiring between probe and device
inputs must be short and guarded against interference, as shown in the Layout Guidelines section.
For reliable operation, error detection circuits monitor the probe operation:
1. If the probe driver comparator (CMP) output stays low longer than 32 μs, the ERROR flag asserts active, and
the compensation current (ICOMP) is set to zero.
2. If the probe driver period is less than 275 ns on three consecutive pulses, the ERROR flag asserts active.
See the Error Conditions section for more details.
7.3.2 PWM Processing
The PWM and PWM outputs represent the probe output signal as a differential PWM signal. The signal drives
external circuitry and is used for synchronous ripple reduction. The PWM signal from the probe excitation and
sense stage is internally connected to a high-performance, switched-capacitor integrator followed by an
integrating-differentiating filter. The filter converts the PWM signal into a filtered delta signal and prepares the
PWM signal to drive the analog compensation coil driver. The gain roll-off frequency of the filter stage provides
high dc gain and loop stability. If additional gain is added from external circuitry, the internal gain is reduced by 8
dB, which asserts the GAIN pin high, as shown in the External Compensation Coil Driver section.
18
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Feature Description (接下页)
7.3.3 Compensation Driver
The compensation coil driver provides the driving current for the compensation coil. A fully-differential driver
stage offers high signal voltages to overcome the wire resistance of the coil with a 5-V supply. The compensation
coil is connected between ICOMP1 and ICOMP2, generating an analog voltage across the coil (shown in 图 39) that
turns into current from the wire resistance (and eventually from the inductance). The compensation current
represents the primary current transformed by the turns ratio. A shunt resistor is connected in this loop and the
high-precision difference amplifier translates the voltage from the shunt to an output voltage.
Both compensation driver outputs provide low impedance over a wide frequency range to ensure smooth
transitions between the closed-loop compensation frequency range and the high-frequency range, where the
primary winding directly couples the primary current into the compensation coil at a rate set by the winding ratio.
The two compensation driver outputs are designed with protection circuitry to handle inductive energy. However,
additional external protection diodes may be necessary for high-current sensors.
For reliable operation, a wire break in the compensation circuit can be detected. If the feedback loop is broken,
the integrating filter drives the ICOMP1 and ICOMP2 outputs to the opposite rails. With one of these pins coming
within 300 mV to ground, a comparator tests for a minimum current flowing between ICOMP1 and ICOMP2. If the
current stays below the threshold current level for a minimum of 100 μs, the ERROR pin is asserted active (low).
The threshold current level for the test is less than 57 mA at 25°C and 65 mA at −40°C if the ICOMP pins are fully
railed, as shown in the Typical Characteristics section.
For sensors with high winding resistance (compensation coil resistance + RSHUNT) or that are connected to an
external compensation driver, this function must be disabled by pulling the CCdiag pin low, as shown in 公式 1:
VOUT
RMAX
=
65 mA
where:
•
•
VOUT equals the peak voltage between ICOMP1 and ICOMP2 at a 65-mA drive current; and
RMAX equals the sum of the coil and the shunt resistance
(1)
7.3.4 External Compensation Coil Driver
An external driver for the compensation coil connects to the ICOMP1 and ICOMP2 outputs. To prevent a wire break
indication, CCdiag must be asserted low.
An external driver provides a higher drive voltage and more drive current. The driver moves the power dissipation
to the external transistors, thereby allowing a higher winding resistance in the compensation coil and more
current. 图 40 shows a block diagram of an external compensation coil driver. To drive the buffer, one or both of
the ICOMP outputs may be used. Note, however, that the additional voltage gain can cause instability of the loop.
Therefore, the internal gain may be reduced by approximately 8 dB by asserting the GAIN pin high. RSHUNT is
connected to GND to allow for a single-ended external compensation driver. The differential amplifier continues
to sense the voltage, and is used for the gain and over-range comparator or ERROR flag.
V+
DRV401-Q1
ICOMP1
External
Buffer
Compensation
Coil
ICOMP2
RSHUNT
V-
Copyright © 2016, Texas Instruments Incorporated
图 40. DRV401-Q1 with External Compensation Coil Driver and RSHUNT Connected to GND
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Feature Description (接下页)
7.3.5 Shunt Sense Amplifier
The differential (H-bridge) driver arrangement for the compensation coil requires a differential sense amplifier for
the shunt voltage. This differential amplifier offers wide bandwidth and a high slew rate for fast current sensors.
Excellent dc stability and accuracy result from an auto-zero technique. The voltage gain is 4 V/V, set by precisely
matched and stable internal SiCr resistors.
7.3.6 Over-Range Comparator
High peak current can overload the differential amplifier connected to the shunt. The OVER-RANGE pin, an
open-drain output, indicates an over-voltage condition for the differential amplifier by pulling low. The output of
this flag is suppressed for 3 μs, preventing unwanted triggering from transients and noise. This pin returns to high
when the overload condition is removed (an external pull-up is required to return the pin high).
This ERROR flag provides a warning about a signal clipping condition, but is also a window comparator output
for actively shutting off circuits in the system. The value of the shunt resistor defines the operating window for the
current. The value of the shunt resistor sets the ratio between the nominal signal and the trip level of the over-
range flag. The trip current of this window comparator is calculated using the following example:
With a 5-V supply, the output voltage swing is approximately ±2.45 V (load and supply voltage-dependent).
The gain of 4 V/V allows an input swing of ±0.6125 V.
Thus, the clipping current is IMAX = 0.6125 V / RSHUNT
.
See 图 10.
The over-range condition is internally detected when the amplifier exceeds the linear operating range, not merely
as a set voltage level. Therefore, the error or the over-range comparator level is reliably indicated in fault
conditions such as output shorts, low load or low supply conditions. The flag is activated when the output cannot
drive the voltage higher. The configuration is a safety improvement over a voltage level comparator.
注
The internal resistance of the compensation coil may prevent high compensation current
from flowing because of ICOMP driver overload. Therefore, the differential amplifier may not
overload with this current. However, a fast rate of change of the primary current would be
transmitted through transformer action and safely trigger the overload flag.
20
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ZHCSFT7 –DECEMBER 2016
7.3.7 Voltage Reference
The precision 2.5-V reference circuit offers low drift (typically 10 ppm/K), used for internal biasing, and connects
to the REFOUT pin. The circuit is intended as the reference point of the output signal to allow a bipolar signal
around it. The output is buffered for low impedance and tolerates sink and source currents of ±5 mA. Capacitive
loads may be directly connected, but generate ringing on fast load transients. A small series resistor of a few
ohms improves the response, especially for a capacitive load in the range of 1 μF. 图 41 illustrates this circuit
configuration and the transient load regulation with 1-nF direct load.
The reference source is part of the integrated circuit and referenced to GND2. Large current pulses driving the
compensation coil generates a voltage drop in the GND connection that may add on to the reference voltage.
Therefore, a low impedance GND layout is critical to handle the currents and the high bandwidth of the device.
Test Circuit:
10 kW
REFOUT
1 nF
±5 V
+2.5 V
2.5 ms/div
图 41. Pulse Response: Test Circuit and Scope Shot of Reference
7.3.8 Demagnetization
Iron cores are not immune to residual (remanence) magnetism. The residual remanence produces a signal offset
error, especially after strong current overload, which goes along with high magnetic field density. Therefore, the
DRV401-Q1 device includes a signal generator for a demagnetization cycle. The digital control pin, DEMAG,
starts the cycle on demand after the pin is held high for at least 25.6 μs. Shorter pulses are ignored. The cycle
lasts for approximately 110 ms. During this time, the ERROR flag is asserted low to indicate that the output is not
valid. When DEMAG is high during power-on, a demagnetization cycle immediately initiates (12 μs) after power-
on (VDD > 4 V). Holding DEMAG low avoids this cycle at power-up. See the Power-On and Brownout section for
more information.
The probe circuit is in normal operation and oscillates during the demagnetization cycle. The PWM and PWM
outputs are active accordingly.
A demagnetization cycle can be aborted by pulling DEMAG low, filtered by 25 μs to ignore glitches, as shown in
图 46. In a typical circuit, the DEMAG pin may be connected to the positive supply, which enables a degauss
cycle every time the unit is powered on.
The degauss cycle is based on an internal clock and counter logic. The maximum current is limited by the
resistance of the connected coil in series with the shunt resistor. The DEMAG logic input requires a 5-V, CMOS-
compatible signal.
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7.3.9 Power-On and Brownout
Power-on is detected with the supply voltage going higher than 4 V at VDD1. When DEMAG is high, a degauss
cycle is started, as shown in 图 46 through 图 49. During this time the ERROR flag remains low, indicating the
not ready condition. Maintaining DEMAG low prevents this cycle, and the DRV401-Q1 device starts operation
approximately 32 μs after power-up. If no probe error conditions are detected within four full cycles (that is, the
probe half-periods are shorter than 32 μs and longer than 280 ns), the compensation driver starts and the
ERROR pin indicates the ready condition by going high, typically about 42 μs after power-up.
注
An external pull-up resistor is required to pull the ERROR pin high.
Both supply pins (VDD1 and VDD2) must not differ by more than 100 mV for proper device operation. They are
normally connected together or separately filtered as shown in Layout.
The DRV401-Q1 device tests for low supply voltage with a brownout voltage level of 4 V; proper power
conditions must be supplied. Good power-supply and low equivalent series resistance (ESR) bypass capacitors
are required to maintain the supply voltage during the large current pulses that the DRV401-Q1 device drives.
A critical voltage level is derived from the proper operation of the probe driver. The probe interface relies on a
peak current flowing through the probe to trip the comparator. The probe resistance plus the internal resistance
of the driver (see Probe Coil Loop, Internal Resistor parameters in the Electrical Characteristics table) sets the
lower limit for the acceptable supply voltage. Voltage drops lasting less than 31 μs are ignored. The probe error
detection activates the ERROR pin when proper oscillation fails for more than 32 μs.
A low supply voltage condition, or brownout, is detected at 4 V. Short and light voltage drops of less than 100 μs
are ignored, provided the probe circuit continues to operate. If the probe no longer operates, the ERROR pin
goes active. Signal overload recovery is only provided if the probe loop was not discontinued.
A supply drop lasting longer than 100 μs generates power-on reset. A voltage dip down to 1.8 V (for VDD1
)
initiates a power-on reset.
7.3.10 Error Conditions
In addition to the overrange flag that indicates signal clipping in the output amplifier (differential amplifier), a
system error flag is provided. The ERROR flag indicates conditions when the output voltage does not represent
the primary current. The ERROR flag is active during a demagnetization cycle, power-fail, or brownout. The
ERROR flag becomes active with an open or short-circuit in the probe loop. When the error condition is no longer
present and the circuit returns to normal operation, the flag resets.
The ERROR and overrange flags are open-drain logic outputs. The flags connect together for a wired-OR and
require an external pull-up resistor for proper operation.
The following conditions result in ERROR flag activation (ERROR asserts low):
1. The probe comparator stays low for more than 32 μs. This condition occurs if the probe coil connection is
open or if the supply voltage dips to the level where the required saturation current cannot be reached.
During the 32-μs timeout, the ICOMP driver remains active but goes inactive thereafter. In case of recovery,
ERROR is low and the ICOMP driver remains in reset for another 3.3 ms.
2. The probe driver pulse-width is less than 280 ns for three consecutive periods. This condition indicates a
shorted field probe coil or a fully-saturated sensor at start-up. If this condition persists longer than 25 μs and
then recovers, the ERROR flag remains low and ICOMP is in reset for another 3.3 ms. If the condition lasts
less than 25 μs, the ERROR flag recovers immediately and the ICOMP driver is not interrupted.
3. During demagnetization, if the cycle is aborted early by pulling DEMAG low, the ERROR flag stays low for
another 3.3 ms (ICOMP is disabled during this time).
4. An open compensation coil is detected (longer than 100 μs). This condition indicates that not enough current
is flowing in the ICOMP driver output; this condition may be the result of a high-resistance compensation coil or
the connection of an external driver. Detection of this condition can be disabled by setting the CCdiag pin
low.
22
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DRV401-Q1
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ZHCSFT7 –DECEMBER 2016
注
The probe driver, the PWM signal filter, and the ICOMP driver continue to function in normal
mode. Only the ERROR flag is asserted in the case when an open compensation coil is
detected.
5. At power-on after VDD1 crosses the 4-V threshold, the ERROR flag is low for approximately 42 μs.
6. A supply voltage low (brownout) condition lasts longer than 100 μs. Recovery is the same as power-up, with
or without a demagnetization cycle.
7.3.11 Protection Recommendations
The IAIN1 and IAIN2 inputs require external protection to limit the voltage swing beyond 10 V of the supply voltage.
The driver outputs ICOMP1 and ICOMP2 handles high current pulses protected by internal clamp circuits to the
supply voltage. If repeated overcurrents of large magnitudes are expected, connect external Schottky diodes to
the supply rails. This external protection prevents current flowing into the die.
The IS1 and IS2 probe connections are protected with diode clamps to the supply rails. In normal applications,
no external protection is required. The maximum current must be limited to ±75 mA.
All other pins offer standard protection. See the Absolute Maximum Ratings table for more information.
7.4 Device Functional Modes
The DRV401-Q1 has a single functional mode and is operational when the power supply voltages, VDD1 and
VDD2, are between 4.5 V and 5.5 V. For unusual operating conditions where a brownout condition may occur the
DRV401-Q1 may perform a power-on reset. See the Power-On and Brownout section for a complete description
of operation during a brownout.
版权 © 2016, Texas Instruments Incorporated
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Functional Principle of Closed-Loop Current Sensors with Magnetic Probe Using the DRV401-Q1
Device
Closed-loop current sensors measure current over wide frequency ranges, including dc. These types of devices
offer a contact-free method and an excellent galvanic isolation performance combined with high resolution,
accuracy, and reliability.
At dc and in low-frequency ranges, the magnetic field induced from the current in the primary winding is
compensated by a current flowing through a compensation winding. A magnetic field probe, located in the
magnetic core loop, detects the magnetic flux. This probe delivers the signal to the amplifier that drives the
current through the compensation coil, bringing the magnetic flux back to zero. This compensation current is
proportional to the primary current, relative to the winding ratio.
In higher-frequency ranges, the compensation winding acts as the secondary winding in the current transformer,
while the H-bridge compensation driver is rolled off and provides low output impedance.
A difference amplifier senses the voltage across a small shunt resistor that is connected to the compensation
loop. This difference amplifier generates the output voltage that is referenced to REFIN and is proportional to the
primary current. The Functional Block Diagram shows the DRV401-Q1 device used as a compensation current
sensor.
24
版权 © 2016, Texas Instruments Incorporated
DRV401-Q1
www.ti.com.cn
ZHCSFT7 –DECEMBER 2016
Application Information (接下页)
8.1.2 Basic Connection
The circuit shown in 图 42 offers an example of a fully-connected current sensor system.
IP
Primary Winding
Current Sensor Module
Probe
Core
Main Core
Probe Coil
S2
Compensation Coil
S1
K1
K2
+5 V
IS2
ICOMP
R3
R4
C4
D1
D2
C3
R2
R1
+5 V
IS1
IS2
PWM PWM
GAIN
CCdiag
ICOMP1 ICOMP2 IAIN2
IAIN1
(PWM is in
phase with IS1)
Amp
V = 4
+5 V
R6
+5 V
VDD1
Integrator
Probe Coil
Driver and
Comparator
OVER-RANGE
VOUT
H-Bridge
Driver
C2
VSW
R5
GND1
REFIN
VSW
2.5 V
Bandgap
Reference
REFOUT
10 MHz
DEMAG
Logic: Timing, Error Detection, and Demagnetize
Oscillator Reset
Power Valid
DRV401-Q1
R7
ERROR
VDD2
C4
GND2
+5 V
+5 V
Copyright © 2016, Texas Instruments Incorporated
图 42. Basic Connection Circuit
The connection example in 图 42 illustrates the few external components required for optimal performance. Each
component is described in the following list:
•
•
IP is the primary current to be measured; K1 and K2 connect to the compensation coil. S1 and S2 connect to
the magnetic field probe. The dots indicate the winding direction on the sensor main core.
R1 and R2 form the shunt resistor RSHUNT. This resistance is split into two to allow for adjustments to the
required RSHUNT value. The accuracy and temperature stability of these resistors are part of the final system
performance.
•
R3 and R4, together with C3 and C4, form a network that reduces the remaining probe oscillator ripple in the
output signal. The component values depend on the sensor type and are tailored for best results. This
network is not required for normal operation.
版权 © 2016, Texas Instruments Incorporated
25
DRV401-Q1
ZHCSFT7 –DECEMBER 2016
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Application Information (接下页)
•
R5 is the dummy shunt (RD) resistor used to restore the symmetry of both differential amplifier inputs. R5 = 4
× RSHUNT, but the accuracy is less important.
•
•
R6 and R7 are pull-up resistors connected to the logic outputs.
C1 and C2 are decoupling capacitors. Use low ESR-type capacitors connected close to the pins. Use low-
impedance printed circuit board (PCB) traces, either avoiding vias (plated-through holes) or using multiple
vias. A combination of a large (> 1-μF) and a small (< 4.7-nF) capacitor are suggested. When selecting
capacitors, make sure to consider the large pulse currents handled from the DRV401-Q1 device.
•
D1 and D2 are protection diodes for the differential amplifier input. They are only needed if the voltage drop at
RSHUNT exceeds 10 V at the maximum possible peak current.
8.2 Typical Application
The differential (H-bridge) driver arrangement for the compensation coil requires a differential sense amplifier for
the shunt voltage. This differential amplifier offers wide bandwidth and a high slew rate for fast current sensors.
Excellent dc stability and accuracy result from an auto-zero technique. The voltage gain is 4 V/V, set by precisely
matched and stable internal SiCr resistors.
Both inputs of the differential amplifier are normally connected to the current shunt resistor. The resistor adds to
the internal (10-kΩ) resistor, slightly reducing the gain in this leg. For best common-mode rejection (CMR), a
dummy shunt resistor (R5) is placed in series with the REFIN pin to restore matching of both resistor dividers, as
shown in 图 43.
DRV401-Q1
Differential Amplifier Section
ICOMP2
R1
R2
10 kW
40 kW
Decoupling, Low-Pass Filter
RF
50 W
VOUT
RSHUNT
ADC
CF
Differential
Amplifier
10 nF
R5
R3
R4
40 kW
Dummy
Shunt
10 kW
REFIN
Compensated
REFIN
K2
Copyright © 2016, Texas Instruments Incorporated
R5 is a dummy shunt resistor equal to 4 × RSHUNT to compensate for RSHUNT and provide optimal CMR.
图 43. Internal Difference Amplifier with an Example of a Decoupling Filter
8.2.1 Design Requirements
•
•
•
•
Operate from a single 5-V power supply.
Measure the compensation coil current with a gain = 4 V/V.
Maximize the gain accuracy.
Minimize the common-mode error.
26
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DRV401-Q1
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ZHCSFT7 –DECEMBER 2016
Typical Application (接下页)
8.2.2 Detailed Design Procedure
For gains of 4 V/V, 公式 2 shows the calculation:
R2
R4 + R5
4 =
=
R1 RSHUNT + R3
(2)
With R2 / R1 = R4 / R3 = 4; R5 = RSHUNT × 4.
Typically, the gain error resulting from the resistance of RSHUNT is negligible; for 70 dB of common-mode
rejection, however, the match of both divider ratios must be better than 1/3000.
The amplifier output may drive close to the supply rails, and is designed to drive the input of a successive-
approximation resistance (SAR)-type ADC; adding an RC low-pass filter stage between the DRV401-Q1 device
and the ADC is recommended. This filter limits the signal bandwidth and decouples the high-frequency
component of the converter input sampling noise from the amplifier output. For RF and CF values, see the
specific converter recommendations in the specific product data sheet. Empirical evaluation may be necessary to
obtain optimum results.
The output drives 100 pF directly and shows 50% overshoot with approximately 1-nF capacitance. Adding RF
allows much larger capacitive loads, as shown in 图 44 and 图 45.
注
Note that with an RF value of only 20 Ω, the load capacitor must be smaller than 1 nF or
larger than 33 nF to avoid overshoot; with an RF value of 50 Ω, this transient area is
avoided.
The reference input (REFIN) is the reference node for the exact output signal (VOUT). Connecting REFIN to the
reference output (REFOUT) results in a live zero reference voltage of 2.5 V. Using the same reference for REFIN
and the ADC avoids mismatch errors that exist between two reference sources.
8.2.3 Application Curves
10 ms/div
10 ms/div
R5 = 20 Ω, CD
=
R5 = 50 Ω, CD = 10
100 nF
nF
图 44. 图 44 Performance (VOUT
)
图 45. 图 45 Performance (VOUT)
版权 © 2016, Texas Instruments Incorporated
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DRV401-Q1
ZHCSFT7 –DECEMBER 2016
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9 Power Supply Recommendations
The DRV401-Q operates from a single power supply, nominally 5 V, and must remain between 4.5 V and 5.5 V
for normal operation. See 图 46, 图 47, 图 48, and 图 49 for device power-on behavior.
VDD1
V(ERROR)
106 ms
1
4
V(ICOMP2
)
RSH = 10 W
2
VOUT
3
20 ms/div
With power-up, the VOUT across the compensation coil centers around half the supply and then starts the cycle after
the 4-V threshold is exceeded. The ERROR flag resets to H after the cycle is completed.
图 46. Demagnetization and Power-On Timing: Demagnetization Cycle on Power-Up
VDD1
42 ms
1
V(ERROR)
4
V(IS1)
2
V(ICOMP2
)
Initial setting upon
3
closing of feedback loop.
20 ms/div
The probe oscillation V(IS1) starts just before ERROR resets—15 μs after the supply voltage crosses the 4-V
threshold.
图 47. Demagnetization and Power-On Timing: Power-Up Without Demagnetization
V(DEMAG)
1
V(ERROR)
106 ms
4
V(ICOMP2
)
2
RSH = 10 W
VOUT
3
20 ms/div
图 48. Demagnetization and Power-On Timing: Demagnetization Cycle On Command
28
版权 © 2016, Texas Instruments Incorporated
DRV401-Q1
www.ti.com.cn
ZHCSFT7 –DECEMBER 2016
V(DEMAG)
1
4
V(ERROR)
V(ICOMP2
)
RSH = 10 W
2
3.4 ms
VOUT
3
500 ms/div
The ERROR flag resets to H (as shown) and the output settles back to normal operation.
图 49. Demagnetization and Power-On Timing: Abort of Demagnetization Cycle
10 Layout
10.1 Layout Guidelines
The typical device configuration is shown in 图 42. The DRV401-Q1 operates with relatively large currents and
fast current pulses, and offers wide-bandwidth performance. The device is often exposed to large distortion
energy from the primary signal and the operating environment. Therefore, the wiring layout must provide
shielding and low-impedance connections between critical points.
Use low-ESR capacitors for power-supply decoupling. Use a combination of a small capacitor and a large
capacitor with a 1-μF or larger value. Use low-impedance tracks to connect the capacitors to the pins.
Both grounds must be connected to a local ground plane. Both supplies can be connected together; however,
best results are achieved with separate decoupling (to the local GND plane) and ferrite beads in series with the
main supply. The ferrite beads decouple the DRV401-Q1 device, reducing interaction with other circuits powered
from the same supply voltage source.
The reference output is referred to GND2. A low-impedance, star-type connection is required to avoid the driver
current and the probe current modulating the voltage drop on the ground track.
The connection wires of the difference amplifier to the shunt must be low resistance and of equal length. For best
accuracy, avoid current in this connection. Consider using a Kelvin Contact-type connection. The required
resistance value may be set using two resistors.
Wires and PCB traces for S1 and S2 must be close or twisted. ICOMP1 and ICOMP2 must be wired close together.
To avoid capacitive coupling, run a ground shield between the S1/S2 and ICOMP wire pair or keep them distant
from each other.
The compensation driver outputs (ICOMP) are low frequency only. However, the primary signal (with high-
frequency content present) is coupled into the compensation winding, the shunt, and the difference amplifier. TI
recommends a careful layout.
The REFOUT and VOUT output drives some capacitive loads, but avoid large direct capacitive loads; these loads
increase internal pulse currents. Given the wide bandwidth of the differential amplifier, isolate any large
capacitive load with a small series resistor. A small capacitor (in the pF range) improves the transient response
on a high resistive load.
The exposed thermal pad on the bottom of the package must be soldered to GND because the thermal pad is
internally connected to the substrate, which must be connected to the most negative potential. Solder the
exposed pad to the PCB to provide structural integrity and long-term reliability.
版权 © 2016, Texas Instruments Incorporated
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DRV401-Q1
ZHCSFT7 –DECEMBER 2016
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10.2 Layout Example
Probe coil
20 19 18 17 16
+5V
1
2
3
4
5
15
14
13
12
11
Exposed
thermal pad,
connect to
GND1
+5V
6
7
8
9
10
Compensation
coil
VOUT
+5V
Copyright © 2016, Texas
Instruments Incorporated
图 50. DRV401-Q1 Layout Example (RGW Package)
10.3 Power Dissipation
Using the thermally-enhanced VQFN package dramatically reduces the thermal impedance from junction to case.
This package is constructed using a down-set lead frame that the die is mounted on. This arrangement results in
the lead frame exposed as a thermal pad on the underside of the package. Because this thermal pad has direct
thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path
away from the thermal pad.
The two outputs (ICOMP1 and ICOMP2) are linear outputs. Therefore, the power dissipation on each output is
proportional to the current multiplied by the internal voltage drop on the active transistor. For ICOMP1 and ICOMP2
,
this internal voltage drop is the voltage drop to VDD2 or GND, according to the current-conducting side of the
output.
Output short-circuits are particularly critical for the driver because the full supply voltage can be seen across the
conducting transistor, and the current is not limited by anything other than the current density limitation of the
FET. Permanent damage to the device may occur.
The DRV401-Q1 does not include temperature protection or thermal shutdown.
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 TINA-TI™（免费软件下载）
TINA™是一款简单、功能强大且易于使用的电路仿真程序，此程序基于 SPICE 引擎。TINA-TI 是 TINA 软件的一
款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 提供所有传
统的 SPICE 直流、瞬态和频域分析，以及其他设计功能。
30
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器件支持 (接下页)
TINA-TI 可从 WEBENCH® 设计中心免费下载，它提供全面的后续处理能力，使得用户能够以多种方式形成结果。
虚拟仪器提供选择输入波形和探测电路节点、电压和波形的功能，从而创建一个动态的快速入门工具。
注
这些文件需要安装 TINA 软件（由 DesignSoft™提供）或者 TINA-TI 软件。请从 TINA-TI 文
件夹 中下载免费的 TINA-TI 软件。
11.1.1.2 TI 高精度设计
TI 高精度设计是由 TI 公司高精度模拟 应用 专家创建的模拟解决方案，提供了许多实用电路的工作原理、组件选
择、仿真、完整印刷电路板 (PCB) 电路原理图和布局布线、物料清单以及性能测量结果。欲获取 TI 高精度设计，
请访问 http://www.ti.com.cn/ww/analog/precision-designs/。
11.1.1.3 WEBENCH® Filter Designer
WEBENCH® 滤波器设计器是一款简单、功能强大且便于使用的有源滤波器设计程序。借助WEBENCH 滤波设计
器，用户可使用精选 TI 运算放大器和 TI 供应商合作伙伴提供的无源组件来打造最佳滤波器设计方案。
WEBENCH® 设计中心以基于网络的工具形式提供 WEBENCH® 滤波器设计器。用户通过该工具可在短时间内完
成多级有源滤波器解决方案的设计、优化和仿真。
11.2 文档支持
11.2.1 相关文档
使用 DRV401-Q1 器件时，建议参考下列相关文档。除非另外注明，否则这些文档均可从 www.ti.com 下载。
•
•
•
《PowerPAD 散热增强型封装》 (SLMA002)
《四方扁平无引线逻辑器件封装》（文献编号：SCBA017）
《QFN/SON PCB 连接》（文献编号：SLUA271）
11.3 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 商标
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
版权 © 2016, Texas Instruments Incorporated
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ZHCSFT7 –DECEMBER 2016
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11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
32
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DRV401-Q1
www.ti.com.cn
ZHCSFT7 –DECEMBER 2016
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
12.1 散热焊盘
散热焊盘外露型封装经专门设计可提供出色的功率耗散，但电路板布局会严重影响总体热耗散。表 1 显示了将外露
散热焊盘焊接到常规 PCB 上的种封装的热阻 (θJA)，如《PowerPAD 散热增强型封装》 (SLMA002) 所述。请参阅
EIA/JEDEC 规范 JESD51-0 至 JESD51-7、《QFN/SON PCB 连接》 (SLUA271) 和《方形扁平无引脚逻辑封装》
(SCBA017)。这些文档可从 www.ti.com.cn 下载。
表 1. 根据 EIA/JED51-7 规范得出的 θJA 和 θJP 估算值(1)
参数
VQFN
9
θJP
θ
JA（不通风时）
JA（强制通风，气流为 150lfm 时）
40
θ
38
(1) θJA = 结至环境热阻。
TI 建议测量尽可能靠近散热焊盘处的温度。热阻值 θJP 相对较低，小于 10°C/W（到 PCB 上的温度测试点具有一
些额外热阻），从而可对应用中的结温进行很好的估算。
PCB 上的散热焊盘必须包含九个或更多个适用于 VQFN 封装的通孔。
组件填充、线迹布局、层级和气流均会严重影响热耗散。必须在实际运行环境中测试最差的负载情况，以确保温度
条件适当。应最大程度地减小热应力，以实现长期正常运行，并使结温远低于 125°C。
注
所有热模型的精度 ≈ 20%。
版权 © 2016, Texas Instruments Incorporated
33
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV401AQRGWRQ1
ACTIVE
VQFN
RGW
20
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV
401Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
RGW 20
5 x 5, 0.65 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4227157/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGW0020A
PLASTIC QUAD FLATPACK-NO LEAD
5.1
4.9
B
PIN 1 INDEX AREA
5.1
4.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
3.15±0.1
2X 2.6
(0.1) TYP
10
6
16X 0.65
5
11
SYMM
21
2X
2.6
15
1
0.36
0.26
20X
PIN1 ID
(OPTIONAL)
0.1
C A B
C
20
16
0.05
SYMM
0.65
0.45
20X
4219039/A 06/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGW0020A
PLASTIC QUAD FLATPACK-NO LEAD
(4.65)
3.15)
(2.6)
(
20
16
16X (0.65)
15
1
(1.325)
21
SYMM
(4.65) (2.6)
(R0.05) TYP
11
5
20X (0.31)
20X (0.75)
(Ø0.2) VIA
6
10
TYP
(1.325)
SYMM
LAND PATTERN EXAMPLE
SCALE: 15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219039/A 06/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGW0020A
PLASTIC QUAD FLATPACK-NO LEAD
(4.65)
4X ( 1.37)
2X (0.785)
16
20
16X (0.65)
21
1
15
2X (0.785)
SYMM
(4.65) (2.6)
(R0.05) TYP
11
5
20X (0.31)
20X (0.75)
METAL
TYP
6
10
SYMM
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
75% PRINTED COVERAGE BY AREA
SCALE: 15X
4219039/A 06/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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