DRV5825P [TI]
具有智能 I/V 保护的 4.5V 至 26.4V、7.5A 立体声、15A 单声道、数字输入压电式驱动器;
| 型号： | DRV5825P |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有智能 I/V 保护的 4.5V 至 26.4V、7.5A 立体声、15A 单声道、数字输入压电式驱动器 驱动 驱动器 |
| 文件： | 总96页 (文件大小：3204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZHCSLS8 – AUGUST 2020
DRV5825P
具有自适应 I/V 限制器的 DRV5825P 数字输入 48VPP 7.5A 立体声/15A 单声道压
电式扬声器驱动器
1 特性
2 应用
•
灵活的音频 I/O：
• DTV、HDTV、UHD 和多功能监控器
– 支持 32、44.1、48、88.2、96kHz 采样率
– 用于音频监控或回声消除的 I2S、LJ、RJ、TDM
和 SDOUT
•
笔记本电脑，平板电脑
3 说明
DRV5825P 是一款高性能的立体声闭环 D 类扬声器驱
动器，具有集成的音频处理器和高达 96kHz 的架构。
– 支持三线制数字音频接口（无需 MCLK）
高电压、大电流压电式驱动器
– 48VPP
•
•
强大的音频 DSP 内核支持高级音频处理。集成的 SRC
（采样率转换器）可检测到输入采样率变化，然后自动
转换为 DSP 正在运行的目标采样率以避免任何音频失
真。这些处理流支持：2×15 个 BQ、基于压电式扬声
器阻抗和 LC 滤波器模型的自适应 I/V 限制器、全频带
AGL（自动增益限制器）、THD 管理器（斩波器）。
– 立体声 2.0 模式：2 × 7.5A
– 1.0 模式：1 × 15A
自适应 I/V 限制器
– 可调节限流阈值
– 基于阻抗和频率的电流限制器
– 在触发限制器之前无增益衰减
– 无需外部功率电阻器
器件信息
封装(1)
封装尺寸（标称值）
器件型号
DRV5825P
VQFN (32) RHB
5.00mm × 5.00mm
•
•
优异的音频性能：
– Vout = 2Vrms、1kHz、PVDD = 12V 条件下，
THD+N ≤ 0.03%
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– SNR ≥ 110dB（A 加权），ICN ≤ 45µVRMS
高级处理特性
Piezo Speaker
L Channel
Piezo Speaker
R Channel
– SRC（采样率转换器）、直流阻断
– 输入混合器、输出交叉开关、电平计
– 2 × 15 个 BQ、2 个后处理 BQ、斩波器
– 自适应 I/V 限制器、全频带 AGL
灵活的电源配置
•
•
– PVDD：4.5V 至 26.4V
– DVDD 和 I/O：1.8V 或 3.3V
出色的集成式自保护功能：
– 过流错误 (OCE)
– 逐周期电流限制
– 过热警告 (OTW)
– 过热错误 (OTE)
– 欠压/过压锁定 (UVLO/OVLO)
可轻松进行系统集成
•
– I2C 软件控制
Digital
Audio
Source
System
Processor
– 解决方案尺寸更小
•
•
•
小型 5 x 5mm 封装
简化版原理图
无需外部功率电阻器
大多数应用都不需要体积较大的电解电容器
或大型电感器
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASEV7
DRV5825P
ZHCSLS8 – AUGUST 2020
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Table of Contents
8.3 Feature Description...................................................16
8.4 Device Functional Modes..........................................22
8.5 Programming and Control.........................................25
8.6 Register Maps...........................................................33
9 Application and Implementation..................................75
9.1 Application Information............................................. 75
9.2 Typical Applications.................................................. 77
10 Power Supply Recommendations..............................81
10.1 DVDD Supply..........................................................81
10.2 PVDD Supply..........................................................82
11 Layout...........................................................................83
11.1 Layout Guidelines................................................... 83
11.2 Layout Example...................................................... 85
12 Device and Documentation Support..........................87
12.1 Device Support....................................................... 87
12.2 Receiving Notification of Documentation Updates..87
12.3 Support Resources................................................. 87
12.4 Trademarks.............................................................87
12.5 Electrostatic Discharge Caution..............................88
12.6 Glossary..................................................................88
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................6
6.6 Timing Requirements .................................................9
6.7 Typical Characteristics..............................................10
7 Typical Characteristics................................................. 13
7.1 Bridge Tied Load (BTL) Configuration...................... 13
7.2 Parallel Bridge Tied Load (PBTL) Configuration.......14
8 Detailed Description......................................................15
8.1 Overview...................................................................15
8.2 Functional Block Diagram.........................................15
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
August 2020
*
Initial release.
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5 Pin Configuration and Functions
BST_A+
OUT_A+
PVDD
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
BST_B+
OUT_B+
PVDD
PVDD
AGND
AVDD
GVDD
PDN
PVDD
Thermal
Pad
DGND
DVDD
VR_DIG
ADR
Not to scale
图 5-1. RHB Package 32-Pin VQFN Top View
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
DGND
DVDD
VR_DIG
ADR
NO.
5
6
7
8
P
P
Digital ground
3.3-V or 1.8-V digital power supply
P
Internally regulated 1.5-V digital supply voltage. This pin must not be used to drive external devices
A table of resistor value (Pull down to GND) will decide device I2C address. See 表 8-5.
AI
General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and
0x61h). Can be configured to be CMOS output or Open drain output (WARNZ or FAULTZ)
GPIO0
GPIO1
GPIO2
9
DI/O
DI/O
DI/O
General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and
0x62h). Can be configured to be CMOS output or Open drain output (WARNZ or FAULTZ)
10
11
General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and
0x63h). Can be configured to be CMOS output or Open drain output (WARNZ or FAULTZ)
Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this
corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync
boundary.
LRCLK
SCLK(2)
12
13
DI
DI
Bit clock for the digital signal that is active on the input data line of the serial data port. Sometimes, this pin also be
written as "bit clock (BCLK)"
SDIN
SDA
14
15
16
17
18
19
20
DI
DI/O
DI
DI
P
Data line to the serial data port
I2C serial control data interface input/output
SCL
I2C serial control clock input
PDN
Power down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators.
Gate drive internal regulator output. This pin must not be used to drive external devices
Internally regulated 5-V analog supply voltage. This pin must not be used to drive external devices
Analog ground
GVDD
AVDD
AGND
P
P
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PIN
TYPE(1)
DESCRIPTION
NAME
NO.
3
P
P
P
P
P
P
P
P
O
4
PVDD
PVDD voltage input
21
22
25
26
31
32
23
PGND
Ground reference for power device circuitry. Connect this pin to system ground.
Positive pin for differential speaker amplifier output B
OUT_B+
BST_B+
OUT_B-
BST_B-
Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side
gate drive for OUT_B+
24
27
28
P
O
P
Negative pin for differential speaker amplifier output B
Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate
drive for OUT_B-
Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate
drive for OUT_A-
BST_A-
OUT_A-
BST_A+
29
30
1
P
O
P
Negative pin for differential speaker amplifier output A
Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side
gate drive for OUT_A+
OUT_A+
2
O
P
Positive pin for differential speaker amplifier output A
Connect to the system Ground
PowerPAD™
(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P =
Power, G = Ground (0 V)
(2) Typically written "bit clock (BCLK)" in some audio codecs.
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6 Specifications
6.1 Absolute Maximum Ratings
Free-air room temperature 25°C (unless otherwise noted) (1)
MIN
–0.3
–0.3
–0.5
–0.3
–25
–40
MAX
UNIT
V
DVDD
PVDD
VI(DigIn)
VI(SPK_OUTxx)
TA
Low-voltage digital supply
PVDD supply
3.9
30
V
DVDD referenced digital inputs(2)
Voltage at speaker output pins
Ambient operating temperature,
Storage temperature
VDVDD + 0.5
V
32
85
V
°C
°C
Tstg
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under
Recommended OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device
reliability.
(2) DVDD referenced digital pins include: ADR, GPIO0, GPIO1,GPIO2, LRCLK, SCLK, SDIN,,SCL, SDA, PDN
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.62
4.5
NOM
MAX
3.63
26.4
UNIT
DVDD
PVDD
V(POWER)
Power supply inputs
V
Minimum inductor value in LC filter under short-circuit
condition
LOUT
1
4.7
µH
6.4 Thermal Information
DRV5825P
VQFN (RHB)
32 PINS
THERMAL METRIC(1)
UNIT
JEDEC
STANDARD
4-LAYER PCB
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
30
19.1
9.9
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.2
10.5
ψJB
(1) For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application
report.
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6.5 Electrical Characteristics
Free-air room temperature 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL I/O
Input logic high current
|IIH|
level for DVDD referenced VIN(DigIn) = VDVDD
digital input pins
10
µA
µA
Input logic low current level
|IIL|
for DVDD referenced
digital input pins
VIN(DigIn) = 0 V
–10
Input logic high threshold
for DVDD referenced
digital inputs
VIH(Digin)
70%
80%
VDVDD
Input logic low threshold
for DVDD referenced
digital inputs
VIL(Digin)
30%
VDVDD
Output logic high voltage
level
VOH(Digin)
VOL(Digin)
IOH = 4 mA
VDVDD
VDVDD
Output logic low voltage
level
20%
400
IOH = –4 mA
I2C CONTROL PORT
Allowable load capacitance
CL(I2C)
pF
for each I2C Line
fSCL(fast)
fSCL(slow)
Support SCL frequency
Support SCL frequency
No wait states, fast mode
No wait states, slow mode
400
100
kHz
kHz
SERIAL AUDIO PORT
Required LRCK/FS to
SCLK rising edge delay
tDLY
DSCLK
fS
5
40%
32
ns
Allowable SCLK duty cycle
60%
96
Supported input sample
rates
kHz
Supported SCLK
frequencies
fSCLK
fSCLK
32
64
fS
SCLK frequency
24.576
MHz
SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS)
toff
Turn-off Time
Excluding volume ramp
10
ms
Quiescent supply current
of DVDD
PDN=2V,DVDD=3.3V,Play mode, Piezo
Drive Alolgorithm Enable,48kHz
ICC
17.5
0.87
0.82
7.4
mA
Quiescent supply current
of DVDD
ICC
ICC
ICC
PDN=2V,DVDD=3.3V,Sleep mode
mA
mA
uA
Quiescent supply current
of DVDD
PDN=2V,DVDD=3.3V,Deep Sleep mode
PDN=0.8V,DVDD=3.3V,Shutdown mode
Quiescent supply current
of DVDD
PDN=2V, PVDD=24V, No Load, LC filter =
10uH + 0.47uF, Fsw = 768kHz, Output Hiz
Mode
Quiescent supply current
of PVDD
ICC
ICC
ICC
10.9
7.3
mA
mA
uA
Quiescent supply current
of PVDD
PDN=2V, PVDD=24V, No Load, LC filter =
10uH + 0.47uF, Fsw = 768kHz, Sleep Mode
PDN=2V, PVDD=13.5V, No Load, LC filter =
10uH + 0.47uF, Fsw = 768khz, Deep Sleep
Mode
Quiescent supply current
of PVDD
12.01
PDN=0.8V, PVDD=13.5V, No Load, LC filter
= 10uH + 0.47uF, Fsw = 768khz, Shutdown
Mode
Quiescent supply current
of PVDD
ICC
7.8
uA
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6.5 Electrical Characteristics (continued)
Free-air room temperature 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Value represents the "peak voltage"
disregarding clipping due to lower PVDD).
Measured at 0 dB input (1FS)
AV(SPK_AMP)
Programmable Gain
4.87
29.5
V
Amplifier gain error
Gain = 29.5 Vp
0.5
dB
ΔAV(SPK_AMP)
Switching frequency of the
speaker amplifier
fSPK_AMP
768
kHz
Drain-to-source on
RDS(on)
resistance of the individual FET + Metallization.
output MOSFETs
90
mΩ
Over-Current Error
Threshold
Any short to supply, ground, or other
channels, BTL Mode
7
6
7.5
6.5
15
A
A
Over-Current cycle-by-
cycle limit
OCETHRES
BTL Mode
Over-Current Error
Threshold
Any short to supply, ground, or other
channels, PBTL Mode
14
A
PVDD over voltage error
threshold
OVETHRES(PVDD
UVETHRES(PVDD
OTETHRES
28
V
PVDD under voltage error
threshold
4.2
160
10
V
Over temperature error
threshold
°C
°C
°C
°C
°C
°C
Over temperature error
hysteresis
OTEHystersis
OTWTHRES
Over temperature warning
level 1
Read by register 0x73 bit0
Read by register 0x73 bit1
Read by register 0x73 bit2
Read by register 0x73 bit3
112
122
134
146
Over temperature warning
level 2
OTWTHRES
Over temperature warning
level 3
OTWTHRES
Over temperature warning
level 4
OTWTHRES
SPEAKER AMPLIFIER (STEREO BTL)
Measured differentially with zero input data,
programmable gain configured with 29.5
Vp/FS gain, VPVDD = 24 V
|VOS
|
Amplifier offset voltage
5
mV
–5
Idle channel noise(A-
weighted, AES17)
ICN(SPK)
DR
VPVDD = 24 V, LC-filter, BD Modualtion
45
111
111
72
µVrms
dB
A-Weighted, -60dBFS method, PVDD=24V,
SPK_GAIN=29.5VP/FS
Dynamic Range
A-Weighted, referenced to 1% THD+N
Output Level, PVDD = 24 V
SNR
KSVR
Signal-to-noise ratio
dB
Power supply rejection
ratio
Injected Noise = 1 KHz, 1 Vrms, PVDD = 14.4
V, input audio signal = digital zero
dB
Cross-talk (worst case
between left-to-right and
right-to-left coupling)
X-talkSPK
f = 1 KHz
100
dB
SPEAKER AMPLIFIER (MONO PBTL)
Measured differentially with zero input data,
programmable gain configured with 29.5 Vp
gain, VPVDD = 24 V
|VOS
DR
|
Amplifier offset voltage
Dynamic range
-7.5
7.5
mV
dB
A-Weighted, -60 dBFS method, PVDD=19V
109
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6.5 Electrical Characteristics (continued)
Free-air room temperature 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
A-Weighted, referenced to 1% THD+N
Output Level, PVDD = 19 V
109
dB
SNR
Signal-to-noise ratio
A-Weighted, referenced to 1% THD+N
Output Level, PVDD = 24 V
111
dB
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6.6 Timing Requirements
MIN
NOM
MAX
UNIT
Serial Audio Port Timing – Slave Mode
fSCLK
tSCLK
tSCLKL
tSCLKH
tSL
SCLK frequency
1.024
40
16
16
8
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
kHz
µs
µs
µs
µs
µs
ns
ns
ns
SCLK period
SCLK pulse width, low
SCLK pulse width, high
SCLK rising to LRCK/FS edge
LRCK/FS Edge to SCLK rising edge
Data setup time, before SCLK rising edge
Data hold time, after SCLK rising edge
Data delay time from SCLK falling edge
tLS
8
tSU
8
tDH
8
tDFS
15
I2C Bus Timing – Standard
fSCL
SCL clock frequency
100
tBUF
Bus free time between a STOP and START condition
Low period of the SCL clock
4.7
tLOW
tHI
4.7
High period of the SCL clock
Setup time for (repeated) START condition
Hold time for (repeated) START condition
Data setup time
4
tRS-SU
tS-HD
tD-SU
tD-HD
tSCL-R
4.7
4
250
Data hold time
0
3450
1000
Rise time of SCL signal
20 + 0.1CB
Rise time of SCL signal after a repeated START condition and
after an acknowledge bit
tSCL-R1
20 + 0.1CB
1000
ns
tSCL-F
tSDA-R
tSDA-F
tP-SU
Cb
Fall time of SCL signal
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
4
1000
1000
1000
ns
ns
ns
µs
pf
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
Capacitive load for each bus line
400
400
I2C Bus Timing – Fast
fSCL
SCL clock frequency
kHz
µs
µs
ns
ns
ns
ns
ns
ns
tBUF
Bus free time between a STOP and START condition
Low period of the SCL clock
High period of the SCL clock
Setup time for (repeated)START condition
Hold time for (repeated)START condition
Data setup time
1.3
tLOW
tHI
1.3
600
tRS-SU
tRS-HD
tD-SU
tD-HD
tSCL-R
600
600
100
Data hold time
0
900
300
Rise time of SCL signal
20 + 0.1CB
Rise time of SCL signal after a repeated START condition and
after an acknowledge bit
tSCL-R1
20 + 0.1CB
300
ns
tSCL-F
tSDA-R
tSDA-F
tP-SU
tSP
Fall time of SCL signal
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
600
300
300
300
ns
ns
ns
ns
ns
pf
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
Pulse width of spike suppressed
Capacitive load for each bus line
50
Cb
400
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6.7 Typical Characteristics
6.7.1 Bridge Tied Load (BTL) Configuration
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using DRV5825PEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 768 kHz with 175kHz
Loop Bandwidth and BD Modulation, 2 channel run, PPC3 setting with 5.5A current limiter, unless otherwise
noted.
10
5
10
5
PVDD=12V
TA=25èC
Load=1mF
LC Filter=10uH+0.68uF
PVDD=12V
TA=25èC
BTL Mode
VOUT=6VP
2
1
2
1
Load=1mF
LC Filter=10mH+0.68mF
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
Fin=1kHz
Fin=5kHz
Fin=10kHz
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
1
Output Voltage (Vrms)
D80002
D08071
LC Filter = 10µH +
0.68µF
VOUT = 6 VP
Load = 1 µF
LC Filter = 10µH + Input Frequency =
0.68µF 1kHz,5kHz,10kHz
Load = 1 µF
图 6-1. THD+N vs Frequency
图 6-2. THD+N vs Output Voltage (Per Channel)
0.4
Fin=1kHz
Fin=5kHz
Fin=10kHz
PVDD=12V
BTL Mode
2 Channel Run
Load=1mF
0.3
0.2
0.1
0
LC Filter=10mH+0.68mF
0
2
4
VOUT (Vrms)
6
8
D800387814
LC Filter = 10µH + 0.68µF
Input Frequency = 1kHz,5kHz,10kHz
Load = 1 µF
图 6-3. Supply Current vs Output Voltage (Per Channel)
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6.7.2 Parallel Bridge Tied Load (PBTL) Configuration
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using DRV5825PEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 768 kHz with 175kHz
Loop bandwidth, BD Modulation, the LC filter used was 3.3 μH / 0.47 μF （Post-Filter PBTL), PPC3 setting
with 9A current limiter, unless otherwise noted.
10
5
10
5
PVDD=24V
TA=25èC
Load=4mF
LC Filter=3.3mH+0.47mF
PBTL Mode
PVDD=24V
TA=25èC
PBTL Mode
Load=4mF
LC Filter=3.3mH+0.47mF
VOUT=12VP
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
Fin=1kHz
Fin=5kHz
Fin=10kHz
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
1
10
Output Voltage (Vrms)
D80032
D0807
LC Filter = 3.3µH +
0.47µF
VOUT = 12 VP
Load = 4 µF
LC Filter = 3.3µH + Input Frequency =
0.47µF 1kHz,5kHz,10kHz
Load = 4 µF
图 6-4. THD+N vs Frequency
图 6-5. THD+N vs Output Voltage
1
PVDD=24V
PBTL Mode
Load=4mF
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
LC Filter=3.3mH+0.47mF
Fin=1kHz
Fin=5kHz
Fin=10kHz
0
2
4
6
8 10
VOUT (Vrms)
12
14
16
18
D80038718
LC Filter = 3.3µH + 0.47µF
Input Frequency = 1kHz,5kHz,10kHz
Load = 4 µF
图 6-6. Supply Current vs Output Voltage
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Parameter Measurement Information
LRCK/FS
(Input)
0.5 × DVDD
0.5 × DVDD
t
t
SCLKL
SCLKH
t
LS
SCLK
(Input)
t
t
SL
SCLK
DATA
(Input)
0.5 × DVDD
0.5 × DVDD
STOP
t
t
DH
SU
t
DFS
DATA
(Output)
图 7-1. Serial Audio Port Timing in Slave Mode
Repeated
START
START
t
t
t
t
P-SU
t
D-SU
D-HD
SDA-F
SDA-R
t
BUF.
SDA
t
t
t
SP
SCL-R.
RS-HD
t
LOW.
SCL
t
HI.
t
RS-SU
t
t
SCL-F.
S-HD.
图 7-2. I2C Communication Port Timing Diagram
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7 Typical Characteristics
7.1 Bridge Tied Load (BTL) Configuration
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using DRV5825PEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 768 kHz with 175kHz
Loop Bandwidth and BD Modulation, 2 channel run, PPC3 setting with 5.5A current limiter, unless otherwise
noted.
10
5
10
5
PVDD=12V
TA=25èC
Load=1mF
LC Filter=10uH+0.68uF
PVDD=12V
TA=25èC
BTL Mode
VOUT=6VP
2
1
2
1
Load=1mF
LC Filter=10mH+0.68mF
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
Fin=1kHz
Fin=5kHz
Fin=10kHz
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
1
Output Voltage (Vrms)
D80002
D08071
LC Filter = 10µH +
0.68µF
VOUT = 6 VP
Load = 1 µF
LC Filter = 10µH + Input Frequency =
0.68µF 1kHz,5kHz,10kHz
Load = 1 µF
图 7-1. THD+N vs Frequency
图 7-2. THD+N vs Output Voltage (Per Channel)
0.4
Fin=1kHz
Fin=5kHz
Fin=10kHz
PVDD=12V
BTL Mode
2 Channel Run
Load=1mF
0.3
0.2
0.1
0
LC Filter=10mH+0.68mF
0
2
4
VOUT (Vrms)
6
8
D800387814
LC Filter = 10µH + 0.68µF
Input Frequency = 1kHz,5kHz,10kHz
Load = 1 µF
图 7-3. Supply Current vs Output Voltage (Per Channel)
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7.2 Parallel Bridge Tied Load (PBTL) Configuration
Free-air room temperature 25°C (unless otherwise noted) Measurements were made using DRV5825PEVM
board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All
measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 768 kHz with 175kHz
Loop bandwidth, BD Modulation, the LC filter used was 3.3 μH / 0.47 μF （Post-Filter PBTL), PPC3 setting
with 9A current limiter, unless otherwise noted.
10
5
10
5
PVDD=24V
TA=25èC
Load=4mF
LC Filter=3.3mH+0.47mF
PBTL Mode
PVDD=24V
TA=25èC
PBTL Mode
Load=4mF
LC Filter=3.3mH+0.47mF
VOUT=12VP
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
Fin=1kHz
Fin=5kHz
Fin=10kHz
0.005
0.005
0.002
0.001
0.002
0.001
20
100
1k
Frequency (Hz)
10k 20k
1
10
Output Voltage (Vrms)
D80032
D0807
LC Filter = 3.3µH +
0.47µF
VOUT = 12 VP
Load = 4 µF
LC Filter = 3.3µH + Input Frequency =
0.47µF 1kHz,5kHz,10kHz
Load = 4 µF
图 7-4. THD+N vs Frequency
图 7-5. THD+N vs Output Voltage
1
PVDD=24V
PBTL Mode
Load=4mF
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
LC Filter=3.3mH+0.47mF
Fin=1kHz
Fin=5kHz
Fin=10kHz
0
2
4
6
8 10
VOUT (Vrms)
12
14
16
18
D80038718
LC Filter = 3.3µH + 0.47µF
Input Frequency = 1kHz,5kHz,10kHz
Load = 4 µF
图 7-6. Supply Current vs Output Voltage
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8 Detailed Description
8.1 Overview
The DRV5825P device combines 4 main building blocks into a single cohesive device that maximizes sound
quality, flexibility, and ease of use. The 4 main building blocks are listed as follows:
• A stereo digital to PWM modulator.
• An Audio DSP subsystem.
• A flexible close-loop amplifier capable of operating in stereo or mono, at several different switching
frequencies, and with a variety of output voltages and loads.
• An I2C control port for communication with the device
The device requires only two power supplies for proper operation. A DVDD supply is required to power the low
voltage digital circuitry. Another supply, called PVDD, is required to provide power to the output stage of the
audio amplifier. Two internal LDOs convert PVDD to 5 V for GVDD and AVDD and to 1.5V for DVDD
respectively.
8.2 Functional Block Diagram
4.5-24V
3.3/1.8V
DVDD
VR_DIG
AVDD
PVDD1/2/3/4
LDO 1.5V
LDO 5V
BST_A+
Close Loop Feedback
ADR
IO
OUT_A+
PDN
I2S/TDM
OUT_A-
BST_A-
GPIO0
GPIO1
GPIO2
H Bridge
&
Gate Driver
&
Audio DSP
Subsystem
Digital to PWM
Conversion
SDA
SCL
BST_B-
OC/DC Protect
PDM
OUT_B-
Modulator
SDIN
OUT_B+
BST_B+
LRCLK
SCLK
PLL & OSC
LDO 5V
(PVDD to GVDD)
Close Loop Feedback
GVDD
PGND 1/2/3/4
AGND
DGND
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8.3 Feature Description
8.3.1 Power Supplies
For system design, DRV5825P needs a 3.3-V or 1.8-V supply in addition to the (typical) 12 V or 24 V power-
stage supply. Two internal voltage regulators provide suitable voltage levels for the gate drive circuitry and
internal circuitry. The external pins are provided only as a connection point for off-chip bypass capacitors to filter
the supply. Connecting external circuitry to these regulator outputs may result in reduced performance and
damage to the device. Additionally, all circuitry requiring a floating voltage supply, that is, the high-side gate
drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors. To provide good
electrical and acoustical characteristics, the PWM signal path for the output stage is designed as identical,
independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BST_x). The gate drive
voltages (GVDD) are derived from the PVDD voltage. Special attention should be paid to placing all decoupling
capacitors as close to their associated pins as possible. In general, inductance between the power-supply pins
and decoupling capacitors must be avoided. For a properly functioning bootstrap circuit, a small ceramic
capacitor must be connected from each bootstrap pin (BST_x) to the power-stage output pin (OUT_x). When the
power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the
gate-drive regulator output pin (GVDD) and the bootstrap pin. When the power-stage output is high, the
bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for
the high-side gate driver.
8.3.2 Device Clocking
The DRV5825P device has flexible systems for clocking. Internally, the device requires a number of clocks,
mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio
Interface.
DACCLK
LRCLK/FS
DSPCLK
OSRCLK
DSP
(Including
interpolator)
Serial Audio
Interface (Input)
Delta Sigma
Modulator
Audio In
DAC
图 8-1. Audio Flow with Respective Clocks
图 8-1 shows the basic data flow and clock Distribution.
The Serial Audio Interface typically has 3 connection pins which are listed as follows:
• SCLK (Bit Clock)
• LRCLK/FS (Left/Right Word Clock or Frame Sync)
• SDIN (Input Data)
The device has an internal PLL that is used to take SCLK and create the higher rate clocks required by the DSP
and the DAC clock.
The DRV5825P device has an audio sampling rate detection circuit that automatically senses which frequency
the sampling rate is operating. Common audio sampling frequencies of 32 kHz, 44.1kHz – 48 kHz, 88.2 kHz –
96 kHz are supported. The sampling frequency detector sets the clock for DAC and DSP automatically.
If the input LRCLK/SCLK stopped during music playing, the DRV5825P DSP switches to sleep state and waiting
for the clock recovery (Class D output switches to Hiz automatically ), once LRCLK/SCLK recovered, DRV5825P
auto recovers to the play mode. There is no need to reload the DSP code.
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8.3.3 Serial Audio Port – Clock Rates
The serial audio interface port is a 3-wire serial port with the signals LRCLK/FS , SCLK , and SDIN. SCLK is the
serial audio bit clock, used to clock the serial data present on SDIN into the serial shift register of the audio
interface. Serial data is clocked into the DRV5825P device with SCLK. The LRCLK/FS pin is the serial audio left/
right word clock or frame sync when the device is operated in TDM Mode.
表 8-1. Audio Data Formats, Bit Depths and Clock Rates
MAXIMUM LRCLK/FS FREQUENCY
FORMAT
DATA BITS
SCLK RATE (fS)
(kHz)
32 to 96
32
I2S/LJ/RJ
32, 24, 20, 16
64, 32
128
TDM
32, 24, 20, 16
44.1,48
96
128,256,512
128,256
When Clock halt, non-supported SCLK to LRCLK(FS) ratio is detected, the device reports Clock Error in
Register 113 (Register Address 0x71).
8.3.4 Clock Halt Auto-recovery
As some of host processor will Halt the I2S clock when there is no audio playing. When Clock halt, the device
puts all channels into the Hi-Z state and reports Clock Error in Register 113 (Register Address 0x71). After audio
clocks recovery, the device automatically returns to the previous state.
8.3.5 Sample Rate on the Fly Change
DRV5825P supports LRCLK(FS) rate on the fly change. For example, change LCRLK from 32kHz to 48kHz or
96kHz, Host processor needs to put the LRCLK(FS)/SCLK to Halt state at least 10ms before changing to the
new sample rate.
8.3.6 Serial Audio Port - Data Formats and Bit Depths
The device supports industry-standard audio data formats, including standard I2S, left-justified, right-justified and
TDM/DSP data. Data formats are selected via Register (Register Address 0x33h -D[5:4]). If the high width of
LRCLK/FS in TDM/DSP mode is less than 8 cycles of SCK, the register (Register Address 0x33h -D[3:2]) should
set to 01. All formats require binary two's complement, MSB-first audio data; up to 32-bit audio data is accepted.
All the data formats, word length and clock rate supported by this device are shown in 表 8-1. The data formats
are detailed in 图 8-2 through 图 8-6. The word length are selected via Register (Register Address 0x33h -
D[1:0]). The offsets of data are selected via Register (Register Address 0x33h -D[7]) and Register (Register
Address 0x34h -D[7:0]). Default setting is I2S and 24 bit word length.
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1 tS
LRCLK/FS
SCLK
Right-channel
Left-channel
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1
2
15 16
1
2
2
2
15 16
MSB
LSB
MSB
MSB
MSB
LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1
2
23 24
1
23 24
MSB
LSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1
2
31 32
1
31 32
MSB
LSB
LSB
图 8-2. Left Justified Audio Data Format
1 tS
LRCLK/FS
SCLK
Right-channel
Left-channel
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1
2
15 16
1
1
1
2
2
2
15 16
MSB LSB
MSB LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1
2
23 24
23 24
MSB
MSB
LSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1
2
31 32
31 32
MSB
MSB
LSB
LSB
I2S Data Format; L-channel = LOW, R-channel = HIGH
I2S Data Format; L-channel = LOW, R-channel = HIGH
图 8-3. I2S Audio Data Format
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1 tS
LRCLK/FS
SCLK
Right-channel
Left-channel
Audio data word = 16-bit, SCLK = 32, 64fs
DATA
1
2
15 16
1
2
15 16
MSB LSB
MSB LSB
Audio data word = 24-bit, SCLK = 64fs
DATA
1
2
23 24
1
2
23 24
MSB
MSB
LSB
LSB
Audio data word = 32-bit, SCLK = 64fs
DATA
1
2
31 32
1
2
31 32
MSB
MSB
LSB
LSB
Right-Justified Data Format; L-channel = HIGH, R-channel = LOW
Right Justified Data Format; L-channel = HIGH, R-channel = LOW
图 8-4. Right Justified Audio Data Format
1 /fS .
LRCK/FS
SCLK
…
…
…
…
…
…
Audio data word = 16-bit, Offset = 0
…
1
2
15 16
1
2
15 16
1
1
1
DATA
Data Slot 1
Data Slot 2
LSB
MSB
LSB
MSB
Audio data word = 24-bit, Offset = 0
,
-
…
…
1
2
23 24
1
2
23 24
LSB
DATA
Data Slot 1
LSB
MSB
MSB
Audio data word = 32-bit, Offset = 0
…
…
1
2
31 32
LSB
1
2
31 32
LSB
DATA
MSB
TDM Data Format with OFFSET = 0
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
图 8-5. TDM 1 Audio Data Format
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1 /fS .
OFFSET = 1
LRCK/FS
SCLK
…
…
…
…
…
Audio data word = 16-bit, Offset = 1
…
…
1
2
15 16
1
2
15 16
1
1
1
DATA
Data Slot 1
LSB
Data Slot 2
LSB
MSB
MSB
Audio data word = 24-bit, Offset = 1
…
…
1
2
23 24
1
2
23 24
LSB
DATA
Data Slot 1
Data Slot 2
LSB
MSB
MSB
Audio data word = 32-bit, Offset = 1
…
…
1
2
31 32
LSB
1
2
31 32
DATA
Data Slot 1
Data Slot 2
LSB
MSB
TDM Data Format with OFFSET = 1
In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.
图 8-6. TDM 2 Audio Data Format
8.3.7 Digital Audio Processing
DRV5825P DSP can provide advanced audio processing functions, such as SRC (sample rate convertor), Input
Mixer, 15 EQ bands, volume control, Smart Piezo Drive Algorithm, 2 Post EQs, Full band AGL, Clipper and
Output crossbar, Level meter.
Amp L
Amp R
Adaptive
Input
Input
Mixer
EQ
15 BQs
I/V Limiter
+
2 Band AGL
Post EQ
2 BQs
Output
Crossbar
SRC
Volume
AGL
Clipper
I2S L
I2S R
Level
Meter
图 8-7. DRV5825P Audio Signal Processing
Piezo speaker behaves like a capcictor with low impedance at high frequency which means high frequency
current is easier to trigger amplifier over current protection. Capacitive load also causes high Q to LC filter. Piezo
drive algorithm do adaptive current/voltage limitation based on output filter's frequency response and piezo
impedance. The current/voltage limiter only been triggered with large input level which means this algorithm
enhance the dynamic range keep the original sound quality.
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Input
Adaptive
Output
High Loop Bandwidth
LC Filter
Current/Voltage Limiter
(Current/Voltage Estimator)
Audio Amplifier
LC Filter Value Input
Q factor
Estimator
Piezo Speaker
Impedance
Model
Piezo Impedance Curve Import
图 8-8. Adaptive I/V Limiter Algorithm
8.3.8 Class D Audio Amplifier
Following the digital clipper, the interpolated audio data is next sent to the Closed Loop Class-D amplifier, whose
first stage is Digital to PWM Conversion (DPC) block. In this block, the stereo audio data is translated into two
pairs of complimentary pulse width modulated (PWM) signals which are used to drive the outputs of the speaker
amplifier. Feedback loops around the DPC ensure constant gain across supply voltages, reduce distortion, and
increase immunity to power supply injected noise and distortion. The analog gain is also applied in the Class-D
amplifier section of the device. The gain structures are discussed in detail below for both 图 8-9 and 表 8-2. The
switching rate of the amplifier is configurable by register (Register Address 0x02h -D[6:4])
8.3.8.1 Speaker Amplifier Gain Select
A combination of digital gain and analog gain is used to provide the overall gain of the speaker amplifier. As
seen in 图 8-9, the audio path of the DRV5825P consists of a digital audio input port, a digital audio path, a
digital to PWM converter (DPC), a gate driver stage, a Class D power stage, and a feedback loop which feeds
the output information back into the DPC block to correct for distortion sensed on the output pins. The total
amplifier gain is comprised of digital gain, shown in the digital audio path and the analog gain from the input of
the analog modulator to the output of the speaker amplifier power stage.
Analog Gain
Analog Gain
Digital Gain
Digital Gain
Closed Loop Class D Amplifier
Closed Loop Class D Amplifier
SPK_OUTA+
SPK_OUTA+
Full Bridge Power
Full Bridge Power
Stage
A
A
Stage
Gate
Gate
Drivers
Drivers
SPK_OUTA-
SPK_OUTA-
Serial
Serial
Audio Processing
Audio Processing
(Flexible Audio Process Flows)
(Flexible Audio Process Flows)
Serial
Serial
Audio In
Audio In
Digital to PWM
Digital to PWM
Conversion
Conversion
Audio
Audio
Port
Port
SPK_OUTB+
SPK_OUTB+
Gate
Gate
Drivers
Drivers
Full Bridge Power
Full Bridge Power
Stage
Stage
B
B
SPK_OUTB-
SPK_OUTB-
SCL
I2C Interface
I2C Interface
Control Register
Control Register
Closed Loop Class D Amplifier
Closed Loop Class D Amplifier
SDA
Copyright © 2017, Texas Instruments Incorporated
Copyright © 2017, Texas Instruments Incorporated
图 8-9. Speaker Amplifier Gain
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As shown in 图 8-9, the first gain stage for the speaker amplifier is present in the digital audio path. It consists of
the volume control and the digital boost block. The volume control is set to 0 dB by default, it does not change.
For all settings of the register 0x54, AGAIN[4:0], the digital boost block remains at 0 dB. These gain settings
ensure that the output signal is not clipping at different PVDD levels. 0dBFS output is 29.5-V peak output voltage
表 8-2. Analog Gain Setting
AMPLIFIER OUTPUT PEAK
VOLTAGE (VP/FS)
AMPLIFIER OUTPUT PEAK
VOLTAGE (dBV/FS)
AGAIN <4:0>
GAIN (dBFS)
00000 (Default Setting)
0
29.5VP/FS (Default Setting)
27.85VP/FS
29.4dBV/FS
28.9dBV/FS
28.4dBV/FS
27.9dBV/FS
00001
00010
00011
-0.5
-1.0
-1.5
26.29VP/FS
24.82VP/FS
……
……
……
……
11111
-15.5
4.95VP/FS
13.9dBV/FS
8.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
DRV5825P closed loop structure provides Loop bandwidth setting option (Setting by register 83 -Register
address 0x53h-D[6-5]) to co-work with different switching frequency (Setting by register 2 -Register address
0x02h-D[6-4] ). 表 8-3 shows recommended settings for the Loop Bandwidth and Switching Frequency selection.
Same Fsw, Better THD+N performance with higher BW.
表 8-3. Loop Bandwidth and Switching Frequency Setting
Modulation
Scheme
Fsw
BW (Loop Band Width)
Notes
Principle: Fsw (Switching Frequency) ≥ 3 × Loop
Bandwidth. Suggest to use 175kHz BW with 768kHz Fsw.
BD
768kHz
80kHz, 100kHz, 120kHz, 175kHz
8.4 Device Functional Modes
8.4.1 Software Control
The DRV5825P device is configured via an I2 C communication port.
The I2C Communication Protocol is detailed in the I2C Communication Port section. The I2C timing requirements
are described in the I2C Bus Timing – Standard and I2C Bus Timing – Fast sections.
There are two methods to program DRV5825P DSP memory.
• Loading with I2C Communication Port by host processor. This method is recommend for most of applications.
• Fast loading from external EEPROM with SPI communication Port. This method can be used in some
applications which need fast loading to save initialization time or release the Host Controller's loading.
DRV5825P supports to load the DSP memory data from external EEPROM via SPI. The GPIOs can be
configured as SI,SO and SCK for EEPROM via Register (0x60,0x61,0x62,0x63,0x64). The chip selection CS
of EEPROM is controlled by the Host Processor. See AppNote: Load TAS5825M Configurations from
EEPROM via SPI.
8.4.2 Speaker Amplifier Operating Modes
The DRV5825P device can be used with two different amplifier configurations, can be configured by Register
0x02h -D[2]:
• BTL Mode
• PBTL Mode
8.4.2.1 BTL Mode
In BTL mode, the DRV5825P amplifies two independent signals, which represent the left and right portions of a
stereo signal. The amplified left signal is presented on differential output pair shown as OUT_A+ and OUT_A-,
the amplified right signal is presented on differential output pair shown as OUT_B+ and OUT_B-.
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8.4.2.2 PBTL Mode
The PBTL mode of operation is used to describe operation in which the two outputs of the device are placed in
parallel with one another to increase the power sourcing capabilities of the device. On the output side of the
DRV5825P device, the summation of the devices can be done before the filter in a configuration called Pre-Filter
Parallel Bridge Tied Load (PBTL). However, the two outputs can be required to merge together after the inductor
portion of the output filter. Doing so does require two additional inductors, but allows smaller, less expensive
inductors to be used because the current is divided between the two inductors. The process is called Post-Filter
PBTL. On the input side of the DRV5825P device, the input signal to the PBTL amplifier is left frame of I2S or
TDM data.
8.4.3 Low EMI Modes
DRV5825P employs several modes to minimize EMI during playing audio, and they can be used based on
different applications.
8.4.3.1 Spread Spectrum
Spread spectrum is used in some inductor free or inductor less case to minimize EMI noise. The DRV5825P
supports Spread Spectrum with triangle mode.
User need configure register SS_CTRL0 (0x6B) to Enable triangle mode and enable spread spectrum, select
spread spectrum frequency and range with SS_CTRL1 (0x6C). For 768kHz FSW which configured by
DEVICE_CTRL1 (0x02), the spread spectrum frequency and range are described in 表 8-4.
表 8-4. Triangle Mode Spread Spectrum Frequency and Range Selection
SS_TRI_CTRL[3:0]
0
1
2
3
4
5
6
7
Triangle Freq
24k
48k
Spread Spectrum
Range
5%
10%
20%
25%
5%
10%
20%
25%
User Application example: Central Switching Frequency is 768kHz, Triangle Frequency is 24kHz.
Register 0x6b = 0x03 // Enable Spread Spectrum
Register 0x6c = 0x03 // SS_CTRL[3:0]=0001, Triangle Frequency = 24kHz, Spread Spectrum Range should be
10% (730kHz~806kHz)
8.4.3.2 Channel to Channel Phase Shift
This device supports channel to channel 180-degree PWM phase shift to minimize the EMI. Bit 0 of Register
0x53 can be used to disable or enable the phase shift.
8.4.3.3 Multi-Devices PWM Phase Synchronization
DRV5825P support up to 4 phases selection for the multi devices application system. For example, when a
system integrated 4 DRV5825P devices, user can select phase0/1/2/3 for each device by register
PHASE_CTRL(0x6A), which means there is a 45 degree phase shift between each device to minimize the EMI.
There are two methods for Multi-Device PWM phase synchronization. Phase Synchronization With I2S Clock In
Startup Phase or Phase Synchronization With GPIO.
8.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
1. Step 1, Halt I2S clock.
2. Step 2, Configure each device phase selection and enable the phase synchronization. For example: Register
0x6A=0x03 for device 0; Register 0x6A=0x07 for device 1; Register 0x6A=0x0B for device 2; Register
0x6A=0x0F for device 3.
3. Step 3, Configure each device into HIZ mode.
4. Step 4, Provide I2S to each device. Phase synchronization for all 4 devices will be automatically done by
internal sequence.
5. Step 5, Initialize the DSP code (This step can be skipped if only need to do the Phase Synchronization).
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6. Step 6, Device to Device PWM phase shift should be fixed with 45 degree.
8.4.3.3.2 Phase Synchronization With GPIO
1. Step 1, Connect GPIOx pin of each device to SOC's GPIO pin on PCB.
2. Step 2, Configure each device GPIOx as phase sync input usage by registers GPIO_CTRL (0X60) and
GPIO_INPUT_SEL (0x64).
3. Step 3, Select different phase for each device and enable phase synchronization by register PHASE_CTRL
(0x6A).
4. Step 4, Configure each device into PLAY mode by register DEVICE_CTRL2 (0x03) and monitor the
POWER_STATE register (0x68) until device changed to HIZ state.
5. Step 5, Give a 0 to 1 toggle on SOC GPIO. Then all 4 devices will enter into PLAY mode and device to
Device PWM phase shift should be fixed with 45 degree.
6. Step 6, Phase Synchronization has been finished. Configure the GPIOx pin to other function based on the
application.
8.4.4 Device State Control
Except Shutdown Mode, DRV5825P has other 4 states for different power dissipation which listed in the
Electrical Characteristics Table.
• Deep Sleep Mode. Register 0x03h -D[1:0]=00, Device stays in Deep Sleep Mode. In this mode, I2C block
keep works. This mode can be used to extend the battery life time in some portable speaker application case,
once the host processor stopped playing audio for a long time, DRV5825P can be set to Deep Sleep Mode to
minimize power dissipation until host processor start playing audio again. Device returns back to Play Mode
by setting Register 0x03h -D[1:0] to 11. Compare with Shutdown Mode (Pull PDN Low), enter or exit Deep
Sleep Mode, DSP keeps active.
• Sleep Mode. Register 0x03h -D[1:0]=01, Device stays in Sleep Mode. In this mode, I2C block, Digital core,
DSP Memory , 5V Analog LDO keep works. Compare with Shutdown Mode (Pull PDN Low), enter or exit
Sleep Mode, DSP keeps active.
• Output Hiz Mode. Register 0x03h -D[1:0]=10, Device stays in Hiz Mode. In this mode, Only output driver set
to be Hiz state, all other block work normally.
• Play Mode. Register 0x03h -D[1:0]=11, Device stays in Play Mode.
8.4.5 Device Modulation
DRV5825P supports piezo drive algorithm based on BD modulation.
With BD modulation, each output is switching from 0 volts to the supply voltage. The OUTPx and OUTNx are in
phase with each other with no input so that there is little or no current in the speaker. The duty cycle of OUTPx is
greater than 50% and OUTNx is less than 50% for positive output voltages. The duty cycle of OUTPx is less
than 50% and OUTNx is greater than 50% for negative output voltages. The voltage across the load sits at 0 V
throughout most of the switching period, reducing the switching current, which reduces any I2R losses in the
load.
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OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
0V
-
OUTP OUTN
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
OUTP-OUTN
-
PVCC
0A
Speaker
Current
图 8-10. BD Mode Modulation
8.5 Programming and Control
8.5.1 I2C Serial Communication Bus
The device has a bidirectional serial control interface that is compatible with I2C bus protocol and supports 100
and 400-kHz data transfer rates for random and sequential write and read operations as a slave device.
Because the DRV5825P register map and DSP memory spans multi pages, the user should change from page
to page before writing individual register or DSP memory. Changing from page to page is accomplished via
register 0 on each page. This register value selects the page address, from 0 to 255. All registers listed in
DRV5825P Datasheet belongs to Page 0
8.5.2 I2C Slave Address
The DRV5825P device has 7 bits for the slave address. The first five bits (MSBs) of the slave address are
factory preset to 10011(0x9x). The next two bits of address byte are the device select bits which can be user-
defined by ADR pin in 表 8-5.
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表 8-5. I2C Slave Address Configuration
ADR PIN Configuration
0 Ω to GND
MSBs
User Define
LSB
R/ W
R/ W
R/ W
R/ W
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1kΩ to GND
4.7kΩ to GND
15kΩ to GND
8.5.2.1 Random Write
As shown in 图 8-11, a single-byte data-write transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data
transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address and the
read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address byte
corresponding to the internal memory address being accessed. After receiving the address byte, the device
again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the
memory address being accessed. After receiving the data byte, the device again responds with an acknowledge
bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
ACK
A4
R/W
A7
ACK
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5
ACK
A6 A5
A3 A2 A1 A0
D4 D3 D2 D1 D0
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
Data Byte
图 8-11. Random Write Transfer
8.5.2.2 Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are
transmitted by the master to the device as shown in 图 8-12. After receiving each data byte, the device responds
with an acknowledge bit and the I2 subaddress is automatically incremented by one.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A5
A0
R/W ACK
A4 A3
A0
ACK
ACK
ACK
ACK
D0
A6
A1
A7
A6
A5
A1
D7
D0
D7
D0
D7
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte
Other Data Byte
Last Data Byte
图 8-12. Sequential Write Transfer
8.5.2.3 Random Read
As shown in 图 8-13, a single-byte data-read transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. For the data-read transfer, both a write followed by a
read are actually done. Initially, a write is done to transfer the address byte of the internal memory address to be
read. As a result, the read/write bit is a 0. After receiving the address and the read/write bit, the device responds
with an acknowledge bit. In addition, after sending the internal memory address byte, the master device
transmits another start condition followed by the address and the read/write bit again. This time the read/write bit
is a 1, indicating a read transfer. After receiving the address and the read/write bit, the device again responds
with an acknowledge bit. Next, the device transmits the data byte from the memory address being read. After
receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete
the single-byte data-read transfer.
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Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
D0 D6
A6 A5
A1 A0
A7 A6 A5 A4
Subaddress
A0
A6 A5
A1 A0
D7 D6
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Data Byte
图 8-13. Random Read Transfer
8.5.2.4 Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are
transmitted by the device to the master device as shown in 图 8-14. Except for the last data byte, the master
device responds with an acknowledge bit after receiving each data byte and automatically increments the I2C
sub address by one. After receiving the last data byte, the master device transmits a not-acknowledge followed
by a stop condition to complete the transfer.
Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
ACK
ACK
D0
A6
A0
A7 A6 A5
A0
A6
A0
D7
D0
D7
D0
D7
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte Other Data Byte Last Data Byte
图 8-14. Sequential Read Transfer
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8.5.2.5 DSP Memory Book, Page and BQ update
On Page 0x00 of each book, Register 0x7f is used to change the book. Register 0x00 of each page is used to
change the page. To change a Page first write 0x00 to Register 0x00 to switch to Page 0 then write the book
number to Register 0x7f on Page 0. To switch between pages in a book, simply write the page number to
register 0x00.
All the Biquad Filters coefficients are addressed in book 0xAA. The five coefficients of every Biquad Filter should
be written entirely and sequentially from the lowest address to the highest address. The address of all Biquad
Filters can be found in Register Maps: 表 8-6.
8.5.2.6 Checksum
This device supports two different check sum schemes, a cyclic redundancy check (CRC) checksum and an
Exclusive (XOR) checksum. Register reads do not change checksum, but writes to even nonexistent registers
will change the checksum. Both checksums are 8-bit checksums and both are available together simultaneously.
The checksums can be reset by writing a starting value (eg. 0x 00 00 00 00) to their respective 4-byte register
locations.
8.5.2.6.1 Cyclic Redundancy Check (CRC) Checksum
The 8-bit CRC checksum used is the 0x7 polynomial (CRC-8-CCITT I.432.1; ATM HEC, ISDN HEC and cell
delineation, (1 + x1 + x2 + x8)). A major advantage of the CRC checksum is that it is input order sensitive. The
CRC supports all I2C transactions, excluding book and page switching. The CRC checksum is read from register
0x7E on page0 of Book 0x8C (Book_140, Page_0, Reg_126). The CRC checksum can be reset by writing 0x00
to the same register locations where the CRC checksum is valid.
8.5.2.6.2 Exclusive or (XOR) Checksum
The XOR checksum is a simpler checksum scheme. It performs sequential XOR of each register byte write with
the previous 8-bit checksum register value. XOR supports only Book 0x8C, and excludes page switching and all
registers in Page 0x00 of Book 0x8C. XOR checksum is read from location register 0x7D on page 0x00 of book
0x8C (B_140, Page_0, Reg_125). The XOR Checksum can be reset by writing 0x00 to the same register
location where it is read.
PurePathTM Console tools supports CRC and XOR check sum value calculation based on register writting
scritps.
Note
List both CRC and XOR application scenarios in below example, but only one Checksum (CRC or
XOR) method is needed.
Example: Update EQ parameters.
1. Use PPC3 to calculate the EQ parametes and save to .cfg file.
w 58 00 00
w 58 7f aa
w 58 00 24
w 58 18 08 25 39 ce f0 bc db 13 07 26 4d 48 0f 43 24 ed f8 b4 78 ea #EQ parameters
2. Use PPC3 to calculate CRC and XOR Checksum results (based on .cfg file).
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3. Update EQ parameters with CRC/XOR Checksum.
w 58 00 00
w 58 7f 8c
w 58 00 00
w 58 7e 00 #Reset CRC start value to 0x00
w 58 7d 00 #Reset XOR start value to 0x00
w 58 00 00
w 58 7f aa
w 58 00 24
w 58 18 08 25 39 ce f0 bc db 13 07 26 4d 48 0f 43 24 ed f8 b4 78 ea #EQ parameters update
w 58 00 00
w 58 7f 8c
w 58 00 00
r 58 7d 01 #Check if the XOR checksum readback data is 0x21
r 58 7e 01 #Check if the CRC checksum readback data is 0x41
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8.5.3 Control via Software
• Startup Procedures
• Shutdown Procedures
8.5.3.1 Startup Procedures
1. Configure ADR pin with proper setting for I2C device address.
2. Bring up power supplies (it does not matter if PVDD or DVDD comes up first).
3. Once power supplies are stable, bring up PDN to High, then start SCLK, LRCLK.
4. Once I2S clock are stable, set the device into Hi-Z state and enable DSP via the I2C control port.
5. Wait 5ms at least. Then initialize the DSP Coefficient, then set the device to Play state
6. The device is now in normal operation.
Normal Operati
on
Initialization
DVDD
0 ns
PVDD
0 ns
PDN
I2S
I2S
I2C
I2S
I2S
I2S
I2S
I2S
I2S
I2S
I2S
Deep sleep
HiZ - DSP enable
(Book0/Page-0 Register) (Book0/Page-0 Register)
DSP ready to configure
Play
5 ms for device settle down
Notes:
1) I2S only permits to start after DVDD fully powered up. But No sequence requirement with PDN.
2) I2C only response with PDN brought up to HIGH.
3) If I2C register is general register in Book 0, no sequence requirement, write/read BEFORE or AFTER I2S clock ready. But if I2C register is DSP register
(Other BOOK/PAGE), suggest to follow the 5ms requirements and make sure I2S clock is ready (Especially for the first time initialization after power
up).
4) No sequence requirement for PVDD and DVDD.
图 8-15. Start-up Sequence
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8.5.3.2 Shutdown Procedures
1. The device is in normal operation.
2. Configure the Register 0x03h -D[1:0]=10 (Hi-Z) via the I2C control port or Pull PDN low.
3. Wait at least 6ms (this time depends on the LRCLK rate ,digital volume and digital volume ramp down rate).
4. Bring down power supplies.
5. The device is now fully shutdown and powered off.
PDN
6ms
4.5V
PVDD
0ms
DVDD
6ms
I2C
I2C
I2C
I2C
Output Hiz
ñ
ñ
Before PVDD/DVDD power down, Class D Output driver needs to be disabled by PDN or by I2C.
At least 6ms delay needed based on LRCLK (Fs) = 48kHz,Digital volume ramp down update every sample period,
decreased by 0.5dB for each update, digital volume =24dB. Change the value of register 0x4C and 0x4E or change
the LRCLK rate, the delay changes.
图 8-16. Power-Down Sequence
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8.5.3.3 Protection and Monitoring
8.5.3.3.1 Overcurrent Limit (Cycle-By-Cycle)
The CBC current-limiting circuit terminates each PWM pulse limit the output current flow to the average current
limit (ILIM) threshold. The overall effect on the audio in the case of a current overload is quite similar a voltage-
clipping event, temporarily limiting power at the peaks of the music signal and normal operation continues
without disruption on removal of the overload.
Note
CBC (Cycle-By-Cycle) current-limiting only allows in BTL mode, not allowed under PBTL.
8.5.3.3.2 Overcurrent Shutdown (OCSD)
Under severe short-circuit event, such as a short to PVDD or ground, the device uses a peak-current detector,
and the affected channel shuts down in < 100 ns if the peak current are enough. The shutdown speed depends
on a number of factors, such as the impedance of the short circuit, supply voltage, and switching frequency. The
user may restart the affected channel via I2C. An OCSD event activates the fault pin, and the I2C fault register
saves a record. If the supply or ground short is strong enough to exceed the peak current threshold but not
severe enough to trigger the OSCD, the peak current limiter prevents excess current from damaging the output
FETs, and operation returns to normal after the short is removed.
8.5.3.3.3 DC Detect
If the DRV5825P device measures a DC offset in the output voltage, the FAULTZ line is pulled low and the
OUTxx outputs transition to high impedance, signifying a fault.
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8.6 Register Maps
8.6.1 CONTROL PORT Registers
表 8-6 lists the memory-mapped registers for the CONTROL PORT. All register offset addresses not listed in 表
8-6 should be considered as reserved locations and the register contents should not be modified.
表 8-6. CONTROL PORT Registers
Offset
1h
Acronym
Register Name
Section
节 8.6.1.2
节 8.6.1.3
节 8.6.1.4
节 8.6.1.5
节 8.6.1.6
节 8.6.1.7
节 8.6.1.8
节 8.6.1.9
节 8.6.1.10
节 8.6.1.11
节 8.6.1.12
节 8.6.1.13
节 8.6.1.14
节 8.6.1.15
节 8.6.1.16
节 8.6.1.17
节 8.6.1.18
节 8.6.1.19
节 8.6.1.20
节 8.6.1.21
节 8.6.1.22
节 8.6.1.23
节 8.6.1.24
节 8.6.1.25
节 8.6.1.26
节 8.6.1.27
节 8.6.1.28
节 8.6.1.29
节 8.6.1.30
节 8.6.1.31
节 8.6.1.32
节 8.6.1.33
节 8.6.1.34
节 8.6.1.35
节 8.6.1.36
节 8.6.1.37
节 8.6.1.38
节 8.6.1.39
RESET_CTRL
Register 1
2h
DEVICE_CTRL_1
DEVICE_CTRL2
I2C_PAGE_AUTO_INC
SIG_CH_CTRL
CLOCK_DET_CTRL
SDOUT_SEL
Register 2
3h
Register 3
Fh
Register 15
Register 40
Register 41
Register 48
Register 49
Register 51
Register 52
Register 53
Register 55
Register 56
Register 57
Register 64
Register 70
Register 76
Register 78
Register 79
Register 80
Register 81
Register 83
Register 84
Register 85
Register 86
Register 87
Register 88
Register 89
Register 90
Register 91
Register 92
Register 94
Register 96
Register 97
Register 98
Register 99
Register 100
Register 101
28h
29h
30h
31h
33h
34h
35h
37h
38h
39h
40h
46h
4Ch
4Eh
4Fh
50h
51h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Eh
60h
61h
62h
63h
64h
65h
I2S_CTRL
SAP_CTRL1
SAP_CTRL2
SAP_CTRL3
FS_MON
BCK (SCLK)_MON
CLKDET_STATUS
DSP_PGM_MODE
DSP_CTRL
DIG_VOL
DIG_VOL_CTRL1
DIG_VOL_CTRL2
AUTO_MUTE_CTRL
AUTO_MUTE_TIME
ANA_CTRL
AGAIN
SPI_CLK
EEPROM_CTRL0
EEPROM_RD_CMD
EEPROM_ADDR_START0
EEPROM_ADDR_START1
EEPROM_ADDR_START2
EEPROM_BOOT_STATUS
BQ_WR_CTRL1
PVDD_ADC
GPIO_CTRL
GPIO0_SEL
GPIO1_SEL
GPIO2_SEL
GPIO_INPUT_SEL
GPIO_OUT
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表 8-6. CONTROL PORT Registers (continued)
Offset
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
Acronym
Register Name
Section
GPIO_OUT_INV
DIE_ID
Register 102
节 8.6.1.40
节 8.6.1.41
节 8.6.1.42
节 8.6.1.43
节 8.6.1.44
节 8.6.1.45
节 8.6.1.46
节 8.6.1.47
节 8.6.1.48
节 8.6.1.49
节 8.6.1.50
节 8.6.1.51
节 8.6.1.52
节 8.6.1.53
节 8.6.1.54
节 8.6.1.55
节 8.6.1.56
节 8.6.1.57
节 8.6.1.58
Register 103
Register 104
Register 105
Register 106
Register 107
Register 108
Register 109
Register 110
Register 111
Register 112
Register 113
Register 114
Register 115
Register 116
Register 117
Register 118
Register 119
Register 120
POWER_STATE
AUTOMUTE_STATE
PHASE_CTRL
SS_CTRL0
SS_CTRL1
SS_CTRL2
SS_CTRL3
SS_CTRL4
CHAN_FAULT
GLOBAL_FAULT1
GLOBAL_FAULT2
WARNING
PIN_CONTROL1
PIN_CONTROL2
MISC_CONTROL
CBC_CONTROL
FAULT_CLEAR
Complex bit access types are encoded to fit into small table cells. 表 8-7 shows the codes that are used for
access types in this section.
表 8-7. CONTROL PORT Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
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8.6.1.1 RESET_CTRL Register (Offset = 1h) [reset = 0x00]
RESET_CTRL is shown in 图 8-13 and described in 表 8-8.
Return to 表 8-6.
图 8-13. RESET_CTRL Register
7
6
5
4
RST_MOD
W
3
2
RESERVED
R
1
0
RST_REG
W
RESERVED
R/W
表 8-8. RESET_CTRL Register Field Descriptions
Bit
Field
Type
R/W
W
Reset
000
0
Description
7-5
4
RESERVED
This bit is reserved
RST_DIG_CORE
WRITE CLEAR BIT
Reset DIG_CORE
WRITE CLEAR BIT Reset Full Digital Core. This bit resets the Full
Digital Signal Path (Include DSP coefficient RAM and I2C Control
Port Registers), Since the DSP is also reset, the coeffient RAM
content will also be cleared by the DSP.
0: Normal
1: Reset Full Digital Signal Path
3-1
0
RESERVED
RST_REG
R
000
0
This bit is reserved
W
WRITE CLEAR BIT
Reset Registers
This bit resets the mode registers back to their initial values. Only
reset Control Port Registers, The RAM content is not cleared.
0: Normal
1: Reset I2C Control Port Registers
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8.6.1.2 DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]
DEVICE_CTRL_1 is shown in 图 8-14 and described in 表 8-9.
Return to 表 8-6.
图 8-14. DEVICE_CTRL_1 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
FSW_SEL
R/W
RESERVED
R/W
DAMP_PBTL
R/W
DAMP_MOD
R/W
表 8-9. DEVICE_CTRL_1 Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
RESERVED
FSW_SEL
0
This bit is reserved
6-4
000
SELECT FSW
000:384kHz
100:768kHz (Adaptive I/V Limiter co-operate with 768kHz FSW
Others:Reserved
)
3
2
RESERVED
DAMP_PBTL
R/W
R/W
0
0
This bit is reserved
0: SET DAMP TO BTL MODE
1:SET DAMP TO PBTL MODE
1-0
RESERVED
R/W
00
This bit is reserved
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8.6.1.3 DEVICE_CTRL2 Register (Offset = 3h) [reset = 00x10]
DEVICE_CTRL2 is shown in 图 8-15 and described in 表 8-10.
Return to 表 8-6.
图 8-15. DEVICE_CTRL2 Register
7
6
5
4
3
2
1
0
CTRL_STATE
R/W
RESERVED
R/W
DIS_DSP
R/W
MUTE_LEFT
R/W
RESERVED
R/W
表 8-10. DEVICE_CTRL2 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
000
1
Description
7-5
4
RESERVED
DIS_DSP
This bit is reserved
DSP reset
When the bit is made 0, DSP will start powering up and send out
data. This needs to be made 0 only after all the input clocks are
settled so that DMA channels do not go out of sync.
0: Normal operation
1: Reset the DSP
3
MUTE
R/W
0
Mute both Left and Right Channel
This bit issues soft mute request for both left and right channel. The
volume will be smoothly ramped down/up to avoid pop/click noise.
0: Normal volume
1: Mute
2
RESERVED
R/W
R/W
0
This bit is reserved
1-0
CTRL_STATE
00
device state control register
00: Deep Sleep
01: Sleep
10: Hiz,
11: PLAY
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8.6.1.4 I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]
I2C_PAGE_AUTO_INC is shown in 图 8-16 and described in 表 8-11.
Return to 表 8-6.
图 8-16. I2C_PAGE_AUTO_INC Register
7
6
5
4
3
2
1
0
RESERVED
R/W
PAGE_AUTOIN
C_REG
RESERVED
R/W
R/W
表 8-11. I2C_PAGE_AUTO_INC Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
0000
0
Description
7-4
3
RESERVED
This bit is reserved
Page auto increment disable
PAGE_AUTOINC_REG
Disable page auto increment mode. for non -zero books. When end
of page is reached it goes back to 8th address location of next page
when this bit is 0. When this bit is 1 it goes to 0 th location of current
page itself like in older part.
0: Enable Page auto increment
1: Disable Page auto increment
2-0
RESERVED
R/W
000
This bit is reserved
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8.6.1.5 SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]
SIG_CH_CTRL is shown in 图 8-17 and described in 表 8-12.
Return to 表 8-6.
图 8-17. SIG_CH_CTRL Register
7
6
5
4
3
2
1
0
SCLK_RATIO_CONFIGURE
R/W
FSMODE
R/W
RESERVED
R/W
表 8-12. SIG_CH_CTRL Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
SCLK_RATIO_CONFIGU R/W
RE
0000
These bits indicate the configured SCLK ratio, the number of SCLK
clocks in one audio frame. Device will set this ratio automatically.
4'b0011:32FS
4'b0101:64FS
4'b0111:128FS
4'b1001:256FS
4'b1011:512FS
3
FSMODE
R/W
0
FS Speed Mode These bits select the FS operation mode, which
must be set according to the current audio sampling rate. Need set it
manually If the input Fs is 44.1kHz/88.2kHz/176.4kHz.
4 'b0000 Auto detection
4 'b0100 Reserved
4 'b0110 32KHz
4 'b1000 44.1KHz
4 'b1001 48KHz
4'b1010 88.2KHz
4 'b1011 96KHz
4 'b1100 176.4KHz
4 'b1101 192KHz
Others Reserved
2-0
RESERVED
R/W
000
This bit is reserved
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8.6.1.6 CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]
CLOCK_DET_CTRL is shown in 图 8-18 and described in 表 8-13.
Return to 表 8-6.
图 8-18. CLOCK_DET_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
DIS_DET_PLL DIS_DET_SCL DIS_DET_FS DIS_DET_SCL DIS_DET_MISS RESERVED
RESERVED
K_RANGE
K
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
表 8-13. CLOCK_DET_CTRL Register Field Descriptions
Bit
7
Field
RESERVED
DIS_DET_PLL
Type
R/W
R/W
Reset
Description
0
0
This bit is reserved
Ignore PLL overate Detection
6
This bit controls whether to ignore the PLL overrate detection. The
PLL must be slow than 150MHz or an error will be reported. When
ignored, a PLL overrate error will not cause a clock error.
0: Regard PLL overrate detection
1: Ignore PLL overrate detection
5
DIS_DET_SCLK_RANGE R/W
0
Ignore BCK Range Detection
This bit controls whether to ignore the SCLK range detection. The
SCLK must be stable between 256KHz and 50MHz or an error will
be reported. When ignored, a SCLK range error will not cause a
clock error.
0: Regard BCK Range detection
1: Ignore BCK Range detection
4
3
DIS_DET_FS
R/W
R/W
0
0
Ignore FS Error Detection
This bit controls whether to ignore the FS Error detection. When
ignored, FS error will not cause a clock error.But CLKDET_STATUS
will report fs error.
0: Regard FS detection
1: Ignore FS detection
DIS_DET_SCLK
Ignore SCLK Detection
This bit controls whether to ignore the SCLK detection against
LRCK. The SCLK must be stable between 32FS and 512FS
inclusive or an error will be reported. When ignored, a SCLK error
will not cause a clock error.
0: Regard SCLK detection
1: Ignore SCLK detection
2
DIS_DET_MISS
R/W
0
Ignore SCLK Missing Detection
This bit controls whether to ignore the SCLK missing detection.
When ignored an SCLK missing will not cause a clock error.
0: Regard SCLK missing detection
1: Ignore SCLKmissing detection
1
0
RESERVED
RESERVED
R/W
R/W
0
0
This bit is reserved
This bit is reserved
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8.6.1.7 SDOUT_SEL Register (Offset = 30h) [reset = 0x00]
SDOUT_SEL is shown in 图 8-20 and described in 表 8-14.
Return to 表 8-6.
图 8-19. SDOUT_SEL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
RESERVED
R/W
SDOUT_SEL
R/W
表 8-14. SDOUT_SEL Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
0000000
0
Description
7-1
0
RESERVED
SDOUT_SEL
These bits are reserved
SDOUT Select. This bit selects what is being output as SDOUT pin.
0: SDOUT is the DSP output (post-processing)
1: SDOUT is the DSP input (pre-processing)
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8.6.1.8 I2S_CTRL Register (Offset = 31h) [reset = 0x00]
I2S_CTRL is shown in 图 8-20 and described in 表 8-15.
Return to 表 8-6.
图 8-20. I2S_CTRL Register
7
6
5
4
3
RESERVED
R
2
1
0
RESERVED
R/W
SCLK_INV
R/W
RESERVED
R/W
RESERVED
R
RESERVED
R/W
表 8-15. I2S_CTRL Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5
RESERVED
SCLK_INV
00
This bit is reserved
SCLK Polarity
0
This bit sets the inverted SCLK mode. In inverted SCLK mode, the
DAC assumes that the LRCK and DIN edges are aligned to the rising
edge of the SCLK. Normally they are assumed to be aligned to the
falling edge of theSCLK
0: Normal SCLKmode
1: Inverted SCLK mode
4
3
RESERVED
RESERVED
RESERVED
RESERVED
R/W
R
0
This bit is reserved
This bit is reserved
These bits are reserved
This bit is reserved
0
2-1
0
R
00
0
R/W
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8.6.1.9 SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]
SAP_CTRL1 is shown in 图 8-21 and described in 表 8-16.
Return to 表 8-6.
图 8-21. SAP_CTRL1 Register
7
6
5
4
3
2
1
0
I2S_SHIFT_MS
B
RESERVED
DATA_FORMAT
R/W
I2S_LRCLK_PULSE
R/W
WORD_LENGTH
R/W
R/W
R/W
表 8-16. SAP_CTRL1 Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
Reset
Description
I2S_SHIFT_MSB
RESERVED
0
I2S Shift MSB
6
0
This bit is reserved
5-4
DATA_FORMAT
00
I2S Data Format
These bits control both input and output audio interface formats for
DAC operation.
00: I2S
01: TDM/DSP
10: RTJ
11: LTJ
3-2
1-0
I2S_LRCLK_PULSE
WORD_LENGTH
R/W
R/W
00
10
01: LRCLK pulse < 8 SCLK
I2S Word Length
These bits control both input and output audio interface sample word
lengths for DAC operation.
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits
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8.6.1.10 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]
SAP_CTRL2 is shown in 图 8-22 and described in 表 8-17.
Return to 表 8-6.
图 8-22. SAP_CTRL2 Register
7
6
5
4
3
2
1
0
I2S_SHIFT
R/W
表 8-17. SAP_CTRL2 Register Field Descriptions
Bit
7-0
Field
I2S_SHIFT
Type
Reset
Description
R/W
00000000
I2S Shift LSB
These bits control the offset of audio data in the audio frame for both
input and output. The offset is defined as the number of SCLK from
the starting (MSB) of audio frame to the starting of the desired audio
sample. MSB [8] locates in 节 8.6.1.10
000000000: offset = 0 SCLK (no offset)
000000001: ofsset = 1 SCLK
000000010: offset = 2 SCLKs
and
111111111: offset = 512 SCLKs
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8.6.1.11 SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]
SAP_CTRL3 is shown in 图 8-23 and described in 表 8-18.
Return to 表 8-6.
图 8-23. SAP_CTRL3 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
LEFT_DAC_DPATH
R/W
RESERVED
R/W
RIGHT_DAC_DPATH
R/W
表 8-18. SAP_CTRL3 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5-4
RESERVED
00
These bits are reserved
LEFT_DAC_DPATH
01
Left DAC Data Path. These bits control the left channel audio data
path connection.
00: Zero data (mute)
01: Left channel data
10: Right channel data
11: Reserved (do not set)
3-2
1-0
RESERVED
R/W
R/W
00
01
These bits are reserved
RIGHT_DAC_DPATH
Right DAC Data Path. These bits control the right channel audio data
path connection.
00: Zero data (mute)
01: Right channel data
10: Left channel data
11: Reserved (do not set)
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8.6.1.12 FS_MON Register (Offset = 37h) [reset = 0x00]
FS_MON is shown in 图 8-24 and described in 表 8-19.
Return to 表 8-6.
图 8-24. FS_MON Register
7
6
5
4
3
2
1
0
RESERVED
R/W
SCLK_RATIO_HIGH
R
FS
R
表 8-19. FS_MON Register Field Descriptions
Bit
Field
Type
R/W
R
Reset
Description
7-6
5-4
3-0
RESERVED
SCLK_RATIO_HIGH
FS
00
This bit is reserved
2 msbs of detected SCLK ratio
00
R
0000
These bits indicate the currently detected audio sampling rate.
4 'b0000 FS Error
4 'b0100 16KHz
4 'b0110 32KHz
4 'b1000 Reserved
4 'b1001 48KHz
4 'b1011 96KHz
4 'b1101 192KHz
Others Reserved
8.6.1.13 BCK (SCLK)_MON Register (Offset = 38h) [reset = 0x00]
BCK_MON is shown in 图 8-25 and described in 表 8-20.
Return to 表 8-6.
图 8-25. BCK (SCLK)_MON Register
7
6
5
4
3
2
1
0
BCLK (SCLK)_RATIO_LOW
R
表 8-20. BCK_MON Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
BCLK
(SCLK)_RATIO_LOW
R
00000000
These bits indicate the currently detected BCK (SCLK) ratio, the
number of BCK (SCLK) clocks in one audio frame.
BCK (SCLK) = 32 FS~512 FS
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8.6.1.14 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]
CLKDET_STATUS is shown in 图 8-26 and described in 表 8-21.
Return to 表 8-6.
图 8-26. CLKDET_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R/W
DET_STATUS
R
表 8-21. CLKDET_STATUS Register Field Descriptions
Bit
Field
Type
R/W
R
Reset
Description
7-6
5-0
RESERVED
00
These bits are reserved
DET_STATUS
000000
bit0: In auto detection mode(reg_fsmode=0),this bit indicated
whether the audio sampling rate is valid or not. In non auto detection
mode(reg_fsmode!=0), Fs error indicates that configured fs is
different with detected fs. Even FS Error Detection Ignore is set, this
flag will be also asserted.
bit1: This bit indicates whether the SCLK is valid or not. The SCLK
ratio must be stable and in the range of 32-512FS to be valid.
bit2: This bit indicates whether the SCLK is missing or not.
bit3:This bit indicates whether the PLL is locked or not. The PLL will
be reported as unlocked when it is disabled.
bits4:This bit indicates whether the PLL is overrate
bits5:This bit indicates whether the SCLK is overrate or underrate
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8.6.1.15 DSP_PGM_MODE Register (Offset = 40h) [reset = 0x01]
DSP_PGM_MODE is shown in 图 8-27 and described in 表 8-22.
Return to 表 8-6.
图 8-27. DSP_PGM_MODE Register
7
6
5
4
3
2
1
0
RESERVED
R/W
CH_A_HIZ
R/W
CH_B_HIZ
R/W
MODE_SEL
R/W
表 8-22. DSP_PGM_MODE Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
0000
0
Description
7-4
3
RESERVED
CH_A_HIZ
These bits are reserved
1: Force Channel A (L channel) to Hiz mode.
0: Exit Force Hi-Z mode, Channel A is now controlled by Register
0x03, see 表 8-10.
Notes: If channel has been forced to Hiz, only method to exit Force
Hi-Z mode is set this bit to 0. This function is disabled in PBTL mode.
2
CH_B_HIZ
R/W
R/W
0
1: Force Channel B (R channel) to Hiz mode.
0: Exit Force Hi-Z mode, Channel B is now controlled by Register
0x03, see 表 8-10.
Notes: If channel has been forced to Hiz, only method to exit Force
Hi-Z mode is set this bit to 0. This function is disabled in PBTL mode.
1-0
MODE_SEL
01
DSP Program Selection
These bits select the DSP program to use for audio processing.
00 => ram mode
01 => rom mode 1
10 => rom mode 2
11 => rom mode 3
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8.6.1.16 DSP_CTRL Register (Offset = 46h) [reset = 0x01]
DSP_CTRL is shown in 图 8-28 and described in 表 8-23.
Return to 表 8-6.
图 8-28. DSP_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
USER_DEFINED_PROCESSING RESERVED BOOT_FROM_I USE_DEFAULT
_RATE
RAM
_COEFFS
R/W
R/W
R
R/W
R/W
表 8-23. DSP_CTRL Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
000
00
Description
7-5
4-3
R/W
This bit is reserved
USER_DEFINED_PROCE R/W
SSING_RATE
00:input
01:48k
10:96k
11:192k
2
1
0
RESERVED
RESERVED
R
R
0
0
1
This bit is reserved
This bit is reserved
USE_DEFAULT_COEFFS R/W
Use default coefficients from ZROM this bit controls whether to use
default coefficients from ZROM or use the non-default coefficients
downloaded to device by the Host
0 : don't use default coefficients from ZROM
1 : use default coefficents from ZROM
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8.6.1.17 DIG_VOL Register (Offset = 4Ch) [reset = 30h]
DIG_VOL is shown in 图 8-29 and described in 表 8-24.
Return to 表 8-6.
图 8-29. DIG_VOL Register
7
6
5
4
3
2
1
0
PGA_LEFT
R/W
表 8-24. DIG_VOL Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
PGA
R/W
00110000
Digital Volume
These bits control both left and right channel digital volume. The
digital volume is 24 dB to -103 dB in -0.5 dB step.
00000000: +24.0 dB
00000001: +23.5 dB
........
and 00101111: +0.5 dB
00110000: 0.0 dB
00110001: -0.5 dB
.......
11111110: -103 dB
11111111: Mute
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8.6.1.18 DIG_VOL_CTRL1 Register (Offset = 4Eh) [reset = 0x33]
DIG_VOL_CTRL1 is shown in 图 8-30 and described in 表 8-25.
Return to 表 8-6.
图 8-30. DIG_VOL_CTRL1 Register
7
6
5
4
3
2
1
0
PGA_RAMP_DOWN_SPEED
R/W
PGA_RAMP_DOWN_STEP
R/W
PGA_RAMP_UP_SPEED
R/W
PGA_RAMP_UP_STEP
R/W
表 8-25. DIG_VOL_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
PGA_RAMP_DOWN_SPE R/W
ED
00
Digital Volume Normal Ramp Down Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping down.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4
3-2
1-0
PGA_RAMP_DOWN_STE R/W
P
11
00
11
Digital Volume Normal Ramp Down Step
These bits control the step of the digital volume updates when the
volume is ramping down.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
PGA_RAMP_UP_SPEED R/W
Digital Volume Normal Ramp Up Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping up.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly restore the volume (Instant unmute)
PGA_RAMP_UP_STEP
R/W
Digital Volume Normal Ramp Up Step
These bits control the step of the digital volume updates when the
volume is ramping up.
00: Increment by 4 dB for each updat
e 01: Increment by 2 dB for each update
10: Increment by 1 dB for each update
11: Increment by 0.5 dB for each update
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8.6.1.19 DIG_VOL_CTRL2 Register (Offset = 4Fh) [reset = 0x30]
DIG_VOL_CTRL2 is shown in 图 8-31 and described in 表 8-26.
Return to 表 8-6.
图 8-31. DIG_VOL_CTRL2 Register
7
6
5
4
3
2
1
0
FAST_RAMP_DOWN_SPEED
R/W
FAST_RAMP_DOWN_STEP
R/W
RESERVED
R/W
表 8-26. DIG_VOL_CTRL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
FAST_RAMP_DOWN_SP R/W
EED
00
Digital Volume Emergency Ramp Down Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping down due to clock error or power outage,
which usually needs faster ramp down compared to normal soft
mute.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4
FAST_RAMP_DOWN_ST R/W
EP
11
Digital Volume Emergency Ramp Down Step
These bits control the step of the digital volume updates when the
volume is ramping down due to clock error or power outage, which
usually needs faster ramp down compared to normal soft mute.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
3-0
RESERVED
R/W
0000
This bit is reserved
8.6.1.20 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]
AUTO_MUTE_CTRL is shown in 图 8-32 and described in 表 8-27.
Return to 表 8-6.
图 8-32. AUTO_MUTE_CTRL Register
7
6
5
4
3
2
1
REG_AUTO_MUTE_CTRL
R/W
0
RESERVED
R/W
表 8-27. AUTO_MUTE_CTRL Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
00000
111
Description
7-3
2-0
R/W
This bit is reserved
REG_AUTO_MUTE_CTR R/W
L
bit0:
0: Disable left channel auto mute
1: Enable left channel auto mute
bit1:
0: Disable right channel auto mute
1: Enable right channel auto mute
bit2: 0:
Auto mute left channel and right channel independently.
1: Auto mute left and right channels only when both channels are
about to be auto muted.
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8.6.1.21 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]
AUTO_MUTE_TIME is shown in 图 8-33 and described in 表 8-28.
Return to 表 8-6.
图 8-33. AUTO_MUTE_TIME Register
7
6
5
AUTOMUTE_TIME_LEFT
R/W
4
3
2
1
0
RESERVED
R/W
RESERVED
R/W
AUTOMUTE_TIME_RIGHT
R/W
表 8-28. AUTO_MUTE_TIME Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
R/W
0
This bit is reserved
6-4
AUTOMUTE_TIME_LEFT R/W
000
Auto Mute Time for Left Channel
These bits specify the length of consecutive zero samples at left
channel before the channel can be auto muted. The times shown are
for 96 kHz sampling rate and will scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec
3
RESERVED
R/W
0
This bit is reserved
2-0
AUTOMUTE_TIME_RIGH R/W
T
000
Auto Mute Time for Right Channel
These bits specify the length of consecutive zero samples at right
channel before the channel can be auto muted. The times shown are
for 96 kHz sampling rate and will scale with other rates.
000: 11.5 ms
001: 53 ms
010: 106.5 ms
011: 266.5 ms
100: 0.535 sec
101: 1.065 sec
110: 2.665 sec
111: 5.33 sec
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8.6.1.22 ANA_CTRL Register (Offset = 53h) [reset = 0h]
ANA_CTRL is shown in 图 8-34 and described in 表 8-29
Return to 表 8-6
图 8-34. ANA_CTRL Register
7
6
5
4
3
2
1
0
AMUTE_DLY
R/W
表 8-29. ANA_CTRL Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
7
R/W
0
This bit is reserved
6-5
Class D bandwidth control R/W
00
00: 100kHz
01: 80kHz
10: 120kHz
11:175kHz
With Fsw=768kHz, 175kHz bandwidth should be selected for high
audio performance.
4-1
0
RESERVED
R/W
R/W
0000
0
These bits are reserved
L and R PWM output
phase control
0: out of phase
1: in phase
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8.6.1.23 AGAIN Register (Offset = 54h) [reset = 0x00]
AGAIN is shown in 图 8-35 and described in 表 8-30.
Return to 表 8-6.
图 8-35. AGAIN Register
7
6
5
4
3
2
1
0
RESERVED
R/W
ANA_GAIN
R/W
表 8-30. AGAIN Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-5
4-0
RESERVED
ANA_GAIN
000
This bit is reserved
00000
Analog Gain Control
This bit controls the analog gain.
00000: 0 dB (29.5V peak voltage)
00001:-0.5db 11111: -15.5 dB
8.6.1.24 SPI_CLK Register (Offset = 55h) [reset = 0x00]
SPI_CLK is shown in 图 8-36 and described in 表 8-31.
Return to 表 8-6.
图 8-36. SPI_CLK Register
7
6
5
4
3
2
1
0
RESERVED
R/W
SPI_CLK_SEL
R/W
表 8-31. SPI_CLK Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
0000
0000
Description
7-4
3-0
RESERVED
This bit is reserved
SPI_CLK_SEL
00:1.25M
01:2.5M
10:5M
11:10M
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8.6.1.25 EEPROM_CTRL0 Register (Offset = 56h) [reset = 0x00]
EEPROM_CTRL0 is shown in 图 8-37 and described in 表 8-32.
Return to 表 8-6.
图 8-37. EEPROM_CTRL0 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
EEPROM_ADD
R_24BITS_ENA
BLE
SPI_CLK_RATE
SPI_INV_POLA SPI_MST_LSB LOAD_EEPRO
R
M_START
R/W
R/W
R/W
R/W
R/W
表 8-32. EEPROM_CTRL0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R/W
00
This bit is reserved
EEPROM_ADDR_24BITS R/W
_ENABLE
0
enable 24 bits mode for EEPROM address
4-3
SPI_CLK_RATE
R/W
00
0: spi clock rate = 1.25MHz
1: spi clock rate = 2.5MHz
2: spi clock rate = 5MHz
3: spi clock rate = 10MHz
2
SPI_INV_POLAR
SPI_MST_LSB
R/W
R/W
0
0: spi serial data change at post edge SCK
1: spi serial data change at neg edge SCK
1
0
0
0
0: msb first 1: lsb first
LOAD_EEPROM_START R/W
0: dsp coefficients read from host
1: dsp coefficients read from EEPROM
8.6.1.26 EEPROM_RD_CMD Register (Offset = 57h) [reset = 0x03]
EEPROM_RD_CMD is shown in 图 8-38 and described in 表 8-33.
Return to 表 8-6.
图 8-38. EEPROM_RD_CMD Register
7
6
5
4
3
2
1
0
EEPROM_RD_CMD
R/W-00000011
表 8-33. EEPROM_RD_CMD Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
EEPROM_RD_CMD
R/W
00000011
EEPROM read command
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8.6.1.27 EEPROM_ADDR_START0 Register (Offset = 58h) [reset = 0x00]
EEPROM_ADDR_START0 is shown in 图 8-39 and described in 表 8-34.
Return to 表 8-6.
图 8-39. EEPROM_ADDR_START0 Register
7
6
5
4
3
2
1
0
EEPROM_ADDR_START_HIGH
R/W
表 8-34. EEPROM_ADDR_START0 Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
EEPROM_ADDR_START R/W
_HIGH
00000000
8 msb of EEPROM read starting address for coefficient
8.6.1.28 EEPROM_ADDR_START1 Register (Offset = 59h) [reset = 0x00]
EEPROM_ADDR_START1 is shown in 图 8-40 and described in 表 8-35.
Return to 表 8-6.
图 8-40. EEPROM_ADDR_START1 Register
7
6
5
4
3
2
1
0
EEPROM_ADDR_START_MIDDLE
R/W
表 8-35. EEPROM_ADDR_START1 Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
EEPROM_ADDR_START R/W
_MIDDLE
00000000
8 middle of EEPROM read starting address for coefficients
8.6.1.29 EEPROM_ADDR_START2 Register (Offset = 5Ah) [reset = 0h]
EEPROM_ADDR_START2 is shown in 图 8-41 and described in 表 8-36.
Return to 表 8-6.
图 8-41. EEPROM_ADDR_START2 Register
7
6
5
4
3
2
1
0
EEPROM_ADDR_START_LOW
R/W
表 8-36. EEPROM_ADDR_START2 Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
EEPROM_ADDR_START R/W
_LOW
00000000
8 lsb of EEPROM read starting address for coefficients
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8.6.1.30 EEPROM_BOOT_STATUS Register (Offset = 5Bh) [reset = 0x00]
EEPROM_BOOT_STATUS is shown in 图 8-42 and described in 表 8-37.
Return to 表 8-6.
图 8-42. EEPROM_BOOT_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R
LOAD_EEPRO LOAD_EEPRO
M_CRC_ERRO
R
M_DONE
R
R
表 8-37. EEPROM_BOOT_STATUS Register Field Descriptions
Bit
Field
Type
Reset
000000
0
Description
7-2
1
RESERVED
R
This bit is reserved
LOAD_EEPROM_CRC_E
RROR
R
0: CRC pass for EEPROM boot load
1: CRC don't passs for EEPROM boot load.
0
LOAD_EEPROM_DONE
R
0
Indicate that the EEPROM boot load has been finished.
8.6.1.31 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x000]
BQ_WR_CTRL1 is shown in 图 8-43 and described in 表 8-38.
Return to 表 8-6.
图 8-43. BQ_WR_CTRL1 Register
7
6
5
4
3
2
1
0
RESERVED
BQ_WR_FIRST
_COEF
R/W
R/W
表 8-38. BQ_WR_CTRL1 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
0000000
0
Description
7-1
0
RESERVED
This bit is reserved
BQ_WR_FIRST_COEF
Indicate the first coefficient of a BQ is starting to write.
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8.6.1.32 PVDD_ADC Register (Offset = 5Eh) [reset = 0h]
PVDD_ADC is shown in 图 8-44 and described in 表 8-39.
Return to 表 8-6.
图 8-44. PVDD_ADC Register
7
6
5
4
3
2
1
0
ADC_DATA_OUT
R
表 8-39. PVDD_ADC Register Field Descriptions
Bit
Field
Type
Reset
Description
PVDD Voltage = PVDD_ADC[7:0] / 8.428 (V)
223: 26.45V
222: 26.34V
221:26.22V
...
7-0
PVDD_ADC[7:0]
R
00000000
39: 4.63V
38: 4.51V
37: 4.39V
8.6.1.33 GPIO_CTRL Register (Offset = 60h) [reset = 0x00]
GPIO_CTRL is shown in 图 8-45 and described in 表 8-40.
Return to 表 8-6.
图 8-45. GPIO_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
GPIO2_OE
R/W
GPIO1_OE
R/W
GPIO0_OE
R/W
表 8-40. GPIO_CTRL Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
0000
0
Description
7-3
2
RESERVED
GPIO2_OE
This bit is reserved
GPIO2 Output Enable. This bit sets the direction of the GPIO2 pin
0: GPIO2 is input
1: GPIO2 is output
1
0
GPIO1_OE
GPIO0_OE
R/W
R/W
0
0
GPIO1 Output Enable This bit sets the direction of the GPIO1 pin
0: GPIO1 is input
1: GPIO1 is output
GPIO0 Output Enable This bit sets the direction of the GPIO0 pin
0: GPIO0 is input
1: GPIO0 is output
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8.6.1.34 GPIO0_SEL Register (Offset = 61h) [reset = 0x00]
GPIO0_SEL is shown in 图 8-46 and described in 表 8-41.
Return to 表 8-6.
图 8-46. GPIO0_SEL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
GPIO0_SEL
R/W
表 8-41. GPIO0_SEL Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
0000
0000
Description
7-4
3-0
RESERVED
GPIO0_SEL
This bit is reserved
0000: off (low)
0001: Reserved
0010: GPIO output value programmed by User in 节 8.6.1.39
0011: Auto mute flag (asserted when both L and R channels are auto
muted)
0100: Auto mute flag for left channel
0101: Auto mute flag for right channel
0110: Clock invalid flag (clock error or clock missing)
0111: Reserved
1000: GPIO0 as WARNZ output
1001: Serial audio interface data output (SDOUT)
1011: GPIO0 as FAULTZ output
1100: GPIO0 as SPI CLK
1101: GPIO0 as SPI_MOSI
1110: Reserved
1111: Reserved
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8.6.1.35 GPIO1_SEL Register (Offset = 62h) [reset = 0x00]
GPIO1_SEL is shown in 图 8-47 and described in 表 8-42.
Return to 表 8-6.
图 8-47. GPIO1_SEL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
GPIO1_SEL
R/W
表 8-42. GPIO1_SEL Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
0000
0000
Description
7-4
3-0
RESERVED
GPIO1_SEL
This bit is reserved
0000: off (low)
0001: Reserved
0010: GPIO output value programmed by User in 节 8.6.1.39
0011: Auto mute flag (asserted when both L and R channels are auto
muted)
0100: Auto mute flag for left channel
0101: Auto mute flag for right channel
0110: Clock invalid flag (clock error or clock missing)
0111: Reserved
1000: GPIO1 as WARNZ output
1001: Serial audio interface data output (SDOUT)
1011: GPIO1 as FAULTZ output
1100: GPIO1 as SPI CLK
1101: GPIO1 as SPI_MOSI
1110: Reserved
1111: Reserved
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8.6.1.36 GPIO2_SEL Register (Offset = 63h) [reset = 0x00]
GPIO2_SEL is shown in 图 8-48 and described in 表 8-43.
Return to 表 8-6.
图 8-48. GPIO2_SEL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
GPIO2_SEL
R/W
表 8-43. GPIO2_SEL Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
0000
0000
Description
7-4
3-0
RESERVED
GPIO2_SEL
This bit is reserved
0000: off (low)
0001: Reserved
0010: GPIO output value programmed by User in 节 8.6.1.39
0011: Auto mute flag (asserted when both L and R channels are auto
muted)
0100: Auto mute flag for left channel
0101: Auto mute flag for right channel
0110: Clock invalid flag (clock error or clock missing)
0111: Reserved
1000: GPIO2 as WARNZ output
1001: Serial audio interface data output (SDOUT)
1011: GPIO2 as FAULTZ output
1100: GPIO2 as SPI CLK
1101: GPIO2 as SPI_MOSI
1110: Reserved
1111: Reserved
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8.6.1.37 GPIO_INPUT_SEL Register (Offset = 64h) [reset = 0x00]
GPIO_INPUT_SEL is shown in 图 8-49 and described in 表 8-44.
Return to 表 8-6.
图 8-49. GPIO_INPUT_SEL Register
7
6
5
4
3
2
1
0
GPIO_SPI_MISO_SEL
R/W
GPIO_PHASE_SYNC_SEL
R/W
GPIO_RESETZ_SEL
R/W
GPIO_MUTEZ_SEL
R/W
表 8-44. GPIO_INPUT_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
GPIO_SPI_MISO_SEL
R/W
00
00: N/A
01: GPIO0
10: GPIO1
11: GPIO2
5-4
3-2
1-0
GPIO_PHASE_SYNC_SE R/W
L
00
00
00
00: N/A
01: GPIO0
10: GPIO1
11: GPIO2
GPIO_RESETZ_SEL
GPIO_MUTEZ_SEL
R/W
R/W
00: N/A
01: GPIO0
10: GPIO1
11: GPIO2 can not be reset by GPIO reset
00: N/A
01: GPIO0
10: GPIO1
11: GPIO2
MUTEZ pin active-low, output driver will set to HiZ state, Class D
amplifier's output stop switching.
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8.6.1.38 GPIO_OUT Register (Offset = 65h) [reset = 0x00]
GPIO_OUT is shown in 图 8-50 and described in 表 8-45.
Return to 表 8-6.
图 8-50. GPIO_OUT Register
7
6
5
4
3
2
1
0
RESERVED
R/W
GPIO_OUT
R/W
表 8-45. GPIO_OUT Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
00000
000
Description
7-3
2-0
RESERVED
GPIO_OUT
This bit is reserved
bit0: GPIO0 output
bit1: GPIO1 output
bit2: GPIO2 output
8.6.1.39 GPIO_OUT_INV Register (Offset = 66h) [reset = 0x00]
GPIO_OUT_INV is shown in 图 8-51 and described in 表 8-46.
Return to 表 8-6.
图 8-51. GPIO_OUT_INV Register
7
6
5
4
3
2
1
0
RESERVED
R/W
GPIO_OUT
R/W
表 8-46. GPIO_OUT_INV Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
00000
000
Description
7-3
2-0
RESERVED
GPIO_OUT
This bit is reserved
bit0: GPIO0 output invert
bit1: GPIO1 output invert
bit2: GPIO2 output invert
8.6.1.40 DIE_ID Register (Offset = 67h) [reset = 95h]
DIE_ID is shown in 图 8-52 and described in 表 8-47.
Return to 表 8-6.
图 8-52. DIE_ID Register
7
6
5
4
3
2
1
0
DIE_ID
R
表 8-47. DIE_ID Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
DIE_ID
R
10010101
DIE ID
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8.6.1.41 POWER_STATE Register (Offset = 68h) [reset = 0x00]
POWER_STATE is shown in 图 8-53 and described in 表 8-48.
Return to 表 8-6.
图 8-53. POWER_STATE Register
7
6
5
4
3
2
1
0
STATE_RPT
R
表 8-48. POWER_STATE Register Field Descriptions
Bit
7-0
Field
STATE_RPT
Type
Reset
Description
R
00000000
0: Deep sleep
1: Seep
2: HIZ
3: Play
Others: reserved
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8.6.1.42 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]
AUTOMUTE_STATE is shown in 图 8-54 and described in 表 8-49.
Return to 表 8-6.
图 8-54. AUTOMUTE_STATE Register
7
6
5
4
3
2
1
0
RESERVED
R
ZERO_RIGHT_ ZERO_LEFT_M
MON
ON
R
R
表 8-49. AUTOMUTE_STATE Register Field Descriptions
Bit
Field
Type
Reset
000000
0
Description
7-2
1
RESERVED
R
This bit is reserved
ZERO_RIGHT_MON
R
This bit indicates the auto mute status for right channel.
0: Not auto muted
1: Auto muted
0
ZERO_LEFT_MON
R
0
This bit indicates the auto mute status for left channel.
0: Not auto muted
1: Auto muted
8.6.1.43 PHASE_CTRL Register (Offset = 6Ah) [reset = 0]
PHASE_CTRL is shown in 图 8-55 and described in 表 8-50.
Return to 表 8-6.
图 8-55. PHASE_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
R/W
RAMP_PHASE_SEL
R/W
PHASE_SYNC PHASE_SYNC
_SEL
_EN
R/W
R/W
表 8-50. PHASE_CTRL Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
0000
00
Description
7-4
3-2
RESERVED
This bit is reserved
RAMP_PHASE_SEL
select ramp clock phase when multi devices integrated in one
system to reduce EMI and peak supply peak current, it is
recomended set all devices the same RAMP frequency and same
spread spectrum. it must be set before driving device into PLAY
mode if this feature is needed.
2'b00: phase 0
2'b01: phase 1
2'b10: phase 2
2'b11: phase 3 all of above have a 45 degree of phase shift
1
0
PHASE_SYNC_SEL
PHASE_SYNC_EN
R/W
R/W
0
0
ramp phase sync sel,
0: is gpio sync;
1: intenal sync
ramp phase sync enable
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8.6.1.44 RAMP_SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]
RAMP_SS_CTRL0 is shown in 图 8-56 and described in 表 8-51.
Return to 表 8-6.
图 8-56. SS_CTRL0 Register
7
6
5
4
3
2
1
0
RESERVED
RESERVED
SS_PRE_DIV_ SS_MANUAL_
RESERVED
R/W
SS_RDM_EN
SS_TRI_EN
SEL
MODE
R/W
R/W
R/W
R/W
R/W
R/W
表 8-51. RAMP_SS_CTRL0 Register Field Descriptions
Bit
7
Field
RESERVED
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
0
This bit is reserved
This bit is reserved
6
RESERVED
0
5
SS_PRE_DIV_SEL
SS_MANUAL_MODE
RESERVED
0
Select pll clock divide 2 as source clock in manual mode
Set ramp ss controller to manual mode
This bit is reserved
4
0
3-2
1
00
0
SS_RDM_EN
Random SS enable
0
SS_TRI_EN
0
Triangle SS enable
8.6.1.45 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]
SS_CTRL1 is shown in 图 8-57 and described in 表 8-52.
Return to 表 8-6.
图 8-57. SS_CTRL1 Register
7
6
5
4
3
2
1
0
RESERVED
R/W
SS_RDM_CTRL
R/W
SS_TRI_CTRL
R/W
表 8-52. SS_CTRL1 Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
Reset
Description
RESERVED
0
This bit is reserved
Add Dither
6-4
3-0
SS_RDM_CTRL
SS_TRI_CTRL
000
0000
Triangle SS frequency and range control
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8.6.1.46 SS_CTRL2 Register (Offset = 6Dh) [reset = 0xA0]
SS_CTRL2 is shown in 图 8-58 and described in 表 8-53.
Return to 表 8-6.
图 8-58. SS_CTRL2 Register
7
6
5
4
3
2
1
0
TM_FREQ_CTRL
R/W
表 8-53. SS_CTRL2 Register Field Descriptions
Bit
7-0
Field
TM_FREQ_CTRL
Type
Reset
Description
R/W
10100000
Control ramp frequency in manual mode, F=61440000/N
8.6.1.47 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]
SS_CTRL3 is shown in 图 8-59 and described in 表 8-54.
Return to 表 8-6.
图 8-59. SS_CTRL3 Register
7
6
5
4
3
2
1
0
TM_DSTEP_CTRL
R/W
TM_USTEP_CTRL
R/W
表 8-54. SS_CTRL3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
SS_TM_DSTEP_CTRL
R/W
0001
Control triangle mode spread spectrum fall step in ramp ss manual
mode
3-0
SS_TM_USTEP_CTRL
R/W
0001
Control triangle mode spread spectrum rise step in ramp ss manual
mode
8.6.1.48 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]
SS_CTRL4 is shown in 图 8-60 and described in 表 8-55.
Return to 表 8-6.
图 8-60. SS_CTRL4 Register
7
6
5
4
3
2
SS_TM_PERIOD_BOUNDRY
R/W
1
0
RESERVED
R/W
TM_AMP_CTRL
R/W
表 8-55. SS_CTRL4 Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
RESERVED
0
This bit is reserved
6-5
4-0
TM_AMP_CTRL
01
Control ramp amp ctrl in ramp ss manual model
SS_TM_PERIOD_BOUND R/W
RY
00100
Control triangle mode spread spectrum boundary in ramp ss manual
mode
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8.6.1.49 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]
CHAN_FAULT is shown in 图 8-61 and described in 表 8-56.
Return to 表 8-6.
图 8-61. CHAN_FAULT Register
7
6
5
4
3
CH1_DC_1
R
2
CH2_DC_1
R
1
0
RESERVED
R
CH1_OC_I
R
CH2_OC_I
R
表 8-56. CHAN_FAULT Register Field Descriptions
Bit
Field
Type
Reset
0000
0
Description
7-4
3
RESERVED
CH1_DC_1
R
This bit is reserved
R
Left channel DC fault. Once there is a DC fault, this bit will set to be
1. Class D output will set to Hi-Z. Report by FAULT pin (GPIO). Clear
this fault by setting bit 7 of 节 8.6.1.58 to 1 or this bit keeps 1.
2
1
CH2_DC_1
CH1_OC_I
R
R
0
0
Right channel DC fault. Once there is a DC fault, this bit will set to be
1. Class D output will set to Hi-Z. Report by FAULT pin (GPIO). Clear
this fault by setting bit 7 of 节 8.6.1.58 to 1 or this bit keeps 1.
Left channel over current fault. Once there is a OC fault, this bit will
set to be 1. Class D output will set to Hi-Z. Report by FAULT pin
(GPIO). Clear this fault by setting bit 7 of 节 8.6.1.58 to 1 or this bit
keeps 1.
0
CH2_OC_I
R
0
Right channel over current fault. Once there is a OC fault, this bit will
set to be 1. Class D output will set to Hi-Z. Report by FAULT pin
(GPIO). Clear this fault by setting bit 7 of 节 8.6.1.58 to 1 or this bit
keeps 1.
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8.6.1.50 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]
GLOBAL_FAULT1 is shown in 图 8-62 and described in 表 8-57.
Return to 表 8-6.
图 8-62. GLOBAL_FAULT1 Register
7
6
5
4
3
2
1
0
OTP_CRC_ER BQ_WR_ERRO LOAD_EEPRO
RESERVED
RESERVED
CLK_FAULT_I
R
PVDD_OV_I
PVDD_UV_I
ROR
R
M_ERROR
R
R
R
R
R
R
R
表 8-57. GLOBAL_FAULT1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
5
OTP_CRC_ERROR
BQ_WR_ERROR
R
0
0
0
Indicate OTP CRC check error.
The recent BQ is written failed
R
LOAD_EEPROM_ERROR R
0: EEPROM boot load was done successfully
1: EEPROM boot load was done unsuccessfully
4
3
2
RESERVED
RESERVED
CLK_FAULT_I
R
R
R
0
0
0
This bit is reserved
This bit is reserved
Clock fault. Once there is a Clock fault, this bit will set to be 1. Class
D output will set to Hi-Z. Report by FAULT pin (GPIO). Clock fault
works with an auto-recovery mode, once the clock error removes,
device automatically returns to the previous state.
Clear this fault by setting bit 7 of 节 8.6.1.58 to 1 or this bit keeps 1.
1
0
PVDD_OV_I
PVDD_UV_I
R
R
0
0
PVDD OV fault. Once there is a OV fault, this bit will set to be 1.
Class D output will set to Hi-Z. Report by FAULT pin (GPIO). OV fault
works with an auto-recovery mode, once the OV error removes,
device automatically returns to the previous state.
Clear this fault by setting bit 7 of 节 8.6.1.58 to 1 or this bit keeps 1.
PVDD UV fault. Once there is a UV fault, this bit will set to be 1.
Class D output will set to Hi-Z. Report by FAULT pin (GPIO). OV fault
works with an auto-recovery mode, once the OV error removes,
device automatically returns to the previous state.
Clear this fault by setting bit 7 of 节 8.6.1.58 to 1 or this bit keeps 1.
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8.6.1.51 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]
GLOBAL_FAULT2 is shown in 图 8-63 and described in 表 8-58.
Return to 表 8-6.
图 8-63. GLOBAL_FAULT2 Register
7
6
5
4
3
2
1
0
RESERVED
R
CBC_FAULT_C CBC_FAULT_C
OTSD_I
H2_I
H1_I
R
R
R
表 8-58. GLOBAL_FAULT2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
2
RESERVED
R
0000
This bit is reserved
CBC_FAULT_CH2_I
CBC_FAULT_CH1_I
OTSD_I
R
0
0
0
Right channel cycle by cycle over current fault
Left channel cycle by cycle over current fault
Over temperature shut down fault.
1
R
0
R
Once there is a OT fault, this bit will set to be 1. Class D output will
set to Hi-Z. Report by FAULT pin (GPIO). OV fault works with an
auto-recovery mode, once the OV error removes, device
automatically returns to the previous state.
Clear this fault by setting bit 7 of 节 8.6.1.58 to 1 or this bit keeps 1.
8.6.1.52 WARNING Register (Offset = 73h) [reset = 0x00]
WARNING is shown in 图 8-64 and described in 表 8-59.
Return to 表 8-6.
图 8-64. WARNING Register
7
6
5
4
3
2
1
0
RESERVED
R
CBCW_CH1_I CBCW_CH2_I OTW_LEVEL4_ OTW_LEVEL3_ OTW_LEVEL2_ OTW_LEVEL1_
I
I
I
I
R
R
R
R
R
R
表 8-59. WARNING Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0
0
0
0
0
0
0
This bit is reserved
CBCW_CH1_I
CBCW_CH2_I
OTW_LEVEL4_I
OTW_LEVEL3_I
OTW_LEVEL2_I
OTW_LEVEL1_I
R
Left channel cycle by cycle over current warning
Right channel cycle by cycle over current warning
Over temperature warning leve4, 146C
Over temperature warning leve3, 134C
Over temperature warning leve2, 122C
Over temperature warning leve1, 112C
4
R
3
R
2
R
1
R
0
R
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8.6.1.53 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]
PIN_CONTROL1 is shown in 图 8-65 and described in 表 8-60.
Return to 表 8-6.
图 8-65. PIN_CONTROL1 Register
7
6
5
4
3
2
1
0
MASK_OTSD MASK_DVDD_ MASK_DVDD_ MASK_CLK_FA RESERVED
MASK_PVDD_
UV
MASK_DC
MASK_OC
UV
OV
ULT
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
表 8-60. PIN_CONTROL1 Register Field Descriptions
Bit
Field
Type
R/W
R/W
R/W
R/W
R
Reset
Description
7
6
5
4
3
2
1
0
MASK_OTSD
0
0
0
0
0
0
0
0
Mask OTSD fault report
Mask DVDD UV fault report
Mask DVDD OV fault report
Mask clock fault report
This bit is reserved
MASK_DVDD_UV
MASK_DVDD_OV
MASK_CLK_FAULT
RESERVED
MASK_PVDD_UV
MASK_DC
R/W
R/W
R/W
Mask PVDD UV fault report mask PVDD OV fault report
Mask DC fault report
MASK_OC
Mask OC fault report
8.6.1.54 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]
PIN_CONTROL2 is shown in 图 8-66 and described in 表 8-61.
Return to 表 8-6.
图 8-66. PIN_CONTROL2 Register
7
6
5
4
3
2
1
0
CBC_FAULT_L CBC_WARN_L CLKFLT_LATC OTSD_LATCH_ OTW_LATCH_
MASK_OTW
MASK_CBCW MASK_CBC_F
AULT
ATCH_EN
ATCH_EN
H_EN
EN
EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
表 8-61. PIN_CONTROL2 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
CBC_FAULT_LATCH_EN R/W
CBC_WARN_LATCH_EN R/W
1
1
1
1
1
0
0
0
Enable CBC fault latch by setting this bit to 1
Enable CBC warning latch by setting this bit to 1
Enable clock fault latch by setting this bit to 1
Enable OTSD fault latch by setting this bit to 1
Enable OT warning latch by setting this bit to 1
Mask OT warning report by setting this bit to 1
Mask CBC warning report by setting this bit to 1
Mask CBC fault report by setting this bit to 1
6
5
CLKFLT_LATCH_EN
OTSD_LATCH_EN
OTW_LATCH_EN
MASK_OTW
R/W
R/W
R/W
R/W
R/W
R/W
4
3
2
1
MASK_CBCW
0
MASK_CBC_FAULT
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8.6.1.55 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]
MISC_CONTROL is shown in 图 8-67 and described in 表 8-62.
Return to 表 8-6.
图 8-67. MISC_CONTROL Register
7
6
5
4
3
2
1
0
DET_STATUS_
LATCH
RESERVED
R/W
OTSD_AUTO_
REC_EN
RESERVED
R/W
R/W
R/W
表 8-62. MISC_CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DET_STATUS_LATCH
R/W
0
1:Latch clock detection status
0:Don't latch clock detection status
6-5
4
RESERVED
R/W
R/W
R/W
00
These bits are reserved
OTSD auto recovery enable
This bit is reserved
OTSD_AUTO_REC_EN
RESERVED
0
3-0
0000
8.6.1.56 CBC_CONTROL Register (Offset = 77h) [reset = 0x00]
CBC_CONTROL is shown in 图 8-68 and described in 表 8-63.
Return to 表 8-6.
图 8-68. CBC_CONTROL Register
7
6
5
4
3
2
1
0
RESERVED
CBC_EN
CBC_WARN_E CBC_FAULT_E
N
N
R/W
R/W
R/W
R/W
表 8-63. CBC_CONTROL Register Field Descriptions
Bit
Field
Type
R/W
R/W
R/W
R/W
Reset
Description
7-3
2
RESERVED
00000
These bits are reserved
Enable CBC function
Enable CBC warning
Enable CBC fault
CBC_EN
0
0
0
1
CBC_WARN_EN
CBC_FAULT_EN
0
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8.6.1.57 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]
FAULT_CLEAR is shown in 图 8-69 and described in 表 8-64.
Return to 表 8-6.
图 8-69. FAULT_CLEAR Register
7
6
5
4
3
2
1
0
ANALOG_FAUL
T_CLEAR
RESERVED
R/W
W
表 8-64. FAULT_CLEAR Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ANALOG_FAULT_CLEAR
RESERVED
W
0
WRITE CLEAR BIT once write this bit to 1, device will clear analog
fault
6-0
R/W
0000000
This bit is reserved
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
This section details the information required to configure the device for several popular configurations and
provides guidance on integrating the DRV5825P device into the larger system.
9.1.1 LC Filter Design For Piezo Speaker Driving
Compared with traditional coil speaker whose output SPL is regarded to be proportional to output power, piezo
vendor suggests to use voltage on piezo to indicate output SPL. So piezo speaker drive circuit and algorithm
design try to deliver high dynamic range for output voltage and avoid amplifier's over current protection based on
the impedance of external circuit. It requires the algorithm understand the external circuit modeling.
9.1.1.1 LC Filter Recommendation
LC filter selection recommendation principles show as below::
1. Make sure fResonance > 25 kHz for over current avoidance and peaking voltage protection. The Max
inductance of Inductor is limited by the fResonance > 25 kHz. fResonance = 1/(2×π×(L×(C+2×Cpiezo))^0.5)
2. Larger inductor means larger DCR (better stability) and smaller startup/ripple current.
3. Larger inductor, smaller fResonance, more loop gain margin, better stability.
4. Some corner consideration:
• Inductor variation and DCR variation. Suggest to keep within +/-10% make sure fResonance > 25 kHz.
• Make sure DCR of inductor larger than 25 mΩ.
• Piezo speaker capacitance variation. Also make sure fResonance > 25 kHz.
表 9-1. LC Filter recommendation
Piezo Speaker
Capacitance
Fsw (Switching
Frequency)
Class D Loop
Bandwidth (kHz)
LC Filter Recommendation
Resonance Frequency
43.4 kHz
36.9 kHz
32 kHz
8.2 µH (DCR ≥ 25 mΩ) +0.47 µF
10 µH (DCR ≥ 25 mΩ) + 0.68 µF
15 µH (DCR ≥ 25 mΩ) + 0.47 µF
22 µH (DCR ≥ 25 mΩ) + 0.4 7µF
8.2 µH (DCR ≥ 25 mΩ) +0.47 µF
10 µH (DCR ≥ 25 mΩ) + 0.68 µF
15 µH (DCR ≥ 25 mΩ) + 0.47 µF
4.7 µH (DCR ≥ 25 mΩ) +0.47 µF
8.2 µH (DCR ≥ 25 mΩ) +0.47 µF
3.3 µH (DCR ≥ 25 mΩ) +0.47 µF
0.6 µF
1 µF
26.4 kHz
35.1 kHz
30.5 kHz
26 kHz
768kHz
175kHz
34.7 kHz
26.3 kHz
28 kHz
2 µF
4.5 µF
9.1.2 Bootstrap Capacitors
The output stage of the DRV5825P uses a high-side NMOS driver, rather than a PMOS driver. To generate the
gate driver voltage for the high-side NMOS, a bootstrap capacitor for each output terminal acts as a floating
power supply for the switching cycle. Use 0.47-µF capacitors to connect the appropriate output pin (OUT_X) to
the bootstrap pin (BST_X). For example, connect a 0.47-µF capacitor between OUT_A and BST_A for
bootstrapping the A channel. Similarly, connect another 0.47-µF capacitor between the OUT_B and BST_B pins
for the B channel inverting output.
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9.1.3 Power Supply Decoupling
To ensure high efficiency, low THD, and high PSRR, proper power supply decoupling is necessary. Noise
transients on the power supply lines are short duration voltage spikes. These spikes can contain frequency
components that extend into the hundreds of megahertz. The power supply input must be decoupled with some
good quality, low ESL, Low ESR capacitors larger than 22 µF. These capacitors bypasses low frequency noise to
the ground plane. For high frequency decoupling, place 1-µF or 0.1-µF capacitors as close as possible to the
PVDD pins of the device.
An idea power supply can deliver infinite amounts of current without a reduction in its output voltage.In reality, a
power supply maximum current output depends on its series impedance.In practical audio aapplications,where
the decoupling techniques are limited by cost and size,audio frequencies are mostly driven by the supply itself
and not by decoupling/bulk capacitors.The time constant associated with audio frequencies (especially the mid
and high areas) would require a large amount of capacitance which may be deemed impracitcal for most
application. Play high audio frequency with a piezo speaker with high current, the supply voltage drop with larger
bulk capacitors should much smaller than smaller bulk capacitors.
9.1.4 Output EMI Filtering
The DRV5825P device is often used with a low-pass filter, which is used to filter out the carrier frequency of the
PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive
element L and a capacitive element C to make up the 2-pole filter.
The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current
waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several
system level constraints. In some low-power use cases that have no other circuits which are sensitive to EMI, a
simple ferrite bead or a ferrite bead plus a capacitor can replace the tradition large inductor and capacitor that
are commonly used. In other high-power applications, large toroid inductors are required for maximum power
and film capacitors can be used due to audio characteristics. Refer to the application report Class-D LC Filter
Design (SLOA119) for a detailed description on the proper component selection and design of an L-C filter
based upon the desired load and response.
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9.2 Typical Applications
9.2.1 2.0 (Stereo BTL) System
In the 2.0 system, two channels are presented to the amplifier via the digital input signal. These two channels
are amplified and then sent to two separate speakers. In some cases, the amplified signal is further separated
based upon frequency by a passive crossover network after the L-C filter. Even so, the application is considered
2.0.
Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the
audio for the left channel and the other channel containing the audio for the right channel. While certainly the two
channels can contain any two audio channels, such as two surround channels of a multi-channel speaker
system, the most popular occurrence in two channels systems is a stereo pair.
图 9-1 shows the 2.0 (Stereo BTL) system application.
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9.2.2 Design Requirements
• Power supplies:
– 3.3-V supply
– 5-V to 24-V supply
• Communication: host processor serving as I2C compliant master
• External memory (such as EEPROM and FLASH) used for coefficients.
The requirements for the supporting components for the DRV5825P device in a Stereo 2.0 (BTL) system is
provide in 表 9-2.
表 9-2. Supporting Component Requirements for Stereo 2.0 (BTL) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
C1, C16
0.1 µF
22 µF
0402
0805
10x10
0603
0603
0603
0603
0805
CAP, CERM, 0.1 µF, 50 V, ±10%, X7R, 0402
CAP, CERM, 22 µF, 35 V, ±20%, JB, 0805
CAP, AL, 390 µF, 35 V, +/- 20%, 0.08 Ω, SMD
CAP, CERM, 4.7 µF, 10 V, ±10%, X5R, 0603
CAP, CERM, 0.1 µF, 16 V, ±10%, X7R, 0603
CAP, CERM, 1 µF, 16 V, ±10%, X5R, 0603
CAP, CERM, 0.47 µF, 16 V, ±10%, X7R, 0603
CAP, CERM, 0.68 µF, 50 V, ±10%, X7R, 0805
C2, C17
C37, C38
390µF
4.7 µF
0.1 µF
1 µF
C3
C4
C5, C14, C15
C6, C9, C10, C13
C41, C42, C43, C44
0.47 µF
0.68 µF
Inductor, Shielded, Ferrite, 10 µH, 4.4 A, 0.0304 Ω,
L1, L2, L3, L4
10 µH
SMD 1274AS-H-100M=P3
R1
0402
0402
RES, 0, 5%, 0.063 W, 0402
0 Ω
R20, R21, R22, R23
RES, 10.0 k, 1%, 0.063 W, 0402
10 kΩ
9.2.3 Detailed Design procedures
This Design procedures can be used for both Stereo 2.0 and Mono Mode.
9.2.3.1 Step One: Hardware Integration
• Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
• Following the recommended component placement, board layout, and routing given in the example layout
above, integrate the device and its supporting components into the system PCB file.
– The most critical sections of the circuit are the power supply inputs, the amplifier output signals, and the
high-frequency signals, all of which go to the serial audio port. Constructing these signals to ensure they
are given precedent as design trade-offs are made is recommended.
– For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is
necessary, go to the E2E forum to request a layout review.
9.2.3.2 Step Two: Hardware Integration
Using the DRV5825PEVM evaluation module and the development software to configure the desired device
settings.
9.2.3.3 Step Three: Software Integration
• Using the End System Integration feature of the PPC3 app to generate a baseline configuration file.
• Generate additional configuration files based upon operating modes of the end-equipment and integrate
static configuration information into initialization files.
• Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the
main system program.
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9.2.4 MONO (PBTL) Systems
In MONO mode, DRV5825P can be used as PBTL mode to drive sub-woofer with more output power.
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图 9-2. MONO (PBTL) Application Schematic
表 9-3. Supporting Component Requirements for Sub-woofer (PBTL) Systems
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
C37,C38
C1, C16
390uF
0.1 µF
22 µF
10mmx10mm
0402
CAP, AL, 390 μF, 35 V, +/- 20%, 0.08 ohm, SMD
CAP, CERM, 0.1 F, 50 V, ±10%, X7R, 0402
CAP, CERM, 22 µF, 35 V, ±20%, JB, 0805
CAP, CERM, 4.7 µF, 10 V, ±10%, X5R, 0603
CAP, CERM, 0.1 µF, 16 V, ±10%, X7R, 0603
CAP, CERM, 1 µF, 16 V, ±10%, X5R, 0603
CAP, CERM, 0.47 µF, 16 V, ±10%, X7R, 0603
CAP, CERM, 0.47 µF, 50 V, ±10%, X7R, 0805
Inductor, Shielded, 3.3 μH, 8.7 A
C2, C17
0805
C3
4.7 µF
0.1 µF
1 µF
0603
C4
0603
C5,C14,C15
C6,C9,C10,C13
C41,C42,C43,C44
L1,L2,L3,L4
R1
0603
0.47 µF
0.47 µF
3.3 µH
0603
0805
0402
RES, 0, 5%, 0.063 W, 0402
0 kΩ
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表 9-3. Supporting Component Requirements for Sub-woofer (PBTL) Systems (continued)
REFERENCE
DESIGNATOR
VALUE
SIZE
DETAILED DESCRIPTION
RES, 10.0 k, 1%, 0.063 W, 0402
R20,R21,R22,R23
0402
10 kΩ
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10 Power Supply Recommendations
The DRV5825P device requires two power supplies for proper operation. A high-voltage supply calls PVDD is
required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one low-
voltage power supply which is calls DVDD is required to power the various low-power portions of the device. The
allowable voltage range for both PVDD and DVDD supply are listed in the Recommended Operating Conditions
table. The two power supplies do not have a required powerup sequence. The power supplies can be powered
on in any order.
Internal Digital
Circuitry
Digital IO
DVDD
VR_DIG
1.5V
1.8V/3.3V'
LDO
External Filtering/Decoupling
DVDD
Output Stage
Power Supply
Gate Drive
Voltage
PVDD
4.5V~26.4V
GVDD
5V
LDO
LDO
External Filtering/Decoupling
Internal Analog
Circuitry
PVDD
AVDD
5V
External Filtering/Decoupling
Copyright © 2017, Texas Instruments Incorporated
图 10-1. Power Supply Function Block Diagram
10.1 DVDD Supply
The DVDD supply that is required from the system is used to power several portions of the device. As shown in
图 10-1, it provides power to the DVDD pin. Proper connection, routing and decoupling techniques are
highlighted in the 节 9 section and the 节 11.2 section and must be followed as closely as possible for proper
operation and performance.
Some portions of the device also require a separate power supply that is a lower voltage than the DVDD supply.
To simplify the power supply requirements for the system, the DRV5825P device includes an integrated low
dropout (LDO) linear regulator to create this supply. This linear regulator is internally connected to the DVDD
supply and its output is presented on the DVDD_REG pin, providing a connection point for an external bypass
capacitor. It is important to note that the linear regulator integrated in the device has only been designed to
support the current requirements of the internal circuitry, and should not be used to power any additional external
circuity. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and
operation of the device.
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10.2 PVDD Supply
The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which
provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques
are highlighted in the DRV5825PEVM and must be followed as closely as possible for proper operation and
performance. Due to the high-voltage switching of the output stage, it is particularly important to properly
decouple the output power stages in the manner described in the device 节 9. Lack of proper decoupling, like
that shown in the 节 9, results in voltage spikes which can damage the device.
A separate power supply is required to drive the gates of the MOSFETs used in the output stage of the speaker
amplifier. This power supply is derived from the PVDD supply via an integrated linear regulator. A GVDD pin is
provided for the attachment of decoupling capacitor for the gate drive voltage regulator. It is important to note
that the linear regulator integrated in the device has only been designed to support the current requirements of
the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on this
pin could cause the voltage to sag, negatively affecting the performance and operation of the device.
Another separate power supply is derived from the PVDD supply via an integrated linear regulator is AVDD.
AVDD pin is provided for the attachment of decoupling capacitor for the DRV5825P internal circuitry. It is
important to note that the linear regulator integrated in the device has only been designed to support the current
requirements of the internal circuitry, and should not be used to power any additional external circuitry. Additional
loading on this pin could cause the voltage to sag, negatively affecting the performance and operation of the
device.
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11 Layout
11.1 Layout Guidelines
11.1.1 General Guidelines for Audio Amplifiers
Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and
the layout of the supporting components used around them. The system level performance metrics, including
thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all
affected by the device and supporting component layout.
Ideally, the guidance provided in the applications section with regard to device and component selection can be
followed by precise adherence to the layout guidance shown in the 节 11.2 section. These examples represent
exemplary baseline balance of the engineering trade-offs involved with lying out the device. These designs can
be modified slightly as needed to meet the needs of a given application. In some applications, for instance,
solution size can be compromised to improve thermal performance through the use of additional contiguous
copper neat the device. Conversely, EMI performance can be prioritized over thermal performance by routing on
internal traces and incorporating a via picket-fence and additional filtering components. In all cases, it is
recommended to start from the guidance shown in the 节 11.2 section and work with TI field application
engineers or through the E2E community to modify it based upon the application specific goals.
11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
Placing the bypassing and decoupling capacitors close to supply has long been understood in the industry. This
applies to DVDD, AVDD, GVDD and PVDD. However, the capacitors on the PVDD net for the DRV5825P device
deserve special attention.
The small bypass capacitors on the PVDD lines of the DUT must be placed as close to the PVDD pins as
possible. Not only dose placing these device far away from the pins increase the electromagnetic interference in
the system, but doing so can also negatively affect the reliability of the device. Placement of these components
too far from the DRV5825P device can cause ringing on the output pins that can cause the voltage on the output
pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table, damaging the
deice . For that reason, the capacitors on the PVDD net must be no further away from their associated PVDD
pins than what is shown in the example layouts in the 节 11.2 section.
11.1.3 Optimizing Thermal Performance
Follow the layout example shown in the 图 11-1 to achieve the best balance of solution size, thermal, audio, and
electromagnetic performance. In some cases, deviation from this guidance can be required due to design
constraints which cannot be avoided. In these instances, the system designer should ensure that the heat can
get out of the device and into the ambient air surrounding the device. Fortunately, the heat created in the device
naturally travels away from the device and into the lower temperature structures around the device.
11.1.3.1 Device, Copper, and Component Layout
Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures.
These tips should be followed to achieve that goal:
• Avoid placing other heat producing components or structures near the amplifier (including above or below in
the end equipment).
• If possible, use a higher layer count PCB to provide more heat sinking capability for the device and to prevent
traces and copper signal and power planes from breaking up the contiguous copper on the top and bottom
layer.
• Place the DRV5825P device away from the edge of the PCB when possible to ensure that the heat can travel
away from the device on all four sides.
• Avoid cutting off the flow of heat from the DRV5825P device to the surrounding areas with traces or via
strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular
to the device.
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• Unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads, orient it so that the narrow end of the passive component is facing the DRV5825P
device.
• Because the ground pins are the best conductors of heat in the package, maintain a contiguous ground plane
from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible.
11.1.3.2 Stencil Pattern
The recommended drawings for the DRV5825P device PCB foot print and associated stencil pattern are shown
at the end of this document in the package addendum. Additionally, baseline recommendations for the via
arrangement under and around the device are given as a starting point for the PCB design. This guidance is
provided to suit the majority of manufacturing capabilities in the industry and prioritizes manufacturability over all
other performance criteria. In elevated ambient temperature or under high-power dissipation use-cases, this
guidance may be too conservative and advanced PCB design techniques may be used to improve thermal
performance of the system.
Note
The customer must verify that deviation from the guidance shown in the package addendum, including
the deviation explained in this section, meets the customer’s quality, reliability, and manufacturability
goals.
11.1.3.2.1 PCB footprint and Via Arrangement
The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the
shape and position of the copper patterns to which the DRV5825P device is soldered. This footprint can be
followed directly from the guidance in the package addendum at the end of this data sheet. It is important to
make sure that the thermal pad, which connects electrically and thermally to the PowerPAD™ of the DRV5825P
device, be made no smaller than what is specified in the package addendum. This ensures that the DRV5825P
device has the largest interface possible to move heat from the device to the board.
The via pattern shown in the package addendum provides an improved interface to carry the heat from the
device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings)
present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away
from the device and into the surrounding structures and air. By increasing the number of vias, as shown in the 节
11.2 section, this interface can benefit from improved thermal performance.
Note
Vias can obstruct heat flow if they are not constructed properly.
More notes on the construction and placement of vias are as follows:
• Remove thermal reliefs on thermal vias, because they impede the flow of heat through the via.
• Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the
additional cost of filled vias.
• The diameter of the drull must be 8 mm or less. Also, the distance between the via barrel and the surrounding
planes should be minimized to help heat flow from the via into the surrounding copper material. In all cases,
minimum spacing should be determined by the voltages present on the planes surrounding the via and
minimized wherever possible.
• Vias should be arranged in columns, which extend in a line radially from the heat source to the surrounding
area. This arrangement is shown in the 节 11.2 section.
• Ensure that vias do not cut off power current flow from the power supply through the planes on internal
layers. If needed, remove some vias that are farthest from the DRV5825P device to open up the current path
to and from the device.
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11.1.3.2.2 Solder Stencil
During the PCB assembly process, a piece of metal called a stencil on top of the PCB and deposits solder paste
on the PCB wherever there is an opening (called an aperture) in the stencil. The stencil determines the quantity
and the location of solder paste that is applied to the PCB in the electronic manufacturing process. In most
cases, the aperture for each of the component pads is almost the same size as the pad itself. However, the
thermal pad on the PCB is large and depositing a large, single deposition of solder paste would lead to
manufacturing issues. Instead, the solder is applied to the board in multiple apertures, to allow the solder paste
to outgas during the assembly process and reduce the risk of solder bridging under the device. This structure is
called an aperture array, and is shown in the 节 11.2 section. It is important that the total area of the aperture
array (the area of all of the small apertures combined) covers between 70% and 80% of the area of the thermal
pad itself.
11.2 Layout Example
2
11cm
From
System
Processor
图 11-1. 2.0 (Stereo BTL) 3-D View
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图 11-2. 2.0 (Stereo BTL) Top Copper View
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
The glossary listed in the section is a general glossary with commonly used acronyms and words which are
defined in accordance with a broad TI initiative to comply with industry standards such as JEDEC, IPC, IEEE,
and others. The glossary provided in this section defines words, phrases, and acronyms that are unique to this
product and documentation, collateral, or support tools and software used with this product. For any additional
questions regarding definitions and terminology, please see the e2e Audio Amplfier Forum.
Bridge tied load (BTL) is an output configuration in which one terminal of the speaker is connected to one half-
bridge and the other terminal is connected to another half-bridge.
DUT refers to a device under test to differentiate one device from another.
Closed-loop architecture describes a topology in which the amplifier monitors the output terminals, comparing
the output signal to the input signal and attempts to correct for non-linearities in the output.
Dynamic controls are those which are changed during normal use by either the system or the end-user.
GPIO is a general purpose input/output pin. It is a highly configurable, bi-directional digital pin which can perform
many functions as required by the system.
Host processor (also known as System Processor, Scalar, Host, or System Controller) refers to device
which serves as a central system controller, providing control information to devices connected to it as well as
gathering audio source data from devices upstream from it and distributing it to other devices. This device often
configures the controls of the audio processing devices (like the SN005825C) in the audio path in order to
optimize the audio output of a loudspeaker based on frequency response, time alignment, target sound pressure
level, safe operating area of the system, and user preference.
HybridFlow uses components which are built in RAM and components which are built in ROM to make a
configurable device that is easier to use than a fully-programmable device while remaining flexible enough to be
used in several applications
Maximum continuous output power refers to the maximum output power that the amplifier can continuously
deliver without shutting down when operated in a 25°C ambient temperature. Testing is performed for the period
of time required that their temperatures reach thermal equilibrium and are no longer increasing
Parallel bridge tied load (PBTL) is an output configuration in which one terminal of the speaker is connected to
two half-bridges which have been placed in parallel and the other terminal is connected to another pair of half
bridges placed in parallel
rDS(on) is a measure of the on-resistance of the MOSFETs used in the output stage of the amplifier.
Static controls/Static configurations are controls which do not change while the system is in normal use.
Vias are copper-plated through-hole in a PCB.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
12.4 Trademarks
PowerPAD™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
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DRV5825P
ZHCSLS8 – AUGUST 2020
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12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV5825PRHBR
ACTIVE
VQFN
RHB
32
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-25 to 85
5825P
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV5825PRHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RHB 32
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
DRV5825PRHBR
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
20.000
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
SEE SIDE WALL
DETAIL
2X
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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