DRV8311P_技术文档

DRV8311

SLVSFN2 – SEPTEMBER 2021

DRV8311 Three-Phase PWM Motor Driver

1 Features

3 Description

•

Three-phase PWM motor driver

– 3-Phase brushless DC motors

3-V to 20-V operating voltage

– 24-V Absolute maximum voltage

High output current capability

– 5-A Peak current drive

Low on-state resistance MOSFETs

– 200-mΩ typ R_DS(ON)(HS + LS) at T_A= 25°C

Low power sleep mode

– 1.5-µA at V_VM= 12-V, T_A= 25°C

Multiple control interface options

– 6x PWM control interface

The DRV8311 provides three integrated MOSFET

half-H-bridges for driving a three-phase brushless DC

(BLDC) motor for 9-V, 12-V, or 18-V DC rails or

1S to 4S battery powered applications. The device

integrates three current-sense amplifiers (CSA) with

integrated current sense for sensing the three phase

currents of BLDC motors to achieve optimum FOC

and current-control system implementation.

The DRV8311P device provides capability to generate

and configure PWM timers over Texas Instruments

SPI (tSPI), and allows the control of multiple BLDC

motors directly over the tSPI interface. This feature

reduces the number of required I/O ports from the

primary controller to control multiple motors.

– 3x PWM control interface

– PWM generation mode (SPI/tSPI) with optional

calibration between MCU and DRV8311

tSPI interface (DRV8311P)

– PWM duty and frequency update over SPI

– Control multiple DRV8311P devices using

standard 4-wire SPI interface

Supports up to 200-kHz PWM frequency

Integrated current sensing

– No external resistor required

– Sense amplifier output, one per 1/2-H

SPI and hardware device variants

– 10-MHz SPI communication (SPI/tSPI)

Supports 1.8-V, 3.3-V, and 5-V logic inputs

Built-in 3.3-V ± 4.5%, 100-mA LDO regulator

Integrated protection features

– VM undervoltage lockout (UVLO)

– Charge pump undervoltage (CPUV)

– Overcurrent protection (OCP)

Device Information⁽¹⁾

•

PART NUMBER

DRV8311H

PACKAGE

BODY SIZE (NOM)

3.00 mm × 3.00 mm

WQFN (24)

DRV8311S⁽²⁾

WQFN (24)

DRV8311P

•

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

(2) Device available for preview only.

•

3- to 20-V (24-V abs max)

LDO out

3.3V up to 100mA

6x / 3x PWM

PWM input

DRV8311H/S

•

A

B

C

nSLEEP

Only on H variant

Charge Pump

SPI

Only on SPI variant

Built-in Protec on

LDO Regulator

MCU

CSA out

3x voltage feedback

nFAULT

5-A peak output current

Integrated Current Sensing

– Thermal warning and shutdown (OTW/OTSD)

– Fault condition indication pin (nFAULT)

DRV8311H/S Simplified Schematic

2 Applications

3- to 20-V (24-V abs max)

LDO out

•

Brushless-DC (BLDC) Motor Modules

Drones and Handheld Gimbal

Coffee Machines

Vacuum Robots

Washer and Dryer Pumps

Laptop, Desktop, and Server Fans

3.3V up to 100mA

nSLEEP

DRV8311P

A

B

C

Charge Pump

tSPI

Motor control

Built-in Protec on

LDO Regulator

MCU

CSA out

3x voltage feedback

5-A peak output current

nFAULT

Integrated Current Sensing

DRV8311P Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change

without notice.

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings ....................................... 6

6.2 ESD Ratings .............................................................. 6

6.3 Recommended Operating Conditions ........................6

6.4 Thermal Information ...................................................7

6.5 Electrical Characteristics ............................................7

6.6 SPI Timing Requirements ........................................ 12

6.7 SPI Secondary Mode Timings...................................13

7 Detailed Description......................................................14

7.1 Overview...................................................................14

7.2 Functional Block Diagram.........................................15

7.3 Feature Description...................................................18

7.4 Device Functional Modes..........................................43

7.5 SPI Communication.................................................. 44

8 DRV8311 Registers........................................................49

9 Application and Implementation..................................72

9.1 Application Information............................................. 72

9.2 Typical Applications.................................................. 74

10 Power Supply Recommendations..............................75

10.1 Bulk Capacitance....................................................75

11 Layout...........................................................................76

11.1 Layout Guidelines................................................... 76

11.2 Layout Example...................................................... 77

11.3 Thermal Considerations..........................................78

12 Device and Documentation Support..........................79

12.1 Support Resources................................................. 79

12.2 Trademarks.............................................................79

12.3 Electrostatic Discharge Caution..............................79

12.4 Glossary..................................................................79

13 Mechanical, Packaging, and Orderable

Information.................................................................... 79

13.1 Tape and Reel Information......................................83

4 Revision History

DATE

REVISION

NOTES

September 2021

*

Initial release.

2

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

5 Pin Configuration and Functions

1

2

3

4

5

6

7

19

18

17

16

15

14

13

INLB

INLA

AVDD

nFAULT

CSAREF

SOC

DRV8311S

(Thermal PAD)

AGND

INHA

INHB

INHC

SOB

SOA

CP

VIN_AVDD

Figure 5-1. DRV8311S 24-Pin WQFN With Exposed Thermal Pad Top View

1

2

3

4

5

6

7

19

18

17

16

15

14

13

INLB

INLA

AVDD

nFAULT

CSAREF

SOC

DRV8311H

(Thermal PAD)

AGND

INHA

INHB

INHC

SOB

SOA

CP

VIN_AVDD

Figure 5-2. DRV8311H 24-Pin WQFN With Exposed Thermal Pad Top View

Submit Document Feedback

3

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

1

2

3

4

5

6

7

19

18

17

16

15

14

13

PWM_SYNC

NC

nFAULT

CSAREF

AVDD

SOC

DRV8311P

(Thermal PAD)

AGND

AD0

AD1

NC

SOB

SOA

CP

VIN_AVDD

Figure 5-3. DRV8311P 24-Pin WQFN With Exposed Thermal Pad Top View

Table 5-1. Pin Functions

24-pin Package

TYPE⁽¹⁾

DESCRIPTION

DRV8311

H

NAME

DRV8311P DRV8311S

ADo

—

16

17

15

14

16

—

16

I

Only on tSPI device DRV8311P. Address selection for tSPI.

Device analog ground. Connect to system ground.

AD1

AGND

PWR

3.3V regulator output. Connect a X5R or X7R, up to 4.7-µF, 6.3-V ceramic

capacitor between the AVDD and AGND pins. This regulator can source up

to 100 mA externally.

AVDD

17

PWR

6

2

Charge pump output. Connect a X5R or X7R, 0.1-µF, 16-V ceramic capacitor

between the VCP and VM pins.

CP

6

2

6

2

PWR

Current sense amplifier power supply input and reference. Connect a X5R or

X7R, 0.1-µF, 6.3-V ceramic capacitor between the CSAREF and AGND pins.

CSAREF

21

Only on Hardware devices (DRV8311H). Current sense amplifier gain

setting. The pin is a 4 level input pin configured by an external resistor

between GAIN and AVDD or GND.

GAIN

—

I

15

14

13

18

19

20

23

High-side driver control input for OUTA. This pin controls the state of the

high-side MOSFET in 6x/3x PWM Mode.

INHA

INHB

INHC

INLA

INLB

INLC

—

15

14

13

18

19

20

I

High-side driver control input for OUTB. This pin controls the state of the

high-side MOSFET in 6x/3x PWM Mode.

High-side driver control input for OUTC. This pin controls the state of the

high-side MOSFET in 6x/3x PWM Mode.

Low-side driver control input for OUTA. This pin controls the state of the

low-side MOSFET in 6x PWM Mode.

Low-side driver control input for OUTB. This pin controls the state of the

low-side MOSFET in 6x PWM Mode.

Low-side driver control input for OUTC. This pin controls the state of the

low-side MOSFET in 6x PWM Mode.

Only on Hardware devices (DRV8311H). PWM mode setting. This pin is a 4

level input pin configured by an external resistor between MODE and AVDD

or GND.

MODE

—

1

—

1

I

1

Fault indication pin. Pulled logic-low with fault condition; open-drain output

requires an external pullup to AVDD.

nFAULT

O

4

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

Table 5-1. Pin Functions (continued)

24-pin Package

DRV8311

TYPE⁽¹⁾

DESCRIPTION

NAME

DRV8311P DRV8311S

H

—

Only on SPI (DRV8311S) and tSPI (DRV8311P) devices. Serial chip select.

A logic low on this pin enables serial interface communication (SPI devices).

nSCS

20

24

—

I

24

Only on DRV8311H and DRV8311P devices. When this pin is logic low the

device goes to a low-power sleep mode. A 15 to 50-µs low pulse can be

used to reset fault conditions without entering sleeep mode.

nSLEEP

OUTA

OUTB

OUTC

PGND

10

11

12

9

10

11

12

9

10

11

12

9

O

Half bridge output A. Connect to motor winding.

Half bridge output B. Connect to motor winding.

Half bridge output C. Connect to motor winding.

Device power ground. Connect to system ground.

O

PWR

—

Only on tSPI device DRV8311P. Connect to the MCU signal to synchronize

the internally-generated PWM signals from DRV8311 to the MCU in PWM

generation mode.

PWM_SY

NC

18

23

—

I

—

Only on SPI (DRV8311S) and tSPI (DRV8311P) devices. Serial clock input.

Serial data is shifted out on the rising edge and captured on the falling edge

of SCLK (SPI devices).

SCLK

23

—

22

Only on SPI (DRV8311S) and tSPI (DRV8311P) devices. Serial data input.

Data is captured on the falling edge of the SCLK pin (SPI devices).

SDI

22

21

—

22

21

—

I

O

I

Only on SPI (DRV8311S) and tSPI (DRV8311P) devices. Serial data output.

Data is shifted out on the rising edge of the SCLK pin.

SDO

SLEW

Only on DRV8311H device. Slew rate control setting. This pin is a 4 level

input pin set by an external resistor between SLEW pin and AVDD or GND.

SOA

SOB

SOC

5

4

3

5

4

3

5

4

3

O

Current sense amplifier output for OUTA.

Current sense amplifier output for OUTB.

Current sense amplifier output for OUTC.

Power supply for the motor. Connect to motor supply voltage. Connect a X5R

or X7R, 0.1-uF VM-rated ceramic bypass capacitor as well as a >=10-uF,

VM-rated bulk capacitor between VM and PGND. Additionally, connect a

X5R or X7R, 0.1-uF, 16-V ceramic capacitor between the VM and CP pins.

VM

8

7

8

7

8

7

PWR

Supply input for AVDD. Bypass to AGND with a X5R or X7R, 0.1-uF,

VIN_AVDD-rated ceramic capacitor as well as a >=10-uF, VIN_AVDD-rated

rated bulk capacitor between VIN_AVDD and PGND.

VIN_AVDD

Thermal

pad

PWR

—

Must be connected to PGND.

NC

—

13,18

—

No connect. Leave the pin floating.

(1) I = input, O = output, PWR = power, NC = no connect

Submit Document Feedback

5

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX UNIT

Power supply pin voltage (VM)

24

V

AVDD regulator input pin voltage (VIN_AVDD)

Voltage difference between ground pins (PGND, AGND)

Charge pump voltage (CP)

0.3

V_M+ 6

4

Analog regulator output pin voltage (AVDD)

Logic pin input voltage (INHx, INLx, nSCS, nSLEEP, SCLK, SDI, ADx, GAIN, MODE, SLEW,

PWM_SYNC)

–0.3

6

V

Logic pin output voltage (nFAULT, SDO)

Open drain output current range (nFAULT)

Current sense amplifier reference supply input (CSAREF)

Current sense amplifier output (SOx)

Peak Output Current (OUTA, OUTB, OUTC)

Output pin voltage (OUTA, OUTB, OUTC)

Ambient temperature, T_A

–0.3

0

6

V

mA

V

5

–0.3

4

V

5

A

–1

–40

–65

V_M+ 1⁽²⁾

V

125

°C

Junction temperature, T_J

150

Storage tempertaure, T_stg

150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) VM + 1 V or 24 V (whichever is smaller).

6.2 ESD Ratings

VALUE

UNIT

Electrostatic

discharge

V_(ESD)

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾

±1000

V

Electrostatic

discharge

±250

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

3

NOM

12

MAX UNIT

V_VM

Power supply voltage

V_VM

20

V

VIN_AVDD AVDD regulator input pin voltage

V_{VIN_AVDD}

3

12

f_PWM

Output PWM frequency

Peak output current

OUTA, OUTB, OUTC

200

5

kHz

A

(1)

I_OUT

INHx, INLx, nSCS, nSLEEP, SCLK,

SDI, ADx, GAIN, MODE, SLEW,

PWM_SYNC

V_IN

Logic input voltage

-0.1

5.5

V

V_OD

I_OD

Open drain pullup voltage

Open drain output sink current

CSA refernce input Voltage

CSA refernce input Current

nFAULT

CSAREF

5.5

5

V

mA

V

V_CSAREF

I_CSAREF

2

3.6

7.5

2.5

mA

6

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

over operating ambient temperature range (unless otherwise noted)

MIN

–40

NOM

MAX UNIT

T_A

T_J

Operating ambient temperature

Operating Junction temperature

125

150

°C

(1) Power dissipation and thermal limits must be observed

6.4 Thermal Information

DRV8311

THERMAL METRIC⁽¹⁾

QFN (RRW)

24 Pins

42.6

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

37.9

15.7

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

Ψ_JB

15.6

R_θJC(bot)

4.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

at T_J= –40°C to +150°C, V_VM= 3 to 20 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 12 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER SUPPLIES

V_VM= 12 V, nSLEEP = 0, T_A= 25 °C

nSLEEP = 0, T_A= 125 °C

1.5

3

9

µA

I_VMQ

VM sleep mode current

V_VM= 12 V, nSLEEP = 1, INHx = INLx =

0, SPI = 'OFF', T_A= 25 °C

7

8

9

mA

I_VMS

VM standby mode current

nSLEEP = 1, INHx = INLx = 0, SPI =

'OFF'

10 mA

12 mA

14 mA

V_VM= 12 V, nSLEEP = 1, f_PWM= 25 kHz,

T_A= 25 °C

10

12

V_VM= 12 V, nSLEEP = 1, f_PWM= 200

kHz, T_A= 25 °C

I_VM

VM operating mode current

nSLEEP =1, f_PWM= 25 kHz

nSLEEP =1, f_PWM= 200 kHz

10

12

12 mA

15 mA

V_VM> 4V, V_{VIN_AVDD}> 4.5V, 0 mA ≤

I_AVDD≤ 100 mA

V_AVDD

3.15

3

3.3

3.45

V

V_VM> 3.5V, 3.5V ≤V_{VIN_AVDD}≤ 4.5V, 0

mA ≤ I_AVDD≤ 35 mA

3.6

3.4

3.6

2.5V ≤V_{VIN_AVDD}≤ 3.5V, 0 mA ≤ I_AVDD

10 mA

≤

VIN_AVDD

-0.3

Analog regulator voltage

2.2

3

V_VM< 4V, V_{VIN_AVDD}> 4.5V, 0 mA ≤

I_AVDD≤ 40 mA

3.3

V_VM< 3.5V, 3.5V ≤V_{VIN_AVDD}≤ 4.5V, 0

mA ≤ I_AVDD≤ 20 mA

V_AVDD

3

3.3

I_{AVDD_LIM}

External analog regulator current limit

148

200

250 mA

Submit Document Feedback

7

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

at T_J= –40°C to +150°C, V_VM= 3 to 20 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 12 V

PARAMETER

TEST CONDITIONS

V_VM> 4V, V_{VIN_AVDD}> 4.5V

V_VM< 4V, V_{VIN_AVDD}> 4.5V

V_VM> 3.5V, 3.6V ≤V_{VIN_AVDD}≤ 4.5V

V_VM< 3.5V, 3.6V ≤V_{VIN_AVDD}≤ 4.5V

2.5V ≤V_{VIN_AVDD}≤ 3.6V

MIN

TYP

MAX UNIT

100 mA

40 mA

35 mA

20 mA

10 mA

I_AVDD

External analog regulator load

I_AVDD≤ 25 mA;

0.7

3.3

-3

1

7

3

µF

%

C_AVDD

Capacitance on AVDD pin

I_AVDD≥ 25 mA;

4.7

V_{VIN_AVDD}> 4.5V; I_AVDD≤ 20 mA;

V_{VIN_AVDD}> 4.5V; 20 mA ≤ I_AVDD≤ 40

mA;

R_AVDD

AVDD Output Voltage Regulation

-2

-3

2

3

%

V_{VIN_AVDD}> 4.5V; I_AVDD≥ 40 mA;

VCP with respect to VM

%

V

V_VCP

Charge pump regulator voltage

Wakeup time

5

1

V_VM> V_UVLO, nSLEEP = 1 to Output

ready

t_WAKE

3

ms

µs

V_CSAREF> V_{CSAREF_UV}to SOx ready,

when nSLEEP = 1

t_{WAKE_CSA}

Wakeup time for CSA

30

t_SLEEP

t_RST

Turn-off time

nSLEEP = 0 to driver tri-stated

nSLEEP = 0 period to reset faults

100

200

50

µs

Reset Pulse time

15

LOGIC-LEVEL INPUTS (INHx, INLx, nSLEEP, SCLK, SDI)

V_IL

Input logic low voltage

Input logic high voltage

Input logic hysteresis

Input logic low current

0

1.5

200

–1

0.6

5.5

V

V_IH

V_HYS

I_IL

500 mV

V_PIN(Pin Voltage) = 0 V

nSLEEP, V_PIN(Pin Voltage) = 5 V

Other pins, V_PIN(Pin Voltage) = 5 V

nSLEEP

1

30

µA

kΩ

pF

I_IH

Input logic high current

50

230

160

30

300

200

R_PD

C_ID

Input pulldown resistance

Input capacitance

Other pins

LOGIC-LEVEL INPUTS (nSCS)

V_IL

Input logic low voltage

Input logic high voltage

Input logic hysteresis

Input logic low current

Input logic high current

Input pullup resistance

Input capacitance

0

1.5

0.6

5.5

V

V_IH

V_HYS

I_IL

200

500 mV

V_PIN(Pin Voltage) = 0 V

V_PIN(Pin Voltage) = 5 V

90

70

µA

kΩ

pF

I_IH

R_PU

C_ID

48

30

FOUR-LEVEL INPUTS (GAIN, MODE, SLEW)

0.2*AVD

D

V_L1

V_L2

V_L3

V_L4

Input mode 1 voltage

Input mode 2 voltage

Input mode 3 voltage

Input mode 4 voltage

Tied to AGND

47 kΩ +/- 5% tied to GND

Hi-Z

0

V

0.27*AV

DD

0.545*AV

DD

0.5*AVDD

0.606*AV 0.757*AVD 0.909*AV

DD

D

DD

0.94*AV

DD

Tied to AVDD

AVDD

R_PU

R_PD

Input pullup resistance

To AVDD

To AGND

48

kΩ

Input pulldown resistance

160

OPEN-DRAIN OUTPUTS (nFAULT)

8

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

at T_J= –40°C to +150°C, V_VM= 3 to 20 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 12 V

PARAMETER

Output logic low voltage

Output logic high current

Output capacitance

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_OL

I_OH

I_OD= -5 mA

0.4

1

V

V_OD= 5 V

–1

µA

pF

C_OD

30

PUSH-PULL OUTPUTS (SDO)

I_OP= -5 mA, 2.2V ≤ V_AVDD≤ 3V

I_OP= -5 mA, 3V ≤ V_AVDD≤ 3.6V

0

0.55

0.5

V

V_OLOutput logic low voltage

V_AVDD

-

I_OP= 5 mA, 2.2V ≤ V_AVDD≤ 3V

I_OP= 5 mA, 3V ≤ V_AVDD≤ 3.6V

3

V

0.86

V_OH

Output logic high voltage

V_AVDD

-

3.6

0.5

I_OL

Output logic low current

Output logic high current

Output capacitance

V_OP= 0 V

V_OP= 5 V

–1

1

µA

pF

I_OH

C_OD

30

DRIVER OUTPUTS

Total MOSFET on resistance (High-side

R_DS(ON)

SR

6V ≥ V_VM≥ 3 V, I_OUT= 1 A, T_J= 25°C

6V ≥ V_VM≥ 3 V, I_OUT= 1 A, T_J= 150°C

V_VM≥ 6 V, I_OUT= 1 A, T_J= 25°C

300

450

200

330

35

350 mΩ

500 mΩ

250 mΩ

375 mΩ

55 V/us

+ Low-side)

Total MOSFET on resistance (High-side

+ Low-side)

Total MOSFET on resistance (High-side

+ Low-side)

Total MOSFET on resistance (High-side

+ Low-side)

V_VM≥ 6 V, I_OUT= 1 A, T_J= 150°C

V_VM= 12V; SLEW = 00b (SPI Variant)

or SLEW pin tied to AGND (HW Variant)

20

50

V_VM= 12V; SLEW = 01b (SPI Variant)

or SLEW pin to 47 kΩ +/- 5% tied to

AGND (HW Variant)

SR

75

100 V/us

Phase pin slew rate switching low to high

(Rising from 20 % to 80 % of VM)

V_VM= 12V; SLEW = 10b (SPI Variant)

or SLEW pin to Hi-Z (HW Variant)

SR

150

180

20

180

230

35

210 V/us

280 Vus

55 V/us

V_VM= 12V; SLEW = 11b (SPI Variant)

or SLEW pin tied to AVDD (HW Variant)

V_VM= 12V; SLEW = 00b (SPI Variant)

or SLEW pin tied to AGND (HW Variant)

V_VM= 12V; SLEW = 01b (SPI Variant)

or SLEW pin to 47 kΩ +/- 5% tied to

AGND (HW Variant)

50

75

100 V/us

Phase pin slew rate switching high to low

(Falling from 80 % to 20 % of VM)

SR

V_VM= 12V; SLEW = 10b (SPI Variant)

or SLEW pin to Hi-Z (HW Variant)

150

180

230

210 V/us

280 V/us

V_VM= 12V; SLEW = 11b (SPI Variant)

or SLEW pin tied to AVDD (HW Variant)

Submit Document Feedback

9

Product Folder Links: DRV8311

DRV8311

www.ti.com

MAX UNIT

SLVSFN2 – SEPTEMBER 2021

at T_J= –40°C to +150°C, V_VM= 3 to 20 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 12 V

PARAMETER

TEST CONDITIONS

MIN

TYP

V_VM= 12V, SLEW = 00b (SPI Variant)

or SLEW pin tied to AGND (HW

Variant), HS driver ON to LS driver OFF;

DEADTIME = 000b; Handshake only

900

1200

750

ns

V_VM= 12V, SLEW = 01b (SPI Variant)

or SLEW pin to 47 kΩ +/- 5% tied

to AGND (HW Variant), HS driver ON

to LS driver OFF; DEADTIME = 000b;

Handshake only

600

V_VM= 12V, SLEW = 10b (SPI Variant)

or SLEW pin to Hi-Z (HW Variant), HS

driver ON to LS driver OFF; DEADTIME

= 000b; Handshake only

400

350

550

540

ns

V_VM= 12V, SLEW = 11b (SPI Variant)

or SLEW pin tied to AVDD (HW Variant),

DEADTIME = 000b; Handshake only

Output dead time (high to low / low to

high)

t_DEAD

V_VM= 12 V; HS driver ON to LS driver

OFF; DEADTIME = 001b

200

400

ns

V_VM= 12 V; HS driver ON to LS driver

OFF; DEADTIME = 010b

V_VM= 12 V; HS driver ON to LS driver

OFF; DEADTIME = 011b

600

V_VM= 12 V; HS driver ON to LS driver

OFF; DEADTIME = 100b

800

V_VM= 12 V; HS driver ON to LS driver

OFF; DEADTIME = 101b

1000

1200

1400

V_VM= 12 V; HS driver ON to LS driver

OFF; DEADTIME = 110b

V_VM= 12 V; HS driver ON to LS driver

OFF; DEADTIME = 111b

INHx = 1 to OUTx transisition, V_VM

=

12V, SLEW = 00b (SPI Variant) or SLEW

pin tied to AGND (HW Variant)

1000

700

1500

1000

ns

INHx = 1 to OUTx transisition, V_VM

= 12V, SLEW = 01b (SPI Variant)

or SLEW pin to 47 kΩ +/- 5% tied to

AGND (HW Variant)

Propagation delay (high-side / low-side

ON/OFF)

t_PD

INHx = 1 to OUTx transisition, V_VM

=

12V, SLEW = 10b (SPI Variant) or SLEW

pin to Hi-Z (HW Variant)

450

400

750

650

INHx = 1 to OUTx transisition, V_VM

= 12V, SLEW = 11b (SPI Variant)

or SLEW pin tied to AVDD (HW Variant)

ns

t_{MIN_PULSE}

Minimum output pulse width

SLEW = 11b

500

CURRENT SENSE AMPLIFIER

CSA_GAIN = 00 (SPI Variant) or GAIN

pin tied to AGND (HW Variant)

0.25

0.5

V/A

CSA_GAIN = 01 (SPI Variant) or GAIN

pin to 47 kΩ +/- 5% tied to GND (HW

Variant)

G_CSA

Current sense gain (SPI Device)

CSA_GAIN = 10 (SPI Variant) or GAIN

pin to Hi-Z (HW Variant)

1

2

V/A

CSA_GAIN = 11 (SPI Variant) or GAIN

pin tied to AVDD (HW Variant)

10

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

at T_J= –40°C to +150°C, V_VM= 3 to 20 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 12 V

PARAMETER

TEST CONDITIONS

MIN

–3.

–8

TYP

MAX UNIT

T_J= 25°C, I_PHASE< 2.5 A

3

8

%

A

T_J= 25°C, I_PHASE> 2.5 A

I_PHASE< 2.5 A

G_{CSA_ERR}

Current sense gain error

–4.5

–10

–5.5

–5

4.5

10

5.5

5

I_PHASE> 2.5 A

T_J= 25°C

Current sense gain error matching

between phases A, B and C

I_MATCH

FS_POS

FS_NEG

Full scale positive current measurement

Full scale negative current measurement

5

–5

A

V_VREF

–

V_LINEAR

SOX output voltage linear range

0.25

–50

V

0.25

T_J= 25°C, Phase current = 0 A, G_CSA

0.25 V/A

=

50 mA

T_J= 25°C, Phase current = 0 A, G_CSA

0.5 V/A

Current sense offset low side current in

(Room Temperature)

I_{OFFSET_RT}

T_J= 25°C, Phase current = 0 A, G_CSA

1 V/A

T_J= 25°C, Phase current = 0 A, G_CSA

2 V/A

Phase current = 0 A, G_CSA= 0.25 V/A

Phase current = 0 A, G_CSA= 0.5 V/A

Phase current = 0 A, G_CSA= 1 V/A

Phase current = 0 A, G_CSA= 2 V/A

Step on SOx = 1.2 V, G_CSA= 0.25 V/A

Step on SOx = 1.2 V, G_CSA= 0.5 V/A

Step on SOx = 1.2 V, G_CSA= 1 V/A

Step on SOx = 1.2 V, G_CSA= 2 V/A

Phase current = 0 A

–50

50 mA

Current sense offset referred to low side

current in

I_OFFSET

1

μs

t_SET

Settling time to ±1%, 30 pF on SOx pin

V_DRIFT

Drift offset

–80

80 µA/℃

I_CSAREF

CSAREF input current

VREF = 3.0 V

1.7

3

mA

PROTECTION CIRCUITS

VM rising

VM falling

2.6

2.5

60

2.7

2.6

125

5

2.8

2.7

V

V_UVLOSupply undervoltage lockout (UVLO)

V_{UVLO_HYS}Supply undervoltage lockout hysteresis Rising to falling threshold

210 mV

µs

t_UVLO

Supply undervoltage deglitch time

VIN_AVDD rising

VIN_AVDD falling

2.6

2.5

2.7

2.6

2.8

2.7

V

AVDD supply input undervoltage lockout

(VINAVDD_UV)

V_{VINAVDD_UV}

V_{VINAVDD_UV}AVDD supply input undervoltage lockout

Rising to falling threshold

100

125

5

150 mV

µs

hysteresis

_HYS

AVDD supply input undervoltage deglitch

time

t_{VINAVDD_UV}

V_CPrising

V_CPfalling

2

2.3

2.2

2.5

2.4

V

Charge pump undervoltage lockout

V_CPUV

(voltage with respect to VM)

Charge pump undervoltage lockout

V_{CPUV_HYS}

hysteresis

Rising to falling threshold

65

100

0.2

125 mV

µs

Charge pump undervoltage lockout

deglitch time

t_CPUV

V_{CSAREF_UV}CSA reference undervoltage lockout

V_CSAREFrising

V_CSAREFfalling

1.68

1.6

1.8

1.7

1.95

1.85

V

V_{CSAREF_}

CSA reference undervoltage lockout

hysteresis

Rising to falling threshold

80

90

100 mV

UV_HYS

Submit Document Feedback

11

Product Folder Links: DRV8311

DRV8311

www.ti.com

MAX UNIT

SLVSFN2 – SEPTEMBER 2021

at T_J= –40°C to +150°C, V_VM= 3 to 20 V (unless otherwise noted). Typical limits apply for T_A= 25°C, V_VM= 12 V

PARAMETER

TEST CONDITIONS

MIN

TYP

V_AVDDrising

1.9

2

2.1

1.9

V

V_{AVDD_UV}

Analog regulator undervoltage lockout

V_AVDDfalling

1.7

1.8

OCP_LVL = 0 (SPI Variant) or MODE pin

tied to AGND or MODE pin to Hi-Z (HW

Variant)

5.8

3.4

9

5

11.5

7.5

A

I_OCP

Overcurrent protection trip point

OCP_LVL = 1 (SPI Variant) or MODE pin

tied to AVDD or MODE pin 47 kΩ +/- 5%

tied to AGND (HW Variant)

OCP_TBLANK = 00b

OCP_TBLANK = 01b

OCP_TBLANK = 10b

0.2

0.5

0.8

1

µs

Overcurrent protection blanking time

(SPI Variant)

t_BLANK

t_OCP

Overcurrent protection blanking time

(HW Variant)

0.2

µs

OCP_DEG = 00b

OCP_DEG = 01b

OCP_DEG = 10b

OCP_DEG = 11b

0.2

0.5

0.8

1

µs

Overcurrent protection deglitch time (SPI

Variant)

Overcurrent protection deglitch time (HW

Variant)

t_OCP

1

µs

FAST_RETRY = 00b

FAST_RETRY = 01b

FAST_RETRY = 10b

FAST_RETRY = 11b

SLOW_RETRY = 00b

SLOW_RETRY = 01b

SLOW_RETRY = 10b

SLOW_RETRY = 11b

0.5

1

ms

2

5

Overcurrent protection retry time (SPI

Variant)

t_RETRY

500

1000

2000

5000

Overcurrent protection retry time (HW

Variant)

t_RETRY

5

ms

T_OTW

Thermal warning temperature

Thermal warning hysteresis

Die temperature (T_J) Rising

Die temperature (T_J)

170

180

185

200

°C

T_{OTW_HYS}

T_TSD

T_{TSD_HYS}

T_TSD

25

Thermal shutdown temperature

Thermal shutdown hysteresis

Thermal shutdown temperature (LDO)

Thermal shutdown hysteresis (LDO)

Die temperature (T_J) Rising

Die temperature (T_J)

Die temperature (T_J) Rising

Die temperature (T_J)

T_{TSD_HYS}

6.6 SPI Timing Requirements

MIN

NOM

MAX UNIT

t_READY

t_{HI_nSCS}

t_{SU_nSCS}

t_{HD_nSCS}

t_SCLK

SPI ready after power up

nSCS minimum high time

nSCS input setup time

nSCS input hold time

1

ms

ns

300

25

SCLK minimum period

SCLK minimum high time

SCLK minimum low time

SDI input data setup time

100

50

t_SCLKH

t_SCLKL

50

t_{SU_SDI}

25

12

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

MIN

NOM

MAX UNIT

t_{HD_SDI}

SDI input data hold time

SDO output data delay time

SDO enable delay time

SDO disable delay time

25

ns

t_{DLY_SDO}

t_{EN_SDO}

t_{DIS_SDO}

15

50

ns

6.7 SPI Secondary Mode Timings

t_{HD_nSCS}

t_{HI_nSCS}

t_{SU_nSCS}

t_SCLK

t_SCLKH

t_SCLKL

X

MSB

LSB

X

t_{DIS_SDO}

t_{DLY_SDO}

t_{SU_SDI}

t_{HD_SDI}

Z

MSB

LSB

Z

t_{EN_SDO}

Figure 6-1. SPI Secondary Mode Timing Diagram

Submit Document Feedback

13

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7 Detailed Description

7.1 Overview

The DRV8311 is an integrated MOSFET driver for 3-phase motor-drive applications. The combined high-side

and low-side FET's on-state resistance is 200-mΩ typical. The device reduces system component count, cost,

and complexity by integrating three half-bridge MOSFETs, gate drivers, charge pump, current sense amplifier

and linear regulator for an external load. For the DRV8311S, a standard serial peripheral interface (SPI) provides

a simple method for configuring the various device settings and reading fault diagnostic information through an

external controller. For the DRV8311H, a hardware interface (H/W) allows for configuring the most commonly

used settings through fixed external resistors. For the DRV8311P, Texas Instruments SPI (tSPI) provides the

ability to configure various device settings and adjust the PWM duty cycle and frequency to control multiple

motors at a time.

The architecture uses an internal state machine to protect against short-circuit events, and protect against dV/dt

parasitic turn on of the internal power MOSFETs.

The DRV8311 device integrates three bidirectional low side current-shunt amplifiers for monitoring the current

through each of the half-bridges using a built-in current sense and no external current sense resistors are

needed. The gain setting of the shunt amplifier can be adjusted through the SPI, tSPI or hardware interface.

In addition to the high level of device integration, the DRV8311 device provides a wide range of integrated

protection features. These features include power supply undervoltage lockout (UVLO), charge pump

undervoltage lockout (CPUV), overcurrent protection (OCP), AVDD undervoltage lockout (AVDD_UV) and

overtemperature shutdown (OTW and OTSD). Fault events are indicated by the nFAULT pin with detailed

information available in the registers on the SPI and tSPI device versions.

The DRV8311H, DRV8311P and DRV8311S devices are available in 0.4-mm pin pitch, WQFN surface-mount

packages. The WQFN package size is 3.00 mm × 3.00 mm.

14

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.2 Functional Block Diagram

VM

+

C_CP

CP

C_VM1

C_VM2

VM

I/O Control

Protection

LS Predriver Power

Supply Regulator

Charge Pump

Overcurrent

Protection

VIN_AVDD

VLS

UVLO Protection

Thermal Warning

Thermal Shutdown

C_{VIN_AVDD2}

C_{VIN_AVDD1}

INHA

INLA

Regulator

AVDD

Ext.

Load

C_AVDD

AVDD Linear Regulator

AGND

INHB

Input

Control

INLB

Predriver Stage

CP

Power Stage

VM

INHC

HS Pre-

driver

INLC

OUTA

AVDD

VLS

R_nFAULT

LS Pre-

driver

Output

Current

Sense for

Phase - A

nFAULT

PGND

ISEN_A

Digital Control

Predriver Stage

CP

Power Stage

VM

Interface

SCLK

HS Pre-

driver

SPI

OUTB

SDI

AVDD

VLS

LS Pre-

driver

SDO

Current

Sense for

Phase - B

AVDD

PGND

nSCS

ISEN_B

Predriver Stage

CP

Power Stage

VM

CSAREF

C_CSAREF

Current Sense Amplifiers

HS Pre-

driver

ISEN_A

A_V

OUTC

SOC

SOB

SOA

VLS

ISEN_B

ISEN_C

Output Offset

Bias

LS Pre-

driver

Current

Sense for

Phase - C

PGND

ISEN_C

Thermal PAD

PGND

Figure 7-1. DRV8311S Block Diagram

Submit Document Feedback

15

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

VM

+

C_CP

CP

C_VM1

C_VM2

VM

I/O Control

Protection

LS Predriver Power

Supply Regulator

Charge Pump

Overcurrent

Protection

VIN_AVDD

VLS

nSLEEP

UVLO Protection

Thermal Warning

Thermal Shutdown

C_{VIN_AVDD2}

C_{VIN_AVDD1}

Regulator

AVDD

C_AVDD

AGND

INHA

INLA

INHB

INLB

INHC

Ext.

Load

AVDD Linear Regulator

Predriver Stage

CP

Power Stage

VM

HS Pre-

driver

Input

Control

OUTA

INLC

VLS

LS Pre-

driver

Current

Sense for

Phase - A

MODE

SLEW

GAIN

PGND

ISEN_A

Digital Control

Predriver Stage

CP

Power Stage

VM

HS Pre-

driver

OUTB

AVDD

VLS

R_nFAULT

Output

LS Pre-

driver

Current

Sense for

Phase - B

nFAULT

PGND

ISEN_B

Predriver Stage

CP

Power Stage

VM

CSAREF

C_CSAREF

Current Sense Amplifiers

HS Pre-

driver

ISEN_A

A_V

OUTC

SOC

SOB

SOA

VLS

ISEN_B

ISEN_C

Output Offset

Bias

LS Pre-

driver

Current

Sense for

Phase - C

PGND

ISEN_C

PGND

Thermal PAD

Figure 7-2. DRV8311H Block Diagram

16

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

VM

+

C_CP

CP

C_VM1

C_VM2

VM

I/O Control

Protection

LS Predriver Power

Supply Regulator

Charge Pump

Overcurrent

Protection

VIN_AVDD

nSLEEP

VLS

UVLO Protection

Thermal Warning

Thermal Shutdown

C_{VIN_AVDD2}

C_{VIN_AVDD1}

AD0

AD1

Regulator

AVDD

Ext.

Load

C_AVDD

AVDD Linear Regulator

AGND

Input

PWM_SYNC

Control

Predriver Stage

CP

Power Stage

VM

HS Pre-

driver

OUTA

VLS

AVDD

R_nFAULT

LS Pre-

driver

Output

Current

Sense for

Phase - A

nFAULT

PGND

ISEN_A

Digital Control

Predriver Stage

CP

Power Stage

VM

Interface

SCLK

SDI

HS Pre-

driver

tSPI

OUTB

AVDD

VLS

LS Pre-

driver

SDO

Current

Sense for

Phase - B

AVDD

PGND

nSCS

ISEN_B

Predriver Stage

CP

Power Stage

VM

Current Sense Amplifiers

CSAREF

C_CSAREF

HS Pre-

driver

ISEN_A

A_V

OUTC

SOC

SOB

SOA

VLS

ISEN_B

ISEN_C

Output Offset

Bias

LS Pre-

driver

Current

Sense for

Phase - C

PGND

ISEN_C

PGND

Thermal PAD

Figure 7-3. DRV8311P Block Diagram

Submit Document Feedback

17

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.3 Feature Description

Table 7-1 lists the recommended values of the external components for the driver.

Table 7-1. DRV8311 External Components

COMPONENTS

C_VM1

PIN 1

VM

PIN 2

PGND

RECOMMENDED

X5R or X7R, 0.1-µF, VM-rated capacitor

≥ 10-µF, VM-rated electrolytic capacitor

X5R or X7R, 0.1-µF, VIN_AVDD-rated capacitor

≥ 10-µF, VIN_AVDD-rated capacitor

X5R or X7R, 16-V, 0.1-µF capacitor

X5R or X7R, 0.7 to 7-µF, 6.3-V capacitor

5.1-kΩ, Pullup resistor

C_VM2

VM

PGND

C_{VIN_AVDD1}

C_{VIN_AVDD2}

C_CP

VIN_AVDD

CP

AGND

VM

C_AVDD

AVDD

MODE

SLEW

GAIN

AGND

R_nFAULT

R_SDO

nFAULT

SDO

5.1-kΩ, Pullup resistor (Optional)

Section 7.3.3.2

R_MODE

AGND or AVDD

AGND

R_SLEW

Section 7.3.3.2

R_GAIN

Section 7.3.3.2

C_CSAREF

CSAREF

X5R or X7R, 0.1-µF, CSAREF-rated capacitor

7.3.1 Output Stage

The DRV8311 device consists of integrated NMOS MOSFETs connected in a three-phase bridge configuration.

A doubler charge pump provides the proper gate-bias voltage to the high-side NMOS MOSFETs across a wide

operating voltage range in addition to providing 100% duty-cycle support. An internal linear regulator operating

from the VM supply provides the gate-bias voltage (VLS) for the low-side MOSFETs.

7.3.2 Control Modes

The DRV8311 family of devices provides three different control modes to support various commutation and

control methods. Table 7-2 shows the various modes of the DRV8311 device.

Table 7-2. PWM Control Modes

MODE Pin

(DRV8311H)

MODE Bits

(DRV8311S) (DRV8311P)

MODE Bits

MODE Type

MODE

Mode pin tied to

AGND or

Mode pin to 47

kΩ tied to

PWM_MODE =

00b or

PWM_MODE =

Mode 1

NA

6x Mode

01b

AGND

Mode pin Hi-Z

or

Mode pin tied to

AVDD

PWM_MODE =

Mode 2

Mode 3

NA

3x Mode

10b

NA

PWM_MODE = PWM_MODE =

PWM Generation Mode

11b

Note

Texas Instruments do not recommend changing the MODE pin or MODE register during power up

of the device (i.e. during tWAKE). The MODE setting on DRV8311H is latched at power up, so set

nSLEEP = 0 before changing the MODE pin configuration on the DRV8311H. In DRV8311S, set all

INHx and INLx pins to logic low before changing the MODE register.

18

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.3.2.1 6x PWM Mode (DRV8311S and DRV8311H variants only)

In 6x PWM mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). To

configure DRV8311H in 6x PWM mode, connect the MODE pin to AGND or connect the MODE pin to 47

kΩ tied to AGND. To enable 6x PWM mode in DRV8311S configure the MODE bits with PWM_MODE = 00b or

01b. The corresponding INHx and INLx signals control the output state as listed in Table 7-3.

Table 7-3. 6x PWM Mode Truth Table

INLx

INHx

OUTx

Hi-Z

H

0

1

0

1

0

1

L

Hi-Z

Figure 7-4 shows the application diagram of DRV8311 configured in 6x PWM mode.

VM

nSLEEP

(DRV8311H

only)

OUTA

INHA

VM

INLA

INHB

Controller

INLB

INHC

OUTB

Gate

Drive

and

Logic

OCP

BLDC

Motor

INLC

VM

OUTC

PGND

Figure 7-4. 6x PWM Mode

Submit Document Feedback

19

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.3.2.2 3x PWM Mode (DRV8311S and DRV8311H variants only)

In 3x PWM mode, the INHx pin controls each half-bridge and supports two output states: low or high. To

configure DRV8311H in 3x PWM mode, connect the MODE pin to AVDD or keep the MODE pin to Hi-Z. To

enable 3x PWM mode in DRV8311S configure the MODE bits with PWM_MODE = 10b. The INLx pin is used to

put the half bridge in the Hi-Z state. If the Hi-Z state is not required, tie all INLx pins to logic high (for example, by

tying them to AVDD). The corresponding INHx and INLx signals control the output state as listed in Table 7-4.

Table 7-4. 3x PWM Mode Truth Table

INLx

INHx

OUTx

Hi-Z

L

0

1

X

0

1

H

Figure 7-5 shows the typical application diagram of the DRV8311 configured in 3x PWM mode.

VM

nSLEEP

(DRV8311H

only)

OUTA

INHA

VM

INHB

INHC

Controller

INLA

INLB

OUTB

Gate

Drive

and

Logic

OCP

BLDC

Motor

INLC

VM

AVDD

OUTC

PGND

Figure 7-5. 3x PWM Mode

20

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.3.2.3 PWM Generation Mode (DRV8311S and DRV8311P Variants)

In PWM generation mode, the PWM signals are generated internally in the DRV8311 and can be controlled via a

SPI (DRV8311S) or tSPI (DRV8311P) register read/write. This operation mode removes the need for controlling

the motor through the INHx and INLx pins. The PWM period, frequency, and duty cycle for each phase can be

configured over the serial interface. A PWM_SYNC pin functionality allows synchronization between the MCU

and DRV8311. The PWM modes can be configured to enable or disable the high-side or low-side MOSFET

PWM control for each phase in order to allow for continuous or discontinuous switching whenever required.

When using the DRV8311S in PWM Generation mode, , connect the PWM_SYNC signal from MCU to the INLB

pin of DRV8311S. The DRV8311S does not care about the state of all other INHx and INLx pins in this mode.

Trapezoidal, sinusoidal, and FOC control are all possible using PWM generation mode.

VM

OUTA

nSLEEP

PWM_SYNC

VM

AD0

Controller

AD1

OUTB

Gate

Drive

and

Logic

tSPI

OCP

BLDC

Motor

VM

OUTC

PGND

Figure 7-6. PWM Generation Mode - DRV8311P

Submit Document Feedback

21

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

VM

OUTA

PWM_SYNC (INLB)

VM

Controller

SPI

OUTB

Gate

Drive

and

Logic

OCP

BLDC

Motor

VM

OUTC

PGND

Figure 7-7. PWM Generation Mode - DRV8311S

PWM generation mode has three different options: up/down mode, up mode, and down mode. The PWM

generation mode can be configured using PWMCNTR_MODE bits in the PWMG_CTRL register. The duty

cycle defined by the PWM_DUTY_OUTx bits in the PWMG_A_DUTY register, of each phase is compared

against the reference counter signal to generate the high side MOSFET PWM. The reference counter

signal is generated internally based on the configuration of PWM_PRD_OUT bits (PWMG_PERIOD register)

and PWMCNTR_MODE bits. If PWM_EN is high, the high side MOSFET PWM output is high when

PWM_DUTY_OUTx is greater than the reference counter. For PWM_EN being low, the output is always held

low. To achieve 100% duty cycle for the high side MOSFET [HS_ON for entire cycle], the PWM_DUTY_OUTx

value must be higher than the PWM_PRD_OUT value.

In up/down mode [PWMCNTR_MODE = 0h], the reference counter waveform resembles a V shape, counting

down from the PWM_PRD_OUT value when enabled and then counting up again once counter reaches zero.

Configure the PWM_PRD_OUT bits to generate a PWM frequency (F_PWM) using the relation PWM_PRD_OUT =

0.5 x (F_SYS/F_PWM). F_SYSis the DRV8311P internal system clock frequency (approximately 20MHz).

22

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

PWM _PERIOD

PWM_PRD_OUT

Reference

Counter

PWM_DUTY_OUTx

0h

HS_ON

LS_ON

Dead time

Figure 7-8. PWM Generation - Up/Down Mode

In up mode [PWMCNTR_MODE = 1h], the counter counts up from zero until it reaches the PWM_PRD_OUT

value and then resets to zero. PWM_PRD_OUT = F_SYS/F_PWM

PWM _PERIOD

PWM_PRD_OUT

Reference

Counter

PWM_DUTY_OUTx

0h

HS_ON

LS_ON

Dead time

Figure 7-9. PWM Generation - Up Mode

In down mode [PWMCNTR_MODE = 2h], the counter counts down from the PWM_PRD_OUT value until it

reaches zero and then resets to PWM_PRD_OUT value. PWM_PRD_OUT = F_SYS/F_PWM

PWM _PERIOD

PWM_PRD_OUT

Reference

Counter

PWM_DUTY_OUTx

0h

HS_ON

LS_ON

Dead time

Figure 7-10. PWM Generation - Down Mode

Submit Document Feedback

23

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

The dead time configured by the TDEAD_CTRL register is inserted between the LS_ON falling edge and the

HS_ON rising edge as well as between HS_ON falling edge and LS_ON rising edge.

PWM Synchronization in PWM Generation Mode

When there is no dedicated INHx or INLx control signals, the external MCU can lose synchronization with

PWM signal generated by the DRV8311. For synchronization, the external MCU sends one reference signal

to the PWM_SYNC pin. PWM synchronization helps to generate the DRV8311 PWM output with the accuracy

of the MCU clock and aligns PWM outputs with the MCU's ADC sampling the current sense outputs. The

PWM_SYNC signal can also help to measure the DRV8311 internal oscillator frequency. DRV8311 also support

auto-calibration of internal oscillator to calibrate the oscillator at 20MHz regardless of operating conditions.

The DRV8311 allows five different methods of synchronizing between MCU and DRV8311 by configuring the

PWM_OSC_SYNC bits of PWMG_CTRL register. The different synchronization methods are outlined below.

PWM_OSC_SYNC = 1h: The DRV8311 measures the PWM_SYNC signal period (PWM_SYNC_PRD) in counts

of DRV8311 system clock F_SYS(approximately 20MHz). The MCU reads the register PWM_SYNC_PRD and can

calibrate the PWM period. For example, assume that the MCU generate a 50% duty PWM_SYNC signal using

an MCU timer with a period count of N and clock frequency F_MCU. The MCU read the PWM_SYNC_PERIOD

register value say M, generated by DRV8311. The DRV8311 generates the PWM_SYNC_PERIOD using the

DRV8311 system clock F_SYS(DRV). Now the MCU timer clock and the DRV8311 system clock are related by the

equation F_MCUx M = F_SYS(DRV) x N.

The PWM_SYNC_PRD is 12bit and with DRV8311 internal system clock of approximately 20MHz, the minimum

PWM_SYNC frequency that can be read without saturation is approximately 4.885 kHz (F_SYS/4095).

PWM_OSC_SYNC = 2h: The PWM_SYNC signal from the MCU is used to set the PWM period of DRV8311

and PWMG_PERIOD register setting is ignored. DRV8311 resets the PWM counter on rising edge of the

PWM_SYNC.

PWM_SYNC

PWM _PERIOD

Reference

Counter

PWM_DUTY_OUTx

0h

HS_ON

LS_ON

Deadtime

Figure 7-11. PWM Synchronization in Up/down Mode (PWM_OSC_SYNC = 2h )

24

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

PWM_SYNC

PWM _PERIOD

Reference

Counter

PWM_DUTY_OUTx

0h

HS_ON

LS_ON

Dead time

Figure 7-12. PWM Synchronization in Up Mode (PWM_OSC_SYNC = 2h )

PWM_SYNC

PWM _PERIOD

Reference

Counter

PWM_DUTY_OUTx

0h

HS_ON

LS_ON

Dead time

Figure 7-13. PWM Synchronization in Down Mode (PWM_OSC_SYNC = 2h )

PWM_OSC_SYNC = 5h: PWM_SYNC is used for oscillator synchronization (only 20 kHz frequency supported).

For a PWM_SYNC signal of 20kHz, DRV8311 counts the number of internal system oscillator clock pulses

between the rising edges of PWM_SYNC signal. For DRV8311 system clock at 20MHz, the number of clock

pulses is expected to be 1000 in the ideal case. Deviation from this number implies an error in either the PWM

frequency generated by DRV8311 or the PWM_SYNC frequency from the MCU. The PWM_SYNC frequency

from MCU is assumed accurate and DRV8311 does oscillator calibration internally to calibrate the frequency at

20MHz and hence align PWM frequency generated with PWM_SYNC.

PWM_OSC_SYNC = 6h: PWM_SYNC is used for DRV8311 internal system oscillator calibration and setting

PWM period (only 20 kHz frequency supported). The PWMG_PERIOD register setting is ignored. DRV8311

resets the PWM reference counter on rising edge of the PWM_SYNC.

PWM_OSC_SYNC = 7h: The SPI Clock pin SCLK is used for the DRV8311 internal system oscillator

calibration to 20MHz. In this mode, the user has to configure the SPI clock frequency for synchronizing the

oscillator (SPICLK_FREQ_SYNC) and the number of SPI clock cycles required for synchronizing the oscillator

Submit Document Feedback

25

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

(SPISYNC_ACRCY) by configuring the PWMG_CTRL Register. The DRV8311 measures the total time for the

entire SPI clock cycles (configured by SPISYNC_ACRCY) in counts of DRV8311 internal system clock F_SYS

and calibrates the internal system clock to match the counts expected for 20MHz frequency. The DRV8311

system oscillator frequency accuracy after calibration compared to 20MHz depends on the configuration of

SPISYNC_ACRCY.

7.3.3 Device Interface Modes

The DRV8311 family of devices supports three different interface modes (SPI, tSPI and hardware) to offer

either increased simplicity (hardware interface) or greater flexibility and diagnostics (SPI interface). The SPI

(DRV8311S) and hardware (DRV8311H) interface modes share the same four pins, allowing the different

versions to be pin-to-pin compatible. Designers are encouraged to evaluate with the SPI interface version due to

ease of changing settings, and may consider switching to the hardware interface with minimal modifications to

the design.

7.3.3.1 Serial Peripheral Interface (SPI)

The SPI/tSPI devices support a serial communication bus that lets an external controller send and receive data

with the DRV8311. This support allows the external controller to configure device settings and read detailed

fault information. The interface is a four wire interface using the SCLK, SDI, SDO, and nSCS pins which are

described as follows:

•

The SCLK (serial clock) pin is an input that accepts a clock signal to determine when data is captured and

propagated on the SDI and SDO pins.

•

The SDI (serial data in) pin is the data input.

The SDO (serial data out) pin is the data output.

The nSCS (serial chip select) pin is the chip select input. A logic low signal on this pin enables SPI

communication with the DRV8311.

For more information on the SPI, see Section 7.5.

7.3.3.2 Hardware Interface

Hardware interface devices omit the four SPI pins and in their place have nSLEEP pin and three resistor-

configurable inputs which are GAIN, SLEW and MODE.

Common device settings can be adjusted on the hardware interface by tying the pin logic low, logic high,

or pulling up or pulling down with a resistor. Fault conditions are reported on the nFAULT pin, but detailed

diagnostic information is not available.

•

The GAIN pin configures the gain of the current sense amplifier.

The SLEW pin configures the slew rate of the output voltage to motor.

The MODE pin configures the PWM control mode and OCP level.

For more information on the hardware interface, see Section 7.3.9.

Table 7-5. Hardware Pins Decode

Configuration

GAIN

SLEW

MODE

Pin tied to AGND

0.25 V/A

35 V/us

6x PWM Mode and

9A OCP Level

Pin to 47 kΩ tied to AGND

Pin to Hi-Z

0.5 V/A

1 V/A

75 V/us

180 V/us

230 V/us

6x PWM Mode and

5A OCP Level

3x PWM Mode and

9A OCP Level

Pin tied to AVDD

2 V/A

3x PWM Mode and

5A OCP Level

26

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

AVDD

R_SLEW

AVDD

SCLK

SDI

SLEW

SPI

Interface

AVDD

MODE

AVDD

Hardware

Interface

SDO

nSCS

AVDD

GAIN

Figure 7-14. DRV8311 SPI Interface

Figure 7-15. DRV8311 Hardware Interface

Submit Document Feedback

27

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.3.4 AVDD Linear Voltage Regulator

A 3.3-V, 100mA linear regulator is integrated into the DRV8311 family of devices and is available to power

external circuits. The AVDD regulator is used for powering up the internal digital functions of the DRV8311 and

can also provide the supply voltage for a low-power MCU or other circuitry up to 100 mA. The output of the

AVDD regulator should be bypassed near the AVDD and AGND pins with a X5R or X7R, up to 4.7-µF, 6.3-V

ceramic capacitor routed directly back to the adjacent AGND ground pin.

The AVDD nominal, no-load output voltage is 3.3 V.

VIN_AVDD

REF

+

œ

AVDD

AGND

External Load

C_AVDD

Figure 7-16. AVDD Linear Regulator Block Diagram

Use Equation 1 to calculate the power dissipated in the device by the AVDD linear regulator.

P = (V_{VIN_AVDD}- V_AVDD) x I_AVDD

(1)

The spply input voltage for AVDD regulator (VIN_AVDD) can be same as VM supply voltage, or lower or higher

than VM supply voltage.

28

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.3.5 Charge Pump

Because the output stages use N-channel FETs, the device requires a gate-drive voltage higher than the VM

power supply to enhance the high-side FETs fully. The DRV8311 integrates a charge pump circuit that generates

a voltage above the VM supply for this purpose.

The charge pump requires a single external capacitor for operation. See Table 7-1 for details on the capacitor

value.

The charge pump shuts down when nSLEEP is low.

VM

C_CP

CP

VM

Charge

Pump

Control

C_FLY

Figure 7-17. DRV8311 Charge Pump

Submit Document Feedback

29

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.3.6 Slew Rate Control

An adjustable gate-drive current control to the MOSFETs allows for easy slew rate control. The MOSFET VDS

slew rates are a critical factor for optimizing radiated emissions, energy and duration of diode recovery spikes

and switching voltage transients related to parasitics. These slew rates are predominantly determined by the rate

of gate charge to internal MOSFETs as shown in Figure 7-18.

VM

CP

Slew Rate

Control

OUTx

CP

Slew Rate

Control

PGND

Figure 7-18. Slew Rate Circuit Implementation

The slew rate of each half-bridge can be adjusted by SLEW pin in hardware device variant or by using SLEW

register settings in SPI device variant. Each half-bridge can be figured for a slew rate setting of 35-V/µs, 75-V/µs,

180-V/µs or 230-V/µs. The slew rate is calculated by the rise-time and fall-time of the voltage on OUTx pin as

shown in Figure 7-19.

V_OUTx

VM

80%

20%

0

Time

t_fall

t_rise

Figure 7-19. Slew Rate Timings

30

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.3.7 Cross Conduction (Dead Time)

The device is fully protected from cross conduction of MOSFETs. The high-side and low-side MOSFETs are

operated to avoid any shoot through currents by inserting a dead time (t_DEAD). This is implemented by sensing

the gate-source voltage (VGS) of the high-side and low-side MOSFETs and ensured that VGS of high-side

MOSFET has reached below turn-off levels before switching on the low-side MOSFET of same half-bridge

as shown in Figure 7-20 and Figure 7-21. The VGS of the high-side and low-side MOSFETs (VGS_HS and

VGS_LS) shown in Figure 7-21 are DRV8311 internal signals.

VM

Gate

Control

+

VGS

HS

LS

–

OUTx

t_DEAD

Gate

Control

+

PGND

VGS

–

Figure 7-20. Cross Conduction Protection

OUTx HS Gate

OUTx HS

Gate

(VGS_HS)

10%

t_DEAD

OUTx LS

Gate

(VGS_LS)

10%

OUTx LS Gate

Time

Figure 7-21. Dead Time

Submit Document Feedback

31

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.3.8 Propagation Delay

The propagation delay time (t_pd) is measured as the time between an input logic edge to change in OUTx

voltage. The propagation delay time includes the input deglitch delay, analog driver delay, and depends on the

slew rate setting . The input deglitcher prevents high-frequency noise on the input pins from affecting the output

state of the gate drivers. To support multiple control modes, a small digital delay is added as the input command

propagates through the device.

INx

OUTx High

t_PD

10%

OUTx Low

OUTx

Time

Figure 7-22. Propagation Delay

32

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.3.9 Pin Diagrams

This section presents the I/O structure of all digital input and output pins.

7.3.9.1 Logic Level Input Pin (Internal Pulldown)

Figure 7-23 shows the input structure for the logic levels pins INHx, INLx, nSLEEP,MODE, SCLK and SDI. The

input can be driven with an external resistor to GND or an external logic voltage supply. It is recommended to

pull these pins low in device sleep mode to reduce leakage current through the internal pull-down resistors.

AVDD

STATE

V_IH

CONNECTION

Tied to AVDD

Tied to GND

INPUT

Logic High

Logic Low

V_IL

R_PD

ESD

Figure 7-23. Logic-Level Input Pin Structure

7.3.9.2 Logic Level Input Pin (Internal Pullup)

Figure 7-24 shows the input structure for the logic level pin nSCS. The input can be driven with an external

resistor to GND or an external logic voltage supply .

AVDD

STATE

V_IH

CONNECTION

Tied to AVDD

Tied to GND

INPUT

R_PU

Logic High

Logic Low

V_IL

ESD

Figure 7-24. nSCS Input Pin Structure

7.3.9.3 Open Drain Pin

Figure 7-25 shows the structure of the open-drain output pin nFAULT. The open-drain output requires an external

pullup resistor to a logic voltage supply to function properly.

AVDD

STATE

No Fault

Fault

STATUS

Pulled-Up

R_PU

OUTPUT

Inactive

Active

Pulled-Down

ESD

Figure 7-25. Open Drain Output Pin Structure

Submit Document Feedback

33

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.3.9.4 Push Pull Pin

Figure 7-26 shows the structure of the push-pull pin SDO.

AVDD

STATE

V_OH

STATUS

Pulled-Up

Pulled-Down

Open

OUTPUT

Logic High

Logic Low

Hi-Z

V_OL

ESD

Hi-Z

Figure 7-26. Push-Pull Output Pin Structure

7.3.9.5 Four Level Input Pin

Figure 7-27 shows the structure of the four level input pins GAIN and SLEW on hardware interface devices. The

input can be set by tying the pin to AGND or AVDD, leaving the pin unconnected, or connecting an external

resistor from the pin to ground.

CONTROL

AVDD

STATE

V_L1

RESISTANCE

Tied to AGND

Setting-1

Setting-2

Setting-3

Setting-4

+

–

R_PU

47 k ±5%

to AGND

V_L2

V_L3

V_L4

+

–

R_PD

Hi-Z

Tied to AVDD

+

–

Figure 7-27. Four Level Input Pin Structure

34

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.3.10 Current Sense Amplifiers

The DRV8311 integrate three high-performance low-side current sense amplifiers for current measurements

using built-in current sense. Low-side current measurements are commonly used to implement overcurrent

protection, external torque control, or brushless DC commutation with the external controller. All three amplifiers

can be used to sense the current in each of the half-bridge legs (low-side MOSFETs). The current sense

amplifiers include features such as programmable gain and an external voltage reference (VREF) provided on

the pin CSAREF.

7.3.10.1 Current Sense Amplifier Operation

The SOx pin on the DRV8311 outputs an analog voltage proportional to current flowing in the low side FETs

(I_OUTx) multiplied by the gain setting (G_CSA). The gain setting is adjustable between four different levels which

can be set by the GAIN pin (hardware device variant) or the CSA_GAIN bits (SPI or tSPI device variant).

Figure 7-28 shows the internal architecture of the current sense amplifiers. The current sense is implemented

with a sense FET on each low-side FET of the DRV8311 device. This current information is converted in to a

voltage, which generates the CSA output voltage on the SOx pin, based on the voltage on the CSAREF pin

(VREF) and the gain setting. The CSA output voltage can be calculated using Equation 2

V

REF

2

SOx =

± G

× I

(2)

CSA OUTx

VM

VREF

OUTx

Sense

FET

GAIN

I/V Converter

PGND

SOx

Figure 7-28. Integrated Current Sense Amplifier

Submit Document Feedback

35

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

Figure 7-29 and Figure 7-30 show the details of the amplifier operational range. In bi-directional operation, the

amplifier output for 0-V input is set at VREF/2. Any change in the differential input results in a corresponding

change in the output times the G_CSAfactor. The amplifier has a defined linear region in which it can maintain

operation.

SOX

VREF

V

VREF

œ 0.25 V

œI_OUTx

V

SO(rangeœ)

V

SO(off)max

/ 2

V , V

OFF DRIFT

0 V

V

VREF

V

SO(off)min

V

SO(range+)

I_OUTx

0.25 V

0 V

Figure 7-29. Bidirectional Current Sense Output

SOX (V)

V_REF

V_{REF / 2}

V_LINEAR

I_OUTx(A) (Current flowing into the FET)

Figure 7-30. Bidirectional Current Sense Regions

Note

The current sense amplifers uses the externalvoltage reference (VREF) provided at the CSAREF pin.

7.3.10.2 Current Sense Amplifier Offset Correction

CSA output has an offset induced due to ground differences between the sense FET and output FET. When

running trapezoidal control or another single-shunt based control (sensored sine, for example) this CSA offset

has no impact to operation. When running sensorless sinusoidal or FOC control where two or three current

sense are required, some current distortion and noise may occur unless the user implements the corrective

action below.

Corrective Action: Implement the below equations in firmware to correct for any current induced offset:

36

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

1. When all three current sense amplifiers are used:

i = 1.001152*i

− 0.003375*i

− 0.003103*i

(3)

(4)

a

a_sensed

b_sensed

c_sensed

i = 0.002369*i

+ 1.000665*i

− 0.019126*i

b

a

b_sensed

c_sensed

+ 0.998166*i

c_sensed

sensed

i = 0.001234*i

+ 0.001595*i

(5)

c

a

b

sensed

2. When only two of the three current sense amplifiers are used:

a. Current sensed in phases A & B:

i = 1.004346*i

− 0.000199*i

(6)

(7)

a

a_sensed

b_sensed

+ 1.020405*i

b_sensed

i = 0.022060*i

b

a

sensed

i = − i + i

b

(8)

c

a

b. Current sensed in phases B & C:

i = 0.998309*i

− 0.021427*i

(9)

b

b_sensed

c_sensed

+ 0.996967*i

c_sensed

i = 0.000368*i

(10)

c

b

sensed

i = − i + i

c

(11)

a

b

c. Current sensed in phases C & A

i = 1.004547*i

+ 0.000195*i

+ 0.996975*i

c_sensed

(12)

(13)

(14)

a

c_sensed

sensed

i = 0.000371*i

c

a

sensed

i = − i + i

c

b

a

Submit Document Feedback

37

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.3.11 Protections

The DRV8311 family of devices is protected against VM, VIN_AVDD, AVDD and CP undervoltage, overcurrent

and thermal events. Table 7-6 summarizes various faults details.

Table 7-6. Fault Action and Response

FAULT

CONDITION

CONFIGURATION

REPORT

H-BRIDGE

LOGIC

RECOVERY

Automatic:

V_VM> V_{UVLO_R}

CLR_FLT, nSLEEP Reset Pulse (NPOR

bit)

VM undervoltage

(NPOR)

V_VM< V_UVLO

—

Hi-Z

Disabled

VINAVDD

undervoltage

(VINAVDD_UV)

Active

(SPI disabled)

V_VINAVDD< V_{VINAVDD_UV}

V_AVDD< V_{AVDD_UV}

V_CP< V_CPUV

—

nFAULT

Hi-Z

Configured using UVP_MODE

AVDD undervoltage

(AVDD_UV)

Active

(SPI disabled)

Charge pump

undervoltage

(CP_UV)

Active

(CSA disabled)

CSAREF

undervoltage

(CSAREF_UV)

CSAREFUV_EN= 1b

CSAREFUV_EN= 0b

OCP_MODE = 000b

nFAULT

None

Active

Configured using UVP_MODE

No Action

V_CSAREF< V_{CSAREF_UV}

Active

Hi-Z

Automatic Retry:

SLOW_TRETRY

nFAULT

Automatic Retry:

FAST_TRETRY

OCP_MODE = 001b

OCP_MODE = 010b

nFAULT

Hi-Z

Active

Overcurrent

Protection

(OCP)

I_PHASE> I_OCP

Latched:

CLR_FLT, nSLEEP Reset Pulse

OCP_MODE = 011b

OCP_MODE = 111b

SPIFLT_MODE = 0b

SPIFLT_MODE = 1b

OTW_EN = 0b

nFAULT

None

Active

No action

Automatic

No action

nFAULT

None

SPI error

(SPI_FLT)

SCLK fault and ADDR

fault

None

Thermal warning

(OTW)

T_J> T_OTW

Automatic:

T_J< T_OTW– T_HYS

OTW_EN = 1b

nFAULT

Active

Hi-Z

Active

Automatic

SLOW_TRETRY after

T_J< T_OTSD– T_HYS

OTSD_MODE = 00b

Thermal shutdown

(OTSD)

T_J> T_OTSD

Automatic

OTSD_MODE = 01b

nFAULT

Hi-Z

Active

FAST_TRETRY after

T_J< T_OTSD– T_HYS

38

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.3.11.1 VM Supply Undervoltage Lockout (NPOR)

If at any time the input supply voltage on the VM pin falls lower than the V_UVLOthreshold (VM UVLO falling

threshold), all of the integrated FETs, driver charge-pump and digital logic controller are disabled as shown in

Figure 7-31. Normal operation resumes (driver operation) when the VM undervoltage condition is removed. The

NPOR bit is reset and latched low in the device status (DEV_STS1) register once the device presumes VM. The

NPOR bit remains in reset condition until cleared through the CLR_FLT bit or an nSLEEP pin reset pulse (t_RST).

V_UVLO(max) rising

V_UVLO(min) rising

V_UVLO(max) falling

V_UVLO(min) falling

V_VM

DEVICE ON

DEVICE OFF

DEVICE ON

Time

Figure 7-31. VM Supply Undervoltage Lockout

7.3.11.2 Under Voltage Protections (UVP)

Other than VM ULVO, DRV8311 family of devices has undervoltage protections for VIN_AVDD, CSAREF, AVDD

and CP pins. VINAVDD_UV, CSAREF_UV and AVDD_UV undervoltage protections are enabled and cannot

be disabled, while CSAREF_UV is disabled by default and can be enabled in SPI variant by configuring

CSAREFUV_EN in SYSF_CTRL register.

In hardware device variants, AVDD_UV, VINAVDD_UV, CP_UV protections are enabled, while CSAREF_UV is

disabled and the t_RETRYis configured for fast automatic rety time to 5 ms.

t_RETRYconfiguration for SPI device variant for all UV protections

•

Slow retry time SLOW_TRETRY can be used for t_RETRYperiod by configuring UVP_MODE to 000b

Fast retry time FAST_TRETRY can be used for t_RETRYperiod by configuring UVP_MODE to 001b

VIN AVDD Undervoltage Protections (VINAVDD_UV)

If at any time the voltage on VIN_AVDD pin falls lower than the V_{VINAVDD_UV}threshold, all of the integrated FETs,

SPI communication is disabled, nFAULT pin is driven low, FAULT and UVP in DEV_STS1 and VINAVDD_UV

in SUP_STS1 are set high. Normal operation starts again automatically (driver operation, the nFAULT pin is

released and VINAVDD_UV bit is cleared) after VIN_AVDD pin rises above the V_{VINAVDD_UV}threshold and the

t_RETRYtime elapses. The FAULT and UVP bits stays latched high until a clear fault command is issued either

through the CLR_FLT bit or an nSLEEP reset pulse (t_RST).

AVDD Undervoltage Protections (AVDD_UV)

If at any time the voltage on AVDD pin falls lower than the V_{AVDD_UV}threshold, all of the integrated FETs,

SPI communication is disabled, nFAULT pin is driven low, FAULT and UVP in DEV_STS1 and AVDD_UV

in SUP_STS1 are set high. Normal operation starts again automatically (driver operation, the nFAULT pin is

released and AVDD_UV bit is cleared) after AVDD pin rises above the V_{AVDD_UV}threshold and the t_RETRYtime

elapses. The FAULT and UVP bits stays latched high until a clear fault command is issued either through the

CLR_FLT bit or an nSLEEP reset pulse (t_RST).

Submit Document Feedback

39

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

CSAREF Undervoltage Protections (CSAREF_UV)

If at any time the voltage on CSAREF pin falls lower than the V_{CSAREF_UV}threshold, CSAREF_UV is recognized.

CSA_UV can be enabled or disabled by configuring CSAREFUV_EN. When enabled, after CSAREF_UV

event,CSA are disabled, nFAULT pin is driven low, FAULT and UVP in DEV_STS1 and CSAREF_UV in

SUP_STS1 are set high. Normal operation starts again automatically (CSA operation, the nFAULT pin is

released and CSAREF_UV bit is cleared) after CSAREF_UV condition is cleared and the t_RETRYtime elapses.

The FAULT and UVP bits stays latched high until a clear fault command is issued either through the CLR_FLT bit

or an nSLEEP reset pulse (t_RST).

Note

CSAREF_UV is disabled in hardware variant and by default in SPI variants

CP Undervoltage Protections (CP_UV)

If at any time the voltage on CP pin falls lower than the V_{CP_UV}threshold, all of the integrated FETs and charge

pump operation is disabled, nFAULT pin is driven low, FAULT and UVP in DEV_STS1 and CP_UV in SUP_STS1

are set high. Normal operation starts again automatically (driver and charge pump operation, the nFAULT pin

is released and CP_UV bit is cleared) after CP pin rises above the the V_{CP_UV}threshold and the t_RETRYtime

elapses. The FAULT and UVP bits stays latched high until a clear fault command is issued either through the

CLR_FLT bit or an nSLEEP reset pulse (t_RST).

7.3.11.3 Overcurrent Protection (OCP)

A MOSFET overcurrent event is sensed by monitoring the current flowing through FETs. If the current across a

FET exceeds the I_OCPthreshold for longer than the t_OCPdeglitch time, a OCP event is recognized and action is

done according to the OCP_MODE bit. In order to avoid false triger of OCP during PWM trasnition due to ringing

in phase voltage, there is t_BLANKblanking time applied at each edge of PWM signals in digital. During blanking

time, OCP events are ignored.

On hardware device varaints, the I_OCPthreshold is fixed to 9A (typ), the t_{OCP_DEG}is fixed at 1-µs, t_BLANKis fixed

at 0.2-µs and the OCP_MODE bit is configured with fast retry with 5-ms automatic retry. On SPI devices, the

I_OCPthreshold is set through the OCP_LVL, the t_{OCP_DEG}is set through the OCP_DEG, the t_BLANKis set through

the OCP_TBLANK and the OCP_MODE bit can operate in four different modes: OCP latched shutdown, OCP

automatic retry with fast and slow retry times, OCP report only, and OCP disabled.

7.3.11.3.1 OCP Latched Shutdown (OCP_MODE = 010b)

After a OCP event in this mode, all MOSFETs are disabled and the nFAULT pin is driven low. The FAULT, OCP,

and corresponding FET's OCP bits are latched high in the SPI registers. Normal operation starts again (driver

operation, FAULT, OCP, and corresponding FET's OCP bits are cleared and the nFAULT pin is released) when

the OCP condition clears and a clear faults command is issued either through the CLR_FLT bit or an nSLEEP

reset pulse (t_RST).

40

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

Peak Current due

to deglitch time

I_OCP

I_OUTx

t_OCP

nFAULT Released

nFAULT Pulled High

Fault Condition

nFAULT

Clear Fault

Time

Figure 7-32. Overcurrent Protection - Latched Shutdown Mode

7.3.11.3.2 OCP Automatic Retry (OCP_MODE = 000b or 001b)

After a OCP event in this mode, all the FETs are disabled and the nFAULT pin is driven low. The FAULT, OCP,

and corresponding FET's OCP bits are set high in the SPI registers. Normal operation starts again automatically

(driver operation, the nFAULT pin is released and corresponding FET's OCP bits are cleared) after the t_RETRY

time elapses. The FAULT and OCP stays latched high until clear faults command is issued either through the

CLR_FLT bit or an nSLEEP reset pulse (t_RST).

t_RETRYconfiguration

•

Slow retry time SLOW_TRETRY can be used for t_RETRYperiod by configuring OCP_MODE to 000b

Fast retry time FAST_TRETRY can be used for t_RETRYperiod by configuring OCP_MODE to 001b

Peak Current due

to deglitch time

I_OCP

I_OUTx

t_RETRY

t_OCP

nFAULT Released

nFAULT Pulled High

Fault Condition

nFAULT

Time

Figure 7-33. Overcurrent Protection - Automatic Retry Mode

Submit Document Feedback

41

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.3.11.3.3 OCP Report Only (OCP_MODE = 011b)

No protective action occurs after a OCP event in this mode. The overcurrent event is reported by driving the

nFAULT pin low and setting the FAULT, OCP, and corresponding FET's OCP bits high in the SPI registers.

DRV8311 continue to operate as usual. The external controller manages the overcurrent condition by acting

appropriately. The reporting clears (nFAULT pin is released, FAULT, OCP, and corresponding FET's OCP bits are

cleared) when the OCP condition clears and a clear faults command is issued either through the CLR_FLT bit or

an nSLEEP reset pulse (t_RST).

7.3.11.3.4 OCP Disabled (OCP_MODE = 111b)

No action occurs after a OCP event in this mode.

7.3.11.4 Thermal Protections

DRV8311 family of devices has over temperature warning (OTW) and over temperature shutdown (OTSD) for

over temperature events.

7.3.11.4.1 Thermal Warning (OTW)

If the die temperature exceeds the trip point of the thermal warning (T_OTW), the OT bit in the device status

(DEV_STS1) register and OTW bit in the OT_STS status register is set. The reporting of OTW on the nFAULT

pin can be enabled by setting the over-temperature warning reporting (OTW_EN) bit in the configuration control

register. The device performs no additional action and continues to function. In this case, the nFAULT pin

releases and OTW bit cleared when the die temperature decreases below the hysteresis point of the thermal

warning (T_{OTW_HYS}). The OT bit remains latched until cleared through the CLR_FLT bit or an nSLEEP reset

pulse (t_RST) and the die temperature is lower than thermal warning trip (T_OTW).

In hardware device variants, Over Temperature warning is not reported on nFAULT pin by default.

7.3.11.4.2 Thermal Shutdown (OTSD)

If the die temperature exceeds the trip point of the thermal shutdown limit (T_OTS), all the FETs are disabled, the

charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and OT bit in the OT bit

in the device status (DEV_STS1) register and OTSD bit in the OT_STS status register is set. Normal operation

starts again (driver operation the nFAULT pin is released and OTSD bit cleared) when the overtemperature

condition clears and after the t_RETRYtime elapses. The OT and FAUTL bits stays latched high indicating that a

thermal event occurred until a clear fault command is issued either through the CLR_FLT bit or an nSLEEP reset

pulse (t_RST). This protection feature cannot be disabled.

On hardware device variants the t_RETRYperios is fixed to fast retry time of 5ms

t_RETRYconfiguration for SPI device variant

•

Slow retry time SLOW_TRETRY can be used for t_RETRYperiod by configuring OTSD_MODE to 00b

Fast retry time FAST_TRETRY can be used for t_RETRYperiod by configuring OTSD_MODE to 01b

42

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.4 Device Functional Modes

7.4.1 Functional Modes

7.4.1.1 Sleep Mode

The nSLEEP pin manages the state of the DRV8311 family of devices. When the nSLEEP pin is low, the device

goes to a low-power sleep mode. In sleep mode, all FETs are disabled, sense amplifiers are disabled, buck

regualtor (if present) is disabled, the charge pump is disabled, the AVDD regulator is disabled, and the SPI bus

is disabled. The t_SLEEPtime must elapse after a falling edge on the nSLEEP pin before the device goes to sleep

mode. The device comes out of sleep mode automatically if the nSLEEP pin is pulled high. The t_WAKEtime must

elapse before the device is ready for inputs.

In sleep mode and when V_VM< V_UVLO, all MOSFETs are disabled.

Note

During power up and power down of the device through the nSLEEP pin, the nFAULT pin is held low

as the internal regulators are enable or disable. After the regulators have enabled or disabled, the

nFAULT pin is automatically released. The duration that the nFAULT pin is low does not exceed the

t_SLEEPor t_WAKEtime.

7.4.1.2 Operating Mode

When the nSLEEP pin is high and the V_VMvoltage is greater than the V_UVLOvoltage, the device goes to

operating mode. The t_WAKEtime must elapse before the device is ready for inputs. In this mode the charge

pump, AVDD regulator, Buck Regulator and SPI bus are active.

7.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)

In the case of device latched faults, the DRV8311 family of devices goes to a partial shutdown state to help

protect the power MOSFETs and system.

When the fault condition clears, the device can go to the operating state again by either setting the CLR_FLT

SPI bit on SPI devices or issuing a reset pulse to the nSLEEP pin on either interface variant. The nSLEEP

reset pulse (t_RST) consists of a high-to-low-to-high transition on the nSLEEP pin. The low period of the sequence

should fall with the t_RSTtime window or else the device will start the complete shutdown sequence. The reset

pulse has no effect on any of the regulators, device settings, or other functional blocks

Submit Document Feedback

43

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

7.5 SPI Communication

7.5.1 Programming

7.5.1.1 SPI and tSPI Format

SPI Format - with Parity

The SDI input data word is 24 bits long and consists of the following format:

•

1 read or write bit, W (bit B23)

6 address bits, A (bits B22 through B17)

Parity bit, P (bit B16)

15 data bits with 1 parity bit, D (bits B15 through B0)

The SDO output data word is 24 bits long. The first 8 bits are status bits and the last 16 bits are the data content

of the register being accessed.

Table 7-7. SDI Input Data Word Format for SPI

PAR PAR

R/W

ADDRESS

DATA

ITY ITY

B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

W0 A5 A4 A3 A2 A1 A0

P

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table 7-8. SDO Output Data Word Format

STATUS

DATA

B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

S7 S6 S5 S4 S3 S2 S1 S0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

tSPI Format - with Parity

The SDI input data word is 32 bits long and consists of the following format:

•

1 read or write bit, W (bit B31)

4 secondary device ID bits, AD (bits B30 through B27)

8 address bits, A (bits B26 through B19)

2 reserved bits, 0 (bits B18, bit B17)

Parity bit, P (bit B16)

15 data bits with 1 parity bit, D (bits B15 through B0)

The SDO output data word is 24 bits long. The first 8 bits are status bits and the last 16 bits are the data content

of the register being accessed. The format is same as standard SPI shown in Table 7-8

Table 7-9. tSPI with Parity - SDI Input Data Word Format

R/W

B31

W0

Secondary device ID

ADDRESS

00

PARITY PARITY

DATA

B30

0

B29

0

B28

AD1

B27 B26 - B19 B18

B17

0

B16

P

B15

P

B14 - B0

D14 - D0

AD0

A7 - A0

0

The details of the bits used in SPI and tSPI frame format are detailed below.

Read/Write Bit (R/W) : R/W (W0) bit being 0 indicates a SPI/tSPI Write transaction. For a read operation RW bit

needs to be 1.

Secondary device ID Bits (AD) : Each tSPI secondary device on the same chip select should have a unique

identifier. Secondary device ID field is the 4-bit unique identifier of the tSPI secondary device. For a successful

Read/Write transaction the secondary device ID field should match with the secondary device address. In

DRV8311 the two most significant bits of secondary device addresses are set to 00. The least two significant

bits of the secondary device address can be configured using the AD1 and AD0 pins. The secondary device

address 15 (0xF) is reserved for general call, all the devices on the same bus accept a write operation when

44

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

the secondary device ID field is set to 15. Hence the valid tSPI secondary device addresses for DRV8311 range

from 0 to 3 and 15 (general call address).

Address Bits (A) : A tSPI secondary device takes 8-bit register address whereas SPI secondary device

takes 6-bit register address. Each tSPI secondary device has two dedicated 8-bit address pointers, one for

read and one for write. During a sequential read transaction, the read address pointer gets incremented

automatically.During a sequential write transaction, both write address pointer and read address pointer will

be incremented automatically.

Parity Bit (P) : Both header and data fields of a SPI/tSPI input data frame include a parity bit for single bit error

detection. The parity scheme used is even parity i.e., the number of ones in a block of 16-bits (including the

parity bit) is even. Data will be written to the internal registers only if the parity check is successful. During a read

operation, the tSPI secondary device inserts a parity bit at the MSB of read data. Parity checks can be enabled

or disabled by configuring the SPI_PEN bit of SYS_CTRL register. Parity checks are disabled by default.

Note

Though parity checks are disabled by default, TI recommends enabling parity checks to safeguard

against single-bit errors.

Error Handling

Parity Error: Upon detecting a parity error, the secondary device responds in the following ways. Parity error

gets latched and reported on nFAULT. The error status is available for read on SPI_PARITY field of SYS_STS

register. A parity error in the header will not prevent the secondary device from responding with data. The

SDO will be driven by the secondary device being addressed. Updates to write address pointer and the device

registers will be ignored when parity error is detected. In a sequential write, upon detection of parity error any

subsequent register writes will be ignored.

Frame Error :Any incomplete tSPI Frame will be reported as Frame error. If the number of tSPI clock cycles is

not a multiple of 16, then the transfer is considered to be incomplete. Frame errors will be latched in FRM_ERR

field of SYS_STS register and indicated on nFAULT.

SPI Read / Write Sequence

SPI Read Sequence: The SPI read transaction comprises of an 8-bit header (R/W - 1 bit, Address - 6 bits,

and party -1 bit) followed by 16-bit dummy data words. Upon receiving the first byte of header, the secondary

device responds with an 8-bit device status information. The read address pointer gets updated immediately

after receiving the address field of the header. The read address from the header acts as the starting address for

the register reads. The read address pointer gets incremented automatically upon completion of a 16-bit transfer.

The length of data transfer is not restricted by the secondary device. The secondary device responds with data

as long as the primary device transmits dummy words. If parity error check is enabled, the MSB of read data will

be replaced with computed parity bit

SPI Write Sequence: SPI write transaction comprises of an 8-bit header followed by 16-bit data words to be

written into the register bank. Similar to a read transaction, the addressed secondary device responds with an

8-bit device status information upon receiving the first byte of header. Once the header bytes are received,

the write address pointer gets updated. The write address from the header acts as the starting address for

sequential register writes. The read address pointer will retain the address of the register being read in the

previous tSPI transaction. The length of data transfer is not restricted by the secondary device. Both read and

write address pointers will be incremented automatically upon completion of a 16-bit transfer. While receiving

data from the primary device, the SDO will be driven with the register data addressed by read address pointer.

tSPI Communication Sequence

The tSPI interface is similar to regular SPI interface in functionality but add support for multiple devices under

the same Chip Select (nSCS). Any existing SPI primary device would be able to communicate with the tSPI

secondary devices with modifications in the frame format.A valid tSPI frame must meet the following conditions

(similar to SPI interface):

Submit Document Feedback

45

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

•

The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high. A high to

low transition at the nSCS pin is the start of frame and a low to high transition is the end of the frame.

When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is

placed in the Hi-Z state.

Data is captured on the falling edge of the SCLK signal and data is driven on the rising edge of the SCLK

signal.

•

The most significant bit (MSB) is shifted in and out first.

A minimum of 16 SCLK cycles must occur for transaction to be valid & the number of SCLK cycles in a single

transaction must me a multiple of 16.

•

If the data word sent to the SDI pin is not a multiple of 16 bits, a frame error occurs and the excess SCLK

cycles are ignored.

AD0 AD1

nSCS

SCLK

SDI

CS

MCLK

MO

DEVICE-1

SDO

AD0 AD1

nSCS

SCLK

SDI

DEVICE-2

MCU

AD0 AD1

nSCS

SCLK

SDI

DEVICE-3

MI

Figure 7-34. tSPI Block Diagram with Multiple Devices on Same Chip Select

46

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

AD0 AD1

nSCS

SCLK

SDI

CS

MCLK

MO

SDO

DEVICE-1

PWM_SYN

SOB SOC

SOA

PWM

ADC1

ADC2

ADC3

AD0 AD1

nSCS

SCLK

SDI

SDO

DEVICE-2

PWM_SYN

SOA

MCU

ADC1

ADC2

ADC3

AD0 AD1

nSCS

SCLK

SDI

SDO

DEVICE-3

PWM_SYN

SOA

ADC1

ADC2

ADC3

MI

Figure 7-35. tSPI with PWM_SYNC

tSPI Read Sequence: A tSPI read transaction has a 16-bit header (R/W - 1 bit, Secondary device ID - 4 bits,

Address - 8 bits, reserved -2 bits and party -1 bit) followed by 16-bit dummy data words. Upon receiving the first

byte of header, the secondary device being addressed with matching secondary device ID field (configured using

AD0 and and AD1 pins), responds with an 8-bit device status information. The read address from the header

acts as the starting address for the register reads. The address gets incremented automatically upon completion

of a 16-bit transfer. The length of data transfer is not restricted by the secondary device. The secondary device

responds with data as long as the primary device transmits dummy words. If parity error check is enabled, the

MSB of read data will be replaced with computed parity bit.

tSPI Write Sequence: A tSPI write transaction has a 16-bit header followed by 16-bit data words to be written

into the register bank. Similar to a read transaction, the addressed secondary device responds with an 8-bit

device status information upon receiving the first byte of header. The write address from the header acts as

the starting address for sequential register writes. The length of data transfer is not restricted by the secondary

device. Both write and read address pointers will be incremented automatically upon completion of a 16-bit

transfer. While receiving data from the primary device, the SDO will be driven with the register data addressed

by read address pointer

tSPI Read Address Update Sequence: The independent read and write address pointers in the secondary

device would allow reading data from one set of registers while writing data to another set of registers. To

achieve this, the primary device should first send a read address update frame before the tSPI write transaction.

A read address frame is nothing but just the tSPI read sequence with just the header. The first tSPI transaction

Submit Document Feedback

47

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

updates the read address pointer to desired register address. The second tSPI transaction is a register write

sequence. During this sequence, the data send on SDO by the secondary device will be from the register

pointed by read address pointer which was initialised in the previous tSPI read sequence.

The tSPI read/write sequence with parity is shown in Figure 7-36. The SPI frame header is marked as

CMD[15:8] and CMD[7:0].

Read address update

SPI_PEN=0, R/W=1

CMD[15:8]

CMD[7:0]

DEV_STS

Single Read – 16-bit

CMD[15:8]

SPI_PEN=0, R/W=1

DUMMY

CMD[7:0]

DEV_STS

RDATA[15:0]

Single Write with parity -16-bit

CMD[15:8]

SPI_PEN=0, R/W=0

CMD[7:0]

DEV_STS

P

WDATA[15:0]

RDATA[15:0]

Multi-Write with parity – 2x16-bit

CMD[15:8] CMD[7:0]

DLEN=0, CE=1, R/W =0

WDATA0[15:0]

P

WDATA1[15:0]

DEV_STS

RDATA0[15:0]

RDATA1[15:0]

Multi-Write with parity – 3x16-bit

CMD[15:8] CMD[7:0]

DLEN=1, CE=1, R/W =0

WDATA0[15:0]

RDATA0[15:0]

WDATA1[15:0]

RDATA1[15:0]

P

WDATA2[15:0]

RDATA2[15:0]

DEV_STS

Multi-Write with parity – 4x16-bit

DLEN=2, CE=1, R/W =0

CMD[15:8]

CMD[7:0]

P

WDATA0[15:0]

RDATA0[15:0]

WDATA1[15:0]

RDATA1[15:0]

P

WDATA2[15:0]

RDATA2[15:0]

P

WDATA3[15:0]

RDATA3[15:0]

DEV_STS

Figure 7-36. tSPI Read/Write with Partiy

48

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8 DRV8311 Registers

DRV8311 Registers lists the memory-mapped registers for the DRV8311 registers. All register offset addresses

not listed in DRV8311 Registers should be considered as reserved locations and the register contents should not

be modified.

Table 8-1. DRV8311 Registers

Offset Acronym

Register Name

Section

0h

4h

DEV_STS1

Device Status 1 Register

Over Temperature Status Register

Supply Status Register

Section 8.1

Section 8.2

Section 8.3

Section 8.4

Section 8.5

Section 8.6

Section 8.7

Section 8.8

Section 8.9

Section 8.10

Section 8.11

Section 8.12

Section 8.13

Section 8.14

Section 8.15

Section 8.16

Section 8.17

Section 8.18

Section 8.19

Section 8.20

Section 8.21

OT_STS

5h

SUP_STS

6h

DRV_STS

Driver Status Register

7h

SYS_STS

System Status Register

PWM Sync Period Register

Fault Mode Register

Ch

PWM_SYNC_PRD

FLT_MODE

10h

12h

13h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

20h

22h

23h

3Fh

SYSF_CTRL

DRVF_CTRL

FLT_TCTRL

FLT_CLR

System Fault Control Register

Drviver Fault Control Register

Fault Timing Control Register

Fault Clear Register

PWMG_PERIOD

PWMG_A_DUTY

PWMG_B_DUTY

PWMG_C_DUTY

PWM_STATE

PWMG_CTRL

PWM_CTRL1

DRV_CTRL

PWM_GEN Period Register

PWM_GEN A Duty Register

PWM_GEN B Duty Register

PWM_GEN C Duty Register

PWM State Register

PWM_GEN Control Register

PWM Control Register 1

Predriver control Register

CSA Control Register

CSA_CTRL

SYS_CTRL

System Control Register

Complex bit access types are encoded to fit into small table cells. DRV8311 Access Type Codes shows the

codes that are used for access types in this section.

Table 8-2. DRV8311 Access Type Codes

Access Type

Code

Description

Read Type

R

Read

R-0

R

Read

-0

Returns 0s

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default

value

Submit Document Feedback

49

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.1 DEV_STS1 Register (Offset = 0h) [Reset = 0080h]

DEV_STS1 is shown in DEV_STS1 Register and described in DEV_STS1 Register Field Descriptions.

Return to the DRV8311 Registers.

Device Status 1 Register

Figure 8-1. DEV_STS1 Register

15

14

13

12

11

10

9

8

Parity_bit

R-0h

RESERVED

R-0-0h

OTP_FLT

R-0h

7

6

5

4

3

2

1

0

RESET

R-1h

SPI_FLT

R-0h

OCP

R-0h

RESERVED

R-0h

UVP

R-0h

OT

FAULT

R-0h

Table 8-3. DEV_STS1 Register Field Descriptions

Bit

15

Field

Type

Reset

Description

Parity_bit

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-9

8

RESERVED

OTP_FLT

R-0

R

0h

OTP read fault

0h = No OTP read fault is detected

1h = OTP read fault detected

7

6

5

RESET

SPI_FLT

OCP

R

1h

0h

Supply Power On Reset Status

0h = No power on reset condition is detected

1h = Power-on-reset condition is detected

SPI Fault Status

0h = No SPI communication fault is detected

1h = SPI communication fault is detected

Driver Overcurrent Protection Status

0h = No overcurrent condition is detected

1h = Overcurrent condition is detected

4-3

2

RESERVED

UVP

R

0h

Reserved

Supply Undervoltage Status

0h = No undervoltage voltage condition is detected on CP, AVDD or

VIN_AVDD

1h = Undervoltage voltage condition is detected on CP, AVDD or

VIN_AVDD

1

0

OT

R

0h

Overtemperature Fault Status

0h = No overtemperature warning / shutdown is detected

1h = Overtemperature warning / shutdown is detected

FAULT

Device Fault Status

0h = No fault condition is detected

1h = Fault condition is detected

50

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.2 OT_STS Register (Offset = 4h) [Reset = 0000h]

OT_STS is shown in OT_STS Register and described in OT_STS Register Field Descriptions.

Return to the DRV8311 Registers.

Over Temperature Status Register

Figure 8-2. OT_STS Register

15

14

6

13

12

11

10

9

8

Parity_bit

R-0h

RESERVED

R-0-0h

7

5

4

3

2

1

0

RESERVED

R-0-0h

OTS_AVDD

R-0h

OTW

R-0h

OTSD

R-0h

Table 8-4. OT_STS Register Field Descriptions

Bit

15

Field

Type

Reset

Description

Parity_bit

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-3

2

RESERVED

OTS_AVDD

R-0

R

0h

AVDD LDO Overtemperature Fault Status

0h = No overtemperature shutdown near AVDD is detected

1h = Overtemperature shutdown near AVDD is detected

1

0

OTW

R

0h

Overtemperature Warning Status

0h = No overtemperature warning is detected

1h = Overtemperature warning is detected

OTSD

Overtemperature Shutdown Fault Status

0h = No overtemperature shutdown is detected

1h = Overtemperature shutdown is detected

Submit Document Feedback

51

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.3 SUP_STS Register (Offset = 5h) [Reset = 0000h]

SUP_STS is shown in SUP_STS Register and described in SUP_STS Register Field Descriptions.

Return to the DRV8311 Registers.

Supply Status Register

Figure 8-3. SUP_STS Register

15

14

6

13

12

11

10

9

8

Parity_bit

R-0h

RESERVED

R-0-0h

7

5

4

3

2

1

0

RESERVED

CSAREF_UV

R-0h

CP_UV

R-0h

RESERVED

R-0-0h

AVDD_UV

R-0h

RESERVED

R-0-0h

VINAVDD_UV

R-0h

R-0-0h

Table 8-5. SUP_STS Register Field Descriptions

Bit

15

Field

Type

Reset

Description

Parity_bit

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-6

5

RESERVED

CSAREF_UV

R-0

R

0h

CSA REF Undervoltage Fault Status

0h = No CSAREF undervoltage is detected

1h = CSAREF undervoltage is detected

4

CP_UV

R

0h

Charge Pump Undervoltage Fault Status

0h = No charge pump undervoltage is detected

1h = Charge pump undervoltage is detected

3

2

RESERVED

AVDD_UV

R-0

R

0h

Reserved

AVDD LDO Undervoltage Fault Status

0h = No AVDD ouput undervoltage is detected

1h = AVDD ouput undervoltage is detected

1

0

RESERVED

R-0

R

0h

Reserved

VINAVDD_UV

VIN_AVDD Undervoltage Fault Status

0h = No AVDD supply input undervoltage is detected

1h = AVDD supply input undervoltage is detected

52

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.4 DRV_STS Register (Offset = 6h) [Reset = 0000h]

DRV_STS is shown in DRV_STS Register and described in DRV_STS Register Field Descriptions.

Return to the DRV8311 Registers.

Driver Status Register

Figure 8-4. DRV_STS Register

15

14

13

12

11

10

9

8

Parity_bit

R-0h

RESERVED

R-0-0h

7

6

5

4

3

2

1

0

RESERVED

R-0-0h

OCPC_HS

R-0h

OCPB_HS

R-0h

OCPA_HS

R-0h

RESERVED

R-0-0h

OCPC_LS

R-0h

OCPB_LS

R-0h

OCPA_LS

R-0h

Table 8-6. DRV_STS Register Field Descriptions

Bit

15

Field

Parity_bit

Type

Reset

Description

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-7

6

RESERVED

OCPC_HS

R-0

R

0h

Overcurrent Status on High-side MOSFET of OUTC

0h = No overcurrent detected on high-side MOSFET of OUTC

1h = Overcurrent detected on high-side MOSFET of OUTC

5

4

OCPB_HS

OCPA_HS

R

0h

Overcurrent Status on High-side MOSFET of OUTB

0h = No overcurrent detected on high-side MOSFET of OUTB

1h = Overcurrent detected on high-side MOSFET of OUTB

Overcurrent Status on High-side MOSFET of OUTA

0h = No overcurrent detected on high-side MOSFET of OUTA

1h = Overcurrent detected on high-side MOSFET of OUTA

3

2

RESERVED

OCPC_LS

R-0

R

0h

Reserved

Overcurrent Status on Low-side MOSFET of OUTC

0h = No overcurrent detected on low-side MOSFET of OUTC

1h = Overcurrent detected on low-side MOSFET of OUTC

1

0

OCPB_LS

OCPA_LS

R

0h

Overcurrent Status on Low-side MOSFET of OUTB

0h = No overcurrent detected on low-side MOSFET of OUTB

1h = Overcurrent detected on low-side MOSFET of OUTB

Overcurrent Status on Low-side MOSFET of OUTA

0h = No overcurrent detected on low-side MOSFET of OUTA

1h = Overcurrent detected on low-side MOSFET of OUTA

Submit Document Feedback

53

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.5 SYS_STS Register (Offset = 7h) [Reset = 0000h]

SYS_STS is shown in SYS_STS Register and described in SYS_STS Register Field Descriptions.

Return to the DRV8311 Registers.

System Status Register

Figure 8-5. SYS_STS Register

15

14

13

5

12

11

10

9

8

Parity_bit

R-0h

RESERVED

R-0-0h

7

6

4

3

2

1

0

RESERVED

R-0-0h

OTPLD_ERR

R-0h

RESERVED

R-0-0h

SPI_PARITY

R-0h

BUS_CNT

R-0h

FRM_ERR

R-0h

Table 8-7. SYS_STS Register Field Descriptions

Bit

15

Field

Type

Reset

Description

Parity_bit

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-5

4

RESERVED

OTPLD_ERR

R-0

R

0h

OTP Read Error

0h = No OTP read error is detected

1h = OTP read error is detected

3

2

RESERVED

SPI_PARITY

R-0

R

0h

Reserved

SPI Parity Error

0h = No SPI Parity Error is detected

1h = SPI Parity Error is detected

1

0

BUS_CNT

FRM_ERR

R

0h

SPI Bus Contention Error

0h = No SPI Bus Contention Error is detected

1h = SPI Bus Contention Error is detected

SPI Frame Error

0h = No SPI Frame Error is detected

1h = SPI Frame Error is detected

54

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.6 PWM_SYNC_PRD Register (Offset = Ch) [Reset = 0000h]

PWM_SYNC_PRD is shown in PWM_SYNC_PRD Register and described in PWM_SYNC_PRD Register Field

Descriptions.

Return to the DRV8311 Registers.

PWM Sync Period Register

Figure 8-6. PWM_SYNC_PRD Register

15

14

13

12

11

10

9

8

0

Parity_bit

R-0h

RESERVED

R-0-0h

PWM_SYNC_PRD

R-0h

7

6

5

4

3

2

1

PWM_SYNC_PRD

R-0h

Table 8-8. PWM_SYNC_PRD Register Field Descriptions

Bit

15

Field

Type

Reset

Description

Parity_bit

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-12

11-0

RESERVED

R-0

R

0h

PWM_SYNC_PRD

0h

12-bit output indicating period of PWM_SYNC signal

Submit Document Feedback

55

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.7 FLT_MODE Register (Offset = 10h) [Reset = 0000h]

FLT_MODE is shown in FLT_MODE Register and described in FLT_MODE Register Field Descriptions.

Return to the DRV8311 Registers.

Fault Mode Register

Figure 8-7. FLT_MODE Register

15

14

6

13

12

11

10

2

9

1

8

Parity_bit

RESERVED

R-0-0h

OTPFLT_MOD

E

R-0h

R/W-0h

0

7

5

4

3

SPIFLT_MODE

R/W-0h

OCP_MODE

R/W-0h

UVP_MODE

R/W-0h

OTSD_MODE

R/W-0h

Table 8-9. FLT_MODE Register Field Descriptions

Bit

15

Field

Parity_bit

Type

Reset

Description

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-9

8

RESERVED

R-0

R/W

0h

OTPFLT_MODE

0h

System Fault Mode.

0h = OTP read fault is enabled

1h = OTP read fault is disabled

7

SPIFLT_MODE

OCP_MODE

R/W

0h

SPI Fault mode

0h = SPI Fault is enabled

1h = SPI Fault is disabled

6-4

Overcurrent Protection Fault mode

0h = Report on nFault, predriver HiZ, auto recovery with Slow Retry

time (in ms)

1h = Report on nFault, predriver HiZ, auto recovery with Fast Retry

time (in ms)

2h = Report on nFault, predriver HiZ, Latched Fault

3h = Report on nFault, No action on predriver

4h = Reserved

5h = Reserved

6h = Reserved

7h = Disabled

3-2

UVP_MODE

R/W

0h

Undervoltage Protection Fault mode

0h = Report on nFault, predriver HiZ, auto recovery with Slow Retry

time (in ms)

1h = Report on nFault, redriver HiZ, auto recovery with Fast Retry

time (in ms)

2h = Reserved

3h = Reserved

1-0

OTSD_MODE

R/W

0h

Overtemperature Fault mode

0h = Report on nFault, predriver HiZ, auto recovery with Slow Retry

time (in ms)

1h = Report on nFault, predriver HiZ, auto recovery with Fast Retry

time (in ms)

2h = Reserved

3h = Reserved

56

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.8 SYSF_CTRL Register (Offset = 12h) [Reset = 0735h]

SYSF_CTRL is shown in SYSF_CTRL Register and described in SYSF_CTRL Register Field Descriptions.

Return to the DRV8311 Registers.

System Fault Control Register

Figure 8-8. SYSF_CTRL Register

15

14

6

13

12

11

10

9

8

Parity_bit

R-0h

RESERVED

R-0-0h

OTAVDD_EN

R/W-1h

OTW_EN

R/W-1h

RESERVED

R-0-4h

7

5

4

3

2

1

0

RESERVED

CSAVREFUV_

EN

RESERVED

R-0-4h

R/W-1h

R-0-0h

R/W-1h

R-0-0h

R/W-1h

Table 8-10. SYSF_CTRL Register Field Descriptions

Bit

15

Field

Type

Reset

Description

Parity_bit

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-11

10

RESERVED

OTAVDD_EN

R-0

R/W

0h

1h

AVDD Overtemperature Fault Enable

0h = Overtemperature protection near AVDD is disabled

1h = Overtemperature protection near AVDD is enabled

9

OTW_EN

R/W

1h

Overtemperature Warning Fault Enable

0h = Over temperature warning reporting on nFAULT is disabled

1h = Over temperature warning reporting on nFAULT is enabled

8-6

5

RESERVED

R-0

4h

1h

Reserved

CSAVREFUV_EN

R/W

CSAREF Undervoltage Fault Enable

0h = CSAREF undervoltage lockout is disabled

1h = CSAREF undervoltage lockout is enabled

4

3

2

1

0

RESERVED

R/W

R-0

1h

0h

1h

0h

1h

Reserved

R/W

R-0

R/W

Submit Document Feedback

57

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.9 DRVF_CTRL Register (Offset = 13h) [Reset = 0000h]

DRVF_CTRL is shown in DRVF_CTRL Register and described in DRVF_CTRL Register Field Descriptions.

Return to the DRV8311 Registers.

Drviver Fault Control Register

Figure 8-9. DRVF_CTRL Register

15

14

6

13

5

12

11

10

2

9

8

Parity_bit

R-0h

RESERVED

R-0-0h

7

4

3

1

0

RESERVED

OCP_DEG

R/W-0h

OCP_TBLANK

R/W-0h

RESERVED

R-0-0h

OCP_LVL

R/W-0h

R-0-0h

Table 8-11. DRVF_CTRL Register Field Descriptions

Bit

15

Field

Type

Reset

Description

Parity_bit

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-6

5-4

RESERVED

OCP_DEG

R-0

R/W

0h

OCP Deglitch time

0h = OCP deglitch time is 0.2 µs

1h = OCP deglitch time is 0.5 µs

2h = OCP deglitch time is 0.8 µs

3h = OCP deglitch time is 1 µs

3-2

OCP_TBLANK

R/W

0h

OCP Blanking time

0h = OCP blanking time is 0.2 µs

1h = OCP blanking time is 0.5 µs

2h = OCP blanking time is 0.8 µs

3h = OCP blanking time is 1 µs

1

0

RESERVED

OCP_LVL

R-0

0h

Reserved

R/W

OCP Level Settings

0h = OCP level is 9 A (TYP)

1h = OCP level is 5 A (TYP)

58

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.10 FLT_TCTRL Register (Offset = 16h) [Reset = 0005h]

FLT_TCTRL is shown in FLT_TCTRL Register and described in FLT_TCTRL Register Field Descriptions.

Return to the DRV8311 Registers.

Fault Timing Control Register

Figure 8-10. FLT_TCTRL Register

15

14

6

13

5

12

11

10

9

1

8

0

Parity_bit

R-0h

RESERVED

R-0-0h

7

4

3

2

RESERVED

R-0-0h

SLOW_TRETRY

R/W-1h

FAST_TRETRY

R/W-1h

Table 8-12. FLT_TCTRL Register Field Descriptions

Bit

15

Field

Type

Reset

Description

Parity_bit

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-4

3-2

RESERVED

R-0

R/W

0h

SLOW_TRETRY

1h

Slow Recovery Retry Time from Fault Condition

0h = 0.5s

1h = 1s

2h = 2s

3h = 5s

1-0

FAST_TRETRY

R/W

1h

Fast Recovery Retry Time from Fault Condition

0h = 0.5ms

1h = 1ms

2h = 2ms

3h = 5ms

Submit Document Feedback

59

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.11 FLT_CLR Register (Offset = 17h) [Reset = 0000h]

FLT_CLR is shown in FLT_CLR Register and described in FLT_CLR Register Field Descriptions.

Return to the DRV8311 Registers.

Fault Clear Register

Figure 8-11. FLT_CLR Register

15

14

6

13

5

12

11

10

2

9

1

8

Parity_bit

R-0h

RESERVED

R-0-0h

7

4

3

0

RESERVED

R-0-0h

FLT_CLR

W-0h

Table 8-13. FLT_CLR Register Field Descriptions

Bit

15

Field

Type

Reset

Description

Parity_bit

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-1

0

RESERVED

FLT_CLR

R-0

W

0h

Clear Fault

0h = No clear fault command is issued

1h = To clear the latched fault bits. This bit automatically resets after

being written.

60

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.12 PWMG_PERIOD Register (Offset = 18h) [Reset = 0000h]

PWMG_PERIOD is shown in PWMG_PERIOD Register and described in PWMG_PERIOD Register Field

Descriptions.

Return to the DRV8311 Registers.

PWM_GEN Period Register

Figure 8-12. PWMG_PERIOD Register

15

14

13

12

11

10

PWM_PRD_OUT

R/W-0h

9

8

0

Parity_bit

R-0h

RESERVED

R-0-0h

7

6

5

4

3

2

1

PWM_PRD_OUT

R/W-0h

Table 8-14. PWMG_PERIOD Register Field Descriptions

Bit

15

Field

Type

Reset

Description

Parity_bit

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-12

11-0

RESERVED

R-0

R/W

0h

PWM_PRD_OUT

0h

12-bit Period for output PWM signals in PWM Generation Mode

Submit Document Feedback

61

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.13 PWMG_A_DUTY Register (Offset = 19h) [Reset = 0000h]

PWMG_A_DUTY is shown in PWMG_A_DUTY Register and described in PWMG_A_DUTY Register Field

Descriptions.

Return to the DRV8311 Registers.

PWM_GEN A Duty Register

Figure 8-13. PWMG_A_DUTY Register

15

14

13

12

11

10

9

8

0

Parity_bit

R-0h

RESERVED

R-0-0h

PWM_DUTY_OUTA

R/W-0h

7

6

5

4

3

2

1

PWM_DUTY_OUTA

R/W-0h

Table 8-15. PWMG_A_DUTY Register Field Descriptions

Bit

15

Field

Type

Reset

Description

Parity_bit

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-12

11-0

RESERVED

R-0

R/W

0h

PWM_DUTY_OUTA

0h

12-bit Duty Cycle for Phase A output in PWM Generation Mode

62

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.14 PWMG_B_DUTY Register (Offset = 1Ah) [Reset = 0000h]

PWMG_B_DUTY is shown in PWMG_B_DUTY Register and described in PWMG_B_DUTY Register Field

Descriptions.

Return to the DRV8311 Registers.

PWM_GEN B Duty Register

Figure 8-14. PWMG_B_DUTY Register

15

14

13

12

11

10

9

8

0

Parity_bit

R-0h

RESERVED

R-0-0h

PWM_DUTY_OUTB

R/W-0h

7

6

5

4

3

2

1

PWM_DUTY_OUTB

R/W-0h

Table 8-16. PWMG_B_DUTY Register Field Descriptions

Bit

15

Field

Type

Reset

Description

Parity_bit

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-12

11-0

RESERVED

R-0

R/W

0h

PWM_DUTY_OUTB

0h

12-bit Duty Cycle for Phase B output in PWM Generation Mode

Submit Document Feedback

63

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.15 PWMG_C_DUTY Register (Offset = 1Bh) [Reset = 0000h]

PWMG_C_DUTY is shown in PWMG_C_DUTY Register and described in PWMG_C_DUTY Register Field

Descriptions.

Return to the DRV8311 Registers.

PWM_GEN C Duty Register

Figure 8-15. PWMG_C_DUTY Register

15

14

13

12

11

10

9

8

0

Parity_bit

R-0h

RESERVED

R-0-0h

PWM_DUTY_OUTC

R/W-0h

7

6

5

4

3

2

1

PWM_DUTY_OUTC

R/W-0h

Table 8-17. PWMG_C_DUTY Register Field Descriptions

Bit

15

Field

Type

Reset

Description

Parity_bit

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-12

11-0

RESERVED

R-0

R/W

0h

PWM_DUTY_OUTC

0h

12-bit Duty Cycle for Phase C output in PWM Generation Mode

64

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.16 PWM_STATE Register (Offset = 1Ch) [Reset = 0777h]

PWM_STATE is shown in PWM_STATE Register and described in PWM_STATE Register Field Descriptions.

Return to the DRV8311 Registers.

PWM State Register

Figure 8-16. PWM_STATE Register

15

14

13

5

12

11

10

2

9

8

0

Parity_bit

R-0h

RESERVED

R-0-0h

PWMC_STATE

R/W-7h

7

6

4

3

1

RESERVED

R-0-0h

PWMB_STATE

R/W-7h

RESERVED

R-0-0h

PWMA_STATE

R/W-7h

Table 8-18. PWM_STATE Register Field Descriptions

Bit

15

Field

Parity_bit

Type

Reset

Description

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-11

10-8

RESERVED

R-0

R/W

0h

PWMC_STATE

7h

Phase C Driver Output control

0h = High Side is OFF, Low Side is OFF

1h = High Side is OFF, Low Side is forced ON

2h = High Side is forced ON, Low Side is OFF

3h = Reserved

4h = Reserved

5h = High Side is OFF, Low Side PWM

6h = High Side PWM, Low Side is OFF

7h = High Side PWM, Low Side !PWM

7

RESERVED

R-0

0h

7h

Reserved

6-4

PWMB_STATE

R/W

Phase B Driver Output control

0h = High Side is OFF, Low Side is OFF

1h = High Side is OFF, Low Side is forced ON

2h = High Side is forced ON, Low Side is OFF

3h = Reserved

4h = Reserved

5h = High Side is OFF, Low Side PWM

6h = High Side PWM, Low Side is OFF

7h = High Side PWM, Low Side !PWM

3

RESERVED

R-0

0h

7h

Reserved

2-0

PWMA_STATE

R/W

Phase A Driver Output control

0h = High Side is OFF, Low Side is OFF

1h = High Side is OFF, Low Side is forced ON

2h = High Side is forced ON, Low Side is OFF

3h = Reserved

4h = Reserved

5h = High Side is OFF, Low Side PWM

6h = High Side PWM, Low Side is OFF

7h = High Side PWM, Low Side !PWM

Submit Document Feedback

65

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.17 PWMG_CTRL Register (Offset = 1Dh) [Reset = 0000h]

PWMG_CTRL is shown in PWMG_CTRL Register and described in PWMG_CTRL Register Field Descriptions.

Return to the DRV8311 Registers.

PWM_GEN Control Register

Figure 8-17. PWMG_CTRL Register

15

14

13

5

12

11

10

9

8

Parity_bit

R-0h

RESERVED

R-0-0h

PWM_EN

R/W-0h

PWMCNTR_MODE

R/W-0h

7

6

4

3

2

1

0

PWM_OSC_SYNC

R/W-0h

SPICLK_FREQ_SYNC

R/W-0h

SPISYNC_ACRCY

R/W-0h

Table 8-19. PWMG_CTRL Register Field Descriptions

Bit

15

Field

Type

Reset

Description

Parity_bit

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-11

10

RESERVED

PWM_EN

R-0

R/W

0h

Enable 3X Internal mode PWM Generation

0h = PWM_GEN disabled

1h = PWM_GEN enabled

9-8

7-5

PWMCNTR_MODE

PWM_OSC_SYNC

R/W

0h

PWM Gen counter mode

0h = Up and Down

1h = Up

2h = Down

3h = No action

Oscillator synchronization and PWM_SYNC control

0h = Oscillator synchronization is disable

1h = PWM_SYNC_PRD indicates period of PWM_SYNC signal and

can be used to calibrate PWM period

2h = PWM_SYNC used to set PWM period

3h = Oscillator synchronization is disable

4h = Oscillator synchronization is disable

5h = PWM_SYNC used for oscillator synchronization (only 20 kHz

frequency supported)

6h = PWM_SYNC used for oscillator synchronization and setting

PWM period (only 20 kHz frequency supported)

7h = SPI Clock pin SCLK used for oscillator synchronization

(Configure SPICLK_FREQ_SYNC)

4-2

SPICLK_FREQ_SYNC

R/W

0h

SPI Clock Frequency for synchronizing the Oscillator

0h = 1 MHz

1h = 1.25 MHz

2h = 2 MHz

3h = 2.5 MHz

4h = 4 MHz

5h = 5 MHz

6h = 8 MHz

7h = 10 MHz

66

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

Table 8-19. PWMG_CTRL Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1-0

SPISYNC_ACRCY

R/W

0h

Number of SPI Clock Cycle require for synchronizing the Oscillator

0h = 512 Clock Cycles (1%)

1h = 256 Clock Cycles (1%)

2h = 128 Clock Cycles (1%)

3h = 64 Clock Cycles (2%)

Submit Document Feedback

67

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.18 PWM_CTRL1 Register (Offset = 20h) [Reset = 0003h]

PWM_CTRL1 is shown in PWM_CTRL1 Register and described in PWM_CTRL1 Register Field Descriptions.

Return to the DRV8311 Registers.

PWM Control Register 1

Figure 8-18. PWM_CTRL1 Register

15

14

13

12

11

10

9

1

8

0

Parity_bit

R-0h

RESERVED

R-0-0h

7

6

5

4

3

2

RESERVED

R-0-0h

SSC_DIS

R/W-0h

PWM_MODE

R/W-3h

Table 8-20. PWM_CTRL1 Register Field Descriptions

Bit

15

Field

Type

Reset

Description

Parity_bit

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-3

2

RESERVED

SSC_DIS

R-0

R/W

0h

Disable Spread Spectrum Modulation for internal Oscillator

0h = Spread spectrum modulation is enabled

1h = Spread spectrum modulation is disabled

1-0

PWM_MODE

R/W

3h

PWM mode selection

0h = 6x mode

1h = 6x mode

2h = 3x mode

3h = PWM Generation mode

68

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.19 DRV_CTRL Register (Offset = 22h) [Reset = 0000h]

DRV_CTRL is shown in DRV_CTRL Register and described in DRV_CTRL Register Field Descriptions.

Return to the DRV8311 Registers.

Predriver control Register

Figure 8-19. DRV_CTRL Register

15

14

6

13

12

11

10

2

9

1

8

0

Parity_bit

R-0h

RESERVED

R-0-0h

RESERVED

R/W-0h

7

5

4

3

DLYCMP_EN

R/W-0h

TDEAD_CTRL

R/W-0h

RESERVED

R-0-0h

SLEW_RATE

R/W-0h

Table 8-21. DRV_CTRL Register Field Descriptions

Bit

15

Field

Parity_bit

Type

Reset

Description

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

14-12

11-8

7

RESERVED

DLYCMP_EN

R-0

R/W

0h

Reserved

0h

Driver Delay Compensation enable

0h = Driver Delay Compensation is disabled

1h = Driver Delay Compensation is enabled

6-4

TDEAD_CTRL

R/W

0h

Deadtime insertion control

0h = No deadtime (Handsake Only)

1h = 200ns

2h = 400ns

3h = 600ns

4h = 800ns

5h = 1us

6h = 1.2us

7h = 1.4us

3-2

1-0

RESERVED

SLEW_RATE

R-0

0h

Reserved

R/W

Slew rate settings

0h = Slew rate is 35 V/µs

1h = Slew rate is 75 V/µs

2h = Slew rate is 180 V/µs

3h = Slew rate is 230 V/µs

Submit Document Feedback

69

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.20 CSA_CTRL Register (Offset = 23h) [Reset = 0000h]

CSA_CTRL is shown in CSA_CTRL Register and described in CSA_CTRL Register Field Descriptions.

Return to the DRV8311 Registers.

CSA Control Register

Figure 8-20. CSA_CTRL Register

15

14

6

13

5

12

11

10

9

1

8

0

Parity_bit

R-0h

RESERVED

R-0-0h

7

4

3

2

RESERVED

R-0-0h

CSA_EN

R/W-0h

RESERVED

R-0-0h

CSA_GAIN

R/W-0h

Table 8-22. CSA_CTRL Register Field Descriptions

Bit

15

Field

Type

Reset

Description

Parity_bit

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

Reserved

14-4

3

RESERVED

CSA_EN

R-0

R/W

0h

Current Sense Amplifier Enable

0h = Current Sense Amplifier is disabled

1h = Current Sense Amplifier is enabled

2

RESERVED

CSA_GAIN

R-0

0h

Reserved

1-0

R/W

Current Sense Amplifier Gain settings

0h = CSA gain is 0.25 V/A

1h = CSA gain is 0.5 V/A

2h = CSA gain is 1 V/A

3h = CSA gain is 2 V/A

70

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

8.21 SYS_CTRL Register (Offset = 3Fh) [Reset = 0000h]

SYS_CTRL is shown in SYS_CTRL Register and described in SYS_CTRL Register Field Descriptions.

Return to the DRV8311 Registers.

System Control Register

Figure 8-21. SYS_CTRL Register

15

14

13

12

11

10

9

8

Parity_bit

R-0h

WRITE_KEY

W-0h

RESERVED

R-0-0h

RESERVED

R/W-0h

7

6

5

4

3

2

1

0

REG_LOCK

R/W-0h

SPI_PEN

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

RESERVED

R/W-0h

Table 8-23. SYS_CTRL Register Field Descriptions

Bit

15

Field

Type

Reset

Description

Parity_bit

R

0h

Parity Bit if SPI_PEN is set to '1' otherwise reserved

14-12

11-9

8

WRITE_KEY

RESERVED

REG_LOCK

W

0h

0x5 Write Key Specific to this register.

R-0

R/W

0h

Reserved

0h

7

0h

Register Lock Bit

0h = Registers Unlocked

1h = Registers Locked

6

SPI_PEN

R/W

0h

Parity Enable for both SPI and tSPI

0h = Parity Disabled

1h = Parity Enabled

5-4

3

RESERVED

R/W

0h

Reserved

2-0

Submit Document Feedback

71

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The DRV8311 can be used to drive Brushless-DC motors.

V_VM

+

1 µF

VM

0.1 µF

10 µF

0.1 µF

CP

V_CC

Voltage

Regulator

CSAREF

Buck Regulator

Microcontroller

VIN_AVDD

AVDD

ADC

External

Load

SOC

SOB

SOA

Current

Sensing

C_AVDD

CSA

ADC

AGND

R_PU1

DRV8311H

nFAULT

nSLEEP

GP-I

Driver

Control

Hall

Sensors

(Optional)

GP-O

OUTA

A

B

INHA

INLA

INHB

INLB

INHC

INLC

GP-O

OUTB

OUTC

PWM

Control

Module

PWM

Control

Input

GP-O

AVDD

MODE

SLEW

PGND

HW

GAIN

Hall Input

GP-I

Figure 9-1. Application Schematics (DRV8311H)

72

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

V_VM

+

0.1 µF

VM

0.1 µF

10 µF

0.1 µF

CP

V_CC

Buck Regulator

Voltage

Regulator

CSAREF

VIN_AVDD

Microcontroller

+

0.1 µF

10 µF

ADC

External

Load

SOC

SOB

SOA

AVDD

AGND

Current

Sensing

C_AVDD

CSA

ADC

R_PU1

DRV8311P

nFAULT

nSLEEP

GP-I

Hall

Sensors

(Optional)

GP-O

OUTA

PWM_SYNC

AVDD

A

B

OUTB

OUTC

AD0

Device

Address

Select

AD1

SDO

GP-I

GP-O

nSCS

SCLK

PGND

SPI

SDI

Hall Input

GP-I

Figure 9-2. Application Schematics (DRV8311P)

Submit Document Feedback

73

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

9.2 Typical Applications

9.2.1 Three-Phase Brushless-DC Motor Control

In this application, the DRV8311H is used to drive a Brushless-DC motor

9.2.1.1 Detailed Design Procedure

Table 9-1lists the example input parameters for the system design.

Table 9-1. Design Parameters

DESIGN PARAMETERS

Supply voltage

REFERENCE

V_VM

I_RMS

EXAMPLE VALUE

12 V

2 A

Motor RMS current

Motor peak current

I_PEAK

3 A

PWM Frequency

f_PWM

50 kHz

230 V/µs

12 V

Slew Rate Setting

SR

VIN_AVDD supply voltage

CSA reference voltage

System ambient temperature

V_{VIN_AVDD}

V_{CSA_REF}

T_A

3.0 V

–20°C to +105°C

9.2.1.1.1 Motor Voltage

Brushless-DC motors are typically rated for a certain voltage (for example 12 V ). Operating a motor at a higher

voltage corresponds to a lower drive current to obtain the same motor power. A higher operating voltage also

corresponds to a higher obtainable rpm. DRV8311 device allows for the use of higher operating voltage because

of a maximum VM rating of 20 V.

Operating at lower voltages generally allows for more accurate control of phase currents. The DRV8311

functions down to a supply of 3 V.

74

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

10 Power Supply Recommendations

10.1 Bulk Capacitance

Having an appropriate local bulk capacitance is an important factor in motor drive system design. It is generally

beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.

The amount of local capacitance needed depends on a variety of factors, including:

•

The highest current required by the motor system

The capacitance and current capability of the power supply

The amount of parasitic inductance between the power supply and motor system

The acceptable voltage ripple

The type of motor used (brushed dc, brushless DC, stepper)

The motor braking method

The inductance between the power supply and the motor drive system limits the rate current can change from

the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands

or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage

remains stable and high current can be quickly supplied.

The data sheet generally provides a recommended value, but system-level testing is required to determine the

appropriate sized bulk capacitor.

Parasitic Wire

Inductance

Motor Drive System

Power Supply

VM

+

Motor Driver

œ

GND

Local

Bulk Capacitor

IC Bypass

Capacitor

Figure 10-1. Example Setup of Motor Drive System With External Power Supply

The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases

when the motor transfers energy to the supply.

Submit Document Feedback

75

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

11 Layout

11.1 Layout Guidelines

The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver

device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used

when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high

current.

Small-value capacitors should be ceramic, and placed closely to device pins.

The high-current device outputs should use wide metal traces.

The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to

connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate

the I²× r_DS(on)heat that is generated in the device.

76

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

11.2 Layout Example

Figure 11-1. Recommended Layout Example for DRV8311

Submit Document Feedback

77

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

11.3 Thermal Considerations

The DRV8311 has thermal shutdown (TSD) as previously described. A die temperature in excess of 150°C

(minimally) disables the device until the temperature drops to a safe level.

Any tendency of the device to enter thermal shutdown is an indication of excessive power dissipation, insufficient

heatsinking, or too high an ambient temperature.

11.3.1 Power Dissipation

The power dissipated in the output FET resistance, or r_DS(on)dominates power dissipation in the DRV8311. A

rough estimate of average power dissipation of each half-H-bridge when running a static load is:

At start-up and fault conditions, this current is much higher than normal running current; remember to take these

peak currents and their duration into consideration.

The total device dissipation is the power dissipated in each of the three half-H-bridges added together.

The maximum amount of power that the device can dissipate depends on ambient temperature and heatsinking.

Note that r_DS(on)increases with temperature, so as the device heats, the power dissipation increases. Take this

into consideration when sizing the heatsink.

78

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

12 Device and Documentation Support

12.1 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.2 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.4 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most-

current data available for the designated device. This data is subject to change without notice and without

revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.

Submit Document Feedback

79

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

PACKAGE OUTLINE

RRW0024A

WQFN - 0.8 mm max height

S

C

A

L

E

4

.

0

PLASTIC QUAD FLATPACK - NO LEAD

3.1

2.9

B

A

3.1

2.9

PIN 1 INDEX AREA

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 2.4

1.95

1.85

(0.1) TYP

6

12

20X 0.4

5

13

(0.93)

2X

21

SYMM

1.6

17

1

0.25

0.15

24X

PIN 1 ID

(OPTIONAL)

0.1

C A

B

24

0.05

18

SYMM

0.37

0.17

24X

4226921/A 07/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

80

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

EXAMPLE BOARD LAYOUT

RRW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.9)

SYMM

24

18

24X (0.47)

24X (0.2)

1

17

(0.7)

TYP

25

(0.67)

SYMM

(2.93)

20X (0.4)

5

13

(

0.2) TYP VIA

(R0.05)

TYP

6

12

(2.93)

LAND PATTERN EXAMPLE

SCALE:25X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4226921/A 07/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be ﬁlled, plugged or tented.

www.ti.com

Submit Document Feedback

81

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

EXAMPLE STENCIL DESIGN

RRW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(0.47) TYP

(R0.05) TYP

18

24

24X (0.47)

24X (0.2)

1

17

25

(0.67)

(0.47)

TYP

SYMM

(2.93)

20X (0.4)

5

13

METAL

TYP

6

12

4X ( 0.75)

(2.93)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 21:

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4226921/A 07/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

82

Submit Document Feedback

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

13.1 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

K0

P1

W

B0

Reel

Diameter

Cavity

A0

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

W

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

A0

(mm)

B0

(mm)

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

Device

Pins

SPQ

PDRV8311PRRWR

PDRV8311HRRWR

WQFN-24

RRW

24

5000

330.0

12.4

3.3

1.1

8.0

12.0

Q2

Submit Document Feedback

83

Product Folder Links: DRV8311

DRV8311

SLVSFN2 – SEPTEMBER 2021

www.ti.com

TAPE AND REEL BOX DIMENSIONS

Width (mm)

H

W

L

Device

Package Type

WQFN-24

Package Drawing Pins

SPQ

5000

Length (mm) Width (mm)

Height (mm)

35.0

PDRV8311PRRWR

PDRV8311HRRWR

RRW

24

367.0

WQFN-24

35.0

84

Submit Document Feedback

Product Folder Links: DRV8311

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	DRV8311P
厂家：	TEXAS INSTRUMENTS
描述：	DRV8311 Three-Phase PWM Motor Driver
文件：	总87页 (文件大小：2588K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DRV8311P [TI]

相关型号：

DRV8311PRRWR

DRV8311S

DRV8312

DRV8312DDW

DRV8312DDWR

DRV8312_1

DRV8312_11

DRV8312_14

DRV8312_15

DRV8313

DRV8313EVM

DRV8313PWP