DRV8350F [TI]
DRV835xF 100-V Three-Phase Smart Gate Driver;
| 型号： | DRV8350F |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DRV835xF 100-V Three-Phase Smart Gate Driver 栅 |
| 文件： | 总97页 (文件大小：3654K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV8350F, DRV8353F, DRV8350RF, DRV8353RF
SLVSFV1 – SEPTEMBER 2020
DRV835xF 100-V Three-Phase Smart Gate Driver
1 Features
3 Description
•
•
•
9 to 100-V, Triple half-bridge gate driver
The DRV835xF family of devices are highly-integrated
gate drivers for three-phase brushless DC (BLDC)
motor applications. The device variants provide
optional integrated current shunt amplifiers to support
different motor control schemes and a buck regulator
to power the gate driver or external controller.
– Optional integrated buck regulator
– Optional triple low-side current shunt amplifiers
Functional Safety Quality-Managed
– Documentation available to aid IEC 61800-5-2
functional safety system design
Smart gate drive architecture
– Adjustable slew rate control for EMI
performance
The DRV835xF uses smart gate drive (SGD)
architecture to decrease the number of external
components that are typically necessary for MOSFET
slew rate control and protection circuits. The SGD
architecture also optimizes dead time to prevent
shoot-through conditions, provides flexibility in
decreasing electromagnetic interference (EMI) by
MOSFET slew rate control, and protects against gate
short circuit conditions through VGS monitors. A strong
gate pulldown circuit helps prevent unwanted dV/dt
parasitic gate turn on events
– VGS handshake and minimum dead-time
insertion to prevent shoot-through
– 50-mA to 1-A peak source current
– 100-mA to 2-A peak sink current
– dV/dt mitigation through strong pulldown
Integrated gate driver power supplies
– High-side doubler charge pump For 100%
PWM duty cycle control
•
Various PWM control modes (6x, 3x, 1x, and
independent) are supported for simple interfacing to
the external controller. These modes can decrease
the number of outputs required of the controller for the
motor driver PWM control signals. This family of
devices also includes 1x PWM mode for simple
sensored trapezoidal control of a BLDC motor by
using an internal block commutation table.
– Low-side linear regulator
•
•
•
Integrated LM5008A buck regulator
– 6 to 95-V operating voltage range
– 2.5 to 75-V, 350-mA output capability
Integrated triple current shunt amplifiers
– Adjustable gain (5, 10, 20, 40 V/V)
– Bidirectional or unidirectional support
6x, 3x, 1x, and independent PWM modes
– Supports 120° sensored operation
SPI or hardware interface available
Low-power sleep mode (20 µA at VVM = 48-V)
Integrated protection features
– VM undervoltage lockout (UVLO)
– Gate drive supply undervoltage (GDUV)
– MOSFET VDS overcurrent protection (OCP)
– MOSFET shoot-through prevention
– Gate driver fault (GDF)
Device Information
(1)PART NUMBER
DRV8350F
PACKAGE
BODY SIZE (NOM)
5.00 mm × 5.00 mm
7.00 mm × 7.00 mm
6.00 mm × 6.00 mm
7.00 mm × 7.00 mm
WQFN (32)
•
•
•
DRV8350RF (2)
DRV8353F (2)
DRV8353RF (2)
VQFN (48)
WQFN (40)
VQFN (48)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Device is available for preview only.
9 to 75 V
7 to 100 V
– Thermal warning and shutdown (OTW/OTSD)
– Fault condition indicator (nFAULT)
Drain
Sense
DRV835xF
PWM
Three-Phase
Smart Gate Driver
SPI or H/W
M
Gate Drive
2 Applications
nFAULT
Current Sense
350 mA
Protection
•
•
•
•
•
•
3-phase brushless-DC (BLDC) motor modules
Servo drives, Factory automation
Linear motor transport systems
Industrial collaborative robot
Autonomous Guided Vehicle, Delivery Drones
E-Bikes, E-scooters, and E-mobility
Current
Sense
3x Shunt Amplifiers
Buck Regulator
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8350F, DRV8353F, DRV8350RF, DRV8353RF
SLVSFV1 – SEPTEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
Pin Functions—32-Pin DRV8350F Devices......................3
Pin Functions—48-Pin DRV8350RF Devices...................5
Pin Functions—40-Pin DRV8353F Devices......................6
Pin Functions—48-Pin DRV8353FR Devices...................8
7 Specifications................................................................ 10
7.1 Absolute Maximum Ratings...................................... 10
7.2 ESD Ratings..............................................................11
7.3 Recommended Operating Conditions.......................11
7.4 Thermal Information..................................................11
7.5 Electrical Characteristics...........................................12
7.6 SPI Timing Requirements......................................... 19
7.7 Typical Characteristics..............................................20
8 Detailed Description......................................................22
8.1 Overview...................................................................22
8.2 Functional Block Diagram.........................................23
8.3 Feature Description...................................................31
8.4 Device Functional Modes..........................................58
8.5 Programming............................................................ 59
8.6 Register Maps...........................................................61
9 Application and Implementation..................................73
9.1 Application Information............................................. 73
9.2 Typical Application.................................................... 73
10 Power Supply Recommendations..............................86
10.1 Bulk Capacitance Sizing......................................... 86
11 Layout...........................................................................87
11.1 Layout Guidelines................................................... 87
11.2 Layout Example...................................................... 88
12 Device and Documentation Support..........................89
12.1 Device Support....................................................... 89
12.2 Documentation Support.......................................... 89
12.3 Related Links.......................................................... 90
12.4 Receiving Notification of Documentation Updates..90
12.5 Support Resources................................................. 90
12.6 Trademarks.............................................................90
12.7 Electrostatic Discharge Caution..............................90
12.8 Glossary..................................................................90
13 Mechanical, Packaging, and Orderable
Information.................................................................... 90
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Table 4-1. Pre-Release Revision Notes
DATE
REVISION
NOTES
September 2020
*
Initial release
Copyright © 2020 Texas Instruments Incorporated
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DRV8350F, DRV8353F, DRV8350RF, DRV8353RF
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SLVSFV1 – SEPTEMBER 2020
5 Device Comparison Table
DEVICE
VARIANT
SHUNT AMPLIFIERS
BUCK REGULATOR
INTERFACE
Hardware (H)
SPI (S)
DRV8350FH
DRV8350FS
DRV8350RFH
DRV8350RFS
DRV8353FH
DRV8353FS
DRV8353RFH
DRV8353RFS
DRV8350F
None
0
Hardware (H)
SPI (S)
DRV8350RF
DRV8353F
DRV8353RF
350 mA (R)
None
Hardware (H)
SPI (S)
3
Hardware (H)
SPI (S)
350 mA (R)
6 Pin Configuration and Functions
CPH
VM
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
INLA
CPH
VM
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
INLA
INHA
INHA
VDRAIN
VCP
ENABLE
NC
VDRAIN
VCP
ENABLE
nSCS
SCLK
SDI
Thermal
Pad
Thermal
Pad
GHA
VDS
GHA
SHA
IDRIVE
MODE
nFAULT
SHA
GLA
GLA
SDO
SLA
SLA
nFAULT
Not to scale
Not to scale
Figure 6-1. DRV8350FH RTV Package 32-Pin WQFN Figure 6-2. DRV8350FS RTV Package 32-Pin WQFN
With Exposed Thermal Pad Top View
With Exposed Thermal Pad Top View
Pin Functions—32-Pin DRV8350F Devices
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8350FH
DRV8350FS
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPH
1
1
PWR
PWR
PWR
I
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPL
32
29
22
32
29
22
5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This
regulator can source up to 10 mA externally.
DVDD
ENABLE
Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs pulse can be used
to reset fault conditions.
GHA
GHB
GHC
GLA
GLB
GLC
GND
5
5
O
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Device primary ground. Connect to system ground.
12
13
7
12
13
7
O
O
10
15
30
10
15
30
O
O
PWR
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Product Folder Links: DRV8350F DRV8353F DRV8350RF DRV8353RF
DRV8350F, DRV8353F, DRV8350RF, DRV8353RF
SLVSFV1 – SEPTEMBER 2020
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PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8350FH
DRV8350FS
IDRIVE
INHA
INHB
INHC
INLA
INLB
INLC
MODE
NC
19
23
25
27
24
26
28
18
21
17
—
—
—
—
6
—
23
25
27
24
26
28
—
—
17
21
20
19
18
6
I
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
No internal connection. This pin can be left floating or connected to system ground.
I
I
I
I
I
I
I
NC
nFAULT
nSCS
SCLK
SDI
OD
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
Serial chip select. A logic low on this pin enables serial interface communication.
I
I
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
Serial data input. Data is captured on the falling edge of the SCLK pin.
I
SDO
SHA
OD
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
High-side source sense input. Connect to the high-side power MOSFET source.
I
SHB
11
14
8
11
14
8
I
High-side source sense input. Connect to the high-side power MOSFET source.
SHC
I
High-side source sense input. Connect to the high-side power MOSFET source.
SLA
I
Low-side source sense input. Connect to the low-side power MOSFET source.
SLB
9
9
I
Low-side source sense input. Connect to the low-side power MOSFET source.
SLC
16
4
16
4
I
Low-side source sense input. Connect to the low-side power MOSFET source.
VCP
PWR
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
VDRAIN
VDS
3
3
I
I
20
31
—
31
VGLS
PWR
Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R,
0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
VM
2
2
PWR
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain
GND
VGLS
CPL
1
36
35
34
33
32
31
30
29
28
27
26
25
INHB
INLA
GND
VGLS
CPL
1
36
35
34
33
32
31
30
29
28
27
26
25
INHB
INLA
2
2
3
INHA
ENABLE
NC
3
INHA
ENABLE
nSCS
SCLK
SDI
CPH
VM
4
CPH
VM
4
5
5
VDRAIN
VCP
6
VDS
VDRAIN
VCP
6
Thermal
Pad
Thermal
Pad
7
IDRIVE
MODE
nFAULT
AGND
NC
7
GHA
SHA
8
GHA
SHA
8
SDO
9
9
nFAULT
AGND
NC
GLA
10
11
12
GLA
10
11
12
SLA
SLA
NC
NC
NC
NC
Not to scale
Not to scale
Figure 6-3. DRV8350RFH RGZ Package 48-Pin
VQFN With Exposed Thermal Pad Top View
Figure 6-4. DRV8350RFS RGZ Package 48-Pin
VQFN With Exposed Thermal Pad Top View
Copyright © 2020 Texas Instruments Incorporated
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Product Folder Links: DRV8350F DRV8353F DRV8350RF DRV8353RF
DRV8350F, DRV8353F, DRV8350RF, DRV8353RF
www.ti.com
SLVSFV1 – SEPTEMBER 2020
Pin Functions—48-Pin DRV8350RF Devices
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8350RFH
DRV8350RFS
AGND
BST
27
45
27
45
PWR
PWR
Device analog ground. Connect to system ground.
Buck regulator bootstrap input. Connect a X5R or X7R, 0.01-µF, 16-V, capacitor between the BST and SW pins.
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPH
4
4
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPL
3
3
PWR
PWR
PWR
DGND
DVDD
41
40
41
40
Device digital ground. Connect to system ground.
5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and DGND pins. This
regulator can source up to 10 mA externally.
Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be
used to reset fault conditions.
ENABLE
33
33
I
FB
48
8
48
8
I
Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Device primary ground. Connect to system ground.
GHA
GHB
GHC
GLA
GLB
GLC
GND
IDRIVE
INHA
INHB
INHC
INLA
INLB
INLC
MODE
NC
O
17
18
10
15
20
1
17
18
10
15
20
1
O
O
O
O
O
PWR
30
34
36
38
35
37
39
29
12
13
22
23
24
25
26
32
28
—
46
47
—
—
—
9
—
34
36
38
35
37
39
—
12
13
22
23
24
25
26
—
28
32
46
47
31
30
29
9
I
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
No internal connection. This pin can be left floating or connected to system ground.
No internal connection. This pin can be left floating or connected to system ground.
No internal connection. This pin can be left floating or connected to system ground.
No internal connection. This pin can be left floating or connected to system ground.
No internal connection. This pin can be left floating or connected to system ground.
No internal connection. This pin can be left floating or connected to system ground.
No internal connection. This pin can be left floating or connected to system ground.
No internal connection. This pin can be left floating or connected to system ground.
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
Serial chip select. A logic low on this pin enables serial interface communication.
Current limit off time set input. Connect a resistor between RCL and GND.
I
I
I
I
I
I
I
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
nFAULT
nSCS
RCL
RT/SD
SCLK
SDI
OD
I
I
I
On time set and remote shutdown input. Connect a resistor between RT/SD and VIN.
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
Serial data input. Data is captured on the falling edge of the SCLK pin.
I
I
SDO
SHA
SHB
SHC
SLA
OD
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
Low-side source sense input. Connect to the low-side power MOSFET source.
Low-side source sense input. Connect to the low-side power MOSFET source.
Low-side source sense input. Connect to the low-side power MOSFET source.
Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
I
I
16
19
11
14
21
42
16
19
11
14
21
42
I
I
SLB
I
SLC
SW
I
O
7-V internal regulator output. Gate supply for buck switch. Connect a X5R or X7R, 0.47-µF, 16-V ceramic capacitor between
the VCC and GND pins.
VCC
44
44
PWR
VCP
7
6
7
6
PWR
I
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDRAIN
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Product Folder Links: DRV8350F DRV8353F DRV8350RF DRV8353RF
DRV8350F, DRV8353F, DRV8350RF, DRV8353RF
SLVSFV1 – SEPTEMBER 2020
www.ti.com
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8350RFH
DRV8350RFS
VDS
VGLS
VIN
31
2
—
2
I
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
PWR
PWR
11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and GND pins.
43
43
Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R,
0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
VM
5
5
PWR
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain
CPL
CPH
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
GAIN
VDS
CPL
CPH
1
30
29
28
27
26
25
24
23
22
21
nSCS
SCLK
SDI
2
VM
IDRIVE
MODE
nFAULT
AGND
VREF
SOA
VM
3
VDRAIN
VCP
VDRAIN
VCP
4
SDO
5
nFAULT
AGND
VREF
SOA
Thermal
Pad
Thermal
Pad
GHA
SHA
GHA
SHA
6
7
GLA
GLA
8
SPA
SOB
SPA
9
SOB
SNA
SOC
SNA
10
SOC
Not to scale
Not to scale
Figure 6-5. DRV8353FH RTA Package 40-Pin WQFN Figure 6-6. DRV8353FS RTA Package 40-Pin WQFN
With Exposed Thermal Pad Top View
With Exposed Thermal Pad Top View
Pin Functions—40-Pin DRV8353F Devices
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8353FH
DRV8353FS
AGND
CPH
25
25
PWR
PWR
Device analog ground. Connect to system ground.
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
2
1
2
1
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPL
PWR
PWR
I
5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This
regulator can source up to 10 mA externally.
DVDD
ENABLE
38
31
38
31
Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be
used to reset fault conditions.
GAIN
GND
GHA
GHB
GHC
GLA
30
39
6
—
39
6
I
Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
Device power ground. Connect to system ground.
PWR
O
O
O
O
O
O
I
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
15
16
8
15
16
8
GLB
13
18
28
32
34
36
13
18
—
32
34
36
GLC
IDRIVE
INHA
INHB
INHC
I
I
I
Copyright © 2020 Texas Instruments Incorporated
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Product Folder Links: DRV8350F DRV8353F DRV8350RF DRV8353RF
DRV8350F, DRV8353F, DRV8350RF, DRV8353RF
www.ti.com
SLVSFV1 – SEPTEMBER 2020
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8353FH
DRV8353FS
INLA
INLB
INLC
MODE
nFAULT
nSCS
SCLK
SDI
33
35
37
27
26
—
—
—
—
7
33
35
37
—
26
30
29
28
27
7
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
Serial chip select. A logic low on this pin enables serial interface communication.
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
Serial data input. Data is captured on the falling edge of the SCLK pin.
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier output.
I
I
OD
I
I
I
SDO
SHA
OD
I
I
SHB
14
17
10
11
20
23
22
21
14
17
10
11
20
23
22
21
SHC
SNA
I
I
SNB
I
SNC
SOA
SOB
SOC
I
O
O
O
Shunt amplifier output.
Shunt amplifier output.
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current
shunt resistor.
SPA
SPB
SPC
9
9
I
I
I
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current
shunt resistor.
12
19
12
19
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current
shunt resistor.
VCP
5
4
5
4
PWR
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VDRAIN
VDS
I
I
29
40
—
40
VGLS
PWR
11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R,
0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
VM
3
3
PWR
PWR
Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF
and AGND pins.
VREF
24
24
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain
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GND
VGLS
CPL
1
36
35
34
33
32
31
30
29
28
27
26
25
INHB
GND
VGLS
CPL
1
36
35
34
33
32
31
30
29
28
27
26
25
INHB
INLA
2
INLA
2
3
INHA
3
INHA
ENABLE
nSCS
SCLK
SDI
CPH
4
ENABLE
GAIN
CPH
4
VM
5
VM
5
VDRAIN
VCP
6
VDS
VDRAIN
VCP
6
Thermal
Pad
Thermal
Pad
7
IDRIVE
MODE
nFAULT
AGND
VREF
SOA
7
GHA
SHA
8
GHA
SHA
8
SDO
9
9
nFAULT
AGND
VREF
SOA
GLA
10
11
12
GLA
10
11
12
SPA
SPA
SNA
SNA
Not to scale
Not to scale
Figure 6-7. DRV8353RFH RGZ Package 48-Pin
VQFN With Exposed Thermal Pad Top View
Figure 6-8. DRV8353RFS RGZ Package 48-Pin
VQFN With Exposed Thermal Pad Top View
Pin Functions—48-Pin DRV8353FR Devices
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8353RFH
DRV8353RFS
AGND
BST
27
45
27
45
PWR
PWR
Device analog ground. Connect to system ground.
Buck regulator bootstrap input. Connect a X5R or X7R, 0.01-µF, 16-V, capacitor between the BST and SW pins.
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPH
4
4
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPL
3
3
PWR
PWR
PWR
DGND
DVDD
41
40
41
40
Device ground. Connect to system ground.
5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and DGND pins. This
regulator can source up to 10 mA externally.
Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be
used to reset fault conditions.
ENABLE
33
33
I
FB
48
32
1
48
—
1
I
Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GAIN
GND
GHA
GHB
GHC
GLA
I
PWR
Device power ground. Connect to system ground.
8
8
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
High-side gate driver control input. This pin controls the output of the high-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
Serial chip select. A logic low on this pin enables serial interface communication.
Current limit off time set input. Connect a resistor between RCL and GND.
17
18
10
15
20
30
34
36
38
35
37
39
29
28
—
46
17
18
10
15
20
—
34
36
38
35
37
39
—
28
32
46
O
O
O
GLB
O
GLC
O
IDRIVE
INHA
INHB
INHC
INLA
INLB
INLC
MODE
nFAULT
nSCS
RCL
I
I
I
I
I
I
I
I
OD
I
I
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SLVSFV1 – SEPTEMBER 2020
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DRV8353RFH
DRV8353RFS
RT/SD
SCLK
SDI
47
—
—
—
9
47
31
30
29
9
I
On time set and remote shutdown input. Connect a resistor between RT/SD and VIN.
I
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
Serial data input. Data is captured on the falling edge of the SCLK pin.
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
High-side source sense input. Connect to the high-side power MOSFET source.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier input. Connect to the low-side of the current shunt resistor.
Shunt amplifier output.
I
SDO
SHA
SHB
SHC
SNA
SNB
SNC
SOA
SOB
SOC
OD
I
I
16
19
12
13
22
25
24
23
16
19
12
13
22
25
24
23
I
I
I
I
O
O
O
Shunt amplifier output.
Shunt amplifier output.
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current
shunt resistor.
SPA
SPB
11
14
11
14
I
I
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current
shunt resistor.
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current
shunt resistor.
SPC
SW
21
42
44
21
42
44
I
O
Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor.
7-V internal regulator output. Gate supply for buck switch. Connect a X5R or X7R, 0.47-µF, 16-V ceramic capacitor between
the VCC and GND pins.
VCC
PWR
VCP
7
6
7
6
PWR
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VDRAIN
VDS
I
31
2
—
2
I
VGLS
VIN
PWR
PWR
11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and BGND pins.
43
43
Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R, 0.1-
µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
VM
5
5
PWR
PWR
Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF
and AGND pins.
VREF
26
26
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain
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7 Specifications
7.1 Absolute Maximum Ratings
at TA = –40°C to +125°C (unless otherwise noted)(1)
MIN
MAX
UNIT
GATE DRIVER
Power supply pin voltage (VM)
–0.3
–0.3
–0.3
0
80
V
V
Voltage differential between ground pins (AGND, BGND, DGND, PGND)
MOSFET drain sense pin voltage (VDRAIN)
MOSFET drain sense pin voltage slew rate (VDRAIN)
Charge pump pin voltage (CPH, VCP)
0.3
102
V
2
VVDRAIN + 16
VVDRAIN
18
V/µs
V
–0.3
–0.3
–0.3
–0.3
Charge-pump negative-switching pin voltage (CPL)
Low-side gate drive regulator pin voltage (VGLS)
Internal logic regulator pin voltage (DVDD)
V
V
5.75
V
Digital pin voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO,
VDS)
–0.3
5.75
V
Continuous high-side gate drive pin voltage (GHx)
Transient 200-ns high-side gate drive pin voltage (GHx)
High-side gate drive pin voltage with respect to SHx (GHx)
Continuous high-side source sense pin voltage (SHx)
Continuous high-side source sense pin voltage (SHx)
Transient 200-ns high-side source sense pin voltage (SHx)
Continuous low-side gate drive pin voltage (GLx)
Transient 200-ns low-side gate drive pin voltage (GLx)
Gate drive pin source current (GHx, GLx)
Gate drive pin sink current (GHx, GLx)
Continuous low-side source sense pin voltage (SLx)
Transient 200-ns low-side source sense pin voltage (SLx)
Continuous shunt amplifier input pin voltage (SNx, SPx)
Transient 200-ns shunt amplifier input pin voltage (SNx, SPx)
Reference input pin voltage (VREF)
–5(2)
–10
VVCP + 0.3
VVCP + 0.3
16
V
V
V
V
V
V
V
V
A
A
V
V
V
V
V
V
–0.3
–5(2)
–5(2)
–10
102
VVDRAIN + 5
VVDRAIN + 10
VVGLS + 0.3
VVGLS + 0.3
–1.0
–5.0
Internally limited Internally limited
Internally limited Internally limited
–1
–5
1
5
–1
1
5
–5
–0.3
–0.3
5.75
Shunt amplifier output pin voltage (SOx)
BUCK REGULATOR
VVREF + 0.3
Power supply pin voltage (VIN)
–0.3
–0.3
–0.3
–0.3
–1
100
114
14
V
V
V
V
V
V
V
Bootstrap pin voltage (BST)
Bootstrap pin voltage with respect to SW (BST)
Bootstrap pin voltage with respect to VCC (BST)
Switching node pin voltage (SW)
100
VVIN
14
Internal regulator pin voltage (VCC)
–0.3
–0.3
Input pin voltage (FB, RCL, RT/SD)
7
DRV835xF
Ambient temperature, TA
–40
–40
–65
125
150
150
°C
°C
°C
Junction temperature, TJ
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) VDRAIN pin voltage with respect to high-side gate pin (GHx) and phase node pin voltage (SHx) should be limited to 102 V maximum.
This will limit the GHx and SHx pin negative voltage capability when VDRAIN is greater than 92 V.
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SLVSFV1 – SEPTEMBER 2020
7.2 ESD Ratings
VALUE
±1000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500
V may actually have higher performance.
7.3 Recommended Operating Conditions
at TA = –40°C to +125°C (unless otherwise noted)
MIN
MAX
UNIT
GATE DRIVER
VVM
Gate driver power supply voltage (VM)
9
7
0
0
0
0
0
0
3
0
0
0
75
100
5.5
V
V
VVDRAIN
VI
Charge pump reference and drain voltage sense (VDRAIN)
Input voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS, SCLK, SDI, VDS)
Applied PWM signal (INHx, INLx)
V
fPWM
200(1)
2
kHz
V/ns
mA
mA
mA
V
tSH
Switch-node slew rate range (SHx)
IGATE_HS
IGATE_LS
IDVDD
VVREF
ISO
High-side average gate-drive current (GHx)
Low-side average gate-drive current (GLx)
External load current (DVDD)
25(1)
25(1)
10(1)
5.5
Reference voltage input (VREF)
Shunt amplifier output current (SOx)
5
mA
V
VOD
Open drain pullup voltage (nFAULT, SDO)
Open drain output current (nFAULT, SDO)
5.5
IOD
5
mA
BUCK REGULATOR
VVIN
Power supply voltage (VIN)
6
95
V
DRV835xF
TA
TJ
Operating ambient temperature
Operating junction temperature
–40
–40
125
150
°C
°C
(1) Power dissipation and thermal limits must be observed.
7.4 Thermal Information
DRV8350F
RTV (WQFN)
32 PINS
29.2
DRV8353F
RTA (WQFN)
40 PINS
26.1
DRV835xRF
THERMAL METRIC(1)
RGZ (VQFN)
48 PINS
24.7
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
15.2
13.1
12.0
9.2
8.4
7.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
0.1
0.1
ψJB
9.2
8.4
7.1
RθJC(bot)
1.2
1.1
0.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (DVDD, VCP, VGLS, VM)
IVM
VM operating supply current
VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V
VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V
ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 25°C
ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 125°C
ENABLE = 0 V period to reset faults
VVM > VUVLO, ENABLE = 3.3 V to outputs ready
ENABLE = 0 V to device sleep mode
IDVDD = 0 to 10 mA
8.5
1.9
20
13
4
mA
mA
IVDRAIN
VDRAIN operating supply current
40
ISLEEP
Sleep mode supply current
µA
100
40
tRST
Reset pulse time
Turnon time
5
µs
ms
ms
V
tWAKE
tSLEEP
VDVDD
1
Turnoff time
1
DVDD regulator voltage
4.75
9
5
10.5
10
5.25
12
VVM = 15 V, IVCP = 0 to 25 mA
VVM = 12 V, IVCP = 0 to 20 mA
7.5
6
11.5
9.5
8.5
16
VCP operating voltage
with respect to VDRAIN
VVCP
V
V
VVM = 10 V, IVCP = 0 to 15 mA
8
VVM = 9 V, IVCP = 0 to 10 mA
5.5
13
10
8
7.5
14.5
11.5
9.5
8.5
VVM = 15 V, IVGLS = 0 to 25 mA
VVM = 12 V, IVGLS = 0 to 20 mA
12.5
10.5
9.5
VGLS operating voltage
with respect to GND
VVGLS
VVM = 10 V, IVGLS = 0 to 15 mA
VVM = 9 V, IVGLS = 0 to 10 mA
7
LOGIC-LEVEL INPUTS (ENABLE, INHx, INLx, nSCS, SCLK, SDI)
VIL
VIH
VHYS
IIL
Input logic low voltage
Input logic high voltage
Input logic hysteresis
Input logic low current
Input logic high current
Pulldown resistance
Propagation delay
0
0.8
5.5
V
V
1.5
100
mV
µA
µA
kΩ
ns
VVIN = 0 V
–5
5
IIH
VVIN = 5 V
50
100
200
70
RPD
tPD
To GND
INHx/INLx transition to GHx/GLx transition
FOUR-LEVEL H/W INPUTS (GAIN, MODE)
VI1
Input mode 1 voltage
Tied to GND
0
1.256
1.9
V
V
VCOMP1
VI2
VCOMP2
VI3
VCOMP3
VI4
Quad-level voltage comparator 1
Input mode 2 voltage
Voltage comparator between VI1 and VI2
47 kΩ ± 5% to tied GND
Voltage comparator between VI2 and VI3
Hi-Z
1.156
2.408
3.614
1.356
2.608
3.814
V
Quad-level voltage comparator 1
Input mode 3 voltage
2.508
3.1
V
V
Quad-level voltage comparator 3
Input mode 4 voltage
Voltage comparator between VI3 and VI4
Tied to DVDD
3.714
5
V
V
RPU
Pullup resistance
Internal pullup to DVDD
Internal pulldown to GND
50
kΩ
kΩ
RPD
Pulldown resistance
84
SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)
VI1
Input mode 1 voltage
Tied to GND
0
0.157
0.8
V
V
V
V
V
V
V
V
V
V
V
V
VCOMP1
VI2
VCOMP2
VI3
VCOMP3
VI4
VCOMP4
VI5
VCOMP5
VI6
Seven-level voltage comparator 1
Input mode 2 voltage
Voltage comparator between VI1 and VI2
18 kΩ ± 5% tied to GND
0.057
1.158
2.257
2.561
3.615
4.75
0.257
1.358
2.457
2.761
3.815
4.95
Seven-level voltage comparator 2
Input mode 3 voltage
Voltage comparator between VI2 and VI3
75 kΩ ± 5% tied to GND
1.258
1.7
Seven-level voltage comparator 3
Input mode 4 voltage
Voltage comparator between VI3 and VI4
Hi-Z
2.357
2.5
Seven-level voltage comparator 4
Input mode 5 voltage
Voltage comparator between VI4 and VI5
75 kΩ ± 5% tied to DVDD
2.661
3.3
Seven-level voltage comparator 5
Input mode 6 voltage
Voltage comparator between VI5 and VI6
18 kΩ ± 5% tied to DVDD
3.715
4.2
VCOMP6
Seven-level voltage comparator 6
Voltage comparator between VI6 and VI7
4.85
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SLVSFV1 – SEPTEMBER 2020
at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
Input mode 7 voltage
Pullup resistance
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VI7
Tied to DVDD
5
RPU
RPD
Internal pullup to DVDD
Internal pulldown to GND
73
73
kΩ
Pulldown resistance
kΩ
OPEN DRAIN OUTPUTS (nFAULT, SDO)
VOL
IOZ
Output logic low voltage
IO = 5 mA
VO = 5 V
0.125
2
V
Output high impedance leakage
–2
µA
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at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GATE DRIVERS (GHx, GLx)
VVM = 15 V, IVCP = 0 to 25 mA
9
7.5
6
10.5
10
12
11.5
9.5
VVM = 12 , IVCP = 0 to 20 mA
VVM = 10 V, IVCP = 0 to 15 mA
VVM = 9 V, IVCP = 0 to 10 mA
VVM = 15 V, IVGLS = 0 to 25 mA
VVM = 12 V, IVGLS = 0 to 20 mA
VVM = 10 V, IVGLS = 0 to 15 mA
VVM = 9 V, IVGLS = 0 to 10 mA
DEAD_TIME = 00b
High-side gate drive voltage
with respect to SHx
VGSH
V
8
5.5
9.5
9
7.5
8.5
11
12.5
12
10.5
9
Low-side gate drive voltage
with respect to PGND
VGSL
V
7.5
6.5
10.5
9.5
8
50
DEAD_TIME = 01b
100
200
400
100
500
1000
2000
4000
4000
50
SPI Device
Gate drive
dead time
tDEAD
DEAD_TIME = 10b
ns
DEAD_TIME = 11b
H/W Device
SPI Device
H/W Device
TDRIVE = 00b
TDRIVE = 01b
TDRIVE = 10b
TDRIVE = 11b
Peak current
gate drive time
tDRIVE
ns
IDRIVEP_HS or IDRIVEP_LS = 0000b
IDRIVEP_HS or IDRIVEP_LS = 0001b
IDRIVEP_HS or IDRIVEP_LS = 0010b
IDRIVEP_HS or IDRIVEP_LS = 0011b
IDRIVEP_HS or IDRIVEP_LS = 0100b
IDRIVEP_HS or IDRIVEP_LS = 0101b
IDRIVEP_HS or IDRIVEP_LS = 0110b
IDRIVEP_HS or IDRIVEP_LS = 0111b
IDRIVEP_HS or IDRIVEP_LS = 1000b
IDRIVEP_HS or IDRIVEP_LS = 1001b
IDRIVEP_HS or IDRIVEP_LS = 1010b
IDRIVEP_HS or IDRIVEP_LS = 1011b
IDRIVEP_HS or IDRIVEP_LS = 1100b
IDRIVEP_HS or IDRIVEP_LS = 1101b
IDRIVEP_HS or IDRIVEP_LS = 1110b
IDRIVEP_HS or IDRIVEP_LS = 1111b
IDRIVE = Tied to GND
50
100
150
300
350
400
450
550
600
650
700
850
900
950
1000
50
SPI Device
Peak source
gate current
IDRIVEP
mA
IDRIVE = 18 kΩ ± 5% tied to GND
IDRIVE = 75 kΩ ± 5% tied to GND
IDRIVE = Hi-Z
100
150
300
450
700
1000
100
100
200
300
600
700
800
900
H/W Device
IDRIVE = 75 kΩ ± 5% tied to DVDD
IDRIVE = 18 kΩ ± 5% tied to DVDD
IDRIVE = Tied to DVDD
IDRIVEN_HS or IDRIVEN_LS = 0000b
IDRIVEN_HS or IDRIVEN_LS = 0001b
IDRIVEN_HS or IDRIVEN_LS = 0010b
IDRIVEN_HS or IDRIVEN_LS = 0011b
IDRIVEN_HS or IDRIVEN_LS = 0100b
IDRIVEN_HS or IDRIVEN_LS = 0101b
IDRIVEN_HS or IDRIVEN_LS = 0110b
IDRIVEN_HS or IDRIVEN_LS = 0111b
Peak sink
gate current
IDRIVEN
SPI Device
mA
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SLVSFV1 – SEPTEMBER 2020
at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IDRIVEN_HS or IDRIVEN_LS = 1000b
IDRIVEN_HS or IDRIVEN_LS = 1001b
IDRIVEN_HS or IDRIVEN_LS = 1010b
IDRIVEN_HS or IDRIVEN_LS = 1011b
IDRIVEN_HS or IDRIVEN_LS = 1100b
IDRIVEN_HS or IDRIVEN_LS = 1101b
IDRIVEN_HS or IDRIVEN_LS = 1110b
IDRIVEN_HS or IDRIVEN_LS = 1111b
IDRIVE = Tied to GND
MIN
TYP
1100
1200
1300
1400
1700
1800
1900
2000
100
MAX
UNIT
IDRIVE = 18 kΩ ± 5% tied to GND
IDRIVE = 75 kΩ ± 5% tied to GND
IDRIVE = Hi-Z
200
300
H/W Device
600
IDRIVE = 75 kΩ ± 5% tied to DVDD
IDRIVE = 18 kΩ ± 5% tied to DVDD
IDRIVE = Tied to DVDD
900
1400
2000
50
Source current after tDRIVE
IHOLD
Gate holding current
mA
Sink current after tDRIVE
100
ISTRONG
ROFF
Gate strong pulldown current
Gate hold off resistor
GHx to SHx and GLx to SPx/SLx
GHx to SHx and GLx to SPx/SLx
2
A
150
kΩ
CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)
CSA_GAIN = 00b
4.85
9.7
5
10
5.15
10.3
20.6
41.2
5.15
10.3
20.6
41.2
CSA_GAIN = 01b
SPI Device
CSA_GAIN = 10b
19.4
38.8
4.85
9.7
20
CSA_GAIN = 11b
40
GCSA
Amplifier gain
V/V
GAIN = Tied to GND
5
GAIN = 47 kΩ ± 5% tied to GND
GAIN = Hi-Z
10
H/W Device
19.4
38.8
20
GAIN = Tied to DVDD
VO_STEP = 0.5 V, GCSA = 5 V/V
VO_STEP = 0.5 V, GCSA = 10 V/V
VO_STEP = 0.5 V, GVSA = 20 V/V
VO_STEP = 0.5 V, GCSA = 40 V/V
40
250
500
1000
2000
tSET
Settling time to ±1%
ns
VCOM
VDIFF
VOFF
Common mode input range
–0.15
–0.3
–3
0.15
0.3
3
V
V
Differential mode input range
Input offset error
VSP = VSN = 0 V
VSP = VSN = 0 V
mV
µV/°C
VDRIFT
Drift offset
10
VVREF
–
VLINEAR
SOx output voltage linear range
0.25
V
0.25
VVREF
–
VSP = VSN = 0 V, VREF_DIV = 0b
VSP = VSN = 0 V, VREF_DIV = 1b
VSP = VSN = 0 V
0.3
SPI Device
VVREF
/
2
VBIAS
SOx output voltage bias
V
VVREF
/
2
H/W Device
IBIAS
SPx/SNx input bias current
SOx output slew rate
VREF input current
250
2.5
µA
VSLEW
IVREF
60-pF load
10
1.5
10
1
V/µs
mA
VVREF = 5 V
DRV835xF: 60-pF load
DRV835xFR: 60-pF load
MHz
MHz
UGB
Unity gain bandwidth
PROTECTION CIRCUITS
VVM_UV VM undervoltage lockout
DRV835xF: VM falling, UVLO report
8.0
8.3
8.8
V
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at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DRV835xF: VM rising, UVLO recovery
DRV835xFR: VM falling, UVLO report
DRV835xFR: VM rising, UVLO recovery
Rising to falling threshold
MIN
8.2
8.0
8.2
TYP
8.5
8.3
8.5
200
10
MAX
UNIT
9.0
8.6
8.8
VVM_UVH
tVM_UVD
VM undervoltage hysteresis
VM undervoltage deglitch time
mV
µs
VM falling, UVLO report
DRV835xF: VDRAIN falling, UVLO report
DRV835xF: VDRAIN rising, UVLO recovery
DRV835xFR: VDRAIN falling, UVLO report
DRV835xFR: VDRAIN rising, UVLO recovery
Rising to falling threshold
6.1
6.3
6.1
6.3
6.4
6.6
6.4
6.6
200
10
6.8
7.0
6.7
6.9
VVDR_UV
VDRAIN undervoltage lockout
V
VVDR_UVH
tVDR_UVD
VDRAIN undervoltage hysteresis
VDRAIN undervoltage deglitch time
mV
µs
VDRAIN falling, UVLO report
VDRAIN
+ 5
VVCP_UV
VCP charge pump undervoltage lockout
VCP falling, GDUV report
VGLS falling, GDUV report
V
V
VGLS low-side regulator undervoltage
lockout
VVGLS_UV
4.25
Positive clamping voltage
Negative clamping voltage
DRV835xF: VDS_LVL = 0000b
DRV835xF: VDS_LVL = 0001b
DRV835xF: VDS_LVL = 0010b
DRV835xF: VDS_LVL = 0011b
DRV835xF: VDS_LVL = 0100b
DRV835xFR: VDS_LVL = 0000b
DRV835xFR: VDS_LVL = 0001b
DRV835xFR: VDS_LVL = 0010b
DRV835xFR: VDS_LVL = 0011b
DRV835xFR: VDS_LVL = 0100b
VDS_LVL = 0101b
12.5
13.5
–0.7
0.06
0.07
0.08
0.09
0.1
16
VGS_CLAMP
High-side gate clamp
V
0.041
0.051
0.061
0.071
0.081
0.048
0.056
0.064
0.072
0.085
0.18
0.072
0.084
0.096
0.108
0.115
0.072
0.084
0.096
0.108
0.115
0.22
0.06
0.07
0.08
0.09
0.1
SPI Device
0.2
V
VDS_LVL = 0110b
0.27
0.3
0.33
VDS_LVL = 0111b
0.36
0.4
0.44
VDS_LVL = 1000b
0.45
0.5
0.55
VDS_LVL = 1001b
0.54
0.6
0.66
VDS overcurrent
trip voltage
VVDS_OCP
VDS_LVL = 1010b
0.63
0.7
0.77
VDS_LVL = 1011b
0.72
0.8
0.88
VDS_LVL = 1100b
0.81
0.9
0.99
VDS_LVL = 1101b
0.9
1.0
1.1
VDS_LVL = 1110b
1.35
1.5
1.65
VDS_LVL = 1111b
1.8
2
2.2
DRV835xF: VDS = Tied to GND
DRV835xF: VDS = 18 kΩ ± 5% tied to GND
DRV835xFR: VDS = Tied to GND
DRV835xFR: VDS = 18 kΩ ± 5% tied to GND
VDS = 75 kΩ ± 5% tied to GND
VDS = Hi-Z
0.041
0.081
0.048
0.085
0.18
0.06
0.1
0.072
0.115
0.072
0.115
0.22
0.06
0.1
H/W Device
0.2
V
0.36
0.4
0.44
VDS = 75 kΩ ± 5% tied to DVDD
VDS = 18 kΩ ± 5% tied to DVDD
VDS = Tied to DVDD
0.63
0.7
0.77
0.9
1
1.1
Disabled
1
OCP_DEG = 00b
OCP_DEG = 01b
2
VDS and VSENSE
SPI Device
tOCP_DEG
µs
overcurrent deglitch time
OCP_DEG = 10b
4
OCP_DEG = 11b
8
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SLVSFV1 – SEPTEMBER 2020
at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
H/W Device
4
SEN_LVL = 00b
SEN_LVL = 01b
SEN_LVL = 10b
SEN_LVL = 11b
0.25
0.5
0.75
1
SPI Device
VSENSE overcurrent trip
voltage
VSEN_OCP
V
H/W Device
SPI Device
H/W Device
1
TRETRY = 0b
TRETRY = 1b
8
ms
μs
tRETRY
Overcurrent retry time
50
8
ms
°C
°C
°C
TOTW
TOTSD
THYS
Thermal warning temperature
Thermal shutdown temperature
Thermal hysteresis
Die temperature, TJ
Die temperature, TJ
Die temperature, TJ
130
150
150
170
20
170
190
BUCK REGULATOR VCC
6.6
7
100
8.5
300
100
8.8
0.8
9.2
5.3
190
3
7.4
V
mV
V
VVCC_REG
VCC regulator voltage
VVIN = 6 to 8.5 V
VVIN increasing
VVCC_BYT
VVCC_BYH
VCC bypass threshold
VCC bypass hysteresis
mV
Ω
VVIN = 6 V
VVIN = 10 V
VVIN = 48 V
VVCC_OUT
VCC output impedance
Ω
Ω
VVCC_LIM
VVCC_UV
VVCC_UVH
VVCC_UVFD
IIN_OP
VCC current limit
mA
V
VCC undervoltage lockout
VCC undervoltage lockout hysteresis
VCC filter delay
mV
μs
μA
μA
IIN operating current
FB = 3 V
550
110
750
176
IIN_OP
IIN shutdown current
RT/SD = 0 V
BUCK REGULATOR SWITCHING
RDS(on)
Buck switch RDS(on)
ITEST = 200 mA
1.25
3.8
2.57
4.8
Ω
V
VGATE_UV
Gate drive undervoltage lockout
VBST - VSW rising
2.8
Gate drive undervoltage lockout
hysteresis
VGATE_UVH
490
mV
VSWITCH
tON
Pre-charge switch voltage
Pre-charge switch on-time
At 1 mA
0.8
V
150
ns
BUCK REGULATOR CURRENT LIMIT
ILIMIT
tLIM
tOFF1
tOFF2
Current limit threshold
Current limit response time
Off time generator
0.41
0.51
350
35
0.61
A
ISW overdrive = 0.1 A, time to switch off
FB = 0 V, RCL = 100 kΩ
ns
μs
μs
Off time generator
FB = 2.3 V, RCL = 100 kΩ
2.56
BUCK REGULATOR ON TIME GENERATOR
tON1
Ton 1
VVIN = 10 V, RON = 200 kΩ
VVIN = 95 V, RON = 200 kΩ
Rising
2.15
200
0.4
2.77
300
0.7
35
3.5
420
μs
μs
V
tON2
Ton 2
VSDT
VSDH
Remote shutdown threshold
Remote shutdown hysteresis
1.05
mV
BUCK REGULATOR MINIMUM OFF TIME
tOFF_MIN Minimum off time
FB = 0 V
300
ns
BUCK REGULATOR REGULATIONS AND OV COMPARATORS
VFB
FB reference threshold
FB overvoltage threshold
FB bias current
Internal reference, trip point for switch on
Trip point for switch off
2.445
2.5
2.875
100
2.55
V
V
VFB_OV
IFB_BIAS
μA
BUCK REGULATOR THERMAL SHUTDOWN
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at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
165
25
MAX
UNIT
°C
TSD
Thermal shutdown threshold
Thermal shutdown hysteresis
TSDH
°C
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SLVSFV1 – SEPTEMBER 2020
7.6 SPI Timing Requirements
at TA = –40°C to +125°C, VVM = 9 to 75 V (unless otherwise noted)
MIN
NOM
MAX
UNIT
ms
ns
tREADY
tCLK
SPI ready after enable
SCLK minimum period
SCLK minimum high time
SCLK minimum low time
SDI input data setup time
SDI input data hold time
SDO output data delay time
nSCS input setup time
nSCS input hold time
VM > UVLO, ENABLE = 3.3 V
1
100
50
50
20
30
tCLKH
ns
tCLKL
ns
tSU_SDI
tH_SDI
ns
ns
tD_SDO
tSU_nSCS
tH_nSCS
tHI_nSCS
tDIS_nSCS
SCLK high to SDO valid
30
ns
50
50
ns
ns
nSCS minimum high time before active low
nSCS disable time
400
ns
nSCS high to SDO high impedance
10
ns
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7.7 Typical Characteristics
10
2
1.95
1.9
TA = -40°C
TA = 25°C
TA = 125°C
9.5
9
1.85
1.8
1.75
1.7
8.5
8
1.65
1.6
TA = -40°C
TA = 25°C
TA = 125°C
7.5
7
1.55
1.5
0
10
20
30
40
50
60
Supply Voltage (V)
70
80
90 100
0
10
20
30
40
50
Supply Voltage (V)
60
70
80
D002
D001
VVM = VVDRAIN
VVM = VVDRAIN
Figure 7-2. VDRAIN Supply Current Over Supply
Voltage
Figure 7-1. VM Supply Current Over Supply
Voltage
40
40
TA = -40°C
TA = 25°C
TA = 125°C
VSUP = 9 V
VSUP = 48 V
VSUP = 100 V
35
30
25
20
15
10
35
30
25
20
15
10
0
10
20
30
40
Supply Voltage (V)
50
60
70
80
90 100
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D003
D004
IVM + IVDRAIN
IVM + IVDRAIN
Figure 7-3. Sleep Current Over Supply Voltage
Figure 7-4. Sleep Current Over Temperature
11
15.5
TA = -40èC
TA = -40èC
10.9
15.4
TA = 25èC
TA = 25èC
TA = 125èC
TA = 125èC
10.8
15.3
10.7
10.6
10.5
10.4
10.3
10.2
10.1
10
15.2
15.1
15
14.9
14.8
14.7
14.6
14.5
0
5
10 15
VCP Load Current (mA)
20
25
0
5
10 15
VGLS Load Current (mA)
20
25
D005
D006
VVM = 48-V
VVM = 48-V
Figure 7-5. VCP Voltage Over Load
Figure 7-6. VGLS Voltage Over Load Current
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SLVSFV1 – SEPTEMBER 2020
11
10.9
10.8
10.7
10.6
10.5
10.4
10.3
10.2
10.1
10
16
15.8
15.6
15.4
15.2
15
TA = -40èC
TA = 25èC
TA = 125èC
TA = -40èC
TA = 25èC
TA = 125èC
14.8
14.6
14.4
14.2
14
0
5
10 15
VCP Load Current (mA)
20
25
0
5
10 15
VGLS Load Current (mA)
20
25
D007
D008
VVM = 15-V
VVM = 15-V
Figure 7-7. VCP Voltage Over Load Current
Figure 7-8. VGLS Voltage Over Load Current
11
13
TA = -40èC
TA = -40èC
10.8
12.8
TA = 25èC
TA = 25èC
TA = 25èC
TA = 125èC
10.6
12.6
10.4
10.2
10
12.4
12.2
12
9.8
9.6
9.4
9.2
9
11.8
11.6
11.4
11.2
11
0
5
10
VCP Load Current (mA)
15
20
0
5
10
VGLS Load Current (mA)
15
20
D009
D010
VVM = 12-V
VVM = 12-V
Figure 7-9. VCP Voltage Over Load Current
Figure 7-10. VGLS Voltage Over Load Current
9
10
TA = -40èC
TA = -40èC
8.8
9.8
TA = 25èC
TA = 25èC
TA = 125èC
TA = 125èC
8.6
9.6
9.4
9.2
9
8.4
8.2
8
8.8
8.6
8.4
8.2
8
7.8
7.6
7.4
7.2
7
0
2
4
6
VGLS Load Current (mA)
8
10
0
2
4
6
VCP Load Current (mA)
8
10
D012
D011
VVM = 9-V
VVM = 9-V
Figure 7-12. VGLS Voltage Over Load Current
Figure 7-11. VCP Voltage Over Load Current
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8 Detailed Description
8.1 Overview
The DRV835xF family of devices are integrated 100-V gate drivers for three-phase motor drive applications.
These devices decrease system component count, cost, and complexity by integrating three independent half-
bridge gate drivers, charge pump and linear regulator for the high-side and low-side gate driver supply voltages,
optional triple current shunt amplifiers, and an optional 350-mA buck regulator. A standard serial peripheral
interface (SPI) provides a simple method for configuring the various device settings and reading fault diagnostic
information through an external controller. Alternatively, a hardware interface (H/W) option allows for configuring
the most commonly used settings through fixed external resistors.
The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-A
source, 2-A sink peak currents with a 25-mA average output current. The high-side gate drive supply voltage is
generated using a doubler charge-pump architecture that regulates the VCP output to VVDRAIN + 10.5-V. The
low-side gate drive supply voltage is generated using a linear regulator from the VM power supply that regulates
the VGLS output to 14.5-V. The VGLS supply is further regulated to 11-V on the GLx low-side gate driver
outputs. A smart gate-drive architecture provides the ability to dynamically adjust the output gate-drive current
strength allowing for the gate driver to control the power MOSFET VDS switching speed. This allows for the
removal of external gate drive resistors and diodes reducing BOM component count, cost, and PCB area. The
architecture also uses an internal state machine to protect against gate-drive short-circuit events, control the
half-bridge dead time, and protect against dV/dt parasitic turnon of the external power MOSFET.
The gate drivers can operate in either a single or dual supply architecture. In the single supply architecture, VM
can be tied to VDRAIN and is regulated to the correct supply voltages internally. In the dual supply architecture,
VM can be connected to a lower voltage supply from a more efficient switching regulator to improve the device
efficiency. VDRAIN stays connected to the external MOSFETs to set the correct charge pump and overcurrent
monitor reference.
The DRV8353F and DRV8353RF devices integrate three, bidirectional current-shunt amplifiers for monitoring
the current level through each of the external half-bridges using a low-side shunt resistor. The gain setting of the
shunt amplifier can be adjusted through the SPI or hardware interface with the SPI providing additional flexibility
to adjust the output bias point.
The DRV8350RF and DRV8353RF devices integrate a 350-mA buck regulator that can be used to power an
external controller or other logic circuits. The buck regulator is implemented as a separate internal die that can
use either the same or a different power supply from the gate driver.
In addition to the high level of device integration, the DRV835xF family of devices provides a wide range of
integrated protection features. These features include power-supply undervoltage lockout (UVLO), gate drive
undervoltage lockout (GDUV), VDS overcurrent monitoring (OCP), gate-driver short-circuit detection (GDF), and
overtemperature shutdown (OTW/OTSD). Fault events are indicated by the nFAULT pin with detailed information
available in the SPI registers on the SPI device version.
The DRV835xF family of devices are available in 0.5-mm pin pitch, QFN surface-mount packages. The QFN
sizes are 5 × 5 mm for the 32-pin package, 6 × 6 mm for the 40-pin package, and 7 × 7 mm for the 48-pin
package.
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8.2 Functional Block Diagram
VM
VDRAIN
VDRAIN
VM
>10 …F
0.1 …F
VCP
VCP
CPH
GHA
HS
VCP
Charge
Pump
1 …F
SHA
VDRAIN
VGLS
CPL
VGLS
DVDD
47 nF
GLA
LS
VGLS
Linear
Regulator
SLA
Gate Driver
1 …F
DVDD
Linear
Regulator
VDRAIN
1 …F
VCP
HS
GHB
GND
Power Supplies
SHB
ENABLE
VGLS
Digital
Core
GLB
INHA
INLA
INHB
INLB
INHC
INLC
LS
SLB
Gate Driver
VDRAIN
VCP
HS
Smart Gate
Drive
GHC
Control
Inputs
Protection
SHC
VGLS
GLC
LS
MODE
IDRIVE
VDS
SLC
Gate Driver
VCC
R
PU
Fault Output
nFAULT
Figure 8-1. Block Diagram for DRV8350FH
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VM
VDRAIN
VM
VDRAIN
>10 …F
0.1 …F
VCP
HS
VCP
CPH
GHA
SHA
VCP
Charge
Pump
1 …F
VDRAIN
VGLS
LS
CPL
VGLS
DVDD
47 nF
GLA
SLA
VGLS
Linear
Regulator
Gate Driver
1 …F
DVDD
Linear
Regulator
VDRAIN
1 …F
VCP
HS
GHB
SHB
GND
Power Supplies
ENABLE
VGLS
LS
Digital
Core
GLB
SLB
INHA
INLA
INHB
INLB
INHC
INLC
SDI
Gate Driver
Control
Inputs
VDRAIN
VCP
HS
Smart Gate
Drive
GHC
SHC
Protection
VGLS
LS
GLC
SLC
VCC
SPI
Gate Driver
Fault Output
R
PU
VCC
SDO
R
PU
SCLK
nFAULT
nSCS
Figure 8-2. Block Diagram for DRV8350FS
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VM
VDRAIN
VDRAIN
VM
>10 …F
0.1 …F
VCP
VCP
CPH
GHA
HS
VCP
Charge
Pump
1 …F
VDRAIN
SHA
VGLS
CPL
VGLS
DVDD
47 nF
GLA
LS
VGLS
Linear
Regulator
SLA
Gate Driver
1 …F
DVDD
Linear
Regulator
VDRAIN
1 …F
VCP
HS
GHB
GND
Power Supplies
SHB
ENABLE
VGLS
Digital
Core
GLB
INHA
INLA
INHB
INLB
INHC
INLC
LS
SLB
Gate Driver
VDRAIN
VCP
HS
Smart Gate
Drive
GHC
Control
Inputs
Protection
SHC
VGLS
GLC
LS
MODE
IDRIVE
VDS
SLC
Gate Driver
VCC
R
PU
Fault Output
nFAULT
VIN
BST
0.01 µF
VIN
RT/SD
RCL
LOUT
RRT/SD
CIN
350 mA
RFB1
SW
FB
Buck Regulator
(LM5008A)
ROUT
COUT
DOUT
GND
VCC
RRCL
RFB2
0.47 µF
Figure 8-3. Block Diagram for DRV8350RFH
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VM
VDRAIN
VM
VDRAIN
>10 …F
0.1 …F
VCP
HS
VCP
CPH
GHA
SHA
VCP
Charge
Pump
1 …F
VDRAIN
VGLS
LS
CPL
VGLS
DVDD
47 nF
GLA
SLA
VGLS
Linear
Regulator
Gate Driver
1 …F
DVDD
Linear
Regulator
VDRAIN
1 …F
VCP
HS
GHB
SHB
GND
Power Supplies
ENABLE
VGLS
LS
Digital
Core
GLB
SLB
INHA
INLA
INHB
INLB
INHC
INLC
SDI
Gate Driver
Control
Inputs
VDRAIN
VCP
HS
Smart Gate
Drive
GHC
SHC
Protection
VGLS
LS
GLC
SLC
VCC
SPI
Gate Driver
Fault Output
R
PU
VCC
SDO
R
PU
SCLK
nFAULT
nSCS
VIN
BST
0.01 µF
VIN
RT/SD
RCL
LOUT
RRT/SD
CIN
350 mA
SW
FB
Buck Regulator
(LM5008A)
ROUT
COUT
RFB1
DOUT
GND
VCC
RRCL
RFB2
0.47 µF
Figure 8-4. Block Diagram for DRV8350RFS
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VM
VDRAIN
VDRAIN
VM
>10 …F
0.1 …F
VCP
VCP
CPH
GHA
SHA
HS
VCP
Charge
Pump
1 …F
VDRAIN
VGLS
LS
CPL
VGLS
DVDD
47 nF
GLA
SPA
VGLS
Linear
Regulator
Gate Driver
1 …F
DVDD
Linear
Regulator
VDRAIN
1 …F
VCP
HS
GHB
SHB
GND
Power Supplies
ENABLE
VGLS
LS
Digital
Core
GLB
SPB
INHA
INLA
INHB
INLB
INHC
INLC
Gate Driver
VDRAIN
VCP
HS
Smart Gate
Drive
GHC
SHC
Protection
Control
Inputs
VGLS
LS
GLC
SPC
MODE
Gate Driver
Fault Output
IDRIVE
VCC
PU
R
VDS
nFAULT
GAIN
VCC
0.1 …F
SPC
SNC
VREF
AV
AV
AV
RSENC
SOC
SOB
SOA
SPB
SNB
Output
Offset
Bias
RSENB
SPA
SNA
AGND
RSENA
Figure 8-5. Block Diagram for DRV8353FH
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VM
VDRAIN
VM
VDRAIN
>10 …F
0.1 …F
VCP
HS
VCP
CPH
GHA
SHA
VCP
Charge
Pump
1 …F
VDRAIN
VGLS
LS
CPL
VGLS
DVDD
47 nF
GLA
SPA
VGLS
Linear
Regulator
Gate Driver
1 …F
DVDD
Linear
Regulator
VDRAIN
1 …F
VCP
HS
GHB
SHB
GND
Power Supplies
ENABLE
VGLS
LS
Digital
Core
GLB
SPB
INHA
INLA
INHB
INLB
INHC
INLC
SDI
Gate Driver
Control
Inputs
VDRAIN
VCP
HS
Smart Gate
Drive
GHC
SHC
Protection
VGLS
LS
GLC
SPC
VCC
SPI
Gate Driver
Fault Output
R
PU
VCC
PU
SDO
R
SCLK
nFAULT
nSCS
VCC
0.1 …F
SPC
SNC
VREF
AV
AV
AV
RSENC
SOC
SOB
SOA
SPB
SNB
Output
Offset
Bias
RSENB
SPA
SNA
AGND
RSENA
Figure 8-6. Block Diagram for DRV8353FS
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SLVSFV1 – SEPTEMBER 2020
VM
VDRAIN
VDRAIN
VM
>10 …F
0.1 …F
VCP
VCP
CPH
GHA
SHA
HS
VCP
Charge
Pump
1 …F
VDRAIN
VGLS
LS
CPL
VGLS
DVDD
47 nF
GLA
SPA
VGLS
Linear
Regulator
Gate Driver
1 …F
DVDD
Linear
Regulator
VDRAIN
1 …F
VCP
HS
GHB
SHB
GND
Power Supplies
ENABLE
VGLS
LS
Digital
Core
GLB
SPB
INHA
INLA
INHB
INLB
INHC
INLC
Gate Driver
VDRAIN
VCP
HS
Smart Gate
Drive
GHC
SHC
Protection
Control
Inputs
VGLS
LS
GLC
SPC
MODE
Gate Driver
Fault Output
IDRIVE
VCC
PU
R
VDS
nFAULT
GAIN
VCC
SPC
SNC
VREF
AV
AV
AV
RSENC
0.1 …F
SOC
SOB
SOA
SPB
SNB
Output
Offset
Bias
RSENB
SPA
SNA
AGND
RSENA
VIN
BST
0.01 µF
VIN
RT/SD
RCL
LOUT
RRT/SD
CIN
350 mA
RFB1
SW
FB
Buck Regulator
(LM5008A)
ROUT
COUT
DOUT
GND
VCC
RRCL
RFB2
0.47 µF
Figure 8-7. Block Diagram for DRV8353RFH
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VM
VDRAIN
VM
VDRAIN
>10 …F
0.1 …F
VCP
HS
VCP
CPH
GHA
SHA
VCP
Charge
Pump
1 …F
VDRAIN
VGLS
LS
CPL
VGLS
DVDD
47 nF
GLA
SPA
VGLS
Linear
Regulator
Gate Driver
1 …F
DVDD
Linear
Regulator
VDRAIN
1 …F
VCP
HS
GHB
SHB
GND
Power Supplies
ENABLE
VGLS
LS
Digital
Core
GLB
SPB
INHA
INLA
INHB
INLB
INHC
INLC
SDI
Gate Driver
Control
Inputs
VDRAIN
VCP
HS
Smart Gate
Drive
GHC
SHC
Protection
VGLS
LS
GLC
SPC
VCC
SPI
Gate Driver
Fault Output
R
PU
VCC
PU
SDO
R
SCLK
nFAULT
nSCS
VCC
0.1 …F
SPC
SNC
VREF
AV
AV
AV
RSENC
SOC
SOB
SOA
SPB
SNB
Output
Offset
Bias
RSENB
SPA
SNA
AGND
RSENA
VIN
BST
0.01 µF
VIN
RT/SD
RCL
LOUT
RRT/SD
CIN
350 mA
SW
FB
Buck Regulator
(LM5008A)
ROUT
COUT
RFB1
DOUT
GND
VCC
RRCL
RFB2
0.47 µF
Figure 8-8. Block Diagram for DRV8353RFS
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8.3 Feature Description
8.3.1 Three Phase Smart Gate Drivers
The DRV835xF family of devices integrates three, half-bridge gate drivers, each capable of driving high-side and
low-side N-channel power MOSFETs. The VCP doubler charge pump provides the correct gate bias voltage to
the high-side MOSFET across a wide operating voltage range in addition to providing 100% duty-cycle support.
The internal VGLS linear regulator provides the gate-bias voltage for the low-side MOSFETs. The half-bridge
gate drivers can be used in combination to drive a three-phase motor or separately to drive other types of loads.
The DRV835xF family of devices implement a smart gate-drive architecture which allows the user to dynamically
adjust the gate drive current without requiring external gate current limiting resistors. Additionally, this
architecture provides a variety of protection features for the external MOSFETs including automatic dead-time
insertion, parasitic dV/dt gate turnon prevention, and gate-fault detection.
8.3.1.1 PWM Control Modes
The DRV835xF family of devices provides four different PWM control modes to support various commutation
and control methods. Texas Instruments does not recommend changing the MODE pin or PWM_MODE register
during operation of the power MOSFETs. Set all INHx and INLx pins to logic low before making a MODE or
PWM_MODE change.
8.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
In this mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The
corresponding INHx and INLx signals control the output state as listed in Table 8-1.
Table 8-1. 6x PWM Mode Truth Table
INLx
INHx
GLx
GHx
SHx
Hi-Z
H
0
0
1
1
0
1
0
1
L
L
H
L
L
H
L
L
L
Hi-Z
8.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)
In this mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx pin is
used to change the half-bridge to high impedance. If the high-impedance (Hi-Z) sate is not required, tie all INLx
pins logic high. The corresponding INHx and INLx signals control the output state as listed in Table 8-2.
Table 8-2. 3x PWM Mode Truth Table
INLx
INHx
GLx
GHx
SHx
Hi-Z
L
0
1
1
X
0
1
L
L
H
L
L
H
H
8.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
In this mode, the DRV835xF family of devices uses 6-step block commutation tables that are stored internally.
This feature allows for a three-phase BLDC motor to be controlled using a single PWM sourced from a simple
controller. The PWM is applied on the INHA pin and determines the output frequency and duty cycle of the half-
bridges.
The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic
inputs. The state inputs can be controlled by an external controller or connected directly to hall sensor digital
outputs from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM mode usually
operates with synchronous rectification, however it can be configured to use asynchronous diode freewheeling
rectification on SPI devices. This configuration is set using the 1PWM_COM bit through the SPI registers.
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The INHC input controls the direction through the 6-step commutation table which is used to change the
direction of the motor when hall sensors are directly controlling the INLA, INHB, and INLB state inputs. Tie the
INHC pin low if this feature is not required.
The INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs
when it is pulled low. This brake is independent of the states of the other input pins. Tie the INLC pin high if this
feature is not required.
Table 8-3. Synchronous 1x PWM Mode
LOGIC AND HALL INPUTS
GATE-DRIVE OUTPUTS
INHC = 0
INHC = 1
PHASE A
PHASE B PHASE C
STATE
DESCRIPTION
INLA
INHB
INLB
INLA
INHB
INLB
GHA
GLA
GHB
GLB
GHC
GLC
Stop
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
0
1
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
1
0
0
0
1
1
1
0
0
0
1
L
PWM
L
L
!PWM
L
L
L
L
L
Stop
Align
L
H
L
H
Align
1
2
3
4
5
6
PWM
!PWM
L
L
H
H
B → C
A → C
A → B
C → B
C → A
B → A
PWM
PWM
L
!PWM
!PWM
L
L
L
H
L
L
L
L
H
PWM
PWM
L
!PWM
!PWM
L
L
H
L
L
L
H
PWM
!PWM
Table 8-4. Asynchronous 1x PWM Mode 1PWM_COM = 1 (SPI Only)
LOGIC AND HALL INPUTS
GATE-DRIVE OUTPUTS
INHC = 0
INHC = 1
PHASE A
PHASE B PHASE C
STATE
DESCRIPTION
INLA
INHB
INLB
INLA
INHB
INLB
GHA
GLA
L
GHB
GLB
L
GHC
GLC
L
Stop
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
0
1
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
1
0
0
0
1
1
1
0
0
0
1
L
PWM
L
L
L
Stop
Align
L
L
H
L
L
H
H
H
L
Align
1
2
3
4
5
6
L
PWM
L
L
B → C
A → C
A → B
C → B
C → A
B → A
PWM
PWM
L
L
L
L
L
L
L
H
H
L
L
L
PWM
PWM
L
L
L
H
H
L
L
L
PWM
L
L
Figure 8-9 and Figure 8-10 show the different possible configurations in 1x PWM mode.
INHA
MCU_PWM
MCU_GPIO
MCU_GPIO
PWM
INLA
INHB
INLB
INHC
INLC
STATE0
STATE1
STATE2
DIR
BLDC Motor
MCU_GPIO
MCU_GPIO
MCU_GPIO
nBRAKE
Figure 8-9. 1x PWM—Simple Controller
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INHA
INLA
INHB
INLB
INHC
INLC
MCU_PWM
PWM
H
STATE0
STATE1
STATE2
DIR
H
BLDC Motor
H
MCU_GPIO
MCU_GPIO
nBRAKE
Figure 8-10. 1x PWM—Hall Sensor
8.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
In this mode, the corresponding input pin independently controls each high-side and low-side gate driver. This
control mode allows for the external controller to bypass the internal dead-time handshake of the DRV835xF or
to utilize the high-side and low-side drivers to drive separate high-side and low-side loads with each half-bridge.
These types of loads include unidirectional brushed DC motors, solenoids, and low-side and high-side switches.
In this mode, If the system is configured in a half-bridge configuration, shoot-through occurs when the high-side
and low-side MOSFETs are turned on at the same time.
Table 8-5. Independent PWM Mode Truth Table
INLx
INHx
GLx
GHx
0
0
1
1
0
1
0
1
L
L
L
H
H
L
H
H
Because the high-side and low-side VDS overcurrent monitors share the SHx sense line, using both of the
monitors is not possible if both the high-side and low-side gate drivers are being operated independently.
In this case, connect the SHx pin to the high-side driver and disable the VDS overcurrent monitors as shown in
Figure 8-11.
Disable
+
VDS
œ
VM
VDRAIN
VCP
GHx
Load
HS
INHx
SHx
VGLS
INLx
GLx
LS
Load
Gate Driver
Disable
SLx/SPx
+
VDS
œ
Figure 8-11. Independent PWM High-Side and Low-Side Drivers
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If the half-bridge is used to implement only a high-side or low-side driver, using the VDS overcurrent monitors is
still possible. Connect the SHx pin as shown in Figure 8-12 or Figure 8-13. The unused gate driver and the
corresponding input can be left disconnected.
+
VDS
œ
VM
VDRAIN
VCP
GHx
HS
INHx
SHx
VGLS
INLx
GLx
LS
Load
Gate Driver
SLx/SPx
+
VDS
œ
Figure 8-12. Single High-Side Driver
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+
VDS
œ
VM
VDRAIN
VCP
HS
GHx
Load
INHx
INLx
SHx
GLx
VGLS
LS
Gate Driver
SLx/SPx
+
VDS
œ
Figure 8-13. Single Low-Side Driver
8.3.1.2 Device Interface Modes
The DRV835xF family of devices support two different interface modes (SPI and hardware) to allow the end
application to design for either flexibility or simplicity. The two interface modes share the same four pins, allowing
the different versions to be pin to pin compatible. This allows for application designers to evaluate with one
interface version and potentially switch to another with minimal modifications to their design.
8.3.1.2.1 Serial Peripheral Interface (SPI)
The SPI devices support a serial communication bus that allows for an external controller to send and receive
data with the DRV835xF. This allows for the external controller to configure device settings and read detailed
fault information. The interface is a four wire interface utilizing the SCLK, SDI, SDO, and nSCS pins.
•
The SCLK pin is an input which accepts a clock signal to determine when data is captured and propagated
on SDI and SDO.
•
•
The SDI pin is the data input.
The SDO pin is the data output. The SDO pin uses an open-drain structure and requires an external pullup
resistor.
•
The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the
DRV835xF.
For more information on the SPI, see the Section 8.5.1 section.
8.3.1.2.2 Hardware Interface
Hardware interface devices convert the four SPI pins into four resistor configurable inputs, GAIN, IDRIVE,
MODE, and VDS. This allows for the application designer to configure the most commonly used device settings
by tying the pin logic high or logic low, or with a simple pullup or pulldown resistor. This removes the requirement
for an SPI bus from the external controller. General fault information can still be obtained through the nFAULT
pin.
•
•
•
•
The GAIN pin configures the current shunt amplifier gain.
The IDRIVE pin configures the gate drive current strength.
The MODE pin configures the PWM control mode.
The VDS pin configures the voltage threshold of the VDS overcurrent monitors.
For more information on the hardware interface, see the Section 8.3.3 section.
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SCLK
SDI
SPI
Interface
VCC
RPU
SDO
nSCS
Figure 8-14. SPI
DVDD
DVDD
RGAIN
GAIN
Hardware
Interface
DVDD
DVDD
IDRIVE
DVDD
MODE
DVDD
VDS
RVDS
Figure 8-15. Hardware Interface
8.3.1.3 Gate Driver Voltage Supplies and Input Supply Configurations
The high-side gate-drive voltage supply is created using a doubler charge pump that operates from the VM and
VDRAIN voltage supply inputs. The charge pump allows the gate driver to correctly bias the high-side MOSFET
gate with respect to the source across a wide input supply voltage range. The charge pump is regulated to keep
a fixed output voltage of VVDRAIN + 10.5 V and supports an average output current of 25 mA. When VVM is less
than 12 V, the charge pump operates in full doubler mode and generates VVCP = 2 × VVM – 1.5 V with respect to
VVDRAIN when unloaded. The charge pump is continuously monitored for undervoltage to prevent under-driven
MOSFET conditions.
The charge pump requires a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VDRAIN and VCP pins to
act as the storage capacitor. Additionally, a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor is required
between the CPH and CPL pins to act as the flying capacitor.
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VDRAIN
VDRAIN
1 …F
VCP
CPH
VM
Charge
Pump
Control
47 nF
CPL
Figure 8-16. Charge Pump Architecture
The low-side gate drive voltage is created using a linear regulator that operates from the VM voltage supply
input. The VGLS linear regulator allows the gate driver to correctly bias the low-side MOSFET gate with respect
to ground. The VGLS linear regulator output is fixed at 14.5 V and further regulated to 11-V on the GLx outputs
during operation. The VGLS regulator supports an output current of 25 mA. The VGLS linear regulator is
monitored for undervoltage to prevent under driver MOSFET conditions. The VGLS linear regulator requires a
X5R or X7R, 1-µF, 16-V ceramic capacitor between VGLS and GND.
Since the charge pump output is regulated to VVDRAIN + 10.5 V this allows for VM to be supplied either directly
from the high voltage motor supply (up to 75 V) to support a single supply system or from a low voltage gate
driver power supply derived from a switching or linear regulator to improve the device efficiency or utilize an
externally available power supply. On the DRV8350RF and DRV8353RF devices the integrated buck regulator
can be used to create the efficient low voltage supply for VM without the need for an additional regulator. Figure
8-17 and Figure 8-18 show examples of the DRV835xF configured in either single supply or dual supply
configuration.
48-V
Power
Supply
VM
VDRAIN
DRV835xF
Power
MOSFETs
Figure 8-17. Single Supply Example
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48-V
Power
Supply
48-V to 15-V
DC/DC
VM
VDRAIN
DRV835xF
Power
MOSFETs
Figure 8-18. Dual Supply Example
8.3.1.4 Smart Gate Drive Architecture
The DRV835xF gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and
low-side drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates.
Additionally, the gate drivers use a smart gate-drive architecture to provide additional control of the external
power MOSFETs, take additional steps to protect the MOSFETs, and allow for optimal tradeoffs between
efficiency and robustness. This architecture is implemented through two components called IDRIVE and TDRIVE
which are detailed in the Section 8.3.1.4.1 section and Section 8.3.1.4.2 section. Figure 8-19 shows the high-
level functional block diagram of the gate driver.
The IDRIVE gate-drive current and TDRIVE gate-drive time should be initially selected based on the parameters
of the external power MOSFET used in the system and the desired rise and fall times (see the Section 9
section).
The high-side gate driver also implements a Zener clamp diode to help protect the external MOSFET gate from
overvoltage conditions in the case of external short-circuit events on the MOSFET.
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VCP
INHx
INLx
VDRAIN
Control
Inputs
GHx
Level
Shifters
150 kꢀ
SHx
+
GS œ
V
VGLS
Digital
Core
GLx
Level
Shifters
150 kꢀ
SLx/SPx
+
GS œ
V
Figure 8-19. Gate Driver Block Diagram
8.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
The IDRIVE component implements adjustable gate-drive current to control the MOSFET VDS slew rates. The
MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy and duration of diode
recovery spikes, dV/dt gate turnon leading to shoot-through, and switching voltage transients related to
parasitics in the external half-bridge. IDRIVE operates on the principal that the MOSFET VDS slew rates are
predominately determined by the rate of gate charge (or gate current) delivered during the MOSFET QGD or
Miller charging region. By allowing the gate driver to adjust the gate current, it can effectively control the slew
rate of the external power MOSFETs.
IDRIVE allows the DRV835xF family of devices to dynamically switch between gate drive currents either through
a register setting on SPI devices or the IDRIVE pin on hardware interface devices. The SPI devices provide 16
IDRIVE settings ranging between 50-mA to 1-A source and 100-mA to 2-A sink. Hardware interface devices
provides 7 IDRIVE settings between the same ranges. The gate drive current setting is delivered to the gate
during the turnon and turnoff of the external power MOSFET for the tDRIVE duration. After the MOSFET turnon or
turnoff, the gate driver switches to a smaller hold IHOLD current to improve the gate driver efficiency. Additional
details on the IDRIVE settings are described in the Section 8.6 section for the SPI devices and in the Section
8.3.3 section for the hardware interface devices.
8.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
The TDRIVE component is an integrated gate-drive state machine that provides automatic dead time insertion
through switching handshaking, parasitic dV/dt gate turnon prevention, and MOSFET gate-fault detection.
The first component of the TDRIVE state machine is automatic dead-time insertion. Dead time is period of time
between the switching of the external high-side and low-side MOSFETs to make sure that they do not cross
conduct and cause shoot-through. The DRV835xF family of devices use VGS voltage monitors to measure the
MOSFET gate-to-source voltage and determine the correct time to switch instead of relying on a fixed time
value. This feature allows the gate-driver dead time to adjust for variation in the system such a temperature drift
and variation in the MOSFET parameters. An additional digital dead time (tDEAD) can be inserted and is
adjustable through the registers on SPI devices.
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The automatic dead-time insertion has a limitation when the gate driver is transitioning from high-side MOSFET
on to low-side MOSFET on when the phase current is coming into the external half-bridge. In this case, the high-
side diode will conduct during the dead-time and hold up the switch-node voltage to VDRAIN. In this case, an
additional delay of approximately 100-200 ns is introduced into the dead-time handshake. This is introduced due
to the need to discharge the voltage present on the internal VGS detection circuit.
The second component focuses on parasitic dV/dt gate turnon prevention. To implement this, the TDRIVE state
machine enables a strong pulldown ISTRONG current on the opposite MOSFET gate whenever a MOSFET is
switching. The strong pulldown last for the TDRIVE duration. This feature helps remove parasitic charge that
couples into the MOSFET gate when the half-bridge switch-node voltage slews rapidly.
The third component implements a gate-fault detection scheme to detect pin-to-pin solder defects, a MOSFET
gate failure, or a MOSFET gate stuck-high or stuck-low voltage condition. This implementation is done with a
pair of VGS gate-to-source voltage monitors for each half-bridge gate driver. When the gate driver receives a
command to change the state of the half-bridge it starts to monitor the gate voltage of the external MOSFET. If at
the end of the tDRIVE period the VGS voltage has not reached the correct threshold the gate driver will report a
fault. To make sure that a false fault is not detected, a tDRIVE time should be selected that is longer than the time
required to charge or discharge the MOSFET gate. The tDRIVE time does not increase the PWM time and will
terminate if another PWM command is received while active. Additional details on the TDRIVE settings are
described in the Section 8.6 section for SPI devices and in the Section 8.3.3 section for hardware interface
devices.
Figure 8-20 shows an example of the TDRIVE state machine in operation.
V
INHx
V
INLx
V
GHx
tDEAD
IHOLD
tDEAD
I
I
t
I
I
HOLD
HOLD
DRIVE
STRONG
I
GHx
I
t
I
HOLD
DRIVE
DRIVE
DRIVE
V
GLx
GLx
tDEAD
tDEAD
IHOLD
I
I
t
I
I
HOLD
HOLD
DRIVE
DRIVE
STRONG
I
I
I
HOLD
DRIVE
t
DRIVE
Figure 8-20. TDRIVE State Machine
8.3.1.4.3 Propagation Delay
The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output
change. This time has three parts consisting of the digital input deglitcher delay, the digital propagation delay,
and the delay through the analog gate drivers.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. To support multiple control modes and dead time insertion, a small digital delay is added as the input
command propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to
the overall propagation delay of the device.
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8.3.1.4.4 MOSFET VDS Monitors
The gate drivers implement adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on
the external power MOSFETs. When the monitored voltage is greater than the VDS trip point (VVDS_OCP) for
longer than the deglitch time (tOCP), an overcurrent condition is detected and action is taken according to the
device VDS fault mode.
The high-side VDS monitors measure the voltage between the VDRAIN and SHx pins. In devices with three
current-shunt amplifiers (DRV8353F and DRV8353RF), the low-side VDS monitors measure the voltage between
the SHx and SPx pins. If the current shunt amplifier is unused, tie the SP pins to the common ground point of the
external half-bridges. On device options without the current shunt amplifiers (DRV8350F and DRV8350RF) the
low-side VDS monitor measures between the SHx and SLx pins.
For the SPI devices, the low-side VDS monitor reference point can be changed between the SPx and SNx pins if
desired with the LS_REF register setting. This is only for the low-side VDS monitor. The high-side VDS monitor
stays between the VDRAIN and SHx pins.
The VVDS_OCP threshold is programmable between 0.06 V and 2 V on SPI device and between 0.06 V and 1 V
on hardware interface devices. Additional information on the VDS monitor levels are described in the Section 8.6
section for SPI devices and in the Section 8.3.3 section hardware interface device.
VDRAIN
VDRAIN
+
V
+
DS œ
V
V
DSœ
V
V
VDS_OCP
GHx
SHx
GLx
+
DSœ
+
DSœ
V
VDS_OCP
SLx
Figure 8-21. DRV8350F and DRV8350RF VDS Monitors
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VDRAIN
VDRAIN
+
V
+
V
DSœ
DSœ
V
V
VDS_OCP
GHx
SHx
GLx
+
DSœ
+
V
V
DSœ
VDS_OCP
SPx
0
1
R
SENSE
SNx
LS_REF
(SPI Only)
Figure 8-22. DRV8353F and DRV8353RF VDS Monitors
8.3.1.4.5 VDRAIN Sense and Reference Pin
The DRV835xF family of devices provides a separate sense and reference pin for the common point of the high-
side MOSFET drain. This pin is called VDRAIN. This pin allows the sense line for the overcurrent monitors
(VDRAIN) and the power supply (VM) to stay separate and prevent noise on the VDRAIN sense line.
The VDRAIN pin serves as the reference point for the integrated charge pump. This makes sure that the charge
pump reference stays with respect to the power MOSFET supply through voltage transient conditions.
Since the charge pump is referenced to VDRAIN, this also allows for VM to supplied either directed from the
power MOSFET supply (VDRAIN) or from an independent supply. This allows for a configuration where VM can
be supplied from an efficient low voltage supply to increase the device efficiency. On the DRV8350RF and
DRV8353RF devices, the integrated buck regulator can be used to create the efficient low voltage supply.
8.3.2 DVDD Linear Voltage Regulator
A 5-V, 10-mA linear regulator is integrated into the DRV835xF family of devices and is available for use by
external circuitry. This regulator can provide the supply voltage for low-current supporting circuitry. The output of
the DVDD regulator should be bypassed near the DVDD pin with a X5R or X7R, 1-µF, 6.3-V ceramic capacitor
routed directly back to the adjacent DGND or GND ground pin.
The DVDD nominal, no-load output voltage is 5 V. When the DVDD load current exceeds 10 mA, the regulator
functions like a constant-current source. The output voltage drops significantly with a current load greater than
10 mA.
VM
REF
+
œ
5 V, 10 mA
DVDD
1 …F
GND/
DGND
Figure 8-23. DVDD Linear Regulator Block Diagram
Use Equation 1 to calculate the power dissipated in the device because of the DVDD linear regulator.
P = VVM - VDVDD ì I
DVDD
(1)
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For example, at VVM = 24 V, drawing 20 mA out of DVDD results in a power dissipation as shown in Equation 2.
P = 24 V - 3.3 V ì 20 mA = 414 mW
(2)
8.3.3 Pin Diagrams
Figure 8-24 shows the input structure for the logic-level pins, INHx, INLx, ENABLE, nSCS, SCLK, and SDI.
DVDD
STATE
VIH
RESISTANCE
Tied to DVDD
Tied to AGND
INPUT
Logic High
Logic Low
VIL
100 kꢀ
Figure 8-24. Logic-Level Input Pin Structure
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Figure 8-25 shows the structure of the four level input pins, MODE and GAIN, on hardware interface devices.
The input can be set with an external resistor.
MODE
GAIN
DVDD
STATE
VI4
RESISTANCE
Tied to DVDD
DVDD
Independent 40 V/V
+
50 kꢀ
œ
Hi-Z (>500 kΩ to
AGND)
1x PWM
3x PWM
6x PWM
20V/V
10 V/V
5 V/V
VI3
VI2
VI1
+
84 kꢀ
47 kΩ ±5%
to AGND
œ
Tied to AGND
+
œ
Figure 8-25. Four Level Input Pin Structure
Figure 8-26 shows the structure of the seven level input pins, IDRIVE and VDS, on hardware interface devices.
The input can be set with an external resistor.
IDRIVE
1/2 A
VDS
Disabled
+
œ
STATE
VI7
RESISTANCE
Tied to DVDD
700/1400 mA
450/900 mA
300/600 mA
150/300 mA
100/200 mA
50/100 mA
1 V
0.7 V
0.4 V
0.2 V
0.1 V
0.06 V
+
DVDD
DVDD
œ
18 kꢀ 5%
to DVDD
VI6
VI5
VI4
VI3
VI2
VI1
+
75 kꢀ 5%
to DVDD
73 kꢀ
œ
Hi-Z (>500 kΩ
to AGND)
73 kꢀ
+
75 kꢀ 5%
to AGND
œ
18 kΩ ±5%
to AGND
+
Tied to AGND
œ
+
œ
Figure 8-26. Seven Level Input Pin Structure
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Figure 8-27 shows the structure of the open-drain output pins nFAULT and SDO. The open-drain output requires
an external pullup resistor to function correctly.
DVDD
R
PU
STATE
No Fault
Fault
STATUS
Inactive
Active
OUTPUT
Active
Inactive
Figure 8-27. Open-Drain Output Pin Structure
8.3.4 Low-Side Current-Shunt Amplifiers (DRV8353F and DRV8353RF Only)
The DRV8353F and DRV8353RF integrate three, high-performance low-side current-shunt amplifiers for current
measurements using low-side shunt resistors in the external half-bridges. Low-side current measurements are
commonly used to implement overcurrent protection, external torque control, or brushless DC commutation with
the external controller. All three amplifiers can be used to sense the current in each of the half-bridge legs or one
amplifier can be used to sense the sum of the half-bridge legs. The current shunt amplifiers include features
such as programmable gain, offset calibration, unidirectional and bidirectional support, and a voltage reference
pin (VREF).
8.3.4.1 Bidirectional Current Sense Operation
The SOx pin on the DRV8353F and DRV8353RF outputs an analog voltage equal to the voltage across the SPx
and SNx pins multiplied by the gain setting (GCSA). The gain setting is adjustable between four different levels (5
V/V, 10 V/V, 20 V/V, and 40 V/V). Use Equation 3 to calculate the current through the shunt resistor.
VVREF
- VSOx
2
I =
GCSA ì RSENSE
(3)
R2
R3
R4
R5
R6
SOx
REF
I
R1
R1
SPx
SNx
V
CC
œ
R
SENSE
V
+
0.1 …F
R2
R3
R4
R5
½
+
œ
Figure 8-28. Bidirectional Current-Sense Configuration
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SO (V)
V
REF
V
/ 2
VREF
V
LINEAR
SP œ SN (V)
Figure 8-29. Bidirectional Current-Sense Output
I
SP
SO
R
AV
SN
SO
VREF
SP œ SN
œ0.3 V
œI × R
V
VREF
œ 0.25 V
V
SO(rangeœ)
V
SO(off)max
/ 2
V
,
OFF
0 V
V
VREF
V
DRIFT
V
SO(off)min
V
SO(range+)
I × R
0.3 V
0.25 V
0 V
Figure 8-30. Bidirectional Current Sense Regions
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8.3.4.2 Unidirectional Current Sense Operation (SPI only)
On the DRV8353F and DRV8353RF SPI devices, use the VREF_DIV bit to remove the VREF divider. In this
case the shunt amplifier operates unidirectionally and SOx outputs an analog voltage equal to the voltage across
the SPx and SNx pins multiplied by the gain setting (GCSA). Use Equation 4 to calculate the current through the
shunt resistor.
VVREF - VSOx
GCSA ì RSENSE
I =
(4)
R2
R3
R4
R5
R6
SOx
I
R1
R1
SPx
SNx
œ
R
SENSE
+
V
CC
R2
R3
R4
R5
V
REF
+
0.1 …F
œ
Figure 8-31. Unidirectional Current-Sense Configuration
SO (V)
V
REF
V
œ 0.3 V
VREF
V
LINEAR
SP œ SN (V)
Figure 8-32. Unidirectional Current-Sense Output
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I
SP
SN
SO
SO
R
AV
V
REF
V
œ 0.25 V
VREF
V
SO(off)max
SP œ SN
V
,
OFF
0 V
V
œ 0.3 V
VREF
V
DRIFT
V
SO(off)min
V
SO(range)
I × R
0.3 V
0.25 V
0 V
Figure 8-33. Unidirectional Current-Sense Regions
8.3.4.3 Amplifier Calibration Modes
To minimize DC offset and drift over temperature, a DC calibration mode is provided and enabled through the
SPI register (CSA_CAL_X). This option is not available on hardware interface devices. When the calibration
setting is enabled the inputs to the amplifier are shorted and the load is disconnected. DC calibration can be
done at any time, even when the half-bridges are operating. For the best results, do the DC calibration during
the switching OFF period to decrease the potential noise impact to the amplifier. A diagram of the calibration
mode is shown below. When a CSA_CAL_X bit is enabled, the corresponding amplifier goes to the calibration
mode.
RF
ROUT
SOx
RSP
!CAL
!CAL
SP
SN
-
RSENSE
RSN
VREF
+
CAL
CAL
+
RG
-
Figure 8-34. Amplifier Manual Calibration
In addition to the manual calibration method provided on the SPI devices versions, the DRV835xF family of
devices provide an auto calibration feature on both the hardware and SPI device versions in order to minimize
the amplifier input offset after power up and during run time to account for temperature and device variation.
Auto calibration occurs automatically on device power up for both the hardware and SPI device options. The
power up auto calibration starts immediately after the VREF pin crosses the minimum operational VREF voltage.
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50 us should be allowed for the power up auto calibration routine to complete after the VREF pin voltage crosses
the minimum VREF operational voltage. The auto calibration functions by doing a trim routine of the amplifier to
minimize the amplifier input offset. After this the amplifiers are ready for normal operation.
For the SPI device options, auto calibration can also be done again during run time by enabling the AUTO_CAL
register setting. Auto calibration can then be commanded with the corresponding CSA_CAL_X register setting to
rerun the auto calibration routine. During auto calibration all of the amplifiers will be configured for the max gain
setting in order to improve the accuracy of the calibration routine.
8.3.4.4 MOSFET VDS Sense Mode (SPI Only)
The current-sense amplifiers on the DRV8353F and DRV8353RF SPI devices can be configured to amplify the
voltage across the external low-side MOSFET VDS. This allows for the external controller to measure the voltage
drop across the MOSFET RDS(on) without the shunt resistor and then calculate the half-bridge current level.
To enable this mode set the CSA_FET bit to 1. The positive input of the amplifier is then internally connected to
the SHx pin with an internal clamp to prevent high voltage on the SHx pin from damaging the sense amplifier
inputs. During this mode of operation, the SPx pins should stay connected to the source of the low-side
MOSFET as it serves as the reference for the low-side gate driver. When the CSA_FET bit is set to 1, the
negative reference for the low-side VDS monitor is automatically set to SNx, regardless of the state of the
LS_REF bit state. This setting is implemented to prevent disabling of the low-side VDS monitor.
If the system operates in MOSFET VDS sensing mode, route the SHx and SNx pins with Kelvin connections
across the drain and source of the external low-side MOSFETs.
VDRAIN
VDRAIN
High-Side
VCP
V
Monitor
DS
+
V
DSœ
GHx
SHx
(SPI only)
CSA_FET = 0
LS_REF = 0
VGLS
Low-Side
V
Monitor
DS
+
V
DSœ
GLx
0
1
10 kꢀ
10 kꢀ
10 kꢀ
SPx
SOx
AV
R
SEN
SNx
GND
Figure 8-35. Resistor Sense Configuration
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VDRAIN
VDRAIN
High-Side
VCP
V
DS
Monitor
+
V
DSœ
GHx
SHx
(SPI only)
CSA_FET = 1
LS_REF = X
VGLS
Low-Side
V
Monitor
DS
+
V
GLx
SPx
DSœ
0
1
10 kꢀ
10 kꢀ
10 kꢀ
SOx
AV
SNx
GND
Figure 8-36. VDS Sense Configuration
When operating in MOSFET VDS sense mode, the amplifier is enabled at the end of the tDRIVE time. At this time,
the amplifier input is connected to the SHx pin, and the SOx output is valid. When the low-side MOSFET
receives a signal to turn off, the amplifier inputs, SPx and SNx, are shorted together internally.
8.3.5 Step-Down Buck Regulator
The DRV8350RF and DRV8353RF have an integrated buck regulator (LM5008A) to supply power for an
external controller or system voltage rail.
The LM5008A regulator is an easy-to-use buck (step-down) DC-DC regulator that operates from 6-V to 95-V
supply voltage. The device is intended for step-down conversions from 12-V, 24-V, and 48-V unregulated, semi-
regulated and fully-regulated supply rails. With integrated buck power MOSFET, the LM5008A delivers up to
350-mA DC load current with exceptional efficiency and low input quiescent current in a very small solution size.
Designed for simple implementation, an almost fixed-frequency, constant on-time (COT) operation with
discontinuous conduction mode (DCM) at light loads is ideal for low-noise, high current, fast transient load
requirements. Control loop compensation is not required reducing design time and external component count.
The LM5008A incorporates other features for comprehensive system requirements, including VCC undervoltage
lockout (UVLO), gate drive undervoltage lockout, maximum duty cycle limiter, intelligent current limit off-timer, a
precharge switch, and thermal shutdown with automatic recovery. These features enable a flexible and easy-to-
use platform for a wide range of applications. The pin arrangement is designed for simple and optimized PCB
layout, requiring only a few external components.
For additional details and design information refer to the LM5008A 100-V 350-mA Constant On-Time Buck
Switching Regulator data sheet.
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8.3.5.1 Functional Block Diagram
7 V Bias
Regulator
6 V to 95 V
Input
VIN
C5
RT
C1
VCC
UVLO
Thermal
Shutdown
VIN SENSE
VCC
Bypass
Switch
Q2
GND
C3
On Timer
Start
Finish
œ
+
0.7 V
RT
RT/SD
BST
Start
Over-Voltage
Comparator
Vin
GD
UVLO
SHUTDOWN
SD
C4
300 ns MIN
Off Timer
œ
Driver
Finish
2.875 V
Level
Shift
L1
SW
2.5 V
SSET
RCLR
Q
Q
FB
VOUT
œ
D1
Regulation
Comparator
Buck
RCL
RTN
FB
RCL
Finish
Start
Current Limit
Off Timer
RFB2
Pre-
Charge
Switch
Current
Sense
R3
C2
œ
RCL
0.51 A
RFB1
Figure 8-37. Functional Block Diagram
8.3.5.2 Feature Description
8.3.5.2.1 Control Circuit Overview
The LM5008A is a Buck DC-DC regulator that uses a control scheme in which the on-time varies inversely with
line voltage (VIN). Control is based on a comparator and the on-time one-shot, with the output voltage feedback
(FB) compared to an internal reference (2.5 V). If the FB level is below the reference the buck switch is turned on
for a fixed time determined by the line voltage and a programming resistor (RT). Following the ON period, the
switch stays off for at least the minimum off-timer period of 300 ns. If FB is still below the reference at that time,
the switch turns on again for another on-time period. This continues until regulation is achieved.
The LM5008A operates in discontinuous conduction mode at light load currents, and continuous conduction
mode at heavy load current. In discontinuous conduction mode, current through the output inductor starts at zero
and ramps up to a peak during the on-time, then ramps back to zero before the end of the off-time. The next on-
time period starts when the voltage at FB falls below the internal reference; until then, the inductor current stays
zero. In this mode, the operating frequency is lower than in continuous conduction mode and varies with load
current. Therefore, at light loads, the conversion efficiency is kept because the switching losses decrease with
the reduction in load and frequency. The discontinuous operating frequency can be calculated with Equation 5.
VOUT2 ìL ì1.04ì1020
RL ì(RT )2
≈
’
F =
∆
∆
«
÷
÷
◊
(5)
where
RL = the load resistance
•
In continuous conduction mode, current flows continuously through the inductor and never ramps down to zero.
In this mode the operating frequency is greater than the discontinuous mode frequency and stays relatively
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constant with load and line variations. The approximate continuous mode operating frequency can be calculated
with Equation 6.
≈
’
VOUT
F =
∆
∆
«
÷
÷
1.385ì10-10 ìRT ◊
(6)
The output voltage (VOUT) is programmed by two external resistors as shown in Figure 8-37. The regulation point
can be calculated with Equation 7.
VOUT = 2.5 × (RFB1 + RFB2) / RFB1
(7)
The LM5008A regulates the output voltage based on ripple voltage at the feedback input, requiring a minimum
amount of ESR for the output capacitor C2. A minimum of 25 mV to 50 mV of ripple voltage at the feedback pin
(FB) is required for the LM5008A. In cases where the capacitor ESR is too small, additional series resistance
may be required (R3 in the Figure 8-37).
For applications where lower output voltage ripple is required, the output can be taken directly from a low-ESR
output capacitor as shown in Figure 8-38. However, R3 slightly degrades the load regulation.
L1
SW
RFB2
R3
FB
VOUT2
RFB1
C2
Figure 8-38. Low-Ripple Output Configuration
8.3.5.2.2 Start-Up Regulator (VCC
)
The high voltage bias regulator is integrated within the LM5008A. The input pin (VIN) can be connected directly
to line voltages between 6 V and 95 V, with transient capability to 100 V. Referring to the Figure 8-37, when VIN
is between 6 V and the bypass threshold (nominally 8.5 V), the bypass switch (Q2) is on, and VCC tracks VIN
within 100 mV to 150 mV. The bypass switch on-resistance is approximately 100 Ω, with inherent current limiting
at approximately 100 mA. When VIN is above the bypass threshold Q2 is turned off, and VCC is regulated at 7 V.
The VCC regulator output current is limited at approximately 9.2 mA. When the LM5008A is shut down using the
RT/SD pin, the VCC bypass switch is shut off regardless of the voltage at VIN.
When VIN exceeds the bypass threshold, the time required for Q2 to shut off is approximately 2 µs to 3 µs. The
capacitor at VCC (C3) must be a minimum of 0.47 µF to prevent the voltage at VCC from rising above its
absolute maximum rating in response to a step input applied at VIN. C3 must be placed as near as possible to
the VCC and RTN pins. In applications with a relatively high input voltage, power dissipation in the bias regulator
is a concern. An auxiliary voltage of between 7.5 V and 14 V can be diode connected to the VCC pin to shut off
the VCC regulator, thereby reducing internal power dissipation. The current required into the VCC pin is shown in
the typical characteristics curves. Internally a diode connects VCC to VIN requiring that the auxiliary voltage be
less than VIN.
The turnon sequence is shown in Figure 8-39. During the initial delay (t1), VCC ramps up at a rate determined
by its current limit and C3 while internal circuitry stabilizes. When VCC reaches the upper threshold of its
undervoltage lockout (UVLO, typically 5.3 V), the buck switch is enabled. The inductor current increases to the
current limit threshold (ILIM), and during t2 the VOUT increases as the output capacitor charges up. When VOUT
reaches the intended voltage the average inductor current decreases (t3) to the nominal load current (IO).
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VIN
t1
7 V
UVLO
VCC
Vin
0 V
SW Pin
ILIM
Inductor
Current
IO
t3
t2
VOUT
Figure 8-39. Start-Up Sequence
8.3.5.2.3 Regulation Comparator
The feedback voltage at FB is compared to an internal 2.5-V reference. In normal operation (the output voltage
is regulated), an on-time period is initiated when the voltage at FB falls below 2.5 V. The buck switch stays on for
the on-time, causing the FB voltage to rise above 2.5 V. After the on-time period, the buck switch stays off until
the FB voltage again falls below 2.5 V. During start-up, the FB voltage is below 2.5 V at the end of each on-time,
resulting in the minimum off-time of 300 ns. Bias current at the FB pin is nominally 100 nA.
8.3.5.2.4 Overvoltage Comparator
The feedback voltage at FB is compared to an internal 2.875-V reference. If the voltage at FB rises above 2.875
V, the on-time pulse is immediately terminated. This condition can occur if the input voltage or the output load
change suddenly. The buck switch does not turn on again until the voltage at FB falls below 2.5 V.
8.3.5.2.5 On-Time Generator and Shutdown
The on-time for the LM5008A is determined by the RT resistor and is inversely proportional to the input voltage
(VIN), resulting in an almost constant frequency as Vin is varied over its range. The on-time equation for the
LM5008A is Equation 8.
TON = 1.385 × 10–10 × RT / VIN
(8)
RT must be selected for a minimum on-time (at maximum VIN) greater than 400 ns, for correct current limit
operation. This requirement limits the maximum frequency for each application, depending on VIN and VOUT
.
The LM5008A can be remotely disabled by taking the RT/SD pin to ground. See Figure 8-40. The voltage at the
RT/SD pin is between 1.5 V and 3 V, depending on VIN and the value of the RT resistor.
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Input
Voltage
VIN
RT
RT/SD
STOP
RUN
Figure 8-40. Shutdown Implementation
8.3.5.2.6 Current Limit
The LM5008A has an intelligent current limit OFF timer. If the current in the Buck switch exceeds 0.51 A the
present cycle is immediately terminated and a non-resetable OFF timer is initiated. The length of off-time is
controlled by an external resistor (RCL) and the FB voltage. When FB = 0 V, a maximum off-time is required, and
the time is preset to 35 µs. This condition occurs when the output is shorted and during the initial part of start-up.
This amount of time makes sure that safe short-circuit operation occurs up to the maximum input voltage of 95 V.
In cases of overload where the FB voltage is above zero volts (not a short circuit), the current limit off-time is less
than 35 µs. Reducing the off-time during less severe overloads decreases the amount of foldback, recovery
time, and the start-up time. The off-time is calculated from Equation 9.
≈
’
÷
÷
÷
÷
∆
∆
10-5
TOFF
=
∆
VFB
6.35ì10-6 ìRCL
∆ 0.285 +
∆
÷
«
◊
(9)
The current limit-sensing circuit is blanked for the first 50 ns to 70 ns of each on-time, so it is not falsely tripped
by the current surge which occurs at turnon. The current surge is required by the re-circulating diode (D1) for its
turnoff recovery.
8.3.5.2.7 N-Channel Buck Switch and Driver
The LM5008A integrates an N-Channel Buck switch and associated floating high voltage gate driver. The gate
driver circuit works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A 0.01-
µF ceramic capacitor (C4) connected between the BST pin and SW pin provides the voltage to the driver during
the on-time.
During each off-time, the SW pin is at approximately 0 V and the bootstrap capacitor charges from VCC through
the internal diode. The minimum off-timer, set to 300 ns, makes sure that a minimum time each cycle to recharge
the bootstrap capacitor.
The internal precharge switch at the SW pin is turned on for ≊ 150 ns during the minimum off-time period,
ensuring sufficient voltage exists across the bootstrap capacitor for the on-time. This feature helps prevent
operating problems which can occur during very light-load conditions, involving a long off-time, during which the
voltage across the bootstrap capacitor could otherwise decrease to less than the threshold for the gate drive
UVLO. The precharge switch also helps prevent start-up problems which can occur if the output voltage is
precharged prior to turnon. After current limit detection, the precharge switch is turned on for the entire duration
of the forced off-time.
8.3.5.2.8 Thermal Protection
The LM5008A must be operated so the junction temperature does not exceed 125°C during normal operation.
An internal Thermal Shutdown circuit is provided to shutdown the LM5008A in the event of a higher than normal
junction temperature. When activated, typically at 165°C, the controller is forced into a low-power reset state by
disabling the buck switch. This feature prevents catastrophic failures from accidental device overheating. When
the junction temperature decreases below 140°C (typical hysteresis = 25°C), normal operation continues.
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8.3.6 Gate Driver Protective Circuits
The DRV835xF family of devices are fully protected against VM undervoltage, charge pump and low-side
regulator undervoltage, MOSFET VDS overcurrent, gate driver shorts, and overtemperature events.
8.3.6.1 VM Supply and VDRAIN Undervoltage Lockout (UVLO)
If at any time the input supply voltage on the VM pin falls below the VVM_UV threshold or voltage on VDRAIN pin
falls below the VVDR_UV, all of the external MOSFETs are disabled, the charge pump is disabled, and the
nFAULT pin is driven low. The FAULT and UVLO bits are also latched high in the registers on SPI devices.
Normal operation continues (gate driver operation and the nFAULT pin is released) when the undervoltage
condition is removed. The UVLO bit stays set until cleared through the CLR_FLT bit or an ENABLE pin reset
pulse (tRST).
VM supply or VDRAIN undervoltage may also lead to VCP charge pump or VGLS regulator undervoltage
conditions to report. This behavior is expected because the VCP and VGLS supply voltages are dependent on
VM and VDRAIN pin voltages.
8.3.6.2 VCP Charge-Pump and VGLS Regulator Undervoltage Lockout (GDUV)
If at any time the voltage on the VCP pin (charge pump) falls below the VVCP_UV threshold or voltage on the
VGLS pin falls below the VVGLS_UV threshold, all of the external MOSFETs are disabled and the nFAULT pin is
driven low. The FAULT and GDUV bits are also latched high in the registers on SPI devices. Normal operation
continues (gate-driver operation and the nFAULT pin is released) when the undervoltage condition is removed.
The GDUV bit stays set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST). Setting the
DIS_GDUV bit high on the SPI devices disables this protection feature. On hardware interface devices, the
GDUV protection is always enabled.
8.3.6.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
A MOSFET overcurrent event is sensed by monitoring the VDS voltage drop across the external MOSFET
RDS(on). If the voltage across an enabled MOSFET exceeds the VVDS_OCP threshold for longer than the tOCP_DEG
deglitch time, a VDS_OCP event is recognized and action is done according to the OCP_MODE. On hardware
interface devices, the VVDS_OCP threshold is set with the VDS pin, the tOCP_DEG is fixed at 4 µs, and the
OCP_MODE is configured for 8-ms automatic retry but can be disabled by tying the VDS pin to DVDD. On SPI
devices, the VVDS_OCP threshold is set through the VDS_LVL SPI register, the tOCP_DEG is set through the
OCP_DEG SPI register, and the OCP_MODE bit can operate in four different modes: VDS latched shutdown,
VDS automatic retry, VDS report only, and VDS disabled.
The MOSFET VDS overcurrent protection operates in cycle-by-cycle (CBC) mode by default. This can be
disabled on SPI device variants through the SPI registers. When in cycle-by-cycle (CBC) mode a new rising
edge on the PWM inputs will clear an existing overcurrent fault.
Additionally, on SPI devices the OCP_ACT register setting can be set to change the VDS_OCP overcurrent
response between linked and individual shutdown modes. When OCP_ACT is 0, a VDS_OCP fault will only
effect the half-bridge in which it occurred. When OCP_ACT is 1, all three half-bridges will respond to a
VDS_OCP fault on any of the other half-bridges. OCP_ACT defaults to 0, individual shutdown mode.
8.3.6.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation continues (gate driver operation and the nFAULT pin is released) when the VDS_OCP condition is
removed and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.3.2 VDS Automatic Retry (OCP_MODE = 01b)
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation continues automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time
elapses. The FAULT, VDS_OCP, and MOSFET OCP bits stay latched until the tRETRY period expires.
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8.3.6.3.3 VDS Report Only (OCP_MODE = 10b)
No protective action occurs after a VDS_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT, VDS_OCP, and corresponding MOSFET OCP bits high in the SPI
registers. The gate drivers continue to operate as normal. The external controller manages the overcurrent
condition by acting appropriately. The reporting clears (nFAULT pin is released) when the VDS_OCP condition is
removed and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.3.4 VDS Disabled (OCP_MODE = 11b)
No action occurs after a VDS_OCP event in this mode.
8.3.6.4 VSENSE Overcurrent Protection (SEN_OCP)
Half-bridge overcurrent is also monitored by sensing the voltage drop across the external current-sense resistor
with the SP pin. If at any time, the voltage on the SP input of the current-sense amplifier exceeds the VSEN_OCP
threshold for longer than the tOCP_DEG deglitch time, a SEN_OCP event is recognized and action is done
according to the OCP_MODE. On hardware interface devices, the VSENSE threshold is fixed at 1 V, tOCP_DEG is
fixed at 4 µs, and the OCP_MODE for VSENSE is fixed for 8-ms automatic retry. On SPI devices, the VSENSE
threshold is set through the SEN_LVL SPI register, the tOCP_DEG is set through the OCP_DEG SPI register, and
the OCP_MODE bit can operate in four different modes: VSENSE latched shutdown, VSENSE automatic retry,
VSENSE report only, and VSENSE disabled.
The VSENSE overcurrent protection operates in cycle-by-cycle (CBC) mode by default. This can be disabled on
SPI device variants through the SPI registers. When in cycle-by-cycle (CBC) mode a new rising edge on the
PWM inputs will clear an existing overcurrent fault.
Additionally, on SPI devices the OCP_ACT register setting can be set to change the SEN_OCP overcurrent
response between linked and individual shutdown modes. When OCP_ACT is 0, a SEN_OCP fault will only
effect the half-bridge in which it occurred. When OCP_ACT is 1, all three half-bridges will respond to a
SEN_OCP fault on any of the other half-bridges. OCP_ACT defaults to 0, individual shutdown mode.
8.3.6.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT and SEN_OCP bits are latched high in the SPI registers. Normal operation continues (gate driver
operation and the nFAULT pin is released) when the SEN_OCP condition is removed and a clear faults
command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, SEN_OCP, and corresponding sense OCP bits are latched high in the SPI registers. Normal
operation continues automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time
elapses. The FAULT , SEN_OCP, and sense OCP bits stay latched until the tRETRY period expires.
8.3.6.4.3 VSENSE Report Only (OCP_MODE = 10b)
No protective action occurs after a SEN_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT and SEN_OCP bits high in the SPI registers. The gate drivers
continue to operate. The external controller manages the overcurrent condition by acting appropriately. The
reporting clears (nFAULT released) when the SEN_OCP condition is removed and a clear faults command is
issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.6.4.4 VSENSE Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
No action occurs after a SEN_OCP event in this mode. The SEN_OCP bit can be disabled independently of the
VDS_OCP bit by using the DIS_SEN SPI register.
8.3.6.5 Gate Driver Fault (GDF)
The GHx and GLx pins are monitored such that if the voltage on the external MOSFET gate does not increase or
decrease after the tDRIVE time, a gate driver fault is detected. This fault may be encountered if the GHx or GLx
pins are shorted to the PGND, SHx, or VM pins. Additionally, a gate driver fault may be encountered if the
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selected IDRIVE setting is not sufficient to turn on the external MOSFET within the tDRIVE period. After a gate drive
fault is detected, all external MOSFETs are disabled and the nFAULT pin driven low. In addition, the FAULT,
GDF, and corresponding VGS bits are latched high in the SPI registers. Normal operation continues (gate driver
operation and the nFAULT pin is released) when the gate driver fault condition is removed and a clear faults
command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). On SPI devices, setting the
DIS_GDF_UVLO bit high disables this protection feature.
Gate driver faults can indicate that the selected IDRIVE or tDRIVE settings are too low to slew the external
MOSFET in the desired time. Increasing either the IDRIVE or tDRIVE setting can resolve gate driver faults in these
cases. Alternatively, if a gate-to-source short occurs on the external MOSFET, a gate driver fault is reported
because of the MOSFET gate not turning on.
8.3.6.6 Overcurrent Soft Shutdown (OCP Soft)
In the case of a MOSFET VDS or VSENSE overcurrent fault the driver uses a special shutdown sequence to
protect the driver and MOSFETs from large voltage switching transients. These large voltage transients can be
created when rapidly switching off the external MOSFETs when a large drain to source current is present, such
as during an overcurrent event.
To mitigate this issue, the DRV835xF family of devices reduce the IDRIVEN pull down current setting for both the
high-side and low-side gate drivers during the MOSFET turn off in response to the fault event. If the programmed
IDRIVEN value is less than 1100 mA, the IDRIVEN value is set to the minimum IDRIVEN setting. If the programmed
IDRIVEN value is greater than or equal to 1100mA, the IDRIVEN value is reduced by seven code settings.
8.3.6.7 Thermal Warning (OTW)
If the die temperature exceeds the trip point of the thermal warning (TOTW), the OTW bit is set in the registers of
SPI devices. The device does no additional action and continues to function. When the die temperature falls
below the hysteresis point of the thermal warning, the OTW bit clears automatically. The OTW bit can also be
configured to report on the nFAULT pin and FAULT bit by setting the OTW_REP bit to 1 through the SPI
registers.
8.3.6.8 Thermal Shutdown (OTSD)
If the die temperature exceeds the trip point of the thermal shutdown limit (TOTSD), all the external MOSFETs are
disabled, the charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and TSD bits
are latched high. Normal operation continues (gate driver operation and the nFAULT pin is released) when the
overtemperature condition is removed. The TSD bit stays latched high indicating that a thermal event occurred
until a clear fault command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). This
protection feature cannot be disabled.
8.3.6.9 Fault Response Table
Table 8-6. Fault Action and Response
FAULT
CONDITION
CONFIGURATION
REPORT
GATE DRIVER
RECOVERY
VM Undervoltage
(VM_UV)
Automatic:
VVM > VVM_UV
VVM < VVM_UV
—
nFAULT
Hi-Z
VDRAIN Undervoltage
(VDR_UV)
Automatic:
VVM > VVDR_UV
VVDRAIN < VVDR_UV
—
nFAULT
Hi-Z
DIS_GDUV = 0b
DIS_GDUV = 1b
DIS_GDUV = 0b
DIS_GDUV = 1b
nFAULT
None
Hi-Z
Active
Hi-Z
Charge Pump Undervoltage
(VCP_UV)
Automatic:
VVCP > VVCP_UV
VVCP < VVCP_UV
nFAULT
None
VGLS Regulator Undervoltage
(VGLS_UV)
Automatic:
VVGLS > VVGLS_UV
VVGLS < VVGLS_UV
Active
Latched:
CLR_FLT, ENABLE Pulse
OCP_MODE = 00b
OCP_MODE = 01b
nFAULT
nFAULT
Hi-Z
Hi-Z
Retry:
tRETRY
VDS Overcurrent
(VDS_OCP)
VDS > VVDS_OCP
OCP_MODE = 10b
OCP_MODE = 11b
nFAULT
None
Active
Active
No action
No action
VSENSE Overcurrent
(SEN_OCP)
Latched:
CLR_FLT, ENABLE Pulse
VSP > VSEN_OCP
OCP_MODE = 00b
nFAULT
Hi-Z
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Table 8-6. Fault Action and Response (continued)
FAULT
CONDITION
CONFIGURATION
OCP_MODE = 01b
OCP_MODE = 10b
REPORT
nFAULT
nFAULT
None
GATE DRIVER
RECOVERY
Retry:
tRETRY
Hi-Z
Active
No action
No action
Latched:
OCP_MODE = 11b or
DIS_SEN = 1b
Active
DIS_GDF = 0b
DIS_GDF = 1b
OTW_REP = 1b
OTW_REP = 0b
—
nFAULT
None
Hi-Z
Active
Active
Active
Hi-Z
Gate Driver Fault
(GDF)
CLR_FLT, ENABLE Pulse
VGS Stuck > tDRIVE
No action
Automatic:
TJ < TOTW – THYS
nFAULT
None
Thermal Warning
(OTW)
TJ > TOTW
No action
Thermal Shutdown
(OTSD)
Automatic:
TJ < TOTSD – THYS
TJ > TOTSD
nFAULT
8.4 Device Functional Modes
8.4.1 Gate Driver Functional Modes
8.4.1.1 Sleep Mode
The ENABLE pin manages the state of the DRV835xF family of devices. When the ENABLE pin is low, the
device goes to a low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are
disabled, the VCP charge pump and VGLS regulator are disabled, the DVDD regulator is disabled, the sense
amplifiers are disabled, and the SPI bus is disabled. In sleep mode all the device registers will reset to their
default values. The tSLEEP time must elapse after a falling edge on the ENABLE pin before the device goes to
sleep mode. The device comes out of sleep mode automatically if the ENABLE pin is pulled high. The tWAKE time
must elapse before the device is ready for inputs.
In sleep mode and when VVM < VUVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are
pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an
internal resistor.
8.4.1.2 Operating Mode
When the ENABLE pin is high and VVM > VUVLO, the device goes to operating mode. The tWAKE time must
elapse before the device is ready for inputs. In this mode the charge pump, low-side gate regulator, DVDD
regulator, and SPI bus are active
8.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
In the case of device latched faults, the DRV835xF family of devices goes to a partial shutdown state to help
protect the external power MOSFETs and system.
When the fault condition has been removed the device can reenter the operating state by either setting the
CLR_FLT SPI bit on SPI devices or issuing a result pulse to the ENABLE pin on either interface variant. The
ENABLE reset pulse (tRST) consists of a high-to-low-to-high transition on the ENABLE pin. The low period of the
sequence should fall with the tRST time window or else the device will start the complete shutdown sequence.
The reset pulse has no effect on any of the regulators, device settings, or other functional blocks
8.4.2 Buck Regulator Functional Modes
8.4.2.1 Shutdown Mode
The RT/SD pin provides ON and OFF control for the LM5008A. When VSD is below approximately 0.7 V, the
device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in
shutdown mode drops to 110 µA (typical) at VIN = 48 V. The LM5008A also employs VCC bias rail undervoltage
protection. If the VCC bias supply voltage is below its UV threshold, the regulator stays off.
8.4.2.2 Active Mode
LM5008A is in active mode when the internal bias rail, VCC, is above its UV threshold. Depending on the load
current, the device operates in either DCM or CCM mode.
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Whenever the load current is decreased to a level less than half the peak-to-peak inductor ripple current, the
device goes to discontinuous conduction mode (DCM). Calculate the critical conduction boundary using
Equation 10.
VOUT ì 1-D
(
)
DIL
2
IBOUNDARY
=
=
2 ì LF ì fSW
(10)
When the inductor current reaches zero, the SW node becomes high impedance. Resonant ringing occurs at
SW as a result of the LC tank circuit formed by the buck inductor and the parasitic capacitance at the SW node.
At light loads, several pulses may be skipped in between switching cycles, effectively reducing the switching
frequency and further improving light-load efficiency.
8.5 Programming
This section applies only to the DRV835xF SPI devices.
8.5.1 SPI Communication
8.5.1.1 SPI
On DRV835xF SPI devices, an SPI bus is used to set device configurations, operating parameters, and read out
diagnostic information. The SPI operates in slave mode and connects to a master controller. The SPI input data
(SDI) word consists of a 16 bit word, with a 5 bit command and 11 bits of data. The SPI output data (SDO) word
consists of 11-bit register data. The first 5 bits are don’t care bits.
A valid frame must meet the following conditions:
•
•
•
The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
The nSCS pin should be pulled high for at least 400 ns between words.
When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is set
Hi-Z.
•
•
•
•
•
Data is captured on the falling edge of SCLK and data is propagated on the rising edge of SCLK.
The most significant bit (MSB) is shifted in and out first.
A full 16 SCLK cycles must occur for transaction to be valid.
If the data word sent to the SDI pin is not 16 bits, a frame error occurs and the data word is ignored.
For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 5 bit command data.
•
The SDO pin is an open-drain output and requires an external pullup resistor.
8.5.1.1.1 SPI Format
The SDI input data word is 16 bits long and consists of the following format:
•
•
•
1 read or write bit, W (bit B15)
4 address bits, A (bits B14 through B11)
11 data bits, D (bits B11 through B0)
Set the read/write bit (W0, B15) to 0b for a write command. Set the read/write bit (W0, B15) to 1b for a read
command.
The SDO output data word is 16 bits long and the first 5 bits are don't care bits. The response word is the data
currently in the register being accessed.
Table 8-7. SDI Input Data Word Format
R/W
B15
W0
ADDRESS
DATA
B14
A3
B13
A2
B12
A1
B11
A0
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
D5
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Table 8-8. SDO Output Data Word Format
DON'T CARE BITS
DATA
B15
X
B14
X
B13
X
B12
X
B11
X
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
D5
nSCS
SCLK
SDI
X
Z
MSB
LSB
X
Z
MSB
LSB
SDO
Capture
Point
Propagate
Point
Figure 8-41. SPI Slave Timing Diagram
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8.6 Register Maps
This section applies only to the DRV835xF SPI devices.
Note
Do not modify reserved registers or addresses not listed in the register maps . Writing to these registers may have unintended effects. For all
reserved bits, the default value is 0. To help prevent erroneous SPI writes from the master controller, set the LOCK bits to lock the SPI
registers.
Table 8-9. Register Map
Name
10
9
8
7
6
5
4
3
2
1
0
Type
Address
DRV8350FS, DRV8350RFS
Fault Status 1
VGS Status 2
Driver Control
Gate Drive HS
Gate Drive LS
OCP Control
Reserved
FAULT
SA_OC
VDS_OCP
SB_OC
GDF
UVLO
OTW
OTSD
GDUV
VDS_HA
VGS_HA
VDS_LA
VGS_LA
VDS_HB
VGS_HB
VDS_LB
VGS_LB
COAST
VDS_HC
VGS_HC
BRAKE
VDS_LC
VGS_LC
CLR_FLT
R
0h
1h
2h
3h
4h
5h
6h
7h
SC_OC
DIS_GDF
R
OCP_ACT
DIS_GDUV
LOCK
OTW_REP
PWM_MODE
1PWM_COM
1PWM_DIR
RW
RW
RW
RW
RW
RW
IDRIVEP_HS
IDRIVEP_LS
IDRIVEN_HS
CBC
TDRIVE
DEAD_TIME
IDRIVEN_LS
VDS_LVL
TRETRY
OCP_MODE
OCP_DEG
Reserved
Reserved
DRV8353FS, DRV8353RFS
Reserved
Fault Status 1
VGS Status 2
Driver Control
Gate Drive HS
Gate Drive LS
OCP Control
CSA Control
Reserved
FAULT
SA_OC
VDS_OCP
GDF
UVLO
OTW
OTSD
GDUV
VDS_HA
VGS_HA
VDS_LA
VDS_HB
VGS_HB
VDS_LB
VDS_HC
VGS_HC
BRAKE
VDS_LC
VGS_LC
CLR_FLT
R
0h
1h
2h
3h
4h
5h
6h
7h
SB_OC
DIS_GDUV
LOCK
SC_OC
DIS_GDF
VGS_LA
VGS_LB
COAST
R
OCP_ACT
OTW_REP
PWM_MODE
1PWM_COM
1PWM_DIR
RW
RW
RW
RW
RW
RW
IDRIVEP_HS
IDRIVEP_LS
IDRIVEN_HS
CBC
TDRIVE
DEAD_TIME
VREF_DIV LS_REF
IDRIVEN_LS
VDS_LVL
TRETRY
CSA_FET
OCP_MODE
CSA_GAIN
OCP_DEG
DIS_SEN CSA_CAL_A
Reserved
CSA_CAL_B
CSA_CAL_C
SEN_LVL
CAL_MODE
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8.6.1 Status Registers
The status registers are used to reporting warning and fault conditions. The status registers are read-only
registers
Complex bit access types are encoded to fit into small table cells. Table 8-10 shows the codes that are used for
access types in this section.
Table 8-10. Status Registers Access Type Codes
Access Type Code
Description
Read Type
R
R
Read
Reset or Default Value
-n
Value after reset or the default value
8.6.1.1 Fault Status Register 1 (address = 0x00h)
The fault status register 1 is shown in Figure 8-42 and described in Table 8-11.
Register access type: Read only
Figure 8-42. Fault Status Register 1
10
9
8
7
6
5
4
3
2
1
0
FAULT
R-0b
VDS_OCP
R-0b
GDF
R-0b
UVLO
R-0b
OTSD
R-0b
VDS_HA
R-0b
VDS_LA
R-0b
VDS_HB
R-0b
VDS_LB
R-0b
VDS_HC
R-0b
VDS_LC
R-0b
Table 8-11. Fault Status Register 1 Field Descriptions
Bit
Field
Type
Default
Description
10
FAULT
R
0b
Logic OR of FAULT status registers. Mirrors nFAULT pin.
Indicates VDS monitor overcurrent fault condition
Indicates gate drive fault condition
9
8
7
6
5
4
3
2
1
0
VDS_OCP
GDF
R
R
R
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
UVLO
Indicates undervoltage lockout fault condition
OTSD
Indicates overtemperature shutdown
VDS_HA
VDS_LA
VDS_HB
VDS_LB
VDS_HC
VDS_LC
Indicates VDS overcurrent fault on the A high-side MOSFET
Indicates VDS overcurrent fault on the A low-side MOSFET
Indicates VDS overcurrent fault on the B high-side MOSFET
Indicates VDS overcurrent fault on the B low-side MOSFET
Indicates VDS overcurrent fault on the C high-side MOSFET
Indicates VDS overcurrent fault on the C low-side MOSFET
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8.6.1.2 Fault Status Register 2 (address = 0x01h)
The fault status register 2 is shown in Figure 8-43 and described in Table 8-12.
Register access type: Read only
Figure 8-43. Fault Status Register 2
10
9
8
7
6
5
4
3
2
1
0
SA_OC
R-0b
SB_OC
R-0b
SC_OC
R-0b
OTW
R-0b
GDUV
R-0b
VGS_HA
R-0b
VGS_LA
R-0b
VGS_HB
R-0b
VGS_LB
R-0b
VGS_HC
R-0b
VGS_LC
R-0b
Table 8-12. Fault Status Register 2 Field Descriptions
Bit
Field
Type
Default
Description
10
SA_OC
SB_OC
SC_OC
R
0b
Indicates overcurrent on phase A sense amplifier (DRV8353xS
DRV8353xS-Q1)
9
8
R
R
0b
0b
Indicates overcurrent on phase B sense amplifier (DRV8353xS
DRV8353xS-Q1)
Indicates overcurrent on phase C sense amplifier (DRV8353xS
DRV8353xS-Q1)
7
6
OTW
R
R
0b
0b
Indicates overtemperature warning
GDUV
Indicates VCP charge pump and/or VGLS undervoltage fault
condition
5
4
3
2
1
0
VGS_HA
VGS_LA
VGS_HB
VGS_LB
VGS_HC
VGS_LC
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
Indicates gate drive fault on the A high-side MOSFET
Indicates gate drive fault on the A low-side MOSFET
Indicates gate drive fault on the B high-side MOSFET
Indicates gate drive fault on the B low-side MOSFET
Indicates gate drive fault on the C high-side MOSFET
Indicates gate drive fault on the C low-side MOSFET
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8.6.2 Control Registers
The control registers are used to configure the device. The control registers are read and write capable
Complex bit access types are encoded to fit into small table cells. Table 8-13 shows the codes that are used for
access types in this section.
Table 8-13. Control Registers Access Type Codes
Access Type Code
Description
Read Type
R
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default value
8.6.2.1 Driver Control Register (address = 0x02h)
The driver control register is shown in Figure 8-44 and described in Table 8-14.
Register access type: Read/Write
Figure 8-44. Driver Control Register
10
9
8
7
6
5
4
3
2
1
0
OCP
_ACT
DIS
_GDUV
DIS
_GDF
OTW
_REP
1PWM
_COM
1PWM
_DIR
CLR
_FLT
PWM_MODE
R/W-00b
COAST
R/W-0b
BRAKE
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
Table 8-14. Driver Control Field Descriptions
Bit
Field
Type
Default
Description
10
OCP_ACT
R/W
0b
0b = Associated half-bridge is shutdown in response to
VDS_OCP and SEN_OCP
1b = All three half-bridges are shutdown in response to
VDS_OCP and SEN_OCP
9
8
DIS_GDUV
DIS_GDF
R/W
R/W
R/W
R/W
0b
0b =VCP and VGLS undervoltage lockout fault is enabled
1b = VCP and VGLS undervoltage lockout fault is disabled
0b
0b = Gate drive fault is enabled
1b = Gate drive fault is disabled
7
OTW_REP
PWM_MODE
0b
0b = OTW is not reported on nFAULT or the FAULT bit
1b = OTW is reported on nFAULT and the FAULT bit
6-5
00b
00b = 6x PWM Mode
01b = 3x PWM mode
10b = 1x PWM mode
11b = Independent PWM mode
4
1PWM_COM
R/W
0b
0b = 1x PWM mode uses synchronous rectification
1b = 1x PWM mode uses asynchronous rectification
3
2
1
1PWM_DIR
COAST
R/W
R/W
R/W
0b
0b
0b
In 1x PWM mode this bit is ORed with the INHC (DIR) input
Write a 1 to this bit to put all MOSFETs in the Hi-Z state
BRAKE
Write a 1 to this bit to turn on all three low-side MOSFETs
This bit is ORed with the INLC (BRAKE) input in 1x PWM mode.
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Table 8-14. Driver Control Field Descriptions (continued)
Bit
Field
Type
Default
Description
0
CLR_FLT
R/W
0b
Write a 1 to this bit to clear latched fault bits.
This bit automatically resets after being writen.
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8.6.2.2 Gate Drive HS Register (address = 0x03h)
The gate drive HS register is shown in Figure 8-45 and described in Table 8-15.
Register access type: Read/Write
Figure 8-45. Gate Drive HS Register
10
9
8
7
6
5
4
3
2
1
0
LOCK
IDRIVEP_HS
R/W-1111b
IDRIVEn_HS
R/W-1111b
R/W-011b
Table 8-15. Gate Drive HS Field Descriptions
Bit
Field
Type
Default
Description
10-8
LOCK
R/W
011b
Write 110b to lock the settings by ignoring further register writes
except to these bits and address 0x02h bits 0-2.
Writing any sequence other than 110b has no effect when
unlocked.
Write 011b to this register to unlock all registers.
Writing any sequence other than 011b has no effect when
locked.
7-4
IDRIVEP_HS
R/W
1111b
0000b = 50 mA
0001b = 50 mA
0010b = 100 mA
0011b = 150 mA
0100b = 300 mA
0101b = 350 mA
0110b = 400 mA
0111b = 450 mA
1000b = 550 mA
1001b = 600 mA
1010b = 650 mA
1011b = 700 mA
1100b = 850 mA
1101b = 900 mA
1110b = 950 mA
1111b = 1000 mA
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Table 8-15. Gate Drive HS Field Descriptions (continued)
Bit
Field
Type
Default
Description
3-0
IDRIVEN_HS
R/W
1111b
0000b = 100 mA
0001b = 100 mA
0010b = 200 mA
0011b = 300 mA
0100b = 600 mA
0101b = 700 mA
0110b = 800 mA
0111b = 900 mA
1000b = 1100 mA
1001b = 1200 mA
1010b = 1300 mA
1011b = 1400 mA
1100b = 1700 mA
1101b = 1800 mA
1110b = 1900 mA
1111b = 2000 mA
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8.6.2.3 Gate Drive LS Register (address = 0x04h)
The gate drive LS register is shown in Figure 8-46 and described in Table 8-16.
Register access type: Read/Write
Figure 8-46. Gate Drive LS Register
10
9
8
7
6
5
4
3
2
1
0
CBC
TDRIVE
R/W-11b
IDRIVEP_LS
R/W-1111b
IDRIVEN_LS
R/W-1111b
R/W-1b
Table 8-16. Gate Drive LS Register Field Descriptions
Bit
Field
Type
Default
Description
10
CBC
R/W
1b
Active only when OCP_MODE = 01b
0b = For VDS_OCP and SEN_OCP, the fault is cleared after
tRETRY
1b = For VDS_OCP and SEN_OCP, the fault is cleared when
a new PWM input is given or after tRETRY
9-8
7-4
TDRIVE
R/W
R/W
11b
00b = 500-ns peak gate-current drive time
01b = 1000-ns peak gate-current drive time
10b = 2000-ns peak gate-current drive time
11b = 4000-ns peak gate-current drive time
IDRIVEP_LS
1111b
0000b = 50 mA
0001b = 50 mA
0010b = 100 mA
0011b = 150 mA
0100b = 300 mA
0101b = 350 mA
0110b = 400 mA
0111b = 450 mA
1000b = 550 mA
1001b = 600 mA
1010b = 650 mA
1011b = 700 mA
1100b = 850 mA
1101b = 900 mA
1110b = 950 mA
1111b = 1000 mA
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Table 8-16. Gate Drive LS Register Field Descriptions (continued)
Bit
Field
Type
Default
Description
3-0
IDRIVEN_LS
R/W
1111b
0000b = 100 mA
0001b = 100 mA
0010b = 200 mA
0011b = 300 mA
0100b = 600 mA
0101b = 700 mA
0110b = 800 mA
0111b = 900 mA
1000b = 1100 mA
1001b = 1200 mA
1010b = 1300 mA
1011b = 1400 mA
1100b = 1700 mA
1101b = 1800 mA
1110b = 1900 mA
1111b = 2000 mA
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8.6.2.4 OCP Control Register (address = 0x05h)
The OCP control register is shown in Figure 8-47 and described in Table 8-17.
Register access type: Read/Write
Figure 8-47. OCP Control Register
10
9
8
7
6
5
4
3
2
1
0
TRETRY
R/W-0b
DEAD_TIME
R/W-01b
OCP_MODE
R/W-01b
OCP_DEG
R/W-01b
VDS_LVL
R/W-1101b
Table 8-17. OCP Control Field Descriptions
Bit
Field
Type
Default
Description
10
TRETRY
R/W
0b
0b = VDS_OCP and SEN_OCP retry time is 8 ms
1b = VDS_OCP and SEN_OCP retry time is 50 µs
9-8
7-6
5-4
3-0
DEAD_TIME
R/W
R/W
R/W
R/W
01b
00b = 50-ns dead time
01b = 100-ns dead time
10b = 200-ns dead time
11b = 400-ns dead time
OCP_MODE
OCP_DEG
VDS_LVL
01b
00b = Overcurrent causes a latched fault
01b = Overcurrent causes an automatic retrying fault
10b = Overcurrent is report only but no action is taken
11b = Overcurrent is not reported and no action is taken
10b
00b = Overcurrent deglitch of 1 µs
01b = Overcurrent deglitch of 2 µs
10b = Overcurrent deglitch of 4 µs
11b = Overcurrent deglitch of 8 µs
1001b
0000b = 0.06 V
0001b = 0.07 V
0010b = 0.08 V
0011b = 0.09 V
0100b = 0.1 V
0101b = 0.2 V
0110b = 0.3 V
0111b = 0.4 V
1000b = 0.5 V
1001b = 0.6 V
1010b = 0.7 V
1011b = 0.8 V
1100b = 0.9 V
1101b = 1 V
1110b = 1.5 V
1111b = 2 V
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8.6.2.5 CSA Control Register (DRV8353F and DRV8353RF DRV8353F-Q1 and DRV8353RF-Q1 Only)
(address = 0x06h)
The CSA control register is shown in Figure 8-48 and described in Table 8-18.
Register access type: Read/Write
This register is only available with the DRV8353xF DRV8353x-Q1 family of devices.
Figure 8-48. CSA Control Register
10
9
8
7
6
5
4
3
2
1
0
CSA
_FET
VREF
_DIV
LS
_REF
CSA
_GAIN
DIS
_SEN
CSA
_CAL_A
CSA
_CAL_B
CSA
_CAL_C
SEN
_LVL
R/W-0b
R/W-1b
R/W-0b
R/W-10b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-11b
Table 8-18. CSA Control Field Descriptions
Bit
Field
Type
Default
Description
10
CSA_FET
VREF_DIV
LS_REF
R/W
0b
0b = Sense amplifier positive input is SPx
1b = Sense amplifier positive input is SHx (also automatically
sets the LS_REF bit to 1)
9
8
R/W
R/W
1b
0b
0b = Sense amplifier reference voltage is VREF (unidirectional
mode)
1b = Sense amplifier reference voltage is VREF divided by 2
0b = VDS_OCP for the low-side MOSFET is measured
across SHx to SPx
1b = VDS_OCP for the low-side MOSFET is measured across
SHx to SNx
7-6
CSA_GAIN
R/W
10b
00b = 5-V/V shunt amplifier gain
01b = 10-V/V shunt amplifier gain
10b = 20-V/V shunt amplifier gain
11b = 40-V/V shunt amplifier gain
5
4
DIS_SEN
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
11b
0b = Sense overcurrent fault is enabled
1b = Sense overcurrent fault is disabled
CSA_CAL_A
CSA_CAL_B
CSA_CAL_C
SEN_LVL
0b = Normal sense amplifier A operation
1b = Short inputs to sense amplifier A for offset calibration
3
0b = Normal sense amplifier B operation
1b = Short inputs to sense amplifier B for offset calibration
2
0b = Normal sense amplifier C operation
1b = Short inputs to sense amplifier C for offset calibration
1-0
00b = Sense OCP 0.25 V
01b = Sense OCP 0.5 V
10b = Sense OCP 0.75 V
11b = Sense OCP 1 V
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8.6.2.6 Driver Configuration Register (DRV8353F and DRV8353RF DRV8353F-Q1 and DRV8353RF-Q1
Only) (address = 0x07h)
The driver configuration register is shown in Figure 8-49 and described in Table 8-19.
Register access type: Read/Write
This register is only available with the DRV8353F and DRV8353RF DRV8353F-Q1 and DRV8353RF-Q1
devices.
Figure 8-49. Driver Configuration Register
10
9
8
7
6
5
4
3
2
1
0
CAL
_MODE
Reserved
R/W-000 0000 000b
R/W-0b
Table 8-19. Driver Configuration Field Descriptions
Bit
Field
Type
Default
Description
10-1
Reserved
R/W
000 0000
000b
Reserved
0
CAL_MODE
R/W
0b
0b = Amplifier calibration operates in manual mode
1b = Amplifier calibration uses internal auto calibration routine
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The DRV835xF family of devices are primarily used in three-phase brushless DC motor control applications. The
design procedures in the Section 9.2 section highlight how to use and configure the DRV835xF family of
devices.
9.2 Typical Application
9.2.1 Primary Application
The DRV8353RF is shown being used for a single supply, three-phase BLDC motor drive with individual half-
bridge current sense in this application example.
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LOUT
VCC
VM
DOUT
VM
CIN
ROUT
RFB1
1 …F
COUT
RFB2
1
36
35
34
33
32
31
30
29
28
27
26
25
GND
VGLS
CPL
CPH
VM
INHB
INLA
1 …F
2
3
INHA
47 nF
4
ENABLE
nSCS
SCLK
SDI
VM
5
0.1 …F
1 …F
6
VDRAIN
VCP
Thermal
Pad
VCC
1 kꢀ
7
VCC
10 kꢀ
8
GHA
GHA
SHA
SDO
9
SHA
GLA
SPA
SNA
nFAULT
AGND
VREF
SOA
10
11
12
GLA
VCC
1 …F
SPA
SNA
VM
CBULK
VM
VM
VM
VM
CBULK
CBYP
CBYP
CBYP
GHA
GHB
SHB
GHC
SHC
SHA
MOTA
MOTB
MOTC
GLA
SPA
GLB
SPB
GLC
SPC
R
R
R
SENC
SENA
SENB
SNA
SNB
SNC
Figure 9-1. Primary Application Schematic
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9.2.1.1 Design Requirements
Table 9-1 lists the example input parameters for the system design.
Table 9-1. Design Parameters
EXAMPLE DESIGN PARAMETER
Power supply voltage
REFERENCE
EXAMPLE VALUE
48 V
VVM, VVDRAIN, VVIN
MOSFET part number
MOSFET
Qg
CSD19535KCS
78 nC (typical) at VVGS = 10 V
13 nC (typical)
100 to 300 ns
50 to 150 ns
45 kHz
MOSFET total gate charge
MOSFET gate to drain charge
Target output rise time
Qgd
tr
Target output fall time
tf
PWM frequency
ƒPWM
VVCC
IVCC
Imax
Buck regulator output voltage
Buck regulator output current
Maximum motor current
ADC reference voltage
3.3 V
100 mA
100 A
VVREF
ISENSE
IRMS
PSENSE
TA
3.3 V
Winding sense current range
Motor RMS current
–40 A to +40 A
28.3 A
Sense resistor power rating
System ambient temperature
3 W
–20°C to +60°C
9.2.1.2 Detailed Design Procedure
Table 9-2 lists the recommended values of the external components for the gate driver. Table 9-3 lists the
recommended values of the external components for the buck regulator.
Table 9-2. DRV835xF Gate-Driver External Components
COMPONENTS
CVM1
PIN 1
PIN 2
RECOMMENDED
X5R or X7R, 0.1-µF, VM-rated capacitor
≥ 10 µF, VM-rated capacitor
X5R or X7R, 1-µF, 16-V capacitor
X5R or X7R, 1-µF, 16-V capacitor
X5R or X7R, 47-nF, VDRAIN-rated capacitor
X5R or X7R, 1-µF, 6.3-V capacitor
Pullup resistor
VM
GND
CVM2
VM
GND
CVCP
VCP
VM
CVGLS
VGLS
CPH
GND
CSW
CPL
CDVDD
RnFAULT
RSDO
DVDD
VCC(1)
VCC(1)
IDRIVE
VDS
DGND
nFAULT
SDO
Pullup resistor
RIDRIVE
RVDS
RMODE
RGAIN
GND or DVDD
GND or DVDD
GND or DVDD
GND or DVDD
GND or DGND
SNA and GND
SNB and GND
SNC and GND
DRV835xF hardware interface
DRV835xF hardware interface
DRV835xF hardware interface
DRV835xF hardware interface
Optional capacitor rated for VREF
Sense shunt resistor
MODE
GAIN
VREF
SPA
CVREF
RASENSE
RBSENSE
RCSENSE
SPB
Sense shunt resistor
SPC
Sense shunt resistor
(1) VCC is not a pin on the DRV835xF family of devices, but a VCC supply voltage pullup is required for the open-drain output nFAULT
and SDO. These pins can also be pulled up to DVDD.
Table 9-3. DRV835xR Buck Regulator External Components
COMPONENT
PIN 1
PIN 2
RECOMMENDED
(2)
CIN
VIN
GND
X5R or X7R, VIN-rated capacitor
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Table 9-3. DRV835xR Buck Regulator External Components (continued)
COMPONENT
PIN 1
PIN 2
RECOMMENDED
(2)
CBST
BST
SW
X5R or X7R, 0.01-µF, 16-V rated capacitor
X5R or X7R, 0.47-µF, 16-V rated capacitor
Schottky diode
(2)
CVCC
VCC
SW
GND
GND
OUT(1)
GND
GND
FB
(2)
DSW
(2)
LSW
SW
Output filter inductor
(2)
COUT
OUT(1)
OUT(1)
OUT(1)
FB
X5R or X7R, OUT-rated capacitor
Output ripple resistor
(2)
ROUT
(2)
RFB1
Resistor divider to set buck output voltage
(2)
RFB2
GND
(1) OUT is not a pin on the DRV8350RF and DRV8353RF devices, but the regulated output voltage of the buck regulator after the output
inductor.
(2) For detailed design procedures, refer to the LM5008A 100-V 350-mA Constant On-Time Buck Switching Regulator data sheet.
9.2.1.2.1 External MOSFET Support
The DRV835xF family of devices MOSFET support is based on the MOSFET gate charge, VCP charge-pump
capacity, VGLS regulator capacity, and output PWM switching frequency. For a quick calculation of MOSFET
driving capacity, use Equation 11 and Equation 12 for three phase BLDC motor applications.
Trapezoidal 120° Commutation: IVCP/VGLS > Qg × ƒPWM
Sinusoidal 180° Commutation: IVCP/VGLS > 3 × Qg × ƒPWM
(11)
(12)
where
•
•
•
•
ƒPWM is the maximum desired PWM switching frequency.
Qg is the MOSFET total gate charge
IVCP/VGLS is the charge pump or low-side regulator capacity, dependent on the VM pin voltage.
The MOSFET multiplier based on the commutation control method, may vary based on implementation.
9.2.1.2.1.1 MOSFET Example
If a system is using VVM = 48 V (IVCP = 25 mA) and a maximum PWM switching frequency of 45 kHz, then the
VCP charge-pump and VGLS regulator can support MOSFETs using trapezoidal commutation with a Qg < 556
nC, and MOSFETs using sinusoidal commutation with a Qg < 185 nC.
9.2.1.2.2 IDRIVE Configuration
The gate drive current strength, IDRIVE, is selected based on the gate-to-drain charge of the external MOSFETs
and the target rise and fall times at the outputs. If IDRIVE is selected to be too low for a given MOSFET, then the
MOSFET may not turn on completely within the tDRIVE time and a gate drive fault may be asserted. Additionally,
slow rise and fall times will lead to higher switching power losses. TI recommends adjusting these values in
system with the required external MOSFETs and motor to determine the best possible setting for any application.
The IDRIVEP and IDRIVEN current for both the low-side and high-side MOSFETs are independently adjustable on
SPI devices through the SPI registers. On hardware interface devices, both source and sink settings are
selected at the same time on the IDRIVE pin.
For MOSFETs with a known gate-to-drain charge Qgd, desired rise time (tr), and a desired fall time (tf), use
Equation 13 and Equation 14 to calculate the value of IDRIVEP and IDRIVEN (respectively).
Qgd
IDRIVEP
>
tr
(13)
Qgd
tf
IDRIVEN
>
(14)
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9.2.1.2.2.1 IDRIVE Example
Use Equation 15 and Equation 16 to calculate the value of IDRIVEP1 and IDRIVEP2 (respectively) for a gate to drain
charge of 13 nC and a rise time from 100 to 300 ns.
13 nC
IDRIVEP1
=
= 130 mA
= 43 mA
100 ns
(15)
13 nC
IDRIVEP2
=
300 ns
(16)
Select a value for IDRIVEP that is between 43 mA and 130 mA. For this example, the value of IDRIVEP was
selected as 100-mA source.
Use Equation 17 and Equation 18 to calculate the value of IDRIVEN1 and IDRIVEN2 (respectively) for a gate to drain
charge of 13 nC and a fall time from 50 to 150 ns.
13 nC
IDRIVEN1
=
= 260 mA
= 87 mA
50 ns
(17)
13 nC
IDRIVEN2
=
150 ns
(18)
Select a value for IDRIVEN that is between 87 mA and 260 mA. For this example, the value of IDRIVEN was
selected as 200-mA sink.
9.2.1.2.3 VDS Overcurrent Monitor Configuration
The VDS monitors are configured based on the worst-case motor current and the RDS(on) of the external
MOSFETs as shown in Equation 19.
VDS_OCP > Imax ì RDS(on)max
(19)
9.2.1.2.3.1 VDS Overcurrent Example
The goal of this example is to set the VDS monitor to trip at a current greater than 75 A. According to the
CSD19535KCS 100 V N-Channel NexFET™ Power MOSFET data sheet, the RDS(on) value is 2.2 times higher at
175°C, and the maximum RDS(on) value at a VGS of 10 V is 3.6 mΩ at TA = 25°C. From these values, the
approximate worst-case value of RDS(on) is 2.2 × 3.6 mΩ = 7.92 mΩ.
Using Equation 19 with a value of 7.92 mΩ for RDS(on) and a worst-case motor current of 75 A, Equation 20
shows the calculated desired value of the VDS overcurrent monitors.
VDS _ OCP > 75 A ì 7.92 mW
VDS _ OCP > 0.594 V
(20)
For this example, the value of VDS_OCP was selected as 0.6 V.
The SPI devices allow for adjustment of the deglitch time for the VDS overcurrent monitor. The deglitch time can
be set to 1 µs, 2 µs, 4 µs, or 8 µs.
9.2.1.2.4 Sense-Amplifier Bidirectional Configuration (DRV8353F and DRV8353RF)
The sense amplifier gain on the DRV8353F and DRV8353RF devices and sense resistor value are selected
based on the target current range, VREF reference voltage, sense-resistor power rating, and operating
temperature range. In bidirectional operation of the sense amplifier, the dynamic range at the output is
approximately calculated as shown in Equation 21.
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VVREF
VO = V
- 0.25 V -
(
)
VREF
2
(21)
Use Equation 22 to calculate the approximate value of the selected sense resistor with VO calculated using
Equation 21.
VO
2
R =
PSENSE > IRMS ì R
AV ì I
(22)
From Equation 21 and Equation 22, select a target gain setting based on the power rating of the target sense
resistor.
9.2.1.2.4.1 Sense-Amplifier Example
In this system example, the value of VREF voltage is 3.3 V with a sense current from –40 to +40 A. The linear
range of the SOx output is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification). The differential range of the
sense amplifier input is –0.3 to +0.3 V (VDIFF).
3.3 V
V = 3.3 V - 0.25 V -
= 1.4 V
(
)
O
2
(23)
(24)
(25)
1.4 V
AV ì 40 A
R =
2 W > 28.32 ì R ç R < 2.5 mW
1.4 V
AV ì 40 A
2.5 mW >
ç AV > 14
Therefore, the gain setting must be selected as 20 V/V or 40 V/V and the value of the sense resistor must be
less than 2.5 mΩ to meet the power requirement for the sense resistor. For this example, the gain setting was
selected as 20 V/V. The value of the resistor and worst case current can be verified that R < 2.5 mΩ and Imax
40 A does not violate the differential range specification of the sense amplifier input (VSPxD).
=
9.2.1.2.5 Single Supply Power Dissipation
Design care must be taken to make sure that the thermal ratings of the DRV835xF are not violated during
normal operation of the device. The is especially critical in higher voltage and higher ambient operation
applications where power dissipation or the device ambient temperature are increased.
To determine the temperature of the device in single supply operation, first the power internal power dissipation
must be calculated. The internal power dissipation has four primary components:
•
•
•
•
VCP charge pump power dissipation (PVCP
VGLS low-side regulator power dissipation (PVGLS
VM device nominal power dissipation (PVM
VIN buck regulator power dissipation (PBUCK
)
)
)
)
The values of PVCP and PVGLS can be approximated by referring to Section 9.2.1.2.1 to first determine IVCP and
IVGLS and then referring to Equation 26 and Equation 27.
PVCP = IVCP × (VVM + VVDRAIN
)
(26)
(27)
PVGLS = IVGLS × VVM
The value of PVM can be calculated by referring to the data sheet parameter for IVM current and Equation 28.
PVM = IVM × VVM
(28)
(29)
PBUCK = (PO / η) - PO
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where
•
PO = VVCC × IVCC
The value of PBUCK can be calculated with the buck output voltage (VVCC), buck output current (IVCC), and by
referring to the typical characteristic curve for efficiency (η) in the LM5008A data sheet.
The total power dissipation is then calculated by summing the four components as shown in Equation 30.
Ptot = PVCP + PVGLS + PVM + PBUCK
(30)
Lastly, the device junction temperature can be estimate by referring to Section 7.4 and Equation 31.
TJmax = TAmax + (RθJA × Ptot)
(31)
The information in Section 7.4 is based off of a standardized test metric for package and PCB thermal
dissipation. The actual values may vary based on the actual PCB design used in the application.
9.2.1.2.6 Single Supply Power Dissipation Example
In this application example the device is configured for single supply operation. This configuration requires only
one power supply for the DRV835xF but comes at the tradeoff of increased internal power dissipation. The
junction temperature is estimated in the example below.
Use Equation 11 to calculate the value of IVCP and IVGLS for a MOSFET gate charge of 78 nC, all 3 high-side and
3 low-side MOSFETs switching, and a switching frequency of 45 kHz.
IVCP/VGLS = 78 nC × 3 × 45 kHz = 10.5 mA
(32)
Use Equation 26, Equation 27, Equation 28, Equation 29, and Equation 30 to calculate the value of Ptot for VVM
=
VVDRAIN = VVIN = 48 V, IVM = 9.5 mA, IVCP = 10.5 mA, IVGLS = 10.5 mA, VVCC = 3.3 V, IVCC = 100 mA, and η = 86
%.
PVCP = 10.5 mA × (48 V + 48 V) = 1 W
PVGLS = 10.5 mA × 48 V = 0.5 W
(33)
(34)
(35)
(36)
(37)
PVM = 9.5 mA × 48 V = 0.5 W
PBUCK = [(3.3 V × 100 mA) / 0.86] – (3.3 V × 100 mA) = 0.054 W
Ptot = 1 W + 0.5 W + 0.5 W + 0.054 = 2.054 W
Lastly, to estimate the device junction temperature during operation, use Equation 31 to calculate the value of
TJmax for TAmax = 60°C, RθJA = 26.6°C/W for the RGZ package, and Ptot = 2.054 W. Again, please note that the
RθJA is highly dependent on the PCB design used in the actual application and should be verified. For more
information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics
application report.
TJmax = 60°C + (26.6°C/W × 2.054 W) = 115°C
(38)
As shown in this example, the device is within its operational limits, but is operating almost to its maximum
operational junction temperature. Design care should be taken in the single supply configuration to correctly
manage the power dissipation of the device.
9.2.1.2.7 Buck Regulator Configuration (DRV8350RF and DRV8353RF)
For a detailed design procedure and information on selecting the correct buck regulator external components,
refer to LM5008A 100-V 350-mA Constant On-Time Buck Switching Regulator.
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9.2.1.3 Application Curves
Figure 9-2. Gate Driver Operation 30% Duty Cycle Figure 9-3. Gate Driver Operation 90% Duty Cycle
Figure 9-4. IDRIVE Minimum Setting Positive
Current
Figure 9-5. IDRIVE Minimum Setting Negative
Current
Figure 9-6. IDRIVE 300-mA and 600-mA Setting
Positive Current
Figure 9-7. IDRIVE 300-mA and 600-mA Setting
Negative Current
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Figure 9-8. IDRIVE Maximum Setting Positive
Figure 9-9. IDRIVE Maximum Setting Negative
Current
Current
Figure 9-10. FOC Motor Commutation
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9.2.2 Alternative Application
In this application, the DRV8353RF is configured to use one sense amplifier in unidirectional mode for a
summing current sense scheme often used in trapezoidal or hall-based BLDC commutation control. Additionally,
the device is configured in dual supply mode using the integrated buck regulator for the VM gate drive voltage
supply to decrease internal power dissipation.
LOUT
VM
VM
VDRAIN
VDRAIN
CIN
External
LDO
ROUT
RFB1
DOUT
VCC
1 …F
CLIN
CLOUT
COUT
RFB2
1
36
35
34
33
32
31
30
29
28
27
26
25
GND
VGLS
CPL
CPH
VM
INHB
INLA
1 …F
2
3
INHA
47 nF
4
ENABLE
nSCS
SCLK
SDI
VM
5
VDRAIN
1 …F
0.1 …F
6
VDRAIN
VCP
Thermal
VCC
7
Pad
1 kꢀ
VCC
10 kꢀ
8
GHA
SHA
GLA
SPA
SNA
GHA
SHA
SDO
9
nFAULT
AGND
VREF
SOA
10
11
12
GLA
VCC
1 …F
SPA
SNA
VDRAIN
CBULK
VDRAIN
VDRAIN
VDRAIN
VDRAIN
CBULK
CBYP
CBYP
CBYP
GHA
GHB
SHB
GHC
SHC
SHA
MOTA
MOTB
MOTC
GLA
SPA
GLB
SPB
GLC
SPC
R
SEN
SNA
Figure 9-11. Alternative Application Schematic
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9.2.2.1 Design Requirements
Table 9-4 lists the example design input parameters for system design.
Table 9-4. Design Parameters
EXAMPLE DESIGN PARAMETER
Power supply voltage
REFERENCE
EXAMPLE VALUE
12 V
VVM
Buck supply voltage
VVIN
48 V
MOSFET drain voltage
MOSFET part number
VVDRAIN
MOSFET
Qg
48 V
CSD19535KCS
78 nC
MOSFET total gate charge
PWM frequency
fPWM
20 kHz
Buck regulator output voltage
Buck regulator output current
ADC reference voltage
Winding sense current range
Motor RMS current
VVCC
12 V
IVCC
150 mA
3.3 V
VVREF
ISENSE
IRMS
0 to 40 A
28.3 A
Sense-resistor power rating
System ambient temperature
PSENSE
TA
3 W
–20°C to +105°C
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Sense Amplifier Unidirectional Configuration
The sense amplifiers are configured to be unidirectional through the registers on SPI devices by writing a 0 to
the VREF_DIV bit.
The sense-amplifier gain and sense resistor values are selected based on the target current range, VREF,
sense-resistor power rating, and operating temperature range. In unidirectional operation of the sense amplifier,
use Equation 39 to calculate the approximate value of the dynamic range at the output.
V = V
- 0.25 V - 0.25 V = VVREF - 0.5 V
O
VREF
(39)
Use Equation 40 to calculate the approximate value of the selected sense resistor.
VO
2
R =
PSENSE > IRMS ì R
AV ì I
(40)
where
VO = VVREF - 0.5 V
•
From Equation 39 and Equation 40, select a target gain setting based on the power rating of a target sense
resistor.
9.2.2.2.1.1 Sense-Amplifier Example
In this system example, the value of VVREF is 3.3 V with a sense current from 0 to 40 A. The linear range of the
SOx output for the DRV8353x device is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification). The differential
range of the sense-amplifier input is –0.3 to +0.3 V (VDIFF).
VO = 3.3 V - 0.5 V = 2.8 V
(41)
2.8 V
R =
3 W > 28.32 ì R ç R < 3.75 mW
AV ì 40 A
(42)
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2.8 V
3.75 mW >
ç AV > 18.7
AV ì 40 A
(43)
Therefore, the gain setting must be selected as 20 V/V or 40 V/V and the value of the sense resistor must be
less than 3.75 mΩ to meet the power requirement for the sense resistor. For this example, the gain setting was
selected as 20 V/V. The value of the resistor and worst-case current can be verified that R < 3.75 mΩ and Imax
40 A does not violate the differential range specification of the sense amplifier input (VSPxD).
=
9.2.2.2.1.2 Dual Supply Power Dissipation
Design care must be taken to make sure that the thermal ratings of the DRV835xF are not violated during
normal operation of the device. The is especially critical in higher voltage and higher ambient operation
applications where power dissipation or the device ambient temperature are increased.
To determine the temperature of the device in dual supply operation, first the internal power dissipation must be
calculated. The internal power dissipation has four primary components:
•
•
•
•
VCP Charge pump power dissipation (PVCP
VGLS low-side regulator power dissipation (PVGLS
VM device nominal power dissipation (PVM
VIN buck regulator power dissipation (PBUCK
)
)
)
)
The value of PVCP and PVGLS can be approximated by referring to Section 9.2.1.2.1 to first determine IVCP and
IVGLS and then referring to Equation 44 and Equation 45.
PVCP = IVCP × (VVM + VVDRAIN
PVGLS = IVGLS × VVM
)
(44)
(45)
The value of PVM can be calculated by referring to the datasheet parameter for IVM current and Equation 46.
PVM = IVM × VVM
(46)
(47)
PBUCK = (PO / η) – PO
where
PO = VVCC × IVCC
•
The value of PBUCK can be calculated with the buck output voltage (VVCC), buck output current (IVCC), and by
referring to the typical characteristic curve for efficiency (η) in the LM5008A data sheet.
The total power dissipation is then calculated by summing the four components as shown in Equation 48.
Ptot = PVCP + PVGLS + PVM + PBUCK
(48)
Lastly, the device junction temperature can be estimate by referring to the Section 7.4 and Equation 49.
TJmax = TAmax + (RθJA × Ptot)
(49)
Note that the information in the Section 7.4 is based off of a standardized test metric for package and PCB
thermal dissipation. The actual values may vary based on the actual PCB design used in the application.
9.2.2.2.1.3 Dual Supply Power Dissipation Example
In this application example the device is configured for dual supply operation. dual supply operation helps to
decrease the internal power dissipation by providing the gate driver with a lower supply voltage. This can be
derived from the internal buck regulator or an external power supply. The junction temperature is estimated in
the example below.
Use Equation 11 to calculate the value of IVCP and IVGLS for a MOSFET gate charge of 78 nC, 1 high-side and 1
low-side MOSFETs switch at a time, and a switching frequency of 20 kHz.
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IVCP/VGLS = 78 nC × 1 × 20 kHz = 1.56 mA
(50)
Use equation Equation 44, Equation 45, Equation 46, Equation 47, and Equation 48 to calculate the value of Ptot
for VVM = 12 V, VVDRAIN = 48 V, VVIN = 48 V, IVM = 9.5 mA, IVCP = 1.56 mA, IVGLS = 1.56 mA, VVCC = 12 V, IVCC
150 mA, and η = 86 %.
=
PVCP = 1.56 mA × (12 V + 48 V) = 0.1 W
PVGLS = 1.56 mA × 12 V = 0.02 W
(51)
(52)
(53)
(54)
(55)
PVM = 9.5 mA × 12 V = 0.1 W
PBUCK = [(12 V × 150 mA) / 0.86] – (12 V × 150 mA) = 0.29 W
Ptot = 0.1 W + 0.02 W + 0.1 W + 0.29 = 0.51 W
Lastly, to estimate the device junction temperature during operation, use Equation 49 to calculate the value of
TJmax for TAmax = 105°C, RθJA = 26.6°C/W for the RGZ package, and Ptot = 0.51 W. Again, note that the RθJA
is highly dependent on the PCB design used in the actual application and should be verified. For more
information about traditional and new thermal metrics, refer to the Semiconductor and IC Package Thermal
Metrics application report.
TJmax = 105°C + (26.6°C/W × 0.51 W) = 119°C
(56)
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10 Power Supply Recommendations
The DRV835xF family of devices are designed to operate from an input voltage supply (VM) range between 9 V
and 75 V. A 0.1-µF ceramic capacitor rated for VM must be placed as near to the device as possible. In addition,
a bulk capacitor must be included on the VM pin but can be shared with the bulk bypass capacitance for the
external power MOSFETs. Additional bulk capacitance is required to bypass the external half-bridge MOSFETs
and should be sized according to the application requirements.
10.1 Bulk Capacitance Sizing
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is usually
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The
amount of local capacitance depends on a variety of factors including:
•
•
•
•
•
•
The highest current required by the motor system
The power supply's type, capacitance, and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable supply voltage ripple
Type of motor (brushed DC, brushless DC, stepper)
The motor startup and braking methods
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
stays stable and high current can be quickly supplied.
The data sheet provides a recommended minimum value, but system level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 10-1. Motor Drive Supply Parasitics Example
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11 Layout
11.1 Layout Guidelines
Bypass the VM pin to the GND pin using a low-ESR ceramic bypass capacitor with a recommended value of 0.1
µF. Place this capacitor as near to the VM pin as possible with a thick trace or ground plane connected to the
GND pin. Additionally, bypass the VM pin using a bulk capacitor rated for VM. This component can be
electrolytic. This capacitance must be at least 10 µF.
Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk
capacitance should be placed such that it minimizes the length of any high current paths through the external
MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB
layers. These practices minimize inductance and allow the bulk capacitor to deliver high current.
Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 47 nF, rated for
VDRAIN, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and
VDRAIN pins and VGLS and GNDs. These capacitors should be 1 µF, rated for 16 V, and be of type X5R or
X7R.
Bypass the DVDD pin to the GND/DGND pin with a 1-µF low-ESR ceramic capacitor rated for 6.3 V and of type
X5R or X7R. Place this capacitor as near to the pin as possible and minimize the path from the capacitor to the
GND/DGND pin.
The VDRAIN pin can be shorted directly to the VM pin for single supply application configurations. However, if a
significant distance is between the device and the external MOSFETs, use a dedicated trace to connect to the
common point of the drains of the high-side external MOSFETs. Do not connect the SLx pins directly to GND.
Instead, use dedicated traces to connect these pins to the sources of the low-side external MOSFETs. These
recommendations allow for more accurate VDS sensing of the external MOSFETs for overcurrent detection.
Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of
the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx
pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the
low-side MOSFET source back to the SPx/SLx pins.
11.1.1 Buck-Regulator Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI:
•
Put the feedback network resistors near the FB pin and away from the inductor to minimize coupling noise
into the feedback pin.
•
Put the input bypass capacitor near the VIN pin to decrease copper trace resistance which effects input
voltage ripple of the device.
•
•
Put the inductor near the SW pin to decrease magnetic and electrostatic noise.
Put the output capacitor near the junction of the inductor and the diode. The inductor, diode, and COUT trace
should be as short as possible to decrease conducted and radiated noise and increase overall efficiency.
Make the ground connection for the diode, CVIN, and COUT as small as possible and tie it to the system
ground plane in only one spot (preferably at the COUT ground point) to minimize conducted noise in the
system ground plane.
•
For more detail on switching power supply layout considerations refer to the AN-1149 Layout Guidelines for
Switching Power Supplies application report.
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11.2 Layout Example
S
S
S
G
D
D
D
D
D
D
D
D
G
S
S
S
24
23
22
21
20
19
18
17
16
15
14
13
37
SOB
SOC
SNC
SPC
GLC
SHC
GHC
GHB
SHB
GLB
SPB
SNB
INLB
38
INHC
39
INLC
40
D
D
D
D
G
S
S
S
DVDD
41
DGND
42
SW
Thermal Pad
43
VIN
44
VCC
45
BST
46
RCL
47
RT/SD
48
FB
VOUT
S
S
S
G
D
D
D
D
S
S
S
G
D
D
D
D
D
D
D
D
G
S
S
S
Figure 11-1. Layout Example
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SLVSFV1 – SEPTEMBER 2020
12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
The following figure shows a legend for interpreting the complete device name:
DRV83 (5) (3) (R) (S) (RGZ) (R)
Prefix
DRV83 œ Three Phase Brushless DC
Tape and Reel
R œ Tape and Reel
T œ Small Tape and Reel
Package
RTV œ 5 × 5 × 0.75 mm QFN
RTA œ 6 x 6 × 0.75 mm QFN
RGZ œ 7 × 7 × 0.9 mm QFN
Series
5 œ 100 V device
Interface
S œ SPI interface
H œ Hardware interface
Sense amplifiers
0 œ No sense amplifiers
3 œ 3x sense amplifiers
Buck Regulator
[blank] œ No buck regulator
R œ Buck regulator
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, refer to:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Texas Instruments, DRV8353Rx-EVM User’s Guide user's guide
Texas Instruments, DRV8353Rx-EVM GUI User’s Guide
Texas Instruments, DRV8353Rx-EVM InstaSPIN™ Software Quick Start Guide
Texas Instruments, DRV8350x-EVM User’s Guide user's guide
Texas Instruments, DRV8350x-EVM GUI User’s Guide user's guide
Texas Instruments, DRV8350x-EVM Sensorless Software User's Guide user's guide
Texas Instruments, DRV8350x-EVM Sensored Software User's Guide user's guide
Texas Instruments, LM5008A 100-V 350-mA Constant On-Time Buck Switching Regulator data sheet
Texas Instruments, CSD19535KCS 100 V N-Channel NexFET™ Power MOSFET data sheet
Texas Instruments, Understanding IDRIVE and TDRIVE In TI Motor Gate Drivers application report
Texas Instruments, Motor Drive Protection with TI Smart Gate Drive TI TechNote
Texas Instruments, Reduce Motor Drive BOM and PCB Area with TI Smart Gate Drive TI TechNote
Texas Instruments, Reducing EMI Radiated Emissions with TI Smart Gate Drive TI TechNote
Texas Instruments, Hardware Design Considerations for an Efficient Vacuum Cleaner using BLDC Motor
Texas Instruments, Hardware Design Considerations for an Electric Bicycle using BLDC Motor
Texas Instruments, Industrial Motor Drive Solution Guide
Texas Instruments, Layout Guidelines for Switching Power Supplies application report
Texas Instruments, QFN/SON PCB Attachment application report
Texas Instruments, Sensored 3-Phase BLDC Motor Control Using MSP430™ application report
Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies application report
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12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 12-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
DRV8350F
DRV8350RF
DRV8353F
DRV8353RF
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.6 Trademarks
NexFET™, InstaSPIN™, and MSP430™ are trademarks of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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5-Oct-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8350FHRTVR
DRV8350FSRTVR
DRV8350RFHRGZR
DRV8350RFSRGZR
DRV8353FHRTAR
DRV8353FSRTAR
DRV8353RFHRGZR
DRV8353RFSRGZR
ACTIVE
WQFN
WQFN
VQFN
VQFN
WQFN
WQFN
VQFN
VQFN
RTV
32
32
48
48
40
40
48
48
3000
3000
2500
2500
2000
2000
2500
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
8350FH
ACTIVE
RTV
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAUAG
NIPDAUAG
NIPDAU
8350FS
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
RGZ
RGZ
RTA
Green (RoHS
& no Sb/Br)
8350RFH
8350RFS
8353FH
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
RTA
Green (RoHS
& no Sb/Br)
NIPDAU
8353FS
RGZ
RGZ
Green (RoHS
& no Sb/Br)
NIPDAUAG
NIPDAUAG
8353RFH
8353RFS
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Oct-2020
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
RTV0032E
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.15
4.85
B
A
PIN 1 INDEX AREA
5.15
4.85
SIDE WALL LEAD
METAL THICKNESS
DIM A
0.8
0.7
OPTION 1
0.1
OPTION 2
0.2
C
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(DIM A) TYP
3.45 0.1
(0.2) TYP
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
2X
SYMM
33
3.5
0.30
32X
0.18
24
0.1
C A B
1
0.05
C
PIN 1 ID
(OPTIONAL)
32
25
SYMM
0.5
0.3
32X
4225196/A 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RTV0032E
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.24)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225196/A 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RTV0032E
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.24)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4225196/A 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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