DRV8434PRGER [TI]
DRV8434E/P Dual H-Bridge Motor Driver With Integrated Current Sense and Smart Tune Technology;
| 型号： | DRV8434PRGER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DRV8434E/P Dual H-Bridge Motor Driver With Integrated Current Sense and Smart Tune Technology |
| 文件： | 总48页 (文件大小：3464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV8434E
SLOSE49 – NOVEMBER 2020
DRV8434E/P Dual H-Bridge Motor Driver With Integrated Current Sense and Smart
Tune Technology
1 Features
3 Description
•
Dual H-bridge motor driver
– One bipolar stepper motor
The DRV8434E/P devices are dual H-bridge motor
drivers for a wide variety of industrial applications.
The devices can be used for driving two DC motors,
or a bipolar stepper motor.
– Dual bidirectional brushed-DC motors
– Four unidirectional brushed-DC motors
Integrated current sense functionality
– No sense resistors required
– ±4% Full-scale current accuracy
4.5-V to 48-V Operating supply voltage range
Multiple control interface options
•
The output stage of the driver consists of N-channel
power MOSFETs configured as two full H-bridges,
charge pump regulator, current sensing and
regulation, and protection circuitry. The integrated
current sensing uses an internal current mirror
architecture, removing the need for a large power
shunt resistor, saving board area and reducing system
cost. A low-power sleep mode is provided to achieve
ultra- low quiescent current draw by shutting down
most of the internal circuitry. Internal protection
features are provided for supply undervoltage lockout
(UVLO), charge pump undervoltage (CPUV), output
overcurrent (OCP), and device overtemperature
(TSD).
•
•
– PHASE/ENABLE (PH/EN)
– PWM (IN/IN)
•
•
•
Smart tune, fast and mixed decay options
Low RDS(ON): 330 mΩ HS + LS at 24 V, 25°C
High Current Capacity Per Bridge: 4-A peak
(brushed), 2.5-A Full-Scale (stepper)
Inrush current limiting in brushed-DC applications
Pin to pin compatible with -
•
•
The DRV8424E/P is capable of driving a stepper
motor with up to 2.5-A full scale or brushed motors
with up to 4-A peak (dependent on PCB design).
– DRV8426E/P: 33-V, 900 mΩ HS + LS
– DRV8436E/P: 48-V, 900 mΩ HS + LS
– DRV8424E/P: 33-V, 330 mΩ HS + LS
Configurable Off-Time PWM Chopping
– 7, 16, 24 or 32 μs
Supports 1.8-V, 3.3-V, 5.0-V logic inputs
Low-current sleep mode (2 µA)
Spread spectrum clocking for low EMI
Protection features
Device Information
•
PART NUMBER (1)
DRV8434EPWPR
DRV8434ERGER
DRV8434PPWPR
DRV8434PRGER
PACKAGE
HTSSOP (28)
VQFN (24)
BODY SIZE (NOM)
9.7mm x 4.4mm
4.0mm x 4.0mm
9.7mm x 4.4mm
4.0mm x 4.0mm
•
•
•
•
HTSSOP (28)
VQFN (24)
– VM undervoltage lockout (UVLO)
– Charge pump undervoltage (CPUV)
– Overcurrent protection (OCP)
– Thermal shutdown (OTSD)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
– Fault condition output (nFAULT)
2 Applications
•
•
•
•
•
•
Printers and scanners
ATMs and Textile Machines
Office and home automation
Factory automation and robotics
Major home appliances
Vacuum, humanoid, and robotics
Figure 3-1. DRV8434E Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Figure 3-2. DRV8434P Simplified Schematic
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 3
5 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 5
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings........................................ 7
6.2 ESD Ratings............................................................... 7
6.3 Recommended Operating Conditions.........................8
6.4 Thermal Information....................................................8
6.5 Electrical Characteristics.............................................9
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagrams....................................... 13
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................25
8 Application and Implementation..................................27
8.1 Application Information............................................. 27
8.2 Typical Application.................................................... 27
8.3 Alternate Application.................................................30
9 Power Supply Recommendations................................32
9.1 Bulk Capacitance......................................................32
10 Layout...........................................................................33
10.1 Layout Guidelines................................................... 33
10.2 Layout Example...................................................... 33
11 Mechanical, Packaging, and Orderable
Information.................................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
November 2020
*
Initial release.
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5 Pin Configuration and Functions
Figure 5-1. PWP PowerPAD™ Package 28-Pin HTSSOP Top View DRV8434E
Figure 5-2. RGE Package 24-Pin VQFN with Exposed Thermal PAD Top View DRV8434E
Figure 5-3. PWP PowerPAD™ Package 28-Pin HTSSOP Top View DRV8434P
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Figure 5-4. RGE Package 24-Pin VQFN with Exposed Thermal PAD Top View DRV8434P
Pin Functions
PIN
PWP
RGE
TYPE
DESCRIPTION
NAME
DRV8434E
DRV8434P
DRV8434E
DRV8434P
Decay mode setting pin. Set the decay mode
for bridge A; quad-level pin.
ADECAY
AEN
21
25
—
—
21
16
16
I
I
I
I
Bridge A enable input. Logic high enables
bridge A; logic low disables the bridge Hi-Z.
—
25
24
20
—
—
—
20
19
Bridge A PWM input. Logic controls the state
of H-bridge A; internal pulldown.
AIN1
Bridge B PWM input. Logic controls the state
of H-bridge B; internal pulldown.
AIN2
AOUT1
AOUT2
4, 5
6, 7
4, 5
6, 7
3
4
3
4
O
O
Winding A output. Connect to motor winding.
Winding A output. Connect to motor winding.
Bridge A phase input. Logic high drives
current from AOUT1 to AOUT2.
APH
24
18
—
19
13
—
I
I
Reference voltage input. Voltage on this pin
sets the full scale chopping current in H-
bridge A.
VREFA
18
13
Decay mode setting pin. Set the decay mode
for bridge B; quad-level pin.
BDECAY
BEN
20
23
—
—
20
—
23
22
15
18
—
—
15
—
18
17
I
I
I
I
Bridge B enable input. Logic high enables
bridge B; logic low disables the bridge Hi-Z.
Bridge B PWM input. Logic controls the state
of H-bridge B; internal pulldown.
BIN1
Bridge B PWM input. Logic controls the state
of H-bridge B; internal pulldown.
BIN2
BOUT1
BOUT2
10, 11
8, 9
10, 11
8, 9
6
5
6
5
O
O
Winding B output. Connect to motor winding.
Winding B output. Connect to motor winding.
Bridge B phase input. Logic high drives
current from BOUT1 to BOUT2.
BPH
22
17
—
17
12
—
I
I
Reference voltage input. Voltage on this pin
sets the full scale chopping current in H-
bridge B.
VREFB
17
12
CPH
CPL
GND
28
27
14
28
27
14
23
22
9
23
22
9
Charge pump switching node. Connect a
PWR X7R, 0.022-μF, VM-rated ceramic capacitor
from CPH to CPL.
PWR Device ground. Connect to system ground.
Sets the decay mode off-time during current
chopping; quad-level pin.
TOFF
19
19
14
14
I
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PIN
PWP
RGE
TYPE
DESCRIPTION
NAME
DRV8434E
DRV8434P
DRV8434E
DRV8434P
Logic supply voltage. Connect a X7R, 0.47-
DVDD
VCP
15
1
15
10
10
PWR μF to 1-μF, 6.3-V or 10-V rated ceramic
capacitor to GND.
Charge pump output. Connect a X7R, 0.22-
1
24
24
O
μF, 16-V ceramic capacitor to VM.
Power supply. Connect to motor supply
voltage and bypass to PGND with two 0.01-
μF ceramic capacitors (one for each pin) plus
VM
2, 13
2, 13
1, 8
1, 8
PWR
a bulk capacitor rated for VM.
PGND
3, 12
16
3, 12
16
2, 7
11
2, 7
11
PWR Power ground. Connect to system ground.
Fault indication. Pulled logic low with fault
nFAULT
O
condition; open-drain output requires an
external pullup resistor.
Sleep mode input. Logic high to enable
device; logic low to enter low-power sleep
mode; internal pulldown resistor. An nSLEEP
low pulse clears faults.
nSLEEP
PAD
26
-
26
-
21
-
21
-
I
-
Thermal pad. Connect to system ground.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range referenced with respect to GND (unless otherwise noted) (1)
MIN
MAX
UNIT
Power supply voltage (VM)
–0.3
–0.3
–0.3
–0.3
–0.3
50
VVM + 7
VVM
V
V
V
V
V
Charge pump voltage (VCP, CPH)
Charge pump negative switching pin (CPL)
nSLEEP pin voltage (nSLEEP)
Internal regulator voltage (DVDD)
VVM
5.75
Control pin voltage (APH, AEN, BPH, BEN, AIN1, AIN2, BIN1, BIN2, nFAULT,
ADECAY, BDECAY, TOFF)
–0.3
5.75
V
Open drain output current (nFAULT)
0
–0.3
–1
10
mA
V
Reference input pin voltage (VREFA, VREFB)
Continuous phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2)
Transient 100 ns phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2)
Peak drive current (AOUT1, AOUT2, BOUT1, BOUT2)
Operating ambient temperature, TA
5.75
VVM + 1
VVM + 3
V
–3
V
Internally Limited
A
–40
–40
–65
125
150
150
°C
°C
°C
Operating junction temperature, TJ
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
±2000
±750
±500
Electrostatic
discharge
Corner pins for PWP (1,
14, 15, and 28)
V(ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101
Other pins
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
0
MAX
48
UNIT
V
VVM
VI
Supply voltage range for normal (DC) operation
Logic level input voltage
5.5
V
VREF
ƒPWM
IFS
Reference rms voltage range (VREFA, VREFB)
Applied PWM signal (APH, AEN, BPH, BEN, AIN1, AIN2, BIN1, BIN2)
Motor full-scale current (xOUTx)
0.05
0
3.3
V
100
2.5
kHz
A
0
Irms
TA
Motor RMS current (xOUTx)
0
1.8
A
Operating ambient temperature
–40
–40
125
150
°C
°C
TJ
Operating junction temperature
6.4 Thermal Information
PWP (HTSSOP)
RGE (VQFN)
24 PINS
39.0
THERMAL METRIC
UNIT
28 PINS
29.7
23.0
9.3
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
28.9
RθJB
ψJT
Junction-to-board thermal resistance
16.0
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.3
0.4
ψJB
9.2
15.9
RθJC(bot) Junction-to-case (bottom) thermal resistance
2.4
3.4
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6.5 Electrical Characteristics
Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, DVDD)
IVM
VM operating supply current
nSLEEP = 1, No motor load
nSLEEP = 0
5
2
6.5
mA
μA
μs
μs
ms
ms
V
IVMQ
tSLEEP
tRESET
tWAKE
tON
VM sleep mode supply current
Sleep time
4
nSLEEP = 0 to sleep-mode
nSLEEP low to clear fault
nSLEEP = 1 to output transition
VM > UVLO to output transition
No external load, 6 V < VVM < 48 V
No external load, VVM = 4.5 V
120
nSLEEP reset pulse
Wake-up time
20
40
1.2
0.8
0.8
5
Turn-on time
1.2
4.75
4.2
5.25
VDVDD
Internal regulator voltage
4.35
V
CHARGE PUMP (VCP, CPH, CPL)
VVCP
f(VCP)
VCP operating voltage
6 V < VVM < 48 V
VVM + 5
360
V
Charge pump switching
frequency
VVM > UVLO; nSLEEP = 1
kHz
LOGIC-LEVEL INPUTS (APH, AEN, BPH, BEN, AIN1, AIN2, BIN1, BIN2, nSLEEP)
VIL
VIH
VHYS
IIL
Input logic-low voltage
Input logic-high voltage
Input logic hysteresis
Input logic-low current
Input logic-high current
Propagation delay
0
0.6
5.5
V
V
1.5
150
800
mV
μA
μA
ns
VIN = 0 V
–1
1
IIH
VIN = 5 V
100
tPD
xPH, xEN, xINx input to current change
QUAD-LEVEL INPUTS (ADECAY, BDECAY, TOFF)
VI1
VI2
VI3
VI4
IO
Input logic-low voltage
Tied to GND
0
0.6
1.4
2.2
5.5
V
V
330kΩ ± 5% to GND
Hi-Z (>500kΩ to GND)
Tied to DVDD
1
1.25
2
Input Hi-Z voltage
1.8
2.7
V
Input logic-high voltage
Output pull-up current
V
10
μA
CONTROL OUTPUTS (nFAULT)
VOL
IOH
Output logic-low voltage
Output logic-high leakage
IO = 5 mA
0.5
1
V
–1
μA
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
TJ = 25 °C, IO = -1 A
165
250
280
165
250
280
200
300
350
200
300
350
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
RDS(ONH)
High-side FET on resistance
TJ = 125 °C, IO = -1 A
TJ = 150 °C, IO = -1 A
TJ = 25 °C, IO = 1 A
TJ = 125 °C, IO = 1 A
TJ = 150 °C, IO = 1 A
RDS(ONL)
Low-side FET on resistance
Output slew rate
VM = 24V, IO = 1 A, Between 10% and
90%
tSR
240
V/µs
PWM CURRENT CONTROL (VREFA, VREFB)
KV
Transimpedance gain
VREF Leakage Current
VREF = 3.3 V
VREF = 3.3 V
1.254
1.32
1.386
8.25
V/A
μA
IVREF
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Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TOFF = 0
TOFF = 1
7
16
24
32
tOFF
PWM off-time
μs
TOFF = Hi-Z
TOFF = 330 kΩ to GND
0.25 A < IO < 0.5 A
0.5 A < IO < 1 A
–12
12
ΔITRIP
Current trip accuracy
–6
-4
6
4
%
%
1 A < IO < 2.5 A
AOUT and BOUT current
matching
IO,CH
IO = 2.5 A
–2.5
2.5
PROTECTION CIRCUITS
VM falling, UVLO falling
VM rising, UVLO rising
Rising to falling threshold
VCP falling
4.1
4.2
4.25
4.35
100
4.35
4.45
VUVLO
VM UVLO lockout
V
VUVLO,HYS Undervoltage hysteresis
mV
V
VCPUV
IOCP
Charge pump undervoltage
Overcurrent protection
Overcurrent deglitch time
Thermal shutdown
VVM + 2
Current through any FET
4
A
tOCP
2
μs
°C
°C
TOTSD
Die temperature TJ
Die temperature TJ
150
165
20
180
THYS_OTSD Thermal shutdown hysteresis
6.5.1 Typical Characteristics
Figure 6-1. Sleep Current over Supply Voltage
Figure 6-2. Sleep Current over Temperature
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6.5.1 Typical Characteristics (continued)
Figure 6-3. Operating Current over Supply Voltage
Figure 6-4. Operating Current over Temperature
Figure 6-5. Low-Side RDS(ON) over Supply Voltage
Figure 6-6. Low-Side RDS(ON) over Temperature
Figure 6-7. High-Side RDS(ON) over Supply Voltage
Figure 6-8. High-Side RDS(ON) over Temperature
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7 Detailed Description
7.1 Overview
The DRV8434E/P are integrated motor driver solutions for bipolar stepper motors or dual brushed-DC motors.
The devices integrate two N-channel power MOSFET H-bridges, integrated current sense and regulation
circuitry. The DRV8434E/P are pin-to-pin compatible with the DRV8426E/P, DRV8436E/P, and the
DRV8424E/P. The DRV8434E/P can be powered with a supply voltage between 4.5 and 48 V, and are capable
of providing an output current up to 4-A peak or 2.5-A full-scale. The actual full-scale and rms current depends
on the ambient temperature, supply voltage, and PCB thermal capability.
The DRV8434E/P devices use an integrated current-sense architecture which eliminates the need for two
external power sense resistors, hence saving significant board space, BOM cost, design efforts and reduces
significant power consumption. This architecture removes the power dissipated in the sense resistors by using a
current mirror approach and using the internal power MOSFETs for current sensing. The current regulation set
point is adjusted by the voltage at the VREFA and VREFB pins.
A simple PH/EN (DRV8434E) or PWM (DRV8434P) interface allows easy interfacing to the controller circuit.
The current regulation is highly configurable, with several decay modes of operation. The decay mode can be
selected as a smart tune Dynamic Decay, smart tune Ripple Control, mixed, or fast decay. The PWM off-time,
tOFF, can be adjusted to 7, 16, 24, or 32 μs.
A low-power sleep mode is included which allows the system to save power when not driving the motor.
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7.2 Functional Block Diagrams
Figure 7-1. DRV8434E Block Diagram
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Figure 7-2. DRV8434P Block Diagram
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7.3 Feature Description
The following table shows the recommended values of the external components for the driver.
Figure 7-3. Resistor divider connected to the VREF pins
Table 7-1. External Components
COMPONENT
CVM1
PIN 1
VM
PIN 2
PGND
PGND
VM
RECOMMENDED
Two X7R, 0.01-µF, VM-rated ceramic capacitors
Bulk, VM-rated capacitor
CVM2
VM
CVCP
VCP
X7R, 0.22-µF, 16-V ceramic capacitor
X7R, 0.022-µF, VM-rated ceramic capacitor
X7R, 0.47-µF to 1-µF, 6.3-V or 10-V rated ceramic capacitor
>4.7-kΩ resistor
CSW
CPH
CPL
CDVDD
DVDD
VCC
GND
RnFAULT
RREF1
nFAULT
VCC
VREFx
VREFx
Resistor to limit chopping current. It is recommended that the value of parallel
combination of RREF1 and RREF2 should be less than 50-kΩ.
RREF2 (Optional)
GND
VCC is not a pin on the device, but a VCC supply voltage pullup is required for open-drain output nFAULT;
nFAULT may be pulled up to DVDD.
7.3.1 Bridge Control
The DRV8434E is controlled using a PH/EN interface. Table 7-2 gives the full H-bridge state. Note that this table
does not take into account the current control built into the DRV8434E. Positive current is defined in the direction
of xOUT1 to xOUT2.
Table 7-2. DRV8434E (PH/EN) Control Interface
nSLEEP
xEN
X
xPH
xOUT1
Hi-Z
Hi-Z
L
xOUT2
Hi-Z
Hi-Z
H
DESCRIPTION
0
1
1
1
X
Sleep mode; H-bridge disabled Hi-Z
H-bridge disabled Hi-Z
0
X
1
0
Reverse (current xOUT2 to xOUT1)
Forward (current xOUT1 to xOUT2)
1
1
H
L
The DRV8434P is controlled using a PWM interface. Table 7-3 gives the full H-bridge state. Note that this table
does not take into account the current control built into the DRV8434P. Positive current is defined in the direction
of xOUT1 to xOUT2.
Table 7-3. DRV8434P (PWM) Control Interface
nSLEEP
xIN1
xIN2
xOUT1
xOUT2
DESCRIPTION
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Hi-Z
L
Hi-Z
L
Sleep mode; H-bridge disabled Hi-Z
Brake; low-side slow decay
Reverse (current xOUT2 to xOUT1)
Forward (current xOUT1 to xOUT2)
Brake; high-side slow decay
L
H
H
L
H
H
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7.3.2 Current Regulation
The current through the motor windings is regulated by an adjustable, off-time PWM current-regulation circuit.
When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage,
inductance of the winding, and the magnitude of the back EMF present. When the current hits the current
regulation threshold, the bridge enters a decay mode for a period of time determined by the TOFF pin setting to
decrease the current. After the off-time expires, the bridge is re-enabled, starting another PWM cycle.
Table 7-4. Off-Time
Settings
TOFF
OFF-TIME tOFF
0
1
7 µs
16 µs
Hi-Z
24 µs
330kΩ to GND
32 µs
The TOFF pin configures the PWM OFF time for all decay modes except smart tune ripple control. The OFF time
settings can be changed on the fly. After a OFF time setting change, the new OFF time is applied after a 10 µs
de-glitch time.
The current regulation threshold is set by a comparator which monitors the voltage across the current sense
MOSFETs in parallel with the low-side power MOSFETs. To generate the reference voltage for the comparator,
the VREFx input is attenuated by a factor of Kv.
The chopping current (IFS) can be calculated as IFS (A) = VREFx (V) / KV (V/A) = VREFx (V) / 1.32 (V/A).
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7.3.3 Decay Modes
During PWM current chopping, the H-bridge is enabled to drive through the motor winding until the PWM current
chopping threshold is reached. This is shown in Figure 7-4, Item 1.
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or
slow decay. In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses
state to allow winding current to flow in a reverse direction. The opposite FETs are turned on; as the winding
current approaches zero, the bridge is disabled to prevent any reverse current flow. Fast decay mode is shown
in Figure 7-4, item 2. In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs
in the bridge. This is shown in Figure 7-4, Item 3.
Figure 7-4. Decay Modes
The decay mode is selected by setting the quad-level ADECAY and BDECAY pins as shown in Table 7-5.
Table 7-5. Decay Mode Settings
xDECAY
DECAY MODE
Smart tune Dynamic Decay
Smart tune Ripple Control
Mixed decay: 30% fast
Fast decay
0
1
Hi-Z
330k to GND
The ADECAY pin sets the decay mode for H-bridge A (AOUT1, AOUT2), and the BDECAY pin sets the decay
mode for H-bridge B (BOUT1, BOUT2).
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7.3.3.1 Mixed Decay
ITRIP
tOFF
tBLANK
tOFF
tBLANK
tDRIVE
tDRIVE
tDRIVE
ITRIP
tBLANK
tDRIVE
tFAST
tBLANK
tDRIVE
tFAST
tOFF
tOFF
Figure 7-5. Mixed Decay Mode
Mixed decay begins as fast decay for 30% of tOFF, followed by slow decay for the remainder of tOFF
.
This mode exhibits ripple larger than slow decay, but smaller than fast decay. On decreasing current steps,
mixed decay settles to the new ITRIP level faster than slow decay.
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7.3.3.2 Fast Decay
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tOFF
tBLANK
tDRIVE
tOFF
tDRIVE
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
Figure 7-6. Fast/Fast Decay Mode
During fast decay, the polarity of the H-bridge is reversed. The H-bridge will be turned off as current approaches
zero in order to prevent current flow in the reverse direction.
Fast decay exhibits the highest current ripple of the decay modes for a given tOFF. Transition time on decreasing
current steps is much faster than slow decay since the current is allowed to decrease much faster.
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7.3.3.3 Smart tune Dynamic Decay
The smart tune current regulation scheme is an advanced current-regulation control method compared to
traditional fixed off-time current regulation schemes. Smart tune current regulation scheme helps the stepper
motor driver adjust the decay scheme based on operating factors such as the ones listed as follows:
•
•
•
•
•
Motor winding resistance and inductance
Motor aging effects
Motor dynamic speed and load
Motor supply voltage variation
Low-current versus high-current dI/dt
ITRIP
tBLANK
tDRIVE
tBLANK
tBLANK
tDRIVE
tOFF
tOFF
tDRIVE
ITRIP
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tFAST
tFAST
Figure 7-7. Smart tune Dynamic Decay Mode
Smart tune Dynamic Decay greatly simplifies the decay mode selection by automatically configuring the decay
mode between slow, mixed, and fast decay. In mixed decay, smart tune dynamically adjusts the fast decay
percentage of the total mixed decay time. This feature eliminates motor tuning by automatically determining the
best decay setting that results in the lowest ripple for the motor.
The decay mode setting is optimized iteratively each PWM cycle. If the motor current overshoots the target trip
level, then the decay mode becomes more aggressive (add fast decay percentage) on the next cycle to prevent
regulation loss. If a long drive time must occur to reach the target trip level, the decay mode becomes less
aggressive (remove fast decay percentage) on the next cycle to operate with less ripple and more efficiently. On
falling steps, smart tune Dynamic Decay automatically switches to fast decay to reach the next step quickly.
Smart tune Dynamic Decay is optimal for applications that require minimal current ripple but want to maintain a
fixed frequency in the current regulation scheme.
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7.3.3.4 Smart tune Ripple Control
ITRIP
IVALLEY
tBLANK
tDRIVE
tBLANK
tBLANK
tDRIVE
tBLANK
tDRIVE
tOFF
tOFF
tOFF
tDRIVE
ITRIP
IVALLEY
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
tBLANK
tDRIVE
tOFF
Figure 7-8. Smart tune Ripple Control Decay Mode
Smart tune Ripple Control operates by setting an IVALLEY level alongside the ITRIP level. When the current level
reaches ITRIP, instead of entering slow decay until the tOFF time expires, the driver enters slow decay until IVALLEY
is reached. Slow decay operates similar to mode 1 in which both low-side MOSFETs are turned on allowing the
current to recirculate. In this mode, tOFF varies depending on the current level and operating conditions.
This method allows much tighter regulation of the current level increasing motor efficiency and system
performance. Smart tune Ripple Control can be used in systems that can tolerate a variable off-time regulation
scheme to achieve small current ripple in the current regulation.
7.3.3.5 Blanking time
After the current is enabled (start of drive phase) in an H-bridge, the current sense comparator is ignored for a
period of time (tBLANK) before enabling the current-sense circuitry. The blanking time also sets the minimum drive
time of the PWM. The blanking time is approximately 1 µs.
7.3.4 Charge Pump
A charge pump is integrated to supply a high-side N-channel MOSFET gate-drive voltage. The charge pump
requires a capacitor between the VM and VCP pins to act as the storage capacitor. Additionally a ceramic
capacitor is required between the CPH and CPL pins to act as the flying capacitor.
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Figure 7-9. Charge Pump Block Diagram
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7.3.5 Linear Voltage Regulators
A linear voltage regulator is integrated in the device. The DVDD regulator can be used to provide a reference
voltage. DVDD can supply a maximum of 2 mA load. For proper operation, bypass the DVDD pin to GND using
a ceramic capacitor.
The DVDD output is nominally 5-V. When the DVDD LDO current load exceeds 2 mA, the output voltage drops
significantly.
Figure 7-10. Linear Voltage Regulator Block Diagram
If a digital input must be tied permanently high (that is, ADECAY, BDECAY or TOFF), tying the input to the DVDD
pin instead of an external regulator is preferred. This method saves power when the VM pin is not applied or in
sleep mode: the DVDD regulator is disabled and current does not flow through the input pulldown resistors. For
reference, logic level inputs have a typical pulldown of 200 kΩ.
The nSLEEP pin cannot be tied to DVDD, else the device will never exit sleep mode.
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7.3.6 Logic and Quad-Level Pin Diagrams
Figure 7-11 gives the input structure for logic-level pins APH, AEN, BPH, BEN, AIN1, AIN2, BIN1, BIN2 and
nSLEEP:
Figure 7-11. Logic-level Input Pin Diagram
Quad-level logic pins TOFF, ADECAY, and BDECAY have the following structure as shown in Figure 7-12.
Figure 7-12. Quad-Level Input Pin Diagram
7.3.6.1 nFAULT Pin
The nFAULT pin has an open-drain output and should be pulled up to a 5-V, 3.3-V or 1.8-V supply. When a fault
is detected, the nFAULT pin will be logic low. nFAULT pin will be high after power-up. For a 5-V pullup, the
nFAULT pin can be tied to the DVDD pin with a resistor. For a 3.3-V or 1.8-V pullup, an external supply must be
used.
Output
nFAULT
Figure 7-13. nFAULT Pin
7.3.7 Protection Circuits
The devices are fully protected against supply undervoltage, charge pump undervoltage, output overcurrent, and
device overtemperature events.
7.3.7.1 VM Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the UVLO-threshold voltage for the voltage supply, all the
outputs are disabled, and the nFAULT pin is driven low. The charge pump is disabled in this condition. Normal
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operation resumes (motor-driver operation and nFAULT released) when the VM undervoltage condition is
removed.
7.3.7.2 VCP Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin falls below the CPUV voltage, all the outputs are disabled, and the
nFAULT pin is driven low. The charge pump remains active during this condition. Normal operation resumes
(motor-driver operation and nFAULT released) when the VCP undervoltage condition is removed.
7.3.7.3 Overcurrent Protection (OCP)
An analog current-limit circuit on each FET limits the current through the FET by removing the gate drive. If this
current limit persists for longer than the tOCP time, the FETs in that particular H-bridge are disabled and the
nFAULT pin is driven low. The charge pump remains active during this condition. Once the OCP condition is
removed, normal operation resumes after applying an nSLEEP reset pulse or a power cycling.
7.3.7.4 Thermal Shutdown (OTSD)
If the die temperature exceeds the thermal shutdown limit (TOTSD) all MOSFETs in the H-bridge are disabled,
and the nFAULT pin is driven low. After the junction temperature falls below the overtemperature threshold limit
minus the hysteresis (TOTSD – THYS_OTSD), normal operation resumes after applying an nSLEEP reset pulse or a
power cycling.
Fault Condition Summary
Table 7-6. Fault Condition Summary
ERROR
REPORT
CHARGE
PUMP
FAULT
CONDITION
H-BRIDGE
LOGIC
RECOVERY
Reset
VM undervoltage
(UVLO)
VM < VUVLO
nFAULT
Disabled
Disabled
(VDVDD < 3.9 Automatic: VM > VUVLO
V)
CP undervoltage
(CPUV)
VCP < VCPUV
IOUT > IOCP
TJ > TTSD
nFAULT
nFAULT
nFAULT
Disabled
Disabled
Disabled
Operating
Operating
Disabled
Operating
Operating
Operating
VCP > VCPUV
Latched
Overcurrent (OCP)
Thermal Shutdown
(OTSD)
Latched
7.4 Device Functional Modes
7.4.1 Sleep Mode (nSLEEP = 0)
The state of the device is managed by the nSLEEP pin. When the nSLEEP pin is low, the device enters a low-
power sleep mode. In sleep mode, all the internal MOSFETs are disabled and the charge pump is disabled. The
tSLEEP time must elapse after a falling edge on the nSLEEP pin before the device enters sleep mode. The device
is brought out of sleep automatically if the nSLEEP pin is brought high. The tWAKE time must elapse before the
device is ready for inputs.
7.4.2 Operating Mode (nSLEEP = 1)
When the nSLEEP pin is high, and VM > UVLO, the device enters the active mode. The tWAKE time must elapse
before the device is ready for inputs.
7.4.3 nSLEEP Reset Pulse
A latched fault can be cleared through a quick nSLEEP pulse. This pulse width must be greater than 20 µs and
shorter than 40 µs. If nSLEEP is low for longer than 40 µs, but less than 120 µs, the faults are cleared and the
device may or may not shutdown, as shown in the timing diagram (see Figure 7-14). This reset pulse does not
affect the status of the charge pump or other functional blocks.
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Figure 7-14. nSLEEP Reset Pulse
Functional Modes Summary
Table 7-7 lists a summary of the functional modes.
Table 7-7. Functional Modes Summary
CONFIGURATI
ON
CONDITION
H-BRIDGE
DVDD Regulator CHARGE PUMP
Logic
Sleep mode
Operating
4.5 V < VM < 48 V
4.5 V < VM < 48 V
nSLEEP pin = 0
nSLEEP pin = 1
Disabled
Disbaled
Disabled
Disabled
Operating
Operating
Operating
Operating
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The DRV8434E/P are used in brushed or stepper motor control.
8.2 Typical Application
In this application, the device is configured to drive bidirectional currents through two external loads (such as two
brushed DC motors) using H-bridge configuration. The H-bridge polarity and duty cycle are controlled from the
external controller to the xEN/xIN1 and xPH/xIN2 pins.
Figure 8-1. Typical Application Schematic
8.2.1 Design Requirements
Table 8-1 lists the design input parameters for system design.
Table 8-1. Design Parameters
DESIGN PARAMETER
Supply Voltage
REFERENCE
EXAMPLE VALUE
24 V
VM
RL
Motor winding resistance
Motor winding inductance
Switching Frequency
1.2 Ω
LL
2.3 mH
fPWM
IREG
30 kHz
Regulated Current for Each Motor
1.5 A
8.2.2 Detailed Design Procedure
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8.2.2.1 Current Regulation
The regulated current (IREG) is set by the VREFx analog voltage. When starting a brushed-DC motor, a large
inrush current may occur because there is no back-EMF. Current regulation will act to limit this inrush current
and prevent high current on startup. The regulated current (IREG) can be calculated as IREG (A) = VREFx (V) / KV
(V/A) = VREFx (V) / 1.32 (V/A).
8.2.2.2 Power Dissipation and Thermal Calculation
The output current and power dissipation capabilities of the device are heavily dependent on the PCB design
and external system conditions. This section provides some guidelines for calculating these values.
Total power dissipation (P TOT) for the device is composed of three main components. These are the power
MOSFET RDS(ON) (conduction) losses, the power MOSFET switching losses and the quiescent supply current
dissipation. While other factors may contribute additional power losses, these other items are typically
insignificant compared to the three main items.
PTOT = PCOND + PSW + PQ
P COND for each brushed-DC motor can be calculated from the device R DS(ON) and regulated output current
(IREG). Assuming same IREG for both brushed-DC motors,
PCOND = 2 x (IREG)2 x (RDS(ONH) + RDS(ONL)
)
It should be noted that R DS(ON) has a strong correlation with the device temperature. A curve showing the
normalized RDS(ON) with temperature can be found in the Typical Characteristics curves.
PCOND = 2 x (1.5-A)2 x (0.165-Ω + 0.165-Ω) = 1.485-W
P SW can be calculated from the nominal supply voltage (VM), regulated output current (I REG), switching
frequency (fPWM) and the device output rise (tRISE) and fall (tFALL) time specifications.
PSW = 2 x (PSW_RISE + PSW_FALL
)
PSW_RISE = 0.5 x VM x IREG x tRISE x fPWM
PSW_FALL = 0.5 x VM x IREG x tFALL x fPWM
PSW_RISE = 0.5 x 24 V x 1.5 A x 100 ns x 30 kHz = 0.054 W
PSW_FALL = 0.5 x 24 V x 1.5 A x 100 ns x 30 kHz = 0.054 W
PSW = 2 x (0.054W + 0.054W) = 0.216 W
PQ can be calculated from the nominal supply voltage (VM) and the IVM current specification.
PQ = VM x IVM = 24 V x 5 mA = 0.12 W
The total power dissipation (PTOT) is calculated as the sum of conduction loss, switching loss and the quiescent
power loss.
PTOT = PCOND + PSW + PQ = 1.485-W + 0.216-W + 0.12-W = 1.821-W
For an ambient temperature of TA and total power dissipation (PTOT), the junction temperature (TJ) is calculated
as
TJ = TA + (PTOT x RθJA
)
Considering a JEDEC standard 4-layer PCB, the junction-to-ambient thermal resistance (RθJA) is 29.7 °C/W for
the HTSSOP package and 39 °C/W for the VQFN package.
Assuming 25°C ambient temperature, the junction temperature for the HTSSOP package is calculated as -
TJ = 25°C + (1.821-W x 29.7 °C/W) = 79.08 °C
The junction temperature for the VQFN package is calculated as -
TJ = 25°C + (1.821-W x 39 °C/W) = 96.02 °C
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It should be ensured that the device junction temperature is within the specified operating region.
8.2.3 Application Curves
CH3 = VM (10V/div), CH1 = nFAULT (3V/div), CH5 = nSLEEP (3V/div), CH7 = IREG (1.5A/div)
Figure 8-2. Device Power-up with nSLEEP
CH3 = VM (10V/div), CH1 = nFAULT (3V/div), CH5 = nSLEEP (3V/div), CH7 = IREG (1.5A/div)
Figure 8-3. Device Power-up with Supply Voltage (VM) Ramp
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CH1 = IN1 (3V/div), CH7 = IREG (0.75A/div), CH3 = AOUT1 (24V/div), CH2 = AOUT2 (24V/div)
Figure 8-4. Driver Full On Operation with Current Regulation
8.3 Alternate Application
The following design procedure can be used to configure the DRV8434E/P to drive a stepper motor.
Figure 8-5. Alternate Application Schematic
8.3.1 Design Requirements
Table 8-2 gives design input parameters for system design.
Table 8-2. Design Parameters
EXAMPLE
DESIGN PARAMETER
REFERENCE
VALUE
Supply voltage
VM
24 V
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Table 8-2. Design Parameters (continued)
EXAMPLE
VALUE
DESIGN PARAMETER
REFERENCE
Motor winding resistance
Motor winding inductance
Motor Full Step Angle
Target microstepping level
Target motor speed
RL
LL
0.93 Ω/phase
1.9 mH/phase
1.8°/step
1/2 step
θstep
nm
v
90 rpm
Target full-scale current
IFS
2 A
8.3.2 Detailed Design Procedure
8.3.2.1 Current Regulation
In a stepper motor, the full-scale current (IFS) is the maximum current driven through either winding. This quantity
depends on the VREFx voltage. The maximum allowable voltage on the VREFx pins is 3.3 V. DVDD can be
used to provide VREFx through a resistor divider.
IFS (A) = VREF (V) / 1.32 (V/A)
Note
The IFS current must also follow Equation 1 to avoid saturating the motor. VM is the motor supply
voltage, and RL is the motor winding resistance.
VM (V)
IFS (A) <
RL (W) + 2 ì RDS(ON) (W)
(1)
8.3.2.2 Stepper Motor Speed
Next, the driving waveform needs to be planned. In order to command the correct speed, determine the
frequency of the input waveform.
If the target motor speed is too high, the motor will not spin. Make sure that the motor can support the target
speed.
For a desired motor speed (v), microstepping level (nm), and motor full step angle (θstep),
v (rpm) ì 360 (è / rot)
ƒstep (steps / s) =
qstep (è / step) ìnm (steps / microstep) ì 60 (s / min)
(2)
θstep can be found in the stepper motor data sheet or written on the motor itself.
The frequency ƒstep gives the frequency of input change on the device. For the design parameters mentioned in
Equation 2, ƒstep can be calculated as 600 Hz.
8.3.2.3 Decay Modes
The device supports several different decay modes: fast decay, mixed decay, and smart tune. The current
through the motor windings is regulated using an adjustable fixed-time-off scheme. This means that after any
drive phase, when a motor winding current has hit the current chopping threshold (ITRIP), the device will place
the winding in one of the decay modes for TOFF. After TOFF, a new drive phase starts.
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply (VM) range between 4.5 V and 48 V. THe device
has an absolute maximum rating of 50 V. A 0.1 µF ceramic capacitor rated for VM must be placed at each VM
pin as close to the device as possible. In addition, a bulk capacitor must be included on VM.
9.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
•
•
•
•
•
•
The highest current required by the motor system
The power supply’s capacitance and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable voltage ripple
The type of motor used (brushed DC, brushless DC, stepper)
The motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 9-1. Setup of Motor Drive System With External Power Supply
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10 Layout
10.1 Layout Guidelines
The VM pin should be bypassed to PGND using a low-ESR ceramic bypass capacitor with a recommended
value of 0.01 µF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick
trace or ground plane connection to the device PGND pin.
The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component can be an
electrolytic capacitor.
A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. A value of 0.022 µF rated for
VM is recommended. Place this component as close to the pins as possible.
A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. A value of 0.22 µF rated for 16
V is recommended. Place this component as close to the pins as possible.
Bypass the DVDD pin to ground with a low-ESR ceramic capacitor. A value of 0.47 µF rated for 6.3 V is
recommended. Place this bypassing capacitor as close to the pin as possible.
The thermal PAD must be connected to system ground.
10.2 Layout Example
Figure 10-1. HTSSOP Layout Recommendation
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Figure 10-2. QFN Layout Recommendation
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
RGE0024B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
0.5
0.3
PIN 1 INDEX AREA
4.1
3.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
(0.2) TYP
2.45 0.1
7
12
EXPOSED
THERMAL PAD
SEE TERMINAL
DETAIL
13
6
2X
SYMM
25
2.5
18
1
0.3
24X
20X 0.5
0.2
19
24
0.1
C A B
SYMM
24X
PIN 1 ID
(OPTIONAL)
0.05
0.5
0.3
4219013/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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SLOSE49 – NOVEMBER 2020
www.ti.com
EXAMPLE BOARD LAYOUT
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.45)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(R0.05)
TYP
25
SYMM
(3.8)
20X (0.5)
13
6
(
0.2) TYP
VIA
7
12
(0.975) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219013/A 05/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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Product Folder Links: DRV8434E
DRV8434E
SLOSE49 – NOVEMBER 2020
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EXAMPLE STENCIL DESIGN
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.08)
(0.64) TYP
19
24
24X (0.6)
1
25
18
24X (0.25)
(R0.05) TYP
SYMM
(0.64)
TYP
(3.8)
20X (0.5)
13
6
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219013/A 05/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
Copyright © 2020 Texas Instruments Incorporated
38
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Product Folder Links: DRV8434E
DRV8434E
SLOSE49 – NOVEMBER 2020
www.ti.com
PACKAGE OUTLINE
PowerPADTM TSSOP - 1.2 mm max height
PWP0028M
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
26X 0.65
28
1
2X
9.8
9.6
8.45
NOTE 3
14
15
0.30
0.19
28X
4.5
4.3
B
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X 0.82 MAX
NOTE 5
14
15
2X 0.825 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
4.05
3.53
THERMAL
PAD
0.15
0.05
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
1
28
3.10
2.58
4224480/A 08/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
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Product Folder Links: DRV8434E
DRV8434E
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EXAMPLE BOARD LAYOUT
PowerPADTM TSSOP - 1.2 mm max height
PWP0028M
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(3.1)
METAL COVERED
BY SOLDER MASK
SYMM
28X (1.5)
1
28X (0.45)
28
SEE DETAILS
(R0.05) TYP
26X (0.65)
SYMM
(4.05)
(0.6)
(9.7)
NOTE 9
SOLDER MASK
DEFINED PAD
(1.2) TYP
(
0.2) TYP
VIA
14
15
(1.2) TYP
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4224480/A 08/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
Copyright © 2020 Texas Instruments Incorporated
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Product Folder Links: DRV8434E
DRV8434E
SLOSE49 – NOVEMBER 2020
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EXAMPLE STENCIL DESIGN
PowerPADTM TSSOP - 1.2 mm max height
PWP0028M
SMALL OUTLINE PACKAGE
(3.1)
BASED ON
0.125 THICK
STENCIL
28X (1.5)
METAL COVERED
BY SOLDER MASK
1
28X (0.45)
28
(R0.05) TYP
26X (0.65)
SYMM
(4.05)
BASED ON
0.125 THICK
STENCIL
15
14
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.47 X 4.53
3.10 X 4.05 (SHOWN)
2.83 X 3.70
0.125
0.15
0.175
2.62 X 3.42
4224480/A 08/2018
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
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Product Folder Links: DRV8434E
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8434ERGER
DRV8434PRGER
PDRV8434EPWPR
ACTIVE
VQFN
VQFN
RGE
24
24
28
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
DRV
8434E
ACTIVE
RGE
NIPDAU
Call TI
DRV
8434P
PREVIEW
HTSSOP
PWP
1
RoHS (In work)
& Non-Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
0.5
0.3
PIN 1 INDEX AREA
4.1
3.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
(0.2) TYP
2.45 0.1
7
12
EXPOSED
SEE TERMINAL
DETAIL
THERMAL PAD
13
6
2X
SYMM
25
2.5
18
1
0.3
24X
20X 0.5
0.2
19
24
0.1
C A B
SYMM
24X
PIN 1 ID
(OPTIONAL)
0.05
0.5
0.3
4219013/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.45)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(R0.05)
TYP
25
SYMM
(3.8)
20X (0.5)
13
6
(
0.2) TYP
VIA
7
12
(0.975) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219013/A 05/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.08)
(0.64) TYP
19
24
24X (0.6)
1
25
18
24X (0.25)
(R0.05) TYP
SYMM
(0.64)
TYP
(3.8)
20X (0.5)
13
6
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219013/A 05/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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