DRV8801AQRMJRQ1 [TI]
具有电流反馈功能和可湿性侧面 QFN 封装的汽车类 40V、2.8A H 桥电机驱动器 | RMJ | 16 | -40 to 125;
| 型号： | DRV8801AQRMJRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电流反馈功能和可湿性侧面 QFN 封装的汽车类 40V、2.8A H 桥电机驱动器 | RMJ | 16 | -40 to 125 电动机控制 电机 驱动 驱动器 |
| 文件： | 总28页 (文件大小：1523K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV8801A-Q1
SLVSC79D – JUNE 2014 – REVISED NOVEMBER 2020
DRV8801A-Q1 DMOS Full-Bridge Motor Drivers
1 Features
3 Description
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
Low ON-Resistance (0.83 Ω) Outputs
Low-Power Sleep Mode
100% PWM Duty Cycle Supported
6.5 to 36-V Operating Supply Voltage Range
Thermally Enhanced Surface-Mount Package
Configurable Overcurrent Limit
The DRV8801A-Q1 device provides a versatile motor-
driver solution with a full H-bridge driver. The device
can drive a brushed DC motor or one winding of a
stepper motor, as well as other devices like solenoids.
A simple PHASE and ENABLE interface allows easy
interfacing to controller circuits.
The output stages use N-channel power MOSFETs
configured as an H-bridge. The DRV8801A-Q1 device
is capable of peak output currents up to ±2.8 A and
operating voltages up to 36 V. An internal charge
pump generates required gate drive voltages.
Protection Features
– VBB Undervoltage Lockout (UVLO)
– Overcurrent Protection (OCP)
– Short-to-Supply Protection
– Short-to-Ground Protection
A low-power sleep mode is provided which shuts
down internal circuitry to achieve very low quiescent
current draw. This sleep mode can be set using a
dedicated nSLEEP pin.
– Overtemperature Warning (OTW)
– Overtemperature shutdown (OTS)
– Overcurrent and Overtemperature Fault
Conditions Indicated On Pin (nFAULT)
Internal
protection
functions
are
provided
2 Applications
undervoltage lockout, overcurrent protection, short-
to-supply protection, short-to-ground protection,
overtemperature warning, and overtemperature
shutdown. Overcurrent (including short-to-ground and
short-to-supply) and overtemperature fault conditions
are indicated via an nFAULT pin.
•
•
•
•
Automotive Body Systems
Door Locks
HVAC Actuators
Piezo Alarm
The DRV8801A-Q1 device is packaged in a 16-pin
WQFN package with wettable flanks and exposed
thermal pad (Eco-friendly: RoHS & no Sb/Br).
Device Information
PART NUMBER(1)
PACKAGE
BODY SIZE (NOM)
DRV8801A-Q1
WQFN (16)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
6.5 to 36 V
DRV8801A-Q1
PH/EN
VPROPI
nFAULT
M
Full-Bridge
Driver
Simplified Application Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8801A-Q1
SLVSC79D – JUNE 2014 – REVISED NOVEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Dissipation Ratings..................................................... 6
6.7 Typical Characteristics................................................6
7 Detailed Description........................................................8
7.1 Overview.....................................................................8
7.2 Functional Block Diagram...........................................8
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................12
8 Application and Implementation..................................13
8.1 Application Information............................................. 13
8.2 Typical Application.................................................... 13
8.3 Parallel Configuration................................................15
9 Power Supply Recommendations................................19
9.1 Bulk Capacitance......................................................19
10 Layout...........................................................................20
10.1 Layout Guidelines................................................... 20
10.2 Layout Example...................................................... 20
10.3 Power Dissipation................................................... 20
11 Device and Documentation Support..........................21
11.1 Documentation Support.......................................... 21
11.2 Receiving Notification of Documentation Updates..21
11.3 Support Resources................................................. 21
11.4 Community Resources............................................21
11.5 Trademarks............................................................. 21
11.6 Electrostatic Discharge Caution..............................21
11.7 Glossary..................................................................21
12 Mechanical, Packaging, And Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2016) to Revision D (June 2020)
Page
•
•
•
•
•
•
Improved description for pins CP1, CP2,nFAULT, nSLEEP, VBB and VCP in Pin Functions table....................3
Added entries for VCP and CP2 pins in Absolute Maximum Ratings table........................................................4
Removed incorrect duplicate input logic current entry for ENABLE pin in Electrical Characteristics table.........5
Added additional information on SENSE pin behavior..................................................................................... 10
Added equation for VPROPI to help when connecting pin’s output to ADC in Feature Description ................ 11
Added die temperature estimation equation utilizing junction to ambient thermal impedance in Application and
Implementation section.....................................................................................................................................14
Added information on using motor driver’s pulse width modulating modes in Application and Implementation
section.............................................................................................................................................................. 14
Added information on connecting multiple DRV8801-Q1 together to support higher current in Application and
Implementation section.....................................................................................................................................15
•
•
Changes from Revision B (June 2016) to Revision C (July 2016)
Page
•
Changed the TJ value for some test conditions for the output ON resistance parameter in the Electrical
Characteristics ...................................................................................................................................................5
Added the Documentation Support, Receiving Notification of Documentation Updates, and Community
Resources sections ......................................................................................................................................... 21
•
Changes from Revision A (September 2014) to Revision B (June 2016)
Page
•
Changed the value of TJ from 125°C to 25°C in the test condition (source driver, IO = –2.8 A, VBB = 8 to 36 V)
for the output ON resistance parameter............................................................................................................. 5
Added the UVLO hysteresis parameter in the Electrical Characteristics table...................................................5
Added MIN and MAX values for the overcurrent retry time parameter in the Electrical Characteristics table ....
5
•
•
•
•
Updated the Functional Block Diagram ............................................................................................................. 8
Added tpd to the Overcurrent Control Timing image......................................................................................... 10
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Changes from Revision * (June 2014) to Revision A (September 2014)
Page
•
•
Added TYPE column to the Pin Functions table ................................................................................................3
Updated the Overcurrent Control Timing image...............................................................................................10
5 Pin Configuration and Functions
PHASE
GND
1
2
3
4
12
11
10
9
GND
CP2
Thermal
Pad
nSLEEP
ENABLE
CP1
OUTB
Not to scale
Figure 5-1. RMJ Package 16-Pin WQFN With Thermal Pad Top View
Table 5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
CP1
NO.
10
11
4
—
—
I
Charge pump switching node. Connect a X7R, 0.1-μF, VBB-rated ceramic capacitor from CP1 to CP2.
Enables OUTA and OUTB drivers
CP2
ENABLE
2
GND
PWR Ground
12
16
5
MODE 1
MODE 2
I
I
Mode logic input
Mode 2 logic input
Fault indication. Pulled logic low with fault condition; open-drain output requires an external pullup
resistor.
nFAULT
nSLEEP
15
3
OD
I
Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal
pulldown resistor.
OUTA
6
9
1
7
O
O
I
DMOS full-bridge output positive. H-Bridge output A
DMOS full-bridge output negative. H-Bridge output B
Phase logic input for direction control
OUTB
PHASE
SENSE
IO
Sense power return
Driver supply voltage. Bypass to GND with 0.1-μF ceramic capacitors plus a bulk capacitor rated for
VBB
8
PWR
VBB
.
VCP
13
14
—
O
Charge pump reservoir capacitor pin. Connect a X7R, 0.1-μF, 16-V ceramic capacitor to VBB
Winding current proportional voltage output
.
VPROPI
Thermal pad
—
Exposed pad for thermal dissipation; connect to GND pins.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.5
MAX
40
UNIT
V
Power supply voltage(2)
Charge pump voltage
Digital pin voltage
VBB
VCP and CP2
VBB +17
7
V
PHASE, ENABLE, MODE1, MODE2, nSLEEP, nFAULT
V
VBB to OUTx voltage
OUTx to GND voltage
Sense pin voltage
OUTA and OUTB
OUTA and OUTB
SENSE
36
V
36
V
0.5
V
H-bridge output current
VPROPI pin voltage
OUTA, OUTB, and SENSE
VPROPI
2.8
A
–0.3
–40
3.6
V
Maximum junction temperature, TJ
Storage temperature, Tstg
150
125
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
All pins
V(ESD)
V
Corner pins (1, 4, 5, 8, 9, 12,
13, and 16)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
6.5
0
MAX
UNIT
V
VBB
VCC
ƒ(PWM)
IO
Power supply voltage
36
5.5
Logic supply voltage
V
Applied PWM signal (PHASE and ENABLE)
H-bridge peak output current
Ambient temperature
0
100
2.8
kHz
A
0
TA
–40
125
°C
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6.4 Thermal Information
DRV8801A-Q1
THERMAL METRIC(1)
RMJ (WQFN)
16 PINS
36.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
43.4
14.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.7
ψJB
14.7
RθJCbot
4.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TA = 25°C, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
POWER SUPPLIES (VBB
)
VBB
VBB operating supply voltage
6.5
36
V
ƒPWM < 50 kHz
6
IBB
VBB operating supply current
mA
μA
Charge pump on, Outputs disabled
nSLEEP = 0, TJ = 25°C
3.2
IBB(Q)
VBB sleep-mode supply current
10
CONTROL INPUTS (PHASE, ENABLE, MODE1, MODE2, nSLEEP)
VIL
VIH
IIL
Input logic low voltage
Input logic high voltage
Input logic low current
Input logic high current
Input logic low current
Input logic high current
Input logic low voltage
Input logic high voltage
Input logic low current
Input logic high current
0.8
PHASE, ENABLE
MODE1, MODE2
V
2
VI = 0.8 V
VI = 2 V
–20 ≤ –2
20
20
PHASE,
MODE1, MODE2
µA
μA
V
IIH
IIL
< 1
16
40
VI = 0.8 V
VI = 2 V
40
ENABLE
nSLEEP
IIH
VIL
VIH
IIL
100
0.8
2.7
< 1
27
VI = 0.8 V
VI = 2 V
10
50
μA
IIH
CONTROL OUTPUTS (nFAULT)
VOL Output logic low voltage
IO = 1 mA
0.4
V
DMOS DRIVERS (OUTA, OUTB, SENSE, VPROPI)
Source driver, IO = –2.8 A, TJ = 25°C , VBB = 6.5 to 36 V
Source driver, IO = –2.8 A, TJ = 125°C, VBB = 8 to 36 V
Source driver, IO = –2.8 A, TJ = 125°C, VBB = 6.5 to 8 V
Sink driver, IO = 2.8 A, TJ = 25°C, VBB = 6.5 to 36 V
Sink driver, IO = 2.8 A, TJ = 125°C, VBB = 8 to 36 V
Sink driver, IO = 2.8 A, TJ = 125°C, VBB = 6.5 to 8 V
R(SENSE) between SENSE and GND
0.48
0.74 0.85
0.74
0.35
0.52
0.9
rDS(on)
Output ON resistance
Ω
0.7
0.52 0.75
V(TRIP)
Vf
SENSE trip voltage
450
500
550
1.4
1.4
mV
V
Source diode, If = –2.8 A
Body diode forward voltage
Sink diode, If = 2.8 A
Input edge to source or sink ON
600
100
500
tpd
Propagation delay time
Crossover delay
ns
ns
Input edge to source or sink OFF
tCOD
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TA = 25°C, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VBB = 8 to 36 V; SENSE = 0.1 to 0.4 V
VBB = 6.5 to 8 V; SENSE = 0.1 to 0.3 V
MIN TYP MAX UNIT
4.8
4.8
5
5.2
5.2
V/V
V/V
GD(a)
Differential amplifier gain
PROTECTION CIRCUITS
VBB increasing
VBB decreasing
5.5
6.4
5.7
VUV
UVLO threshold
V
UVLO hysteresis
500
3
850
mV
A
I(OCP)
VBB = 8 to 36 V
VBB = 6.5 to 8 V
Overcurrent protection trip level
2.8
A
t(DEG)
Overcurrent deglitch time
Overcurrent retry time
3
1.2
160
15
µs
ms
°C
°C
°C
°C
t(OCP)
0.5
3
T(OTW)
Thys(OTW)
T(OTS)
Thermal warning temperature
Thermal warning hysteresis
Thermal shutdown temperature
Thermal shutdown hysteresis
Die temperature TJ
Die temperature TJ
Die temperature TJ
Die temperature TJ
175
15
Thys(OTS)
6.6 Dissipation Ratings
TA = 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
PACKAGE
RθJA
RMJ
36.8
3 W
27 mW/C
6.7 Typical Characteristics
1400
1300
1200
1100
1000
900
5.35
TA
TA = 25
TA = 85
=
-
40
è
C
TA = -40èC
TA = 25èC
TA = 85èC
è
è
C
C
5.3
5.25
5.2
5.15
5.1
800
700
600
5.05
5
500
400
6
9
12
15
18
21
24
Power Supply Voltage (V)
27
30
33
36
0
0.2
0.4
0.6
0.8
1
Output Current (A)
1.2
1.4
1.6
D001
D002
Figure 6-1. rDS(on) Over Voltage
Figure 6-2. VPROPI Over Output Current
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60
55
50
45
40
35
30
25
20
15
10
6
9
12
15
18
21
24
27
Power Supply Voltage (V)
30
33
36
D003
Figure 6-3. VCP Voltage vs VBB
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7 Detailed Description
7.1 Overview
The DRV8801A-Q1 device is an integrated motor driver solutions for brushed-DC motors. The device integrates
a DMOS H-bridge and current sense and protection circuitry. The device can be powered with a supply voltage
between 6.5 V and 36 V, and is capable of providing an output current up to 2.8-A peak.
A simple PHASE and ENABLE interface allows control of the motor speed and direction.
A shunt amplifier output is provided for accurate current measurements by the system controller. The VPROPI
pin outputs a voltage that is five-times the voltage seen at the SENSE pin.
A low-power sleep mode is included which allows the system to save power when not driving the motor.
7.2 Functional Block Diagram
VCP
VBB
V
BB
+
0.1 µF
0.1 µF
100 µF
VCP
CP2
CP1
Pre-
drive
OUTA
Charge Pump
0.1 µF
VCP
BDC
V
BB
PHASE
ENABLE
MODE1
MODE2
nSLEEP
nFAULT
Pre-
Drive
OUTB
Logic
SENSE
VPROPI
R
(SENSE)
x5
V
CC
R
(VPROPI)
100 kΩ
Undervoltage
V
CC
1000 pF
Temperature
Sensor
GND
PPAD
GND
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7.3 Feature Description
7.3.1 Power Supervisor
The control input, nSLEEP, is used to minimize power consumption when the DRV8801A-Q1 device is not in
use. A logic low on the nSLEEP input disables much of the internal circuitry, including the internal voltage rails
and charge pump. A logic high on this input pin results in normal operation. When switching from low to high,
the user should allow a 1-ms delay before applying PWM signals. This time is needed for the charge pump to
stabilize.
7.3.2 Bridge Control
The following table shows the logic for the DRV8801A-Q1:
nSLEEP PHASE
ENABLE
MODE1
MODE2
OUTA
OUTB
OPERATION
Sleep mode
Reverse
0
1
1
1
1
X
0
1
0
1
X
1
1
0
0
X
X
X
0
X
X
X
X
X
Z
L
Z
H
L
H
H
L
Forward
L
Fast decay
Fast decay
0
H
Low-side Slow
decay
1
1
X
X
0
0
1
1
0
1
L
L
High-side Slow
decay
H
H
To prevent reversal of current during fast-decay synchronous rectification, outputs go to the high impedance
state as the current approaches 0 A.
The path of current flow for each of the states in the above logic table is shown in Figure 7-1.
7.3.2.1 MODE 1
Input MODE 1 is used to toggle between fast-decay mode and slow-decay mode. A logic high puts the device in
slow-decay mode.
7.3.2.2 MODE 2
MODE 2 is used to select which set of drivers (high side versus low side) is used during the slow-decay
recirculation. MODE 2 is meaningful only when MODE 1 is asserted high. A logic high on MODE 2 has current
recirculation through the high-side drivers. A logic low has current recirculation through the low-side drivers.
7.3.3 Fast Decay with Synchronous Rectification
This decay mode is equivalent to a phase change where the FETs opposite of the driving FETs are switched on
(2 in Figure 7-1). When in fast decay, the motor current is not allowed to go negative because this would cause
a change in direction. Instead, as the current approaches zero, the drivers turn off. See the Section 10.3 section
for an equation to calculate power.
7.3.4 Slow Decay with Synchronous Rectification (Brake Mode)
In slow-decay mode, both low-side and high-side drivers turn on, allowing the current to circulate through the
low-side and high-side body diodes of the H-bridge and the load (3 and 4 in Figure 7-1). See the Section 10.3
section for equations to calculate power for both high-side and low-side slow decay.
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VM
4
1
1
2
3
4
Drive
Fast decay with synchronous rectification
xOUTA
xOUTB
3
Low-side slow decay with synchronous rectification
High-side slow decay with synchronous rectification
2
xISEN
R(SENSE)
Figure 7-1. H-Bridge Operation Modes
7.3.5 Charge Pump
The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates. A 0.1-μF
ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1-μF
ceramic monolithic capacitor should be connected between VCP and VBB to act as a reservoir to run the
high-side DMOS devices.
7.3.6 SENSE
A low-value SENSE resistor is used to set an overcurrent threshold lower than the default maximum value of
2.8 A and to provide a voltage for VPROPI. This SENSE resistor must be connected between the SENSE pin
and ground. To minimize ground-trace IR drops in sensing the output current level, the current-sensing resistor
should have an independent ground return to the star ground point. This trace should be as short as possible.
For low-value sense resistors, the IR drops in the PCB can be significant, and should be taken into account.
A direct connection to ground yields a SENSE voltage equal to zero. In that case, maximum current is 2.8 A
and VPROPI outputs 0 V. A resistor connected as explained before, will yield a VPROPI output as detailed in
section Section 7.3.7. Size the sense resistor such that voltage drop across the sense resistor is less than 500
mV under normal loading conditions. Any voltage equal or larger to 500 mV will signal the device to hi-Z the
H-bridge output as overcurrent trip threshold has been reached. In this case, device will enter recirculation as
stipulated by the MODE input pin. The device automatically retries with a period of t(OCP)
.
Equation 1 shows the value of the resistor to a particular current setting.
500 mV
R sense
=
Itrip
(1)
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The overcurrent trip level selected cannot be greater than I(OCP)
.
V
(OUTx)
Hi-Z
I(PEAK)
I
(OCP)
I(OUTx)
Enable,
Source
or Sink
t
pd
t
(DEG)
t(OCP)
nFAULT
Motor Lead
Short Condition
Normal DC
No Fault Condition
Figure 7-2. Overcurrent Control Timing
7.3.7 VPROPI
The analog output VPROPI offers SENSE current information as an analog voltage proportional to the current
flowing through the DC motor winding. This voltage can be used by an analog to digital converter and
microcontroller to accurately determine how much current is flowing through the controlled DC motor. See
Section 7.3.6 for guidance on selecting a SENSE resistor value.
7.3.7.1 Connecting VPROPI Output to ADC
The analog output VPROPI varies proportionally with the SENSE voltage according to Equation 2. It’s important
to note even if VSENSE is negative VPROPI will remain at 0 V.
VPROPI = 5 ì VSENSE
(2)
An RC network in series with the VPROPI output is recommended, if this voltage is to be sampled by an analog
to digital converter.
Figure 7-3. RC Network in Series With the VPROPI Output
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It is imperative to realize that VPROPI will decrease to 0 V while the H-Bridge enters slow decay recirculation.
7.3.8 Protection Circuits
The DRV8801A-Q1 device is fully protected against VBB undervoltage, overcurrent, and overtemperature events.
FAULT
ERROR REPORT
H-BRIDGE
CHARGE PUMP
RECOVERY
VBB undervoltage (UVLO) No error report – nFAULT Disabled
is hi-Z
Shut Down
VBB > VUVLO RISING
Overcurrent (OCP)
nFAULT pulled low
Disabled
Enabled
Operating
Operating
Retry time, t(OCP)
Overtemperature Warning nFAULT pulled low
(OTW)
TJ < T(OTW) – Thys(OTW)
Overtemperature
Shutdown (OTS)
nFAULT remains pulled
low (set during OTW)
Disabled
Shut Down
TJ < T(OTS) – Thys(OTS)
7.3.8.1 VBB Undervoltage Lockout (UVLO)
If at any time the voltage on the VBB pin falls below the undervoltage lockout threshold voltage, all FETs in
the H-bridge are disabled and the charge pump is disabled. The nFAULT pin does not report the UVLO fault
condition and remains hi-Z. Operation resumes when VBB rises above the UVLO threshold.
7.3.8.2 Overcurrent Protection (OCP)
The current flowing through the high-side and low-side drivers is monitored to ensure that the motor lead is
not shorted to supply or ground. If a short is detected, all FETs in the H-bridge are disabled, nFAULT is driven
low, and a t(OCP) fault timer is started. After this period, t(OCP), the device is then allowed to follow the input
commands and another turn-on is attempted (nFAULT releases during this attempt). If there is still a fault
condition, the cycle repeats. If the short condition is not present after t(OCP) expires, normal operation resumes
and nFAULT is released.
7.3.8.3 Overtemperature Warning (OTW)
If the die temperature increases past the thermal warning threshold the nFAULT pin is driven low. When the die
temperature has fallen below the hysteresis level, the nFAULT pin is released. If the die temperature continues
to increase, the device enters overtemperature shutdown as described in the Section 7.3.8.4 section.
7.3.8.4 Overtemperature Shutdown (OTS)
If the die temperature exceeds the thermal shutdown temperature, all FETs in the H-bridge are disabled and
the charge pump shuts down. The nFAULT pin remains pulled low during this fault condition. When the die
temperature falls below the hysteresis threshold, operation automatically resumes.
7.4 Device Functional Modes
The DRV8801A-Q1 device is active unless the nSLEEP pin is brought logic low. In sleep mode the charge pump
is disabled and the H-bridge FETs are disabled hi-Z. The DRV8801A-Q1 device is brought out of sleep mode
automatically if nSLEEP is brought logic high.
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8 Application and Implementation
8.1 Application Information
The DRV8801A-Q1 device is used in medium voltage brushed-DC motor control applications.
8.2 Typical Application
100 kꢀ
ANA_VPROPI
VDD
VBB
3.3 kꢀ
0.1 µF
50 V
1000 pF
VDD
PHASE
GND
GND
CP2
3.3 kꢀ
DRV8801A-Q1
0.1 µF
50 V
nSLEEP
ENABLE
CP1
OUTB
0.1 µF
50 V
100 µF
50 V
R(SENSE)
Figure 8-1. Typical Application Diagram
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8.2.1 Design Requirements
The example supply voltage for this design is VBB = 18 V.
8.2.2 Detailed Design Procedure
8.2.2.1 Drive Current
This current path is through the high-side sourcing DMOS driver, motor winding, and low-side sinking DMOS
driver. Power dissipation I2R losses in one source and one sink DMOS driver, as shown in Equation 3.
8.2.2.2
PD = I2(rDS(on)Source + rDS(on)Sink
)
(3)
8.2.2.3 Slow-Decay SR (Brake Mode)
In slow-decay mode, both low-side sinking drivers turn on, allowing the current to circulate through the low side
of the H-bridge (two sink drivers) and the load. Power dissipation I2R loses in the two sink DMOS drivers as
shown in Equation 4
PD = I2(2´rDS(on)Sink
)
(4)
8.2.3 Thermal Considerations
Although DRV8801A-Q1 is rated at 2.8-A of current handling, the previous only holds true as long as the internal
temperature does not exceed 170°C. In order to operate at this rate, the following measures must be taken
under consideration.
8.2.3.1 Junction-to-Ambiant Thermal Impedance (ƟJA)
At any given time during the steady state portion of the cycle, two FETs are enabled: A high side sourcing FET
and a low side sinking FET. The increase in die temperature above ambient can be estimated by Equation 5
oC
2
Tdie = ꢀJA
ì Iwinding ì RDSON + TA
(5)
8.2.4 Pulse-Width Modulating
8.2.4.1 Pulse-Width Modulating ENABLE
The most common H-Bridge direction/speed control scheme is to use a conventional GPIO output for the
PHASE (selects direction) and pulse-width modulate ENABLE for speed control.
8.2.4.2 Pulse-Width Modulating PHASE
A technique that uses a speed/direction control scheme where ENABLE is connected to a GPIO output and
the PHASE is pulse-width modulated. In this case, both direction and speed are controlled with a single signal.
ENABLE is only used to disable the motor and stop all current flow.
When pulse-width modulating PHASE, a 50% duty cycle will stop the motor. Duty cycles above 50% will have
the motor moving on the clockwise direction with proportional control; 100% duty cycle represents full speed.
Duty cycles below 50% will have the motor rotating with a counter clockwise direction; 0% duty cycle represents
full speed.
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8.2.5 Application Curves
OUTA
OUTA
OUTB
OUTB
IO
IO
Figure 8-3. 75% Drive, 25% Fast Decay; ƒ(PWM) = 5
kHz
Figure 8-2. 75% Drive, 25% Slow Decay; ƒ(PWM) = 5
kHz
8.3 Parallel Configuration
It is possible to drive higher than the 2.8 A of current by connecting more than one devices in parallel. To
properly use this option the guidelines documented below must be followed.
8.3.1 Parallel Connections
Figure 8-4 shows the signals that need to be connected together. ENABLE, PHASE, MODE 1, MODE 2,
nSLEEP, OUTA, OUTB, SENSE, VBB and GND.
VBB
MODE 1
MODE 2
ENABLE
PHASE
OUT+
OUT-
SENSE
nSLEEP
DRV8801A-Q1
MODE 1
MODE 2
ENABLE
PHASE
OUT+
OUT-
SENSE
nSLEEP
DRV8801A-Q1
GND
Figure 8-4. Functional Block Diagram (Connected Signals)
8.3.2 Non – Parallel Connections
Figure 8-5 shows the signals that should not be connected together and will be driven on an individual basis.
These are: VCP, CP1, CP2, and VPROPI.
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VBB
VPROPI
CP2
CP1
VCP
DRV8801A-Q1
VBB
VPROPI
CP2
CP1
VCP
DRV8801A-Q1
Figure 8-5. Functional Block Diagram (Individual Signals)
8.3.3 Wiring nFAULT as Wired OR
Since nFAULT is an open drain output, multiple nFAULT outputs can be paralleled with a single resistor. The end
result is a wired OR configuration. When any individual nFAULT output goes to a logic low, the wired OR output
will go to the same logic low. There is no need to determine which device signaled the fault condition, as once
they are connected in parallel they function as a single device.
VDD
NFAULT
DRV8801A-Q1
NFAULT
DRV8801A-Q1
Figure 8-6. nFAULT as Wired OR
8.3.4 Electrical Considerations
8.3.4.1 Device Spacing
It is recommended that devices be connected as close as possible and with trace lengths as short as possible.
Doing this minimizes the potential of generating timing differences between devices. Although it may seem like a
harmful situation for the power stage, DRV8801A-Q1 contains enough protection to effectively deal with enable
time skews from device to device. This consideration focuses on motion quality, as total current needed for
acceleration and proper speed control will only be available when all power stages are brought online.
8.3.4.2 Recirculation Current Handling
During recirculation, it is not possible to synchronize all devices connected in parallel so that the current is
equally distributed. Also, during the asynchronous portion of the current decay, the body diode with the lowest
forward voltage will start conducting and sink all of the current. Said body diode is not meant to handle the new
increased current capacity and will be severely affected if allowed to sink current of said magnitude.
In order to assure proper operation when devices are connected in parallel, it is imperative that external schottky
diodes be used. These schottky diodes will conduct during the asynchronous portion of the recirculation mode
and will sink the inductive load current until the respective FET switches are brought online.
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Schottky diodes should be connected as shown in Figure 8-7.
VBB
VBB
M
VBB
DRV8801A-Q1
GND
Figure 8-7. Schottky Diodes Connection
8.3.4.3 Sense Resistor Selection
The guideline for the SENSE resistor chosen doesn't change in parallel mode. As the goal of this configuration
is to evenly distribute the current load across multiple devices, each device should be configured with the same
ITRIP setting. Therefore, the same SENSE resistor should be used for all devices connected in parallel.
Connection of the SENSE resistors should be as shown in Figure 8-8.
SENSE
DRV8801A-Q1
SENSE
DRV8801A-Q1
Figure 8-8. SENSE Resistors Connection
8.3.4.4 Maximum System Current
The idea behind placing multiple devices in parallel is to increase maximum drive current. At first glance, it may
seem that the new increased ITRIP setting is given by Equation 6.
SystemITRIP = I
ìN
TRIP
(6)
Where:
N is the number of devices connected in parallel.
ITRIP is the individual ITRIP value per device.
However, although in theory accurate, due to tolerances in internal SENSE amplifier/comparator circuitry, the
system ITRIP should be expected to be less than the addition of all the individual ITRIP. The reason for this is
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that as soon as one of the devices senses a current for which the H Bridge should be disabled, the remaining
devices will end up having to conduct the same current but with less capacity. Therefore, remaining devices are
expected to get disabled shortly after.
A good rule of thumb is to expect 90% of the theoretical maximum.
By way of example, if the system level requirements indicate that 6 A of current are required to meet the motion
control requirements, then:
6 A = (2.8 A x 0.9)N
N = (6 A) / (2.8 A x 0.9)
N = 2.38
In this example, three devices would be required to safely meet the needs of the system.
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9 Power Supply Recommendations
The DRV8801A-Q1 device is designed to operate from an input-voltage supply (VBB) range between 6.5 V
and 36 V. One 0.1-µF ceramic capacitor rated for VBB must be placed as close as possible to the VBB pin. In
addition to the local decoupling caps, additional bulk capacitance is required and must be sized accordingly to
the application requirements.
9.1 Bulk Capacitance
Bulk capacitance sizing is an important factor in motor drive system design. This sizing is dependent on a variety
of factors including:
•
•
•
•
•
•
Type of power supply
Acceptable supply voltage ripple
Parasitic inductance in the power supply wiring
Type of motor (brushed DC, brushless DC, stepper)
Motor startup current
Motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands
or dumps from the motor with a change in voltage. Size the bulk capacitance to meet acceptable voltage ripple
levels.
The data sheet generally provides a recommended value but system-level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
External Power Supply
Motor Drive System
V
BB
+
Motor
Driver
œ
GND
Power Supply
Bulk Cap
Local
Bulk Cap
Local
Filter Cap
Figure 9-1. Bulk Capacitance
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10 Layout
10.1 Layout Guidelines
The printed circuit board (PCB) should use a heavy ground plane. For optimum electrical and thermal
performance, the DRV8801A-Q1 device must be soldered directly onto the board. On the bottom side of the
DRV8801A-Q1 device is a thermal pad, which provides a path for enhanced thermal dissipation. The thermal
pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to
other layers of the PCB. For more information on this technique, refer to QFN/SON PCB Attachment.
The load supply pin, VBB, should be decoupled with an electrolytic capacitor (typically 100 μF) in parallel with a
ceramic capacitor placed as close as possible to the device. In order to minimize lead inductance, the ceramic
capacitors between the VCP and VBB pins, connected to the REG pin, and the capacitors between the CP1 and
CP2 pins should be as close to the pins of the device as possible.
10.2 Layout Example
GND
GND
16
15
14
13
5
6
7
8
MODE1
nFAULT
VPROPI
VCP
MODE2
OUTA
GND
OUTA
OUTB
(PPAD)
SENSE
V
BB
0.1 µF
R
(SENSE)
V
BB
0.1 µF
100 µF
0.1 µF
GND
Figure 10-1. DRV8801A-Q1 Layout
10.3 Power Dissipation
First-order approximation of power dissipation in the DRV8801A-Q1 device can be calculated by examining
the power dissipation in the full-bridge during each of the operation modes. The DRV8801A-Q1 device uses
synchronous rectification. During the decay cycle, the body diode is shorted by the low-rDS(on) driver, which
in turn reduces power dissipation in the full-bridge. In order to prevent shoot through (high-side and low-side
drivers on the same side are ON at the same time), the DRV8801A-Q1 device implements a 500-ns typical
crossover delay time. During this period, the body diode in the decay current path conducts the current
until the DMOS driver turns on. High-current and high-ambient-temperature applications should take this into
consideration. In addition, motor parameters and switching losses can add power dissipation that could affect
critical applications.
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
QFN/SON PCB Attachment
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Community Resources
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, And Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8801AQRMJRQ1
ACTIVE
WQFN
RMJ
16
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
DRV8801
ARMJQ1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-May-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8801AQRMJRQ1
WQFN
RMJ
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-May-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RMJ 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
DRV8801AQRMJRQ1
3000
Pack Materials-Page 2
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