DRV8816_15 [TI]
DMOS Dual 1/2-H-Bridge Motor Drivers;
| 型号： | DRV8816_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DMOS Dual 1/2-H-Bridge Motor Drivers |
| 文件： | 总17页 (文件大小：861K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV8816
www.ti.com
SLRS063 –SEPTEMBER 2013
DMOS DUAL ½-H-BRIDGE MOTOR DRIVERS
Check for Samples: DRV8816
1
FEATURES
DESCRIPTION
The DRV8816 provides a versatile power driver
solution with two independent ½-H bridge drivers.
The device can drive one brushed DC motor or one
winding of a stepper motor, as well as other devices
like solenoids. A simple INx/ENx interface allows
easy interfacing to controller circuits.
•
•
•
•
•
•
•
•
Low ON-Resistance (0.83-Ω) Outputs
Individual ½-H bridge control
Low-Power Sleep Mode
100% PWM Supported
8.0 - 38 V Operating Supply Voltage Range
Thermally Enhanced Surface Mount Package
Configurable Overcurrent Limit
Protection Features
The output stages use N-channel power MOSFET’s
configured as ½-H-bridges. The DRV8816 is capable
of peak output currents up to ±2.8 A and operating
voltages up to 38 V. An internal charge pump
generates needed gate drive voltages.
–
–
–
–
–
–
–
–
VBB Undervoltage Lockout (UVLO)
Charge Pump Undervoltage (CPUV)
Overcurrent Protection (OCP)
A low-power sleep mode is provided which shuts
down internal circuitry to achieve very low quiescent
current draw. This sleep mode can be set using a
dedicated nSLEEP pin.
Short-to-Supply Protection (STS)
Short-to-Ground Protection (STG)
Overtemperature Warning (OTW)
Overtemperature Shutdown (OTS)
Fault Condition Indication Pin (nFAULT)
Internal protection functions are provided for under
voltage lockout, charge pump fault, overcurrent
protection, short-to-supply protection, short-to-ground
protection,
overtemperature
warning,
and
overtemperature shutdown. Fault conditions are
indicated via an nFAULT pin
APPLICATIONS
The DRV8816 is packaged in a 16 pin HTSSOP
package with PowerPAD™ (Eco-friendly: RoHS & no
Sb/Br)
•
•
Printers
Industrial Automation
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
DRV8816
SLRS063 –SEPTEMBER 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
BLOCK DIAGRAM
VCP
VBB
VBB
0.1 µF
100 µF
0.1 µF
0.1 µF
VCP
CP2
CP1
Pre-
drive
OUT1
Charge
Pump
VCP
BDC
VBB
IN1
IN2
Pre-
Drive
OUT2
Logic
SENSE
EN1
RSENSE
VPROPI
x5
EN2
VCC
RVPROPI
Undervoltage
nSLEEP
nFAULT
VCC
Temperature
Sensor
GND PPAD
GND
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SLRS063 –SEPTEMBER 2013
nFAULT
EN2
1
2
3
4
5
6
7
8
16
15
14
IN2
VPROPI
IN1
VCP
GND
CP2
CP1
OUT2
VBB
GND
13
12
11
10
9
nSLEEP
EN1
OUT1
SENSE
TERMINAL FUNCTIONS
Name
Pin
Type
Description
Comments
Power and Ground
VBB
9
PWR
Power supply
Device ground
Connect to motor supply voltage; bypass to GND
with a 0.1 µF plus a 100 µF capacitor rated for VBB
GND
VCP
CP1
4, 13
14
PWR
Must be connected to ground
O
-
Charge pump output
Connect a 16 V, 0.1 µF ceramic capacitor to VBB
11
Charge pump switching node
Connect a 0.1 µF X7R capacitor rated for VBB
between CP1 and CP2
CP2
Control
IN1
12
-
I
3
½-H bridge control
½-H bridge enable
Logic high enables the high side ½-H bridge FET;
logic low enables the low side FET; internal
pulldown
IN2
16
EN1
EN2
6
2
5
I
Logic high enables ½-H bridge output; logic low
puts the FETs in HI-Z; internal pulldown
nSLEEP
I
Device sleep mode
Fault indication pin
Pull logic low to put device into a low-power sleep
mode; internal pulldown
nFAULT
1
O
Pulled logic low with fault condition; open-drain
output requires an external pullup
Output
OUT1
7
10
8
O
O
O
½-H bridge output
OUT2
½-H bridge output
SENSE
H-bridge low-side connect
Connect directly to GND or through a sense resistor
to set OCP
VPROPI
VPROPI
15
O
Current-proportional output
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EXTERNAL COMPONENTS
Component
CVBB1
Pin 1
Pin 2
GND
Recommended
VBB
VBB
0.1 µF capacitor rated for VBB
100 µF capacitor rated for VBB
16 V, 0.1 µF ceramic capacitor
> 1 kΩ
CVBB1
GND
CVCP
VCP
VCC(1)
VBB
RnFAULT
RSENSE
nFAULT
GND
SENSE
Optional low-side sense resistor connected to shunt
(1) VCC is not a pin on the DRV8816, but a VCC supply voltage pullup is required for open-drain output nFAULT
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
40
UNIT
V
VBB
Load supply voltage
-0.6
-0.6
-0.6
–0.3
-0.6
-0.6
-0.5
0
Charge Pump Voltage (VCP, CP+)
Charge pump negative switching pin range (CP-)
Digital pin voltage range (IN1, IN2, EN1, EN2, nSLEEP, nFAULT)
VBB to OUTx
VBB + 7
VBB
7
V
V
VDD
V
40
V
OUTx to SENSE
40
V
VSense
Sense voltage (SENSE)
1.0
v
H-bridge output current (OUT1, OUT2, SENSE)
VPROPI pin voltage range (VPROPI)
Operating ambient temperature
Operating junction temperature
Storage temperature range
2.8
A
-0.3
-40
-40
-40
3.6
V
TA
Tj
85
190
125
°C
Tstg
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ELECTROSTATIC DISCHARGE PROTECTION
MIN
2000
500
MAX
UNIT
HBM on any other pin
V
Charge Device Model (CDM)
4
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SLRS063 –SEPTEMBER 2013
THERMAL INFORMATION
DRV8816
THERMAL METRIC(1)
PWP - HTSSOP
UNITS
16 PINS
43.9
30.8
25.3
1.1
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
°C/W
ψJT
ψJB
25
θJCbot
5.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS(1)
MIN
MAX
38
UNIT
V
VBB
VCC
fPWM
IOUT
TA
Power supply voltage range
Logic voltage
8
5.5
100
2.8
85
V
Applied PWM signal (IN1 and IN2)
H-bridge output current
Ambient temperature
kHz
A
–40
°C
(1) Power dissipation and thermal limits must be observed.
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ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VBB)
VBB
VBB operating voltage
8
38
10
V
fPWM < 50 kHz
6
mA
mA
µA
IVBB
VBB operating supply current
Charge pump on, Outputs disabled
3.2
IVBBQ
VBB sleep-mode supply current nSLEEP = 0, TJ = 25°C
CONTROL INPUTS (IN1, IN2, EN1, EN2, nSLEEP)
VIL
VIH
IIL
Input logic low voltage
Input logic high voltage
Input logic low current
Input logic high current
Input logic low current
Input logic high current
Input logic low voltage
Input logic high voltage
Input logic low current
Input logic high current
Pulldown resistance
VIN = 0.8 V
VIN = 2.0 V
VIN = 0.8 V
VIN = 2.0 V
VIN = 0.8 V
VIN = 2.0 V
VIN = 0.8 V
VIN = 2.8 V
VIN = 0.8 V
VIN = 2.8 V
0
2
0.8
5.5
+20
20
IN1, IN2, EN1, EN2
IN1, IN2, EN2
EN1
V
–20
μA
μA
IIH
IIL
16
40
40
IIH
100
0.8
VIL
VIH
IIL
V
V
2.2
nSLEEP
10
50
μA
kΩ
IIH
27
RPD
100
SERIAL AND CONTROL OUTPUT (nFAULT)
VOL Output logic low voltage Isink = 1 mA
DMOS DRIVERS (OUT1, OUT2, SENSE)
0.4
V
Source driver, IOUT = –2.8 A, TJ = 25°C
Source driver, IOUT = –2.8 A, TJ = 125°C
Sink driver, IOUT = –2.8 A, TJ = 25°C
Sink driver, IOUT = –2.8 A, TJ = 125°C
RSENSE between SENSE and GND
Source diode, If = –2.8 A
0.48
0.74
0.35
0.52
500
0.85
0.7
Rds(ON)
Output ON resistance
Ω
VTRP
Vf
SENSE trip voltage
mV
V
1.4
1.4
Body diode forward voltage
Sink diode, If = 2.8 A
INx, Change to source or sink ON
INx, Change to source or sink OFF
600
100
500
5
tpd
Propagation delay time
Crossover delay
ns
tCOD
ns
DAGain Differential amplifier gain
Sense = 0.1 V to 0.4 V
V/V
Protection Circuits
VUVLO
VCPUV
IOCP
VBB undervoltage lockout
VCP undervoltage lockout(1)
Overcurrent protection trip level
Overcurrent deglitch time
Overcurrent retry time
VBB rising
6.5
12
7.5
V
V
VBB rising; CPUV recovery
13.8
3
A
tDEG
3.0
1.6
160
15
µs
ms
°C
°C
°C
°C
tOCP
TOTW
Thermal shutdown temperature Die temperature Tj
TOTW HYS Thermal shutdown hysteresis
TOTS Thermal shutdown hysteresis
TOTS HYS Thermal shutdown hysteresis
Die temperature Tj
Die temperature Tj
Die temperature Tj
175
15
(1) Whenever VCP is less than VM + 10 V, a CPUV event occurs. This fault will be asserted whenever VBB is below 12 V. Note that the H-
bridges will remain enabled until VBB = VUVLO even through nFAULT is pulled low.
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FUNCTIONAL DESCRIPTION
Power Supervisor
Control input nSLEEP is used to minimize power consumption when the DRV8816 is not in use. This disables
much of the internal circuitry, including the internal voltage rails and charge pump. nSLEEP is asserted low. A
logic high on this input pin results in normal operation. When switching from low to high, the user should allow a
1-ms delay before applying PWM signals. This time is needed for the charge pump to stabilize.
Bridge Control
The DRV8816 is controlled using separate enable and input pins for each ½-H-bridge.
The following table shows the logic for the DRV8816:
ENx
INx
X
OUTx
0
1
1
Z
L
0
1
H
If a single DC motor is connected to the DRV8816, it is connected between the OUT1 and OUT2 pins as shown
in the first image below. Two DC motors may also be connected to the DRV8816. In this mode, it is not possible
to reverse the direction of the motors; they will turn only in one direction. The connections are shown below:
VBB
BDC
VBB
OUT1
OUT1
OUT1
BDC
BDC
BDC
OUT2
OUT2
OUT2
BDC
Motor operation for a single brushed DC motor is controlled as follows:
EN1
0
EN2
X
IN1
X
X
0
IN2
X
X
0
OUT1
OUT2
Operation
Off (coast)
Off (coast)
Brake
Z
See (1)
X
0
See (1)
Z
L
1
1
L
L
1
1
0
1
H
L
Reverse
Forward
Brake
1
1
1
0
H
H
1
1
1
1
H
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Motor operation for dual brushed DC motors is controlled as follows:
Motor connected
to GND
ENx
INx
X
OUTx
Operation
Off (coast)
Brake
0
1
1
Z
L
0
1
H
Forward
Motor connected
to VBB
ENx
INx
X
OUTx
Operation
Off (coast)
Forward
Brake
0
1
1
Z
L
0
1
H
Charge Pump
The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates. A 0.1-μF
ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1-μF
ceramic monolithic capacitor should be connected between VCP and VBB to act as a reservoir to run the high-
side DMOS devices. The VCP voltage level is internally monitored and, in the case of a fault condition, the
outputs of the device are disabled.
VBB
0.1 µF
VCP
CP1
Charge
Pump
VM
0.1 µF
CP2
SENSE
A low-value resistor can be placed between the SENSE pin and ground for current-sensing purposes. To
minimize ground-trace IR drops in sensing the output current level, the current-sensing resistor should have an
independent ground return to the star ground point. This trace should be as short as possible. For low-value
sense resistors, the IR drops in the PCB can be significant, and should be taken into account.
To set a manual overcurrent trip threshold, place a resistor between the SENSE pin and GND. When the SENSE
pin rises above 500 mV, the H-bridge output is disabled (High-Z). The device will automatically retry with a period
of tOCP
.
The overcurrent trip threshold can be calculated using Itrip = 500 mV/R. The overcurrent trip level selected cannot
be greater than IOCP
.
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VOUT+
VOUT-
High-Z
IPEAK
I
OCP
IOUTx
Enable,
Source
or Sink
t
BLANK
tOCP
nFAULT
Motor Lead
Short Condition
Normal DC
No Fault Condition
VPROPI
The VPROPI output is equal to approximately five times the voltage present on the SENSE pin. VPROPI is
meaningful only if there is a resistor connected to the SENSE pin; If SENSE is connected to ground, VPROPI
measures 0 V. Also note that during slow decay (brake), VPROPI will measure 0 V. VPROPI can output a
maximum of 2.5 V, since at 500 mV on SENSE, the H-bridge is disabled.
Protection Circuits
The DRV8816 is fully protected against VBB undervoltage, charge pump undervoltage, overcurrent, and
overtemperature events.
VBB UNDERVOLTAGE LOCKOUT (UVLO)
If at any time the voltage on the VBB pin falls below the undervoltage lockout threshold voltage, all FETs in the
H-bridge will be disabled and the charge pump will be disabled. Operation will resume when VBB rises above the
UVLO threshold. Note that nFAULT does not indicate a UVLO because the CPUV fault is always asserted below
VBB = 12 V.
VCP UNDERVOLTAGE LOCKOUT (CPUV)
During a CPUV event, the VCP voltage is measured to be below VCP + 10 V. If at any time the voltage on the
VCP pin falls below the undervoltage lockout threshold voltage, the nFAULT pin will be driven low. The nFAULT
pin will be released after operation has resumed. Note that this fault does not disable the output FETs and allows
the device to continue operating. When VBB is below 12 V, this fault condition is always asserted and nFAULT is
pulled low.
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OVERCURRENT PROTECTION (OCP)
The current flowing through the high-side and low-side drivers is monitored to ensure that the motor lead is not
shorted to supply or ground. If a short is detected, all FETs in the H-bridge will be disabled, nFAULT is driven
low, and a tOCP fault timer is started. After this period, tOCP, the device is then allowed to follow the input
commands and another turn-on is attempted (nFAULT becomes high again during this attempt). If there is still a
fault condition, the cycle repeats. If after tOCP expires it is determined the short condition is not present, normal
operation resumes and nFAULT is released.
OVERTEMPERATURE WARNING (OTW)
If the die temperature increases past the thermal warning threshold the nFAULT pin will be driven low. Once the
die temperature has fallen below the hysteresis level, the nFAULT pin will be released. If the die temperature
continues to increase, the device will enter over temperature shutdown as described below.
OVERTEMPERATURE SHUTDOWN (OTS)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the charge pump will be
shut down. Once the die temperature has fallen to a safe level operation will automatically resume.
THERMAL INFORMATION
Thermal Protection
If the die temperature exceeds approximately 150°C, the device will be disabled until the temperature drops to a
safe level. Any tendency of the device to enter thermal shutdown is an indication of either excessive power
dissipation, insufficient heatsinking, or too high an ambient temperature.
Power Dissipation
Power dissipation in the DRV8816 is dominated by the power dissipated in the output FET resistance, or RDS(ON)
.
Average power dissipation can be roughly estimated by:
2
PTOT = RD SON ´ (IOUT RMS )
(
)
(
)
(1)
where PTOT is the total power dissipation, RD(SON) is the resistance of the HS plus LS FETS, and IOUT(RMS) is the
RMS output current being applied to each winding. IOUT(RMS) is equal to approximately 0.7× the full-scale output
current setting.
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases.
PCB LAYOUT
Ground
A ground power plane should be located as close to DRV8816 as possible. The copper ground plane directly
under the PowerPAD package makes a good location. This pad can then be connected to ground for this
purpose.
Layout Considerations
The printed circuit board (PCB) should use a heavy ground plane. For optimum electrical and thermal
performance, the DRV8816 must be soldered directly onto the board. On the underside of the DRV8816 is a
PowerPAD package, which provides a path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the
PCB.
The load supply pin, VBB, should be decoupled with an electrolytic capacitor (typically 100 μF) in parallel with a
ceramic capacitor placed as close as possible to the device. The ceramic capacitors between VCP and VBB,
connected to VREG, and between CP1 and CP2 should be as close to the pins of the device as possible, in
order to minimize lead inductance.
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PACKAGE OPTION ADDENDUM
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30-Sep-2013
PACKAGING INFORMATION
Orderable Device
DRV8816PWP
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
HTSSOP
HTSSOP
PWP
16
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-3-260C-168 HR
DRV8816
DRV8816
DRV8816PWPR
ACTIVE
PWP
2000
Green (RoHS
& no Sb/Br)
Level-3-260C-168 HR
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8816PWPR
HTSSOP PWP
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
DRV8816PWPR
2000
Pack Materials-Page 2
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