DRV8833 [TI]
DUAL H-BRIDGE MOTOR DRIVER; 双H桥式电动机驱动器
| 型号： | DRV8833 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL H-BRIDGE MOTOR DRIVER |
| 文件： | 总22页 (文件大小：960K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRV8833
www.ti.com
SLVSAR1B –JANUARY 2011–REVISED AUGUST 2011
DUAL H-BRIDGE MOTOR DRIVER
Check for Samples: DRV8833
1
FEATURES
•
•
PWM Winding Current Regulation/Limiting
Thermally Enhanced Surface Mount Package
2
•
Dual-H-Bridge Current-Control Motor Driver
–
–
Capable of Driving Two DC Motors or One
Stepper Motor
APPLICATIONS
•
•
•
•
•
•
Battery-Powered Toys
POS Printers
Low MOSFET On-Resistance:
HS + LS 360 mΩ
•
•
•
Output Current 1.5-A RMS, 2-A Peak per
H-Bridge (at VM = 5 V, 25°C)
Video Security Cameras
Office Automation Machines
Gaming Machines
Robotics
Outputs Can Be Paralleled for 3-A RMS,
4-A Peak
Wide Power Supply Voltage Range:
2.7 V – 10.8 V
DESCRIPTION
The DRV8833 provides a dual bridge motor driver solution for toys, printers, and other mechatronic applications.
The device has two H-bridge drivers, and can drive two DC brush motors, a bipolar stepper motor, solenoids, or
other inductive loads.
The output driver block of each H-bridge consists of N-channel power MOSFET’s configured as an H-bridge to
drive the motor windings. Each H-bridge includes circuitry to regulate or limit the winding current.
With proper PCB design, each H-bridge of the DRV8833 is capable of driving up to 1.5-A RMS (or DC)
continuously, at 25°C with a VM supply of 5 V. It can support peak currents of up to 2 A per bridge. Current
capability is reduced slightly at lower VM voltages.
Internal shutdown functions with a fault output pin are provided for over current protection, short circuit
protection, under voltage lockout and overtemperature. A low-power sleep mode is also provided.
The DRV8833 is packaged in a 16-pin HTSSOP or QFN package with PowerPAD™ (Eco-friendly: RoHS & no
Sb/Br).
ORDERING INFORMATION(1)
ORDERABLE PART
NUMBER
TOP-SIDE
MARKING
PACKAGE(2)
PowerPAD™ (HTSSOP) - PWP
Reel of 2000
Tube of 90
DRV8833PWPR
DRV8833PWP
DRV8833RTYR
DRV8833RTYT
DRV8833
DRV8833
Reel of 3000
Reel of 250
PowerPAD™ (QFN) - RTY
(1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
DRV8833
SLVSAR1B –JANUARY 2011–REVISED AUGUST 2011
www.ti.com
DEVICE INFORMATION
Functional Block Diagram
2.2uF
VINT
VM
VM
Internal
Ref &
Regs
VM
Charge
Pump
VCP
0.01uF
10uF
VM
Drives 2x DC motor
or 1x Stepper
AOUT1
Gate
AIN1
AIN2
Drive
&
OCP
Step
Motor
DCM
VM
AOUT2
AISEN
BIN1
BIN2
ISEN
VM
Logic
nSLEEP
BOUT1
nFAULT
Gate
Drive
&
DCM
VM
OCP
Over-
Temp
BOUT2
BISEN
ISEN
GND
2
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NAME
SLVSAR1B –JANUARY 2011–REVISED AUGUST 2011
Table 1. TERMINAL FUNCTIONS
PIN
(PWP)
PIN
(RTY)
EXTERNAL COMPONENTS
OR CONNECTIONS
I/O(1)
DESCRIPTION
POWER AND GROUND
Both the GND pin and device
PowerPAD must be connected to
ground
13
PPAD
11
PPAD
GND
-
-
Device ground
Connect to motor supply. A 10-µF
(minimum) ceramic bypass capacitor to
GND is recommended.
VM
12
10
Device power supply
Bypass to GND with 2.2-μF, 6.3-V
capacitor
VINT
14
11
12
9
-
Internal supply bypass
Connect a 0.01-μF, 16-V (minimum)
X7R ceramic capacitor to VM
VCP
IO
High-side gate drive voltage
CONTROL
AIN1
Logic input controls state of AOUT1.
Internal pulldown.
16
15
9
14
13
7
I
I
I
I
Bridge A input 1
Bridge A input 2
Bridge B input 1
Bridge B input 2
Logic input controls state of AOUT2.
Internal pulldown.
AIN2
BIN1
BIN2
Logic input controls state of BOUT1.
Internal pulldown.
Logic input controls state of BOUT2.
Internal pulldown.
10
8
Logic high to enable device, logic low to
enter low-power sleep mode and reset
all internal logic. Internal pulldown.
nSLEEP
1
8
15
6
I
Sleep mode input
Fault output
STATUS
nFAULT
OUTPUT
Logic low when in fault condition
(overtemp, overcurrent)
OD
Connect to current sense resistor for
bridge A, or GND if current control not
needed
AISEN
BISEN
3
6
1
4
IO
IO
Bridge A ground / Isense
Bridge B ground / Isense
Connect to current sense resistor for
bridge B, or GND if current control not
needed
AOUT1
AOUT2
BOUT1
BOUT2
2
4
7
5
16
2
O
O
O
O
Bridge A output 1
Bridge A output 2
Bridge B output 1
Bridge B output 2
Connect to motor winding A
Connect to motor winding B
5
3
(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output
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DRV8833
SLVSAR1B –JANUARY 2011–REVISED AUGUST 2011
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PWP PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
nSLEEP
AOUT1
AISEN
AOUT2
BOUT2
BISEN
16
15
14
13
12
11
10
9
AIN1
AIN2
VINT
GND
VM
VCP
BIN2
BIN1
GND
(PPAD)
BOUT1
nFAULT
RTY PACKAGE
(TOP VIEW)
1
2
3
4
12
AISEN
VINT
GND
VM
GND
(PPAD)
11
10
9
AOUT2
BOUT2
BISEN
VCP
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SLVSAR1B –JANUARY 2011–REVISED AUGUST 2011
ABSOLUTE MAXIMUM RATINGS(1)(2)
VALUE
–0.3 to 11.8
–0.5 to 7
UNIT
V
VM
Power supply voltage range
Digital input pin voltage range
xISEN pin voltage
V
–0.3 to 0.5
Internally limited
–40 to 150
–60 to 150
V
Peak motor drive output current
Operating junction temperature range
Storage temperature range
A
TJ
°C
°C
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
THERMAL INFORMATION
PWP
16 PINS
40.5
RTY
16 PINS
37.2
THERMAL METRIC
UNITS
θJA
Junction-to-ambient thermal resistance(1)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance(3)
Junction-to-top characterization parameter(4)
Junction-to-board characterization parameter(5)
Junction-to-case (bottom) thermal resistance(6)
θJCtop
θJB
32.9
34.3
28.8
15.3
°C/W
ψJT
0.6
0.3
ψJB
11.5
15.4
θJCbot
4.8
3.5
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
TA = 25°C (unless otherwise noted)
MIN
2.7
NOM
MAX
10.8
5.75
1.5
UNIT
VM
Motor power supply voltage range(1)
Digital input pin voltage range
Continuous RMS or DC output current per bridge(2)
V
V
A
VDIGIN
IOUT
-0.3
(1) Note that RDS(ON) increases and maximum output current is reduced at VM supply voltages below 5 V.
(2) VM = 5 V, power dissipation and thermal limits must be observed.
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ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
IVM
VM operating supply current
VM sleep mode supply current
VM = 5 V, xIN1 = 0 V, xIN2 = 0 V
VM = 5 V
1.7
1.6
3
2.5
2.6
mA
μA
V
IVMQ
VUVLO
VM undervoltage lockout voltage VM falling
VM undervoltage lockout
hysteresis
VHYS
90
mV
LOGIC-LEVEL INPUTS
nSLEEP
0.5
0.7
VIL
Input low voltage
V
All other pins
nSLEEP
2.5
2
VIH
VHYS
RPD
IIL
Input high voltage
Input hysteresis
V
All other pins
0.4
500
150
V
nSLEEP
Input pull-down resistance
Input low current
kΩ
μA
μA
ns
All except nSLEEP
VIN = 0
1
13
33
VIN = 3.3 V, nSLEEP
VIN = 3.3 V, all except nSLEEP
6.6
16.5
450
IIH
Input high current
tDEG
Input deglitch time
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
VOL
IOH
Output low voltage
IO = 5 mA
VO = 3.3 V
0.5
1
V
Output high leakage current
μA
H-BRIDGE FETS
VM = 5 V, I O = 500 mA, TJ = 25°C
VM = 5 V, IO = 500 mA, TJ = 85°C
VM = 2.7 V, I O = 500 mA, TJ = 25°C
VM = 2.7 V, IO = 500 mA, TJ = 85°C
VM = 5 V, I O = 500 mA, TJ = 25°C
VM = 5 V, IO = 500 mA, TJ = 85°C
VM = 2.7 V, I O = 500 mA, TJ = 25°C
VM = 2.7 V, IO = 500 mA, TJ = 85°C
VM = 5 V, TJ = 25°C, VOUT = 0 V
200
250
160
200
325
350
275
HS FET on resistance
RDS(ON)
mΩ
μA
LS FET on resistance
300
1
IOFF
Off-state leakage current
–1
MOTOR DRIVER
fPWM Current control PWM frequency
tR
Internal PWM frequency
VM = 5 V, 16 Ω to GND, 10% to 90% VM
VM = 5 V, 16 Ω to GND, 10% to 90% VM
VM = 5 V
50
180
160
1.1
kHz
ns
Rise time
tF
Fall time
ns
tPROP
tDEAD
Propagation delay INx to OUTx
Dead time(1)
µs
VM = 5 V
450
ns
PROTECTION CIRCUITS
IOCP
tDEG
tOCP
tTSD
Overcurrent protection trip level
2
3.3
2.25
1.35
160
A
OCP Deglitch time
µs
ms
°C
Overcurrent protection period
Thermal shutdown temperature
Die temperature
150
180
(1) Internal dead time. External implementation is not necessary.
6
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ELECTRICAL CHARACTERISTICS (continued)
TA = 25°C (unless otherwise noted)
PARAMETER
CURRENT CONTROL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VTRIP
xISEN trip voltage
160
200
240
mV
tBLANK
Current sense blanking time
3.75
µs
SLEEP MODE
tWAKE
Startup time
nSLEEP inactive high to H-bridge on
1
ms
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FUNCTIONAL DESCRIPTION
PWM Motor Drivers
DRV8833 contains two identical H-bridge motor drivers with current-control PWM circuitry. A block diagram of the
circuitry is shown below:
VM
OCP
VM
VCP, VINT
xOUT1
xIN1
Pre-
DCM
drive
xOUT2
xIN2
PWM
OCP
xISEN
-
+
Optional
REF (200mV)
Figure 1. Motor Control Circuitry
Bridge Control and Decay Modes
The AIN1 and AIN2 input pins control the state of the AOUT1 and AOUT2 outputs; similarly, the BIN1 and BIN2
input pins control the state of the BOUT1 and BOUT2 outputs. Table 2 shows the logic.
Table 2. H-Bridge Logic
xIN1
xIN2
xOUT1
xOUT2
FUNCTION
Coast/fast
decay
0
0
Z
Z
0
1
1
0
L
H
L
Reverse
Forward
H
Brake/slow
decay
1
1
L
L
The inputs can also be used for PWM control of the motor speed. When controlling a winding with PWM, when
the drive current is interrupted, the inductive nature of the motor requires that the current must continue to flow.
This is called recirculation current. To handle this recirculation current, the H-bridge can operate in two different
states, fast decay or slow decay. In fast decay mode, the H-bridge is disabled and recirculation current flows
through the body diodes; in slow decay, the motor winding is shorted.
To PWM using fast decay, the PWM signal is applied to one xIN pin while the other is held low; to use slow
decay, one xIN pin is held high.
Table 3. PWM Control of Motor Speed
xIN1
PWM
1
xIN2
0
FUNCTION
Forward PWM, fast decay
Forward PWM, slow decay
Reverse PWM, fast decay
Reverse PWM, slow decay
PWM
PWM
1
0
PWM
8
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Figure 2 shows the current paths in different drive and decay modes.
VM
VM
1
2
3
Forward drive
Fast decay
Slow decay
1
2
3
Reverse drive
Fast decay
1
2
1
2
xOUT2
xOUT1
xOUT1
xOUT2
Slow decay
3
3
FORWARD
REVERSE
Figure 2. Decay Modes
Current Control
The current through the motor windings may be limited, or controlled, by a fixed-frequency PWM current
regulation, or current chopping. For DC motors, current control is used to limit the start-up and stall current of the
motor. For stepper motors, current control is often used at all times.
When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage and
inductance of the winding. If the current reaches the current chopping threshold, the bridge disables the current
until the beginning of the next PWM cycle. Note that immediately after the current is enabled, the voltage on the
xISEN pin is ignored for a fixed period of time before enabling the current sense circuitry. This blanking time is
fixed at 3.75 μs. This blanking time also sets the minimum on time of the PWM when operating in current
chopping mode.
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor
connected to the xISEN pins with a reference voltage. The reference voltage is fixed at 200 mV.
The chopping current is calculated in Equation 1.
200 mV
ICHOP =
RISENSE
(1)
Example:
If a 1-Ω sense resistor is used, the chopping current will be 200 mV/1 Ω = 200 mA.
Once the chopping current threshold is reached, the H-bridge switches to slow decay mode. Winding current is
re-circulated by enabling both of the low-side FETs in the bridge. This state is held until the beginning of the next
fixed-frequency PWM cycle.
Note that if current control is not needed, the xISEN pins should be connected directly to ground.
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nSLEEP Operation
Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the
gate drive charge pump is stopped, all internal logic is reset, and all internal clocks are stopped. All inputs are
ignored until nSLEEP returns inactive high. When returning from sleep mode, some time (up to 1 ms) needs to
pass before the motor driver becomes fully operational. To make the board design simple, the nSLEEP can be
pulled up to the supply (VM). It is recommended to use a pullup resistor when this is done. This resistor limits the
current to the input in case VM is higher than 6.5 V. Internally, the nSLEEP pin has a 500-kΩ resistor to GND. It
also has a clamping zener diode that clamps the voltage at the pin at 6.5 V. Currents greater than 250 µA can
cause damage to the input structure. Hence the recommended pullup resistor would be between 20 kΩ and
75 kΩ.
Protection Circuits
The DRV8833 is fully protected against undervoltage, overcurrent and overtemperature events.
Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive. If this
analog current limit persists for longer than the OCP deglitch time, all FETs in the H-bridge will be disabled and
the nFAULT pin will be driven low. The driver will be re-enabled after the OCP retry period (tOCP) has passed.
nFAULT becomes high again at this time. If the fault condition is still present, the cycle repeats. If the fault is no
longer present, normal operation resumes and nFAULT remains deasserted. Please note that only the H-bridge
in which the OCP is detected will be disabled while the other bridge will function normally.
Overcurrent conditions are detected independently on both high and low side devices; i.e., a short to ground,
supply, or across the motor winding will all result in an overcurrent shutdown. Note that overcurrent protection
does not use the current sense circuitry used for PWM current control, so functions even without presence of the
xISEN resistors.
Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be
driven low. Once the die temperature has fallen to a safe level operation will automatically resume.
Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the
device will be disabled, and all internal logic will be reset. Operation will resume when VM rises above the UVLO
threshold. nFAULT is driven low in the event of an undervoltage condition.
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APPLICATIONS INFORMATION
Parallel Mode
The two H-bridges in the DRV8833 can be connected in parallel for double the current of a single H-bridge. The
internal dead time in the DRV8833 prevents any risk of cross-conduction (shoot-through) between the two
bridges due to timing differences between the two bridges. The drawing below shows the connections.
Figure 3. Parallel Mode
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THERMAL INFORMATION
Maximum Output Current
In actual operation, the maximum output current achievable with a motor driver is a function of die temperature.
This in turn is greatly affected by ambient temperature and PCB design. Basically, the maximum motor current
will be the amount of current that results in a power dissipation level that, along with the thermal resistance of the
package and PCB, keeps the die at a low enough temperature to stay out of thermal shutdown.
The dissipation ratings given in the datasheet can be used as a guide to calculate the approximate maximum
power dissipation that can be expected to be possible without entering thermal shutdown for several different
PCB constructions. However, for accurate data, the actual PCB design must be analyzed via measurement or
thermal simulation.
Thermal Protection
The DRV8833 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately
150°C, the device will be disabled until the temperature drops by 45°C.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
Power Dissipation
Power dissipation in the DRV8833 is dominated by the DC power dissipated in the output FET resistance, or
RDS(ON). There is additional power dissipated due to PWM switching losses, which are dependent on PWM
frequency, rise and fall times, and VM supply voltages. These switching losses are typically on the order of 10%
to 30% of the DC power dissipation.
The DC power dissipation of one H-bridge can be roughly estimated by Equation 2.
2
PTOT = (HS - RDS(ON) · IOUT(RMS)2) + (LS - RDS(ON) · IOUT(RMS)
)
(2)
where PTOT is the total power dissipation, HS - RDS(ON) is the resistance of the high side FET, LS - RDS(ON) is the
resistance of the low side FET, and IOUT(RMS) is the RMS output current being applied to the motor.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.
Heatsinking
The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs
without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area
is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and
bottom layers.
For details about how to design the PCB, refer to TI application report SLMA002, " PowerPAD™ Thermally
Enhanced Package" and TI application brief SLMA004, " PowerPAD™ Made Easy", available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated.
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
DRV8833PWP
DRV8833PWPR
DRV8833RTYR
DRV8833RTYT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
QFN
PWP
PWP
RTY
RTY
16
16
16
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
2000
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8833PWPR
DRV8833RTYR
DRV8833RTYT
HTSSOP PWP
16
16
16
2000
3000
250
330.0
330.0
180.0
12.4
12.4
12.4
6.9
5.6
1.6
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q2
Q2
QFN
QFN
RTY
RTY
4.25
4.25
4.25
4.25
1.15
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV8833PWPR
DRV8833RTYR
DRV8833RTYT
HTSSOP
QFN
PWP
RTY
RTY
16
16
16
2000
3000
250
346.0
346.0
210.0
346.0
346.0
185.0
29.0
29.0
35.0
QFN
Pack Materials-Page 2
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