DS100BR410SQ [TI]

Low Power Quad Channel Repeater with 10.3125 Gbps Equalizer and De-Emphasis Driver; 低功耗四通道中继器与10.3125 Gbps的均衡和去加重驱动器


型号：	DS100BR410SQ
厂家：	TEXAS INSTRUMENTS
描述：	Low Power Quad Channel Repeater with 10.3125 Gbps Equalizer and De-Emphasis Driver 低功耗四通道中继器与10.3125 Gbps的均衡和去加重驱动器驱动器中继器
文件：	总21页 (文件大小：1453K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

March 22, 2012

DS100BR410

Low Power Quad Channel Repeater with 10.3125 Gbps

Equalizer and De-Emphasis Driver

General Description

Features

The DS100BR410 is an extremely low power, high perfor-

mance quad-channel repeater for high-speed serial links with

data rates up to 10.3125 Gbps. The device performs both re-

ceive equalization and transmit de-emphasis on each of its 4

channels to compensate for channel loss, allowing maximum

flexibility of physical placement within a system.

Quad channel repeater for up to 10.3125 Gbps

■

Low power consumption, with option to power down

unused channels

Adjustable receive equalization

■

Adjustable transmit de-emphasis

Adjustable transmit V_OD(up to 1200 mVp-p)

The receiver's continuous time linear equalizer (CTLE) is ca-

pable of opening an input eye that is completely closed due

to inter-symbol interference (ISI) induced by the interconnect

medium such as backplane trace or cable. The transmitter

features adjustable V_OD(output amplitude voltage level) and

de-emphasis driver to compensate for PCB trace lost.

IDLE detection — squelch function auto mutes the output

for SATA/SAS OOB signal

<0.22 UI of residual DJ at 10.3125 Gbps with 12 meters

cable

■

Programmable via pin selection or SMBus interface

■

With a low power consumption and control to turn-off unused

channels, the DS100BR410 is part of National's PowerWise

family of energy efficient devices.

Single supply operation at 2.5 V ±5%

-40°C to +85°C Operation

≥7 kV HBM ESD Rating

High speed signal flow–thru pinout package: 48-pin LLP

(7 mm x 7 mm, 0.5 mm pitch)

The programmable settings can be applied via pin mode or

SMBus mode interface.

Applications

High-speed active copper cable modules

■

FR-4 Backplanes

10GE, 8GFC, 10GFC, 10G SONET, SAS, SATA, and

InfiniBand

Typical Application Diagram

30122480

301224 SNLS326A

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Connection Diagram

30122426

Ordering Information

NSID

Package Description

Quantity

Package

Spec

NOPB

DS100BR410SQE 48-pin LLP (7mm X 7mm X 0.8mm, 0.5mm pitch)

250 in Tape & Reel

1000 in Tape & Reel

2500 in Tape & Reel

SQA48A

DS100BR410SQ

48-pin LLP (7mm X 7mm X 0.8mm, 0.5mm pitch)

DS100BR410SQX 48-pin LLP (7mm X 7mm X 0.8mm, 0.5mm pitch)

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Pin Descriptions

Pin Name

Pin #

I/O, Type

Description

HIGH SPEED DIFFERENTIAL I/O

IN_0+

IN_0–

I, CML

O, CML

Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω

terminating resistor connects IN_0+ to IN_0-.

IN_1+

IN_1–

Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω

terminating resistor connects IN_1+ to IN_1-.

IN_2+

IN_2–

Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω

terminating resistor connects IN_2+ to IN_2-.

IN_3+

IN_3–

Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω

terminating resistor connects IN_3+ to IN_3-.

OUT_0+

OUT_0–

Inverting and non-inverting CML differential outputs from the driver. An on-chip 100Ω

terminating resistor connects OUT_0+ to OUT_0-.

OUT_1+

OUT_1–

Inverting and non-inverting CML differential outputs from the driver. An on-chip 100Ω

terminating resistor connects OUT_1+ to OUT_1-.

OUT_2+

OUT_2–

Inverting and non-inverting CML differential outputs from the driver. An on-chip 100Ω

terminating resistor connects OUT_2+ to OUT_2-.

OUT_3+

OUT_3–

Inverting and non-inverting CML differential outputs from the driver. An on-chip 100Ω

terminating resistor connects OUT_3+ to OUT_3-.

2.5V LVCMOS CONTROL PINS

BST_2

BST_1

BST_0

I, LVCMOS BST_2, BST_1, and BST_0 select the equalizer boost level for all channels.

BST_2 and BST_1 are internally pulled high.

BST_0 is internally pulled low. See Table 1

EN0

EN1

EN2

EN3

I, LVCMOS Enable channel n input.

When held High, normal operation is selected.

When held Low, standby mode is selected.

EN is internally pulled High.

PIN_MODE

I, LVCMOS Pin mode control input.

When held High, device is in Pin control mode.

When held Low, device is in SMBus Control Mode

PIN_MODE is internally pulled High.

SD0

SD1

SD2

SD3

O, LVCMOS Signal detect n output.

Output is High when signal is detected.

Output is Low when signal is NOT detected.

OOB_DIS

I, LVCMOS OOB disable control input.

When held High, OOB is disabled.

When held Low, OOB is enabled.

Out Of Band (OOB) for SATA/SAS applications is active.

OOB_DIS is internally pulled Low.

Analog Input Pins (4–level Inputs)

VOD_SEL

I, analog

Differential Output Voltage Select Input

Tie to V_DD, V_OD= 1.2 Vp-p

Leave Open, V_OD= 1.0 Vp-p

Resistor (20 kΩ) to GND, V_OD= 800 mVp-p

Tie to GND, V_OD= 600 mVp-p

DE_SEL

De-Emphasis Select Input

Tie to V_DD= -9 dB

Leave Open = -6 dB

Resistor (20 kΩ) to GND = -3 dB

Tie to GND = 0 dB

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Pin Name

Pin #

I/O, Type

Description

SERIAL MANAGEMENT BUS (SMBus) INTERFACE

SDA

I/O, LVCMOS Data Input / Open Drain Output

External pull-up resistor is required.

Pin is 3.3 V LVCMOS tolerant.

SDC

I, LVCMOS Clock Input

Pin is 3.3 V LVCMOS tolerant.

I, LVCMOS Chip Select

When high, access to the SMBus registers are enabled. When low, access to the SMBus

registers are disabled. Please refer to “SMBus configuration Registers” section for detail

information.

Pin is 3.3 V LVCMOS tolerant.

POWER

V_DD

3, 6, 7,

10, 13,

15, 46

Power

V_DD= 2.5 V ± 5%

Ground reference.

GND

DAP

RES

22, 24,

27, 30,

31, 34

PAD

Ground reference. The exposed pad at the center of the package must be connected to

ground plane of the board with at least 4 via to lower the ground impedance and improve

the thermal performance of the package.

Reserved – Do not connect

Note: I = Input O = Output, LVCMOS pins are 2.5 V levels only, only SMBus pins SDA, SDC and CS are 3.3V tolerant.

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MM, STD - JESD22-A115-A

CDM, STD - JESD22-C101-D

≥200 V

≥1250 V

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the Texas Instruments Sales Office/

Distributors for availability and specifications.

Thermal Resistance

ꢀθ_JA, No Airflow,

4 layer JEDEC, 9 thermal vias

For soldering specifications: see product folder at

www.national.com

27.6 °C/W

Supply Voltage (V_DD

2.5 I/O Voltage

)

-0.5V to +2.75V

(LVCMOS and Analog Input)

www.national.com/ms/MS/MS-SOLDERING.pdf

3.3 LVCMOS I/O Voltage

(SDA, SDC, CS)

-0.5V to +4.0V

Recommended Operating

Conditions

CML Input Voltage (IN_n+/-)

CML Output Voltage (OUT_n+/-)

Junction Temperature

Storage Temperature

-0.5V to +2.75V

+150°C

Min

Typ

Max Units

-65°C to +150°C

Supply Voltage

V_DDto GND

ESD Rating

2.375

-40

2.5 2.625

25 +85

HBM, STD - JESD22-A114F

≥7 kV

Ambient Temperature

°C

Electrical Characteristics

Over recommended operating supply and temperature ranges with default register settings unless other specified. (Note 2)

Symbol

POWER

Parameter

Conditions

Min

Typ

Max

Units

Power Supply Consumption

Device Output Enabled

(EN[3:0] = High),

220

275

VOD_SEL = open (1.0 Vp-p)

Device Output Disable

(EN[3:0] = Low)

PS_NT

Supply Noise Tolerance (Note 4) 50 Hz to 100 Hz

100 Hz to 10 MHz

mV_P-P

100

10 MHz to 5.0 GHz

2.5 LVCMOS DC SPECIFICATIONS

V_IH

V_IL

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

Low Level Output Voltage

Input Leakage Current

1.75

-0.3

2.0

V_DD

0.7

V_OH

V_OL

I_IN

I_OH= -3mA

I_OL= 3mA

V_IN= V_DD

V_IN= GND

0.4

+10

μA

-10

-50

I_IN-P

Input Leakage Current with

Internal Pull-Down/Up Resistors

V_IN= V_DD, with internal pull-down

resistors

+65

V_IN= GND, with internal pull-up

resistors

μA

SIGNAL DETECT

SDH

Signal Detect ON Threshold Level Default input signal level to assert

SD pin, 10.3125 Gbps

130

mV_p-p

SDL

Signal Detect OFF Threshold

Level

Default input signal level to de-

assert SD, 10.3125 Gbps

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Symbol

Parameter

Conditions

Min

Typ

Max

Units

CML RECEIVER INPUTS (IN_n+, IN_n-)

V_TX

Source Transmit Launch Signal

Level (IN diff)

AC-Coupled Requirement,

Differential measurement at point

A. Figure 1

mV_P-P

600

1600

R_LI

Differential Input Return Loss -

SDD11

100 MHz – 6 GHz, with fixture’s

effect de-embedded

-15

CML DRIVER OUTPUTS (OUT_n+, OUT_n-)

V_OD

Output Differential Voltage Level Differential measurement with

(Note 6), Figure 2

OUT+ and OUT- terminated by

50Ω to GND, AC-Coupled,

VOD_SEL = open (1.0 Vp-p),

DE_SEL = GND

mV_P-P

750

970

1150

Differential measurement with

OUT+ and OUT- terminated by

50Ω to GND, AC-Coupled,

VOD_SEL = V_DD(1.2 Vp-p),

DE_SEL = GND

mV_P-P

1140

V_{OD_DE}

De-Emphasis Levels

(Note 6, Note 7)

DE_SEL = 20kΩ to GND,

VOD_SEL = V_DD(1.2 Vp-p)

-3

-6

-9

DE_SEL = open,

VOD_SEL = V_DD(1.2 Vp-p)

DE_SEL = V_DD

VOD_SEL = V_DD(1.2 Vp-p)

t_R, t_F

Transition Time

20% to 80% of differential output

voltage, measured within 1” from

output pins. Figure 2

R_LO

Differential Output Return Loss - 100 MHz – 6 GHz, with fixture’s

SDD22

effect de-embedded. IN+ = static

high.

-15

t_PLHD

t_PHLD

t_CCSK

t_PPSK

Differential Low to High

Propagation Delay

Propagation delay measurement

at 50% crossing between input to

output, 100 Mbps. Figure 3

240

Differential High to Low

Propagation Delay

Inter Pair Channel to Channel

Skew

Difference in 50% crossing

between channels

Part to Part Output Skew

Difference in 50% crossing

between outputs

Random Jitter

V_TX= 1.0 Vp-p, BST_[2:0] = 000,

ps_rms

0.3

(Note 6, Note 8)

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Symbol

Parameter

Conditions

Min

Typ

Max

Units

EQUALIZATION

DJ1

Residual Deterministic Jitter

at 10.3125 Gbps

V_TX= 1.0 V_P-P

12 meter 30 AWG cable,

EQ = 03F'h (BST[2:0] = 111),

PRBS-7 (2⁷-1) pattern. (Note 5)

UI_P-P

0.10

0.22

DJ2

Residual Deterministic Jitter

at 6.0 Gbps

V_TX= 1.0 V_P-P,

12 meter 30 AWG cable,

EQ = 07F'h, PRBS-7 (2⁷-1)

pattern. (Note 5)

UI_P-P

0.07

0.12

SIGNAL DETECT and ENABLE TIMING

t_ZISD

Input OFF to ON detect — SD

Output High Response Time

Response time measurement at

V_INto SD output, V_IN= 800 mV_P-P

100 Mbps, 40” of 6 mil microstrip

FR4. Figure 4

400

150

t_IZSD

Input ON to OFF detect — SD

Output Low Response Time

t_OZOED

t_ZOED

EN High to Output ON Response Response time measurement at

Time

EN input to V_O, V_IN= 800 mV_P-P,

100 Mbps, 40” of 6 mil microstrip

FR4. Figure 5

EN Low to Output OFF Response

Time

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the

device should not be operated beyond such conditions.

Note 2: Typical values represent most likely parametric norms at V_DD= 2.5V, T_A= 25°C., and at the Recommended Operation Conditions at the time of product

characterization and are not guaranteed.

Note 3: Allowed supply noise (mV_P-Psine wave) under typical conditions.

Note 4: Specification is guaranteed by characterization at optimal boost setting and is not tested in production.

Note 5: Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point A of Figure 1).

Random jitter is removed through the use of averaging or similar means.

Note 6: Measured with clock-like {11111 00000} pattern.

Note 7: The de-emphasis level of −3 dB, −6 dB, −9 dB are for V_OD= 1.2 Vp-p. At lower V_ODlevel, the de-emphasis levels are reduced.

Note 8: Random jitter contributed by the equalizer is defined as sqrt (J_OUT²– J_IN²). J_OUTis the random jitter at equalizer outputs in ps-rms, see point C of Figure

1; J_INis the random jitter at the input of the equalizer in ps-rms, see point B of Figure 1.

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Electrical Characteristics — Serial Management Bus Interface

Over recommended operating supply and temperature ranges unless other specified. (Note 2)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

SERIAL BUS INTERFACE DC SPECIFICATIONS

V_IL

Data, Clock Input Low Voltage

Data, Clock Input High Voltage

0.8

V_IH

2.1

V_DD

I_PULLUP

Current Through Pull-Up Resistor High Power Specification

or Current Source

V_DD

Nominal Bus Voltage

2.375

-200

3.6

I_LEAK-Bus

I_LEAK-Pin

C_I

Input Leakage Per Bus Segment (Note 11)

Input Leakage Per Device Pin

+200

µA

-15

Capacitance for SDA and SDC

(Note 11, Note 12)

R_TERM

External Termination Resistance V_DD3.3

2000

1000

Ω

pull to V_DD= 2.5V ± 5% OR 3.3V ±

10%

(Note 11, Note 12)

V_DD2.5

(Note 11, Note 12)

SERIAL BUS INTERFACE TIMING SPECIFICATIONS – (See Figure 6)

F_SMB

T_BUF

Bus Operating Frequency

100

kHz

µs

Bus Free Time Between Stop and

Start Condition

4.7

T_HD:STA

Hold time after (Repeated) Start

Condition. After this period, the first

clock is generated.

At I_PULLUP, Max

4.0

4.7

µs

T_SU:STA

Repeated Start Condition Setup

Time

T_SU:STO

T_HD:DAT

T_SU:DAT

T_LOW

T_HIGH

t_F

Stop Condition Setup Time

Data Hold Time

4.0

300

250

4.7

µs

Data Setup Time

Clock Low Period

Clock High Period

Clock/Data Fall Time

Clock/Data Rise Time

4.0

300

t_R

1000

t_POR

Time in which a device must be

operational after power-on reset

500

Note 9: Recommended value. Parameter not tested in production.

Note 10: Recommended maximum capacitance load per bus segment is 400pF.

Note 11: Maximum termination voltage should be identical to the device supply voltage.

Note 12: Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1 SMBus common

AC specifications for details.

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AC Waveforms and Test Circuits

30122427

FIGURE 1. Test Setup Diagram

30122402

FIGURE 2. Output Transition Times

30122403

FIGURE 3. Propagation Delay Timing Diagram

30122404

FIGURE 4. Signal Detect (SD) Delay Timing Diagram

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30122405

FIGURE 5. Enable (EN) Delay Timing Diagram

30122418

FIGURE 6. SMBus Timing Parameters

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DATA CHANNELS

Functional Description

The DS100BR410 provides four data channels. Each data

channel consists of an equalizer stage, a limiting amplifier, a

DC offset correction block, and a CML driver as shown in

Figure 7.

DS100BR410 Functional Descriptions

The DS100BR410 is a Low Power Quad Channel Repeater

with Equalizer and De-Emphasis Driver optimized for opera-

tion up to 10.3125 Gbps for backplane and cable applications.

30122406

FIGURE 7. Simplified Block Diagram

EQUALIZER BOOST CONTROL

Inputs

SMBus

Each data channel support eight programmable levels of

equalization boost. The state of the PIN_MODE control input

determines how the boost settings are controlled. If

PIN_MODE is held High, then the equalizer boost setting is

controlled by the Boost Set pins (BST_[2:0]) in accordance

with Table 1. If this programming method is chosen, then the

boost setting selected on the Boost Set pins is applied to all

channels. When PIN_MODE is held Low, the equalizer boost

level is controlled through the SMBus. This programming

method is accessed via the appropriate SMBus registers (see

Table 4). Using this approach, equalizer boost settings can

be programmed for each channel individually. PIN_MODE is

internally pulled High, therefore if left open, the boost settings

are controlled by the Boost Set pins (BST_[2:0]). The eight

levels of boost settings enables the DS100BR410 to address

a wide range of media loss and data rates.

Result @ 5 GHz

BST_2 BST_1 BST_0 [8:0]

000101111

000111111

27.6 dB (default)

28.9 dB

SIGNAL DETECT

The DS100BR410 features a signal detect circuit on each

data channel. The status of the signal of each channel can be

determined by either reading the Signal Detect bit (SDn) in

the SMBus registers (see Table 4) or by the state of each SDn

pin. An output logic high indicates the presence of a signal

that has exceeded the ON threshold value (called SDH). An

output logic Low means that the input signal has fallen below

the OFF threshold value (called SDL). These values are pro-

grammed via the SMBus. If not programmed via the SMBus,

the thresholds take on the default values. The Signal Detect

threshold values can be changed through the SMBus. All

threshold values specified are DC peak-to-peak differential

signals (positive signal minus negative signal) at the input of

the device.

TABLE 1. Boost / EQ Pin Mode Configuration

Inputs

SMBus

Result @ 5 GHz

BST_2 BST_1 BST_0 [8:0]

OUTPUT LEVEL CONTROL

000000000

000000001

000000011

000000111

000001111

000011111

2.7 dB

The output amplitude of the CML drivers can be controlled via

the 4–level analog input VOD_SEL pin or via SMBus (see

Table 4). The default V_ODlevel is 1.0 Vp-p.

7.3 dB

12.2 dB

16.6 dB

20.6 dB

24.8 dB

TABLE 2. VOD_SEL Pin Configuration

VOD_SEL Pin

Tie High - V_DD

Open* (default)

20 kΩ resistor to GND

Tie to GND

Result

1.2 Vp-p

1.0 Vp-p

800 mVp-p

600 mVp-p

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OUTPUT DE-EMPHASIS CONTROL

SMBus Transactions

The output De-Emphasis may be controled via the 4–level

analog input DE_SEL pin or via SMBus (see Table 4).

The device supports WRITE, Burst WRITE, READ. and Burst

READ transactions. See Register Description table for regis-

ter address, type (Read/Write, Read Only), default value and

function information.

TABLE 3. DE_SEL Pin Configuration

DE_SEL Pin

Result

-9 dB

-6 dB

-3 dB

0 dB

Writing a Register

To write a register, the following protocol is used (see SMBus

2.0 specification).

Tie High - V_DD

Open* (default)

20 kΩ resistor to GND

Tie to GND

1. The Host (Master) selects the device by driving its

SMBus Chip Select (CS) signal High.

2. The Host drives a START condition, the 7-bit SMBus

address, and a “0” indicating a WRITE.

AUTOMATIC ENABLE FEATURE

3. The Device (Slave) drives the ACK bit (“0”).

4. The Host drives the 8-bit Register Address.

5. The Device drives an ACK bit (“0”).

6. The Host drive the 8-bit data byte.

7. The Device drives an ACK bit (“0”).

8. The Host drives a STOP condition.

It may be desirable to place unused channels in power-saving

Standby mode. This can be accomplished by connecting the

Signal detect (SDn) pin to the Enable (ENn) pin for each

channel (See Figure 7).

System Management Bus (SMBus)

and Configuration Registers

9. The Host de-selects the device by driving its SMBus CS

signal Low.

The System Management Bus interface is compatible to SM-

Bus 2.0 physical layer specification. The use of the Chip

Select signal is required. Holding the CS pin High enables

the SMBus port allowing access to the configuration registers.

Holding the CS pin Low disables the device's SMBus allowing

communication from the host to other slave devices on the

bus. In the STANDBY state, the System Management Bus

remains active. When communication to other devices on the

SMBus is active, the CS signal for the DS100BR410s must

be driven Low.

The WRITE transaction is completed, the bus goes IDLE and

communication with other SMBus devices may now occur.

Reading a Register

To read a register, the following protocol is used (see SMBus

2.0 specification).

1. The Host (Master) selects the device by driving its

SMBus Chip Select (CS) signal High.

2. The Host drives a START condition, the 7-bit SMBus

address, and a “0” indicating a WRITE.

The address byte for all DS100BR410s is AC'h. Based on the

SMBus 2.0 specification, the DS100BR410 has a 7-bit slave

address of 1010110'b. The LSB is set to 0'b (for a WRITE),

thus the 8-bit value is 1010 1100'b or AC'h.

3. The Device (Slave) drives the ACK bit (“0”).

4. The Host drives the 8-bit Register Address.

5. The Device drives an ACK bit (“0”).

6. The Host drives a START condition.

The SDA, SDC and CS pins are 3.3V tolerant, but are not 5V

tolerant. External pull-up resistor is required on the SDA. The

resistor value can be from 1 kΩ to 5 kΩ depending on the

voltage, loading and speed. The SDC and CS may also re-

quire an external pull-up resistor and it depends on the Host

that drives the bus.

7. The Host drives the 7-bit SMBus Address, and a “1”

indicating a READ.

8. The Device drives an ACK bit “0”.

9. The Device drives the 8-bit data value (register contents).

10. The Host drives a NACK bit “1”indicating end of the

READ transfer.

Transfer of Data via the SMBus

During normal operation the data on SDA must be stable dur-

ing the time when SDC is High.

11. The Host drives a STOP condition.

12. The Host de-selects the device by driving its SMBus CS

signal Low.

There are three unique states for the SMBus:

START: A High-to-Low transition on SDA while SDC is High

indicates a message START condition.

The READ transaction is completed, the bus goes IDLE and

communication with other SMBus devices may now occur.

STOP: A Low-to-High transition on SDA while SDC is High

indicates a message STOP condition.

Information on the Registers

The status registers 01'h to 03'h provide information of the

channel that is selected. The information provided are the

OOB_DIS, EN, EQ Boost, VOD and DEM bits of the selected

channel. By default, channel 0 is selected. In order to change

the selected channel, write to reg_07 bit[5:4]. Write a 1 to

reg_07 bit[0] is also needed to allow the registers 13'h to 1A'h

to control the channel EN and EQ boost bits of each of the

channels. Each channel can be individually enabled (EN) and

set to a desired boost level with these registers. Please refer

to Table 4 for additional information.

IDLE: If SDC and SDA are both High for a time exceeding

t_BUFfrom the last detected STOP condition or if they are High

for a total exceeding the maximum specification for t_HIGHthen

the bus will transfer to the IDLE state.

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TABLE 4. DS100BR410 Register Map

ADD

(hex)

Default

Type

REG Name

Bit(s)

Field

Description

(binary)

Device ID

7:4

Device ID

SD_CH3

0010

Device ID Value

1: Signal detected on CH3

0: No signal

SD_CH2

SD_CH1

SD_CH0

1: Signal detected on CH2

0: No signal

1: Signal detected on CH1

0: No signal

1: Signal detected on CH0

0: No signal

Status Register

for OOB_DIS,

EN and

Reserved

OOB_DIS

1: OOB Disabled

0: OOB Enabled

Boost_bit[8]

Reserved

1: Channel Enabled

0: Channel Disabled

3:1

Reserved

Boost_bit[8]

Boost_bit[7:0]

Boost_bit[8]

Status Register 7:0

for Boost_bit

[7:0]

Boost_bit[7:0]

Status Register 7:6

Reserved

for VOD[5:4] and

DEM[1:0]

5:4

VOD[5:4]

00 = 0.6 Vp-p

01 = 0.8 Vp-p

10 = 1.0 Vp-p

11 = 1.2 Vp-p

3:2

1:0

Reserved

DEM[1:0]

00 = 0 dB

01 = -3 dB

10 = -6 dB

11 = -9 dB

Reserved

7:0

7:6

5:4

3:2

1:0

Reserved

Signal Detect

Assert

Threshold

SD_ON_CH3

SD_ON_CH2

SD_ON_CH1

SD_ON_CH0

R/W

Signal Detect ON Threshold

00 = 130 mV

01 = 125 mV

10 = 150 mV

11 = 140 mV

Signal Detect

De-assert

Threshold

7:6

5:4

3:2

1:0

SD_OFF_CH3

SD_OFF_CH2

SD_OFF_CH1

SD_FF_CH0

R/W

Signal Detect OFF Threshold

00 = 60 mV

01 = 40 mV

10 = 105 mV

11 = 90 mV

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ADD

(hex)

Default

(binary)

REG Name

Bit(s)

Field

Type

Description

Port/Channel

Select and

Enable SMBus

Registers

7:6

5:4

Reserved

R/W

Port/Channel Select for

Status

Select port/channel [1:0] to report status

in REG_01 to REG_03

00 = port0 (CH0)

01 = port1 (CH1)

10 = port2 (CH2)

11 = port3 (CH3)

3:1

Reserved

R/W

000

SMBUS Channel EN and R/W

EQ boost

Channel EN and EQ Boost through pins

or smbus REG_13 to REG_1A

0 = Channel EN[3:0] and EQ BST[2:0]

boost set by external pins

1 = Allow channel EN and EQ boost to be

set by SMBus Register bits: REG_13 to

REG_1A

Driver V_OD

Control

Reserved

VOD Control

R/W

6:4

3:2

111

00 = 0.6 Vp-p

01 = 0.8 Vp-p

10 = 1.0 Vp-p

11 = 1.2 Vp-p

1:0

7:0

7:6

5:4

3:2

1:0

7:3

2:1

Reserved

DEM_CH3

DEM_CH2

DEM_CH1

DEM_CH0

Reserved

R/W

09 – 10 Reserved

00000000

De-Emphasis

Control

00 = 0 dB

01 = -3 dB

10 = -6 dB

11 = -9 dB

OOB Signal

Detect Control

00000

OOB Signal Detect Control R/W

0 = OOB signal detect enabled

1 = OOB signal detect disabled

Channel 3

EN and EQ

Control

7:5

Reserved

R/W

000

Channel Enable

0 = Disabled

1 = Enabled

3:1

Reserved

Boost[8]

R/W

000

See Table 5

EQ Control

Channel 3

7:0

Boost[7:0]

00000000 See Table 5

Channel 2

EN and EQ

Control

7:5

Reserved

R/W

000

Channel Enable

0 = Disabled

1 = Enabled

3:1

Reserved

Boost[8]

R/W

000

See Table 5

EQ Control

Channel 2

7:0

Boost[7:0]

00000000 See Table 5

Channel 1

EN and EQ

Control

7:5

Reserved

R/W

000

Channel Enable

0 = Disabled

1 = Enabled

3:1

Reserved

Boost[8]

R/W

000

See Table 5

EQ Control

Channel 1

7:0

Boost[7:0]

00000000 See Table 5

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ADD

(hex)

Default

(binary)

REG Name

Bit(s)

Field

Type

Description

Channel 0

EN and EQ

Control

7:5

Reserved

R/W

000

Channel Enable

0 = Disabled

1 = Enabled

3:1

Reserved

Boost[8]

R/W

000

See Table 5

EQ Control

Channel 0

7:0

Boost[7:0]

00000000 See Table 5

TABLE 5. Boost / EQ SMBus Register: 16 levels - recommended settings

Boost Register Bits Result

bit[8] bit[7] bit[6] bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] @ 5.5 GHz

000'h - 2.7 dB (BST_[2:0]=000)

001'h - 7.3 dB (BST_[2:0]=001)

002'h - 10.3 dB

003'h - 12.2 dB (BST_[2:0]=010)

007'h - 16.6 dB (BST_[2:0]=011)

015'h - 17 dB

00B'h - 19.2 dB

00F'h - 20.6 dB (BST_[2:0]=100)

055'h - 21.9 dB

01F'h - 24.8 dB (BST_[2:0]=101)

02F'h - 27.6 dB (BST_[2:0]=110)

03F'h - 28.9 dB (BST_[2:0]=111)

0AA'h - 31.3 dB

07F'h - 33.3 dB

0BF'h - 35.7 dB

0FF'h - 37 dB

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close to the signal via for a low inductance return current path

is recommended. When the via structure is associated with

stripline trace and a thick board, further optimization such as

back drilling is often used to reduce the high frequency effects

of via stubs on the signal path. To minimize cross-talk cou-

pling, it is recommended to have >3X gap spacing between

the differential pairs. For example, if the trace width is 5 mils

with 5 mils spacing – 100Ω differential impedance (closely

coupled). The gap spacing between the differential pairs

should be >15 mils.

Applications Information

GENERAL RECOMMENDATIONS

The DS100BR410 is a high performance circuit capable of

delivering excellent performance up to 10.3125 Gbps. Careful

attention must be paid to the details associated with high-

speed design as well as providing a clean power supply. Refer

to the LVDS Owner's Manual for more detailed information on

high speed design tips to address signal integrity design is-

sues.

POWER SUPPLY BYPASSING

UNUSED CHANNEL

Two approaches are recommended to ensure that the

DS100BR410 is provided with an adequate power supply.

First, the supply (VDD) and ground (GND) pins should be

connected to power planes routed on adjacent layers of the

printed circuit board. The layer thickness of the dielectric

should be minimized so that the V_DDand GND planes create

a low inductance supply with distributed capacitance. Sec-

ond, careful attention to supply bypassing through the proper

use of bypass capacitors is required. A 0.1uF or 0.01 μF by-

pass capacitor should be connected to each V_DDpin such that

the capacitor is placed as close as possible to the

DS100BR410. Smaller body size capacitors can help facili-

tate proper component placement. Additionally, three capac-

itors with capacitance in the range of 2.2 μF to 10 μF should

be incorporated in the power supply bypassing design as well.

These capacitors can be either tantalum or an ultra-low ESR

ceramic.

It is recommended to disable the unused channel (EN[3:0] =

LOW). The power consumption of the device is reduced when

the channel is disabled.

PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL

PAIRS

The high speed CML inputs and outputs must have a con-

trolled differential impedance of 100Ω. It is preferable to route

differential lines exclusively on one layer of the board, partic-

ularly for the input traces. The use of vias should be avoided

if possible. If vias must be used, they should be used sparingly

and must be placed symmetrically for each side of a given

differential pair. Route the differential signals away from other

signals and noise sources on the printed circuit board. See

AN-1187 for additional information on LLP packages.

Impedance discontinuities at the differential via can be mini-

mized or eliminated by increasing the swell around each via

hole. To further improve the signal quality, a ground via placed

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Typical Performance Curves Characteristics

30122428

FIGURE 8. Power Dissipation (PD) vs. Output Differential Voltage (VOD)

30122429

FIGURE 9. Output Differential Voltage (VOD = 1.0 Vp-p) vs. Supply Voltage (VDD)

30122430

FIGURE 10. Output Differential Voltage (VOD = 1.0 Vp-p) vs. Temperature

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Typical Performance Eye Diagrams Characteristics

30122431

FIGURE 11. Test Setup Connections Diagram

30122432

FIGURE 12. 12 meters, 30–AWG Cable at 10.3125 Gbps,

BST[2:0] = 111, DE_SEL = 0 dB

30122433

FIGURE 13. 40 inches, 6–mil FR4 Trace at 10.3125 Gbps,

BST[2:0] = 101, DE_SEL = 0 dB

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Physical Dimensions inches (millimeters) unless otherwise noted

48-pin LLP Package (7 mm x 7 mm x 0.8 mm, 0.5 mm pitch)

Package Number SQA48A

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Notes

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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

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DS100BR410SQ [TI]

相关型号：

DS100BR410SQ/NOPB

DS100BR410SQE

DS100BR410SQE/NOPB

DS100BR410SQX

DS100BR410SQX/NOPB

DS100D6S

DS100DF410

DS100DF410SQ

DS100DF410SQ/NOPB

DS100DF410SQE

DS100DF410SQE/NOPB

DS100KR401