DS10BR254 [TI]
1.5Gbps 1:4 LVDS 中继器;
| 型号： | DS10BR254 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.5Gbps 1:4 LVDS 中继器 中继器 |
| 文件： | 总19页 (文件大小：492K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS10BR254
www.ti.com
SNLS260D –DECEMBER 2007–REVISED APRIL 2013
DS10BR254 1.5 Gbps 1:4 LVDS Repeater
Check for Samples: DS10BR254
1
FEATURES
DESCRIPTION
The DS10BR254 is a 1.5 Gbps 1:4 LVDS repeater
optimized for high-speed signal routing and
distribution over FR-4 printed circuit board
backplanes and balanced cables. Fully differential
signal paths ensure exceptional signal integrity and
noise immunity.
2
•
DC - 1.5 Gbps Low Jitter, Low Skew, Low
Power Operation
•
Wide Input Common Mode Voltage Range
Allows for DC-Coupled Interface to LVDS, CML
and LVPECL Drivers
•
•
Redundant Inputs
The device has two different LVDS input channels
and a select pin determines which input is active. A
loss-of-signal (LOS) circuit monitors both input
channels and a unique LOS pin is asserted when no
signal is detected at that input.
LOS Circuitry Detects Open Inputs Fault
Condition
•
•
•
Integrated 100Ω Input and Output
Terminations
Wide input common mode range allows the switch to
accept signals with LVDS, CML and LVPECL levels;
the output levels are LVDS. A very small package
footprint requires a minimal space on the board while
the flow-through pinout allows easy board layout.
Each differential input and output is internally
terminated with a 100Ω resistor to lower device return
losses, reduce component count and further minimize
board space.
8 kV ESD on LVDS I/O Pins Protects Adjoining
Components
Small 6 mm x 6 mm WQFN-40 Space Saving
Package
APPLICATIONS
•
•
•
•
Clock Distribution
Clock and Data Buffering and Muxing
OC-12 / STM-4
SD/HD SDI Routers
Typical Application
CARD A
CARD C
ASIC/FPGA 1
ASIC/FPGA
ASIC/FPGA 2
DS10BR254
1:4 LVDS
Repeater
Discrete
Deserializer 1
Discrete
Serializer
Discrete
Deserializer 2
CARD B
BACKPLANE
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
DS10BR254
SNLS260D –DECEMBER 2007–REVISED APRIL 2013
www.ti.com
Block Diagram
SEL_in
PWDNn
4
OUT0+
OUT0-
IN1+
IN1-
OUT1+
OUT1-
IN2+
IN2-
OUT2+
OUT2-
OUT3+
OUT3-
PWDN
LOSn
Control and LOS
Circuitry
2
Connection Diagram
NC
NC
VDD
1
2
30
29
28
27
26
25
24
23
22
21
OUT0+
OUT0-
OUT1+
OUT1-
VDD
VDD
IN1+
IN1-
IN2+
IN2-
VDD
NC
3
4
DAP
5
6
(GND)
OUT2+
OUT2-
OUT3+
OUT3-
7
8
9
NC
10
Figure 1. DS10BR254 Pin Diagram
See Package Number RTA0040A
2
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Pin Name
SNLS260D –DECEMBER 2007–REVISED APRIL 2013
PIN DESCRIPTIONS
Pin
Number
I/O, Type
Pin Description
IN1+, IN1-,
IN2+, IN2-,
4, 5,
6, 7,
I, LVDS
Inverting and non-inverting high speed LVDS input pins.
Inverting and non-inverting high speed LVDS output pins.
OUT0+, OUT0-,
OUT1+, OUT1-,
OUT2+, OUT2-,
OUT3+, OUT3-
29, 28,
27, 26,
24, 23,
22, 21
O, LVDS
SEL_in
14
I, LVCMOS
O, LVCMOS
This pin selects which LVDS input is active.
LOS1,
LOS2
37,
36
Loss Of Signal output pins, LOSn report when an open input fault condition is
detected at the input, INn. These are open drain outputs. External pull up
resistors are required.
PWDN0,
PWDN1,
PWDN2,
PWDN3
35,
34
33,
32
I, LVCMOS
Channel output power down pin. When the PWDNn is set to L, the channel
output OUTn is in the power down mode.
PWDN
38
I, LVCMOS
Power
Device power down pin. When the PWDN is set to L, the device is in the
power down mode.
VDD
3, 8,
Power supply pins.
15,25, 30
GND
NC
16, DAP
Power
NC
Ground pin and a pad (DAP - die attach pad).
NO CONNECT pins. May be left floating.
1, 2
9, 10,
11, 12,
13, 17,
18, 19,
20, 31,
39, 40
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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SNLS260D –DECEMBER 2007–REVISED APRIL 2013
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Absolute Maximum Ratings(1)(2)
Supply Voltage
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to +4V
1V
LVCMOS Input Voltage
LVCMOS Output Voltage
LVDS Input Voltage
Differential Input Voltage |VID|
LVDS Output Voltage
−0.3V to (VCC + 0.3V)
0.0V to +1V
5 ms
LVDS Differential Output Voltage
LVDS Output Short Circuit Current Duration
Junction Temperature
+150°C
Storage Temperature Range
Lead Temperature Range Soldering (4 sec.)
−65°C to +150°C
+260°C
Maximum Package Power
Dissipation at 25°C
SQA Package
4.65W
Derate SQA Package
37.2 mW/°C above +25°C
+26.9°C/W
Package Thermal
Resistance
θJA
θJC
+3.8°C/W
ESD Susceptibility
HBM(3)
MM(4)
CDM(5)
≥8 kV
≥250V
≥1250V
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. JESD22-A114C
(4) Machine Model, applicable std. JESD22-A115-A
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions
Min
3.0
0
Typ
Max
3.6
1
Units
V
Supply Voltage (VCC
)
3.3
Receiver Differential Input Voltage (VID
)
V
Operating Free Air Temperature (TA)
−40
+25
+85
°C
4
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SNLS260D –DECEMBER 2007–REVISED APRIL 2013
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS
VIH
VIL
IIH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
2.0
VDD
0.8
V
V
GND
VIN = 3.6V
VCC = 3.6V
0
0
±10
μA
IIL
Low Level Input Current
VIN = GND
VCC = 3.6V
±10
μA
VCL
VOL
Input Clamp Voltage
ICL = −18 mA, VCC = 0V
−0.9
−1.5
V
V
Low Level Output Voltage
IOL= 4 mA
0.26
0.4
LVDS INPUT DC SPECIFICATIONS
VID
Input Differential Voltage
0
1
V
mV
mV
V
VTH
VTL
Differential Input High Threshold
Differential Input Low Threshold
Common Mode Voltage Range
VCM = +0.05V or VCC-0.05V
VID = 100 mV
0
0
+100
−100
VCMR
0.05
VCC -
0.05
VIN = +3.6V or 0V
VCC = 3.6V or 0V
±1
±10
μA
IIN
Input Current
CIN
RIN
Input Capacitance
Any LVDS Input Pin to GND
Between IN+ and IN-
1.7
pF
Input Termination Resistor
100
Ω
LVDS OUTPUT DC SPECIFICATIONS
VOD
Differential Output Voltage
250
-35
350
1.2
450
35
mV
mV
V
RL = 100Ω
RL = 100Ω
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
VOS
Offset Voltage
1.05
-35
1.375
35
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
mV
IOS
Output Short Circuit Current(4)
OUT to GND
-35
7
-55
55
mA
mA
pF
Ω
OUT to VCC
COUT
ROUT
Output Capacitance
Any LVDS Output Pin to GND
Between OUT+ and OUT-
1.2
100
Output Termination Resistor
SUPPLY CURRENT
ICC
Supply Current
Power Down Supply Current
PWDN = H
PWDN = L
113
50
135
60
mA
mA
ICCZ
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD
.
(3) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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SNLS260D –DECEMBER 2007–REVISED APRIL 2013
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AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVDS OUTPUT AC SPECIFICATIONS
tPLHD
tPHLD
Differential Propagation Delay Low to
440
400
650
650
ps
ps
High(1)
RL = 100Ω
Differential Propagation Delay High to
Low(1)
(1)(2)
tSKD1
tSKD2
tSKD3
tLHT
Pulse Skew |tPLHD − tPHLD
|
40
40
50
150
150
8
100
125
200
300
300
20
ps
ps
ps
ps
ps
μs
ns
ns
Channel to Channel Skew(1)(3)
Part to Part Skew(1)(4)
Rise Time(1)
RL = 100Ω
tHLT
Fall Time(1)
tON
Any PWDN to Output Active Time
Any PWDN to Output Inactive Time
Select Time
tOFF
tSEL
5
12
5
12
JITTER PERFORMANCE(1)
tRJ1
VID = 350 mV
VCM = 1.2V
Clock (RZ)
135 MHz
0.5
0.5
0.5
0.5
6
1
1
ps
ps
tRJ2
tRJ3
tRJ4
tDJ1
tDJ2
tDJ3
tDJ4
tTJ1
tTJ2
tTJ3
tTJ4
311 MHz
Random Jitter
(RMS Value)(5)
503 MHz
1
ps
750 MHz
1
ps
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
270 Mbps
622 Mbps
1.0625 Gbps
1.5 Gbps
22
ps
6
21
ps
Deterministic Jitter
(Peak to Peak Value)(6)
9
18
ps
9
17
ps
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
270 Mbps
622 Mbps
1.0625 Gbps
1.5 Gbps
0.01
0.01
0.01
0.01
0.03
0.03
0.04
0.06
UIP-P
UIP-P
UIP-P
UIP-P
Total Jitter(7)
(1) Specification is specified by characterization and is not tested in production.
(2) tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
(3) tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode
(any one input to all outputs).
(4) tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(5) Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
(6) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
(7) Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.
6
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SNLS260D –DECEMBER 2007–REVISED APRIL 2013
APPLICATION INFORMATION
DC TEST CIRCUITS
¼ DS10BR254
V
OH
OUT+
IN+
IN-
Power Supply
Power Supply
R
L
R
D
OUT-
V
OL
AC TEST CIRCUITS AND TIMING DIAGRAMS
¼ DS10BR254
OUT+
OUT-
IN+
Signal Generator
R
L
R
D
IN-
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SNLS260D –DECEMBER 2007–REVISED APRIL 2013
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FUNCTIONAL DESCRIPTION
The DS10BR254 is a 1.5 Gbps 1:4 LVDS repeater optimized for high-speed signal routing and distribution over
lossy FR-4 printed circuit board backplanes and balanced cables.
Table 1. Input Select Truth Table
CONTROL Pin (SEL_in) State
Input Selected
0
1
IN1
IN2
Input Interfacing
The DS10BR254 accepts differential signals and allows simple AC or DC coupling. With a wide common mode
range, the DS10BR254 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The
following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the
DS10BR254 inputs are internally terminated with a 100Ω resistor.
LVDS
Driver
DS10BR254
Receiver
100W Differential T-Line
OUT+
OUT-
IN+
100W
IN-
Figure 2. Typical LVDS Driver DC-Coupled Interface to an DS10BR254 Input
CML3.3V or CML2.5V
Driver
V
CC
DS10BR254
Receiver
50W
50W
100W Differential T-Line
OUT+
OUT-
IN+
IN-
100W
Figure 3. Typical CML Driver DC-Coupled Interface to an DS10BR254 Input
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SNLS260D –DECEMBER 2007–REVISED APRIL 2013
LVPECL
Driver
LVDS
Receiver
IN+
100W Differential T-Line
OUT+
100W
OUT-
IN-
150-250W
150-250W
Figure 4. Typical LVPECL Driver DC-Coupled Interface to an DS10BR254 Input
Output Interfacing
The DS10BR254 outputs signals compliant to the LVDS standard. Its outputs can be DC-coupled to most
common differential receivers. The following figure illustrates typical DC-coupled interface to common differential
receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a
common mode input range that can accomodate LVDS compliant signals, it is recommended to check respective
receiver's data sheet prior to implementing the suggested interface implementation.
DS10BR254
Driver
Differential
Receiver
100W Differential T-Line
OUT+
IN+
CML or
LVPECL or
LVDS
100W
100W
IN-
OUT-
Figure 5. Typical DS10BR254 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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SNLS260D –DECEMBER 2007–REVISED APRIL 2013
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Typical Performance
Figure 6. A 1.5 Gbps NRZ PRBS-7 After 2"
Figure 7. A 1.06 Gbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
Differential FR-4 Stripline
V:100 mV / DIV, H:100 ps / DIV
V:100 mV / DIV, H:200 ps / DIV
Figure 8. A 622 Mbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
Figure 9. A 270 Mbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:200 ps / DIV
V:100 mV / DIV, H:500 ps / DIV
120
V
CC
= 3.3V
T
= 25°C
A
110
100
All Outputs ON
NRZ PRBS-7
3 Outputs ON
2 Outputs ON
90
80
70
1 Output ON
3.2 4.0
60
0
0.8
1.6
2.4
DATA RATE (Gbps)
Figure 10. Supply Current as a Function of a Number of Outputs Used
10
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SNLS260D –DECEMBER 2007–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS10BR254TSQ/NOPB
DS10BR254TSQX/NOPB
ACTIVE
ACTIVE
WQFN
WQFN
RTA
RTA
40
40
250
RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
1BR254SQ
1BR254SQ
2500 RoHS & Green
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS10BR254TSQ/NOPB WQFN
DS10BR254TSQX/NOPB WQFN
RTA
RTA
40
40
250
178.0
330.0
16.4
16.4
6.3
6.3
6.3
6.3
1.5
1.5
12.0
12.0
16.0
16.0
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS10BR254TSQ/NOPB
DS10BR254TSQX/NOPB
WQFN
WQFN
RTA
RTA
40
40
250
208.0
356.0
191.0
356.0
35.0
35.0
2500
Pack Materials-Page 2
PACKAGE OUTLINE
RTA0040A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
6.1
5.9
0.5
0.3
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
0.08
0.05
0.00
(0.2) TYP
(0.1) TYP
4.6 0.1
EXPOSED
THERMAL PAD
20
11
36X 0.5
10
21
4X
4.5
SEE TERMINAL
DETAIL
1
30
0.3
40X
40
31
0.2
PIN 1 ID
(OPTIONAL)
0.5
0.3
0.1
C A B
40X
0.05
4214989/B 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RTA0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.6)
SYMM
40
31
40X (0.6)
40X (0.25)
1
30
36X (0.5)
SYMM
(5.8)
(0.74)
TYP
(
0.2) TYP
VIA
(1.31)
TYP
10
21
(R0.05) TYP
11
20
(0.74) TYP
(1.31 TYP)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214989/B 02/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RTA0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.48) TYP
9X ( 1.28)
40
31
40X (0.6)
1
30
40X (0.25)
36X (0.5)
(1.48)
TYP
SYMM
(5.8)
METAL
TYP
10
21
(R0.05) TYP
11
20
SYMM
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
70% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
4214989/B 02/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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