DS125MB203SQ/NOPB [TI]

12.5Gbps 双端口多路复用器和扇出缓冲器 | NJY | 54 | -40 to 85;


型号：	DS125MB203SQ/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	12.5Gbps 双端口多路复用器和扇出缓冲器 \| NJY \| 54 \| -40 to 85 信号电路复用器模拟IC
文件：	总48页 (文件大小：1331K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS125MB203

www.ti.com

SNLS432B –OCTOBER 2012–REVISED APRIL 2013

Low-Power 12.5-Gbps Dual-Lane 2:1/1:2 Mux/Buffer With Equalization and De-Emphasis

Check for Samples: DS125MB203

FEATURES

DESCRIPTION

The DS125MB203 is an extremely low-power high-

performance dual-port 2:1 mux and 1:2 switch/fanout

designed to support high-availability systems using

PCIe Gen-3/2/1, 10G-KR, and other high-speed

interface serial protocols up to 12.5 Gbps. The

integrated signal conditioning function eliminates the

need for external devices, reducing BOM cost and

board space. The receiver's continuous time linear

equalizer (CTLE) provides a boost of up to +30 dB at

6.25 GHz (12.5 Gbps) and is capable of opening an

input eye that is completely closed due to inter

symbol interference (ISI) induced by interconnect

medium such as 30in+ backplane traces or 8m+

•

Comprehensive Family, Proven System

Interoperability

–

DS125BR111: One-Lane Repeater

DS125BR210: Two-Channel Repeater

DS125BR401: Four-Lane Repeater

DS125BR800: Eight-Channel Repeater

DS125MB203: Two-Port, 2:1/1:2 Mux

DS125DF410: Four-Channel Retimer With

CDR

•

Low 65-mW/Channel (Typical) Power

Consumption, With Option to Power Down

Unused Channels

copper cables. The transmitter provides

a de-

emphasis boost of up to -12 dB and output voltage

amplitude control from 700 mV to 1300 mV.

•

Transparent Management of Link Training

Protocol for PCIe and 10G-KR

When operating in 10G-KR and PCIe Gen-3 mode,

the DS125MB203 transparently allows the host

controller and the end point to optimize the full link

and negotiate transmit equalizer coefficients. This

seamless management of the link training protocol

ensures system level interoperability with minimum

latency. With a low power consumption of 390 mW

(typ) total or 195 mW/port (bidirectional) and option to

turn off unused ports, the DS125MB203 enables

energy-efficient system design. A single supply of

3.3 V or 2.5 V is required to power the device.

Advanced Signal Conditioning Features

–

Receive Equalization up to 30dB at 6.25

GHz

–

Transmit De-emphasis up to -12dB

Transmit Output Voltage Control: 700 mV to

1300 mV

•

Programmable via Pin Selection, EEPROM, or

SMBus Interface

Single Supply Voltage: 2.5 V or 3.3 V

(selectable)

The programmable settings can be applied via pin

settings, SMBus (I2C) protocol or an external

EEPROM. When operating in the EEPROM mode,

the configuration information is automatically loaded

on power up. This eliminates the need for an external

microprocessor or software driver.

•

40°C to 85°C Operating Temperature Range

3-kV HBM ESD Rating

Flow-Thru Pinout in 10mmx5.5mm 54-Pin

Leadless QFN Package

SUPPORTED PROTOCOLS

•

SAS/SATA (up to 6 Gbps), Fibre Channel (up

to 10GFC)

•

PCIe Gen-3/2/1, 10G-KR, 10GbE, XAUI, RXAUI

sRIO, Infiniband, Interlaken, CPRI, OBSAI

Other proprietary interface up to 12.5 Gbps

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS125MB203

SNLS432B –OCTOBER 2012–REVISED APRIL 2013

www.ti.com

Typical Application

DS125MB203

SEL0

ASIC_2

S_INA0

TXA_0

ASIC_3

D_OUT0

S_INB0

ASIC_0

TXB_0

S_INA1

TXA_1

D_OUT1

TXB_1

S_OUTA0

S_OUTB0

ASIC_1

RXA_0

RXA_1

D_IN0

D_IN1

RXB_0

RXB_1

S_OUTA1

S_OUTB1

SEL1

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SNLS432B –OCTOBER 2012–REVISED APRIL 2013

Pin Diagram

SMBUS AND CONTROL

S_INA0+

S_INA0-

S_INB0+

S_INB0-

D_OUT0+

D_OUT0-

VDD

S_INA1+

S_INA1-

D_OUT1+

D_OUT1-

S_INB1+

TOP VIEW

DAP = GND

VDD

S_INB1-

D_IN0+

D_IN0-

VDD

S_OUTA0+

S_OUTA0-

S_OUTB0+

S_OUTB0-

S_OUTA1+

S_OUTA1-

S_OUTB1+

S_OUTB1-

VDD

D_IN1+

D_IN1-

LDO REG

3.3V to 2.5V

NOTE: Above 54-lead QFN graphic is a TOP VIEW, looking down through the package.

Figure 1. DS125MB203 Pin Diagram 54 Lead WQFN Package

See Package Number NJY0054A

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SNLS432B –OCTOBER 2012–REVISED APRIL 2013

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PIN DESCRIPTIONS⁽¹⁾

Pin Name

Pin Number

I/O, Type

Pin Description

Differential High Speed I/O's

D_IN0+, D_IN0-,

D_IN1+, D_IN1-

10, 11,

15, 16

Inverting and non-inverting CML differential inputs to the equalizer. On-

chip 50Ω termination resistor connects D_INn+ to VDD and D_INn- to

VDD.

AC coupling required on high-speed I/O

D_OUT0+, D_ OUT0-,

D_OUT1+, D_OUT1-

3, 4,

7, 8

Inverting and non-inverting 50Ω driver outputs with de-emphasis.

Compatible with AC coupled CML inputs.

AC coupling required on high-speed I/O

S_INA0+, S_INA0-,

S_INA1+, S_INA1-

45, 44,

40, 39

Inverting and non-inverting CML differential inputs to the equalizer. On-

chip 50Ω termination resistor connects S_INAn+ to VDD and S_INAn- to

VDD.

AC coupling required on high-speed I/O

S_OUTA0+, S_OUTA0-,

S_OUTA1+, S_OUTA1-

35, 34,

31, 30

Inverting and non-inverting 50Ω driver outputs with de-emphasis.

Compatible with AC coupled CML inputs.

AC coupling required on high-speed I/O

S_INB0+, S_INB0-,

S_INB1+, S_INB1-

43, 42,

38, 37

Inverting and non-inverting CML differential inputs to the equalizer. On-

chip 50Ω termination resistor connects S_INBn+ to VDD and S_INBn- to

VDD.

AC coupling required on high-speed I/O

S_OUTB0+, S_OUTB0-,

S_OUTB1+, S_OUTB1-

33, 32,

29, 28

Inverting and non-inverting 50Ω driver outputs with de-emphasis.

Compatible with AC coupled CML inputs.

AC coupling required on high-speed I/O

Control Pins - Shared (LVCMOS)

ENSMB 48

I, FLOAT,

LVCMOS

System Management Bus (SMBus) enable pin

Tie 1kΩ to VDD = Register Access SMBus Slave mode

FLOAT = Read External EEPROM (Master SMBUS Mode)

Tie 1kΩ to GND = Pin Mode

ENSMB = 1 (SMBUS SLAVE MODE), Float (SMBUS MASTER MODE)

SCL

I, LVCMOS,

O, OPEN

Drain

ENSMB Master or Slave mode

SMBUS clock input pin is enabled (slave mode)

SMBUS clock output when loading configuration from EEPROM (master

mode)

SDA

I, LVCMOS,

O, OPEN

Drain

ENSMB Master or Slave mode

The SMBus bidirectional SDA pin is enabled. Data input or open drain

(pull-down only) output.

AD0-AD3

54, 53, 47, 46

I, LVCMOS

ENSMB Master or Slave mode

SMBus Slave Address Inputs. In SMBus mode, these pins are the user

set SMBus slave address inputs.

READ_EN

I, LVCMOS

ENSMB = FLOAT (SMBUS master mode)

When using an External EEPROM, a transition from high to low starts

the load from the external EEPROM

ENSMB = 0 (PIN MODE)

EQ_D0, EQ_D1

EQ_S0, EQ_S1

20, 19

46, 47

I, 4-LEVEL,

LVCMOS

EQ_D[1:0] and EQ_S[1:0] control the level of equalization on the high

speed input pins. The pins are active only when ENSMB is deasserted

(low). The input are organized into two sides. The D side is controlled

with the EQ_D[1:0] pins and the S side is controlled with the EQ_S[1:0]

pins. When ENSMB goes high the SMBus registers provide independent

control of each channel. The EQ_S[1:0] pins are converted to SMBUS

AD2/ AD3 inputs. EQ_D[1:0] pins are not used.

See Table 2

(1) LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured. Input edge

rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%. Input edge rate for LVCMOS/FLOAT inputs must be faster

than 50 ns from 10–90%. For 3.3V mode operation, VIN pin = 3.3V and the "VDD" for the 4-level input is 3.3V. For 2.5V mode

operation, VDD pin = 2.5V and the "VDD" for the 4-level input is 2.5V.

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SNLS432B –OCTOBER 2012–REVISED APRIL 2013

PIN DESCRIPTIONS⁽¹⁾(continued)

Pin Name

Pin Number

49, 50

53, 54

I/O, Type

Pin Description

DEM_S0, DEM_S1

DEM_D0, DEM_D1

I, 4-LEVEL,

LVCMOS

DEM_D[1:0] and DEM_S[1:0] control the level of VOD and de-emphasis

on the high speed output. The pins are active only when ENSMB is

deasserted (low). The output are organized into two sides. The D side is

controlled with the DEM_D[1:0] pins and the S side is controlled with the

DEM_S[1:0] pins. When ENSMB goes high the SMBus registers provide

independent control of each channel. The DEM_D[1:0] and DEM_S[1:0]

pins are converted to SMBUS AD1/AD0 and SCL/SDA inputs.

See Table 3

Control Pins — Both Pin and SMBus Modes (LVCMOS)

MODE

I, 4-LEVEL,

LVCMOS

MODE control pin selects operating modes.

Tie 1kΩ to GND = GEN 1,2 and SAS 1,2

Float = Auto Mode Select (for PCIe)

Tie 20kΩ to GND = PCIe GEN-3 without De-emphasis

Tie 1kΩ to VDD = PCIe GEN-3 with De-emphasis

See Table 7

INPUT_EN

I, 4-LEVEL,

LVCMOS

0: Normal Operation, FANOUT is disabled, use SEL0/1 to select the A

or B input/output (see SEL0/1 pin), input always enabled with 50 ohms.

20kΩ to GND: Reserved

FLOAT: AUTO - Use RX Detect, SEL0/1 to determine which input or

output to enable, FANOUT is disable

1: Normal Operation, FANOUT is enabled (both S_OUT0/1 are ON).

Input always enabled with 50 ohms.

SEL0

SEL1

I, 4-LEVEL,

LVCMOS

Select pin for Lane 0.

0: selects input S_INB0+/-, output S_OUTB0+/-.

20kΩ to GND: selects input S_INB0+/-, output S_OUTA0+/-.

FLOAT: selects input S_INA0+/-, output S_OUTB0+/-.

1: selects input S_INA0+/-, output S_OUTA0+/-.

I, 4-LEVEL,

LVCMOS

Select pin for Lane 1.

0: selects input S_INB1+/-, output S_OUTB1+/-.

20kΩ to GND: selects input S_INB1+/-, output S_OUTA1+/-.

FLOAT: selects input S_INA1+/-, output S_OUTB1+/-.

1: selects input S_INA1+/-, output S_OUTA1+/-.

VDD_SEL

PWDN

I, FLOAT

Controls the internal regulator

FLOAT = 2.5V mode

Tied to GND: 3.3V mode

I, LVCMOS

0: Normal Operation (device is enabled).

1: Low Power Mode.

Output (LVCMOS)

ALL_DONE

0, LVCMOS

Valid Register Load Status Output

0: External EEPROM load passed

1: External EEPROM load failed

Power

VIN

Power

In 3.3V mode, feed 3.3V +/-10% to VIN

In 2.5V mode, leave floating.

VDD

GND

9, 14,36, 41, 51

Power supply pins CML/analog

2.5V mode, connect to 2.5V +/-5%

3.3V mode, connect 0.1 uF cap to each VDD pin

DAP

Power

Ground pad (DAP - die attach pad).

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings⁽¹⁾⁽²⁾

Supply Voltage (VDD - 2.5V mode)

Supply Voltage (VIN - 3.3V mode)

LVCMOS Input/Output Voltage

CML Input Voltage

-0.5V to +2.75V

-0.5V to +4.0V

-0.5V to (VDD+0.5)

-30 to +30 mA

125°C

CML Input Current

Junction Temperature

Storage Temperature

-40°C to +125°C

+260°C

Lead Temperature Range Soldering (4 sec.)

Derate NJY0054A Package

ESD Rating

52.6mW/°C above +25°C

3 kV

HBM, STD - JESD22-A114F

MM, STD - JESD22-A115-A

CDM, STD - JESD22-C101-D

θ_JC

150 V

1000 V

Thermal Resistance

11.5°C/W

θ_JA, No Airflow, 4 layer JEDEC

19.1°C/W

For soldering specifications: See application note SNOA549.

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or

other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating

Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute

Maximum Numbers are ensured for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating

Voltages only.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

Recommended Operating Conditions

Min

2.375

3.0

Typ

2.5

3.3

Max

2.625

3.6

Unit

Supply Voltage (2.5V mode)

Supply Voltage (3.3V mode)

Ambient Temperature

-40

+85

3.6

°C

SMBus (SDA, SCL)

Supply Noise up to 50 MHz⁽¹⁾

100

mVp-p

(1) Allowed supply noise (mVp-p sine wave) under typical conditions.

Electrical Characteristics

Parameter

Test Conditions

Min

Typ

Max

Unit

Power

IDD

Power Dissipation

VDD = 2.5 V supply

EQ Enabled,

VOD = 1.0 Vp-p,

PWDN = 0

390

515

500

685

VIN = 3.3 V supply

EQ Enabled,

VOD = 1.0 Vp-p,

PWDN = 0

LVCMOS / LVTTL DC Specifications

V_ih

V_il

High Level Input Voltage

Low Level Input Voltage

2.0

3.6

0.8

V_oh

High Level Output Voltage

(ALL_DONE pin)

I_oh= −4mA

2.0

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SNLS432B –OCTOBER 2012–REVISED APRIL 2013

Electrical Characteristics (continued)

Parameter

Test Conditions

Min

Typ

Max

Unit

V_ol

I_ih

Low Level Output Voltage

(ALL_DONE pin)

I_ol= 4mA

0.4

Input High Current (RESET pin)

VIN = 3.6 V,

LVCMOS = 3.6 V

-15

+15

Input High Current

with internal resistors

(4–level input pin)

+20

+150

I_il

Input Low Current (RESET pin)

VIN = 3.6 V,

LVCMOS = 0 V

-15

+15

-40

Input Low Current

with internal resistors

(4–level input pin)

-160

CML Receiver Inputs (IN_n+, IN_n-)

RL_rx-diff

RX Differential return loss

0.05 - 7.5 GHz

7.5 - 15 GHz

0.05 - 5 GHz

-15

-5

Ω

RL_rx-cm

Z_rx-dc

RX Common mode return loss

-10

RX DC common mode impedance Tested at VDD = 2.5 V

Z_rx-diff-dc

RX DC differntial mode

impedance

Tested at VDD = 2.5 V

100

120

Ω

V_rx-diff-dc

Differential RX peak to peak

voltage (VID)

Tested at pins

0.6

1.0

180

110

1.2

V_{rx-signal-det-diff-pp}Signal detect assert level for

active data signal

0101 pattern at 12.5 Gbps

mVp-p

V_{rx-idle-det-diff-pp}

Signal detect de-assert level for

electrical idle

High Speed Outputs

V_tx-diff-pp

Output Voltage Differential Swing Differential measurement with

OUT_n+ and OUT_n-,

0.8

1.0

1.2

Vp-p

terminated by 50Ω to GND,

AC-Coupled, VID = 1.0 Vp-p,

DEM_x[1:0] = R, F,

(1)

V_{tx-de-ratio_3.5}

V_{tx-de-ratio_6}

TX de-emphasis ratio

VOD = 1.0 Vp-p,

DEM_x[1:0] = R, F

-3.5

-6

VOD = 1.0 Vp-p,

DEM_x[1:0] = F, 0

T_TX-HF-DJ-DD

T_TX-RISE-FALL

TX Dj > 1.5 MHz

0.15

3.0

ps RMS

TX RMS jitter < 1.5 MHz

TX rise/fall time

20% to 80% of differential output

voltage

T_RF-MISMATCH

RL_TX-DIFF

TX rise/fall mismatch

20% to 80% of differential output

voltage

0.01

0.1

TX Differential return loss

0.05 - 7.5 GHz

7.5 - 15 GHz

0.05 - 5 GHz

-15

-5

RL_TX-CM

TX Common mode return loss

DC differential TX impedance

TX AC common mode voltage

-10

100

Z_TX-DIFF-DC

V_TX-CM-AC-PP

Ω

VOD = 1.0 Vp-p,

DEM_x[1:0] = R, F

100

mVpp

I_TX-SHORT

TX short circuit current limit

Total current the transmitter can

supply when shorted to VDD or

GND

V_TX-CM-DC-

ACTIVE-IDLE-DELTA

Absolute delta of DC common

mode voltage during L0 and

electrical idle

(1) In PCIe GEN3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The

output VOD level set by DEM_x[1:0] in GEN3 mode is dependent on the VID level and the frequency content. The DS125MB203

repeater in GEN3 mode is designed to be transparent, so the TX-FIR (de-emphasis) is passed to the RX to support the PCIe GEN3

handshake negotiation link training.

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Electrical Characteristics (continued)

Parameter

Test Conditions

Min

Typ

Max

Unit

V_{TX-CM-DC-LINE-}

DELTA

Absolute delta of DC common

mode voltgae between TX+ and

TX-

T_TX-IDLE-DATA

T_TX-DATA-IDLE

Max time to transition to

differential DATA signal after IDLE

VID = 1.0 Vp-p, 8 Gbps

3.5

6.2

Max time to transition to IDLE

after differential DATA signal

(2)

T_PLHD/PHLD

T_LSK

Differential Propagation Delay

Lane to lane skew

EQ = 00,

200

T = 25C, VDD = 2.5V

T_PPSK

Part to part propagation delay

skew

T_MUX-SWITCH

Equalization

DJE1

Mux/Switch Time

100

Residual deterministic jitter at 12

Gbps

30” 5mils FR4,

VID = 0.6 Vp-p,

PRBS15, EQ = 07'h,

DEM = 0 dB

0.18

DJE2

DJE3

DJE4

DJE5

Residual deterministic jitter at 8

Gbps

30” 5mils FR4,

VID = 0.6 Vp-p,

PRBS15, EQ = 07'h,

DEM = 0 dB

0.11

0.07

0.25

0.33

Residual deterministic jitter at 5

Gbps

30” 5mils FR4,

VID = 0.6 Vp-p,

PRBS15, EQ = 07'h,

DEM = 0 dB

Residual deterministic jitter at 12

Gbps

5 meters 30 awg cable,

VID = 0.6 Vp-p,

PRBS15,EQ = 07'h,

DEM = 0 dB

Residual deterministic jitter at 12

Gbps

8 meters 30 awg cable,

VID = 0.6 Vp-p,

PRBS15, EQ = 0F'h,

DEM = 0 dB

De-emphasis (MODE = 0)

DJD1 Residual deterministic jitter at 12

Gbps

Input Channel: 20” 5mils FR4,

Output Channel: 10” 5mils FR4,

VID = 0.6 Vp-p,

0.1

PRBS15, EQ = 03'h,

VOD = 1.0 Vp-p,

DEM = −3.5 dB

(2) Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the shortest propagation

delays.

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SNLS432B –OCTOBER 2012–REVISED APRIL 2013

Electrical Characteristics — Serial Management Bus Interface

Over recommended operating supply and temperature ranges unless other specified.

Parameter

Test Conditions

Min

Typ

Max

Unit

SERIAL BUS INTERFACE DC SPECIFICATIONS

V_IL

Data, Clock Input Low Voltage

Data, Clock Input High Voltage

0.8

3.6

V_IH

2.1

I_PULLUP

Current Through Pull-Up Resistor

or Current Source

High Power Specification

V_DD

Nominal Bus Voltage

2.375

-200

3.6

(1)

I_LEAK-Bus

I_LEAK-Pin

C_I

Input Leakage Per Bus Segment

Input Leakage Per Device Pin

Capacitance for SDA and SCL

+200

µA

-15

(1) (2)

R_TERM

External Termination Resistance

pull to V_DD= 2.5V ± 5% OR 3.3V ±

10%

Pullup V_DD= 3.3V,

2000

1000

Ω

(1) (2) (3)

Pullup V_DD= 2.5V,

(1) (2) (3)

SERIAL BUS INTERFACE TIMING SPECIFICATIONS

FSMB

Bus Operating Frequency

ENSMB = VDD (Slave Mode)

400

520

kHz

ENSMB = FLOAT (Master Mode)

280

1.3

400

TBUF

Bus Free Time Between Stop and

Start Condition

µs

THD:STA

Hold time after (Repeated) Start

Condition. After this period, the first

clock is generated.

At I_PULLUP, Max

0.6

TSU:STA

Repeated Start Condition Setup

Time

0.6

TSU:STO

THD:DAT

TSU:DAT

T_LOW

Stop Condition Setup Time

Data Hold Time

0.6

µs

Data Setup Time

100

1.3

0.6

Clock Low Period

(4)

T_HIGH

t_F

Clock High Period

Clock/Data Fall Time

Clock/Data Rise Time

300

(4)

t_R

(4) (5)

t_POR

Time in which a device must be

operational after power-on reset

500

(1) Recommended value.

(2) Recommended maximum capacitance load per bus segment is 400pF.

(3) Maximum termination voltage should be identical to the device supply voltage.

(4) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1

SMBus common AC specifications for details.

(5) Ensured by Design. Parameter not tested in production.

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TIMING DIAGRAMS

(OUT+)

80%

V_OD(p-p) = (OUT+) œ (OUT-)

20%

(OUT-)

RISE

FALL

Figure 2. CML Output and Rise and FALL Transition Time

PHLD

PLHD

OUT

Figure 3. Propagation Delay Timing Diagram

DATA

DATA-IDLE

DATA

IDLE-DATA

OUT

IDLE

Figure 4. Transmit IDLE-DATA and DATA-IDLE Response Time

LOW

HIGH

SCL

SDA

SU:STA

HD:STA

HD:DAT

BUF

SU:STO

SU:DAT

Figure 5. SMBus Timing Parameters

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SNLS432B –OCTOBER 2012–REVISED APRIL 2013

FUNCTIONAL DESCRIPTION

The DS125MB203 is a dual lane 2:1 multiplexer and 1:2 switch or fan-out buffer with signal conditioning. The

DS125MB203 compensates for lossy FR-4 printed circuit board backplanes and balanced cables. The

DS125MB203 operates in 3 modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and

SMBus Master Mode (ENSMB = float) to load register informations from external EEPROM; please refer to

SMBUS Master Mode for additional information.

Pin Control Mode:

When in pin mode (ENSMB = 0), equalization and de-emphasis can be selected via pin for each side

independently. When de-emphasis is asserted VOD is automatically adjusted per Table 3. For PCIe applications,

the RXDET pins provides automatic and manual control for input termination (50Ω or >50KΩ). MODE setting is

also pin controllable with pin selections (Gen 1/2, auto detect and PCIe Gen 3). The receiver electrical idle detect

threshold is also adjustable via the SD_TH pin.

SMBUS Mode:

When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination

disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode

case. Upon assertion of ENSMB, the EQx and DEMx functions revert to register control immediately. The EQx

and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins (MODE,

INPUT_EN, and SD_TH) remain active unless their respective registers are written to and the appropriate

override bit is set, in which case they are ignored until ENSMB is driven low (pin mode). On power-up and when

ENSMB is driven low all registers are reset to their default state. If PWDN is asserted while ENSMB is high, the

registers retain their current state.

Equalization settings accessible via the pin controls were chosen to meet the needs of most high speed

applications. If additional fine tuning or adjustment is needed, additional equalization settings can be accessed

via the SMBus registers. Each input has a total of 256 possible equalization settings. The tables show the 16

setting when the device is in pin mode. When using SMBus mode, the equalization, VOD and de- Emphasis

levels are set by registers.

The 4-level input pins utilize a resistor divider to help set the 4 valid levels and provide a wider range of control

settings when ENSMB=0. There is an internal 30K pull-up and a 60K pull-down connected to the package pin.

These resistors, together with the external resistor connection combine to achieve the desired voltage level.

Using the 1K pull-up, 1K pull-down, no connect, and 20K pull-down provide the optimal voltage levels for each of

the four input states.

Table 1. 4-Level Control Pin Settings

Level

Setting

3.3V Mode

0.10 V

2.5V Mode

0.08 V

Tie 1kΩ to GND

Tie 20kΩ to GND

Float (leave pin open)

Tie 1kΩ to V_INor V_DD

1/3 x V_IN

2/3 x V_IN

V_IN- 0.05 V

1/3 x V_DD

2/3 x V_DD

V_DD- 0.04 V

Float

Typical 4-Level Input Thresholds

•

Level 1 - 2 = 0.2 * V_INor V_DD

Level 2 - 3 = 0.5 * V_INor V_DD

Level 3 - 4 = 0.8 * V_INor V_DD

In order to minimize the startup current associated with the integrated 2.5V regulator the 1K pull-up / pull-down

resistors are recommended. If several 4 level inputs require the same setting, it is possible to combine two or

more 1K resistors into a single lower value resistor. As an example; combining two inputs with a single 500 Ohm

resistor is a good way to save board space.

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3.3V or 2.5V Supply Mode Operation

The DS125MB203 has an optional internal voltage regulator to provide the 2.5V supply to the device. In 3.3V

mode operation, the VIN pin = 3.3V is used to supply power to the device. The internal regulator will provide the

2.5V to the VDD pins of the device and a 0.1 uF cap is needed at each of the 5 VDD pins for power supply de-

coupling (total capacitance should be ≤0.5 uF), and the VDD pins should be left open. The VDD_SEL pin must

be tied to GND to enable the internal regulator. In 2.5V mode operation, the VIN pin should be left open and 2.5V

supply must be applied to the 5 VDD pins to power the device. The VDD_SEL pin must be left open (no connect)

to disable the internal regulator.

3.3V mode

2.5V mode

VDD_SEL

open

Enable

Disable

3.3V

Internal

voltage

regulator

Internal

Capacitors can be

either tantalum or an

ultra-low ESR seramic.

voltage

VIN

VDD

VIN

VDD

regulator

2.5V

0.1 uF

Capacitors can be

either tantalum or an

ultra-low ESR seramic.

0.1 uF

Place 0.1 uF close to VDD Pin

Place capcitors close to VDD Pin

Total capacitance should be 7 0.5 uF

Figure 6. 3.3V or 2.5V Supply Connection Diagram

PCIe Signal Integrity

When using the DS125MB203 in PCIe GEN-3 systems, there are specific signal integrity settings to ensure

signal integrity margin. The settings were achieved with completing extensive testing. Please contact your field

representative for more information regarding the testing completed to achieve these settings.

For tuning the in the downstream direction (from CPU to EP).

•

EQ: use the guidelines outlined in Table 2.

De-Emphasis: use the guidelines outlined in Table 3.

VOD: use the guidelines outlined in Table 3.

For tuning in the upstream direction (from EP to CPU).

•

EQ: use the guidelines outlined in Table 2.

De-Emphasis:

–

For trace lengths < 15in set to -3.5 dB

For trace lengths > 15in set to -6 dB

•

VOD: set to 900 mV

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Level

SNLS432B –OCTOBER 2012–REVISED APRIL 2013

Table 2. Equalizer Settings

EQ_D1

EQ_S1

EQ_D0

EQ_S0

dB at

EQ – 8 bits [7:0]

Suggested Use⁽¹⁾

1.5 GHz

2.5 GHz

4 GHz

6 GHz

0000 0000 = 0x00

0000 0001 = 0x01

0000 0010 = 0x02

0000 0011 = 0x03

0000 0111 = 0x07

0001 0101 = 0x15

0000 1011 = 0x0B

0000 1111 = 0x0F

0101 0101 = 0x55

0001 1111 = 0x1F

0010 1111 = 0x2F

0011 1111 = 0x3F

1010 1010 = 0xAA

0111 1111 = 0x7F

1011 1111 = 0xBF

1111 1111 = 0xFF

2.5

3.8

3.5

5.4

3.8

6.7

3.1

6.7

FR4 < 5 inch trace

FR4 5-10 inch trace

FR4 10 inch trace

Float

5.0

7.0

8.4

5.9

8.0

9.3

9.1

FR4 15-20 inch trace

FR4 20-30 inch trace

FR4 25-30 inch trace

8m, 30awg cable

7.4

10.3

10.2

12.4

13.8

12.6

16.2

18.3

19.8

20.5

22.2

24.4

25.8

12.8

13.9

15.3

16.7

17.5

20.3

22.8

24.2

26.4

27.8

30.2

31.6

13.7

16.2

15.9

17.0

20.7

21.8

23.6

24.7

28.0

29.2

30.9

31.9

6.9

Float

9.0

10.2

8.5

Float

11.7

13.2

14.4

16.0

17.6

18.7

Float

(1) Cable and FR4 lengths are for reference only. FR4 lengths based on a 100 Ohm differential stripline with 5-mil traces and 8-mil trace

separation. Optimal EQ setting should be determined via simulation and prototype verification.

Table 3. De-emphasis and Output Voltage Settings

DEM_D1

DEM_S1

DEM_D0

DEM_S0

Inner Amplitude

Vp-p

Level

VOD Vp-p

DEM dB⁽¹⁾

Suggested Use⁽²⁾

0.6

0.8

0.9

1.0

1.1

1.2

0.6

0.8

FR4 <5 inch 4–mil trace

FR4 10 inch 4–mil trace

FR4 <5 inch 4–mil trace

FR4 10 inch 4–mil trace

FR4 15 inch 4–mil trace

FR4 <5 inch 4–mil trace

FR4 10 inch 4–mil trace

FR4 15 inch 4–mil trace

FR4 <5 inch 4–mil trace

FR4 10 inch 4–mil trace

FR4 15 inch 4–mil trace

FR4 <5 inch 4–mil trace

FR4 10 inch 4–mil trace

FR4 15 inch 4–mil trace

FR4 20 inch 4–mil trace

Float

- 3.5

0.55

1.0

- 3.5

- 6

0.45

0.5

Float

1.0

- 3.5

- 6

0.7

Float

0.5

1.1

Float

- 3.5

- 6

0.7

0.55

1.2

- 3.5

- 6

- 9

0.8

Float

0.6

0.45

(1) The VOD output amplitude and DEM de-emphasis levels are set with the DEMD/S[1:0] pins.

The de-emphasis levels are also available in PCIe GEN-3 mode when MODE = 1 (tied to VDD).

(2) FR4 lengths are for reference only. FR4 lengths based on a 100 Ohm differential stripline with 5-mil traces and 8-mil trace separation.

Optimal DEM settings should be determined via simulation and prototype verification.

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Table 4. Input Termination Condition with PWDN, INPUT_EN and SEL0 / SEL1

Input Termination

S_INA0

Input Termination

S_INB0

Input Termination

PWDN

(PIN 52)

INPUT_E

N (PIN 22

SEL0

SEL1

MODE

D_IN0

D_IN1

S_INA1

S_INB1

Low Power

High Z

Manual Mux

Mode

50 Ω

Reserved

High Z

Reserved

Auto -

Pre Detect: Hi-Z

continuous poll,

DIN_B

Post Detect: 50 Ω

Auto -

continuous poll,

DIN_B

High Z

Pre Detect: Hi-Z

Post Detect: 50 Ω

Pre Detect: Hi-Z

Post Detect: 50 Ω

Auto -

Pre Detect: Hi-Z

High Z

50 Ω

Pre Detect: Hi-Z

Post Detect: 50 Ω

continuous poll, Post Detect: 50 Ω

DIN_A

Auto -

Pre Detect: Hi-Z

Post Detect: 50 Ω

continuous poll, Post Detect: 50 Ω

DIN_A

Manual Fanout

Mode

50 Ω

RX-Detect Polling in SAS/SATA (up to 6 Gbps) Applications

Unlike PCIe systems, SAS/SATA (up to 6 Gbps) systems use a low speed Out-Of-Band or OOB communications

sequence to detect and communicate between Controllers/Expanders and target drives. This communication

eliminates the need to detect for endpoints like PCIe. For non-PCIe systems, it is recommended to tie the

INPUT_EN pin high or low . This will ensure any OOB sequences sent from the SAS Controller/Expander will

reach the target drive without any additional latency due to the termination detection sequence defined by PCIe.

Table 5. Mux/Switch and Fanout Control

SEL0

(PIN 23)

SEL1

(PIN 26)

INPUT_EN

(PIN 22)

Description of Connection Path

D_OUT0 connects to S_INB0.

D_OUT1 connects to S_INB1.

D_IN0 connects to S_OUTB0. S_OUTA0 is in IDLE (output muted).

D_IN1 connects to S_OUTB1. S_OUTA1 is in IDLE (output muted).

Reserved

D_OUT0 connects to S_INB0.

D_OUT1 connects to S_INB1.

D_IN0 connects to S_OUTB0. S_OUTA0 is in IDLE (output muted).

D_IN1 connects to S_OUTB1. S_OUTA1 is in IDLE (output muted).

D_OUT0 connects to S_INB0.

D_OUT1 connects to S_INB1.

D_IN0 connects to S_OUTB0 and S_OUTA0.

D_IN1 connects to S_OUTB1 and S_OUTA1.

D_OUT0 connects to S_INB0.

D_OUT1 connects to S_INB1.

D_IN0 connects to S_OUTA0. S_OUTB0 is in IDLE (output muted).

D_IN1 connects to S_OUTA1. S_OUTB1 is in IDLE (output muted).

Reserved

D_OUT0 connects to S_INB0.

D_OUT1 connects to S_INB1.

D_IN0 connects to S_OUTA0. S_OUTB0 is in IDLE (output muted).

D_IN1 connects to S_OUTA1. S_OUTB1 is in IDLE (output muted).

D_OUT0 connects to S_INB0.

D_OUT1 connects to S_INB1.

D_IN0 connects to S_OUTB0 and S_OUTA0.

D_IN1 connects to S_OUTB1 and S_OUTA1.

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Table 5. Mux/Switch and Fanout Control (continued)

D_OUT0 connects to S_INA0.

D_OUT1 connects to S_INA1.

D_IN0 connects to S_OUTB0. S_OUTA0 is in IDLE (output muted).

D_IN1 connects to S_OUTB1. S_OUTA1 is in IDLE (output muted).

Reserved

D_OUT0 connects to S_INA0.

D_OUT1 connects to S_INA1.

D_IN0 connects to S_OUTB0. S_OUTA0 is in IDLE (output muted).

D_IN1 connects to S_OUTB1. S_OUTA1 is in IDLE (output muted).

D_OUT0 connects to S_INA0.

D_OUT1 connects to S_INA1.

D_IN0 connects to S_OUTB0 and S_OUTA0.

D_IN1 connects to S_OUTB1 and S_OUTA1.

D_OUT0 connects to S_INA0.

D_OUT1 connects to S_INA1.

D_IN0 connects to S_OUTA0. S_OUTB0 is in IDLE (output muted).

D_IN1 connects to S_OUTA1. S_OUTB1 is in IDLE (output muted).

Reserved

D_OUT0 connects to S_INA0.

D_OUT1 connects to S_INA1.

D_IN0 connects to S_OUTA0. S_OUTB0 is in IDLE (output muted).

D_IN1 connects to S_OUTA1. S_OUTB1 is in IDLE (output muted).

D_OUT0 connects to S_INA0.

D_OUT1 connects to S_INA1.

D_IN0 connects to S_OUTA0 and S_OUTB0.

D_IN1 connects to S_OUTA1 and S_OUTB1.

Table 6. Signal Detect Threshold Level⁽¹⁾

SMBus REG bit [3:2] and [1:0]

Assert Level (typ)

210 mVp-p

De-assert Level (typ)

150 mVp-p

100 mVp-p

110 mVp-p

130 mVp-p

160 mVp-p

00 (default)

180 mVp-p

190 mVp-p

(1) VDD = 2.5V, 25°C and 0101 pattern at 8 Gbps

Table 7. MODE Operation With Pin Control

MODE

(PIN 21)

SAS

SATA

CPRI

OBSAI

SRIO

(R)XAUI

Interlaken

Infiniband

Driver Characteristics

PCIe

10G-KR

10GbE

Limiting

F (default)

Transparent without DE

Automatic

Transparent with DE

Note: SAS/SATA limited to 6 Gbps. Automatic operation allows input to sense the incoming data-rate and utilize

a "Transparent" output driver for operation at or above 8 Gbps.

MODE operation with SMBus Registers

When in SMBus mode (Slave or Master), the MODE pin retains control of the output driver characteristics. In

order to override this control function, Register 0x08[2] must be written with a "1". Writting this bit enables MODE

control of each channel individually using the channel registers defined in Table 8.

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SMBUS Master Mode

The DS125MB203 devices support reading directly from an external EEPROM device by implementing SMBus

Master mode. When using the SMBus master mode, the DS125MB203 will read directly from specific location in

the external EEPROM. When designing a system for using the external EEPROM, the user needs to follow these

specific guidelines below. NOTE: SEL0, SEL1 and INPUT_EN control are to be set with the external strap

pins because there no EEPROM bits to configure them.

•

Set ENSMB = Float — enable the SMBUS master mode.

The external EEPROM device address byte must be 0xA0'h and capable of 400 kHz operation at 2.5V and

3.3V supply.

•

Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is B0'h.

When tying multiple DS125MB203 devices to the SDA and SCL bus, use these guidelines to configure the

devices.

•

Use SMBus AD[3:0] address bits so that each device can loaded it's configuration from the EEPROM.

Example below is for 4 device.

–

U1: AD[3:0] = 0000 = 0xB0'h,

U2: AD[3:0] = 0001 = 0xB2'h,

U3: AD[3:0] = 0010 = 0xB4'h,

U4: AD[3:0] = 0011 = 0xB6'h

•

Use a pull-up resistor on SDA and SCL; value = 2k ohms

Daisy-chain READEN# (pin 26) and ALL_DONE# (pin 27) from one device to the next device in the sequence

so that they do not compete for the EEPROM at the same time.

–

1. Tie READEN# of the 1st device in the chain (U1) to GND

2. Tie ALL_DONE# of U1 to READEN# of U2

3. Tie ALL_DONE# of U2 to READEN# of U3

4. Tie ALL_DONE# of U3 to READEN# of U4

5. Optional: Tie ALL_DONE# output of U4 to a LED to show the devices have been loaded successfully

Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS125MB203 device. The first 3

bytes of the EEPROM always contain a header common and necessary to control initialization of all devices

connected to the I2C bus. CRC enable flag to enable/disable CRC checking. If CRC checking is disabled, a fixed

pattern (8’hA5) is written/read instead of the CRC byte from the CRC location, to simplify the control. There is a

MAP bit to flag the presence of an address map that specifies the configuration data start in the EEPROM. If the

MAP bit is not present the configuration data start address is derived from the DS125MB203 address and the

configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the

EEPROM. There are 37 bytes of data size for each DS125MB203 device.

:2000000000001000000407002FAD4002FAD4002FAD4002FAD401805F5A8005F5A8005F5AD8

:200020008005F5A800005454000000000000000000000000000000000000000000000000F6

:20006000000000000000000000000000000000000000000000000000000000000000000080

:20008000000000000000000000000000000000000000000000000000000000000000000060

:2000A000000000000000000000000000000000000000000000000000000000000000000040

:2000C000000000000000000000000000000000000000000000000000000000000000000020

:2000E000000000000000000000000000000000000000000000000000000000000000000000

:200040000000000000000000000000000000000000000000000000000000000000000000A0

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Table 8. EEPROM Register Map With Default Value

EEPROM

Address

Byte HEX

Bit 7

CRC EN

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

BIt 0

Description

Address Map

Present

EEPROM > 256

Bytes

RES

Binary

Description

Binary

RES

Description

Max EEPROM

Burst size[7]

Max EEPROM

Burst size[6]

Max EEPROM

Burst size[5]

Max EEPROM

Burst size[4]

Max EEPROM

Burst size[3]

Max EEPROM

Burst size[2]

Max EEPROM

Burst size[1]

Max EEPROM

Burst size[0]

Binary

Description

Binary

PWDN_ch7

PWDN_ch6

PWDN_ch5

PWDN_ch4

PWDN_ch3

PWDN_ch2

PWDN_ch1

PWDN_ch0

Description

Binary

RES

Ovrd_RESET

RES

Description

Binary

RES

rxdet_btb_en

RES

Description

Binary

RES

Ovrd_RX_DET

Ovrd_MODE

RES

rx_delay_sel_2

rx_delay_sel_1

rx_delay_sel_0

Description

Binary

RD_delay_sel_3 RD_delay_sel_2 RD_delay_sel_1

RD_delay_sel_0 RES

RES

ch0_RXDET_1

ch0_RXDET_0

Description

Binary

ch0_BST_7

ch0_BST_6

ch0_BST_5

ch0_BST_4

ch0_BST_3

ch0_BST_2

ch0_BST_1

ch0_BST_0

Description

Binary

ch0_RES

ch0_RES_2

ch0_RES_1

ch0_RES_0

ch0_RES_2

ch0_RES_1

ch0_RES_0

Description 10

Binary

ch0_RES_2

ch0_RES_1

ch0_RES_0

ch0_Slow

ch0_RES_1

ch0_RES_0

ch0_RES_1

ch0_RES_0

Description 11

Binary

ch1_RES

ch1_RXDET_1

ch1_RXDET_0

ch1_BST_7

ch1_BST_6

ch1_BST_5

ch1_BST_4

Description 12

Binary

ch1_BST_3

ch1_BST_2

ch1_BST_1

ch1_BST_0

ch1_Sel_scp

ch1_Sel_MODE

ch1_RES_2

ch1_RES_1

Description 13

Binary

ch1_RES_0

ch1_VOD_2

ch1_VOD_1

ch1_VOD_0

ch1_DEM_2

ch1_DEM_1

ch1_DEM_0

ch1_Slow

Description 14

Binary

ch1_RES_1

ch1_RES_0

ch1_RES_1

ch1_RES_0

ch2_RES

ch2_RXDET_1

ch2_RXDET_0

Description 15

Binary

ch2_BST_7

ch2_BST_6

ch2_BST_5

ch2_BST_4

ch2_BST_3

ch2_BST_2

ch2_BST_1

ch2_BST_0

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Table 8. EEPROM Register Map With Default Value (continued)

EEPROM

Address

Byte HEX

Bit 7

ch2_RES

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

BIt 0

ch2_RES_0

Description 16

Binary

ch2_RES

ch2_RES_2

ch2_RES_1

ch2_RES_0

ch2_RES_2

ch2_RES_1

Description 17

Binary

ch2_RES_2

ch2_RES_1

ch2_RES_0

ch2_Slow

ch2_RES_1

ch2_RES_0

ch2_RES_1

ch2_RES_0

Description 18

Binary

ch3_RES

ch3_RXDET_1

ch3_RXDET_0

ch3_BST_7

ch3_BST_6

ch3_BST_5

ch3_BST_4

Description 19

Binary

ch3_BST_3

ch3_BST_2

ch3_BST_1

ch3_BST_0

ch3_Sel_scp

ch3_Sel_MODE

ch3_RES_2

ch3_RES_1

Description 20

Binary

ch3_RES_0

ch3_VOD_2

ch3_VOD_1

ch3_VOD_0

ch3_DEM_2

ch3_DEM_1

ch3_DEM_0

ch3_Slow

Description 21

Binary

ch3_RES_1

ch3_RES_0

ch3_RES_1

ch3_RES_0

ovrd_fast_idle

en_h_idle_th_n

en_h_idle_th_s

en_fast_idle_n

Description 22

Binary

en_fast_idle_s

eqsd_mgain_n

eqsd_mgain_s

ch4_RES

ch4_RXDET_1

ch4_RXDET_0

ch4_BST_7

Description 23

Binary

ch4_BST_6

ch4_BST_5

ch4_BST_4

ch4_BST_3

ch4_BST_2

ch4_BST_1

ch4_BST_0

ch4_Sel_scp

Description 24

Binary

ch4_Sel_MODE ch4_RES_2

ch4_RES_1

ch4_RES_0

ch4_VOD_2

ch4_VOD_1

ch4_VOD_0

ch4_DEM_2

Description 25

Binary

ch4_DEM_1

ch4_DEM_0

ch4_Slow

ch4_RES_1

ch4_RES_0

ch4_RES_1

ch4_RES_0

ch5_RES

Description 26

Binary

ch5_RES

Description 27

Binary

ch5_RES

ch5_Sel_scp

ch5_Sel_MODE

ch5_RES_2

ch5_RES_1

ch5_RES_0

Description 28

Binary

ch5_VOD_2

ch5_VOD_1

ch5_VOD_0

ch5_DEM_2

ch5_DEM_1

ch5_DEM_0

ch5_Slow

ch5_RES_1

Description 29

Binary

ch5_RES_0

ch5_RES_1

ch5_RES_0

ch6_RES

ch6_RXDET_1

ch6_RXDET_0

ch6_BST_7

Description 30

Binary

ch6_BST_6

ch6_BST_5

ch6_BST_4

ch6_BST_3

ch6_BST_2

ch6_BST_1

ch6_BST_0

ch6_Sel_scp

Description 31

Binary

ch6_Sel_MODE ch6_RES_2

ch6_RES_1

ch6_RES_0

ch6_VOD_2

ch6_VOD_1

ch6_VOD_0

ch6_DEM_2

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Table 8. EEPROM Register Map With Default Value (continued)

EEPROM

Address

Byte HEX

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

BIt 0

ch7_RES

Description 32

Binary

ch6_DEM_1

ch6_DEM_0

ch6_Slow

ch6_RES_1

ch6_RES_0

ch6_RES_1

ch6_RES_0

Description 33

Binary

ch7_RES

Description 34

Binary

ch7_RES

ch7_Sel_scp

ch7_Sel_MODE

ch7_RES_2

ch7_RES_1

ch7_RES_0

Description 35

Binary

ch7_VOD_2

ch7_VOD_1

ch7_VOD_0

ch7_DEM_2

ch7_DEM_1

ch7_DEM_0

ch7_Slow

ch7_RES_1

Description 36

Binary

ch7_RES_0

ch7_RES_1

ch7_RES_0

iph_dac_ns_1

iph_dac_ns_0

ipp_dac_ns_1

ipp_dac_ns_0

ipp_dac_1

Description 37

Binary

ipp_dac_0

RD23_67

RD01_45

RD_PD_ovrd

RD_Sel_test

RD_RESET_ovrd

PWDB_input_DC

DEM_VOD_ovrd

Description 38

Binary

DEM_ovrd_N2

DEM_ovrd_N1

DEM_ovrd_N0

VOD_ovrd_N2

VOD_ovrd_N1

VOD_ovrd_N0

SPARE0

SPARE1

Description 39

Binary

DEM__ovrd_S2 DEM__ovrd_S1 DEM_ovrd_S0

VOD_ovrd_S2

VOD_ovrd_S1

VOD_ovrd_S0

SPARE0

SPARE1

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Table 9. Example of EEPROM for Four Devices Using Two Address Maps

EEPROM Address

Address (Hex)

EEPROM Data

0x43

0x00

0x08

0x00

0x0B

0x00

0x0B

0x00

0x30

0x00

0x30

0x00

0x04

0x07

0x00

0xAB

0x00

0x0A

0xB0

0x00

0xAB

0x00

0x0A

0xB0

0x01

0x80

0x01

0x56

0x00

0x15

0x60

0x00

0x01

0x56

0x00

0x15

0x60

0x00

0x54

Comments

CRC_EN = 0, Address Map = 1, >256 bytes = 0, Device Count[3:0] = 3

EEPROM Burst Size

CRC not used

Device 0 Address Location

CRC not used

Device 1 Address Location

CRC not used

Device 2 Address Location

CRC not used

Device 3 Address Location

Begin Device 0, 1 - Address Offset 3

EQ CHB0 = 00

VOD CHB0 = 1.0V

DEM CHB0 = 0 (0dB)

EQ CHB1 = 00

VOD CHB1 = 1.0V

DEM CHB1 = 0 (0dB)

EQ CHB2 = 00

VOD CHB2 = 1.0V

DEM CHB2 = 0 (0dB)

EQ CHB3 = 00

VOD CHB3 = 1.0V

DEM CHB3 = 0 (0dB)

EQ CHA0 = 00

VOD CHA0 = 1.0V

DEM CHA0 = 0 (0dB)

EQ CHA1 = 00

VOD CHA1 = 1.0V

DEM CHA1 = 0 (0dB)

EQ CHA2 = 00

VOD CHA2 = 1.0V

DEM CHA2 = 0 (0dB)

EQ CHA3 = 00

VOD CHA3 = 1.0V

DEM CHA3 = 0 (0dB)

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Table 9. Example of EEPROM for Four Devices Using Two Address Maps (continued)

EEPROM Address

Address (Hex)

EEPROM Data

0x54

0x00

0x04

0x07

0x00

0xAB

0x00

0x0A

0xB0

0x00

0xAB

0x00

0x0A

0xB0

0x01

0x80

0x01

0x56

0x00

0x15

0x60

0x00

0x01

0x56

0x00

0x15

0x60

0x00

0x54

Comments

End Device 0, 1 - Address Offset 39

Begin Device 2, 3 - Address Offset 3

EQ CHB0 = 00

VOD CHB0 = 1.0V

DEM CHB0 = 0 (0dB)

EQ CHB1 = 00

VOD CHB1 = 1.0V

DEM CHB1 = 0 (0dB)

EQ CHB2 = 00

VOD CHB2 = 1.0V

DEM CHB2 = 0 (0dB)

EQ CHB3 = 00

VOD CHB3 = 1.0V

DEM CHB3 = 0 (0dB)

EQ CHA0 = 00

VOD CHA0 = 1.0V

DEM CHA0 = 0 (0dB)

EQ CHA1 = 00

VOD CHA1 = 1.0V

DEM CHA1 = 0 (0dB)

EQ CHA2 = 00

VOD CHA2 = 1.0V

DEM CHA2 = 0 (0dB)

EQ CHA3 = 00

VOD CHA3 = 1.0V

DEM CHA3 = 0 (0dB)

End Device 2, 3 - Address Offset 39

Note: CRC_EN = 0, Address Map = 1, >256 byte = 0, Device Count[3:0] = 3. This example has all channels set

to EQ = 00 (min boost), VOD = 1.0V, DEM = 0 (0dB) and multiple device can point to the same address map.

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System Management Bus (SMBus) and Configuration Registers

The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB = 1kΩ

to VDD to enable SMBus slave mode and allow access to the configuration registers.

The DS125MB203 has the AD[3:0] inputs in SMBus mode. These pins are the user set SMBUS slave address

inputs. The AD[3:0] pins have internal pull-down. When left floating or pulled low the AD[3:0] = 0000'b, the device

default address byte is B0'h. Based on the SMBus 2.0 specification, the DS125MB203 has a 7-bit slave address.

The LSB is set to 0'b (for a WRITE). The device supports up to 16 address byte, which can be set with the

AD[3:0] inputs. Below are the 16 addresses.

Table 10.

AD[3:0] Settings

0000

Address Bytes (HEX)

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

The SDA, SCL pins are 3.3V tolerant, but are not 5V tolerant. External pull-up resistor is required on the SDA.

The resistor value can be from 1 kΩ to 5 kΩ depending on the voltage, loading and speed. The SCL may also

require an external pull-up resistor and it depends on the Host that drives the bus.

TRANSFER OF DATA VIA THE SMBus

During normal operation the data on SDA must be stable during the time when SCL is High.

There are three unique states for the SMBus:

START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.

STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.

IDLE: If SCL and SDA are both High for a time exceeding t_BUFfrom the last detected STOP condition or if they

are High for a total exceeding the maximum specification for t_HIGHthen the bus will transfer to the IDLE state.

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SMBus TRANSACTIONS

The device supports WRITE and READ transactions. See Table 11 for register address, type (Read/Write, Read

Only), default value and function information.

WRITING A REGISTER

To write a register, the following protocol is used (see SMBus 2.0 specification).

1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.

2. The Device (Slave) drives the ACK bit (“0”).

3. The Host drives the 8-bit Register Address.

4. The Device drives an ACK bit (“0”).

5. The Host drive the 8-bit data byte.

6. The Device drives an ACK bit (“0”).

7. The Host drives a STOP condition.

The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may

now occur.

READING A REGISTER

To read a register, the following protocol is used (see SMBus 2.0 specification).

1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.

2. The Device (Slave) drives the ACK bit (“0”).

3. The Host drives the 8-bit Register Address.

4. The Device drives an ACK bit (“0”).

5. The Host drives a START condition.

6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.

7. The Device drives an ACK bit “0”.

8. The Device drives the 8-bit data value (register contents).

9. The Host drives a NACK bit “1”indicating end of the READ transfer.

10. The Host drives a STOP condition.

The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now

occur.

See Table 11 for more information.

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Table 11. SMBUS Slave Mode Register Map

Address

Bit(s)

Field

Reserved

Type Default

Description

0x00

Observation

R/W

0x00

Set bit to 0.

6:3

Address Bit

AD[3:0]

Observation of AD[3:0] bit

[6]: AD3

[5]: AD2

[4]: AD1

[3]: AD0

EEPROM Read

Done

1: Device completed the read from external EEPROM.

Reserved

PWDN CHx

R/W

Set bit to 0.

0x01

PWDN Channels

7:0

0x00

Power Down per Channel

[7]: CH7 (NC – S_OUTB1)

[6]: CH6 (D_IN1 – S_OUTA1)

[5]: CH5 (NC – S_OUTB0)

[4]: CH4 (D_IN0 – S_OUTA0)

[3]: CH3 (D_OUT1 – S_INB1)

[2]: CH2 (NC – S_INA1)

[1]: CH1 (D_OUT0 – S_INB0)

[0]: CH0 (NC – S_INA0)

00'h = all channels enabled

FF'h = all channels disabled; device in low power state

Note: override RESET pin in Reg_02.

0x02

Override

RESET Control

7:1

Reserved

R/W

0x00

Set bits to 0.

Override RESET

1: Block RESET pin control; use Reg_01 to configure.

0: Allow RESET pin control.

0x05

0x06

Slave Mode CRC

Bits

7:0

CRC bits

R/W

0x00

0x10

CRC bits [7:0]

Slave Register

Control

7:5

Reserved

Set bits to 0.

Set bit to 1.

Reserved

1: Enables high speed channel control via SMBus

registers without CRC

0: Channel control via SMBus registers requires correct

CRC in Reg 0x05

Note: In order to change VOD, DEM and EQ of the

channels in slave mode without also setting CRC each

time, set this bit to 1.

2:0

Reserved

Set bits to 0.

Set bit to 0.

0x07

0x08

Digital Reset and

Control

Reserved

R/W

0x01

0x00

Reset Registers

Self clearing reset for SMBus registers. Writing a [1] will

return register settings to default values

Reset SMBus

Master

Self clearing reset to SMBus master state machine

4:0

7:4

Reserved

Set bits to 0 0001'b.

Set bits to 0.

Override RXDET,

MODE

Reserved

Override RXDET

1: Block RXDET control; use register to configure.

0: Allow RXDET control.

Override MODE

1: Block MODE pin control; use register to configure.

0: Allow MODE pin control

1:0

Set bits to 0.

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Table 11. SMBUS Slave Mode Register Map (continued)

Address

Bit(s)

7:4

Field

Reserved

Type Default

R/W 0x00 Set bits to 0.

Description

0x0E

CH0 - S_INA0

RXDET

3:2

RXDET

00: Input is high-z impedance

01: Auto RX-Detect,

outputs test every 12 ms for 600 ms (50 times) then

stops; termination is high-z until detection; once

detected input termination is 50 Ω

10: Auto RX-Detect,

outputs test every 12 ms until detection occurs;

termination is high-z until detection; once detected

input termination is 50 Ω

11: Input is 50 Ω

Note: override RXDET control in Reg_08.

1:0

7:0

Reserved

Set bits to 0.

0x0F

CH0 - S_INA0

EQ Control

R/W

0x2F

EQ Control - total of 256 levels.

See Table 2.

0x10

0x11

0x12

0x15

Reserved

7:0

7:4

3:2

Reserved

RXDET

R/W

0xAD

0x02

0x00

CH1 - S_INB0

RXDET

Set bits to 0.

00: Input is high-z impedance

01: Auto RX-Detect,

outputs test every 12 ms for 600 ms (50 times) then

stops; termination is high-z until detection; once

detected input termination is 50 Ω

10: Auto RX-Detect,

outputs test every 12 ms until detection occurs;

termination is high-z until detection; once detected

input termination is 50 Ω

11: Input is 50 Ω

Note: override RXDET control in Reg_08.

1:0

7:0

Reserved

Set bits to 0.

0x16

0x17

CH1 - S_INB0

EQ Control

R/W

0x2F

EQ Control - total of 256 levels.

See Table 2.

CH1 - D_OUT0

VOD

Short Circuit

Protection

0xAD

1: Enable the short circuit protection

0: Disable the short circuit protection

MODE Control

1: PCIe GEN 1/2, 10GE

0: PCIe GEN-3, 10G-KR

Note: override the MODE pin in Reg_08.

5:3

2:0

Reserved

Set bits to default value - 101.

VOD Control

000: 0.6 V

001: 0.7 V

010: 0.8 V

011: 0.9 V

100: 1.0 V

101: 1.1 V (default)

110: 1.2 V

111: 1.3 V

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Table 11. SMBUS Slave Mode Register Map (continued)

Address

Bit(s)

Field

Type Default

Description

0x18

CH1 - D_OUT0

DEM

RXDET STATUS

0x02

Observation bit for RXDET CH1 - CHB1.

1: RX = detected

0: RX = not detected

6:5

4:3

2:0

MODE STATUS

Reserved

Observation bit for MODE.

Set bits to 0.

R/W

DEM Control

000: 0 dB

001: –1.5 dB

010: –3.5 dB (default)

011: –5 dB

100: –6 dB

101: –8 dB

110: –9 dB

111: –12 dB

0x19

0x1C

Reserved

7:0

7:4

3:2

Reserved

RXDET

R/W

0x00

Set bits to 0.

CH2 - S_INA1

RXDET

00: Input is high-z impedance

01: Auto RX-Detect,

outputs test every 12 ms for 600 ms (50 times) then

stops; termination is high-z until detection; once

detected input termination is 50 Ω

10: Auto RX-Detect,

outputs test every 12 ms until detection occurs;

termination is high-z until detection; once detected

input termination is 50 Ω

11: Input is 50 Ω

Note: override RXDET control in Reg_08.

1:0

7:0

Set bits to 0.

0x1D

CH2 - S_INA1

EQ Control

R/W

0x2F

EQ Control - total of 256 levels.

See Table 2.

0x1E

0x1F

0x20

0x23

Reserved

7:0

7:4

3:2

Reserved

RXDET

R/W

0xAD

0x02

0x00

CH3 - S_INB1

RXDET

Set bits to 0.

00: Input is high-z impedance

01: Auto RX-Detect,

outputs test every 12 ms for 600 ms (50 times) then

stops; termination is high-z until detection; once

detected input termination is 50 Ω

10: Auto RX-Detect,

outputs test every 12 ms until detection occurs;

termination is high-z until detection; once detected

input termination is 50 Ω

11: Input is 50 Ω

Note: override RXDET control in Reg_08.

1:0

7:0

Reserved

Set bits to 0.

0x24

CH3 - S_INB1

EQ Control

R/W

0x2F

EQ Control - total of 256 levels.

See Table 2.

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Table 11. SMBUS Slave Mode Register Map (continued)

Address

Bit(s)

Field

Type Default

R/W 0xAD

Description

0x25

CH3 - D_OUT1

VOD

Short Circuit

Protection

1: Enable the short circuit protection

0: Disable the short circuit protection

MODE Control

1: PCIe GEN 1/2, 10GE

0: PCIe GEN 3, 10G-KR

Note: override the MODE pin in Reg_08.

5:3

2:0

Reserved

Set bits to default value - 101.

VOD Control

000: 0.6 V

001: 0.7 V

010: 0.8 V

011: 0.9 V

100: 1.0 V

101: 1.1 V (default)

110: 1.2 V

111: 1.3 V

0x26

CH3 - D_OUT1

DEM

RXDET STATUS

0x02

Observation bit for RXDET CH1 - CHB1.

1: RX = detected

0: RX = not detected

6:5

4:3

2:0

MODE STATUS

Reserved

Observation bit for MODE.

Set bits to 0.

R/W

DEM Control

000: 0 dB

001: –1.5 dB

010: –3.5 dB (default)

011: –5 dB

100: –6 dB

101: –8 dB

110: –9 dB

111: –12 dB

0x27

0x2B

Reserved

7:0

7:4

3:2

Reserved

RXDET

R/W

0x00

Set bits to 0.

CH4 - D_IN0

RXDET

00: Input is high-z impedance

01: Auto RX-Detect,

outputs test every 12 ms for 600 ms (50 times) then

stops; termination is high-z until detection; once

detected input termination is 50 Ω

10: Auto RX-Detect,

outputs test every 12 ms until detection occurs;

termination is high-z until detection; once detected

input termination is 50 Ω

11: Input is 50 Ω

Note: override RXDET control in Reg_08.

1:0

7:0

Reserved

Set bits to 0.

0x2C

0x2D

CH4 - D_IN0

EQ Control

R/W

0x2F

EQ Control - total of 256 levels.

See Table 2.

CH4 - S_OUTA0

VOD

Short Circuit

Protection

0xAD

1: Enable the short circuit protection

0: Disable the short circuit protection

MODE Control

1: PCIe GEN 1/2, 10GE

0: PCIe GEN 3, 10G-KR

Note: override the MODE pin in Reg_08.

5:3

2:0

Reserved

Set bits to default value - 101.

VOD Control

000: 0.6 V

001: 0.7 V

010: 0.8 V

011: 0.9 V

100: 1.0 V

101: 1.1 V (default)

110: 1.2 V

111: 1.3 V

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Table 11. SMBUS Slave Mode Register Map (continued)

Address

Bit(s)

Field

Type Default

Description

0x2E

CH4 - S_OUTA0

DEM

RXDET STATUS

0x02

Observation bit for RXDET.

1: RX = detected

0: RX = not detected

6:5

4:3

2:0

MODE STATUS

Reserved

Observation bit for MODE.

Set bits to 0.

R/W

DEM Control

000: 0 dB

001: –1.5 dB

010: –3.5 dB (default)

011: –5 dB

100: –6 dB

101: –8 dB

110: –9 dB

111: –12 dB

0x2F

0x32

0x33

0x34

Reserved

7:0

Reserved

R/W

0x00

0x2F

0xAD

Set bits to 0.

CH5 - S_OUTB0

VOD

Short Circuit

Protection

1: Enable the short circuit protection

0: Disable the short circuit protection

MODE Control

1: PCIe GEN 1/2, 10GE

0: PCIe GEN 3, 10G-KR

Note: override the MODE pin in Reg_08.

5:3

2:0

Reserved

Set bits to default value - 101.

VOD Control

000: 0.6 V

001: 0.7 V

010: 0.8 V

011: 0.9 V

100: 1.0 V

101: 1.1 V (default)

110: 1.2 V

111: 1.3 V

0x35

CH5 - S_OUTB0

DEM

RXDET STATUS

0x02

Observation bit for RXDET.

1: RX = detected

0: RX = not detected

6:5

4:3

2:0

MODE STATUS

Reserved

Observation bit for MODE.

Set bits to 0.

R/W

DEM Control

000: 0 dB

001: –1.5 dB

010: –3.5 dB (default)

011: –5 dB

100: –6 dB

101: –8 dB

110: –9 dB

111: –12 dB

0x36

0x39

Reserved

7:0

7:4

3:2

Reserved

RXDET

R/W

0x00

Set bits to 0.

CH6 - D_IN1

RXDET

00: Input is high-z impedance

01: Auto RX-Detect,

outputs test every 12 ms for 600 ms (50 times) then

stops; termination is high-z until detection; once

detected input termination is 50 Ω

10: Auto RX-Detect,

outputs test every 12 ms until detection occurs;

termination is high-z until detection; once detected

input termination is 50 Ω

11: Input is 50 Ω

Note: override RXDET control in Reg_08.

1:0

Reserved

Set bits to 0.

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Table 11. SMBUS Slave Mode Register Map (continued)

Address

Bit(s)

Field

EQ Control

Type Default

Description

0x3A

CH6 - D_IN1

7:0

R/W

0x2F

EQ Control - total of 256 levels.

See Table 2.

0x3B

CH6 - S_OUTA1

VOD

Short Circuit

Protection

R/W

0xAD

1: Enable the short circuit protection

0: Disable the short circuit protection

MODE Control

1: PCIe GEN 1/2, 10GE

0: PCIe GEN 3, 10G-KR

Note: override the MODE pin in Reg_08.

5:3

2:0

Reserved

Set bits to default value - 101.

VOD Control

000: 0.6 V

001: 0.7 V

010: 0.8 V

011: 0.9 V

100: 1.0 V

101: 1.1 V (default)

110: 1.2 V

111: 1.3 V

0x3C

CH6 - S_OUTA1

DEM

RXDET STATUS

0x02

Observation bit for RXDET.

1: RX = detected

0: RX = not detected

6:5

4:3

2:0

MODE STATUS

Reserved

Observation bit for MODE.

Set bits to 0.

R/W

DEM Control

000: 0 dB

001: –1.5 dB

010: –3.5 dB (default)

011: –5 dB

100: –6 dB

101: –8 dB

110: –9 dB

111: –12 dB

0x3D

0x40

0x41

Reserved

7:0

Reserved

R/W

0x00

0x2F

Set bits to 0.

EQ Control - total of 256 levels.

See Table 2.

0x42

CH7 - S_OUTB1

VOD

Short Circuit

Protection

R/W

0xAD

1: Enable the short circuit protection

0: Disable the short circuit protection

MODE Control

1: PCIe GEN 1/2, 10GE

0: PCIe GEN 3, 10G-KR

Note: override the MODE pin in Reg_08.

5:3

2:0

Reserved

Set bits to default value - 101.

VOD Control

000: 0.6 V

001: 0.7 V

010: 0.8 V

011: 0.9 V

100: 1.0 V

101: 1.1 V (default)

110: 1.2 V

111: 1.3 V

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Table 11. SMBUS Slave Mode Register Map (continued)

Address

Bit(s)

Field

Type Default

Description

0x43

CH7 - S_OUTB1

DEM

RXDET STATUS

0x02

Observation bit for RXDET.

CH7 - CHA3.

1: RX = detected

0: RX = not detected

6:5

4:3

2:0

MODE STATUS

Reserved

Observation bit for MODE.

Set bits to 0.

R/W

DEM Control

000: 0 dB

001: –1.5 dB

010: –3.5 dB (default)

011: –5 dB

100: –6 dB

101: –8 dB

110: –9 dB

111: –12 dB

0x44

0x51

Reserved

Device ID

7:4

7:5

4:0

7:3

Reserved

VERSION

R/W

0x00

0x46

Set bits to 0.

010'b

00110'b

0x5E

Override SEL1,

SEL0 and

INPUT_EN

Reserved

Override SEL1 pin

R/W

0x00

Set bits to 0.

1: Block SEL1 pin control;

use Reg_5F to configure.

0: Allow SEL1 pin control

Override SEL0 pin

1: Block SEL0 pin control;

use Reg_5F to configure.

0: Allow SEL0 pin control

Override INPUT_EN

1: Block INPUT_EN pin control;

use Reg_5F to configure.

0: Allow INPUT_EN pin control

0x5F

Control SEL1, SEL0 7:6

and INPUT_ENl

SEL1 Control

R/W

0x00

Select for Lane 1.

00: 0 - selects input S_INB1+/-,

output S_OUTB1+/-.

01: 20kΩ to GND - selects input S_INB1+/-,

output S_OUTA1+/-

10: FLOAT - selects input S_INA1+/-,

output S_OUTB1+/-

11: 1 - selects input S_INA1+/-,

output S_OUTA1+/-.

5:4

SEL0 Control

Select for Lane 0.

00: 0 - selects input S_INB0+/-,

output S_OUTB0+/-.

01: 20kΩ to GND - selects input S_INB0+/-,

output S_OUTA0+/-

10: FLOAT - selects input S_INA0+/-,

output S_OUTB0+/-

11: 1 - selects input S_INA0+/-,

output S_OUTA0+/-.

3:2

INPUT_EN Control

00: 0 - Normal Operation, FANOUT is disabled, use

SEL0/1 to select the A or B input/output (see SEL0/1

pin), input always enabled with 50 ohms.

01: 20kΩ to GND - Reserved.

10: FLOAT - AUTO - Use RX Detect, SEL0/1 to

determine which input or output to enable, FANOUT is

disable.

11: 1 - Normal Operation, FANOUT is enabled (both

S_OUT0/1 are ON). Input always enabled with 50

ohms.

1:0

Reserved

Set bits to 0.

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SNLS432B –OCTOBER 2012–REVISED APRIL 2013

APPLICATIONS INFORMATION

GENERAL RECOMMENDATIONS

The DS125MB203 is a high performance circuit capable of delivering excellent performance. Careful attention

must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer

to the information below and Revision 4 of the LVDS Owner's Manual for more detailed information on high

speed design tips to address signal integrity design issues.

PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS

The CML inputs and LPDS outputs have been optimized to work with interconnects using a controlled differential

impedance of 85 - 100Ω. It is preferable to route differential lines exclusively on one layer of the board,

particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should

be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever

differential vias are used the layout must also provide for a low inductance path for the return currents as well.

Route the differential signals away from other signals and noise sources on the printed circuit board. See AN-

1187(SNOA401) for additional information on QFN (WQFN) packages.

20 mils

EXTERNAL MICROSTRIP

100 mils

20 mils

INTERNAL STRIPLINE

VDD

14 13

BOTTOM OF PKG

GND

VDD

36 37

39 40 41 42

30 31

33 34

VDD

Figure 7. Typical Routing Options

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The graphic shown above depicts different transmission line topologies which can be used in various

combinations to achieve the optimal system performance. Impedance discontinuities at the differential via can be

minimized or eliminated by increasing the swell around each hole and providing for a low inductance return

current path. When the via structure is associated with thick backplane PCB, further optimization such as back

drilling is often used to reduce the deterimential high frequency effects of stubs on the signal path.

POWER SUPPLY BYPASSING

Two approaches are recommended to ensure that the DS125MB203 is provided with an adequate power supply.

First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers

of the printed circuit board. The layer thickness of the dielectric should be minimized so that the V_DDand GND

planes create a low inductance supply with distributed capacitance. Second, careful attention to supply

bypassing through the proper use of bypass capacitors is required. A 0.1 μF bypass capacitor should be

connected to each V_DDpin such that the capacitor is placed as close as possible to the DS125MB203. Smaller

body size capacitors can help facilitate proper component placement. Additionally, capacitor with capacitance in

the range of 1 μF to 10 μF should be incorporated in the power supply bypassing design as well. These

capacitors can be either tantalum or an ultra-low ESR ceramic.

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Typical Performance Curves Characteristics

1021

1019

1016

1013

1010

1007

1020

1018

1016

1014

1012

T = 25°C

= 2.5 V

-40

-15

2.375

2.5

2.625

TEMPERATURE (°C)

VDD (V)

Figure 8. Output Differential Voltage (VOD = 1.0 Vp-p) vs.

Supply Voltage (VDD)

Figure 9. Output Differential Voltage (VOD = 1.0 Vp-p) vs.

Temperature

Typical Performance Eye Diagrams Characteristics

Pattern

Generator

Scope

BW = 60 GHz

OUT

DS125MB203

= 1.0 Vp-p,

Lossy Channel

DE = 0 dB

PRBS15

Figure 10. Test Setup Connections Diagram

Figure 11. TL = 10 inch 5–mil FR4 trace, 5 Gbps

DS125MB203 settings: EQ[1:0] = 0, F = 02'h, DEM[1:0] = 0, 1

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Typical Performance Eye Diagrams Characteristics (continued)

Figure 12. TL = 10 inch 5–mil FR4 trace, 8 Gbps

DS125MB203 settings: EQ[1:0] = 0, F = 02'h, DEM[1:0] = 0, 1

Figure 13. TL = 10 inch 5–mil FR4 trace, 12 Gbps

DS125MB203 settings: EQ[1:0] = 0, R = 01'h, DEM[1:0] = 0, 1

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Typical Performance Eye Diagrams Characteristics (continued)

Figure 14. TL = 20 inch 5–mil FR4 trace, 5 Gbps

DS125MB203 settings: EQ[1:0] = 0, 1 = 03'h, DEM[1:0] = 0, 1

Figure 15. TL = 20 inch 5–mil FR4 trace, 8 Gbps

DS125MB203 settings: EQ[1:0] = 0, 1 = 03'h, DEM[1:0] = 0, 1

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Typical Performance Eye Diagrams Characteristics (continued)

Figure 16. TL = 20 inch 5–mil FR4 trace, 12 Gbps

DS125MB203 settings: EQ[1:0] = 0, 1 = 03'h, DEM[1:0] = 0, 1

Figure 17. TL = 30 inch 5–mil FR4 trace, 5 Gbps

DS125MB203 settings: EQ[1:0] = R, 0 = 07'h, DEM[1:0] = 0, 1

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Typical Performance Eye Diagrams Characteristics (continued)

Figure 18. TL = 30 inch 5–mil FR4 trace, 8 Gbps

DS125MB203 settings: EQ[1:0] = R, 0 = 07'h, DEM[1:0] = 0, 1

Figure 19. TL = 30 inch 5–mil FR4 trace, 12 Gbps

DS125MB203 settings: EQ[1:0] = R, 0 = 07'h, DEM[1:0] = 0, 1

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Typical Performance Eye Diagrams Characteristics (continued)

Figure 20. TL1 = 5-meter 30-AWG 100 Ohm Twin-axial Cable, 12 Gbps

DS125MB203 settings: EQ[1:0] = R, 0 = 07'h, DEM[1:0] = 0, 1

Figure 21. TL1 = 8-meter 30-AWG 100 Ohm Twin-axial Cable, 12 Gbps

DS125MB203 settings: EQ[1:0] = R, 1 = 0F'h, DEM[1:0] = 0, 1

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Typical Performance Eye Diagrams Characteristics (continued)

Pattern

Generator

Scope

BW = 60 GHz

TL1

Lossy Channel

TL2

Lossy Channel

OUT

DS125MB203

= 1.0 Vp-p,

DE = 0 dB

PRBS15

Figure 22. Test Setup Connections Diagram

Figure 23. TL1 = 20 inch 5–mil FR4 trace, TL2 = 10 inch 5–mil FR4 trace, 5 Gbps

DS125MB203 settings: EQ[1:0] = 0, 1 = 03'h, DEM[1:0] = R, 0

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Typical Performance Eye Diagrams Characteristics (continued)

Figure 24. TL1 = 20 inch 5–mil FR4 trace, TL2 = 10 inch 5–mil FR4 trace, 8 Gbps

DS125MB203 settings: EQ[1:0] = R, 1 = 03'h, DEM[1:0] = R, 0

Figure 25. TL1 = 20 inch 5–mil FR4 trace, TL2 = 10 inch 5-mil FR4 trace, 12 Gbps

DS125MB203 settings: EQ[1:0] = R, 1 = 03'h, DEM[1:0] = R, 0

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SNLS432B –OCTOBER 2012–REVISED APRIL 2013

REVISION HISTORY

Changes from Revision A (April 2013) to Revision B

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 40

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PACKAGE OPTION ADDENDUM

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16-Apr-2013

PACKAGING INFORMATION

Orderable Device

DS125MB203SQ/NOPB

DS125MB203SQE/NOPB

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

ACTIVE

WQFN

NJY

2000

Green (RoHS

& no Sb/Br)

CU SN

Level-2-260C-1 YEAR

DS125MB203

ACTIVE

NJY

250

Green (RoHS

& no Sb/Br)

Level-2-260C-1 YEAR

DS125MB203

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Apr-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DS125MB203SQ/NOPB WQFN

DS125MB203SQE/NOPB WQFN

NJY

2000

250

330.0

178.0

16.4

5.8

10.3

1.0

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Apr-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DS125MB203SQ/NOPB

DS125MB203SQE/NOPB

WQFN

NJY

2000

250

367.0

213.0

367.0

191.0

38.0

55.0

Pack Materials-Page 2

PACKAGE OUTLINE

NJY0054A

WQFN

SCALE 2.000

WQFN

5.6

5.4

PIN 1 INDEX AREA

0.5

0.3

0.2

10.1

9.9

DETAIL

OPTIONAL TERMINAL

TYPICAL

0.8 MAX

SEATING PLANE

2X 4

3.51±0.1

(0.1)

SEE TERMINAL

DETAIL

50X 0.5

7.5±0.1

8.5

0.3

54X

0.2

PIN 1 ID

(OPTIONAL)

0.5

0.3

54X

0.1

C A

0.05

4214993/A 07/2013

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

NJY0054A

WQFN

(3.51)

SYMM

54X (0.6)

54X (0.25)

SEE DETAILS

50X (0.5)

(7.5)

(9.8)

SYMM

(1.17)

TYP

(1.16)

(

0.2) TYP

VIA

(1) TYP

(5.3)

LAND PATTERN EXAMPLE

SCALE:8X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214993/A 07/2013

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note

in literature No. SLUA271 (www.ti.com/lit/slua271).

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EXAMPLE STENCIL DESIGN

NJY0054A

WQFN

SYMM

METAL

TYP

(0.855) TYP

54X (0.6)

54X (0.25)

50X (0.5)

(1.17)

TYP

SYMM

(9.8)

12X (0.97)

12X (1.51)

(5.3)

SOLDERPASTE EXAMPLE

BASED ON 0.125mm THICK STENCIL

EXPOSED PAD

67% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

4214993/A 07/2013

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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DS125MB203SQ/NOPB [TI]

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