DS15MB200 [TI]

具有预加重功能的双路 1.5Gbps 2:1/1:2 LVDS 多路复用器/缓冲器;


型号：	DS15MB200
厂家：	TEXAS INSTRUMENTS
描述：	具有预加重功能的双路 1.5Gbps 2:1/1:2 LVDS 多路复用器/缓冲器复用器
文件：	总18页 (文件大小：437K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS15MB200

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SNLS196E –NOVEMBER 2005–REVISED MARCH 2013

DS15MB200 Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis

Check for Samples: DS15MB200

FEATURES

DESCRIPTION

The DS15MB200 is a dual-port 2 to 1 multiplexer and

1 to 2 repeater/buffer. High-speed data paths and

flow-through pinout minimize internal device jitter and

simplify board layout, while pre-emphasis overcomes

ISI jitter effects from lossy backplanes and cables.

The differential inputs and outputs interface to LVDS

or Bus LVDS signals such as those on Texas

Instrument's 10-, 16-, and 18-bit Bus LVDS SerDes,

or to CML or LVPECL signals.

•

1.5 Gbps Data Rate Per Channel

Configurable Off/On Pre-emphasis Drives

Lossy Backplanes and Cables

•

LVDS/BLVDS/CML/LVPECL Compatible Inputs,

LVDS Compatible Outputs

•

Low Output Skew and Jitter

On-chip 100Ω Input and Output Termination

15 kV ESD Protection on LVDS Inputs/Outputs

Hot Plug Protection

The 3.3V supply, CMOS process, and robust I/O

ensure high performance at low power over the entire

industrial -40 to +85°C temperature range.

Single 3.3V Supply

Industrial -40 to +85°C Temperature Range

48-pin WQFN Package

Typical Application

Switch

Fabric A

FPGA

Mux Buffer

ASIC

Switch

Fabric B

Figure 1.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS15MB200

SNLS196E –NOVEMBER 2005–REVISED MARCH 2013

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Block Diagram

PREA_0

ENA_0

PREB_0

ENB_0

LI_0

SOA_0

SOB_0

PREL_0

ENL_0

SIA_0

SIB_0

LO_0

MUX_S0

Channel 0

Channel 1

Figure 2.

PIN DESCRIPTIONS

Name

WQFN Pin

Number

I/O, Type

Description

SWITCH SIDE DIFFERENTIAL INPUTS

SIA_0+

SIA_0−

I, LVDS

Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LVPECL compatible.

SIA_1+

SIA_1−

Switch A-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LVPECL compatible.

SIB_0+

SIB_0−

Switch B-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LVPECL compatible.

SIB_1+

SIB_1−

Switch B-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LVPECL compatible.

LINE SIDE DIFFERENTIAL INPUTS

LI_0+

LI_0−

I, LVDS

Line-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LVPECL compatible.

LI_1+

LI_1−

I, LVDS

Line-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LVPECL compatible.

SWITCH SIDE DIFFERENTIAL OUTPUTS

SOA_0+

SOA_0−

O, LVDS

Switch A-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible⁽¹⁾⁽²⁾

Switch A-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible⁽¹⁾⁽²⁾

Switch B-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible⁽¹⁾⁽²⁾

Switch B-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible⁽¹⁾⁽²⁾

SOA_1+

SOA_1−

SOB_0+

SOB_0−

SOB_1+

SOB_1−

LINE SIDE DIFFERENTIAL OUTPUTS

LO_0+

LO_0−

O, LVDS

Line-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible⁽¹⁾⁽²⁾

LO_1+

LO_1−

O, LVDS

Line-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible⁽¹⁾⁽²⁾

(1) For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the applications section of this datasheet (planned).

(2) The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS15MB200 device have

been optimized for point-to-point backplane and cable applications.

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SNLS196E –NOVEMBER 2005–REVISED MARCH 2013

PIN DESCRIPTIONS (continued)

Name

WQFN Pin

Number

I/O, Type

Description

DIGITAL CONTROL INTERFACE

MUX_S0

MUX_S1

I, LVTTL

Mux Select Control Inputs (per channel) to select which Switch-side input, A or B, is passed through

to the Line-side.

PREA_0

PREA_1

PREB_0

PREB_1

I, LVTTL

Output pre-emphasis control for Switch-side outputs. Each output driver on the Switch A-side and B-

side has a separate pin to control the pre-emphasis on or off.

PREL_0

PREL_1

I, LVTTL

Output pre-emphasis control for Line-side outputs. Each output driver on the Line A-side and B-side

has a separate pin to control the pre-emphasis on or off.

ENA_0

ENA_1

ENB_0

ENB_1

Output Enable Control for Switch A-side and B-side outputs. Each output driver on the A-side and

B-side has a separate enable pin.

ENL_0

ENL_1

I, LVTTL

Output Enable Control for The Line-side outputs. Each output driver on the Line-side has a separate

enable pin.

POWER

V_DD

2, 6, 12,

37, 43, 46,

3, 47⁽³⁾

I, Power

V_DD= 3.3V ±0.3V.

GND

Ground reference for LVDS and CMOS circuitry.

For the WQFN package, the DAP is used as the primary GND connection to the device. The DAP is

the exposed metal contact at the bottom of the WQFN-48 package. It should be connected to the

ground plane with at least 4 vias for optimal AC and thermal performance.

(3) Note that the DAP on the backside of the WQFN package is the primary GND connection for the device when using the WQFN

package.

Connection Diagrams

12 11 10

ENA_1

ENB_1

ENA_1

ENB_1

Channel 1

GND

SOA_1+

SOA_1-

SOB_1+

SOB_1-

SIA_1+

SIA_1-

SOA_1+

SOA_1-

SOB_1+

SOB_1-

SIA_1+

SIA_1-

ENL_0

PREL_0

Channel 0

DAP

(GND)

LO_0+

LO_0-

LI_0+

LO_0+

LO_0-

LI_0+

SIB_1+

SIB_1-

SIB_1+

SIB_1-

LI_0-

MUX_S0

PREA_1

PREB_1

MUX_S0

PREA_1

PREB_1

25 26 27 28 29 30 31 32 33 34 35 36

Figure 3. WQFN Top View

DAP = GND

Figure 4. Directional Signal Paths Top View

(Refer to pin names for signal polarity)

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Output Characteristics

The output characteristics of the DS15MB200 have been optimized for point-to-point backplane and cable

applications, and are not intended for multipoint or multidrop signaling.

A 100Ω output (source) termination resistor is incorporated in the device to eliminate the need for an external

resistor, providing excellent drive characteristics by locating the source termination as close to the output as

physically possible.

Pre-Emphasis Controls

The pre-emphasis is used to compensate for long or lossy transmission media. Separate pins are provided for

each output to minimize power consumption. Pre-emphasis is programmable to be off or on per the Pre-

emphasis Control Table.

PREx_n⁽¹⁾

Output Pre-Emphasis

100%

(1) Applies to PREA_0, PREA_1, PREB_0, PREB_1, PREL_0, PREL_1

Multiplexer Truth Table⁽²⁾⁽³⁾

Data Inputs

Control Inputs

Output

LO_0

SIB_0

SIA_0

SIB_0

valid

MUX_S0

ENL_0

valid

(2) Same functionality for channel 1

(3) X = Don't Care

Z = High Impedance (TRI-STATE)

Repeater/Buffer Truth Table⁽¹⁾⁽²⁾

Data Input

Control Inputs

Outputs

LI_0

ENA_0

ENB_0

SOA_0

SOB_0

valid

LI_0

(1) Same functionality for channel 1

(2) X = Don't Care

Z = High Impedance (TRI-STATE)

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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SNLS196E –NOVEMBER 2005–REVISED MARCH 2013

Absolute Maximum Ratings⁽¹⁾

Value

Unit

Supply Voltage (V_DD

)

−0.3 to +4.0

CMOS Input Voltage

-0.3 to

(V_DD+0.3)

LVDS Receiver Input Voltage⁽²⁾

LVDS Driver Output Voltage

-0.3 to

(V_DD+0.3)

-0.3 to

(V_DD+0.3)

°C

LVDS Output Short Circuit Current

Junction Temperature

+40

+150

Storage Temperature

−65 to +150

Lead Temperature (Solder, 4sec)

Max Pkg Power Capacity @ 25°C

260

5.2

Thermal Resistance (θ_JA

)

°C/W

mW/°C

Package Derating above +25°C

41.7

HBM, 1.5kΩ, 100pF

LVDS pins to GND only

EIAJ, 0Ω, 200pF

CDM

ESD Last Passing Voltage

250

1000

(1) Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met,

without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables.

Texas Instruments does not recommend operation of products outside of recommended operation conditions.

(2) V_IDmax < 2.4V

Recommended Operating Conditions

Min

Max

Unit

Supply Voltage (V_CC

Input Voltage (V_I)⁽¹⁾

Output Voltage (V_O)

)

3.0

3.6

V_CC

+85

Operating Temperature (T_A) Industrial

(1) V_IDmax < 2.4V

−40

°C

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Units

Electrical Characteristics

Over recommended operating supply and temperature ranges unless other specified.

Symbol

Parameter

Conditions

Min

Typ⁽¹⁾

Max

LVTTL DC SPECIFICATIONS (MUX_Sn, PREA_n, PREB_n, PREL_n, ENA_n, ENB_n, ENL_n)

V_IH

V_IL

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

2.0

GND

−10

V_DD

0.8

I_IH

V_IN= V_DD= V_DDMAX

+10

200

+10

µA

I_IHR

I_IL

PREA_n, PREB_n, PREL_n

V_IN= V_SS, V_DD= V_DDMAX

Any Digital Input Pin to V_SS

Any Digital Output Pin to V_SS

I_CL= −18 mA

−10

C_IN1

C_OUT1

V_CL

2.0

4.0

Output Capacitance

Input Clamp Voltage

−1.5

−0.8

LVDS INPUT DC SPECIFICATIONS (SIA±, SIB±, LI±)

V_TH

Differential Input High Threshold⁽²⁾

V_CM= 0.8V or 1.2V or 3.55V,

V_DD= 3.6V

100

V_TL

Differential Input Low Threshold⁽²⁾

V_CM= 0.8V or 1.2V or 3.55V,

V_DD= 3.6V

−100

V_ID

Differential Input Voltage

Common Mode Voltage Range

Input Capacitance

V_CM= 0.8V to 3.55V, V_DD= 3.6V

V_ID= 150 mV, V_DD= 3.6V

IN+ or IN− to V_SS

100

2400

3.55

V_CMR

C_IN2

I_IN

0.05

2.0

µA

Input Current

V_IN= 3.6V, V_DD= V_DDMAXor 0V

V_IN= 0V, V_DD= V_DDMAXor 0V

−15

+15

LVDS OUTPUT DC SPECIFICATIONS (SOA_n±, SOB_n±, LO_n±)

V_OD

Differential Output Voltage,

0% Pre-emphasis⁽²⁾

R_Lis the internal 100Ω between OUT+

and OUT−

250

360

500

ΔV_OD

Change in V_ODbetween

Complementary States

Offset Voltage⁽³⁾

-35

1.05

-35

1.475

V_OS

1.22

ΔV_OS

Change in V_OSbetween

Complementary States

I_OS

Output Short Circuit Current

Output Capacitance

OUT+ or OUT− Short to GND

−21

-40

C_OUT2

OUT+ or OUT− to GND when TRI-

STATE

4.0

SUPPLY CURRENT (Static)

I_CC

Supply Current

All inputs and outputs enabled and

active, terminated with external load of

100Ω between OUT+ and OUT-.

225

0.6

275

4.0

I_CCZ

Supply Current - Powerdown Mode

ENA_0 = ENB_0 = ENL_0 = ENA_1 =

ENB_1 = ENL_1 = L

SWITCHING CHARACTERISTICS—LVDS OUTPUTS

t_LHT

Differential Low to High Transition

Time

Use an alternating 1 and 0 pattern at 200

170

1.0

250

2.5

Mb/s, measure between 20% and 80% of

(4)

V_OD

t_HLT

Differential High to Low Transition

Time

t_PLHD

t_PHLD

Differential Low to High Propagation Use an alternating 1 and 0 pattern at 200

Delay

Mb/s, measure at 50% V_ODbetween

input to output.

Differential High to Low Propagation

Delay

1.0

2.5

(4)

t_SKD1

t_SKCC

Pulse Skew

|t_PLHD–t_PHLD|

Output Channel to Channel Skew

Difference in propagation delay (t_PLHDor

t_PHLD) among all output channels.⁽⁴⁾

115

(1) Typical parameters are measured at V_DD= 3.3V, T_A= 25°C. They are for reference purposes, and are not production-tested.

(2) Differential output voltage V_ODis defined as ABS(OUT+–OUT−). Differential input voltage V_IDis defined as ABS(IN+–IN−).

(3) Output offset voltage V_OSis defined as the average of the LVDS single-ended output voltages at logic high and logic low states.

(4) Not production tested. Guaranteed by statistical analysis on a sample basis at the time of characterization.

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Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges unless other specified.

Symbol

Parameter

Conditions

Min

Typ⁽¹⁾

1.1

Max

1.5

Units

psrms

psp-p

t_JIT

Jitter (0% Pre-emphasis)⁽⁵⁾

RJ - Alternating 1 and 0 at 750MHz⁽⁶⁾

DJ - K28.5 Pattern, 1.5 Gbps⁽⁷⁾

TJ - PRBS 2⁷-1 Pattern, 1.5 Gbps⁽⁸⁾

t_ON

LVDS Output Enable Time

Time from ENA_n, ENB_n, or ENL_n to

OUT± change from TRI-STATE to active.

0.5

1.5

µs

t_ON2

LVDS Output Enable Time from

Powerdown Mode

Time from ENA_n, ENB_n, or ENL_n to

OUT± change from Powerdown Mode to

active.

µs

t_OFF

LVDS Output Disable Time

Time from ENA_n, ENB_n, or ENL_n to

OUT± change from active to TRI-STATE

or Powerdown mode.

(5) Jitter is not production tested, but guaranteed through characterization on a sample basis.

(6) Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = V_ID= 500mV, 50%

duty cycle at 750MHz, t_r= t_f= 50ps (20% to 80%).

(7) Deterministic Jitter, or D_J, is measured to a histogram mean with a sample size of 350 hits. Stimulus and fixture jitter have been

subtracted. The input voltage = V_ID= 500mV, K28.5 pattern at 1.5 Gbps, t_r= t_f= 50ps (20% to 80%). The K28.5 pattern is repeating bit

streams of (0011111010 1100000101).

(8) Total Jitter, or T_J, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter have been

subtracted. The input voltage = V_ID= 500mV, 2⁷-1 PRBS pattern at 1.5 Gbps, t_r= t_f= 50ps (20% to 80%).

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WQFN Performance Characteristics

Power Supply Current vs. Bit Data Rate

350

Total Jitter vs. Bit Data Rate

300

250

200

150

100

PRE-EMPHASIS ON

PRE-EMPHASIS OFF

VCM = 1.2V

VCM = 0.25V

VCM = 3.0V

500

1000

1500

2000

500

1000

1500

2000

BIT DATA RATE (Mbps)

Dynamic power supply current was measured with all channels

active and toggling at the bit data rate. Data pattern has no effect

on the power consumption.

Total Jitter measured at 0V differential while running a PRBS 2^7-1

pattern with one channel active, all other channels are disabled.

V_DD= 3.3V, T_A= +25°C, V_ID= 0.5V, pre-emphasis off.

V_DD= 3.3V, T_A= +25°C, V_ID= 0.5V, V_CM= 1.2V

Figure 5.

Figure 6.

Total Jitter vs. Temperature

-40 -20

80 100

TEMPERATURE (°C)

Total Jitter measured at 0V differential while running a PRBS 2⁷-1 pattern with one channel active, all other channels are disabled. V_DD

3.3V, V_ID= 0.5V, V_CM= 1.2V, 1.5 Gbps data rate, pre-emphasis off.

Figure 7.

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TRI-STATE AND POWERDOWN MODES

The DS15MB200 has output enable control on each of the six onboard LVDS output drivers. This control allows

each output individually to be placed in a low power TRI-STATE mode while the device remains active, and is

useful to reduce power consumption on unused channels. In TRI-STATE mode, some outputs may remain active

while some are in TRI-STATE.

When all six of the output enables (all drivers on both channels) are deasserted (LOW), then the device enters a

Powerdown mode that consumes only 0.5mA (typical) of supply current. In this mode, the entire device is

essentially powered off, including all receiver inputs, output drivers and internal bandgap reference generators.

When returning to active mode from Powerdown mode, there is a delay until valid data is presented at the

outputs because of the ramp to power up the internal bandgap reference generators.

Any single output enable that remains active will hold the device in active mode even if the other five outputs are

in TRI-STATE.

When in Powerdown mode, any output enable that becomes active will wake up the device back into active

mode, even if the other five outputs are in TRI-STATE.

Input Failsafe Biasing

External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe

under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor

and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors

should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-

mode bias point ideally should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal

circuitry. Please refer to application note AN-1194, “Failsafe Biasing of LVDS Interfaces” (SNLA051) for more

information.

Interfacing LVPECL to LVDS

An LVPECL driver consists of a differential pair with coupled emitters connected to GND via a current source.

This drives a pair of emitter-followers that require a 50 ohm to V_CC-2.0 load. A modern LVPECL driver will

typically include the termination scheme within the device for the emitter follower. If the driver does not include

the load, then an external scheme must be used. The 1.3 V supply is usually not readily available on a PCB,

therefore, a load scheme without a unique power supply requirement may be used.

50W

15MB200

LVPECL

50W

150W 150W

Figure 8. DC Coupled LVPECL to LVDS Interface

Figure 8 is a separated π termination scheme for a 3.3 V LVPECL driver. R1 and R2 provides proper DC load for

the driver emitter followers, and may be included as part of the driver device⁽¹⁾. The DS15MB200 includes a 100

ohm input termination for the transmission line. The common mode voltage will be at the normal LVPECL

levels – around 2 V. This scheme works well with LVDS receivers that have rail-to-rail common mode voltage,

V_CM, range. Most Texas Instrument's LVDS receivers have wide V_CMrange. The exceptions are noted in devices’

respective datasheets. Those LVDS devices that do have a wide V_CMrange do not vary in performance

significantly when receiving a signal with a common mode other than standard LVDS V_CMof 1.2 V.

(1) The bias networks shown above for LVPECL drivers and receivers may or may not be present within the driver device. The LVPECL

driver and receiver specification must be reviewed closely to ensure compatibility between the driver and receiver terminations and

common mode operating ranges.

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0.1 mF

50W

15MB200

LVPECL

150W

Figure 9. AC Coupled LVPECL to LVDS Interface

An AC coupled interface is preferred when transmitter and receiver ground references differ more than 1 V. This

is a likely scenario when transmitter and receiver devices are on separate PCBs. Figure 9 illustrates an AC

coupled interface between a LVPECL driver and LVDS receiver. R1 and R2, if not present in the driver device⁽²⁾,

provide DC load for the emitter followers and may range between 140-220 ohms for most LVPECL devices for

this particular configuration. The DS15MB200 includes an internal 100 ohm resistor to terminate the transmission

line for minimal reflections. The signal after AC coupling capacitors will swing around a level set by internal

biasing resistors (i.e. fail-safe) which is either V_DD/2 or 0 V depending on the actual failsafe implementation. If

internal biasing is not implemented, the signal common mode voltage will slowly wander to GND level.

Interfacing LVDS to LVPECL

An LVDS driver consists of a current source (nominal 3.5mA) which drives a CMOS differential pair. It needs a

differential resistive load in the range of 70 to 130 ohms to generate LVDS levels. In a system, the load should

be selected to match transmission line characteristic differential impedance so that the line is properly

terminated. The termination resistor should be placed as close to the receiver inputs as possible. When

interfacing an LVDS driver with a non-LVDS receiver, one only needs to bias the LVDS signal so that it is within

the common mode range of the receiver. This may be done by using separate biasing voltage which demands

another power supply. Some receivers have required biasing voltage available on-chip (V_T, V_TTor V_BB).

50W

LVPECL

15MB200

50W

Figure 10. DC Coupled LVDS to LVPECL Interface

Figure 10 illustrates interface between an LVDS driver and a LVPECL with a V_Tpin available. R1 and R2, if not

present in the receiver⁽²⁾, provide proper resistive load for the driver and termination for the transmission line,

and V_Tsets desired bias for the receiver.

(2) The bias networks shown above for LVPECL drivers and receivers may or may not be present within the driver device. The LVPECL

driver and receiver specification must be reviewed closely to ensure compatibility between the driver and receiver terminations and

common mode operating ranges.

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83W

0.1 mF

50W

LVPECL

15MB200

130W 130W

Figure 11. AC Coupled LVDS to LVPECL Interface

Figure 11 illustrates AC coupled interface between an LVDS driver and LVPECL receiver without a V_Tpin

available. The resistors R1, R2, R3, and R4, if not present in the receiver⁽²⁾, provide a load for the driver,

terminate the transmission line, and bias the signal for the receiver.

Packaging Information

The Leadless Leadframe Package (WQFN) is a leadframe based chip scale package (CSP) that may enhance

chip speed, reduce thermal impedance, and reduce the printed circuit board area required for mounting. The

small size and very low profile make this package ideal for high density PCBs used in small-scale electronic

applications such as cellular phones, pagers, and handheld PDAs. The WQFN package is offered in the no

Pullback configuration. In the no Pullback configuration the standard solder pads extend and terminate at the

edge of the package. This feature offers a visible solder fillet after board mounting.

The WQFN has the following advantages:

•

Low thermal resistance

Reduced electrical parasitics

Improved board space efficiency

Reduced package height

Reduced package mass

For more details about WQFN packaging technology, refer to applications note AN-1187, "Leadless Leadframe

Package" (SNOA401).

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REVISION HISTORY

Changes from Revision D (March 2013) to Revision E

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 11

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PACKAGE OPTION ADDENDUM

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10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

DS15MB200TSQ/NOPB

DS15MB200TSQX/NOPB

ACTIVE

WQFN

RHS

250

RoHS & Green

Level-3-260C-168 HR

-40 to 85

15M200

2500 RoHS & Green

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DS15MB200TSQ/NOPB WQFN

DS15MB200TSQX/NOPB WQFN

RHS

250

178.0

330.0

16.4

7.3

1.3

12.0

16.0

2500

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

DS15MB200TSQ/NOPB

DS15MB200TSQX/NOPB

WQFN

RHS

250

208.0

356.0

191.0

356.0

35.0

2500

Pack Materials-Page 2

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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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