DS1776E/883 [TI]
PI 总线收发器 | FK | 28 | -55 to 125;
| 型号： | DS1776E/883 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PI 总线收发器 | FK | 28 | -55 to 125 输入元件 信息通信管理 输出元件 逻辑集成电路 总线收发器 |
| 文件： | 总17页 (文件大小：676K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DS1776QML
ZHCSDX7B –AUGUST 2012–REVISED JUNE 2015
DS1776QML PI 总线收发器
1 特性
DS1776 是一款具有集电极开路 B 和三态 A 端口输出
驱动器的八路双向收发器。 该器件为 A 端口信号提供
了锁存功能。 B 端口输出驱动器设计为在 2V 电压时
具有 100mA 灌电流，并且特有受控线性斜坡，能够最
大限度降低总线上的串扰和振铃。
1
•
•
•
•
•
类似于桥接负载 (BTL)
低功耗 ICCL = 41mA（最大值）
B 输出控制的斜率
B 输入抗扰度：4ns（典型值）
与 Signetics 54F776 引脚和功能兼容
该器件提供了独立的高电平控制电压 (VX)，以防止 A
侧输出高电平超过未来高密度处理器的电源电压。 对
2 说明
于 5V 系统，VX 连接至 VCC
。
DS1776 是一款八路 PI 总线收发器。 A 到 B 的路径被
锁存。 B 输出是串联肖特基二极管的集电极开路输
出，可确保将 B 输出负载降至最低。 B 输出还具有斜
升和斜降时间（典型值为 2.5ns），可确保将 PI 总线
振铃最小化。 B 输入具有毛刺脉冲抑制电路，典型值
为 4ns。
器件信息(1)
器件型号
封装
封装尺寸（标称值）
11.43mm x 11.43mm
DS1776QML
LCCC (FK)
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
逻辑符号
该器件采用德州仪器 (TI) 的双极互补金属氧化物半导
体 (Bi-CMOS) 工艺设计，在工作和禁用状态下均可实
现低功耗。 其交流性能针对 PI 总线的互操作性要求进
行了优化。
DS1776 是一款八路锁存收发器，旨在为高性能线或总
线提供电气接口。 该总线的负载特性阻抗范围为 20Ω
至 50Ω，两端采用 30Ω 至 40Ω 范围内的电阻进行端
接。
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNOSC82
DS1776QML
ZHCSDX7B –AUGUST 2012–REVISED JUNE 2015
www.ti.com.cn
目录
5.8 Pi Bus Transceiver DS1776 AC Parameters: A To
B Path ........................................................................ 7
1
2
3
4
5
特性.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
5.1 Absolute Maximum Ratings ...................................... 4
5.2 ESD Ratings ............................................................ 4
5.3 Recommend Operating Conditions........................... 4
5.4 Thermal Information ................................................. 4
5.5 Quality Conformance Inspection............................... 5
5.6 Pi Bus Transceiver DS1776 DC Parameters............ 5
5.9 Pi Bus Transceiver DS1776 AC Parameters: Setup
/ Hold / Pulse Width Specifications............................ 7
5.10 Test Circuit And Waveforms ................................... 8
Detailed Description ............................................ 10
6.1 Controller Power Sequencing Operation ................ 11
器件和文档支持...................................................... 12
7.1 社区资源.................................................................. 12
7.2 商标......................................................................... 12
7.3 静电放电警告........................................................... 12
7.4 Glossary.................................................................. 12
机械、封装和可订购信息 ....................................... 12
6
7
5.7 Pi Bus Transceiver DS1776 AC Parameters: B To
A Path ........................................................................ 6
8
3 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2013) to Revision B
Page
•
•
已删除 产品预览...................................................................................................................................................................... 1
已更改 布局以符合新的 TI 格式 .............................................................................................................................................. 1
发布时间
修订版本
部分
更改
2012 年 7 月 30
日
已将 MDS 数据表转换为一种公司数据表格式。
MNDS1776-X 版本 2A0. 将被归档。
A1
新版本，公司格式
全部
2013 年 4 月 12
日
A
已将国家半导体数据表的版面布局更改为 TI 格式。
2
Copyright © 2012–2015, Texas Instruments Incorporated
DS1776QML
www.ti.com.cn
ZHCSDX7B –AUGUST 2012–REVISED JUNE 2015
4 Pin Configuration and Functions
LCCC Package
FK0028A
Top View
Pin Descriptions
PIN
I/O
DESCRIPTION
NAME
A0
NO.
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
A1
5
A2
6
A3
7
TTL Level, latched input/TRI-STATE output (with VX control option)
A4
9
A5
10
12
13
27
26
24
23
21
20
19
17
15
16
2
A6
A7
B0
B1
B2
B3
Data input with special threshold circuitry to reject noise/Open Collector output, High
current drive
B4
B5
B6
B7
OEB 0
OEB 1
OEA
LE
Enables the B outputs when both pins are low
I
I
Enables the A outputs when High
28
14
I
Latched when High (a special delay feature is built in for proper enabling times)
Clamping voltage keeping VOH from rising above VX (VX = VCC for normal use)
VX
I
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5 Specifications
5.1 Absolute Maximum Ratings(1)
MIN
−0.5
−0.5
−0.5
−0.5
−40
MAX
7.0
UNIT
V
Supply Voltage (VCC
)
VX, VOH Output Level Control Voltage (A Outputs)
OEBn, OEA, LE Input Voltage (VI)
7.0
V
7.0
V
A0–A7, B0–B7 Input Voltage (VI)
5.5
V
Input Current (II)
5
mA
Voltage Applied to Output in High Output State (VO)
A0–A7 Current Applied to Output in Low Output State (IO)
B0–B7 Current Applied to Output in Low Output State (IO)
Lead Temperature (Soldering 10 Sec.)
−0.5V
40
+VCC
40
mA
mA
°C
200
200
260
740
+150
(2)
Power Dissipation
mW
°C
Storage temperature
Tstg
−65
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For specified specifications and test conditions, see the
Electrical Characteristics. The specified specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),
θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any
temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
5.2 ESD Ratings
MIN
MAX
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1) (2)
V(ESD)
Electrostatic discharge
500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) CZap = 120 pF, RZap = 1500Ω
5.3 Recommend Operating Conditions
MIN
4.5
MAX
5.5
UNIT
Supply Voltage (VCC
)
V
Operating Temp. Range (TA)
−55
+125
°C
5.4 Thermal Information
DS1776QML
FK0028A
28 PINS
+67.5
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
RθJC(top)
See MIL-STD-
1835
Junction-to-case (top) thermal resistance
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2012–2015, Texas Instruments Incorporated
DS1776QML
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ZHCSDX7B –AUGUST 2012–REVISED JUNE 2015
5.5 Quality Conformance Inspection
Table 1. Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Static tests at
Temp (°C)
+25
1
2
Static tests at
+125
-55
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling time at
Settling time at
Settling time at
+25
5
+125
-55
6
7
+25
8A
8B
9
+125
-55
+25
10
11
12
13
14
+125
-55
+25
+125
-55
5.6 Pi Bus Transceiver DS1776 DC Parameters
The following conditions apply, unless otherwise specified. VCC = 5.5V
SUB-
GROUPS
SYMBOL
PARAMETER
CONDITIONS
NOTES
MIN MAX
UNIT
VIL2
Low Level In Voltage Bn
All Other Inputs
VCC = 4.5
VCC = 4.5
See(1)
1.45
.8
V
V
1, 2, 3
1, 2, 3
VIL1
VIH1
VIH2
IOH1
Hi Level Input Voltage OEBn,
OEA, An, LE
See(1)
See(2)
2.0
1.6
-3.0
V
V
1, 2, 3
1, 2, 3
1, 2, 3
High Level In Voltage B0-B7
VCC = 4.5, VIN = VIH or VIL,
VOH = 2.5V
High Level Output Current An
mA
VCC = 5.5, VIL = 0.8V,
VIH = 2.0V, VOH = 2.1V
IOH2
IOL1
IOL2
High Level Output Current Bn
Low Level Output Current An
Low Level Output Current Bn
100
20
µA
mA
mA
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
VCC = 4.5, VIN = VIH or VIL,
VOL = 0.5V
See(3)
VCC = 4.5, VIN = VIH or VIL,
VOL = 1.15V
100
VCC = 4.5, VIN = VIL or VIH
IOH = -3 mA, VX = 4.5V
,
2.5
2.5
4.5
VX
VOH
High Level Output Voltage An
Low Level Output Voltage An
VCC = 4.5, VIN = VIL or VIH
IOH = -0.4 mA,
VX = 3.13 to 3.47V
,
V
V
1, 2, 3
1, 2, 3
VCC = 4.5, VIL = Max,
VIH = Min, IOL = 20mA,
VX = VCC
VOL
0.5
VCC = 4.5, VIL = Max,
VIH = Min, IOL = 100mA
1.15
V
V
1, 2, 3
1, 2, 3
VOLB
Low Level Output Voltage Bn
Input Clamp Voltage An
VCC = 4.5, VIL = Max,
VIH = Min, IOL = 4mA
0.4
VIK
VIK
VCC = 4.5, II = -40mA
-0.5
-1.2
V
V
1, 2, 3
1, 2, 3
Input Clamp Voltage Other Inputs VCC = 4.5, II = -18mA
(1) Tested Go-No-Go
(2) Same as VOH test.
(3) Same as VOL test.
Copyright © 2012–2015, Texas Instruments Incorporated
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ZHCSDX7B –AUGUST 2012–REVISED JUNE 2015
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Pi Bus Transceiver DS1776 DC Parameters (continued)
The following conditions apply, unless otherwise specified. VCC = 5.5V
SUB-
GROUPS
SYMBOL
IIH1
PARAMETER
CONDITIONS
VCC = 5.5, VI = 7.0V
NOTES
MIN MAX
100
UNIT
µA
Input Current Max Input Voltage
OEBn, OEA, LE
1, 2, 3
1, 2, 3
Input Current Max Input Voltage
An, Bn
IIH2
VCC = 5.5, VI = 5.5V
1.0
mA
High Level Input Current OEBn,
OEA, LE
IIH3
IIH4
IIL1
VCC = 5.5, VI = 2.7V
VCC = 5.5, VI = 2.1V
VCC = 5.5, VI = 0.5V
20
100
-20
µA
µA
µA
1, 2, 3
1, 2, 3
1, 2, 3
High Level Input Current Bn
Low Level Input Current OEBn,
OEA, Except OEBn or OEA
-20
-40
µA
µA
µA
1
IIL2
Low Level Input Current LE
Low Level Input Current Bn
VCC = 5.5, VI = 0.5V
2, 3
IIL3
VCC = 5.5, VI = 0.3V
VCC = 5.5, VO = 2.7V
-100
1, 2, 3
IOZH + IIH
TRI-STATE Output Current, High
Level Voltage Applied An
70
µA
µA
1, 2, 3
1, 2, 3
IOZL + IIL
TRI-STATE Output Current, Low
Level Voltage Applied An
VCC = 5.5, VO = 0.5V
-70
VCC = 5.5, VX = 5.5V,
LE = OEA = OEBn = 2.7V,
A0-A7 = 2.7, B0-B7 = 2V
-100 100
µA
mA
mA
1, 2, 3
1, 2, 3
1, 2, 3
IX
High Level Control Current
VCC = 5.5, B0-B7 = 2V
VX = 3.13V and 3.47V,
LE = OEA = 2.7V,
-10
-60
10
OEBn = A0-A7 = 2.7V,
VCC = 5.5, Bn = 1.9V,
OEA = 2.0V, OEBn = 2.7V,
VO = 0V
Short Circuit Output Current A0-
A7 only
IOS
See(4)
-150
37
41
38
34
35
mA
mA
mA
mA
mA
1, 2
3
ICCH
Supply Current (Total) ICCH
Supply Current (Total) ICCL
VCC = 5.5, VIN (An) = 5.0V
1, 3
2
ICCL
ICCZ
IOff
VCC = 5.5, VIN (An) = 0.5V
VCC = 5.5, VIN (An) = 0.5V
Supply Current (Total) ICCZ
1, 2, 3
VCC = 0, Bn = 2.1V, VIL = Max,
VIH = Min
Power Off Output Current B0-B7
100
µA
1, 2, 3
(4) Not more than one output should be shorted at a time. For testing IOS, the use of high speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged
shorting of a High output may raise the chip temperature above normal and thereby cause invalid readings in other parameter tests. In
any sequence of parameter test, IOS tests should be performed last.
5.7 Pi Bus Transceiver DS1776 AC Parameters: B To A Path
The following conditions apply, unless otherwise specified. VCC = 5V ±10%, CL = 50pF, RL = 500Ω
SUB-
SYMBOL
PARAMETER
CONDITIONS
NOTES
MIN MAX
UNIT
GROUPS
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
tPLH
Propagation Delay B to A
Propagation Delay B to A
Output Enable OEA To A
Output Enable OEA To A
Output Disable OEA to A
Output Disable OEA to A
Waveform 1, 2
4.5
6.0
4.0
4.0
2.0
2.0
17
17
17
21
12
13
ns
ns
ns
ns
ns
ns
tPHL
tPZH
tPZL
tPHZ
tPLZ
Waveform 1, 2
Waveform 3, 4
Waveform 3, 4
Waveform 3, 4
Waveform 3, 4
6
Copyright © 2012–2015, Texas Instruments Incorporated
DS1776QML
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ZHCSDX7B –AUGUST 2012–REVISED JUNE 2015
5.8 Pi Bus Transceiver DS1776 AC Parameters: A To B Path
The following conditions apply, unless otherwise specified. VCC = 5V ±10%, CL = 30pF, RL = 9Ω
SUB-
GROUPS
SYMBOL
PARAMETER
CONDITIONS
NOTES
MIN MAX
UNIT
2.0
2.0
2.5
2.0
2.0
2.0
2.0
2.0
3.5
3.5
3.5
13
17
13
16
22
16
13
16
14
13
16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9, 11
10
tPLH
Propagation Delay A to B
Waveform 1, 2
tPHL
tPLH
Propagation Delay A to B
Propagation Delay LE to B
Waveform 1, 2
Waveform 1, 2
9, 10, 11
9, 11
10
tPHL
tPLH
Propagation Delay LE to B
Waveform 1, 2
9, 10, 11
9, 11
10
Enable / Disable Time OEBn to B Waveform 1, 2
9
tPHL
Enable / Disable Time OEBn to B Waveform 1, 2
10
11
5.9 Pi Bus Transceiver DS1776 AC Parameters: Setup / Hold / Pulse Width Specifications
The following conditions apply, unless otherwise specified. VCC = 5V ±10%
SUB-
GROUPS
SYMBOL
PARAMETER
CONDITIONS
NOTES
MIN MAX
UNIT
tS
A to LE Setup
Waveform 5
7.0
0.0
12
ns
ns
ns
9, 10, 11
9, 10, 11
9, 10, 11
tH
A to LE Hold
Waveform 5
Waveform 5
tW
LE Pulse Width Low
Figure 1. Propagation Delay For Data To Output
Figure 2. Propagation Delay For Data To Output
Figure 3. TRI-STATE Output Enable Time
To High Level And Output Disable
Time From High Level
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ZHCSDX7B –AUGUST 2012–REVISED JUNE 2015
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Figure 4. TRI-STATE Output Enable Time
To Low Level And Output Disable
Time From Low Level
The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 5. Data Setup And Hold Times And Le Pulse Widths
5.10 Test Circuit And Waveforms
Figure 6. Test Circuit For TRI-STATE Outputs On A Side
Table 2. Switch Position
Test
Switch
tPLZ, tPZL
All Other
Closed
Open
Figure 7. Test Circuit For TRI-STATE Outputs On B Side
DEFINITIONS
RL = Load resistor 500Ω
CL = Load capacitance includes jig and probe capacitance
RT = Termination resistance should be equal to ZO of pulse generators.
RU = Pull up resistor
8
Copyright © 2012–2015, Texas Instruments Incorporated
DS1776QML
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ZHCSDX7B –AUGUST 2012–REVISED JUNE 2015
Figure 8. Input Pulse Definition
Input Pulse Characteristics
Amplitude
3.0V
Low V
0.0V
Rep. Rate
1 MHz
tW
tTLH
2 ns
2 ns
tTHL
2 ns
2 ns
A Side
B Side
500 ns
500 ns
2.0V
1.0V
1 MHz
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6 Detailed Description
VCC = Pin 1
VX = Pin 14
Gnd = Pins 4, 8, 11, 18, 22, 25
Figure 9. Functional Logic Diagram
10
Copyright © 2012–2015, Texas Instruments Incorporated
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ZHCSDX7B –AUGUST 2012–REVISED JUNE 2015
Table 3. Function Table(1)
Inputs
LE OEA OEB 0 OEB 1
Latch
State
H
Outputs
Mode
An
H
Bn(2)
X
An
Bn
L
L
L
L
L
L
L
L
Z
Z
H
L
A TRI-STATE, Data from A to B
L
X
L
X
X
H
L
L
L
L
Qn
See(3)
H(4)
H(4)
Qn
H
Z
Qn
See(2)
off(4)
off(4)
Qn
off
A TRI-STATE, Latched Data to B
Feedback: A to B, B to A
—
—
—
—
H
—
H
L
H
H
H
H
L
L
L
See(2)
H
H
H
L
L
L
H
Preconditioned Latch Enabling
Data Transfer from B to A
Latch State to A and B
L
L
L
—
X
L
L
Qn
Z
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
L
X
L
L
L
Z
off
B off and A TRI-STATE
X
X
H
L
L
Qn
H
Z
off
—
—
—
—
H
H
L
H
H
H
H
L
H
off
L
L
L
off
H
L
H
H
L
Qn
Qn
H
H
off
B off, Data from B to A
B off and A TRI-STATE
B off, Data from B to A
L
off
X
Z
off
L
X
L
L
L
Z
off
X
X
H
L
L
Qn
H
Z
off
—
—
—
—
H
L
H
H
H
H
H
off
L
L
L
off
H
L
H
H
Qn
Qn
H
off
L
off
(1) H = High Voltage Level
L = Low Voltage Level
X = Don't Care
— = Input not externally driven
Z = High Impedance (off) state
Qn = High or Low voltage level one setup time prior to the Low-to-High LE transition
(2) Condition will cause a feedback loop path; A to B and B to A.
(3) Precaution should be taken to ensure that the B inputs do not float. If they do, they are equal to a Low state.
(4) The latch must be preconditioned such that B inputs may assume a High or Low level while OEB 0 and OEB 1, are Low and LE is high.
6.1 Controller Power Sequencing Operation
The DS1776 has a design feature which controls the output transitions during power up (or down). There are two
possible conditions that occur.
1. When LE = Low and OEBn = Low, the B outputs are disabled until the LE circuit can take control. This
feature ensures that the B outputs will follow the A inputs and allow only one transition during power up (or
down).
2. If LE = High or OEBn = High, then the B outputs still remain disabled during power up (or down).
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7 器件和文档支持
7.1 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
7.2 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
7.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
7.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
8 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
12
版权 © 2012–2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962-9231701M3A
ACTIVE
LCCC
LCCC
FK
28
28
25
RoHS-Exempt
& Green
Call TI
Level-1-NA-UNLIM
-55 to 125
DS1776E
/883 Q
5962-92317
01M3A ACO
01M3A >T
Samples
DS1776E/883
ACTIVE
FK
25
RoHS-Exempt
& Green
Call TI
Level-1-NA-UNLIM
-55 to 125
DS1776E
/883 Q
Samples
5962-92317
01M3A ACO
01M3A >T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Apr-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
5962-9231701M3A
DS1776E/883
FK
FK
LCCC
LCCC
28
28
25
25
NA
NA
NA
NA
109.22 109.22 7620 12.7 26.01 26.01
109.22 109.22 7620 12.7 26.01 26.01
Pack Materials-Page 1
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