DS25BR101 [TI]
具有发送预加重和接收均衡功能的 3.125Gbps LVDS 缓冲器;
| 型号： | DS25BR101 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有发送预加重和接收均衡功能的 3.125Gbps LVDS 缓冲器 |
| 文件： | 总21页 (文件大小：559K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS25BR100
www.ti.com
SNLS217F –MARCH 2007–REVISED APRIL 2013
DS25BR100 / DS25BR101 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and
Receive Equalization
Check for Samples: DS25BR100
1
FEATURES
DESCRIPTION
The DS25BR100 and DS25BR101 are single channel
3.125 Gbps LVDS buffers optimized for high-speed
signal transmission over lossy FR-4 printed circuit
board backplanes and balanced metallic cables. Fully
differential signal paths ensure exceptional signal
integrity and noise immunity.
2
•
DC - 3.125 Gbps Low Jitter, High Noise
Immunity, Low Power Operation
•
•
•
Receive Equalization Reduces ISI Jitter Due to
Media Loss
Transmit Pre-Emphasis Drives Lossy
Backplanes and Cables
The DS25BR100 and DS25BR101 feature transmit
pre-emphasis (PE) and receive equalization (EQ),
making them ideal for use as a repeater device.
Other LVDS devices with similar IO characteristics
include the following products. The DS25BR120
features four levels of pre-emphasis for use as an
optimized driver device, while the DS25BR110
features four levels of equalization for use as an
optimized receiver device. The DS25BR150 is a
buffer/repeater with the lowest power consumption
and does not feature transmit pre-emphasis nor
receive equalization.
On-Chip 100Ω Input and Output Termination:
–
–
–
Minimizes Insertion and Return Losses
Reduces Component Count
Minimizes Board Space
•
•
•
DS25BR101 Eliminates On-Chip Input
Termination for Added Design Flexibility
7 kV ESD on LVDS I/O Pins Protects Adjoining
Components
Small 3 mm x 3 mm WSON-8 Space Saving
Package
Wide input common mode range allows the receiver
to accept signals with LVDS, CML and LVPECL
levels; the output levels are LVDS. A very small
package footprint requires minimal space on the
board while the flow-through pinout allows easy board
layout. On the DS25BR100 the differential input and
output is internally terminated with a 100Ω resistor to
lower return losses, reduce component count and
further minimize board space. For added design
flexibility the 100Ω input terminations on the
DS25BR101 have been eliminated. This elimination
enables a designer to adjust the termination for
custom interconnect topologies and layout.
APPLICATIONS
•
•
•
Clock and Data Buffering
Metallic Cable Driving and Equalization
FR-4 Equalization
Typical Application
V
CC
CML
LVDS
ASIC / FPGA
BR100
LVPECL
V
CC
ASIC / FPGA
BR100
LVDS
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
DS25BR100
SNLS217F –MARCH 2007–REVISED APRIL 2013
Device Information
Device
www.ti.com
Function
Buffer / Repeater
Buffer / Repeater
Termination Option
Available Signal Conditioning
2 Levels: PE and EQ
2 Levels: PE and EQ
4 Levels: EQ
DS25BR100
DS25BR101
DS25BR110
DS25BR120
DS25BR150
Internal 100Ω for LVDS inputs
External termination required
Internal 100Ω for LVDS inputs
Internal 100Ω for LVDS inputs
Internal 100Ω for LVDS inputs
Receiver
Driver
4 Levels: PE
Buffer / Repeater
None
Block Diagram
EQ
PE
IN+
IN-
OUT+
OUT-
DS25BR101 eliminates 100Ω input termination.
Pin Diagram
EQ
IN+
IN-
PE
1
2
3
4
8
7
6
5
VCC
DAP
GND
OUT+
OUT-
NC
PIN DESCRIPTIONS
Pin Name
EQ
Pin Name
Pin Type
Pin Description
1
2
Input
Input
Equalizer select pin.
Non-inverting LVDS input pin.
IN+
IN-
3
Input
Inverting LVDS input pin.
Pre-emphasis select pin.
"NO CONNECT" pin.
PE
4
Input
NC
5
NA
OUT-
OUT+
VCC
GND
6
Output
Output
Power
Power
Inverting LVDS output pin.
Non-inverting LVDS Output pin.
Power supply pin.
7
8
DAP
Ground pad (DAP - die attach pad).
Control Pins (PE and EQ) Truth Table
EQ
0
PE
0
Equalization Level
Pre-emphasis Level
Low (Approx. 4 dB at 1.56 GHz)
Low (Approx. 4 dB at 1.56 GHz)
Medium (Approx. 8 dB at 1.56 GHz)
Medium (Approx. 8 dB at 1.56 GHz)
Off
0
1
Medium (Approx. 6 dB at 1.56 GHz)
Off
1
0
1
1
Medium (Approx. 6 dB at 1.56 GHz)
2
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SNLS217F –MARCH 2007–REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to +4V
1V
LVCMOS Input Voltage (EQ, PE)
LVDS Input Voltage (IN+, IN−)
Differential Input Voltage |VID| (DS25BR100)
LVDS Differential Input Voltage (DS25BR101)
LVDS Output Voltage (OUT+, OUT−)
LVDS Differential Output Voltage ((OUT+) - (OUT−))
LVDS Output Short Circuit Current Duration
Junction Temperature
VCC + 0.6V
−0.3V to (VCC + 0.3V)
0V to 1V
5 ms
+150°C
Storage Temperature Range
−65°C to +150°C
+260°C
Lead Temperature Range
Soldering (4 sec.)
NGQ0008A Package
2.08W
Maximum Package Power Dissipation at 25°C
Package Thermal Resistance
Derate NGQ0008A Package
16.7 mW/°C above +25°C
+60.0°C/W
θJA
θJC
+12.3°C/W
HBM(3)
MM(4)
CDM(5)
≥7 kV
ESD Susceptibility
≥250V
≥1250V
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) Human Body Model, applicable std. JESD22-A114C
(4) Machine Model, applicable std. JESD22-A115-A
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions
Min
Typ
Max
3.6
Units
V
Supply Voltage (VCC
)
3.0
3.3
Receiver Differential Input Voltage (VID) (DS25BR100 only)
Operating Free Air Temperature (TA)
1.0
V
−40
+25
+85
°C
Copyright © 2007–2013, Texas Instruments Incorporated
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DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified(1)(2)(3)
Parameter
Test Conditions
Min
Typ
Max
Units
LVCMOS INPUT DC SPECIFICATIONS (EQ, PE)
VIH
VIL
IIH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
2.0
VCC
0.8
V
V
GND
VIN = 3.6V
VCC = 3.6V
0
0
±10
μA
IIL
Low Level Input Current
Input Clamp Voltage
VIN = GND
VCC = 3.6V
±10
μA
VCL
ICL = −18 mA, VCC = 0V
-0.9
−1.5
V
LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-)
VOD
Differential Output Voltage
250
-35
350
1.2
450
35
mV
mV
V
RL = 100Ω
RL = 100Ω
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
VOS
Offset Voltage
1.05
-35
1.375
35
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
mV
IOS
Output Short Circuit Current(4)
OUT to GND, PE = 0
-35
7
-55
55
mA
mA
pF
Ω
OUT to VCC, PE = 0
COUT
ROUT
Output Capacitance
Any LVDS Output Pin to GND
Between OUT+ and OUT-
1.2
100
Output Termination Resistor
LVDS INPUT DC SPECIFICATIONS (IN+, IN-)
VID
Input Differential Voltage(5)
0
1
V
mV
mV
V
VTH
VTL
Differential Input High Threshold
Differential Input Low Threshold
Common Mode Voltage Range
VCM = +0.05V or VCC-0.05V
VID = 100 mV
0
0
+100
−100
VCMR
0.05
VCC -
0.05
VIN = GND or 3.6V
VCC = 3.6V or 0.0V
±1
±10
μA
IIN
Input Current
CIN
RIN
Input Capacitance
Input Termination Resistor(6)
Any LVDS Input Pin to GND
Between IN+ and IN-
1.7
pF
100
Ω
SUPPLY CURRENT
ICC Supply Current
EQ = 0, PE = 0
35
43
mA
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD
.
(3) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
(5) Input Differential Voltage (VID) The DS25BR100 limits input amplitude to 1 volt. The DS25BR101 supports any VID within the supply
voltage to GND range.
(6) Input Termination Resistor (RIN) The DS25BR100 provides an integrated 100 ohm input termination for the high speed LVDS pair. The
DS25BR101 eliminates this internal termination.
4
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SNLS217F –MARCH 2007–REVISED APRIL 2013
AC Electrical Characteristics(1)
Over recommended operating supply and temperature ranges unless otherwise specified(2)(3)
Parameter
Test Conditions
Min
Typ
Max
Units
LVDS OUTPUT AC SPECIFICATIONS (OUT+, OUT-)
tPHLD
tPLHD
tSKD1
tSKD2
tLHT
Differential Propagation Delay High to Low
350
350
45
465
465
100
150
150
150
ps
ps
ps
ps
ps
ps
RL = 100Ω
Differential Propagation Delay Low to High
(4)
Pulse Skew |tPLHD − tPHLD
Part to Part Skew(5)
Rise Time
|
45
80
RL = 100Ω
tHLT
Fall Time
80
JITTER PERFORMANCE WITH PE = OFF AND EQ = LOW(6)(7)
tRJ1A VID = 350 mV
tRJ2A
2.5 Gbps
0.5
0.5
1
1
1
ps
ps
Random Jitter (RMS Value)
Input Test Channel D(8)
VCM = 1.2V
Clock (RZ)
3.125 Gbps
2.5 Gbps
PE = 0, EQ = 0
tDJ1A
tDJ2A
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
PE = 0, EQ = 0
16
ps
Deterministic Jitter (Peak to Peak)
Input Test Channel D(9)
3.125 Gbps
2.5 Gbps
11
31
ps
tTJ1A
tTJ2A
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
PE = 0, EQ = 0
0.03
0.06
0.09
0.14
UIP-P
UIP-P
Total Jitter (Peak to Peak)
Input Test Channel D(10)
3.125 Gbps
JITTER PERFORMANCE WITH PE = OFF AND EQ = MEDIUM(6)(7)
tRJ1B VID = 350 mV
tRJ2B
2.5 Gbps
0.5
0.5
10
1
1
ps
ps
Random Jitter (RMS Value)
Input Test Channel E(8)
VCM = 1.2V
Clock (RZ)
3.125 Gbps
2.5 Gbps
PE = 0, EQ = 1
tDJ1B
tDJ2B
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
PE = 0, EQ = 1
29
ps
Deterministic Jitter (Peak to Peak)
Input Test Channel E(9)
3.125 Gbps
2.5 Gbps
27
43
ps
tTJ1B
tTJ2B
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
PE = 0, EQ = 1
0.07
0.12
0.12
0.17
UIP-P
UIP-P
Total Jitter (Peak to Peak)
Input Test Channel E(10)
3.125 Gbps
(1) Specification is ensured by characterization and is not tested in production.
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
(4) tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(5) tSKD2, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(6) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD
.
(7) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
(8) Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted
geometrically.
(9) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
(10) Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
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AC Electrical Characteristics(1) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified(2)(3)
Parameter
Test Conditions
Min
Typ
Max
Units
JITTER PERFORMANCE WITH PE = MEDIUM AND EQ = LOW(11)(12)
tRJ1C
tRJ2C
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
0.5
29
1
1
ps
ps
Random Jitter (RMS Value)
Input Test Channel D
Output Test Channel B(13)
3.125 Gbps
2.5 Gbps
PE = 1, EQ = 0
tDJ1C
tDJ2C
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
PE = 1, EQ = 0
57
ps
Deterministic Jitter (Peak to Peak)
Input Test Channel D
Output Test Channel B(14)
3.125 Gbps
2.5 Gbps
29
51
ps
tTJ1C
tTJ2C
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
PE = 1, EQ = 0
0.10
0.13
0.19
0.22
UIP-P
UIP-P
Total Jitter (Peak to Peak)
Input Test Channel D
Output Test Channel B(15)
3.125 Gbps
JITTER PERFORMANCE WITH PE = MEDIUM AND EQ = MEDIUM(11)(12)
tRJ1D
tRJ2D
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
0.5
41
1.1
1
ps
ps
Random Jitter (RMS Value)
Input Test Channel E
Output Test Channel B(13)
3.125 Gbps
2.5 Gbps
PE = 1, EQ = 1
tDJ1D
tDJ2D
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
PE = 1, EQ = 1
77
ps
Deterministic Jitter (Peak to Peak)
Input Test Channel E
Output Test Channel B(14)
3.125 Gbps
2.5 Gbps
46
98
ps
tTJ1D
tTJ2D
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
PE = 1, EQ = 1
0.13
0.19
0.20
0.30
UIP-P
UIP-P
Total Jitter (Peak to Peak)
Input Test Channel E
Output Test Channel B(15)
3.125 Gbps
(11) Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
(12) Input Differential Voltage (VID) The DS25BR100 limits input amplitude to 1 volt. The DS25BR101 supports any VID within the supply
voltage to GND range.
(13) Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted
geometrically.
(14) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
(15) Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
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Typical Performance Characteristics
4.50
V
CC
= 3.3V
w/ PE and/or EQ
T
= 25°C
A
3.75
3.00
NRZ PRBS-7
TJ = 0.25 UI
2.25
1.50
0.75
w/o PE and EQ
0
0
6
12
18
24
30
CAT5e LENGTH (m)
Figure 1. Maximum Data Rate as a Function of CAT5e
(Belden 1700A) Length
Figure 2. A 2.5 Gbps NRZ PRBS-7 After 60"
Differential FR-4 Stripline
V:125 mV / DIV, H:75 ps / DIV
4.50
w/ PE and/or EQ
3.75
3.00
2.25
w/o PE and EQ
1.50
V
= 3.3V
CC
T
= 25°C
0.75
0
A
NRZ PRBS-7
TJ = 0.5 UI
0
6
12
18
24
30
CAT5e LENGTH (m)
Figure 3. A 3.125 Gbps NRZ PRBS-7 After 60"
Differential FR-4 Stripline
Figure 4. Maximum Data Rate as a Function of CAT5e
(Belden 1700A) Length
V:125 mV / DIV, H:50 ps / DIV
Figure 5. An Equalized (with PE and EQ) 2.5 Gbps NRZ
PRBS-7 After The 40" Input and 20" Output
Differential Stripline (Figure 16)
Figure 6. An Equalized (with PE and EQ) 3.125 Gbps NRZ
PRBS-7 After The 40" Input and 20" Output
Differential Stripline (Figure 16)
V:125 mV / DIV, H:75 ps / DIV
V:125 mV / DIV, H:50 ps / DIV
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Typical Performance Characteristics (continued)
150
150
V
CC
= 3.3V
V
= 3.3V
CC
T
= 25°C
T
= 25°C
A
A
125
100
125
100
NRZ PRBS-7
EQ = Low
PE = Off
NRZ PRBS-7
2.5 Gbps
PE = Off
75
75
20" FR4 Stripline
30" FR4, EQ = Medium
15" FR4, EQ = Low
50
25
50
25
10" FR4 Stripline
0
0.25
0
0.40
0.55
0.70
0.85
1.00
0
0.8
1.6
2.4
3.2
4.0
DIFFERENTIAL INPUT VOLTAGE (V)
DATA RATE (Gbps)
Figure 7. Total Jitter as a Function of Data Rate
Figure 8. Total Jitter as a Function of Input Amplitude
50
150
PE = Medium, EQ = Any
V
= 3.3V
CC
T
= 25°C
A
45
125 40" FR4 Stripline
100
NRZ PRBS-7
EQ = Medium
PE = Off
40
35
PE = Off, EQ = Any
75
30" FR4 Stripline
50
30
25
20" FR4 Stripline
V
= 3.3V
CC
25
0
T
= 25°C
A
20
0
0.4
0.8
1.2
1.6
2.0
0
0.8
1.6
2.4
3.2
4.0
FREQUENCY (GHz)
DATA RATE (Gbps)
Figure 9. Power Supply Current as a Function of Frequency
Figure 10. Total Jitter as a Function of Data Rate
150
V
CC
= 3.3V
T
= 25°C
A
125
100
NRZ PRBS-7
3.125 Gbps
PE = Off
75
30" FR4, EQ = Medium
50
25
15" FR4, EQ = Low
0.70 0.85 1.00
DIFFERENTIAL INPUT VOLTAGE (V)
0
0.25
0.40
0.55
Figure 11. Total Jitter as a Function of Input Amplitude
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APPLICATION INFORMATION
DC Test Circuits
V
OH
OUT+
OUT-
IN+
IN-
Power Supply
Power Supply
R
L
R
D
V
OL
Figure 12. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
OUT+
OUT-
IN+
IN-
Signal Generator
R
L
R
D
Figure 13. Differential Driver AC Test Circuit
NOTE
DS25BR101 requires external 100Ω input termination.
Figure 14. Propagation Delay Timing Diagram
Figure 15. LVDS Output Transition Times
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Pre-Emphasis and Equalization Test Circuits
TEST
CHANNEL
CHARACTERIZATION
BOARD
TEST
CHANNEL
50W
Microstrip
50W
Microstrip
DS25BR100
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50W
Microstrip
50W
Microstrip
Figure 16. Pre-emphasis and Equalization Performance Test Circuit
NOTE
DS25BR101 requires external 100Ω input termination.
TEST
CHANNEL
CHARACTERIZATION
BOARD
50W
Microstrip
50W
Microstrip
DS25BR100
L=4"
L=4"
PATTERN
GENERATOR
OSCILLOSCOPE
L=4"
L=4"
50W
Microstrip
50W
Microstrip
Figure 17. Equalization Performance Test Circuit
NOTE
DS25BR101 requires external 100Ω input termination.
50W MS
50W MS
L=1"
L=1"
L=1"
L=1"
100W Diff.
Stripline
50W MS
50W MS
Figure 18. Test Channel Description
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Test Channel Loss Characteristics
The test channel was fabricated with Polyclad PCL-FR-370-Laminate/PCL-FRP-370 Prepreg materials (Dielectric
constant of 3.7 and Loss Tangent of 0.02). The edge coupled differential striplines have the following geometries:
Trace Width (W) = 5 mils, Gap (S) = 5 mils, Height (B) = 16 mils.
Test Channel
Length
(inches)
Insertion Loss (dB)
1000 MHz 1250 MHz
-2.0 -2.4
500 MHz
-1.2
750 MHz
-1.7
1500 MHz
-2.7
1560 MHz
-2.8
A
B
C
D
E
F
10
20
30
15
30
60
-2.6
-3.5
-4.1
-7.0
-2.7
-5.6
-12.4
-4.8
-8.2
-3.2
-6.6
-14.5
-5.5
-5.6
-4.3
-5.7
-9.4
-9.7
-1.6
-2.2
-3.7
-3.8
-3.4
-4.5
-7.7
-7.9
-7.8
-10.3
-16.6
-17.0
Device Operation
INPUT INTERFACING
The DS25BR100/101 accepts differential signals and allows simple AC or DC coupling. With a wide common
mode range, the DS25BR100/101 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS,
CML). The following three figures illustrate typical DC-coupled interface to common differential drivers.
The DS25BR100 inputs are internally terminated with a 100Ω resistor for optimal device performance, reduced
component count, and minimum board space. External input terminations on the DS25BR101 need to be placed
as close as possible to the device inputs to achieve equivalent AC performance. It is recommended to use SMT
resistors sized 0402 or smaller and to keep the mounting distance to the DS25BR101 pins under 200 mils.
When using the DS25BR101 in a limited multi-drop topology, any transmission line stubs should be kept very
short to minimize any negative effects on signal quality. A single termination resistor or resistor network that
matches the differential line impedance should be used. If DS25BR101 input pairs from two separate devices are
to be connected to a single differential output, it is recommended to mount the DS25BR101 devices directly
opposite of each other. One on top of the PCB and the other directly under the first on the bottom of the PCB
keeps the distance between inputs equal to the PCB thickness.
100W Differential T-Line
OUT+
IN+
LVDS
DS25BR100
IN-
OUT-
Figure 19. Typical LVDS Driver DC-Coupled Interface to DS25BR100 Input
CML3.3V or CML2.5V
V
CC
50W
50W
100W Differential T-Line
OUT+
OUT-
IN+
IN-
DS25BR100
Figure 20. Typical CML Driver DC-Coupled Interface to DS25BR100 Input
Copyright © 2007–2013, Texas Instruments Incorporated
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11
Product Folder Links: DS25BR100
DS25BR100
SNLS217F –MARCH 2007–REVISED APRIL 2013
www.ti.com
LVPECL
Driver
LVDS
Receiver
100W Differential T-Line
IN+
IN-
OUT+
100W
OUT-
150-250W
150-250W
Figure 21. Typical LVPECL Driver DC-Coupled Interface to DS25BR100 Input
NOTE
DS25BR101 requires external 100Ω input termination.
OUTPUT INTERFACING
The DS25BR100/101 outputs signals are compliant to the LVDS standard. It can be DC-coupled to most
common differential receivers. The following figure illustrates the typical DC-coupled interface to common
differential receivers and assumes that the receivers have high impedance inputs. While most differential
receivers have a common mode input range that can accommodate LVDS compliant signals, it is recommended
to check the respective receiver's datasheet prior to implementing the suggested interface implementation.
100W Differential T-Line
OUT+
IN+
CML or
LVPECL or
LVDS
DS25BR100
100W
IN-
OUT-
Figure 22. Typical Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
12
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS25BR100
DS25BR100
www.ti.com
SNLS217F –MARCH 2007–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision E (April 2013) to Revision F
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 12
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: DS25BR100
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS25BR100TSD/NOPB
DS25BR101TSD/NOPB
DS25BR101TSDE/NOPB
DS25BR101TSDX/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
NGQ
NGQ
NGQ
NGQ
8
8
8
8
1000 RoHS & Green
1000 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
2R100
SN
SN
SN
2R101
2R101
2R101
250
RoHS & Green
4500 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS25BR100TSD/NOPB WSON
DS25BR101TSD/NOPB WSON
DS25BR101TSDE/NOPB WSON
DS25BR101TSDX/NOPB WSON
NGQ
NGQ
NGQ
NGQ
8
8
8
8
1000
1000
250
178.0
178.0
178.0
330.0
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.0
1.0
1.0
1.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
4500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS25BR100TSD/NOPB
DS25BR101TSD/NOPB
DS25BR101TSDE/NOPB
DS25BR101TSDX/NOPB
WSON
WSON
WSON
WSON
NGQ
NGQ
NGQ
NGQ
8
8
8
8
1000
1000
250
208.0
208.0
208.0
356.0
191.0
191.0
191.0
356.0
35.0
35.0
35.0
35.0
4500
Pack Materials-Page 2
PACKAGE OUTLINE
NGQ0008A
WSON - 0.8 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
0.8
0.7
SEATING PLANE
0.08 C
1.6 0.1
SYMM
(0.1) TYP
0.05
0.00
EXPOSED
THERMAL PAD
4
5
8
SYMM
9
2X
2
0.1
1.5
1
6X 0.5
0.3
0.2
8X
0.1
C A B
C
0.5
0.3
PIN 1 ID
8X
0.05
4214922/A 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
NGQ0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
SYMM
8X (0.6)
1
8
(0.75)
8X (0.25)
9
SYMM
(2)
6X (0.5)
5
4
(R0.05) TYP
(
0.2) VIA
TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214922/A 03/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
NGQ0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.6)
SYMM
METAL
TYP
9
8
1
8X (0.25)
SYMM
(1.79)
6X (0.5)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 9:
82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4214922/A 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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