DS280MB810ZBLT_技术文档

DS280MB810

ZHCSKE4C –OCTOBER 2016 –REVISED DECEMBER 2020

DS280MB810 具有交叉点的低功耗28Gbps 8 通道线性中继器

附加抖动特性，该器件适用于 100G-SR4/LR4/CR4 等

前端接口。8mm x 13mm 小型封装适用于 QSFP、

SFP、CFP 和 CDFP 等多种标准前端口连接器，并且

无需散热器。

1 特性

• 支持高达28Gbaud NRZ 接口的八通道多协议线性

均衡器

• 具有引脚或寄存器控制的集成2x2 交叉点，适用于

多路复用器、扇出和信号交叉应用

• 低功耗：93mW/通道（典型值）

• 无需散热器

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

封装

DS280MB810

nFBGA (135)

8.0mm x 13.0mm

• 无缝支持链路协商、自动协商和前向纠错(FEC) 直

通功能的直线均衡

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 频率为14GHz 时，可将信道范围扩展17dB+，超

出常规ASIC-to-ASIC 功能

RX0P

RX0N

TX0P

TX0N

• 超低延迟：100ps（典型值）

• 低附加随机抖动

• 采用集成RX 交流耦合电容的8mm x 13mm BGA

小封装，适用于简易直通布线

• 独特引脚可实现在封装下方布置高速信号布线

• 提供交叉点的兼容引脚重定时器

• 2.5V ±5% 单电源

X

RX1P

TX1P

TX1N

.

RX1N

.

RX6P

RX6N

TX6P

TX6N

X

RX7P

RX7N

TX7P

TX7N

VDD

• 工作温度范围：–40°C 至+85°C

SDA⁽¹⁾

SDC⁽¹⁾

To system SMBus

1 kΩ

SMBus

Slave mode

ADDR0

ADDR1

Address straps

(pull-up, pull-down, or float)

2 应用

EN_SMB

• 背板和中板信号分配和均衡

• 实现故障转移冗余的多路复用器和多路信号分离器

• 前端口眼开口和信号分配，适用于端口之间的转换

SMBus Slave

mode

Float for SMBus Slave

READ_EN_N

VDD

ALL_DONE_N

GND

mode, or connect to next

device‘s READ_EN_N for

SMBus Master mode

2.5 V

1 ꢀF

(2x)

0.1 ꢀF

(4x)

3 说明

(1) SMBus signals need to be pulled up elsewhere in the system.

DS280MB810 是一款超低功耗、高性能八通道线性均

衡器，支持数据传输速率高达 28Gbaud NRZ 的多速

率、多协议接口。该器件可用于扩展长度范围并提高背

板、前端口和芯片间应用的高速串行链路的稳健性。

简化原理图

DS280MB810 在每对相邻通道之间都具有一个完整的

2x2 交叉点开关，支持 2 到 1 多路复用和 1 到 2 多路

分解应用，可实现故障转移冗余，以及有助于 PCB 布

线的信号交叉。交叉点可通过引脚或 SMBus 寄存器接

口进行控制。

DS280MB810 均衡的线性特质保留了发射信号的特

性，因此允许主机与链路合作伙伴ASIC 自由协商发射

均衡器系数 (100G-CR4/KR4)。这种链路协商协议的透

明管理有助于在对延迟影响最小的情况下实现系统级互

操作性。DS280MB810 支持两级脉冲振幅调制 (PAM)

或NRZ，可在线性工作范围内提供高达28Gbaud 的符

号速率和峰间信号振幅。

每条通道独立运行，并且可以单独配置。在大多数应用

场景中，无论数据速率如何，都可以使用相同的配置。

DS280MB810 将小型封装尺寸、经优化的高速信号退

出和引脚兼容的重定时器相结合，使其成为高密度背板

应用的理想之选。凭借简化的均衡控制、低功耗和超低

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNLS542

DS280MB810

ZHCSKE4C –OCTOBER 2016 –REVISED DECEMBER 2020

www.ti.com.cn

Table of Contents

8.4 Device Functional Modes..........................................18

8.5 Programming............................................................ 20

8.6 Register Maps...........................................................21

9 Application and Implementation..................................32

9.1 Application Information............................................. 32

9.2 Typical Application.................................................... 32

9.3 Initialization Set Up................................................... 43

10 Power Supply Recommendations..............................43

11 Layout...........................................................................45

11.1 Layout Guidelines................................................... 45

11.2 Layout Examples.....................................................45

12 Device and Documentation Support..........................48

12.1 Documentation Support.......................................... 48

12.2 Receiving Notification of Documentation Updates..48

12.3 Support Resources................................................. 48

12.4 Trademarks.............................................................48

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Description (continued).................................................. 3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 7

7.1 Absolute Maximum Ratings........................................ 7

7.2 ESD Ratings............................................................... 7

7.3 Recommended Operating Conditions.........................7

7.4 Thermal Information....................................................8

7.5 Electrical Characteristics.............................................8

7.6 Timing Requirements –Serial Management

Bus Interface............................................................... 13

7.7 Typical Characteristics..............................................14

8 Detailed Description......................................................15

8.1 Overview...................................................................15

8.2 Functional Block Diagram.........................................15

8.3 Feature Description...................................................16

Information.................................................................... 49

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (October 2019) to Revision C (December 2020)

Page

• 更改了数据速率支持，提示仅支持 NRZ.............................................................................................................1

• 删除了对 PAM4 28 GBd 接口的支持.................................................................................................................. 1

Changes from Revision A (September 2017) to Revision B (October 2019)

Page

• 首次公开发布......................................................................................................................................................1

English Data Sheet: SNLS542

2

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5 Description (continued)

Integrated AC coupling capacitors (RX side) eliminate the need for external capacitors on the PCB. The

DS280MB810 has a single power supply and minimal need for external components. These features reduce

PCB routing complexity and bill of materials (BOM) cost.

A pin-compatible Retimer device with cross-point is available for longer reach applications.

The DS280MB810 can be configured either through the SMBus or through an external EEPROM. Up to 16

devices can share a single EEPROM.

6 Pin Configuration and Functions

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Legend

J

H

G

F

GND

TX1N

GND

TX2N

GND

TX3N

GND

TX4N

GND

TX5N

GND

TX6N

GND

J

H

G

F

GND

VDD

Ground pin

TX0N

TX0P

GND

TX1P

GND

SDC

TX2P

GND

RX2P

GND

VDD

GND

TX3P

GND

VDD

GND

VDD

GND

TX4P

GND

VDD

GND

VDD

GND

TX5P

GND

VDD

GND

TX6P

GND

TX7N

TX7P

GND

High-speed pin

Power pin

READ_

EN_N

INT_N

(NC)

Control/Status pin

CAL_

CLK_

OUT

CAL_

CLK_

IN

EN_SM

B

No connect on

package

MUXSEL1

_TEST1

MUXSEL0

_TEST0

E

D

C

B

A

ADDR1 SDA

E

D

C

B

A

ALL_

GND

RX0P

RX0N

GND ADDR0 GND

GND

RX3P

GND

RX4P

GND

RX5P

GND DONE_ GND

N

GND

RX7P

RX7N

GND

RX1P

RX6P

GND

15

GND

14

RX1N

13

GND

12

RX2N

11

GND

10

RX3N

9

GND

8

RX4N

7

GND

6

RX5N

5

GND

4

RX6N

3

GND

2

GND

1

图6-1. Top View

表6-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

High Speed Differential I/O

RX0P

RX0N

RX1P

RX1N

RX2P

RX2N

RX3P

RX3N

RX4P

RX4N

C15

B15

B13

A13

B11

A11

B9

Input

Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ωtermination

resistor connects RXP to RXN. These inputs are AC coupled with 220 nF capacitors

assembled on the package substrate.

Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ωtermination

resistor connects RXP to RXN. These inputs are AC coupled with 220 nF capacitors

assembled on the package substrate.

Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ωtermination

resistor connects RXP to RXN. These inputs are AC coupled with 220 nF capacitors

assembled on the package substrate.

Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ωtermination

resistor connects RXP to RXN. These inputs are AC coupled with 220 nF capacitors

assembled on the package substrate.

A9

B7

Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ωtermination

resistor connects RXP to RXN. These inputs are AC coupled with 220 nF capacitors

assembled on the package substrate.

A7

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English Data Sheet: SNLS542

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ZHCSKE4C –OCTOBER 2016 –REVISED DECEMBER 2020

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表6-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

RX5P

B5

Input

Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ωtermination

resistor connects RXP to RXN. These inputs are AC coupled with 220 nF capacitors

assembled on the package substrate.

RX5N

RX6P

RX6N

RX7P

RX7N

A5

B3

A3

C1

B1

Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ωtermination

resistor connects RXP to RXN. These inputs are AC coupled with 220 nF capacitors

assembled on the package substrate.

Inverting and non-inverting differential inputs to the equalizer. An on-chip 100-Ωtermination

resistor connects RXP to RXN. These inputs are AC coupled with 220 nF capacitors

assembled on the package substrate.

TX0P

TX0N

TX1P

TX1N

TX2P

TX2N

TX3P

TX3N

TX4P

TX4N

TX5P

TX5N

TX6P

TX6N

TX7P

TX7N

G15

H15

H13

J13

H11

J11

H9

J9

Output

Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential

inputs.

Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential

inputs.

Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential

inputs.

Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential

inputs.

H7

J7

Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential

inputs.

H5

J5

Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential

inputs.

H3

J3

Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential

inputs.

G1

H1

Inverting and non-inverting 50-Ω driver outputs. Compatible with AC-coupled differential

inputs.

Calibration Clock Pins (For Supporting Upgrade Path to Pin-Compatible Retimer Device)

25-MHz (±100 PPM) 2.5-V single-ended clock from external oscillator. No stringent phase

noise or jitter requirements on this clock. A 25-MHz input clock is only required if there is

a need to support a future upgrade to the pin-compatible Retimer device. If there is no

need to support a future upgrade to a pin-compatible Retimer device, then a 25-MHz clock is

not required. This input pin has a weak active pull down and can be left floating if the

CAL_CLK feature is not required.

CAL_CLK_IN

E1

Input

CAL_CLK_

OUT

2.5-V buffered replica of calibration clock input (pin E1) for connecting multiple devices in a

daisy-chained fashion.

E15

Output

System Management Bus (SMBus) Pins

ADDR0

D13

E13

Input, 4-Level 4-level strap pins used to set the SMBus address of the device. The pin state is read on

power-up. The multi-level nature of these pins allows for 16 unique device addresses, see 表

8-1. The four strap options include:

0: 1 kΩ to GND

R: 10 kΩ to GND

ADDR1

Input, 4-Level

F: Float

1: 1 kΩ to VDD

4-level 2.5-V input used to select between SMBus master mode (float) and SMBus slave

mode (high). The four defined levels are:

0: 1 kΩ to GND - RESERVED

R: 10 kΩ to GND - RESERVED, TI test mode

F: Float - SMBus master mode

EN_SMB

SDA

E3

Input, 4-Level

1: 1 kΩ to VDD - SMBus slave mode

I/O, 3.3 V

LVCMOS,

SMBus data input or open drain output. External 2-kΩ to 5-kΩ pull-up resistor is required.

This pin is 3.3-V LVCMOS tolerant.

Open Drain

E12

English Data Sheet: SNLS542

4

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表6-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

I/O, 3.3 V

LVCMOS,

Open Drain

SMBus clock input or open drain clock output. External 2-kΩ to 5-kΩ pull-up resistor is

required. This pin is 3.3-V LVCMOS tolerant.

SDC

F12

SMBus master mode (EN_SMB = Float): When asserted low, initiates the SMBus master

mode EEPROM read function. Once EEPROM read is complete (indicated by assertion of

ALL_DONE_N low), this pin can be held low for normal device operation.

Input, 3.3 V

LVCMOS

READ_EN_N

F13

SMBus slave mode (EN_SMB = 1 kΩto VDD): When asserted low, this causes the device

to be held in reset (SMBus state machine reset and register reset). This pin should be pulled

high or left floating for normal operation in SMBus slave mode.

This pin has an internal weak pull-up and is 3.3-V LVCMOS tolerant.

Indicates the completion of a valid EEPROM register load operation when in SMBus master

mode (EN_SMB = Float):

High = External EEPROM load failed or incomplete.

Low = External EEPROM load successful and complete.

ALL_DONE_

N

Output,

LVCMOS

D3

When in SMBus slave mode (EN_SMB = 1 kΩto VDD), this output will be high-Z until

READ_EN_N is driven low, at which point ALL_DONE_N will be driven low. This behavior

allows the reset signal connected to READ_EN_N of one device to propagate to the

subsequent devices when ALL_DONE_N is connected to READ_EN_N in an SMBus slave

mode application.

Miscellaneous Pins

No connect on package. For applications using DS280MB810 and pin-compatible TI

Retimers, this pin can be connected to other devices’INT_N pins. This is a

recommendation for cases where there is a need to support a potential future upgrade to the

pin-compatible Retimer device, which uses this pin as an interrupt signal to a system

controller.

No connect in

package

INT_N

F3

MUXSEL0_

TEST0

Input,

LVCMOS

When operating the cross-point in pin-control mode (Shared Reg_0x05[1]=1), MUXSEL0

controls the cross-point for channels 0–1 and 4–5, and MUXSEL1 controls the cross-point

for channels 2–3 and 6–7.

E2

If these pins are not used for cross-point control, they may be left floating or tied to GND.

These pins also serve as TI test pins when in test mode (EN_SMB = 10 kΩto GND).

These pins have an internal weak pull-up.

MUXSEL1_

TEST1

Input,

LVCMOS

E14

Power

Power supply, VDD = 2.5 V +/- 5%. Use at least six de-coupling capacitors between the

Repeater’s VDD plane and GND as close to the Repeater as possible. For example, four

0.1-μF capacitors and two 1-μF capacitors directly beneath the device or as close to the

VDD pins as possible. The VDD pins on this device should be connected through a low-

resistance path to the board VDD plane. For more information, see 节10.

D6, D8, D10,

E5, E6, E7,

E8, E9, E10,

F6, F8, F10

VDD

Power

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English Data Sheet: SNLS542

DS280MB810

ZHCSKE4C –OCTOBER 2016 –REVISED DECEMBER 2020

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表6-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

A1, A2, A4,

A6, A8, A10,

A12, A14,

A15, B2, B4,

B6, B8, B10,

B12, B14, C2,

C3, C4, C5,

C6, C7, C8,

C9, C10, C11,

C12, C13,

C14, D1, D2,

D4, D5, D7,

D9, D11, D12,

D14, D15, E4,

E11, F1, F2,

F4, F5, F7,

Ground reference. The GND pins on this device should be connected through a low-

impedance path to the board GND plane.

GND

Power

F9, F11, F14,

F15, G2, G3,

G4, G5, G6,

G7, G8, G9,

G10, G11,

G12, G13,

G14, H2, H4,

H6, H8, H10,

H12, H14, J1,

J2, J4, J6, J8,

J10, J12, J14,

J15

6

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English Data Sheet: SNLS542

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ZHCSKE4C –OCTOBER 2016 –REVISED DECEMBER 2020

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7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted). ⁽¹⁾

MIN

-0.5

MAX

2.75

UNIT

V

VDD_ABSMAX

Supply voltage (VDD)

VIO_2.5V,ABSMAX

2.5 V I/O voltage (LVCMOS and CMOS)

V

Open drain and 3.3 V-tolerance I/O voltage (SDA,

SDC, READ_EN_N)

VIO_3.3V,ABSMAX

-0.5

4.0

V

VIO_HS,ABSMAX

TJ_ABSMAX

T_stg

High-speed I/O voltage (RXnP, RXnN, TXnP, TXnN)

Junction temperature

2.75

150

V

°C

Storage temperature range

-40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾

±1500

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101

±1000

(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2 kV

may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted).

MIN

NOM

MAX

UNIT

DC plus AC power should not

exceed these limits

VDD

Supply voltage, VDD to GND

Supply noise tolerance ⁽¹⁾

2.375

2.5

2.625

V

Supply noise, DC to <50 Hz,

sinusoidal

250

20

mVpp

Supply noise, 50 Hz to 10 MHz,

sinusoidal

N_VDD

Supply noise, >10 MHz,

sinusoidal

10

T_RampVDD

VDD supply ramp time

From 0 V to 2.375 V

150

-40

µs

C

T_J

Operating junction temperature

Operating ambient temperature

110

85

T_A

C

SMBus SDA and SDC Open

Drain Termination Voltage

Supply voltage for open drain

pull-up resistor

VDD_SMBUS

F_SMBus

3.6

V

SMBus clock (SDC) frequency in

SMBus slave mode

400

kHz

(1) Sinusoidal noise is superimposed to supply voltage with negligible impact to device function or critical performance shown in the

Electrical Table.

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English Data Sheet: SNLS542

DS280MB810

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7.4 Thermal Information

DS280MB810

nFBGA

135 PINS

45.2

THERMAL METRIC⁽¹⁾

CONDITIONS/ASSUMPTIONS⁽²⁾

UNIT

4-Layer JEDEC Board

10-Layer 8-in x 6-in Board

20-Layer 8-in x 6-in Board

30-Layer 8-in x 6-in Board

4-Layer JEDEC Board

26.3

R_θJA

Junction-to-ambient thermal resistance

°C/W

24.8

22.7

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

26.6

°C/W

4-Layer JEDEC Board

25.8

4-Layer JEDEC Board

13.3

10-Layer 8-in x 6-in Board

20-Layer 8-in x 6-in Board

30-Layer 8-in x 6-in Board

4-Layer JEDEC Board

13.0

Junction-to-top characterization parameter

Junction-to-board characterization parameter

°C/W

Ψ_JT

13.0

22.8

10-Layer 8-in x 6-in Board

20-Layer 8-in x 6-in Board

30-Layer 8-in x 6-in Board

21.4

Ψ_JB

21.1

20.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) No heat sink or airflow was assumed for these estimations. Depending on the application, a heat sink, faster airflow, or reduced

ambient temperature (<85 C) may be required in order to meet the maximum junction temperature specification per the 节7.3.

7.5 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

82

MAX

109 ⁽¹⁾

100 ⁽¹⁾

UNIT

mW

POWER

Channel enabled with maximum driver

VOD (DRV_SEL_VOD = 3).

Static power consumption not

included.

W_channel

Power consumption per active channel

Channel enabled with minimum driver

VOD (DRV_SEL_VOD = 0).

Static power consumption not

included.

75

mW

Channel enabled, cross-point enabled,

and maximum driver VOD

(DRV_SEL_VOD = 3).

Static power consumption not

included.

82

75

109 ⁽¹⁾

mW

Power consumption per active

channel, cross-point enabled

W_{channel_CP}

Channel enabled, cross-point enabled,

and minimum driver VOD

(DRV_SEL_VOD = 0).

100 ⁽¹⁾

Static power consumption not

included.

English Data Sheet: SNLS542

8

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Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Channel enabled, fanout enabled, and

maximum driver VOD

(DRV_SEL_VOD = 3).

Static power consumption not

included.

69

95 ⁽¹⁾

mW

Power consumption per active

channel, fanout enabled

W_{channel_FO}

Channel enabled, fanout enabled, and

minimum driver VOD (DRV_SEL_VOD

= 0).

61

86 ⁽¹⁾

mW

Static power consumption not

included.

Idle (static) mode total device power

consumption

Channels disabled and powered down

(DRV_PD = 1, EQ_PD = 1).

W_{static_total}

110

307

173 ⁽¹⁾

389

mW

mA

All channels enabled with maximum

driver VOD

(DRV_SEL_VOD = 3).

Active mode total device supply

current consumption

I_total

All channels enabled with minimum

driver VOD

283

307

283

264

240

44

361

389

361

346

318

66

mA

(DRV_SEL_VOD = 0).

All channels enabled, cross-point

enabled, and maximum driver VOD

(DRV_SEL_VOD = 3).

Active mode total device supply

current consumption, cross-point

enabled

I_{total_CP}

All channels enabled, cross-point

enabled, and minimum driver VOD

(DRV_SEL_VOD = 0).

All channels enabled, fanout enabled,

and maximum driver VOD

(DRV_SEL_VOD = 3).

Active mode total device supply

current consumption, fanout enabled

I_{total_FO}

All channels enabled, fanout enabled,

and minimum driver VOD

(DRV_SEL_VOD = 0).

All channels disabled and powered

down

(DRV_PD = 1, EQ_PD = 1).

Idle (static) mode total device supply

current consumption

I_{static_total}

LVCMOS DC SPECIFICATIONS (CAL_CLK_IN, CAL_CLK_OUT, READ_EN_N, ALL_DONE_N, MUXSEL[1:0])

1.75

VDD

3.6

V

V_IH

High level input voltage

READ_EN_N pin only

1.75

GND

2

V_IL

Low level input voltage

High level output voltage

Low level output voltage

0.7

V

V_OH

V_OL

IOH = 4 mA

V

IOL = -4 mA

0.4

16

66

1

V

Vinput = VDD, MUXSEL[1:0] pins

Vinput = VDD, CAL_CLK_IN pin

Vinput = VDD, READ_EN_N pin ⁽²⁾

Vinput = 0 V, MUXSEL[1:0] pins

Vinput = 0 V, CAL_CLK_IN pin ⁽³⁾

Vinput = 0 V, READ_EN_N pin ⁽²⁾

µA

I_IH

Input high leakage current

Input low leakage current

-38

-1

I_IL

-55

4-LEVEL LOGIC ELECTRICAL SPECIFICATIONS (APPLIES TO 4-LEVEL INPUT CONTROL PINS ADDR0, ADDR1, and EN_SMB)

I_IH

I_IL

Input high leakage current

Input low leakage current

105

µA

-253

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Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0.95 *

VDD

High level (1) input voltage

Float level input voltage

V

0.67 *

VDD

V

V_TH

0.33 *

VDD

10 K to GND input voltage

Low level (0) input voltage

V

0.1

HIGH-SPEED DIFFERENTIAL INPUTS (RXnP, RXnN)

Measured with maximum CTLE setting

and maximum BW setting (EQ_BST1

= 7, EQ_BST2 = 7, EQ_BW = 3).

Boost is defined as the gain at 14 GHz

relative to 20 MHz.

25.6

dB

BST

CTLE high-frequency boost

CTLE high-frequency gain variation

Measured with maximum CTLE setting

and maximum BW setting (EQ_BST1

= 7, EQ_BST2 = 7, EQ_BW = 3).

Boost is defined as the gain at 12.9

GHz relative to 20 MHz.

25.3

2.4

Measured with minimum CTLE setting

and minimum BW setting (EQ_BST1 =

0, EQ_BST2 = 0, EQ_BW = 0,

EQ_EN_BYPASS = 1). Boost is

defined as the gain at 14 GHz relative

to 20 MHz.

dB

BST

Measured with minimum CTLE setting

and minimum BW setting (EQ_BST1 =

0, EQ_BST2 = 0, EQ_BW = 0,

EQ_EN_BYPASS = 1). Boost is

defined as the gain at 12.9 GHz

relative to 20 MHz.

2.4

Measured with maximum CTLE setting

(EQ_BST1 = 7, EQ_BST2 = 7). Gain

variation is defined as the total change

in gain at 14 GHz due to temperature

and voltage variation.

< 3

dB

BST_delta

Measured with maximum CTLE setting

(EQ_BST1 = 7, EQ_BST2 = 7). Gain

variation is defined as the total change

in gain at 12.9 GHz due to

temperature and voltage variation.

Measured with minimum CTLE setting

(EQ_BST1 = 0, EQ_BST2 = 0,

EQ_EN_BYPASS = 1). Gain variation

is defined as the total change in gain

at 14 GHz due to temperature and

voltage variation.

< 2

dB

BST_delta

CTLE high-frequency gain variation

Measured with minimum CTLE setting

(EQ_BST1 = 0, EQ_BST2 = 0,

EQ_EN_BYPASS = 1). Gain variation

is defined as the total change in gain

at 12.9 GHz due to temperature and

voltage variation.

50 MHz to 3.7 GHz

3.7 GHz to 10 GHz

10 GHz to 14.1 GHz

14.1 GHz to 20 GHz

< -14

< -12

< -8

dB

RL_SDD11

Input differential return loss

< -6

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Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

100 MHz to 3.3 GHz

3.3 GHz to 12.9 GHz

12.9 GHz to 20 GHz

100 MHz to 10 GHz

10 GHz to 20 GHz

MIN

TYP

< -35

< -26

< -22

< -7

MAX

UNIT

dB

Input differential-to-common-mode

return loss

RL_SDC11

dB

RL_SCC11

Input common-mode return loss

< -8

dB

Minimum input peak-to-peak amplitude

level at device pins required to assert

signal detect. 25.78125 Gbps with

PRBS7 pattern and 20 dB loss

channel.

AC signal detect assert (ON)

differential voltage threshold level

V_SDAT

196

147

mVpp

Maximum input peak-to-peak

amplitude level at device pins which

causes signal detect to de-assert.

25.78125 Gbps with PRBS7 pattern

and 20 dB loss channel.

AC signal detect de-assert (OFF)

differential voltage threshold level

V_SDDT

Measured with the highest wide-band

gain setting (EQ_HIGH_GAIN = 1,

DRV_SEL_VOD = 3). Measured with

minimal input channel and minimum

EQ using a 1 GHz signal.

850

Measured with a mid wide-band gain

setting (EQ_HIGH_GAIN = 1,

DRV_SEL_VOD = 0). Measured with

minimal input channel and minimum

EQ using a 1 GHz signal.

900

Input amplitude linear range. The

maximum VID for which the repeater

remains linear, defined as ≤1 dB

compression of Vout/Vin.

VID_linear

Measured with a mid wide-band gain

setting (EQ_HIGH_GAIN = 0,

DRV_SEL_VOD = 3). Measured with

minimal input channel and minimum

EQ using a 1 GHz signal.

1050

1250

Measured with the lowest wide-band

gain setting (EQ_HIGH_GAIN = 0,

DRV_SEL_VOD = 0). Measured with

minimal input channel and minimum

EQ using a 1 GHz signal.

HIGH-SPEED DIFFERENTIAL OUTPUTS (TXnP, TXnN)

Differential output amplitude, TX

VOD_idle

< 10

4.5

mVpp

dB

disabled or otherwise muted

Measured with the highest wide-band

gain setting (EQ_HIGH_GAIN = 1,

DRV_SEL_VOD = 3) at 20 MHz.

G_DC

Vout/Vin wide-band amplitude gain

Measured with the lowest wide-band

gain setting (EQ_HIGH_GAIN = 0,

DRV_SEL_VOD = 0) at 20 MHz.

-5

dB

Defined as (TXP + TXN)/2. Measured

with a low-pass filter with 3 dB

bandwidth at 33 GHz.

V_cm-TX-AC

Common-mode AC output noise

Common-mode DC output

6

mV, RMS

V

Defined as (TXP + TXN)/2. Measured

with a DC signal.

V_cm-TX-DC

0.75

0.96

1.05

Measured as a single-ended signal on

a Keysight E5505A phase noise

measurement solution with a 28 Gbps

1010 pattern. Additive RJ measured

over a frequency range of 2 kHz to 20

MHz.

RJ_ADD-RMS

Additive Random Jitter

11

fs RMS

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Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

50 MHz to 4.8 GHz

4.8 GHz to 10 GHz

10 GHz to 14.1 GHz

14.1 GHz to 20 GHz

50 MHz to 6.0 GHz

6.0 GHz to 12.9 GHz

12.9 GHz to 14.1 GHz

14.1 GHz to 20 GHz

50 MHz to 3.3 GHz

3.3 GHz to 10.3 GHz

10.3 GHz to 20 GHz

MIN

TYP

< -16

< -15

< -8

MAX

UNIT

dB

Output differential-to-differential return

loss

RL_SDD22

< -8

< -21

< -22

< -21

< -20

< -13

< -11

< -9

Output common-mode-to-differential

return loss

RL_SCD22

RL_SCC22

Output Common-mode return loss

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Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OTHER PARAMETERS

Input-to-output latency (propagation

delay) through a channel

t_D

Straight-thru mode (no cross-point)

100

ps

Input-to-output latency (propagation

delay) through a channel

Cross-over and mux mode (cross-

point enabled)

t_D

100

<14

ps

t_SK

Channel-to-channel interpair skew

Latency difference between channels

Time to assert ALL_DONE_N after

REAN_EN_N has been asserted.

Single device reading its configuration

from an EEPROM with common

channel configuration. This time scales

with the number of devices reading

from the same EEPROM. Does not

include power-on reset time.

4

ms

T_EEPROM

EEPROM configuration load time

Time to assert ALL_DONE_N after

REAN_EN_N has been

asserted. Single device reading its

configuration from an EEPROM. Non-

common channel configuration. This

time scales with the number of devices

reading from the same EEPROM.

Does not include power-on reset time.

7

ms

Internal power-on reset (PoR) stretch

between stable power supply and de-

assertion of internal PoR. The SMBus

address is latched on the completion

of the PoR stretch, and SMBus

accesses are permitted once PoR

completes.

T_POR

Power-on reset assertion time

60

(1) Max values assume VDD = 2.5 V + 5%.

(2) This pin has an internal weak pull-up.

(3) This pin has an internal weak pull-down.

表7-1. Electrical Characteristics –Serial Management Bus Interface

PARAMETER

TEST CONDITIONS

MIN

1.75

GND

TYP

MAX

3.6

UNIT

V

V_IH

V_IL

Input high level voltage

Input low level voltage

Output low level voltage

Input pin capacitance

SDA and SDC

0.8

V

V_OL

C_IN

SDA and SDC, I_OL= 1.25 mA

SDA and SDC

0.4

V

15

pF

SDA or SDC, VINPUT = VIN, VDD,

GND

I_IN

Input current

-18

18

µA

7.6 Timing Requirements –Serial Management Bus Interface

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RECOMMENDED SMBus SWITCHING CHARACTERISTICS (SMBus SLAVE MODE)

f_SDC

SDC clock frequency

Data hold time

EN_SMB = 1k to VDD (Slave Mode)

10

100

0.75

100

150

4.5

400

kHz

ns

T_SDA-HD

T_SDA-SU

T_SDA-R

T_SDA-F

Data setup time

ns

SDA rise time, read operation

SDA fall time, read operation

ns

Pull-up resistor = 1 kΩ, Cb = 50 pF

ns

SMBus SWITCHING CHARACTERISTICS (SMBus MASTER MODE)

f_SDC

SDC clock frequency

EN_SMB = Float (Master Mode)

260

303

346

kHz

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Over operating free-air temperature range (unless otherwise noted).

PARAMETER

T_SDC-LOW

T_SDC-HIGH

T_HD-START

T_SU-START

T_SDA-HD

TEST CONDITIONS

MIN

1.66

1.22

TYP

1.90

1.40

0.6

MAX

2.21

1.63

UNIT

µs

SDC low period

SDC high period

µs

Hold time start operation

Setup time start operation

Data hold time

µs

0.6

µs

0.9

µs

T_SDA-SU

Data setup time

0.1

µs

T_SU-STOP

T_BUF

Stop condition setup time

Bus free time between Stop-Start

SDC rise time

0.6

µs

1.3

µs

T_SDC-R

300

ns

Pull-up resistor = 1 kΩ

T_SDC-F

SDC fall time

ns

7.7 Typical Characteristics

CTLE Low Gain Mode

CTLE High Gain Mode

1.40

1.20

1.00

0.80

0.60

0.40

0.20

0.00

1.40

1.20

1.00

0.80

0.60

0.40

0.20

0.00

VOD = 3

VOD = 0

0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

Differential Input Voltage (V_P-P

)

Differential Input Voltage (V_P-P

)

图7-1. Typical Vin/Vout Linearity (straight-thru

图7-2. Typical Vin/Vout Linearity (straight-thru

mode)

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8 Detailed Description

8.1 Overview

The DS280MB810 is an eight-channel multi-rate linear repeater with integrated signal conditioning and cross-

point. The eight channels operate independently from one another. Each channel includes a continuous-time

linear equalizer (CTLE), multiplexer, and a linear output driver, which compensate for the presence of a

dispersive transmission channel between the source transmitter and the final receiver.

Between each group of two adjacent channels (i.e. between channels 0–1, 2–3, 4–5, and 6–7) is a full 2x2

cross-point switch. This allows multiplexing and de-multiplexing or fanout applications for failover redundancy, as

well as cross-over applications to aid PCB routing.

All receive channels on the DS280MB810 are AC-coupled with physical AC coupling capacitors (220 nF ±20%)

on the package substrate. This ensures input common mode voltage compatibility with all link partner

transmitters and eliminates the need for AC coupling capacitors on the system PCB, thereby saving cost and

greatly reducing PCB routing complexity.

The DS280MB810 is configurable through a single SMBus port. The DS280MB810 can also act as an SMBus

master to configure itself from an EEPROM.

The sections which follow describe the functionality of various circuits and features within the DS280MB810. For

more information about how to program or operate these features refer to the DS280MB810 Programming

Guide.

8.2 Functional Block Diagram

One of Eight Channels

Term

Bypass

Straight-thru Path

Crosspoint Path

RXnP

RXnN

TXnP

TXnN

Boost

Stage 1

Boost

Stage 2

Driver

220 nF

Signal

Detect

Voltage

Regulator

Mux select

(crosspoint)

To adjacent

channel

Signal from

adjacent channel

Channel Digital Core

ADDRn

SCL

SDA

Power-On

Reset

Shared Digital Core

Always-On 10 MHz

READ_EN_N

EN_SMB

ALL_DONE_N

CAL_CLK_OUT

MUXSEL0_TEST0

MUXSEL1_TEST1

CAL_CLK_IN

Buffer

Shared Digital Core (common to all channels)

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8.3 Feature Description

8.3.1 Device Data Path Operation

The DS280MB810 data path consists of several key blocks as shown in 节8.2. These key circuits are:

• 节8.3.2

• 节8.3.3

• 节8.3.4

• 节8.3.5

• 节8.3.6

• 节8.3.7

8.3.2 AC-coupled Receiver Inputs

The differential receiver for each DS280MB810 channel contains an integrated on-die 100 Ω differential

termination as well as 220 nF ±20% series AC coupling capacitors embedded onto the package substrate.

8.3.3 Signal Detect

Each DS280MB810 high speed receiver has a signal detect circuit which monitors the energy level on the inputs.

The signal detect circuit will enable the high-speed data path if a signal is detected, or power it off if no signal is

detected. By default, this feature is enabled, but can be manually controlled though the SMBus channel

registers. This can be useful if it is desired to manually force channels to be disabled. For information on how to

manually operate the signal detect circuit refer to the DS280MB810 Programming Guide.

8.3.4 2-Stage CTLE

The continuous-time linear equalizer (CTLE) in the DS280MB810 consists of two stages which are configurable

through the SMBus channel registers. This CTLE is designed to be highly linear to allow the DS280MB810 to

preserve the transmitter's pre-cursor and post cursor signal characteristics. This highly linear behavior enables

the DS280MB810 to be used in applications that use protocols such as link training, where it is important to

recover and pass through incremental changes in transmit equalization.

Each stage in the CTLE has 3-bit boost control. The first CTLE stage provides a coarse adjustment of the total

boost. Larger settings correspond to higher total boost. The first stage can be bypassed entirely to achieve the

lowest possible total boost. The second CTLE stage acts as a fine adjustment on the total boost and impacts the

shape of the boost curve accordingly. Larger settings correspond to higher total boost. The bandwidth of the

CTLE can be adjusted using a 2-bit bandwidth control. Larger settings correspond to higher total bandwidth. For

information on how to program the CTLE refer to the DS280MB810 Programming Guide.

In addition to high-frequency boost, the CTLE can apply wide-band amplitude gain. There are two settings (high-

gain and low-gain) which work together with the driver DC gain control to affect the total input-to-output wide-

band amplitude gain.

8.3.5 Driver DC Gain Control

In addition to the high-frequency boost provided by the CTLE, the DS280MB810 is also able to provide

additional DC or low-frequency gain. The effective DC gain is controlled by a 3-bit field, allowing for eight levels

of DC attenuation or DC gain. For information on how to configure the DC gain refer to the DS280MB810

Programming Guide.

8.3.6 2x2 Cross-point Switch

Between each group of two adjacent channels (i.e. between channels 0–1, 2–3, 4–5, and 6–7) is a full 2x2

cross-point switch. The cross-point can be configured through pin-mode (shared register 0x05[1]=1) or SMBus

registers (shared register 0x05[1]=0) to operate as follows:.

• Straight-thru mode

• Multiplex two inputs to one output

• Fanout one input to two outputs

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• Cross two inputs to two outputs

图 8-1 shows the four 2x2 cross-points available in the DS280MB810, and 图 8-2 shows how each cross-point

can be configured for straight-thru, multiplex, de-multiplex, or cross-over applications. Refer to the DS280MB810

Programming Guide for details on how to program the cross-point through SMBus registers.

RX0P

RX0N

TX0P

TX0N

X

RX1P

RX1N

TX1P

TX1N

RX2P

RX2N

TX2P

TX2N

X

RX3P

RX3N

TX3P

TX3N

RX4P

RX4N

TX4P

TX4N

RX5P

RX5N

TX5P

TX5N

RX6P

RX6N

TX6P

TX6N

RX7P

RX7N

TX7P

TX7N

图8-1. Block diagram showing all four 2x2 cross-points in the DS280MB810

Straight Thru

Mux / Fanout

RXAP

RXAN

TXAP

TXAN

RXAP

RXAN

TXAP

TXAN

RXBP

RXBN

TXBP

TXBN

RXBP

RXBN

TXBP

TXBN

Cross-over

Mux / Fanout

RXAP

RXAN

TXAP

TXAN

RXAP

RXAN

TXAP

TXAN

RXBP

RXBN

TXBP

TXBN

RXBP

RXBN

TXBP

TXBN

图8-2. Signal distribution options available in each 2x2 cross-point (channel A can be 0, 2, 4, or 6;

channel B can be 1, 3, 5, or 7)

The switching operation of the cross-point can be configured with the MUXSEL0 and MUXSEL1 pins when

shared register 0x05[1]=1. Note that shared register 0x05[1] of both quads must be set to 1 to enable pin-control

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cross-point mode. Each quad can be selected through Reg_0xFF[5:4]. Refer to the DS280MB810 Programming

Guide for more information.

The behavior of the cross-point (i.e. straight-thru, fanout, or mux) for each state of MUXSEL is illustrated in 图

8-3. Note that MUXSEL0 controls channels 0, 1, 4, and 5; and MUXSEL1 controls channels 2, 3, 6, and 7.

Channel A, Reg_0x07[5]=0

Channel B, Reg_0x07[5]=0

Channel A, Reg_0x07[5]=0

Channel B, Reg_0x07[5]=1

Channel A, Reg_0x07[5]=1

Channel B, Reg_0x07[5]=0

Channel A, Reg_0x07[5]=1

Channel B, Reg_0x07[5]=1

RXAP

RXAN

TXAP

TXAN

RXAP

RXAN

TXAP

TXAN

RXAP

RXAN

TXAP

TXAN

RXAP

RXAN

TXAP

TXAN

MUXSEL=0

RXBP

RXBN

TXBP

TXBN

RXBP

RXBN

TXBP

TXBN

RXBP

RXBN

TXBP

TXBN

RXBP

RXBN

TXBP

TXBN

Channel A, Reg_0x07[5]=0

Channel B, Reg_0x07[5]=0

Channel A, Reg_0x07[5]=0

Channel B, Reg_0x07[5]=1

Channel A, Reg_0x07[5]=1

Channel B, Reg_0x07[5]=0

Channel A, Reg_0x07[5]=1

Channel B, Reg_0x07[5]=1

RXAP

RXAN

TXAP

TXAN

RXAP

RXAN

TXAP

TXAN

RXAP

RXAN

TXAP

TXAN

RXAP

RXAN

TXAP

TXAN

MUXSEL=1

RXBP

RXBN

TXBP

TXBN

RXBP

RXBN

TXBP

TXBN

RXBP

RXBN

TXBP

TXBN

RXBP

RXBN

TXBP

TXBN

图8-3. Signal distribution configuration options when using pin-control mode (channel A can be 0, 2, 4,

or 6; channel B can be 1, 3, 5, or 7)

8.3.7 Configurable SMBus Address

The DS280MB810’s SMBus slave address is strapped at power up using the ADDR[1:0] pins. The pin state is

read on power up, after the internal power-on reset completes. The ADDR[1:0] pins are four-level LVCMOS I/Os,

which provide for 16 unique SMBus addresses. 表8-1 lists the DS280MB810 SMBus slave address options.

表8-1. SMBus Address Map

REQUIRED ADDRESS PIN STRAP VALUE

7-BIT SLAVE ADDRESS

8-BIT WRITE ADDRESS

ADDR1

ADDR0

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x30

0x32

0x34

0x36

0x38

0x3A

0x3C

0x3E

0x40

0x42

0x44

0x46

0x48

0x4A

0x4C

0x4E

0

R

F

1

0

R

F

1

0

R

F

1

0

R

F

1

0

1

R

F

1

8.4 Device Functional Modes

8.4.1 SMBus Slave Mode Configuration

To configure the DS280MB810 for SMBus slave mode connect the EN_SMB pin to VDD with a 1-kΩ resistor.

When the DS280MB810 is configured for SMBus slave mode operation the READ_EN_N becomes an active-

low reset pin, resetting register values when driven to LOW, or V_IL. Additionally, when the DS280MB810 is

configured for SMBus slave mode the ALL_DONE_N output pin is high-Z; except for when READ_EN_N is

English Data Sheet: SNLS542

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driven LOW which causes ALL_DONE_N to also be driven LOW. Refer to 节 8.6 for additional register

information.

8.4.2 SMBus Master Mode Configuration (EEPROM Self Load)

To configure the DS280MB810 for SMBus master mode, leave the EN_SMB pin floating (no connect). If the

DS280MB810 is configured for SMBus master mode, it will remain in the SMBus IDLE state until the

READ_EN_N pin is asserted to LOW, or V_IL. Once the READ_EN_N pin is driven LOW, the DS280MB810

becomes an SMBus master and attempts to self-configure by reading device settings stored in an external

EEPROM (SMBus 8-bit address 0xA0). When the DS280MB810 has finished reading from the EEPROM

successfully, it will drive the ALL_DONE_N pin LOW and then change from an SMBus master to an SMBus

slave. Not all bits in the register map can be configured through an EEPROM load. Refer to the DS280MB810

Programming Guide for more information.

When designing a system for using the external EEPROM, the user must follow these guidelines:

• Maximum EEPROM size is 8 kb (1024 x 8-bit).

• Set EN_SMB = FLOAT to configure for SMBus master mode.

• The external EEPROM 8-bit device address must be 0xA0 and capable of 400 kHz operation at 2.5 V or 3.3

V supply.

• Once the DS280MB810 completes its EEPROM load the device becomes an SMBus slave on the control

bus.

• If multiple DS280MB810 devices share a single EEPROM, connect the ALL_DONE_N output of the first

device to the READ_EN_N input of the next device, as shown in 图8-4.

EEPROM

8-bit SMBus

address: 0xA0

SMBus address

SDC

SDA

DS280MB810

SDC

SDA

SDC

SDA

SDC

SDA

EN_SMB

READ_EN_N

ALL_DONE_N

READ_EN_N

ALL_DONE_N

READ_EN_N

ALL_DONE_N

Tie first retimer‘s READ_EN_L pin low to

automatically initiate EEPROM read at

power up, or control this pin from a device

to initiate EEPROM read manually.

Leave final retimer‘s ALL_DONE_L

pin floating or connect to a control

chip to monitor completion of final

EEPROM read.

图8-4. Example daisy chain for multiple device, single EEPROM configuration

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When tying multiple DS280MB810 devices to the SDA and SDC bus, use these guidelines to configure the

devices for SMBus master mode:

• Use SMBus ADDR[1:0] address bits so that each device can load its configuration from the EEPROM. The

example below is for four devices. The first device in the sequence conventionally uses the 8-bit slave write

address 0x30, while subsequent devices follow the address order listed below.

– DS280MB810 instance 1 (U1): ADDR[1:0] = {0, 0} = 0x30

– DS280MB810 instance 2 (U2): ADDR[1:0] = {0, R} = 0x32

– DS280MB810 instance 3 (U3): ADDR[1:0] = {0, F} = 0x34

– DS280MB810 instance 4 (U4): ADDR[1:0] = {0, 1} = 0x36

• Use a pull-up resistor on SDA and SDC; resistor value = 2 kΩto 5 kΩis adequate.

• Float (no connect) the EN_SMB pin (E3) on all DS280MB810 devices to configure them for SMBus master

mode. The EN_SMB pin should not be dynamically changed between the high and float states.

• Daisy-chain READ_EN_N (pin F13) and ALL_DONE_N (pin D3) from one device to the next device in the

following sequence so that they do not compete for master control of the EEPROM at the same time.

1. Tie READ_EN_N of the first device in the chain (U1) to GND to trigger EEPROM read immediately after

the DS280MB810 power-on reset (PoR) completes. Alternatively, drive the READ_EN_N pin from a

control device (micro-controller or FPGA) to trigger the EEPROM read at a specific time.

2. Tie ALL_DONE_N of U1 to READ_EN_N of U2

3. Tie ALL_DONE_N of U2 to READ_EN_N of U3

4. Tie ALL_DONE_N of U3 to READ_EN_N of U4

5. Optional: Tie ALL_DONE_N output of U4 to a micro-controller or an LED to show the devices have been

loaded successfully.

Once the ALL_DONE_N status pin of the last device is flagged to indicate that all devices sharing the SMBus

line have been successfully programmed, control of the SMBus line is released by the DS280MB810. The device

then reverts back to SMBus slave mode. At this point, an external controller can perform any additional Read or

Write operations to the DS280MB810.

Refer to the DS280MB810 Programming Guide for additional information concerning SMBus master mode.

8.5 Programming

The DS280MB810 can be programmed in two ways. The DS280MB810 can be configured as an SMBus slave

(EN_SMB = HIGH) or the device can temporarily act as an SMBus master and load its configuration settings

from an external EEPROM (EN_SMB = FLOAT). Refer to 节8.4.1 and 节8.4.2 for details.

8.5.1 Transfer of Data with the SMBus Interface

The System Management Bus (SMBus) is a two-wire serial interface through which a master can communicate

with various system components. Slave devices are identified by a unique device address. The two-wire serial

interface consists of SDC and SDA signals. SDC is a clock output from the master to all of the slave devices on

the bus. SDA is a bidirectional data signal between the master and slave devices. The DS280MB810 SMBus

SDC and SDA signals are open drain and require external pull-up resistors.

Start and Stop Conditions:

The master generates Start and Stop conditions at the beginning and end of each transaction:

• Start: High to LOW transition (falling edge) of SDA while SDC is HIGH.

• Stop: Low to HIGH transition (rising edge) of SDA while SDC is HIGH.

The master generates 9 clock pulses for each byte transfer. The 9th clock pulse constitutes the acknowledge

(ACK) cycle. The transmitter releases SDA to allow the receiver to send the ACK signal. An ACK is when the

device pulls SDA LOW, while a NACK (no acknowledge) is recorded if the line remains HIGH.

Writing data from a master to a slave consists of three parts:

• The master begins with a start condition followed by the slave device address with the R/W bit cleared.

• The master sends the 8-bit register address that will be written.

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• The master sends the data byte to write for the selected register address. The register address pointer will

then increment, so the master can send the data byte for the subsequent register without re-addressing the

device, if desired. The final data byte to write should be followed by a stop condition.

SMBus read operations consist of four parts:

• The master initiates the read cycle with start condition followed by slave device address with the R/W bit

cleared.

• The master sends the 8-bit register address that will be read.

• After acknowledgment from the slave, the master initiates a re-start condition.

• The slave device address is resent followed with R/W bit set.

• After acknowledgment from the slave, the data is read back from the slave to the master. The last ACK is

HIGH if there are no more bytes to read.

8.6 Register Maps

Many of the registers in the DS280MB810 are divided into bit fields. This allows a single register to serve

multiple purposes which may be unrelated. Often, configuring the DS280MB810 requires writing a bit field that

makes up only part of a register value while leaving the remainder of the register value unchanged. The

procedure for accomplishing this task is to read in the current value of the register to be written, modify only the

desired bits in this value, and write the modified value back to the register. This sequence is commonly referred

to as Read-Modify-Write. If the entire register is to be changed, rather than just a bit field within the register, it is

not necessary to read in the current value of the register first.

Most register bits can be read or written to. However, some register bits are constrained to specific interface

instructions.

Register bits can have the following interface constraints:

• R - Read only

• RW - Read/Write

• RWSC - Read/Write, Self-Clearing

8.6.1 Register Types: Global, Shared, and Channel

The DS280MB810 has 3 types of registers:

1. Global Registers - These registers can be accessed at any time and are used to select between individual

channel registers and shared registers, or to read back the TI ID and version information.

2. Shared Registers - These registers are used for device-level configuration, status read back or control. Set

register 0xFF[0] = 0 and configure 0xFF[5:4] to access the shared registers.

3. Channel Registers –These registers are used to control and configure specific features for each individual

channel. All channels have the same channel register set and can be configured independent of each other.

Set register 0xFF[0] = 1 and configure register 0xFC to access the desired channel register set.

Refer to the Programming Guide for additional information on register configuration.

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8.6.2 Global Registers: Channel Selection and ID Information

The global registers can be accessed at any time, regardless of whether the shared or channel register set is

selected. The DS280MB810 global registers are located at address 0xEF - 0xFF.

表8-2. Global Register Map

Addr

[HEX]

Bit

Default [HEX] Mode

0x0C

EEPROM Field

Description

0xEF

General

7

0

1

RW

R

N

RESERVED

6

5

4

3

N

DEVICE_ID_QUAD_C TI device ID (quad count). Contains 0x0C.

NT[3]

2

1

0

1

0

R

DEVICE_ID_QUAD_C

NT[2]

DEVICE_ID_QUAD_C

NT[1]

DEVICE_ID_QUAD_C

NT[0]

0xF0

0xF1

0xF3

0x00

Version Revision

7

6

5

4

3

2

1

0

R

N

TYPE

TI version ID. Contains 0x00.

VERSION[6]

0

VERSION[5]

0

VERSION[4]

0

VERSION[3]

0

VERSION[2]

0

VERSION[1]

0

VERSION[0]

0x42

0

Channel Control

DEVICE_ID[7]

DEVICE_ID[6]

DEVICE_ID[5]

DEVICE_ID[4]

DEVICE_ID[3]

DEVICE_ID[2]

DEVICE_ID[1]

DEVICE_ID[0]

Channel Control

7

6

5

4

3

2

1

0

R

N

TI device ID. Contains 0x42.

1

0

1

0

0x00

0

7

6

5

4

3

2

1

0

R

N

CHAN_VERSION[3] TI digital channel version ID. Contains 0x00.

CHAN_VERSION[2]

0

CHAN_VERSION[1]

0

CHAN_VERSION[0]

0

SHARE_VERSION[3] TI digital share version ID. Contains 0x00.

SHARE_VERSION[2]

0

SHARE_VERSION[1]

0

SHARE_VERSION[0]

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Addr

表8-2. Global Register Map (continued)

[HEX]

Bit

Default [HEX] Mode

0x00

EEPROM Field

Description

0xFC

General

EN_CH7

EN_CH6

EN_CH5

EN_CH4

EN_CH3

EN_CH2

EN_CH1

EN_CH0

7

0

RW

N

Select channel 7

Select channel 6

Select channel 5

Select channel 4

Select channel 3

Select channel 2

Select channel 1

Select channel 0

6

5

4

3

2

1

0

0xFD

0xFE

0xFF

0x00

7

6

5

4

3

2

1

0

RW

N

RESERVED

Vendor ID

RESERVED

0

0x03

7

6

5

4

3

2

1

0

R

N

VENDOR_ID[7]

VENDOR_ID[6]

VENDOR_ID[5]

VENDOR_ID[4]

VENDOR_ID[3]

VENDOR_ID[2]

VENDOR_ID[1]

VENDOR_ID[0]

Channel Control

RESERVED

TI vendor ID. Contains 0x03.

0

1

0x10

0

7

6

5

4

3

2

1

RW

N

RESERVED

0

RESERVED

0

EN_SHARE_Q1

EN_SHARE_Q0

RESERVED

Select shared registers for Quad 1 (Channels 4-7).

Select shared registers for Quad 0 (Channels 0-3).

RESERVED

1

0

RESERVED

0

WRITE_ALL_CH

Allows customer to write to all channels as if they are the same, but only

allows to read back from the channel specified in 0xFC and 0xFD.

Note: EN_CH_SMB must be = 1 or else this function is invalid.

1: Enables SMBus access to the channels specified in register 0xFC.

0: The shared registers are selected, see 0xFF[5:4].

0

RW

N

EN_CH_SMB

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8.6.3 Shared Registers

表8-3. Shared Register Map

Addr

[HEX]

Bit

Default [HEX] Mode

0x01

EEPROM Field

Description

0x00

General

7

0

R

N

I²C_ADDR[3]

I²C_ADDR[2]

I²C_ADDR[1]

I²C_ADDR[0]

RESERVED

I²C strap observation. The device 7-bit slave address is 0x18 +

I²C_ADDR[3:0].

6

5

4

3

2

1

0

RESERVED

0

RESERVED

0

1'b when Quad1 Shared registers enabled.

1'b when Quad0 Shared registers enabled.

1

0x01

0x02

0x03

0x04

0x02

Version Revision

RESERVED

Channel Control

RESERVED

Channel Control

RESERVED

General

7

6

5

4

3

2

1

0

R

N

RESERVED

0

1

0

0x00

7

6

5

4

3

2

1

0

RW

N

RESERVED

0

0x00

7

6

5

4

3

2

1

0

RW

N

RESERVED

0

0x01

0

7

6

RW

N

RESERVED

RST_I²C_REGS

RESERVED

0

RWSC

1: Reset shared registers, bit is self-clearing.

0: Normal operation

5

4

0

RWSC

RW

N

RST_I²C_MAS

1: Self-clearing reset for I²C master.

0: Normal operation

FRC_EEPRM_RD

1: Override EN_SMB and input chain status to force EEPROM

Configuration.

0: Normal operation

RESERVED

3

2

0

RW

N

RESERVED

REGS_CLOCK_EN RESERVED

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Addr

表8-3. Shared Register Map (continued)

[HEX]

Bit

Default [HEX] Mode

EEPROM Field

Description

1

0

1

RW

N

I²C_MAS_CLK_EN RESERVED

0

7

I²CSLV_CLK_EN

RESERVED

0x05

0x00

0

General

RW

N

DISAB_EEPRM_CFG 1: Disable Master Mode EEPROM Configuration (If not started, not effective

midway or after configuration).

0: Normal operation

6

5

0

RW

N

CRC_EN

RESERVED

ML_TEST

_CONTROL

4

0

R

N

EEPROM_READING Sets 1 when EEPROM reading is done.

_DONE

3

2

0

R

N

Y

RESERVED

CAL_CLK_INV_DIS 1: Disable the inversion of CAL_CLK_OUT.

0: Normal operation, CAL_CLK_OUT is inverted with respect to

RESERVED

CAL_CLK_IN.

1

0

R

N

MUX_CONFIG_PIN_C 1: MUXSEL0_TEST0 and MUXSEL1_TEST1 are used to configure the

TRL

cross-point mux. MUXSEL0_TEST0 controls the cross-point for channels

0–1 and 4–5. MUXSEL1_TEST1 controls the cross-point for channels 2–

3 and 6–7. For mux pin-control, Reg_05[0] must also be 0, which is the

power-on default value.

0: Cross-point mux is configured on a per-channel basis with Reg_0x06[0].

TEST0_AS_CAL

_CLK

RESERVED

0x06

0x00

General

RESERVED

General

7

6

5

4

3

2

1

0

RW

N

RESERVED

0

0x07

0x00

0

7

6

RW

R

N

RESERVED

CAL_CLK_DET

RESERVED

0

1: Indicates that CAL_CLK has been detected.

0: Indicates that CAL_CLK has not been detected.

RESERVED

5

4

3

0

RW

N

RESERVED

MR_CAL_CLK_DET 1: Disable CAL_CLK detect.

_DIS

0: Enable CAL_CLK detect.

2

1

0

RW

N

Y

RESERVED

DIS_CAL_CLK_OUT 1: Disable CAL_CLK_OUT, output is high-Z.

0: Enable CAL_CLK_OUT.

0x08

0x00

General

7

6

5

4

3

2

1

0

RW

N

RESERVED

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表8-3. Shared Register Map (continued)

Addr

[HEX]

Bit

Default [HEX] Mode

EEPROM Field

Description

0

RW

N

RESERVED

General

RESERVED

0x09

0x00

7

6

5

4

3

2

1

0

R

N

RESERVED

General

RESERVED

0

0x0A

0x00

7

6

5

4

3

2

1

0

RW

R

N

RESERVED

0

R

0x0B

0x00

0

7

6

R

N

EECFG_CMPLT

EECFG_FAIL

11: Not valid.

10: EEPROM load completed successfully.

01: EEPROM load failed after 64 attempts.

00: EEPROM load in progress.

0

5

4

3

2

1

0

R

N

EECFG_ATMPT[5]

EECFG_ATMPT[4]

EECFG_ATMPT[3]

EECFG_ATMPT[2]

EECFG_ATMPT[1]

EECFG_ATMPT[0]

Indicates number of attempts made to load EEPROM image.

0

0x0C

0x91

1

7

RW

N

I²C_FAST

1: EEPROM load uses Fast I²C Mode (400 kHz).

0: EEPROM load uses Standard I²C Mode (100 kHz).

6

5

4

3

2

1

0

1

0

1

RW

N

I²C_SDA_HOLD[2]

I²C_ SDA_HOLD[1]

I²C_ SDA_HOLD[0]

Internal SDA Hold Time

This field configures the amount of internal hold time provided for the SDA

input relative to the SDC input. Units are 100 ns.

I²C_FLTR_DEPTH[3] I²C Glitch Filter Depth

This field configures the maximum width of glitch pulses on the SDC and

SDA inputs that will be rejected. Units are 100 ns.

I²C_FLTR_DEPTH[2]

I²C_FLTR_DEPTH[1]

I²C_FLTR_DEPTH[0]

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8.6.4 Channel Registers

表8-4. Channel Register Map

Addr

[HEX]

Bit

Default [HEX] Mode

0x00

EEPROM Field

Description

0x00

General

7

0

RW

N

CLK_CORE_DISAB 1: Disables 10 M core clock. This is the main clock domain for all the state

machines.

0: Normal operation

6

0

RW

CLK_REGS_EN

1: Force enable the clock to the registers. Normally, the register clock is

enabled automatically on a needed basis.

0: Normal operation

5

4

0

RW

N

RESERVED

CLK_REF_DISAB

1: Disables the 25 MHz CAL_CLK domain.

0: Normal operation

3

2

0

RW

N

RST_CORE

RST_REGS

1: Reset the 10 M core clock domain. This is the main clock domain for all

the state machines.

0: Normal operation

RWSC

1: Reset channel registers to power-up defaults.

0: Normal operation

1

0

RW

N

RESERVED

RST_CAL_CLK

1: Resets the 25 MHz reference clock domain.

0: Normal operation

0x01

SIG_DET

7

6

0

R

N

SIGDET

Signal detect status.

1: Signal detected at RX inputs.

0: No signal detected at RX inputs.

0

SIGDET_ADJACENT Signal detect status of adjacent channel. "Adjacent," referring to channel

N+1 if N is even, or channel N-1 if N is odd.

1: Signal detected at RX inputs of adjacent channel.

0: No signal detected at RX inputs.

5

4

3

2

1

0

R

N

RESERVED

0

1

0x02

0x00

7

6

5

4

3

2

1

0

R

N

RESERVED

CTLE_BOOST

EQ_BW[1]

RESERVED

0

R

0

R

0

RW

0

0x03

0x80

1

7

6

RW

Y

EQ stage one buffer current (strength) control. Impacts EQ bandwidth.

2'b11 yields highest bandwidth, 2'b00 yields lowest bandwidth. Refer to the

Programming Guide for more information.

0

EQ_BW[0]

5

4

3

2

1

0

RW

Y

EQ_BST2[2]

EQ_BST2[1]

EQ_BST2[0]

EQ_BST1[2]

EQ_BST1[1]

EQ_BST1[0]

EQ boost stage 2 controls. Directly goes to analog. No override bit is

needed. Refer to the Programming Guide for more information.

0

EQ boost stage 1 controls. Directly goes to analog. No override bit is

needed. Refer to the Programming Guide for more information.

0

0x04

0x90

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表8-4. Channel Register Map (continued)

Addr

[HEX]

Bit

Default [HEX] Mode

EEPROM Field

Description

7

1

0

RW

N

RESERVED

EQ_PD_SD

RESERVED

6

1: Power down signal detect

0: Normal operation

1: Enable EQ high gain

0: Enable EQ low gain

RESERVED

5

0

RW

Y

EQ_HIGH_GAIN

4

3

1

0

RW

Y

EQ_EN_DC_OFF

EQ_PD_EQ

1: Power down EQ

0: Enable EQ

2

1

0

RW

N

Y

RESERVED

BG_SEL_IPP100[2] CTLE bias programming. BG_SEL_IPP100[1:0] is in Reg_0x0F[5:4].

EQ_EN_BYPASS

1: Enable EQ boost stage 1 (BST1) bypass.

0: Normal operation, signal travels through boost stage 1 (BST1).

0x05

0x04

SIG_DET_CONFIG

EQ_SD_PRESET

7

6

0

RW

Y

1: Force signal detect result to 1.

0: Normal operation

This bit should not be set if 0x05[6] is also set.

1: Force signal detect result to 0.

0: Normal operation

0

EQ_SD_RESET

This bit should not be set if 0x05[7] is also set.

5

4

3

2

1

0

RW

Y

N

EQ_REFA_SEL[1]

EQ_REFA_SEL[0]

EQ_REFD_SEL[1]

EQ_REFD_SEL[0]

RESERVED

Signal detect assert thresholds. Refer to the Programming Guide for more

information.

0

Signal detect de-assert thresholds. Refer to the Programming Guide for

more information.

1

0

RESERVED

0

RESERVED

0x06

0xC0

GPIO2 Config

7

6

5

1

0

RW

Y

DRV_SEL_VOD[1]

DRV_SEL_VOD[0]

DRV_EQ_PD_OV

Driver VOD adjust (DC gain). Refer to the Programming Guide for more

information.

1: Driver and equalizer power down manually with Reg_0x06[3] and

Reg_0x04[3], respectively.

0: Driver and equalizer are powered down or up by default when LOS=1/0.

Driver mute override:

4

0

RW

Y

DRV_SEL_MUTE

_OV

1: Use register 0x06[1] for mute control.

0: Normal operation. Mute is automatically controlled by signal detect.

1: Power down the driver.

3

2

1

0

RW

Y

DRV_PD

0: Normal operation, driver power on or off is controlled by signal detect.

DRV_PD_CM_LOOP

DRV_SEL_MUTE

1: Disable the driver’s common mode loop control circuit.

0: Normal operation, common mode loop enabled.

1: Mute driver if override bit is enabled.

0: Normal operation

DRV_SEL_SOURCE Select the signal source for the current channel's driver using the cross-

point.

1: Transmit the signal from the adjacent channel.

0: Transmit the signal from the local channel.

0x07

0x00

7

6

0

RW

N

RESERVED

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Addr

表8-4. Channel Register Map (continued)

[HEX]

Bit

Default [HEX] Mode

EEPROM Field

Description

5

0

RW

Y

MUX_INV_PIN_CTRL Invert the mux pin control. Only applicable if Shared Reg_0x05[1]=1.

For channels 0, 1, 4, and 5 (controlled by MUXSEL0):

0: If MUXSEL0=0, channel is in straight-thru mode. If MUXSEL0=1, channel

output is from adjacent channel's EQ.

1: If MUXSEL0=1, channel is in straight-thru mode. If MUXSEL0=0, channel

output is from adjacent channel's EQ.

For channels 2, 3, 6, and 7 (controlled by MUXSEL1):

0: If MUXSEL1=0, channel is in straight-thru mode. If MUXSEL1=1, channel

output is from adjacent channel's EQ.

1: If MUXSEL1=1, channel is in straight-thru mode. If MUXSEL1=0, channel

output is from adjacent channel's EQ.

4

3

2

1

0

RW

N

RESERVED

0

0x08

0x50

7

6

5

4

3

0

1

0

1

0

RW

Y

RESERVED

BG_SEL_IPTAT25

1: Increases the current to the CTLE by 5%.

0: Default

2

1

0

RW

N

RESERVED

0

RESERVED

0

RESERVED

0x09

0x00

7

6

5

4

3

2

1

0

RW

N

RESERVED

0

0x0A

0x30

0

7

6

RW

N

Y

RESERVED

0

SD_EN_FAST

1: Fast signal detect enabled.

0: Fast signal detect disabled.

5

4

1

RW

Y

SD_REF_HIGH

SD_GAIN

Signal detect threshold controls:

11: Normal operation

10: Signal detect assert or de-assert thresholds reduced.

01: Signal detect assert or de-assert thresholds reduced.

00: Signal detect assert or de-assert thresholds reduced.

3

2

1

0

RW

N

RESERVED

0

0x0B

0x1A

7

6

5

4

3

0

1

RW

N

Y

RESERVED

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表8-4. Channel Register Map (continued)

Addr

[HEX]

Bit

Default [HEX] Mode

EEPROM Field

Description

RESERVED

2

0

RW

Y

RESERVED

1

0

1

0

0x0C

0x00

7

6

5

4

3

2

1

0

RW

N

Y

RESERVED

0

0x0D

0x0E

0x0F

0x00

7

6

5

4

3

2

1

0

RW

N

Y

RESERVED

0

0x00

7

6

5

4

3

2

1

0

RW

N

RESERVED

0

0x00

0

7

6

5

4

RW

N

RESERVED

0

Y

BG_SEL_IPP100[1] CTLE bias programming. BG_SEL_IPP100[2] is in Reg_0x04[1].

000: 0% additional current (Default)

001: 5% additional current

0

BG_SEL_IPP100[0]

010: 10% additional current

011: 15% additional current

100: 20% additional current

101: 25% additional current

110: 30% additional current

111: 35% additional current

3

2

0

RW

Y

BG_SEL_IPH200

_v1[1]

Program pre-driver bias current:

00: 0% additional current (Default)

01: 12.5% additional current

10: 25% additional current

BG_SEL_IPH200

_v1[0]

11: 37.5% additional current

Program driver bias current:

00: 0% additional current (Default)

01: 12.5% additional current

10: 25% additional current

1

0

RW

Y

BG_SEL_IPH200

_v0[1]

BG_SEL_IPH200

_v0[0]

11: 37.5% additional current

0x10

0x00

7

0

RW

N

RESERVED

English Data Sheet: SNLS542

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Addr

表8-4. Channel Register Map (continued)

[HEX]

Bit

Default [HEX] Mode

EEPROM Field

Description

RESERVED

6

0

RW

N

Y

RESERVED

5

4

3

2

1

0

0x11-0x1

9

0x00

7

6

5

4

3

2

1

0

RW

N

RESERVED

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9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The DS280MB810 is a high-speed linear repeater which extends the reach of differential channels impaired by

loss from transmission media like PCBs and cables while simultaneously providing signal distribution. It can be

deployed in a variety of systems from backplanes and mid-planes to front ports and chip-to-chip interfaces. The

following sections outline typical applications and their associated design considerations.

9.2 Typical Application

The DS280MB810 with integrated cross-point is typically used in two main application scenarios:

1. Backplane, mid-plane, and chip-to-chip reach extension

2. Front-port eye opening for copper and optical applications

Line Card 2

Line Card 1

Switch Fabric Card

25G/28G-VSR

QSFP28,

SFP28, etc.

4

ASIC

4

ASIC

FPGA

ASIC

FPGA

Line Card

4

QSFP28,

SFP28, etc.

Backplane/

Midplane

图9-1. Typical application block diagram

English Data Sheet: SNLS542

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备注

TI recommends to AC couple the DS280MB810's high-speed outputs. In some cases, ASIC or FPGA

SerDes receivers support DC coupling, and it may be desirable to DC couple the DS280MB810 output

with the ASIC/FPGA RX input to reduce the PCB area which would normally be consumed by AC

coupling capacitors. To DC couple the DS280MB810 output with an ASIC RX input, the ASIC RX must

support DC coupling and it must support an input common mode voltage of 1.05 V. To determine if the

ASIC RX supports DC coupling, here are some items to consider based on 图9-2:

1.

1. The ASIC RX must be AC coupled on-chip.

2. The ASIC RX should not force a DC bias on the RX pins.

3. System designers should ensure that when the PCB powers on, the power supply rails are

appropriately sequenced to prevent the DS280MB810's output common mode voltage from

forward-biasing the ESD structure of the ASIC or violating the absolute maximum input voltage

specifications of the ASIC.

ASIC or FPGA RX

(3)

VCC

Termination

/ Bias

(2)

DS280MB810

RX

Rx Pins

(1)

VSS

图9-2. Considerations for DC coupling to ASIC RX

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9.2.1 Backplane and Mid-Plane Reach Extension

The DS280MB810 has strong equalization capabilities that allow it to equalize insertion loss and extend the

reach of backplane channels by 17+ dB beyond the normal capabilities of the ASICs operating over the channel.

The DS280MB810 is designed to apply gain in a linear fashion. Whenever system design constraints allow, the

DS280MB810 should be placed with the higher loss channel segment at the input and the lower loss channel

segment at the output; however, since the DS280MB810 operates in a linear fashion, it can also be used in

applications where the lower loss channel segment is at the input and the higher loss channel segment is at the

output. 图 9-3 shows a typical backplane and mid-plane configuration using the DS280MB810 to perform

equalization and signal distribution for failover or redundancy. 图 9-4 shows the corresponding simplified

schematic for this application.

Passive Backplane/

Midplane

Switch Fabric Card

Line Card 1

4

ASIC

25 G / 28 G-LR

4

FPGA

ASIC

FPGA

Line Card 2

4

ASIC

4

25 G / 28 G-LR

4

FPGA

图9-3. Typical backplane and mid-plane application block diagram

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AC coupling implemented close to or

inside Receiver

No AC coupling

capacitors needed

Ingress Repeater (Multiplexer)

TX0P

TX0N

RX0P

RX0N

X

RX1P

RX1N

TX1P

TX1N

.

RX6P

RX6N

TX6P

TX6N

X

RX7P

RX7N

TX7P

TX7N

VDD

SDA⁽¹⁾

SDC⁽¹⁾

To system

SMBus⁽¹⁾

1 kΩ

SMBus

Slave mode

ADDR0

ADDR1

Address straps

(pull-up, pull-down, or float)

EN_SMB

Float for SMBus

Slave mode

SMBus Slave

mode

READ_EN_N

VDD

ALL_DONE_N

GND

2.5 V

Minimum

recommended

decoupling

1 ꢀF

(2x)

0.1 ꢀF

(4x)

Backplane / Mid-plane

Connector

ASIC or FPGA

Egress Repeater (De-multiplexer)

AC coupling implemented close

to or inside Receiver

No AC coupling

capacitors needed

RX0P

RX0N

TX0P

TX0N

X

RX1P

RX1N

TX1P

TX1N

.

RX6P

RX6N

TX6P

TX6N

X

RX7P

RX7N

TX7P

TX7N

SDA⁽¹⁾

SDC⁽¹⁾

To system

SMBus⁽¹⁾

VDD

ADDR0

ADDR1

Address straps

(pull-up, pull-down,

or float)

SMBus

Slave mode

1 kΩ

EN_SMB

SMBus Slave

mode

Float for SMBus

Slave mode

READ_EN_N

ALL_DONE_N

GND

2.5 V

VDD

Minimum

recommended

decoupling

1 ꢀF

(2x)

0.1 ꢀF

(4x)

(1) SMBus signals need to be pulled up elsewhere in the system.

图9-4. Typical backplane and mid-plane simplified schematic

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9.2.1.1 Design Requirements

For backplane, mid-plane, and chip-to-chip reach extension applications, use the guidelines in the table below.

DESIGN PARAMETER

REQUIREMENT

AC coupling capacitors

Generally not required. 220-nF AC coupling capacitors are included

in the DS280MB810 package on the RX side.

Input channel insertion loss

≥10 dB at 14 GHz as a rough guideline. For best performance, the

input channel insertion loss should be greater than or equal to the

equalizer boost setting used in the DS280MB810.

Output channel insertion loss

Depends on downstream ASIC or FPGA SerDes capabilities. Should

be ≥5 dB at 14 GHz as a rough guideline.

Total (input + output) channel insertion loss

Depends on downstream ASIC or FPGA SerDes capabilities. The

DS280MB810 can extend the reach between two ASICs by 17+ dB

beyond the ASICs' normal capabilities.

Link partner TX launch amplitude

Link partner TX FIR filter

800 mV_PPto 1200 mV_PPdifferential

Depends on the channel loss.

9.2.1.2 Detailed Design Procedure

The design procedure for backplane and mid-plane applications is as follows:

1. Determine the total number of channels on the board which require a DS280MB810 for signal conditioning.

This will dictate the total number of DS280MB810 devices required for the board. It is generally

recommended that channels with similar total insertion loss on the board be grouped together in the same

DS280MB810 device. This will simplify the device settings, as similar loss channels generally utilize similar

settings.

2. Determine the maximum current draw required for all DS280MB810 devices. This may impact the selection

of the regulator for the 2.5-V supply rail. To calculate the maximum current draw, multiply the maximum

power supply current by the total number of DS280MB810 devices.

3. Determine the SMBus address scheme needed to uniquely address each DS280MB810 device on the

board, depending on the total number of devices identified in step 1. Each DS280MB810 can be strapped

with one of 16 unique SMBus addresses. If there are more DS280MB810 devices on the board than the

number of unique SMBus addresses which can be assigned, then use an I²C expander like the TCA/PCA

family of I²C/SMBus switches and multiplexers to split the SMBus into multiple busses.

4. Determine if the device will be configured from EEPROM (SMBus master mode) or from the system SMBus

(SMBus slave mode).

a. If SMBus master mode will be used, provisions should be made for an EEPROM on the board with 8-bit

SMBus address 0xA0. Refer to 节8.4.2 for more details on SMBus Master Mode including EEPROM

size requirements.

b. If SMBus slave mode will be used for all device configurations, an EEPROM is not needed.

5. Make provisions in the schematic and layout for standard decoupling capacitors between the device VDD

supply and GND. Refer to 节10 for more information.

6. If there is a need to potentially upgrade to a pin-compatible TI Retimer device, then make provisions in the

schematic and layout for a 25-MHz (±100 ppm) single-ended CMOS clock. Each DS280MB810 buffers the

clock on the CAL_CLK_IN pin and presents the buffered clock on the CAL_CLK_OUT pin. This allows

multiple (up to 20) DS280MB810 calibration clocks to be daisy chained to avoid the need for multiple

oscillators on the board. If the oscillator used on the board has a 2.5-V CMOS output, then no AC coupling

capacitor or resistor ladder is required at the input to CAL_CLK_IN. No AC coupling or resistor ladder is

needed between one DS280MB810 CAL_CLK_OUT output and the next DS280MB810’s CAL_CLK_IN

input. The final DS280MB810’s CAL_CLK_OUT output can be left floating. A 25 MHz clock is not required

for the DS280MB810, but it is good practice to provision for it in case there is a future plan to upgrade to a

pin-compatible TI Retimer device.

7. If there is a need to potentially upgrade to a pin-compatible TI Retimer device, then connect the INT_N pin to

an FPGA or CPU for interrupt monitoring. Note that multiple INT_N outputs can be connected together. The

common INT_N net should be pulled high to 2.5 V or 3.3 V. The INT_N pin on the DS280MB810 does not

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perform the interrupt functionality that the equivalent pin on the pin-compatible Retimer device does;

however, it is good practice to provision for this in case there is a future plan to upgrade to a pin-compatible

TI Retimer device.

9.2.2 Front-Port Applications

The DS280MB810 has strong equalization capabilities that allow it to equalize insertion loss and extend the

reach of front-port channels by 17 dB beyond the normal capabilities of the ASIC while supporting CAUI-4 and

CR4 electrical requirements. The DS280MB810 is designed to apply gain in a linear fashion in order to support

longer distances between the switch ASIC and the front-port module. 图9-5 illustrates a configuration where two

DS280MB810s are used to mux between one QSFP28 port and four SFP28 ports. 图 9-9 shows the simplified

schematic for this application.

Line Card / Switch Card

QSFP28

4

ASIC

Line Card

FPGA

4

SFP28

图9-5. Front-port application block diagram

Standard front-port modules have AC coupling capacitors included inside the module. The DS280MB810,

therefore, is ideal for front-port Egress signal conditioning applications since it includes AC coupling capacitors

on the input (RX) side and does not include AC coupling capacitors on the output (TX) side.

Egress signal

conditioning

x8 25 G SR/MR/LR

VSR

DS280MB810

QSFP,

SFP, etc.

ASIC or

FPGA

图9-6. DS280MB810 recommended for front-port Egress

The optimum solution for front-port Ingress signal conditioning applications depends on whether the ASIC RX

supports DC coupling and whether it can support an input common mode voltage of 1.05 V. For further guidance

on determining if the ASIC RX supports DC coupling, refer to 图 9-2. If the ASIC RX supports DC coupling and

can tolerate an input common mode voltage of 1.05-V or less, then the DS280MB810 is the optimum solution for

front-port Ingress signal conditioning. If the ASIC RX does not support DC coupling or cannot tolerate an input

common mode voltage of 1.05-V, then the pin-compatible DS280DF810 Retimer with cross-point, which has

integrated AC Coupling capacitors on both RX and TX, may be the optimum solution.

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ASIC or FPGA

SerDes RX supports

DC coupling and

tolerates DC input

QSFP,

SFP, etc.

DS280MB810

x8 25 G SR/MR/LR

common mode < 1.05 V

Ingress signal

conditioning

图9-7. DS280MB810 recommended for front-port Ingress

QSFP,

SFP, etc.

DS280MB810

ASIC or FPGA

x8 25 G SR/MR/LR

SerDes RX does not

support DC coupling or

requires DC input

Ingress signal

conditioning

common mode << 1.05 V

QSFP,

SFP, etc.

DS280MB810

图9-8. DS280MB810 or DS280DF810 recommended for front-port Ingress

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AC coupling implemented close to or

inside Receiver

No AC coupling

capacitors needed

Ingress Repeater (Multiplexer)

TX0P

TX0N

RX0P

RX0N

X

RX1P

RX1N

TX1P

TX1N

.

RX6P

RX6N

TX6P

TX6N

X

RX7P

RX7N

TX7P

TX7N

VDD

SDA

To system

SMBus⁽¹⁾

SDC

ADDR0

ADDR1

1 kΩ

SMBus

Slave mode

Address straps

(pull-up, pull-down, or float)

EN_SMB

Float for SMBus

Slave mode

SMBus Slave

mode

READ_EN_N

VDD

ALL_DONE_N

GND

2.5 V

Minimum

recommended

decoupling

1 ꢀF

(2x)

0.1 ꢀF

(4x)

QSFP28, SFP28, or

similar connector

ASIC or FPGA

Egress Repeater (De-multiplexer)

No AC coupling capacitors

needed

No AC coupling

capacitors needed

RX0P

RX0N

TX0P

TX0N

X

RX1P

RX1N

TX1P

TX1N

.

RX6P

RX6N

TX6P

TX6N

X

RX7P

RX7N

TX7P

TX7N

SDA

SDC

To system

SMBus⁽¹⁾

VDD

ADDR0

ADDR1

Address straps

(pull-up, pull-down,

or float)

SMBus

Slave mode

1 kΩ

EN_SMB

SMBus Slave

mode

Float for SMBus

Slave mode

READ_EN_N

ALL_DONE_N

GND

2.5 V

VDD

Minimum

recommended

decoupling

1 ꢀF

(2x)

0.1 ꢀF

(4x)

(1) SMBus signals need to be pulled up elsewhere in the system.

图9-9. Front-port application simplified schematic

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9.2.2.1 Design Requirements

For front-port reach extension and signal distribution applications, use the guidelines in the table below.

DESIGN PARAMETER

REQUIREMENT

AC Coupling Capacitors

Generally not required. 220-nF AC coupling capacitors are included

in the DS280MB810 package on the RX side.

Input Channel Insertion Loss

Output Channel Insertion Loss

≥10 dB at 14 GHz as a rough guideline. For best performance, the

input channel insertion loss should be greater than or equal to the

equalizer boost setting used in the Repeater.

For best performance in egress applications, place the Repeater

close to the front-port cage.

For best performance in ingress applications, place the Repeater

with ≥5 dB loss at 14 GHz between the output and the

downstream ASIC.

Switch ASIC TX Launch Amplitude

600 mVppd to 1000 mVppd

9.2.2.2 Detailed Design Procedure

The design procedure for front-port applications is as follows:

1. Determine the total number of channels on the board which require a DS280MB810 for signal conditioning.

This will dictate the total number of DS280MB810 devices required for the board. It is generally

recommended that channels belonging to the same port be grouped together in the same DS280MB810

device. This will simplify the device settings, as similar loss channels generally utilize similar settings.