DS320PR810 [TI]
PCIe® 5.0、32Gbps、8 通道线性转接驱动器;
| 型号： | DS320PR810 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PCIe® 5.0、32Gbps、8 通道线性转接驱动器 PC 驱动 驱动器 |
| 文件： | 总38页 (文件大小：2077K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS320PR810
ZHCSQD1 –AUGUST 2022
DS320PR810 八通道线性转接驱动器，用于PCIe 5.0、CXL 1.1
1 特性
3 说明
• 八通道线性转接驱动器支持速率高达32 Gbps 的
PCIe 5.0、CXL 2.0 和UPI 2.0
• 支持大多数交流耦合接口，包括DP、SAS、
SATA、XFI
• CTLE 在16GHz 下可升至22dB
• 100 ps 的超低延迟
• PRBS 数据的75 fs 低附加随机抖动
• 16GHz 时-10dB 的极低回波损耗
• 3.3V 单电源
• 内部稳压器具有抗电源噪声能力
• 160mW/通道的低有功功率
• 无需散热器
• 引脚搭接、SMBus 或EEPROM 编程
• 针对PCIe 用例的自动接收器检测
• 与协议无关的线性转接驱动器可无缝支持PCIe 链
接训练
• 通过一个或多个DS320PR810 支持x4、x8、
x16、x24 总线宽度
DS320PR810 是一款八通道低功耗高性能线性中继器
或转接驱动器，专为支持 PCIe 5.0、CXL 2.0、UPI
2.0 和其他速率高达32 Gbps 的接口而设计。
DS320PR810 接收器部署了连续时间线性均衡器
(CTLE)，用以提供可编程高频增强功能。均衡器可以
打开由于 PCB 布线等互连介质引起的码间串扰 (ISI)
而完全关闭的输入眼图。CTLE 接收器后跟一个线性输
出驱动器。DS320PR810 的线性数据路径保留了发射
预设信号的特性。线性转接驱动器成为无源通道的一部
分，该通道作为一个整体进行链路训练，可获得更优发
送和接收均衡设置。对这种链路训练协议进行透明管理
可实现更优的电气链路和尽可能低的延迟。该器件具有
低通道间串扰、低附加抖动和极低的回波损耗，因此在
链路中几乎可用作无源元件，而又具有实用的均衡功
能。该器件的数据路径使用内部稳压电源轨，可高度抵
抗板上的各种电源噪声。
此器件还具有低交流和直流增益变化，可在各种平台部
署中提供一致的均衡功能。
• 温度范围为-40 °C 至85°C
• 5.5mm × 10mm、64 引脚WQFN 封装
封装信息(1)
封装尺寸（标称值）
器件型号
封装
2 应用
WQFN（NJX，
64）
DS320PR810
5.50mm × 10.00mm
• 机架式服务器、微服务器和塔式服务器
• 高性能计算
• 硬件加速器
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
• 网络连接存储
• 存储区域网络(SAN) 和主机总线适配器(HBA) 卡
• 网络接口卡(NIC)
• 台式计算机/主板
DS320PR810
PR810
PCIe 5.0 x16 Network Interface Card
8-Channel
Linear Redriver
PR810
PCIe
X16
CPU
/ PCIe
Root
Complex
x16
Riser Card
x16
End
Point
Server Motherboard
DS320PR810
Connector
CPU
8-Channel
x16
Linear Redriver
典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNLS668
DS320PR810
ZHCSQD1 –AUGUST 2022
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................16
7.5 Programming............................................................ 17
8 Application and Implementation..................................22
8.1 Application Information............................................. 22
8.2 Typical Applications.................................................. 22
9 Power Supply Recommendations................................28
10 Layout...........................................................................28
10.1 Layout Guidelines................................................... 28
10.2 Layout Example...................................................... 29
11 Device and Documentation Support..........................30
11.1 接收文档更新通知................................................... 30
11.2 支持资源..................................................................30
11.3 Trademarks............................................................. 30
11.4 静电放电警告...........................................................30
11.5 术语表..................................................................... 30
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings........................................ 7
6.2 ESD Ratings............................................................... 7
6.3 Recommended Operating Conditions.........................7
6.4 Thermal Information....................................................8
6.5 DC Electrical Characteristics...................................... 8
6.6 High Speed Electrical Characteristics.........................9
6.7 SMBUS/I2C Timing Charateristics............................ 10
6.8 Typical Characteristics..............................................12
6.9 Typical Jitter Characteristics..................................... 13
7 Detailed Description......................................................14
7.1 Overview...................................................................14
7.2 Functional Block Diagram.........................................14
Information.................................................................... 30
4 Revision History
DATE
REVISION
NOTES
August 2022
*
Initial Release
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5 Pin Configuration and Functions
1
RX0P
RX0N
55
55
1
TX0P
TX0N
2
2
54
54
53
53
3
GND
TX1P
TX1N
VCC
RSVD2
3
52
52
4
4
RX1P
RX1N
51
51
5
5
50
50
6
6
VCC
RX2P
49
49
TX2P
TX2N
7
7
RX2N
48
48
8
8
47
47
RSVD5
GND
RX3P
RX3N
9
9
46
46
10
10
TX3P
TX3N
GND
11
11
45
45
EP=GND
12
12
44
44
GND
RX4P
13
13
43
43
TX4P
TX4N
GND
RX4N
14
14
42
42
15
15
41
41
RSVD3
RX5P
16
16
40
40
TX5P
17
17
39
39
TX5N
VCC
RX5N
VCC
18
18
38
38
RX6P
19
19
37
37
TX6P
RX6N 20
20
36
36
TX6N
RSVD4
GND 21
21
35
35
22
34
34
TX7P
TX7N
RX7P
RX7N
22
23
23
33
33
图5-1. NJX Package, 64-Pin WQFN (Top View)
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表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
In SMBus/I2C Primary mode:
Indicates the completion of a valid EEPROM register load operation. External pullup
resistor such as 4.7 kΩ required for operation.
O, 3.3 V open
drain
ALL_DONE_N
31
High: External EEPROM load failed or incomplete
Low: External EEPROM load successful and complete
In SMBus/I2C Secondary/Pin mode:
This output is High-Z. The pin can be left floating.
Sets device control configuration modes. 5-level IO pin as provided in 表7-4. The pin
can be exercised at device power up or in normal operation mode.
L0: Pin mode –device control configuration is done solely by strap pins.
L1: SMBus/I2C Primary mode –device control configuration is read from external
EEPROM. When the DS320PR810 has finished reading from the EEPROM
successfully, it will drive the ALL_DONE_N pin LOW. SMBus/I2C secondary operation
is available in this mode before, during or after EEPROM reading. Note: during
EEPROM reading if the external SMBus/I2C primary wants to access DS320PR810
registers it must support arbitration.
MODE
61
I, 5-level
L2: SMBus/I2C Secondary mode –device control configuration is done by an
external controller with SMBus/I2C primary.
L3 and L4 (Float): RESERVED –TI internal test modes.
EQ0 / ADDR0
EQ1 / ADDR1
59
60
I, 5-level
I, 5-level
In Pin mode:
Sets receiver linear equalization (CTLE) boost for channels 0-3 (Bank 0) as provided in
表7-1. These pins are sampled at device power-up only.
In SMBus/I2C mode:
Sets SMBus / I2C secondary address as provided in 表7-5. These pins are sampled at
device power-up only.
EQ0_1
EQ1_1
27
29
I, 5-level
I, 5-level
Sets receiver linear equalization (CTLE) boost for channels 4-7 (Bank 1) as provided in
表7-1 in Pin mode. The pin is sampled at device power-up only.
In Pin mode:
Flat gain (DC and AC) from the input to the output of the device for channels 0-3 (Bank
0). The pin is sampled at device power-up only.
I, 5-level / I/O,
3.3 V
LVCMOS,
open drain
GAIN0 / SDA
GAIN1
63
28
In SMBus/I2C mode:
3.3 V SMBus/I2C data. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus /
I2C interface standard.
Flat gain (DC and AC) from the input to the output of the device for channels 4-7 (Bank
1) in Pin mode. The pin is sampled at device power-up only.
I, 5-level
P
Ground reference for the device.
EP, 9, 12, 21,
24, 32, 41, 44,
53, 56, 64
EP: the Exposed Pad at the bottom of the QFN package. It is used as the GND return
for the device. The EP should be connected to one or more ground planes through the
low resistance path. A via array provides a low impedance path to GND. The EP also
improves thermal dissipation.
GND
PD0
PD1
2-level logic controlling the operating state of the redriver. Active in all device control
modes. The pin has internal 1-MΩ weak pull-down resistor. The pin triggers PCIe Rx
detect state machine when toggled.
High: power down for channels 0-3
Low: power up, normal operation for channels 0-3
I, 3.3 V
LVCMOS
25
26
2-level logic controlling the operating state of the redriver. Active in all device control
modes. The pin has internal 1-MΩ weak pull-down resistor. The pin triggers PCIe Rx
detect state machine when toggled.
I, 3.3 V
LVCMOS
High: power down for channels 4-7
Low: power up, normal operation for channels 4-7
In SMBus/I2C Primary mode:
After device power up, when the pin is low, it initiates the SMBus / I2C Primary mode
EEPROM read function. When EEPROM read is complete (indicated by assertion of
ALL_DONE_N low), this pin can be held low for normal device operation. During the
EEPROM load process the device’s signal path is disabled.
In SMBus/I2C Secondary and Pin modes:
I, 3.3 V
LVCMOS
READ_EN_N
57
In these modes the pin is not used. The pin can be left floating. The pin has internal 1-
MΩ weak pull-down resistor.
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表5-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
RSVD0
RSVD1
NO.
58
Reserved use for TI. The pin must be left floating (NC).
Reserved use for TI. The pin must be left floating (NC).
In Pin mode:
—
—
30
I, 5-level / I/O, Sets receiver detect state machine options as provided in 表7-3. The pin is sampled at
3.3 V
LVCMOS,
open drain
device power-up only.
RX_DET / SCL
62
In SMBus/I2C mode:
3.3V SMBus/I2C clock. External 1 kΩ to 5 kΩ pullup resistor is required as per SMBus /
I2C interface standard.
Inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor from
the pin to internal CM bias voltage. Channel 0.
RX0N
RX0P
RX1N
RX1P
RX2N
RX2P
RX3N
RX3P
RX4N
RX4P
RX5N
RX5P
RX6N
RX6P
RX7N
RX7P
2
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Non-inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor
from the pin to internal CM bias voltage. Channel 0.
Inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor from
the pin to internal CM bias voltage. Channel 1.
5
Non-inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor
from the pin to internal CM bias voltage. Channel 1.
4
Inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor from
the pin to internal CM bias voltage. Channel 2.
8
Non-inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor
from the pin to internal CM bias voltage. Channel 2.
7
Inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor from
the pin to internal CM bias voltage. Channel 3.
11
10
14
13
17
16
20
19
23
22
Non-inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor
from the pin to internal CM bias voltage. Channel 3.
Inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor from
the pin to internal CM bias voltage. Channel 4.
Non-inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor
from the pin to internal CM bias voltage. Channel 4.
Inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor from
the pin to internal CM bias voltage. Channel 5.
Non-inverting differential inputs to the equalizer. An on-chip, 100 Ωtermination resistor
connects RXP to RXN. Channel 5.
Inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor from
the pin to internal CM bias voltage. Channel 6.
Non-inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor
from the pin to internal CM bias voltage. Channel 6.
Inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor from
the pin to internal CM bias voltage. Channel 7.
Non-inverting differential inputs to the equalizer. Integrated 50 Ωtermination resistor
from the pin to internal CM bias voltage. Channel 7.
TX0N
TX0P
TX1N
TX1P
TX2N
TX2P
TX3N
TX3P
TX4N
54
55
51
52
48
49
45
46
42
O
O
O
O
O
O
O
O
O
Inverting pin for 100 Ω differential driver output. Channel 0.
Non-inverting pin for 100 Ω differential driver output. Channel 0.
Inverting pin for 100 Ω differential driver output. Channel 1.
Non-inverting pin for 100 Ω differential driver output. Channel 1.
Inverting pin for 100 Ω differential driver output. Channel 2.
Non-inverting pin for 100 Ω differential driver output. Channel 2.
Inverting pin for 100 Ω differential driver output. Channel 3.
Non-inverting pin for 100 Ω differential driver output. Channel 3.
Inverting pin for 100 Ω differential driver output. Channel 4.
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表5-1. Pin Functions (continued)
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
43
39
40
36
37
33
34
TX4P
O
O
O
O
O
O
O
Non-inverting pin for 100 Ω differential driver output. Channel 4.
Inverting pin for 100 Ω differential driver output. Channel 5.
Non-inverting pin for 100 Ω differential driver output. Channel 5.
Inverting pin for 100 Ω differential driver output. Channel 6.
Non-inverting pin for 100 Ω differential driver output. Channel 6.
Inverting pin for 100 Ω differential driver output. Channel 7.
Non-inverting pin for 100 Ω differential driver output. Channel 7.
TX5N
TX5P
TX6N
TX6P
TX7N
TX7P
Power supply pins. VCC = 3.3 V ±10%. The VCC pins on this device should be
connected through a low-resistance path to the board VCC plane. Install a decoupling
capacitor to GND near each VCC pin.
VCC
6, 18, 38, 50
3, 15, 35, 47
P
Reserved pins –for best signal integrity performance connect the pins to GND.
Alternate option would be 0 Ω resistors from pins to GND.
RSVD2, 3, 4, 5
—
(1) I = input, O = output, P = power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
4.0
UNIT
V
VCCABSMAX
VIOCMOS,ABSMAX
VIO5LVL,ABSMAX
VIOHS-RX,ABSMAX
VIOHS-TX,ABSMAX
TJ,ABSMAX
Supply Voltage (VCC)
3.3 V LVCMOS and Open Drain I/O voltage
5-level Input I/O voltage
4.0
V
2.75
3.2
V
High-speed I/O voltage (RXnP, RXnN)
High-speed I/O voltage (TXnP, TXnN)
Junction temperature
V
2.75
150
150
V
°C
°C
Tstg
Storage temperature range
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2 kV
may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
DC plus AC power should not
exceed these limits
VCC
NVCC
Supply voltage, VCC to GND
Supply noise tolerance
3.0
3.3
3.6
V
DC to <50 Hz, sinusoidal1
250
100
33
mVpp
mVpp
mVpp
50 Hz to 500 kHz, sinusoidal1
500 kHz to 2.5 MHz, sinusoidal1
Supply noise, >2.5 MHz,
sinusoidal1
10
mVpp
TRampVCC
VCC supply ramp time
From 0 V to 3.0 V
0.150
100
85
ms
°C
°C
TA
TJ
Operating ambient temperature
Operating junction temperature
Minimum pulse width required for
−40
All device modes
125
PWLVCMOS the device to detect a valid signal PD1/0, and READ_EN_N
on LVCMOS inputs
200
μs
SMBus/I2C SDA and SCL Open Supply voltage for open drain
VCCSMBUS
3.6
V
Drain Termination Voltage
pull-up resistor
SMBus/I2C clock (SCL) frequency
in SMBus secondary mode
FSMBus
10
400
kHz
Source differential launch
amplitude
VIDLAUNCH
DR
800
1
1200
32
mVpp
Gbps
Data rate
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6.4 Thermal Information
DS320PR810
THERMAL METRIC(1)
UNIT
NJX, 64 Pins
RθJA-High K
RθJC(top)
RθJB
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
22.9
9.6
7.2
1.8
7.1
2.5
℃/W
℃/W
℃/W
℃/W
℃/W
℃/W
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 DC Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power
8 channels active, EQ = 0-2
8 channels active, EQ = 5-19
1.15
1.41
1.42
1.75
W
W
PACT
Device active power
Device power consumption while
waiting for far end receiver
terminations
All channels enabled but no far end
receiver detected
PRXDET
166
23
mW
mW
Device power consumption in standby
power mode
PSTBY
All channels disabled (PD1,0 = H)
Control IO
VIH
SDA, SCL, PD1, PD0, READ_EN_N
pins
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
Input high leakage current
Input low leakage current
2.1
2.1
V
V
SDA, SCL, PD1, PD0, READ_EN_N
pins
VIL
1.08
Rpull-up = 4.7 kΩ (SDA, SCL,
ALL_DONE_N pins)
VOH
VOL
IIH
V
IOL = –4 mA (SDA, SCL,
ALL_DONE_N pins)
0.4
10
V
VInput = VCC, (SCL, SDA, PD1, PD0,
READ_EN_N pins)
µA
µA
µA
pF
VInput = 0 V, (SCL, SDA, PD1, PD0,
READ_EN_N pins)
IIL
−10
Input high leakage current for fail safe VInput = 3.6 V, VCC = 0 V, (SCL, SDA, ,
IIH,FS
CIN-CTRL
200
10
input pins
PD1, PD0, READ_EN_N pins)
SDA, SCL, PD1, PD0,
READ_EN_Npins
Input capacitance
1.6
5 Level IOs (MODE, GAIN0, GAIN1, EQ0_0, EQ1_0, EQ0_1, EQ1_1, RX_DET pins)
IIH_5L
IIL_5L
Input high leakage current, 5-level IOs VIN = 2.5 V
µA
µA
Input low leakage current for all 5-level
VIN = GND
−10
IOs except MODE.
Input low leakage current for MODE
pin
IIL_5L,MODE
VIN = GND
µA
−200
Receiver
VRX-DC-CM
ZRX-DC
RX DC Common Mode Voltage
Rx DC Single-Ended Impedance
Device is in active or standby state
1.4
50
V
Ω
ZRX-HIGH-IMP- DC input CM input impedance during
Inputs are at VRX-DC-CM voltage
15
kΩ
Reset or power-down
DC-POS
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6.5 DC Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Transmitter
ZTX-DIFF-DC
VTX-DC-CM
ITX-SHORT
Impedance of Tx during active
signaling, VID,diff = 1 Vpp
DC Differential Tx Impedance
Tx DC common mode Voltage
Tx Short Circuit Current
100
1.0
70
Ω
V
Total current the Tx can supply when
shorted to GND
mA
6.6 High Speed Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Receiver
50 MHz to 1.25 GHz
dB
dB
dB
dB
dB
dB
dB
dB
−22
−19
−16
−12
−9
1.25 GHz to 2.5 GHz
2.5 GHz to 4.0 GHz
4.0 GHz to 8.0 GHz
8.0 GHz to 16 GHz
50 MHz to 2.5 GHz
2.5 GHz to 8.0 GHz
8.0 GHz to 16 GHz
RLRX-DIFF
Input differential return loss
−16
−9
RLRX-CM
Input common-mode return loss
−6
Receiver-side pair-to-pair isolation;
Port A or Port B
Minimum over 10 MHz to 16 GHz
range
XTRX
dB
−40
Transmitter
Measured with lowest EQ, GAIN = L4;
PRBS-7, 32 Gbps, over at least
106 bits using a bandpass-Pass Filter
from 30 Khz - 500 Mhz
Tx AC Peak-to-Peak Common Mode
Voltage
VTX-AC-CM-PP
50
120
600
mVpp
mV
VTX-CM-DC = |VOUTn+ + VOUTn–|/2,
Absolute Delta of DC Common Mode Measured by taking the absolute
VTX-CM-DC-
0
0
ACTIVE-IDLE-
DELTA
Voltage during L0 and Electrical Idle
difference of VTX-CM-DC during PCIe
state L0 and Electrical Idle
Measured while Tx is sensing whether
a low-impedance Receiver is present.
No load is connected to the driver
output
VTX-RCV-
Amount of Voltage change allowed
during Receiver Detection
mV
DETECT
50 MHz to 1.25 GHz
1.25 GHz to 2.5 GHz
2.5 GHz to 4.0 GHz
4.0 GHz to 8.0 GHz
8.0 Ghz to 16 Ghz
50 MHz to 2.5 GHz
2.5 GHz to 8.0 GHz
8.0 GHz to 16 GHz
dB
dB
dB
dB
dB
dB
dB
dB
−22
−21
−19
−14
−10
−14
−10
−7
RLTX-DIFF
Output differential return loss
RLTX-CM
Output Common-mode return loss
Transmit-side pair-to-pair isolation
Minimum over 10 MHz to 16 GHz
range
XTTX
dB
−40
Device Datapath
Input-to-output latency (propagation
delay) through a data channel
For either Low-to-High or High-to-Low
transition.
TPLHD/PHLD
100
140
ps
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6.6 High Speed Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Between any two lanes within a single
transmitter.
LTX-SKEW
Lane-to-Lane Output Skew
20
ps
Jitter through redriver minus the
calibration trace. 32 Gbps PRBS15.
800 mVpp-diff input swing.
TRJ-DATA
Additive Random Jitter with data
75
40
fs
fs
Jitter through redriver minus the
calibration trace. 16 Ghz CK. 800
mVpp-diff input swing.
Intrinsic additive Random Jitter with
clock
TRJ-INTRINSIC
Jitter through redriver minus the
calibration trace. 32 Gbps PRBS15.
800 mVpp-diff input swing.
JITTERTOTAL-
Additive Total Jitter with data
1.5
1.7
ps
ps
DATA
Jitter through redriver minus the
Intrinsic additive Total Jitter with clock calibration trace. 16 Ghz CK. 800
mVpp-diff input swing.
JITTERTOTAL-
INTRINSIC
Minimum EQ, GAIN1/0 = L0
dB
dB
dB
dB
dB
−5.6
−3.8
−1.2
2.6
Minimum EQ, GAIN1/0 = L1
Broadband DC and AC flat gain - input
to output, measured at DC
FLAT-GAIN
EQ-MAX16G
Minimum EQ, GAIN1/0 = L2
Minimum EQ, GAIN1/0 = L3
Minimum EQ, GAIN1/0 = L4 (Float)
0.6
EQ boost at max setting (EQ INDEX = AC gain at 16 GHz relative to gain at
19)
22
dB
dB
100 MHz.
FLAT-
GAINVAR
Flat gain variation across PVT
measured at DC
GAIN1/0 = L4, minimum EQ setting.
Max-Min.
1.5
4.0
−2.5
−3.0
At 16 Ghz. GAIN1/0 = L4, maximum
EQ setting. Max-Min.
EQ-GAINVAR EQ boost variation across PVT
dB
LINEARITY-
Output DC Linearity
DC
at GAIN1/0 = L4
at GAIN1/0 = L4
1700
700
mVpp
mVpp
LINEARITY-
Output AC Linearity at 32Gbps
AC
6.7 SMBUS/I2C Timing Charateristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Secondary Mode
Pulse width of spikes which must be
suppressed by the input filter
tSP
50
ns
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
tHD-STA
0.6
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
1.3
0.6
µs
µs
THIGH
Set-up time for a repeated START
condition
tSU-STA
0.6
µs
tHD-DAT
TSU-DAT
Data hold time
Data setup time
0
µs
µs
0.1
Rise time of both SDA and SCL
signals
tr
120
2
ns
Pull-up resistor = 4.7 kΩ, Cb = 10 pF
Pull-up resistor = 4.7 kΩ, Cb = 10 pF
tf
Fall time of both SDA and SCL signals
Set-up time for STOP condition
ns
µs
tSU-STO
0.6
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6.7 SMBUS/I2C Timing Charateristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Bus free time between a STOP and
START condition
tBUF
1.3
µs
tVD-DAT
tVD-ACK
Cb
Data valid time
0.9
0.9
µs
µs
pF
Data valid acknowledge time
Capacitive load for each bus line
400
Primary Mode
fSCL-M
SCL clock frequency
SCL low period
303
1.90
1.40
kHz
µs
tLOW-M
THIGH-M
SCL high period
µs
Set-up time for a repeated START
condition
tSU-STA-M
2
µs
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
tHD-STA-M
1.5
TSU-DAT-M
tHD-DAT-M
Data setup time
Data hold time
1.4
0.5
µs
µs
Rise time of both SDA and SCL
signals
tR-M
120
ns
Pull-up resistor = 4.7 kΩ, Cb = 10 pF
Pull-up resistor = 4.7 kΩ, Cb = 10 pF
TF-M
Fall time of both SDA and SCL signals
Stop condition setup time
2
ns
µs
tSU-STO-M
1.5
EEPROM Timing
TEEPROM EEPROM configuration load time
TPOR Time to first SMBus access
Time to assert ALL_DONE_N after
READ_EN_N has been asserted.
7.5
50
ms
ms
Power supply stable after initial ramp.
Includes initial power-on reset time.
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6.8 Typical Characteristics
图6-1 shows typical EQ gain curves versus frequency for different EQ settings. 图6-2 shows EQ gain variation over
temperature for maximum EQ setting of 19. 图6-3 shows typical differential return loss for Rx and Tx pins.
30
25
20
15
10
5
30
25
20
15
10
5
0
0
-5
EQ=0
EQ=1
EQ=2
EQ=3
EQ=4
EQ=5
EQ=6
EQ=7
EQ=8
EQ=9
EQ=10
EQ=11
EQ=12
EQ=13
EQ=14
EQ=15
EQ=16
EQ=17
EQ=18
EQ=19
-5
-10
-15
-20
Temperature = 25 C
Temperature = 0 C
Temperature = 85 C
-10
-15
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Frequency (GHz)
Frequency (GHz)
图6-1. Typical EQ Boost vs Frequency
图6-2. Typical EQ Boost vs Frequency at Different Temperature
with EQ=19
5
0
-5
-10
-15
-20
-25
-30
-35
-40
RX SD11
TX SD22
PCIe 5.0 Mask
0
5
10
15
20
25
30
35
40
Frequency (GHz)
图6-3. Typical Differential Return Loss
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6.9 Typical Jitter Characteristics
图6-4 , 图6-5, and 图6-6 show eye diagrams at BERT source output, through calibration traces, and through 810
respectively. Note: 810 adds little to no random jitter. Residual equalization of ≅4 dB at EQ = 0 setting results in slightly lower
deterministic jitter through DUT compared to baseline setup with 7 dB loss.
图6-4. At BERT Source Output (1 dB Loss)
图6-5. Through Baseline Calibration Trace Setup (7 dB Loss)
图6-6. Through DS320PR810 (7 dB Loss and DUT EQ = 0)
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7 Detailed Description
7.1 Overview
The DS320PR810 is an eight-channel multi-rate linear repeater with integrated signal conditioning. The device's
signal channels operate independently from one another. Each channel includes a continuous-time linear
equalizer (CTLE) and a linear output driver, which together compensate for a lossy transmission channel
between the source transmitter and the final receiver. The linearity of the data path is specifically designed to
preserve any transmit equalization while keeping receiver equalization effective.
The DS320PR810 can be configured three different ways:
Pin mode – device control configuration is done solely by strap pins. Pin mode is expected to be good enough
for many system implementation needs.
SMBus/I2C Primary mode – device control configuration is read from external EEPROM. When the
DS320PR810 has finished reading from the EEPROM successfully, it will drive the ALL_DONE_N pin LOW.
SMBus/I2C secondary operation is available in this mode before, during, or after EEPROM reading. Note: during
EEPROM reading, if the external SMBus/I2C primary wants to access DS320PR810 registers, then it must
support arbitration. The mode is preferred when software implementation is not desired.
SMBus/I2C Secondary mode – provides most flexibility. Requires a SMBus/I2C primary device to configure
DS320PR810 though writing to its secondary address.
7.2 Functional Block Diagram
One Channel of Eight
Term
Term
RXnP
RXnN
TXnP
TXnN
Linear
Driver
CTLE
Receiver
Detect
Design for
Production
Testing
Linear Voltage
Regulators
Analog Bias
Circuits
VCC
Power-
On Reset
Always-On
10MHz
Digital Core
GAIN0/SDA
READ_EN_N
ALL_DONE_N
RX_DET/SCL
GND
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7.3 Feature Description
7.3.1 Linear Equalization
The DS320PR810 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency boost
and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of the passive
channel. The receivers implement two stage linear equalizer for wide range of equalization capability. The
equalizer stages also provide flexibility to make subtle modifications of mid-frequency boost for best EQ gain
profile match with wide range of channel media characteristics. The EQ profile control feature is only available in
SMBus/I2C mode. In Pin mode the settings are optimized for FR4 traces.
表 7-1 provides available equalization boost through EQ control pins or SMBus/I2C registers. In Pin Control
mode EQ1_0 and EQ0_0 pins set equalization boost for channels 0-3 (Bank 0) and EQ1_1 and EQ0_1 for
channels 4-7 (Bank 1). In I2C mode individual channels can be independently programmed for EQ boost.
表7-1. Equalization Control Settings
EQUALIZATION SETTING
SMBus/I2C Mode
TYPICAL EQ BOOST (dB)
Pin mode
0
1
L0
L0
L0
L1
L1
L1
L1
L1
L2
L2
L2
L2
L2
L3
L3
L3
L3
L3
L0
L1
L2
L0
L1
L2
L3
L4
L0
L1
L2
L3
L4
L0
L1
L2
L3
L4
0
1
0
0
0
0
0
0
0
0
1
1
1
1
2
3
4
5
6
7
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3.0
4.0
4.0
6.0
2
3
0
5.5
8.0
5
0
1
6.5
10.5
11.5
12.5
13.0
14.0
15.0
15.5
16.5
17.0
18.0
19.0
19.5
20.5
21.0
22.0
6
1
1
7.0
7
2
1
7.5
8
3
3
8.5
9
4
3
9.0
10
11
12
13
14
15
16
17
18
19
5
7
10.0
10.5
11.0
12.0
12.5
13.0
14.0
14.5
15.5
16.0
6
7
8
7
10
10
11
12
13
14
15
7
15
15
15
15
15
15
7.3.2 Flat-Gain
The GAIN1 and GAIN0 pins can be used to set the overall data-path flat gain (DC and AC) of the DS320PR810
when the device is in Pin mode. The pin GAIN0 sets the Flat-Gain for channels 0-3 (Bank 0) and GAIN1 sets the
same for channels 4-7 (Bank 1). In I2C mode each channel can be independently set. 表 7-2 provides flat gain
control configuration settings. In the default recommendation for most systems will be GAIN1,0 = L4 (float) that
provides flat gain of 0 dB.
The flat-gain and equalization of the DS320PR810 must be set such that the output signal swing at DC and high
frequency does not exceed the DC and AC linearity ranges of the devices, respectively.
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表7-2. Flat Gain Configuration Settings
Pin mode GAIN0/1
I2C Modeflat_gain_2:0
Flat Gain
-6 dB
L0
L1
0
1
3
5
7
-4 dB
L2
-2 dB
L4 (float)
L3
0 dB (default recommendation)
+2 dB
7.3.3 Receiver Detect State Machine
The DS320PR810 deploys an Rx detect state machine that governs the Rx detection cycle as defined in the PCI
express specifications. At power up or after a manual PD0/1 toggle the redriver determines whether or not a
valid PCI express termination is present at the far end receiver. The RX_DET pin of DS320PR810 provides
additional flexibility for system designers to appropriately set the device in desired mode as provided in 表 7-3.
PD0 and PD1 pins impact channel groups 0-3 and 4-7 respectively. If all eight channels of DS320PR810 is used
for a same PCI express link, then the PD1 and PD0 pins can be shorted and driven together. For most
applications the RX_DET pin can be left floating for default settings. In SMBus/I2C mode each channel can be
configured independently.
表7-3. Receiver Detect State Machine Settings
Channels 0-3
Rx Common-mode
Impedance
Channels 4-7
Rx Common-mode
Impedance
PD0
PD1
RX_DET
COMMENTS
PCI Express Rx detection state machine is
disabled. Recommended for non PCIe interface
use case where the DS320PR810 is used as
buffer with equalization.
L
L
L
L
L0
L1
Always 50 Ω
Always 50 Ω
Pre Detect: Hi-Z
Post Detect: 50 Ω.
Pre Detect: Hi-Z
Post Detect: 50 Ω.
Outputs polls until 3 consecutive valid detections
Pre Detect: Hi-Z
Post Detect: 50 Ω.
Pre Detect: Hi-Z
Post Detect: 50 Ω.
L
L
L
L
L2
L3
Outputs polls until 2 consecutive valid detections
Reserved
NA
NA
Tx polls every ≅150 µs until valid termination is
detected. Rx CM impedance held at Hi-Z until
detection Reset by asserting PD0/1 high for 200 µs
then low.
Pre Detect: Hi-Z
Post Detect: 50 Ω.
Pre Detect: Hi-Z
Post Detect: 50 Ω.
L
L
L4 (Float)
Pre Detect: Hi-Z
Post Detect: 50 Ω.
Reset Channels 0-3 signal path and set their Rx
impedance to Hi-Z
H
L
L
X
X
Hi-Z
H
Pre Detect: Hi-Z
Post Detect: 50 Ω.
Hi-Z
Hi-Z
Reset Channels 4-7 signal path and set their Rx
impedance to Hi-Z.
H
H
X
Hi-Z
In PCIe applications PD0/1 pins can be connected to PCIe sideband signals PERST# with inverted polarity or
one or more appropriate PRSNTx# signals to achieve desired RX detect functionality.
7.4 Device Functional Modes
7.4.1 Active PCIe Mode
The device is in normal operation with PCIe state machine enabled by RX_DET = L1/L2/L4. In this mode PD0
and PD1 pins are driven low in a system (for example, by PCIE connector PRSNTx# or fundamental reset
PERST# signal). In this mode, the DS320PR810 redrives and equalizes PCIe Rx or Tx signals to provide better
signal integrity.
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7.4.2 Active Buffer Mode
The device is in normal operation with PCIe state machine disabled by RX_DET = L0. This mode is
recommended for non-PCIe use cases. In this mode the device is working as a buffer to provide linear
equalization to improve signal integrity.
7.4.3 Standby Mode
The device is in standby mode invoked by PD1,0 = H. In this mode, the device is in standby mode conserving
power.
7.5 Programming
7.5.1 Pin mode
The DS320PR810 can be fully configured through pin-strap pins. In this mode the device uses 2-level and 5-
level pins for device control and signal integrity optimum settings.
7.5.1.1 Five-Level Control Inputs
The DS320PR810 has eight (EQ0_0, EQ1_0, EQ0_1, EQ1_1, GAIN0, GAIN1, MODE, and RX_DET) 5-level
input pins that are used to control the configuration of the device. These 5-level inputs use a resistor divider to
help set the 5 valid levels and provide a wider range of control settings. External resistors must be of 10%
tolerance or better. The EQ0_0, EQ1_0, EQ0_1, EQ1_1, GAIN0, GAIN1, and RX_DET pins are sampled at
power-up only. The MODE pin can be exercised at device power up or in normal operation mode.
表7-4. 5-level Control Pin Settings
LEVEL
L0
SETTING
1 kΩ to GND
8.25 kΩ to GND
24.9 kΩ to GND
75 kΩ to GND
F (Float)
L1
L2
L3
L4
7.5.2 SMBUS/I2C Register Control Interface
If MODE = L2 (SMBus/I2C Secondary control mode), then the DS320PR810 is configured through a standard
I2C or SMBus interface that may operate up to 400 kHz. The secondary address of the DS320PR810 is
determined by the pin strap settings on the ADDR1 and ADDR0 pins. Note: secondary addresses to access
channels 0-3 (Bank 0) and channels 4-7 (Bank 1) are different. Channel Bank 1 has address which is Channel
Bank 0 address +1. The sixteen possible secondary addresses for each channel bank of the DS320PR810 are
provided in 表 7-5. In SMBus/I2C modes the SCL and SDA pins must be pulled up to a 3.3 V supply with a pull-
up resistor. The value of the resistor depends on total bus capacitance. 4.7 kΩis a good first approximation for a
bus capacitance of 10 pF.
表7-5. SMBUS/I2C Secondary Address Settings
7-bit Secondary Address Channels 0-3 7-bit Secondary Address Channels 4-7
ADDR1
ADDR0
(Bank 0)
(Bank 1)
L0
L0
L0
L0
L0
L1
L1
L1
L1
L0
L1
L2
L3
L4
L0
L1
L2
L3
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
Reserved
0x20
Reserved
0x21
0x22
0x23
0x24
0x25
0x26
0x27
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表7-5. SMBUS/I2C Secondary Address Settings (continued)
7-bit Secondary Address Channels 0-3 7-bit Secondary Address Channels 4-7
ADDR1
ADDR0
(Bank 0)
Reserved
0x28
(Bank 1)
Reserved
0x29
L1
L2
L2
L2
L2
L2
L3
L3
L3
L3
L3
L4
L0
L1
L2
L3
L4
L0
L1
L2
L3
L4
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
Reserved
0x30
Reserved
0x31
0x32
0x33
0x34
0x35
0x36
0x37
Reserved
Reserved
The DS320PR810 has two types of registers:
• Shared Registers: these registers can be accessed at any time and are used for device-level configuration,
status read back, control, or to read back the device ID information.
• Channel Registers: these registers are used to control and configure specific features for each individual
channel. All channels have the same register set and can be configured independent of each other or
configured as a group through broadcast writes to Bank 0 or Bank 1.
The DS320PR810 features two banks of channels, Bank 0 (Channels 0-3) and Bank 1 (Channels 4-7), each
featuring a separate register set and requiring a unique SMBus secondary address.
Channel Registers Base
Address
Channel Bank 0 Access
Channel Bank 1 Access
0x00
0x20
0x40
0x60
0x80
Channel 0 registers
Channel 1 registers
Channel 2 registers
Channel 3 registers
Channel 4 registers
Channel 5 registers
Channel 6 registers
Channel 7 registers
Broadcast write channel Bank 0 registers,
read channel 0 registers
Broadcast write channel Bank 1 registers,
read channel 4 registers
0xA0
0xC0
Broadcast write channel 0-1 registers,
read channel 0 registers
Broadcast write channel 4-5 registers,
read channel 4 registers
Broadcast write channel 2-3 registers,
read channel 2 registers
Broadcast write channel 6-7 registers,
read channel 6 registers
0xE0
Bank 0 Share registers
Bank 1 Share registers
7.5.2.1 Shared Registers
表7-6. General Registers (Offset = 0xE2)
Bit
7
Field
Type
Reset
Description
RESERVED
rst_i2c_regs
R
0x0
Reserved
6
R/W/SC
0x0
Device reset control: Reset all I2C registers to default values
(self-clearing).
5
4-1
0
rst_i2c_mas
RESERVED
frc_eeprm_rd
R/W/SC
R
0x0
0x0
0x0
Reset I2C Primary (self-clearing).
Reserved
R/W/SC
Override MODE and READ_EN_N status to force manual
EEPROM configuration load.
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表7-7. EEPROM_Status Register (Offset = 0xE3)
Bit
7
Field
Type
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
eecfg_cmplt
eecfg_fail
R
EEPROM load complete.
EEPROM load failed.
6
R
5
eecfg_atmpt_1
eecfg_atmpt_0
eecfg_cmplt
eecfg_fail
R
Number of attempts made to load EEPROM image.
see MSB
4
R
3
R
EEPROM load complete 2.
EEPROM load failed 2.
2
R
1
eecfg_atmpt_1
eecfg_atmpt_0
R
Number of attempts made to load EEPROM image 2.
see MSB
0
R
表7-8. DEVICE_ID0 Register (Offset = 0xF0)
Bit
7-4
3
Field
Type
Reset
0x0
0x0
0x1
0x1
X
Description
RESERVED
device_id0_3
device_id0_2
device_id0_1
RESERVED
R
Reserved
R
Device ID0 [3:1]: 011
see MSB
2
R
1
R
see MSB
0
R
Reserved
表7-9. DEVICE_ID1 Register (Offset = 0xF1)
Bit
7
Field
Type
Reset
0x0
0x0
0x1
0x0
0x1
0x0
0x0
0x0
Description
device_id[7]
device_id[6]
device_id[5]
device_id[4]
device_id[3]
device_id[2]
device_id[1]
device_id[0]
R
Device ID 0010 1001: DS320PR810
6
R
see MSB
see MSB
see MSB
see MSB
see MSB
see MSB
see MSB
5
R
4
R
3
R
2
R
1
R
0
R
7.5.2.2 Channel Registers
表7-10. RX Detect Status Register (Channel register base + Offset = 0x00)
Bit
Field
Type
Reset
Description
7
rx_det_comp_p
R
0x0
Rx Detect positive data pin status:
0: Not detected
1: Detected –the value is latched
6
rx_det_comp_n
RESERVED
R
R
0x0
0x0
Rx Detect negative data pin status:
0: Not detected
1: Detected –the value is latched
5-0
Reserved
表7-11. EQ Gain Control Register (Channel register base + Offset = 0x01)
Bit
Field
Type
Reset
Description
7
eq_stage1_bypass
R/W
0x0
Enable EQ stage 1 bypass:
0: Bypass disabled
1: Bypass enabled
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表7-11. EQ Gain Control Register (Channel register base + Offset = 0x01) (continued)
Bit
6
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
eq_stage1_3
eq_stage1_2
eq_stage1_1
eq_stage1_0
eq_stage2_2
eq_stage2_1
eq_stage2_0
EQBoost stage 1 control
5
See 表7-1 for details
4
3
2
EQ Boost stage 2 control
1
See 表7-1 for details
0
表7-12. EQ Gain / Flat Gain Control Register (Channel register base + Offset = 0x03)
Bit
7
Field
Type
Reset
0x0
0x0
0x0
0x0
0x0
0x1
0x0
0x1
Description
RESERVED
eq_profile_3
eq_profile_2
eq_profile_1
eq_profile_0
flat_gain_2
flat_gain_1
flat_gain_0
R
Reserved
6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EQ mid-frequency boost profile
5
See 表7-1 for details
4
3
2
Flat gain select:
1
See 表7-2 for details
0
表7-13. RX Detect Control Register (Channel register base + Offset = 0x04)
Bit
7-3
2
Field
Type
Reset
Description
RESERVED
mr_rx_det_man
R
0x0
Reserved
R/W
0x0
Manual override of rx_detect_p/n decision:
0: rx detect state machine is enabled
1: rx detect state machine is overridden –always valid RX
termination detected
1
0
en_rx_det_count
sel_rx_det_count
R/W
R/W
0x0
0x0
Enable additional RX detect polling
0: Additional RX detect polling disabled
1: Additional RX detect polling enabled
Select number of valid RX detect polls –gated by
en_rx_det_count = 1
0: Device transmitters poll until 2 consecutive valid detections
1: Device transmitters poll until 3 consecutive valid detections
表7-14. PD Override Register (Channel register base + Offset = 0x05)
Bit
Field
Type
Reset
Description
7
device_en_override
R/W
0x0
Enable power down overrides thorugh SMBus/I2C
0: Manual override disabled
1: Manual override enabled
6-0
device_en
R/W
0x111111
Manual power down of redriver various blocks –gated by
device_en_override = 1
111111: All blocks are enabled
000000: All blocks are disabled
表7-15. Bias Register (Channel register base + Offset = 0x06)
Bit
Field
Type
Reset
Description
5-3
Bias current
R/W
0x100
Control bias current
Set 001 for best performance
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表7-15. Bias Register (Channel register base + Offset = 0x06) (continued)
Bit
Field
Type
Reset
Description
7,6,2-0
Reserved
R/W
0x00000
Reserved
7.5.3 SMBus/I2C Primary Mode Configuration (EEPROM Self Load)
The DS320PR810 can also be configured by reading from EEPROM. To enter into this mode MODE pin must be
set to L1. The EEPROM load operation only happens once after the device's initial power-up. If the
DS320PR810 is configured for SMBus Primary mode, then it will remain in the SMBus IDLE state until the
READ_EN_N pin is asserted to LOW. After the READ_EN_N pin is driven LOW, the DS320PR810 becomes an
SMBus primary and attempts to self-configure by reading the device settings stored in an external EEPROM
(SMBus 8-bit address 0xA0). When the DS320PR810 has finished reading from the EEPROM successfully, it will
drive the ALL_DONE_N pin LOW. SMBus/I2C secondary operation is available in this mode before, during, or
after EEPROM reading. Note: during EEPROM reading, if the external SMBus/I2C primary wants to access
DS320PR810 registers, then it must support arbitration.
When designing a system for using the external EEPROM, the user must follow these specific guidelines:
• EEPROM size of 2 kb (256 × 8-bit) is recommended.
• Set MODE = L1, configure for SMBus Primary mode.
• The external EEPROM device address byte must be 0xA0 and capable of 400 kHz operation at 3.3 V supply
• In SMBus/I2C modes the SCL and SDA pins must be pulled up to a 3.3 V supply with a pull-up resistor. The
value of the resistor depends on total bus capacitance. 4.7 kΩis a good first approximation for a bus
capacitance of 10 pF.
图 7-1 shows a use case with four DS320PR810 to implement a PCIe x16 configuration, but the user can
cascade any number of DS320PR810 devices in a similar way. Tie the READ_EN_N pin of the first device low to
automatically initiate EEPROM read at power up. Alternatively, the READ_EN_N pin of the first device can also
be controlled by a micro-controller to initiate the EEPROM read manually. Leave the ALL_DONE_N pin of the
final device floating, or connect the pin to a micro-controller input to monitor the completion of the final EEPROM
read.
图7-1. Daisy Chain Four DS320PR810 Devices to Read from Single EEPROM in x16 Configuration
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The DS320PR810 is a high-speed linear repeater which extends the reach of differential channels impaired by
loss from transmission media like PCBs and cables. It can be deployed in a variety of different systems. The
following sections outline typical applications and their associated design considerations.
8.2 Typical Applications
The DS320PR810 is a PCI Express linear redriver that can also be configured as interface agnostic redriver by
disabling its Rx detect feature. The device can be used in wide range of interfaces including:
• PCI Express 1.0, 2.0, 3.0, 4.0, and 5.0
• Ultra Path Interconnect (UPI) 1.0 and 2.0
• DisplayPort 2.0
The DS320PR810 is a protocol agnostic 8-channel 4-lane linear redriver with PCI Express receiver-detect
capability. Its protocol agnostic nature allows it to be used in PCI Express x4, x8, and x16 applications. 图 8-1
shows how a number of DS320PR810 devices can be used to obtain signal conditioning for PCI Express buses
of varying widths.
DS320PR810
DS320PR810
CPU/
Root
Complex
DS320PR810
DS320PR810
CPU/
Root
Dual X4 PCIe Link
Complex
DS320PR810
DS320PR810
CPU/
Root
Complex
DS320PR810
DS320PR810
X16 PCIe Link
X8 PCIe Link
图8-1. PCI Express x4, x8 and x16 Use Cases Using DS320PR 810
Note: all eight channels of the DS320PR810 flow in same direction. Therefore, if the device is used for dual x4
configuration with two devices, then PD0 of both devices need to be connected together to implement PCIe state
machine for the first x4 link while PD1 for the second x4 link.
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8.2.1 PCIe Reach Extension –x16 Lane Configuration
The DS320PR810 can be used in server or motherboard applications to boost transmit and receive signals to
increase the reach of the host or root complex processor to PCI Express slots or connectors. The following
sections outline detailed procedures and design requirements for a typical PCIe x16 lane configuration.
However, the design recommendations can be used in any lane configuration.
8.2.1.1 Design Requirements
As with any high-speed design, there are many factors which influence the overall performance. The following
list indicates critical areas for consideration during design.
• Use 85 Ωimpedance traces when interfacing with PCIe CEM connectors. Length matching on the P and N
traces should be done on the single-end segments of the differential pair.
• Use a uniform trace width and trace spacing for differential pairs.
• Place AC-coupling capacitors near the receiver end of each channel segment to minimize reflections.
• For PCIe Gen 3.0, 4.0, and 5.0, AC-coupling capacitors of 220 nF are recommended. Set the maximum body
size to 0402 and add a cutout void on the GND plane below the landing pad of the capacitor to reduce
parasitic capacitance to GND.
• Back-drill connector vias and signal vias to minimize stub length.
• Use reference plane vias to ensure a low inductance path for the return current.
8.2.1.2 Detailed Design Procedure
In PCIe Gen 3.0, 4.0, and 5.0 applications, the specification requires Rx-Tx (of root-complex and endpoint) link
training to establish and optimize signal conditioning settings at 8 Gbps, 16 Gbps, and 32 Gbps, respectively. In
link training, the Rx partner requests a series of FIR – preshoot and de-emphasis coefficients (10 Presets) from
the Tx partner. The Rx partner includes 7-levels of CTLE followed by a single tap DFE. The link training would
pre-condition the signal, with an equalized link between the root-complex and endpoint resulting an optimized
link. Note that there is no link training in PCIe Gen 1.0 (2.5 Gbps) or PCIe Gen 2.0 (5.0 Gbps) applications.
For operation in Gen 3.0, 4.0, and 5.0 links, the DS320PR810 is designed with linear data-path to pass the Tx
Preset signaling (by root complex and end point) onto the Rx (of root complex and end point) for the PCIe Gen
3.0, 4.0, or 5.0 link to train and optimize the equalization settings. The linear redriver DS320PR810 helps extend
the PCB trace reach distance by boosting the attenuated signals with its equalization, which allows the user to
recover the signal by the downstream Rx more easily. The device must be placed in between the Tx and Rx (of
root complex and end point) such a way that both Rx and Tx signal swing stays within the linearity range of the
device. Adjustments to the DS320PR810 EQ setting should be performed based on the channel loss to optimize
the eye opening in the Rx partner. The available EQ gain settings are provided in 表7-1. For most PCIe systems
the default flat gain setting 0 dB (GAIN = floating) would be sufficient. However, a flat gain attenuation can be
utilized to apply extra equalization when needed to keep the data-path linear.
The DS320PR810 can be optimized for a given system utilizing its three configuration modes – Pin mode,
SMBus/I2C Primary mode, and SMBus/I2C Secondary mode. In SMBus/I2C modes the SCL and SDA pins must
be pulled up to a 3.3 V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance.
4.7 kΩis a good first approximation for a bus capacitance of 10 pF.
In PCIe applications PD0/1 pins can be connected to PCIe sideband signals PERST# with inverted polarity or
one or more appropriate PRSNTx# signals to achieve desired RX detect functionality.
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图8-2 shows a simplified schematic for x16 lane configuration in Pin mode.
DS320PR810 TX Redrivers
One Channel of Eight
RXnP
RXnN
VCC
TXnP
TXnN
For brevity 1 of 8
channels (from each
DS320PR810) shown
For brevity 1 of 8
channels (from each
DS320PR810) shown
Redriver
Datapath
3.3V
1 F
Voltage
Regulators
Minimum
recommended
decoupling
RSVD2,3,4,5
Connect to GND
0.1 F
(4x)
1 k
GND
MODE
READ_EN_N
ALL_DONE_N
RSVD0,1
Sets Pin Mode
Shared Digital
Drive PD pins of all
redrivers with the inverted
PERST# or appropriate
PRSNT# signal from the
PCIe interface.
PD0
PD1
RX_DET
Two PR810
Pin strap to set
EQ gain
Pin strap to set
datapath DC gain
Two PR810
DS320PR810 RX Redrivers
One Channel of Eight
TXnP
TXnN
RXnP
RXnN
VCC
For brevity 1 of 8
channels (from each
DS320PR810) shown
For brevity 1 of 8
channels (from each
DS320PR810) shown
Redriver
Datapath
3.3V
Voltage
Regulators
Minimum
recommended
decoupling
RSVD2,3,4,5
Connect to GND
0.1 F
(4x)
1 F
1 k
READ_EN_N
ALL_DONE_N
RSVD0,1
MODE
Sets Pin Mode
GND
Shared Digital
Drive PD pins of all
PD0
PD1
redrivers with the inverted
PERST# or appropriate
PRSNT# signal from the
PCIe interface.
RX_DET
Pin strap to set
datapath DC gain
Pin strap to set
EQ gain
图8-2. Simplified Schematic for PCIe x16 Lane Configuration in Pin mode
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图8-3 shows a simplified schematic for x16 lane configuration in SMBus/I2C Primary mode.
DS320PR810 TX Redrivers
One Channel of Eight
RXnP
RXnN
VCC
TXnP
TXnN
For brevity 1 of 8
channels (from each
DS320PR810) shown
For brevity 1 of 8
channels (from each
DS320PR810) shown
Redriver
Datapath
3.3V
1 F
Voltage
Regulator
Minimum
recommended
decoupling
RSVD2,3,4,5
Connect to GND
0.1 F
(4x)
13 k
Sets SMBus
Primary Mode
MODE
READ_EN_N
ALL_DONE_N
GND
Shared Digital
Drive PD pins of all
redrivers with the inverted
PERST# or appropriate
PRSNT# signal from the
PCIe interface.
PD0
PD1
See figure titled
Example Daisy Chain
for Multiple Device
Single EEPROM
Configuration for
connections
Two PR810
4.7 k
4.7 k
Pin strap to set SMBus
Secondary address
Two PR810
DS320PR810 RX Redrivers
One Channel of Eight
TXnP
TXnN
RXnP
RXnN
VCC
For brevity 1 of 8
channels (from each
DS320PR810) shown
Redriver
Datapath
For brevity 1 of 8
channels (from each
DS320PR810) shown
3.3V
Voltage
Regulator
Minimum
recommended
decoupling
RSVD2,3,4,5
Connect to GND
0.1 F
(4x)
1 F
13 k
Sets SMBus
Primary Mode
READ_EN_N
ALL_DONE_N
MODE
GND
Shared Digital
Drive PD pins of all
PD0
PD1
redrivers with the inverted
PERST# or appropriate
PRSNT# signal from the
PCIe interface.
See figure titled
Example Daisy Chain
for Multiple Device
Single EEPROM
Configuration for
connections
4.7 k
4.7 k
Pin strap to set SMBus
Secondary address
图8-3. Simplified Schematic for PCIe x16 Lane Configuration in SMBus/I2C Primary mode
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图8-4 shows a simplified schematic for x16 lane configuration in SMBus/I2C Secondary mode.
DS320PR810 TX Redrivers
One Channel of Eight
RXnP
RXnN
VCC
TXnP
TXnN
For brevity 1 of 8
channels (from each
DS320PR810) shown
For brevity 1 of 8
channels (from each
DS320PR810) shown
Redriver
Datapath
3.3V
1 F
Voltage
Regulators
Minimum
recommended
decoupling
RSVD2,3,4,5
Connect to GND
0.1 F
(4x)
59 k
Sets SMBus
Secondary Mode
MODE
GND
READ_EN_N
RSVDx
Shared Digital
Drive PD pins of all
redrivers with the inverted
PERST# or appropriate
PRSNT# signal from the
PCIe interface.
PD0
PD1
ALL_DONE_N
Two PR810
4.7 k
4.7 k
Pin strap to set
SMBus Secondary
address
Two PR810
DS320PR810 RX Redrivers
One Channel of Eight
TXnP
TXnN
RXnP
RXnN
VCC
For brevity 1 of 8
channels (from each
DS320PR810) shown
For brevity 1 of 8
channels (from each
DS320PR810) shown
Redriver
Datapath
3.3V
Voltage
Regulators
Minimum
recommended
decoupling
RSVD2,3,4,5
Connect to GND
0.1 F
(4x)
1 F
59 k
Sets SMBus
Secondary Mode
MODE
READ_EN_N
RSVDx
GND
Shared Digital
Drive PD pins of all
PD0
PD1
redrivers with the inverted
PERST# or appropriate
PRSNT# signal from the
PCIe interface.
ALL_DONE_N
4.7 k
4.7 k
Pin strap to set
SMBus Secondary
address
图8-4. Simplified Schematic for PCIe x16 Lane Configuration in SMBus/I2C Secondary mode
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8.2.1.3 Application Curves
The DS320PR810 is a linear redriver that can be used to extend channel reach of a PCIe link. Normally, PCIe-
compliant Tx and Rx are equipped with signal-conditioning functions and can handle channel losses of up to 36
dB at 16 GHz. With the DS320PR810, the total channel loss between a PCIe root complex and an end point can
be extended up to 58 dB at 16 GHz.
To demonstrate the reach extension capability of the DS320PR810, two comparative setups are constructed. In
first setup as shown in 图8-5 there is no redriver in the PCIe 5.0 link. 图8-6 shows eye diagram at the end of the
link using SigTest. In second setup as shown in 图 8-7, the DS320PR810 is inserted in the middle to extend link
reach. 图8-8 shows SigTest eye diagram.
Keysight
M8040
BERT
Tek 33 GHz
Scope
10 M Math1
capture ->
SigTest
PCIe 5.0
Comp pa ern
P9 800 mV
Phoenix 5.0
PCIe 5.0
PCIe 5.0
Loss Board
Loss Board
PCIe 5.0
Baseboard
(CBB)
PCIe 5.0
Load Board
(CLB)
图8-5. PCIe 5.0 Link Baseline Setup Without
图8-6. PCIe 5.0 link Baseline Setup Without
Redriver the Link Elements
Redriver Eye Diagram Using SigTest
Keysight
M8040
BERT
Tek 33 GHz
Scope
10 M Math1
capture ->
SigTest
PCIe 5.0
Comp pa ern
P9 800 mV
Phoenix 5.0
PCIe 5.0
PCIe 5.0
Loss Board
Loss Board
PCIe 5.0
Baseboard
(CBB)
PCIe 5.0
Load Board
(CLB)
DS320PR810
Riser card
EQ=10, GAIN=L1
图8-7. PCIe 5.0 Link Setup with the DS320PR810
图8-8. PCIe 5.0 Link Setup with the DS320PR810
the Link Elements
Eye Diagram Using SigTest
表 8-1 summarizes the PCIe 5.0 links without and with the DS320PR810. The illustration shows that redriver is
capable of ≅22 dB reach extension at PCIe 5.0 speed with EQ = 10 (EQ gain of 16 dB) and GAIN1,2 = L1 (flat
gain of −4 dB). Note: actual reach extension depends on various signal integrity factors. It is recommended to
run signal intergrity simulations with all the components in the link to get any guidance.
表8-1. PCIe 5.0 Reach Extension using the DS320PR810
Setup
Pre Channel Loss
Post Channel Loss
Total Loss
Eye at BER 1E-12 SigTest Pass?
14 ps, 41 mV
14 ps, 33 mV
Pass
Pass
Baseline –no DUT
With DUT (DS320PR810)
—
—
≅36 dB
≅29 dB
≅29 dB
≅58 dB
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9 Power Supply Recommendations
Follow these general guidelines when designing the power supply:
1. The power supply should be designed to provide the operating conditions outlined in the recommended
operating conditions section in terms of DC voltage, AC noise, and start-up ramp time.
2. The DS320PR810 does not require any special power supply filtering, such as ferrite beads, provided that
the recommended operating conditions are met. Only standard supply decoupling is required. Typical supply
decoupling consists of a 0.1 µF capacitor per VCC pin, one 1.0 µF bulk capacitor per device, and one 10 µF
bulk capacitor per power bus that delivers power to one or more DS320PR810 devices. The local decoupling
(0.1 µF) capacitors must be connected as close to the VCC pins as possible and with minimal path to the
DS320PR810 ground pad.
3. The DS320PR810 voltage regulator output pins require decoupling caps of 0.1 µF near each pin. The
regulator is only for internal use. Do not use to provide power to any external component.
10 Layout
10.1 Layout Guidelines
The following guidelines should be followed when designing the layout:
1. Decoupling capacitors should be placed as close to the VCC pins as possible. Placing the decoupling
capacitors directly underneath the device is recommended if the board design permits.
2. High-speed differential signals TXnP/TXnN and RXnP/RXnN should be tightly coupled, skew matched, and
impedance controlled.
3. Vias should be avoided when possible on the high-speed differential signals. When vias must be used, take
care to minimize the via stub, either by transitioning through most or all layers or by back drilling.
4. GND relief can be used (but is not required) beneath the high-speed differential signal pads to improve
signal integrity by counteracting the pad capacitance.
5. GND vias should be placed directly beneath the device connecting the GND plane attached to the device to
the GND planes on other layers. This has the added benefit of improving thermal conductivity from the
device to the board.
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10.2 Layout Example
Top Layer
Use ac-coupling
capacitors with 0201
package
Ensure high-speed
trace length is
Route high-speed
traces as differential
coupled microstrips
(S=2W*) with tight
impedance control
( 10%)
matched with ≤ 5 mils
intra-pair; pair-pair
skew is less critical
Avoid acute angles
when routing high-
speed traces
Bottom Layer
Use recommended
package footprint and
ground via placement
Ensure pair-pair gap
is > 5W* for minimal
pair-pair coupling
Place decoupling
capacitors close to
VCC pins; minimize
ground loops
Add ground pours for
additional isolation
Follow connector
manufacturer
guidelines
*W is a trace width.
S is a gap between
adjacent traces.
图10-1. DS320PR810 Layout Example –Sub-Section of a PCIe Riser Card With CEM Connectors
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11 Device and Documentation Support
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答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
30
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Product Folder Links: DS320PR810
PACKAGE OPTION ADDENDUM
www.ti.com
11-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS320PR810NJXR
DS320PR810NJXT
ACTIVE
ACTIVE
WQFN
WQFN
NJX
NJX
64
64
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
5PR8
5PR8
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Oct-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS320PR810NJXR
DS320PR810NJXT
WQFN
WQFN
NJX
NJX
64
64
3000
250
330.0
180.0
16.4
16.4
5.8
5.8
10.3
10.3
1.2
1.2
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS320PR810NJXR
DS320PR810NJXT
WQFN
WQFN
NJX
NJX
64
64
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
NJX0064A
WQFN - 0.8 mm max height
S
C
A
L
E
1
.
8
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.6
5.4
A
B
PIN 1 INDEX AREA
10.1
9.9
0.8
0.6
C
SEATING PLANE
0.08 C
0.05
0.00
4.1 0.1
2X 3.2
EXPOSED
THERMAL PAD
SYMM
(0.1) TYP
32
24
23
33
SYMM
65
8.6 0.1
2X 8.8
1
55
0.25
0.15
64
56
60X 0.4
PIN 1 ID
64X
0.5
0.3
0.1
C A B
64X
0.05
4225514/A 11/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
NJX0064A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(4.1)
SYMM
64X (0.6)
64X (0.2)
SEE SOLDER MASK
DETAIL
64
56
1
55
60X (0.4)
(4.05) TYP
(8.6)
(R0.05) TYP
(
0.2) TYP
VIA
1.15 TYP
SYMM
0.575 TYP
(9.8)
65
23
33
24
(0.68) TYP
32
(1.8) TYP
(5.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225514/A 11/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
NJX0064A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.36) TYP
64X (0.6)
64X (0.2)
56
64
1
55
60X (0.4)
(R0.05) TYP
(1.15) TYP
(9.8)
SYMM
65
23
21X (0.95)
33
24
32
SYMM
21X (1.16)
(5.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 12X
EXPOSED PAD 65
66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4225514/A 11/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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