DS90C031TM/NOPB [TI]
LVDS 四路 CMOS 差动线路驱动器 | D | 16 | -40 to 85;
| 型号： | DS90C031TM/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LVDS 四路 CMOS 差动线路驱动器 | D | 16 | -40 to 85 驱动 光电二极管 接口集成电路 线路驱动器或接收器 驱动程序和接口 |
| 文件： | 总19页 (文件大小：1007K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90C031B
www.ti.com
SNLS051B –MARCH 1999–REVISED MARCH 2013
DS90C031B LVDS Quad CMOS Differential Line Driver
Check for Samples: DS90C031B
1
FEATURES
DESCRIPTION
The DS90C031B is a quad CMOS differential line
driver designed for applications requiring ultra low
power dissipation and high data rates. The device
supports data rates in excess of 155.5 Mbps (77.7
MHz) and uses Low Voltage Differential Signaling
(LVDS) technology.
2
•
•
•
•
•
•
•
•
>155.5 Mbps (77.7 MHz) switching rates
High impedance LVDS outputs with power-off
±350 mV differential signaling
Ultra low power dissipation
400 ps maximum differential skew (5V, 25°C)
3.5 ns maximum propagation delay
Industrial operating temperature range
The DS90C031B accepts TTL/CMOS input levels and
translates them to low voltage (350 mV) differential
output signals. In addition the driver supports a TRI-
STATE function that may be used to disable the
output stage, disabling the load current, and thus
dropping the device to an ultra low idle power state of
11 mW typical.
Pin compatible with DS26C31, MB571 (PECL)
and 41LG (PECL)
•
•
•
Conforms to ANSI/TIA/EIA-644 LVDS standard
Offered in narrow body SOIC package
Fail-safe logic for floating inputs
In addition, the DS90C031B provides power-off high
impedance LVDS outputs. This feature assures
minimal loading effect on the LVDS bus lines when
VCC is not present.
The DS90C031B and companion line receiver
(DS90C032B) provide a new alternative to high
power pseudo-ECL devices for high speed point-to-
point interface applications.
Connection Diagram
Functional Diagram
Figure 1. Dual-In-Line
See Package Number D (R-PDSO-G16)
1
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
DS90C031B
SNLS051B –MARCH 1999–REVISED MARCH 2013
www.ti.com
Driver Truth Table
Enables
Input
DIN
X
Outputs
EN
EN*
DOUT+
DOUT−
L
H
Z
L
Z
H
L
L
All other combinations of ENABLE
inputs
H
H
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
Absolute Maximum Ratings
Supply Voltage (VCC
Input Voltage (DIN
Enable Input Voltage (EN, EN*)
Output Voltage (DOUT+, DOUT−
Short Circuit Duration (DOUT+, DOUT−
)
−0.3V to +6V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to +5.8V
Continuous
)
)
)
Maximum Package Power Dissipation at +25°C
Derate Power Dissipation
1068 mW
8.5 mW/°C above +25°C
−65°C to +150°C
+260°C
Storage Temperature Range
Lead Temperature Range, Soldering (4 seconds)
Maximum Junction Temperature
ESD Rating
+150°C
HBM, 1.5 kΩ, 100 pF
≥ 2kV
EIAJ, 0 Ω, 200 pF
≥ 250V
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to
imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device
operation.
Recommended Operating Conditions
Min
+4.5
−40
Typ
+5.0
+25
Max
+5.5
+85
Units
V
Supply Voltage (VCC
)
Operating Free Air Temperature (TA)
°C
2
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SNLS051B –MARCH 1999–REVISED MARCH 2013
Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
(1) (2)
Symbol
VOD1
Parameter
Test Conditions
RL = 100Ω (Figure 2)
Pin
Min
Typ
345
4
Max
450
35
Units
mV
Differential Output Voltage
DOUT−
DOUT+
,
250
ΔVOD1
Change in Magnitude of VOD1 for
Complementary Output States
|mV|
VOS
Offset Voltage
1.10
1.25
5
1.35
25
V
ΔVOS
Change in Magnitude of VOS for
Complementary Output States
|mV|
VOH
VOL
VIH
VIL
II
Output Voltage High
Output Voltage Low
Input Voltage High
RL = 100Ω
1.41
1.07
1.60
V
V
0.90
2.0
DIN
EN,
EN*
,
VCC
0.8
V
Input Voltage Low
GND
−10
V
Input Current
VIN = VCC, GND, 2.5V or 0.4V
ICL = −18 mA
VOUT = 0V(3)
±1
−0.8
−3.5
±1
+10
μA
V
VCL
IOS
IOZ
Input Clamp Voltage
Output Short Circuit Current
Output TRI-STATE Current
−1.5
DOUT−
DOUT+
,
−5.0
mA
μA
EN = 0.8V and EN* = 2.0V,
VOUT = 0V or VCC
−10
−10
+10
IOFF
ICC
Power - Off Leakage
VO = 0V or 2.4V, VCC = 0V or Open
DIN = VCC or GND
±1
1.7
+10
3.0
μA
mA
mA
mA
No Load Supply Current Drivers
Enabled
VCC
DIN = 2.5V or 0.4V
4.0
6.5
ICCL
ICCZ
Loaded Supply Current Drivers
Enabled
RL = 100Ω (all channels),
VIN = VCC or GND (all inputs)
15.4
21.0
No Load Supply Current Drivers
Disabled
DIN = VCC or GND,
EN = GND, EN* = VCC
2.2
4.0
mA
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except: VOD1 and ΔVOD1
.
(2) All typicals are given for: VCC = +5.0V, TA = +25°C.
(3) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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Switching Characteristics
(1) (2) (3)
VCC = +5.0V, TA = +25°C
Symbol
tPHLD
Parameter
Conditions
Min
1.0
1.0
0
Typ
2.0
Max
3.0
3.0
400
600
1.5
1.5
10
Units
ns
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
RL = 100Ω, CL = 5 pF
(Figure 3 and Figure 4)
tPLHD
tSKD
tSK1
tTLH
tTHL
tPHZ
tPLZ
tPZH
tPZL
2.1
ns
Differential Skew |tPHLD – tPLHD
|
80
ps
(4)
Channel-to-Channel Skew
0
300
0.35
0.35
2.5
ps
Rise Time
ns
Fall Time
ns
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
RL = 100Ω, CL = 5 pF
(Figure 5 and Figure 6)
ns
2.5
10
ns
2.5
10
ns
2.5
10
ns
(1) All typicals are given for: VCC = +5.0V, TA = +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤ 6 ns, and tf ≤ 6 ns.
(3) CL includes probe and jig capacitance.
(4) Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the
same chip with an event on the inputs.
Switching Characteristics
VCC = +5.0V ± 10%, TA = −40°C to +85°C
(1) (2) (3)
Symbol
tPHLD
Parameter
Conditions
Min
0.5
0.5
0
Typ
2.0
2.1
80
Max
3.5
3.5
900
1.0
3.0
2.0
2.0
15
Units
ns
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
RL = 100Ω, CL = 5 pF
(Figure 3 and Figure 4)
tPLHD
tSKD
tSK1
tSK2
tTLH
tTHL
tPHZ
tPLZ
tPZH
tPZL
ns
Differential Skew |tPHLD – tPLHD
|
ps
(4)
Channel-to-Channel Skew
0
0.3
ns
(5)
Chip to Chip Skew
ns
Rise Time
0.35
0.35
2.5
ns
Fall Time
ns
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
RL = 100Ω, CL = 5 pF
(Figure 5 and Figure 6)
ns
2.5
15
ns
2.5
15
ns
2.5
15
ns
(1) All typicals are given for: VCC = +5.0V, TA = +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤ 6 ns, and tf ≤ 6 ns.
(3) CL includes probe and jig capacitance.
(4) Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the
same chip with an event on the inputs.
(5) Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
4
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SNLS051B –MARCH 1999–REVISED MARCH 2013
PARAMETER MEASUREMENT INFORMATION
Figure 2. Driver VOD and VOS Test Circuit
Figure 3. Driver Propagation Delay and Transition Time Test Circuit
Figure 4. Driver Propagation Delay and Transition Time Waveforms
Figure 5. Driver TRI-STATE Delay Test Circuit
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PARAMETER MEASUREMENT INFORMATION (continued)
Figure 6. Driver TRI-STATE Delay Waveform
Typical Application
Figure 7. Point-to-Point Application
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SNLS051B –MARCH 1999–REVISED MARCH 2013
APPLICATIONS INFORMATION
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 7. This configuration provides a clean signaling environment for the quick edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the
range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to
the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a
voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration,
but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination loading must be taken into account.
The DS90C031B differential line driver is a balanced current source design. A current mode driver, generally
speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode
driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in
one direction to produce a logic state and in the other direction to produce the other logic state. The typical
output current is a mere 3.4 mA with a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode
requires (as discussed above) that a resistive termination be employed to terminate the signal and to complete
the loop as shown in Figure 7. AC or unterminated configurations are not allowed. The 3.4 mA loop current will
develop a differential voltage of 340 mV across the 100Ω termination resistor which the receiver detects with a
240 mV minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold
(340 mV – 100 mV = 240 mV). The signal is centered around +1.2V (Driver Offset, VOS) with respect to ground
as shown in Figure 8. Note that the steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage
(VOD) and is typically 680 mV.
The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its
quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver
increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows
between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed
current between its output without any substantial overlap current. This is similar to some ECL and PECL
devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires > 80% less
current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing
RS-422 drivers.
The fail-safe circuitry guarantees that the outputs are enabled and at a logic "0" (the true output is low and the
complement output is high) when the inputs are floating.
The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when
the transmission of data is not required.
The footprint of the DS90C031B is the same as the industry standard 26LS31 Quad Differential (RS-422) Driver.
The DS90C031B is electrically similar to the DS90C031, but differs by supporting high impedance LVDS outputs
under power-off condition. This allows for multiple or redundant drivers to be used in certain applications. The
DS90C031B is offered in a space saving narrow SOIC (150 mil.) package.
For additional LVDS application information, see TI's LVDS Owner's Manual available through TI's website
http://www.ti.com/lsds/ti/analog/interface.page.
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Figure 8. Driver Output Levels
Pin Descriptions
Pin No.
Name
DIN
Description
1, 7, 9, 15
Driver input pin, TTL/CMOS compatible
Non-inverting driver output pin, LVDS levels
Inverting driver output pin, LVDS levels
Active high enable pin, OR-ed with EN*
Active low enable pin, OR-ed with EN
Power supply pin, +5V ± 10%
2, 6, 10, 14
DOUT+
DOUT−
EN
3, 5, 11, 13
4
12
16
8
EN*
VCC
GND
Ground pin
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SNLS051B –MARCH 1999–REVISED MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Current
vs Power Supply Voltage
Power Supply Current
vs Temperature
Figure 9.
Figure 10.
Power Supply Current
vs Power Supply Voltage
Power Supply Current
vs Temperature
Figure 11.
Figure 12.
Output TRI-STATE Current
vs Power Supply Voltage
Output Short Circuit Current
vs Power Supply Voltage
œ3
œ3.2
œ3.4
œ3.6
œ3.8
œ4
TA = 25 °C
VIN = 0V or 5V
VOUT = 0V
5.5
4.5
5
4.75
5.25
VCC œ Power Supply Voltage (V)
Figure 13.
Figure 14.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Differential Output Voltage
vs Power Supply Voltage
Differential Output Voltage
vs Ambient Temperature
Figure 15.
Figure 16.
Output Voltage High vs
Power Supply Voltage
Output Voltage High vs
Ambient Temperature
Figure 17.
Figure 18.
Output Voltage Low vs
Power Supply Voltage
Output Voltage Low vs
Ambient Temperature
Figure 19.
Figure 20.
10
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SNLS051B –MARCH 1999–REVISED MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Offset Voltage vs
Power Supply Voltage
Offset Voltage vs
Ambient Temperature
Figure 21.
Figure 22.
Power Supply Current
vs Frequency
Power Supply Current
vs Frequency
Figure 23.
Figure 24.
Differential Output Voltage
vs Load Resistor
Differential Propagation Delay
vs Power Supply Voltage
Figure 25.
Figure 26.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Differential Propagation Delay
vs Ambient Temperature
Differential Skew vs
Power Supply Voltage
Figure 27.
Figure 28.
Differential Skew vs
Ambient Temperature
Differential Transition Time
vs Power Supply Voltage
Figure 29.
Figure 30.
Differential Transition Time
vs Ambient Temperature
Figure 31.
12
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SNLS051B –MARCH 1999–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 12
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
DS90C031BTM
NRND
ACTIVE
SOIC
SOIC
D
D
16
16
48
TBD
Call TI
CU SN
Call TI
-40 to 85
-40 to 85
DS90C031BTM
DS90C031BTM/NOPB
48
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
DS90C031BTM
DS90C031BTMX/NOPB
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
DS90C031BTM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90C031BTMX/NOPB
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.3
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
DS90C031BTMX/NOPB
D
2500
Pack Materials-Page 2
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TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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相关型号：
DS90C031TMX/NOPB
IC QUAD LINE DRIVER, PDSO16, 0.150 INCH, PLASTIC, SOIC-16, Line Driver or Receiver
NSC
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