DS90C032MW8 [TI]
IC QUAD LINE RECEIVER, UUC, DIE, Line Driver or Receiver;
| 型号： | DS90C032MW8 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC QUAD LINE RECEIVER, UUC, DIE, Line Driver or Receiver |
| 文件： | 总13页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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September 2003
DS90C032
LVDS Quad CMOS Differential Line Receiver
General Description
Features
>
n
155.5 Mbps (77.7 MHz) switching rates
TheDS90C032 is a quad CMOS differential line receiver
designed for applications requiring ultra low power dissipa-
tion and high data rates. The device is designed to support
data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low
Voltage Differential Signaling (LVDS) technology.
n Accepts small swing (350 mV) differential signal levels
n Ultra low power dissipation
n 600 ps maximum differential skew (5V, 25˚C)
n 6.0 ns maximum propagation delay
TheDS90C032 accepts low voltage (350 mV) differential
input signals and translates them to CMOS (TTL compatible)
output levels. The receiver supports a TRI-STATE® function
that may be used to multiplex outputs. The receiver also
supports OPEN, shorted and terminated (100Ω) input Fail-
safe with the addition of external failsafe biasing. Receiver
output will be HIGH for both Failsafe conditions.
n Industrial operating temperature range
n Military operating temperature range option
n Available in surface mount packaging (SOIC) and (LCC)
n Pin compatible with DS26C32A, MB570 (PECL) and
41LF (PECL)
n Supports OPEN, short and terminated input fail-safe
n Compatible with IEEE 1596.3 SCI LVDS standard
n Conforms to ANSI/TIA/EIA-644 LVDS standard
n Available to Standard Microcircuit Drawing (SMD)
5962-95834
TheDS90C032 and companion line driver (DS90C031) pro-
vide a new alternative to high power psuedo-ECL devices for
high speed point-to-point interface applications.
Connection Diagrams
LCC Package
Dual-In-Line
01194501
Order Number
DS90C032TM
See NS Package Number M16A
01194520
Order Number
DS90C032E-QML
See NS Package Number E20A
For complete Military Specifications,
refer to appropriate SMD or MDS.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation
DS011945
www.national.com
Functional Diagram and Truth Tables
01194502
Receiver
ENABLES
INPUTS
RIN+ − RIN−
OUTPUT
EN
EN*
ROUT
L
H
X
Z
H
L
All other combinations
of ENABLE inputs
VID ≥ 0.1V
VID ≤ −0.1V
Full Fail-safe OPEN/SHORT
or Terminated
H
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2
Absolute Maximum Ratings (Note 1)
Maximum Junction
Temperature (DS90C032T)
Maximum Junction
+150˚C
+175˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Temperature (DS90C032E)
ESD Rating (Note 7)
(HBM, 1.5 kΩ, 100 pF)
(EIAJ, 0 Ω, 200 pF)
Supply Voltage (VCC
)
−0.3V to +6V
Input Voltage (RIN+, RIN−
Enable Input Voltage
(EN, EN*)
)
−0.3V to (VCC +0.3V)
≥ 3,500V
≥ 250V
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
Output Voltage (ROUT
)
Recommended Operating
Conditions
@
Maximum Package Power Dissipation +25˚C
M Package
E Package
1025 mW
1830 mW
Min
Typ
Max Units
Supply Voltage (VCC
)
+4.5 +5.0 +5.5
V
V
Derate M Package
8.2 mW/˚C above +25˚C
12.2 mW/˚C above +25˚C
−65˚C to +150˚C
Receiver Input Voltage GND
2.4
Derate E Package
Operating Free Air Temperature (TA)
Storage Temperature Range
Lead Temperature Range
Soldering (4 sec.)
DS90C032T
DS90C032E
−40
−55
+25
+85
˚C
˚C
+25 +125
+260˚C
Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Note 2)
Symbol
VTH
Parameter
Conditions
Pin
Min
Typ
Max
Units
mV
mV
µA
µA
V
Differential Input High Threshold VCM = +1.2V
Differential Input Low Threshold
RIN+
,
+100
RIN−
VTL
−100
−10
−10
3.8
IIN
Input Current
VIN = +2.4V
VIN = 0V
VCC = 5.5V
1
1
+10
+10
VOH
Output High Voltage
IOH = −0.4 mA, VID = +200 mV
ROUT
4.9
4.9
IOH = −0.4 mA,
DS90C032T
3.8
V
Input terminated
VOL
IOS
IOZ
VIH
VIL
II
Output Low Voltage
Output Short Circuit Current
Output TRI-STATE Current
Input High Voltage
IOL = 2 mA, VID = −200 mV
Enabled, VOUT = 0V (Note 8)
Disabled, VOUT = 0V or VCC
0.07
−60
1
0.3
−100
+10
V
−15
−10
2.0
mA
µA
V
EN,
EN*
Input Low Voltage
0.8
V
Input Current
−10
1
−0.8
3.5
3.5
3.7
3.5
3.5
+10
µA
V
VCL
ICC
Input Clamp Voltage
No Load Supply Current
Receivers Enabled
ICL = −18 mA
−1.5
EN, EN* = VCC or GND,
Inputs Open
DS90C032T
DS90C032E
VCC
10
11
11
10
11
mA
mA
mA
mA
mA
EN, EN* = 2.4 or 0.5, Inputs Open
ICCZ
No Load Supply Current
Receivers Disabled
EN = GND, EN* = VCC
Inputs Open
DS90C032T
DS90C032E
3
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Switching Characteristics
VCC = +5.0V, TA = +25˚C DS90C032T (Notes 3, 4, 5, 9)
Symbol
Parameter
Conditions
CL = 5 pF
Min
1.5
1.5
0
Typ
3.40
3.48
80
Max
5.0
5.0
600
1.0
2.0
2.0
15
Units
ns
tPHLD
tPLHD
tSKD
tSK1
tTLH
tTHL
tPHZ
tPLZ
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
VID = 200 mV
ns
Differential Skew |tPHLD − tPLHD
|
(Figure 1 and Figure 2)
ps
Channel-to-Channel Skew (Note 5)
Rise Time
0
0.6
0.5
0.5
10
ns
ns
Fall Time
ns
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
RL = 2 kΩ
ns
CL = 10 pF
10
15
ns
tPZH
tPZL
(Figure 3 and Figure 4)
4
10
ns
4
10
ns
Switching Characteristics
VCC = +5.0V 10%, TA = −40˚C to +85˚C DS90C032T (Notes 3, 4, 5, 6, 9)
Symbol
Parameter
Conditions
CL = 5 pF
Min
1.0
1.0
0
Typ
3.40
3.48
0.08
0.6
Max
6.0
6.0
1.2
1.5
5.0
2.5
2.5
20
Units
ns
tPHLD
tPLHD
tSKD
tSK1
tSK2
tTLH
tTHL
tPHZ
tPLZ
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
VID = 200 mV
ns
Differential Skew |tPHLD − tPLHD
|
(Figure 1 and Figure 2)
ns
Channel-to-Channel Skew (Note 5)
Chip to Chip Skew (Note 6)
Rise Time
0
ns
ns
0.5
0.5
10
10
4
ns
Fall Time
ns
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
RL = 2 kΩ
ns
CL = 10 pF
20
ns
tPZH
tPZL
(Figure 3 and Figure 4)
15
ns
4
15
ns
Switching Characteristics
VCC = +5.0V 10%, TA = −55˚C to +125˚C DS90C032E (Notes 3, 4, 5, 6, 9, 10)
Symbol
Parameter
Conditions
Min
1.0
1.0
0
Typ
3.40
3.48
0.08
0.6
Max
8.0
8.0
3.0
3.0
7.0
20
Units
ns
tPHLD
tPLHD
tSKD
tSK1
tSK2
tPHZ
tPLZ
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
CL = 20 pF
VID = 200 mV
ns
Differential Skew |tPHLD − tPLHD
|
(Figure 1 and Figure 2)
ns
Channel-to-Channel Skew (Note 5)
Chip to Chip Skew (Note 6)
Disable Time High to Z
0
ns
ns
RL = 2 kΩ
10
10
4
ns
Disable Time Low to Z
CL = 10 pF
20
ns
tPZH
tPZL
Enable Time Z to High
(Figure 3 and Figure 4)
20
ns
Enable Time Z to Low
4
20
ns
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4
Parameter Measurement Information
01194503
FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit
01194504
FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms
01194505
C
includes load and test jig capacitance.
L
1
1
S
S
= V
for t
and t
measurements.
PLZ
CC
PZL
= GND for t
and t
measurements.
PHZ
PZH
FIGURE 3. Receiver TRI-STATE Delay Test Circuit
5
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Parameter Measurement Information (Continued)
01194506
FIGURE 4. Receiver TRI-STATE Delay Waveforms
Typical Application
01194507
FIGURE 5. Point-to-Point Application
fects of coupled noise, or a combination of the two. Both
receiver input pins should honor their specified operating
input voltage range of 0V to +2.4V (measured from each pin
to ground), exceeding these limits may turn on the ESD
protection circuitry which will clamp the bus voltages.
Applications Information
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 5. This configuration provides a clean signaling
environment for the quick edge rates of the drivers. The
receiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically the characteristic
impedance of the media is in the range of 100Ω. A termina-
tion resistor of 100Ω should be selected to match the media,
and is located as close to the receiver input pins as possible.
The termination resistor converts the current sourced by the
driver into a voltage that is detected by the receiver. Other
configurations are possible such as a multi-receiver configu-
ration, but the effects of a mid-stream connector(s), cable
stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination
loading must be taken into account.
Receiver Fail-Safe:
The LVDS receiver is a high gain, high speed device that
amplifies a small differential signal (20mV) to CMOS logic
levels. Due to the high gain and tight threshold of the re-
ceiver, care should be taken to prevent noise from appearing
as a valid signal.
The receiver’s internal fail-safe circuitry is designed to
source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for
floating, terminated or shorted receiver inputs.
1. Open Input Pins. TheDS90C032 is a quad receiver
device, and if an application requires only 1, 2 or 3
receivers, the unused channel(s) inputs should be left
OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high
value pull up and pull down resistors to set the output to
a HIGH state. This internal circuitry will guarantee a
HIGH, stable output state for open inputs.
TheDS90C032 differential line receiver is capable of detect-
ing signals as low as 100 mV, over a 1V common-mode
range centered around +1.2V. This is related to the driver
offset voltage which is typically +1.2V. The driven signal is
centered around this voltage and may shift 1V around this
center point. The 1V shifting may be the result of a ground
potential difference between the driver’s ground reference
and the receiver’s ground reference, the common-mode ef-
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6
1V). It is only supported with inputs shorted and no
external common-mode voltage applied.
Applications Information (Continued)
2. Terminated Input. TheDS90C032 requires external fail-
4. Operation in environment with greater than 10mV
safe biasing for terminated input failsafe.
differential noise.
Terminated input failsafe is the case of a receiver that
has a 100Ω termination across its inputs and the driver
is in the following situations. Unplugged from the bus, or
the driver output is in TRI-STATE or in power-off condi-
tion. The use of external biasing resistors provide a
small bias to set the differential input voltage while the
line is un-driven, and therefore the receiver output will be
in HIGH state. If the driver is removed from the bus but
the cable is still present and floating, the unplugged
cable can become a floating antenna that can pick up
noise. The LVDS receiver is designed to detect very
small amplitude and width signals and recover them to
standard logic levels. Thus, if the cable picks up more
than 10mV of differential noise, the receiver may re-
spond. To insure that any noise is seen as common-
mode and not differential, a balanced interconnect and
twisted pair cables is recommended, as they help to
ensure that noise is coupled common to both lines and
rejected by the receivers.
National recommends external failsafe biasing on its
LVDS receivers for a number of system level and signal
quality reasons. First, only an application that requires
failsafe biasing needs to employ it. Second, the amount
of failsafe biasing is now an application design param-
eter and can be custom tailored for the specific applica-
tion. In applications in low noise environments, they may
choose to use a very small bias if any. For applications
with less balanced interconnects and/or in high noise
environments they may choose to boost failsafe further.
Nationals "LVDS Owner’s Manual provides detailed cal-
culations for selecting the proper failsafe biasing resis-
tors. Third, the common-mode voltage is biased by the
resistors during the un-driven state. This is selected to
be close to the nominal driver offset voltage (VOS). Thus
when switching between driven and un-driven states,
the common-mode modulation on the bus is held to a
minimum.
For additional Failsafe Biasing information, please refer
to Application Note AN-1194 for more detail.
3. Shorted Inputs. If a fault condition occurs that shorts
the receiver inputs together, thus resulting in a 0V differ-
ential input voltage, the receiver output will remain in a
HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (1.2V
The footprint of theDS90C032 is the same as the industry
standard 26LS32 Quad Differential (RS-422) Receiver.
7
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Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply that
the devices should be operated at these limits. The table of “Electrical
Characteristics” specifies conditions of device operation.
Pin Descriptions
Pin No.
Name Description
(SOIC)
Note 2: Current into device pins is defined as positive. Current out of device
pins is defined as negative. All voltages are referenced to ground unless
otherwise specified.
2, 6,
RIN+ Non-inverting receiver input pin
10, 14
Note 3: All typicals are given for: V
= +5.0V, T = +25˚C.
A
CC
1, 7, 9, RIN− Inverting receiver input pin
15
Note 4: Generator waveform for all tests unless otherwise specified: f = 1
MHz, Z = 50Ω, t and t (0%–100%) ≤ 1 ns for R and t and t ≤ 6 ns for EN
or EN*.
O
r
f
IN
r
f
3, 5,
11, 13
4
ROUT Receiver output pin
Note 5: Channel-to-Channel Skew is defined as the difference between the
propagation delay of one channel and that of the others on the same chip with
an event on the inputs.
EN Active high enable pin, OR-ed with
EN*
Note 6: Chip to Chip Skew is defined as the difference between the mini-
mum and maximum specified differential propagation delays.
Note 7: ESD Rating:
12
16
8
EN* Active low enable pin, OR-ed with EN
VCC Power supply pin, +5V 10%
GND Ground pin
HBM (1.5 kΩ, 100 pF) ≥ 3,500V
EIAJ (0Ω, 200 pF) ≥ 250V
Note 8: Output short circuit current (I ) is specified as magnitude only,
OS
minus sign indicates direction only. Only one output should be shorted at a
time, do not exceed maximum junction temperature specification.
Ordering Information
Note 9: C includes probe and jig capacitance.
L
Note 10: For DS90C032E propagation delay measurements are from 0V on
Operating
Temperature
Package Type/
Number
Order Number
the input waveform to the 50% point on the output (R
).
OUT
−40˚C to +85˚C
−55˚C to +125˚C
SOP/M16A
LCC/E20A
DS90C032TM
DS90C032E-QML
DS90C032E-QML (NSID)
5962-95834 (SMD)
Typical Performance Characteristics
Output High Voltage vs
Power Supply Voltage
Output High Voltage vs
Ambient Temperature
01194508
01194509
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8
Typical Performance Characteristics (Continued)
Output Low Voltage vs
Power Supply Voltage
Output Low Voltage vs
Ambient Temperature
01194510
01194511
Output Short Circuit Current
vs Power Supply Voltage
Output Short Circuit Current
vs Ambient Temperature
01194512
01194513
Differential Propagation Delay
vs Power Supply Voltage
Differential Propagation Delay
vs Ambient Temperature
01194514
01194515
9
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Typical Performance Characteristics (Continued)
Differential Skew vs
Power Supply Voltage
Differential Skew vs
Ambient Temperature
01194517
01194516
Transition Time vs
Transition Time vs
Power Supply Voltage
Ambient Temperature
01194518
01194519
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10
Physical Dimensions inches (millimeters)
unless otherwise noted
20-Lead Ceramic Leadless Chip Carrier, Type C
Order Number DS90C032E-QML
NS Package Number E20A
16-Lead (0.150" Wide) Molded Small Outline Package, JEDEC
Order Number DS90C032TM
NS Package Number M16A
11
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Notes
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systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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