DS90C189-Q1 [TI]
低功耗 1.8V 双像素 FPD 链接 (LVDS) 串行器;
| 型号： | DS90C189-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低功耗 1.8V 双像素 FPD 链接 (LVDS) 串行器 光电二极管 |
| 文件： | 总36页 (文件大小：1546K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
DS90C189-Q1 低功耗、1.8V RGB 到Open LDI (LVDS) 桥接器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准，包括以下规
格：
DS90C189-Q1 是一款低功耗桥接器，适用于汽车应
用，可减小主机 GPU 与显示屏之间 RGB 接口的尺
寸。
– 器件温度等级2：–40°C 至+105°C 环境工作
温度
– 器件HBM ESD 分类等级±8kV
– 器件CDM ESD 分类等级±750V
• 185MHz 频率下的典型功耗为150mW（SIDO 模
式）
DS90C189-Q1 桥接器旨在支持主机与平板显示器之间
频率为60Hz、分辨率高达 QXGA (2048x1536) 的单像
素数据传输。该发送器可将高达 24 位（单像素 24 位
颜色）的 1.8V LVCMOS 数据转换成双通道 4 数据 +
时钟(4D+C) 宽度更低的接口LVDS 兼容数据流。
• 驱动QXGA 和WQXGA 类显示器
• 两种工作模式：
DS90C189-Q1 支持2 种工作模式。
• 在单输入像素/单输出像素模式下，该器件能够以
60Hz 的频率驱动高达SXGA+ (1400x1050) 的分辨
率。在该模式下，该器件可以将一组24 位的RGB
数据转换成单通道4D+C LVDS 数据流。
• 在单输入像素/双输出像素模式下，该器件能够以
60Hz 的频率驱动高达WUXGA+ (1920x1440) 的分
辨率。在该配置下，该器件可以提供单像素到双像
素的转换，将一组24 位RGB 数据转换成双通道
4D+C LVDS 数据流，其频率是像素时钟频率的一
半。
– 单输入像素、单输出像素(SISO)：最大值105
MHz
– 单输入像素、双输出像素(SIDO)：最大值185
MHz
• 支持24 位RGB
• 支持3D+C、4D+C、6D+C、6D+2C、8D+C 和
8D+2C LVDS 配置
• 与FPD-Link 器件兼容
• 由1.8V 单电源供电
• 直接与1.8V LVCMOS 连接
• 睡眠模式下的功耗低于10mW
• 与扩频时钟兼容
对于所有模式，该器件都支持24bpp 颜色。
DS90C189-Q1 采用小型 64 引脚 QFN 封装，并由
1.8V 单电源供电，实现超低的功率损耗。
• 小型9mm × 9mm × 0.9mm 64 引脚VQFN 封装
2 应用
器件信息(1)
• 摄像头监控系统(CMS)
• 汽车音响主机
• 智能后视镜
封装尺寸（标称值）
器件型号
封装
VQFN (64)
DS90C189-Q1
9.00mm x 9.00mm
• 仪表组
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
4 Typical Application Diagrams
1.8 V LVCMOS
(24 bit RGB + HS/VS/DE)
2 Channels OLDI (LVDS)
(4 Data + Clock)
1.8 V LVCMOS
(24 bit RGB + HS/VS/DE)
2 Channels FPD-Link (LVDS)
(4 Data + Clock)
2 Lanes FPD-Link III
1.8 V
1.8 V
Display (TCON)
DS90C189-
Q1
DS90UB947
-Q1 SER
GPU œ Jacinto 6
GPU
Display (TCON)
DS90C189-
Q1
Single Pixel
R[7:0] G[7:0]
B[7:0]
L
A
T
C
H
LVDS
4D+C
(odd pixel)
DOUT0+
DOUT0-
RIN0+
L
A
T
C
H
RIN0-
FPD-Link III
Interface
RIN1+
RIN1-
DOUT1+
DOUT1-
Single Pixel
R[7:0] G[7:0]
B[7:0]
&
P
2
S
HS
VS
DE
LVDS
4D+C
(even pixel)
&
GPO/CNTL (L/R)
PCLK
P
2
S
HS
PLL
VS
DE
PDB
GPO/CNTL (L/R)
PCLK
PLL
Copyright © 2017, Texas Instruments Incorporated
PDB
Copyright © 2017, Texas Instruments Incorporated
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNLS584
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................16
8.5 Programming............................................................ 18
9 Application and Implementation..................................22
9.1 Application Information............................................. 22
9.2 Typical Application.................................................... 22
10 Power Supply Recommendations..............................24
10.1 Power Up Sequence...............................................24
10.2 Power Supply Filtering............................................24
11 Layout...........................................................................25
11.1 Layout Guidelines................................................... 25
11.2 Layout Example...................................................... 26
12 Device and Documentation Support..........................27
12.1 Documentation Support.......................................... 27
12.2 接收文档更新通知................................................... 27
12.3 支持资源..................................................................27
12.4 Trademarks.............................................................27
12.5 静电放电警告.......................................................... 27
12.6 术语表..................................................................... 27
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Typical Application Diagrams........................................ 1
5 Revision History.............................................................. 2
6 Pin Configuration and Functions...................................3
DS90C189 Pin Descriptions............................................. 4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................7
7.6 Recommended Input Characteristics..........................7
7.7 Switching Characteristics............................................9
7.8 AC Timing Diagrams...................................................9
7.9 Typical Characteristics..............................................13
8 Detailed Description......................................................14
8.1 Overview...................................................................14
8.2 Functional Block Diagrams....................................... 14
8.3 Feature Description...................................................15
Information.................................................................... 27
5 Revision History
Changes from Revision A (August 2018) to Revision B (September 2020)
Page
• Added note on GND tolerance to Abs Max table................................................................................................6
• Added clarifications on VDD starting from GND during power sequence and power down/power up
conditions..........................................................................................................................................................24
Changes from Revision * (May 2018) to Revision A (August 2018)
Page
• 将器件状态从“预告信息”更改为“量产数据”................................................................................................1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNLS584
2
Submit Document Feedback
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
6 Pin Configuration and Functions
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
OB_3-
VDDTX
OB_3+
NC
OA_0-
OA_0+
NC
PDB
VDD
IN0
MODE0
RFB
VODSEL
IN_1
IN_2
IN_3
IN_4
IN_5
IN_6
IN_7
IN_8
NC
DS90C189-Q1
64 VQFN
Top Down View
IN_27
IN_26
IN_25
IN_24
IN_23
IN_22
IN_21
DAP
DE
NC
VDD
图6-1. RTD Package 64-Pin VQFN Top View
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
3
English Data Sheet: SNLS584
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
DS90C189 Pin Descriptions
NAME
NO.
I/O
DESCRIPTION
1.8-V LVCMOS VIDEO INPUTS
IN_[27:21],
IN_[17:14],
IN_[13:9],
IN_[8:1]
25-19,
10-7,
5-1,
62-55,
53
Data Inputs
Typically consists of 8 Red, 8 Green, 8 Blue and a general purpose or L/R control
bit.
Includes pull down.
I
IN_[0]
HS,
VS ,
DE
12,
13,
18
Video Control Signal Inputs -
HS = Horizontal Sync, VS = Vertical SYNC, and DE = Data Enable
I
I
Pixel Input Clock
Includes pull down.
IN_CLK
6
1.8-V LVCMOS CONTROL INPUTS
Mode Control Input (MODE0) -
0= Single In / Single Out
1= Single In / Dual Out
Includes pull down.
MODE0
RFB
27
26
52
54
I
I
I
I
Rising / Falling Clock Edge Select Input -
0 = Falling Edge
1 = Rising Edge
Includes pull down.
Power Down (Sleep) Control Input -
0 = Sleep (Power Down mode)
1 = Device Active (enabled)
Includes pull down.
PDB
VOD Level Select Input -
0 = Low swing
1 = Normal swing
Includes pull down.
VODSEL
N/C
14, 15, 17, 29, 51,
63
I
I
No Connect Pin –Leave Open
Reserved –Tie to Ground.
RSVD
11
LVDS OUTPUTS
OA_C+
OA_C-
43
44
Channel A LVDS Output Clock –
Expects 100 Ω termination.
O
O
O
O
O
O
O
O
O
O
OA_[0]+,
OA_[0]-
50
49
Channel A LVDS Output Data –
Expects 100 Ω termination.
OA_[1]+,
OA_[1]-
48
47
Channel A LVDS Output Data –
Expects 100 Ω termination.
OA_[2]+,
OA_[2]-
46
45
Channel A LVDS Output Data –
Expects 100 Ω termination.
OA_[3]+,
OA_[3]-
41
42
Channel A LVDS Output Data –
Expects 100 Ω termination.
OB_C+,
OB_C-
33
34
Channel B LVDS Output Clock –
Expects 100 Ω termination.
OB_[0]+,
OB_[0]-
39
40
Channel B LVDS Output Data –
Expects 100 Ω termination.
OB_[1]+,
OB_[1]-
37
38
Channel B LVDS Output Data –
Expects 100 Ω termination.
OB_[2]+,
OB_[2]-
35
36
Channel B LVDS Output Data –
Expects 100 Ω termination.
OB_[3]+,
OB_[3]-
30
32
Channel B LVDS Output Data –
Expects 100 Ω termination.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNLS584
4
Submit Document Feedback
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
NAME
NO.
I/O
DESCRIPTION
POWER AND GROUND
VDDTX
VDD
31
28, 64
16
P
P
P
G
Power supply for LVDS Drivers, 1.8 V.
Power supply pin for core, 1.8 V.
Power supply pin for PLL, 1.8 V.
Connect DAP to Ground plane.
VDDP
DAP
DAP
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
5
English Data Sheet: SNLS584
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
See (1) (2)
MIN
−0.3
−0.3
−0.3
MAX
2.5
UNIT
Supply Voltage (VDD
)
V
V
V
LVCMOS Input Voltage
VDD + 0.3
3.6
LVDS Driver Output Voltage
LVDS Output Short-Circuit Duration
Junction Temperature
Continuous
150
150
°C
°C
Storage Temperature (Tstg
)
−65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) GND tolerance +/-5mV compared to system GND
7.2 ESD Ratings
VALUE
±8000
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101
7.3 Recommended Operating Conditions
MIN
1.71
−40
80
NOM
1.80
+25
MAX
1.89
+105
120
UNIT
Supply Voltage
V
Operating Free Air Temperature (TA)
Differential Load Impedance
Supply Noise Voltage
°C
100
Ω
<90
mVp-p
7.4 Thermal Information
DS90C189-Q1
THERMAL METRIC(1)
RTD (VQFN)
64 PINS
23.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
12.5
7.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJT
7.9
ψJB
RθJC(bot)
1.0
(1) For more information about traditional and new thermalmetrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNLS584
6
Submit Document Feedback
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
7.5 Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LVCMOS DC SPECIFICATIONS
VIH
VIL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Current
0.66VDD
GND
VDD
0.35VDD
+10
V
V
VIN = 0V or VDD = 1.71 V to 1.89 V
- 10
±1
µA
LVDS DRIVER DC SPECIFICATIONS
160
(320)
340
(680)
500
mV
VODSEL = VDD
RL = 100Ω
(1000) (mVP-P
400 mV
(800) (mVP-P
)
)
VOD
Differential Output Voltage
110
(220)
220
(440)
VODSEL = VGND
Change in VOD between
Complimentary Output States
RL = 100Ω
See 图7-3
50
1.36
50
mV
V
ΔVOD
RL = 100Ω
See 图7-3
VOS
Offset Voltage
1.09
1.22
Change in VOS between
Complimentary Output States
RL = 100Ω
See 图7-3
mV
mA
ΔVOS
IOS
Output Short-Circuit Current
VOUT = GND, VODSEL = VDD
−15.5
SUPPLY CURRENT
Checkerboard
pattern,
RL = 100 Ω,
VODSEL = VDD
VDD = 1.89 V,
f = 105 MHz,
MODE0 = GND
(SISO)
IDDT1
50
85
mA
Worst Case Supply Current
(includes load current)
,
f = 185 MHz,
MODE0 = VDD
(SIDO)
IDDT2
IDDTP
80
50
140
mA
mA
See Checker Board
Test Pattern
MODE0 = VDD
(SIDO),
f = 150 MHz,
VODSEL = GND,
VDD = 1.8
RL = 100 Ω,
PRBS-7 Pattern
See Typ Current
Draw - Single In/
Dual Out Mode -
PRBS-7 Data
Pattern.
Supply Current PRBS-7
VODSEL = VDD
VDD = 1.8
,
70
53
mA
mA
MODE0 = VDD
(SIDO),
VODSEL = GND,
VDD = 1.8
f = 150 MHz,
RL = 100 Ω,
16 Grayscale Pattern
IDDTG
IDDZ
Supply Current 16 Grayscale
Power Down Supply Current
VODSEL = VDD
VDD = 1.8
,
71
6
mA
µA
PDB = GND
800
7.6 Recommended Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
MIN
TYP
MAX
UNIT
ns
MODE0 = GND
MODE0 = VDD
MODE0 = GND
MODE0 = VDD
1
1
4
2
IN_CLK Transition Time
图7-5
TCIT
TCIP
ns
9.53
5.40
0.35T
0.35T
T(1)
T
40
ns
IN_CLK Period
图7-6
20
ns
TCIH
TCIL
IN_CLK High Time
IN_CLK Low Time
0.5T
0.5T
0.65T
0.65T
ns
See 图7-6
ns
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
7
English Data Sheet: SNLS584
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
MIN
TYP
MAX
0.3T
UNIT
TXIT
IN_n Transition Time
1.5
ns
See 图7-5
(1) T = Typical Period of the input Clock.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNLS584
8
Submit Document Feedback
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
7.7 Switching Characteristics
Over recommended operating supply and temperature ranges unlessotherwise specified.
PARAMETER
MIN
TYP
MAX
UNIT
ns
TSTC
THTC
IN_n Setup to IN_CLK
IN_n Hold from IN_CLK
0
See 图7-6
See 图7-6
2.5
ns
LVDS Low-to-High Transition Time
See 图7-4
LLHT
LHLT
0.33
0.33
ns
ns
LVDS High-to-Low Transition Time
See 图7-4
MODE0 = GND
MODE0 = VDD
1/7 TCIP
2/7 TCIP
ns
ns
TBIT
LVDS Output Bit Width
Transmitter Output Pulse Positions Normalized
for Bit 0
TPPOS0
TPPOS1
TPPOS2
TPPOS3
TPPOS4
TPPOS5
TPPOS6
1
2
3
4
5
6
7
UI
UI
UI
UI
UI
UI
UI
See 图7-9
See 图7-9
See 图7-9
See 图7-9
See 图7-9
See 图7-9
See 图7-9
See 图7-9
Transmitter Output Pulse Positions Normalized
for Bit 1
Transmitter Output Pulse Positions Normalized
for Bit 2
Transmitter Output Pulse Positions Normalized
for Bit 3
Transmitter Output Pulse Positions Normalized
for Bit 4
Transmitter Output Pulse Positions Normalized
for Bit 5
Transmitter Output Pulse Positions Normalized
for Bit 6
Variation in Transmitter Pulse Position (Bit 6 —
Bit 0)
±0.06
110
UI
ps
UI
Δ_TPPOS
TCCS
LVDS Channel to Channel Skew
Jitter Cycle-to-Cycle
MODE0 = GND,
f = 105 MHz
TJCC
0.176
1
TPLLS
TPDD
Phase Lock Loop Set (Enable Time)
Powerdown Delay
ms
ns
ns
See 图7-7
See 图7-8
100
MODE0 = GND
See 图7-11
2*TCIP +
10.54
2*TCIP +
19.38
TSD
Latency Delay
MODE0 = VDD
See 图7-10
ns
Latency Delay for Single Pixel In / Dual Pixel Out
Mode
9*TCIP +
4.19
TLAT
7.8 AC Timing Diagrams
T
IN_CLK
IN_n,
n = ODD
IN_n,
n = EVEN
Falling Edge CLK (RFB = GND) shown
A. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/ I/O.
B. 图7-2 shows a falling edge data strobe (IN_CLK).
图7-1. Checker Board Test Pattern
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
9
English Data Sheet: SNLS584
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
Signal
Signal Pattern
Signal Frequency
PCLK
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
f
f / 16
f / 8
f / 4
f / 2
Steady State, Low
Steady State, Low
f / 16
f / 8
f / 4
f / 2
Steady State, Low
Steady State, Low
f / 16
B1
f / 8
B2
f / 4
B3
f / 2
B4
Steady State, Low
Steady State, Low
Steady State, High
Steady State, High
Steady State, High
B5
HS
VS
DE
A. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/ I/O.
B. Recommended pin to signal mapping for 18 bits per pixel, customer may choose to define differently. The 16 grayscale test pattern tests
device power consumption for a “typical”LCD display pattern. The test pattern approximates signal switching needed to produce
groups of 16 vertical stripes across the display.
C. 图7-2 shows a falling edge data strobe (IN_CLK).
图7-2. “16 Gray Scale”Test Pattern (Falling Edge Clock shown)
OA/B_C+, OA/B_[3:0]+
100W
OA/B_C-, OA/B_[3:0]-
图7-3. DS90C189-Q1 (Transmitter) LVDS Output Load
+VOD
80%
80%
VSS = 2|VOD|
0V
20%
20%
-VOD
LLHT
LHLT
图7-4. LVDS Output Transition Times
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNLS584
10
Submit Document Feedback
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
VDD
80%
80%
50%
20%
20%
GND
TCIT, or
TXIT
TCIT, or
TXIT
图7-5. LVCMOS Input Transition Times
TCIP
TCIH
TCIL
VDD
50%
GND
VDD
50%
GND
VIHmin
TSTC
THTC
VILmax
Falling Edge CLK shown (RFB = GND)
图7-6. LVCMOS Input Setup/Hold and Clock High/Low Times (Falling Edge Strobe)
1.8V
VDD
GND
VDD
IN_CLK
GND
VDD
PDB
GND
TPLLS
OCA/B
(LVDS)
(Diff.)
图7-7. Start Up / Phase Lock Loop Set Time
GND
VDD
IN_CLK
GND
VDD
PDB
50%
GND
TPDD
OCA/B
(Diff.)
(LVDS)
图7-8. Sleep Mode / Power Down Delay
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
11
English Data Sheet: SNLS584
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
Cycle N
OA_C+/-,
or OB_C+/-
OA[3:0]+/-, or
OB[3:0]+/-
bit 1
n-1
bit 0
n-1
bit 6
n
bit 5
n
bit 4
n
bit 3
n
bit 2
n
bit 1
n
bit 0
n
1UI
2UI
3UI
4UI
5UI
6UI
7UI
图7-9. LVDS Serial Bit Positions
IN_CLK
IN_n
DE
Pixel 1
Pixel 2
TLAT
Pixel 3
Pixel 4
OA/B_C+/
-
OA_n+/-
Pixel 1
Pixel 2
Pixel 3
Pixel 4
OB_n+/-
图7-10. Single In, Dual Out Mode Timing and Latency
IN_CLK
IN_n
Pixel n-1
Pixel n
Pixel n+1
Pixel n+2
Pixel n+3
TSD
OA/B_C+/-
OA/B_n+/-
Pixel n
Pixel n+1
图7-11. Single In, Single Out Mode Timing and Latency
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNLS584
12
Submit Document Feedback
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
7.9 Typical Characteristics
110
100
90
60
VODSEL = L
VODSEL = H
VODSEL = L
VODSEL = H
55
50
45
40
35
30
25
20
80
70
60
50
40
30
40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
20
40
60
80
100
120
FREQUENCY (MHz)
图7-12. Typical Current Draw —Single In/Dual Out 图7-13. Typical Current Draw —Single In/Single
Mode —PRBS-7 Data Pattern
Out Mode —PRBS-7 Data Pattern
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
13
English Data Sheet: SNLS584
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
8 Detailed Description
8.1 Overview
DS90C189-Q1 converts a wide parallel LVCMOS input bus into banks of OLDI (LVDS) data. The device can be
configured to support RGB-888 (24-bit color) in two main configurations: single pixel in / single pixel out; single
pixel in / dual pixel out. The DS90C189-Q1 has power saving features including: selectable VOD and a power
down pin control.
8.2 Functional Block Diagrams
LVCMOS INPUTS
RED
GREEN
IN_[27:21],
IN_[17:0]
BLUE
DATA (LVDS)
CNTRL (L/R)
HS
VS
DE
IN_CLK
PLL
CLOCK (LVDS)
PDB
VODSEL
RFB
MODE0
DS90C189-Q1
Single Pixel In / Single Pixel Out
(SISO)
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNLS584
14
Submit Document Feedback
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
LVCMOS INPUTS
RED
GREEN
IN_[27:21],
IN_[17:0]
BLUE
CNTRL (L/R)
HS
VS
DE
DATA (LVDS)
CLOCK (LVDS)
PLL
IN_CLK
PDB
VODSEL
RFB
MODE0
DS90C189-Q1
Single Pixel In / Dual Pixel Out (SIDO)
8.3 Feature Description
8.3.1 AEC-Q100 Qualified
The DS90C189-Q1 is qualified to AEC-Q100 Grade 2 standards and operates from -40°C to +105°C.
8.3.2 ESD Protection
The DS90C189-Q1 has a HBM ESD Classification Level of ±8 kV and CDM ESD Classification Level of ±750 V.
8.3.3 Operating Modes
The DS90C189-Q1 has two operating modes: Single Pixel In, Single Pixel Out (SISO), 25 MHz – 105 MHz and
Single Pixel In, Dual Pixel Out (SIDO), 50 MHz –185 MHz.
8.3.4 LVDS Configurations
The DS90C189-Q1 supports 3D+C, 4D+C, 6D+C, 6D+2C, 8D+C, and 8D+2C LVDS configurations.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
15
English Data Sheet: SNLS584
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
8.4 Device Functional Modes
8.4.1 Device Configuration
The MODE0 pin is used to configure the DS90C189-Q1 into the two main operation modes as shown in the table
below.
表8-1. Mode Configurations
MODE0
CONFIGURATION
0
1
Single Pixel Input, Single Pixel Output (SISO)
Single Pixel Input, Dual Pixel Output (SIDO)
8.4.2 Single Pixel Input / Single Pixel Output
When MODE0 is set to low, data from IN_[27:21], IN_[17:0], HS, VS and DE is serialized and driven out on
OA_[3:0]+/- with OA_C+/-.
In this configuration IN_CLK can range from 25 MHz to 105 MHz, resulting in a total maximum payload of 700
Mbps (28 bits * 25MHz) to 2.94 Gbps (28 bits * 105 MHz). Each LVDS driver will operate at a speed of 7 bits per
input clock cycle, resulting in a serial line rate of 175 Mbps to 735 Mbps. OA_C+/- will operate at the same rate
as IN_CLK with a duty cycle ratio of 57:43.
8.4.3 Single Pixel Input / Dual Pixel Output
When MODE0 is HIGH, data from IN_[27:21], IN_[17:0], HS, VS and DE is serialized and driven out on
OA_[3:0]+/- and OB_[3:0]+/- with OA_C+/- and OB_C+/-. The input LVCMOS data is split into odd and even
pixels starting with the odd (first) pixel outputs OA_[3:0]+/- and then the even (second) pixel outputs OB_[3:0]+/-.
The splitting of the data signals starts with DE (data enable) transitioning from logic LOW to HIGH indicating
active data (see 图 7-10). The number of clock cycles during blanking must be an EVEN number. This
configuration will allow the user to interface with two FPD-Link receivers or other dual pixel inputs.
In this configuration IN_CLK can range from 50 MHz to 185 MHz, resulting in a total maximum payload of 1.4
Gbps (28 bits * 50 MHz) to 5.18 Gbps (28 bits * 185 MHz). Each LVDS driver will operate at a speed of 7 bits per
2 input clock cycles, resulting in a serial line rate of 175 Mbps to 647.5 Mbps. OA_C+/- and OA_B+/- will operate
at ½ the rate as IN_CLK with a duty cycle ratio of 57:43.
In the Single Pixel Input / Dual Pixel Output mode OA_x and OB_x can become misaligned if the clock or data is
interrupted or PDB is toggled. If the clock or data is interrupted or PDB is toggled to prevent misalignment the
following should be done:
1. Disable the clock and data.
2. Toggle PDB to Low and then High.
3. After PDB settles reset the data pattern and enable the clock and data.
8.4.4 Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the input LVCMOS data is latched on. If RFB is HIGH, input data is
latched on the RISING EDGE of the pixel clock (IN_CLK). If RFB is LOW, the input data is latched on the
FALLING EDGE of the pixel clock. Note: This can be set independently of receiver’s output clock strobe.
表8-2. Pixel Clock Edge
RFB
Result
0
1
FALLING edge
RISING edge
8.4.5 Power Management
The DS90C189-Q1 has several features to assist with managing power consumption. The device can be
configured through the MODE0 control pin to enable only the required number of LVDS drivers for each
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNLS584
16
Submit Document Feedback
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
application. If no clock is applied to the IN_CLK pin, the DS90C189-Q1 will enter a low power state. To place the
DS90C189-Q1 in its lowest power state, the device can be powered down by driving the PDB pin to LOW.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
17
English Data Sheet: SNLS584
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
8.4.6 Sleep Mode (PDB)
The DS90C189-Q1 provides a power down feature. When the device has been powered down, current draw
through the supply pins is minimized and the PLL is shut down. The LVDS drivers are also powered down with
their outputs pulled to GND through 100-Ω resistors (not tri-stated).
表8-3. Power Down Select
PDB
Result
0
1
SLEEP Mode (default)
ACTIVE (enabled)
8.4.7 LVDS Outputs
The DS90C189-Q1's LVDS drivers are compatible with ANSI/TIA/EIA-644-A LVDS receivers. The LVDS drivers
can output a power saving low VOD, or a high VOD to enable longer trace and cable lengths by configuring the
VODSEL pin.
表8-4. VOD Select
VODSEL
Result
0
1
±220 mV (440 mVpp)
±340 mV (680 mVpp)
Any unused LVDS outputs that are not powered down due to the MODE0 pin should be externally terminated
differentially with a 100 ohm resistor. For example, when driving a timing controller (TCON) that only requires an
8D + C LVDS interface, rather than 8D + 2C, the unused clock line should be terminated near the package of the
DS90C189-Q1. For more information regarding the electrical characteristics of the LVDS outputs, refer to the
LVDS DC Characteristics and LVDS Switching Specifications.
8.4.8 LVCMOS Inputs
The DS90C189-Q1 has one bank of 24 data inputs, one set of video control signal (HS, VS and DE) inputs and
several device configuration LVCMOS pins. All LVCMOS input pins are designed for 1.8 V LVCMOS logic. All
LVCMOS inputs, including clock, data and configuration pins, have an internal pull down resistor to set a default
state. If any inputs are unused, they can be left as no connect (NC) or connected to ground.
8.5 Programming
8.5.1 LVDS Interface / TFT Color Data Recommended Mapping
Different color mapping options exist. Check with the color mapping of the Deserializer / TCON device that is
used to ensure compatible mapping for the application. The DS90C189-Q1 supports two modes of operation for
single and dual pixel applications supporting 24bpp color depths.
In the Dual Pixel / 24bpp mode, eight LVDS data lines are provided along with two LVDS clock lines (8D+2C).
The Deserializer may utilize one or two clock lines. The 53 bit interface typically assigns 24 bits to RGB for the
odd pixel, 24 bits to RGB for the even pixel, 3 bits for the video control signals (HS, VS and DE), 1 bit for odd
pixel and 1 bit for even pixel which can be ignored or used for general purpose data, control or L/R signaling.
A reduced width input interface is also supported with a Single-to-Dual Pixel conversion where the data is
presented at double rate (same clock edge, 2X speed, see 图 7-10) and the DE transition is used to flag the first
pixel. Also note in the 8D+2C configuration, the three video control signals are sent over both the A and B
outputs. The DES / TCON may recover one set, or both depending upon its implementation. The Dual Pixel /
24bpp 8D+2C LVDS Interface Mapping is shown in 图8-1.
In the Single Pixel / 24bpp mode, four LVDS data lines are provided along with a LVDS clock line (4D+C). The
28 bit interface typically assigns 24 bits to RGB color data, 3 bits to video control (HS, VS and DE) and one
spare bit can be ignored, used for L/R signaling or function as a general purpose bit. The Single Pixel / 24bpp
4D+C LVDS Interface Mapping is shown in 图8-2.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNLS584
18
Submit Document Feedback
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
OA_C+/-
(Diff)
Current Cycle
IN_27 IN_26 IN_25 IN_24 IN_23 IN_22 IN_21
OA_3+/-
(SE)
OA_2+/-
(SE)
DE
VS
HS IN_17 IN_16 IN_15 IN_14
OA_1+/-
(SE)
IN_13 IN_12 IN_11 IN_10 IN_9 IN_8 IN_7
IN_6 IN_5 IN_4 IN_3 IN_2 IN_1 IN_0
IN_27 IN_26 IN_25 IN_24 IN_23 IN_22 IN_21
OA_0+/-
(SE)
OB_3+/-
(SE)
OB_2+/-
(SE)
DE
VS
HS IN_17 IN_16 IN_15 IN_14
OB_1+/-
(SE)
IN_13 IN_12 IN_11 IN_10 IN_9 IN_8 IN_7
IN_6 IN_5 IN_4 IN_3 IN_2 IN_1 IN_0
OB_0+/-
(SE)
OB_C+/-
(Diff)
图8-1. Dual Pixel / 24bpp LVDS Mapping
OA_C+/-
(Diff)
Current Cycle
OA_3+/-
(SE)
IN_27 IN_26 IN_25 IN_24 IN_23 IN_22 IN_21
OA_2+/-
(SE)
DE
VS
HS IN_17 IN_16 IN_15 IN_14
OA_1+/-
(SE)
IN_13 IN_12 IN_11 IN_10 IN_9 IN_8 IN_7
IN_6 IN_5 IN_4 IN_3 IN_2 IN_1 IN_0
OA_0+/-
(SE)
图8-2. Single Pixel / 24bpp LVDS Mapping
8.5.1.1 Color Mapping Information
A defacto color mapping is shown next. Different color mapping options exist. Check with the color mapping of
the Deserializer / TCON device that is used to ensure compatible mapping for the application.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
19
English Data Sheet: SNLS584
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
表8-5. Single Pixel Input / 24bpp / MSB on CH3
DS90C189-Q1 Input
Color Mapping Note
IN_22
IN_21
IN_5
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
DE
VS
HS
GP
MSB
IN_4
IN_3
IN_2
IN_1
IN_0
LSB
IN_24
IN_23
IN_11
IN_10
IN_9
MSB
IN_8
IN_7
IN_6
LSB
IN_26
IN_25
IN_17
IN_16
IN_15
IN_14
IN_13
IN_12
DE
MSB
Data Enable(1)
Vertical Sync
VS
HS
Horizontal Sync
General Purpose
IN_27
(1) See section 节8.4.3.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNLS584
20
Submit Document Feedback
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
表8-6. Single Pixel Input / 24bpp / LSB on CH3
DS90C189-Q1 Input
Color Mapping Note
IN_5
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
DE
VS
HS
GP
MSB
IN_4
IN_3
IN_2
IN_1
IN_0
IN_22
IN_21
IN_11
IN_10
IN_9
LSB
MSB
IN_8
IN_7
IN_6
IN_24
IN_23
IN_17
IN_16
IN_15
IN_14
IN_13
IN_12
IN_26
IN_25
DE
LSB
MSB
Data Enable(1)
Vertical Sync
VS
HS
Horizontal Sync
General Purpose
IN_27
(1) See section 节8.4.3.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
21
English Data Sheet: SNLS584
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The DS90C189-Q1 is a Low Power Bridge for automotive application that reduces the size of the RGB interface
between the host GPU and the Display. It is designed to support single pixel data transmission between Host
and Flat Panel Display up to QXGA (2048x1536) at 60 Hz resolutions. The transmitter converts up to 24 bits
(Single Pixel 24 bit color) of 1.8-V LVCMOS data into two channels of 4 data + clock (4D+C) reduced width
interface LVDS compatible data streams.
9.2 Typical Application
1.8 V LVCMOS
(24 bit RGB + HS/VS/DE)
2 Channels FPD-Link (LVDS)
(4 Data + Clock)
1.8 V
GPU
Display (TCON)
DS90C189-
Q1
LVDS
4D+C
(odd pixel)
L
A
T
C
H
Single Pixel
R[7:0] G[7:0]
B[7:0]
LVDS
4D+C
(even pixel)
&
P
2
S
HS
VS
DE
GPO/CNTL (L/R)
PCLK
PLL
PDB
Copyright © 2017, Texas Instruments Incorporated
图9-1. Single Pixel In Dual Pixel Out (SIDO) Mode
9.2.1 Design Requirements
The DS90C189-Q1 is used to convert 24-bit color to two channels of LVDS datastreams.
表9-1. Design Parameters
DESIGN PARAMETER
VALUE
1.8V
Supply
Display Driven
Pixel Depth
SXGA+, WUXGA+
24 bits
Copyright © 2023 Texas Instruments Incorporated
22
Submit Document Feedback
English Data Sheet: SNLS584
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
9.2.2 Detailed Design Procedure
9.2.2.1 LVDS Interconnect Guidelines
Refer to the AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and Transmission
Line RAPIDESIGNER Operation and Applications Guide (SNLA035) for full details.
• Use 100-Ω coupled differential pairs
• Use differential connectors when above 500 Mbps
• Minimize skew within the pair
• Use the S/2S/3S rule in spacings
– S = space between the pairs
– 2S = space between pairs
– 3S = space to LVCMOS signals
• Place ground vias next to signal vias when changing between layers
• When a signal changes reference planes, place a bypass cap and vias between the new and old reference
plane
For more tips and detailed suggestions regarding high speed board layout principles, see the LVDS Owner's
Manual at http://www.ti.com/lvds
9.2.3 Application Curves
110
100
90
60
55
50
45
40
35
30
25
20
VODSEL = L
VODSEL = H
VODSEL = L
VODSEL = H
80
70
60
50
40
30
40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
20
40
60
80
100
120
FREQUENCY (MHz)
图9-2. Typical Current Draw - Single In/Dual Out 图9-3. Typical Current Draw - Single In/Single Out
Mode - PRBS-7 Data Pattern Mode - PRBS-7 Data Pattern
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
23
English Data Sheet: SNLS584
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
10 Power Supply Recommendations
10.1 Power Up Sequence
The VDD power supply ramp should start from GND +/-5mV and ramp monotonically to the recommended
supply voltage. The VDD power supply pins do not require a specific power on sequence and can be powered on
in any order. However, the PDB pin should only be set to logic HIGH once the power sent to all supply pins is
stable. Active data inputs should not be applied to the DS90C189-Q1 until all of the input power pins have been
powered on, settled to the recommended operating voltage and the PDB pin has be set to logic HIGH.
The user experience can be impacted by the way a system powers up and powers down an LCD screen. The
following sequence is recommended:
Power up sequence (DS90C189-Q1 PDB input initially LOW):
1. Ensure that all supply pins are at GND +/-5mV
2. Ramp up LCD power (maybe 0.5ms to 10ms) but keep backlight turned off.
3. Toggle DS90C189-Q1 power down pin to PDB = VDD
.
4. Enable clock and wait for additional 0-200ms to ensure display noise won’t occur.
5. Enable video source output; start sending black video data.
6. Send >1ms of black video data; this allows the DS90C189-Q1 to be phase locked, and the display to show
black data first.
7. Start sending true image data.
8. Enable backlight.
Power Down sequence (DS90C189-Q1 PDB input initially HIGH):
1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low.
2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive
this for >2 frame times.
3. Set DS90C189-Q1 power down pin to PDB = GND.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for lowest system power.
6. Ensure that VDD supply discharges to GND +/- 5mV before starting the next power up sequence. If rapid
power off/on system behavior is required, then it is recommended to utilize a discharge circuit to ensure VDD
returns to GND +/- 5mV between power off/on conditions
10.2 Power Supply Filtering
The DS90C189-Q1 has several power supply pins at 1.8 V. It is important that these pins all be connected and
properly bypassed. Bypassing should consist of at least one 0.1μF capacitor placed on each pin, with an
additional 4.7 μF - 22 μF capacitor placed on the PLL supply pin (VDDP). 0.01 μF capacitors are typically
recommended for each pin. Additional filtering including ferrite beads may be necessary for noisy systems. It is
recommended to place a 0 ohm resistor at the bypass capacitors that connect to each power pin to allow for
additional filtering if needed. A large bulk capacitor is recommended at the point of power entry. This is typically
in the 50 μF —100 μF range.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNLS584
24
Submit Document Feedback
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
Circuit board layout and stack-up for the LVDS devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved
by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. This practice is
easier to implement in dense pcbs with many layers and may not be practical in simpler boards. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. It is recommended to connect power and ground pins
directly to the power and ground planes with bypass capacitors connected to the plane with vias on both ends of
the capacitor.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency. Some devices provide separate power and ground pins for different portions of
the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate
planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit
blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean
power to sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
For more information on the VQFN package, refer to the AN-1187 Leadless Leadframe Package (LLP)
application note (SNOA401).
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
25
English Data Sheet: SNLS584
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
11.2 Layout Example
图11-1. Layout Example
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNLS584
26
Submit Document Feedback
DS90C189-Q1
ZHCSI69B –JUNE 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see:
• LVDS Owner's Manual (SNLA187)
• AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008)
• Transmission Line RAPIDESIGNER Operation and Applications Guide (SNLA035)
• AN-1187 Leadless Leadframe Package (LLP) (SNOA401)
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
27
English Data Sheet: SNLS584
PACKAGE OPTION ADDENDUM
www.ti.com
3-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90C189TWRTDRQ1
DS90C189TWRTDTQ1
ACTIVE
ACTIVE
VQFN
VQFN
RTD
RTD
64
64
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 115
-40 to 115
DS90C189Q
DS90C189Q
Samples
Samples
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-May-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90C189TWRTDRQ1
DS90C189TWRTDTQ1
VQFN
VQFN
RTD
RTD
64
64
2500
250
330.0
180.0
16.4
16.4
9.3
9.3
9.3
9.3
1.1
1.1
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90C189TWRTDRQ1
DS90C189TWRTDTQ1
VQFN
VQFN
RTD
RTD
64
64
2500
250
367.0
210.0
367.0
185.0
38.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RTD0064F
VQFN - 0.9 mm max height
SCALE 1.600
PLASTIC QUAD FLATPACK - NO LEAD
9.1
8.9
A
B
0.15
0.05
0.05
0.00
PIN 1 ID
(0.15)
DETAIL
A
S
C
A
L
E
2
0
.
0
0
0
DETAIL A
TYPICAL
9.1
8.9
(
8.75)
0.2
0.1
(0.15)
DETAIL
B
S
C
A
L
E
2
0
.
0
0
0
DETAIL B
TYPICAL
0.9 MAX
SEE DETAIL A
SEE DETAIL B
C
SEATING PLANE
0.08 C
(0.2)
4X (45 X0.42)
32
17
16
33
SYMM
65
4X
5.75 0.1
7.5
1
48
0.3
64X
64X 0.5
64
49
0.2
SYMM
0.5
0.3
0.1
C B
C
A
64X
PIN 1 ID
(R0.2)
0.05
4223128/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTD0064F
VQFN - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
5.75)
(1.36) TYP
3X (1.265)
49
64X (0.6)
64
64X (0.25)
1
48
3X
(1.265)
60X (0.5)
SYMM
(1.36) TYP
(8.8)
65
(
0.2) TYP
VIA
16
33
32
17
SYMM
(8.8)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223128/A 08/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTD0064F
VQFN - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.36)
TYP
64X (0.6)
64X (0.25)
64
49
1
48
16X ( 1.16)
(1.36)
TYP
60X (0.5)
SYMM
65
(8.8)
METAL
TYP
33
16
17
32
SYMM
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 65:
65% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:8X
4223128/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
©2020 ICPDF网 联系我们和版权申明