DS90C3202VS/NOPB [TI]
3.3V 8MHz 至 135MHz 双路 FPD 链接接收器 | PDT | 128 | 0 to 70;
| 型号： | DS90C3202VS/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3V 8MHz 至 135MHz 双路 FPD 链接接收器 | PDT | 128 | 0 to 70 驱动 光电二极管 接口集成电路 |
| 文件： | 总27页 (文件大小：570K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90C3202
www.ti.com
SNLS191D –APRIL 2005–REVISED APRIL 2013
DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver
Check for Samples: DS90C3202
1
FEATURES
DESCRIPTION
The DS90C3202 is a 3.3V single/dual FPD-Link 10-
bit color receiver is designed to be used in Liquid
Crystal Display TVs, LCD Monitors, Digital TVs, and
Plasma Display Panel TVs. The DS90C3202 is
designed to interface between the digital video
processor and the display device using the low-
power, low-EMI LVDS (Low Voltage Differential
Signaling) interface. The DS90C3202 converts up to
ten LVDS data streams back into 70 bits of parallel
LVCMOS/LVTTL data. The receiver can be
programmed with rising edge or falling edge clock.
Optional wo-wire serial programming allows fine
tuning in development and production environments.
With an input clock at 135 MHz, the maximum
transmission rate of each LVDS line is 945 Mbps, for
an aggregate throughput rate of 9.45 Gbps (945
Mbytes/s). This allows the dual 10-bit LVDS Receiver
to support resolutions up to HDTV.
2
•
•
•
•
Up to 9.45 Gbit/s data throughput
8 MHz to 135 MHz input clock support
Supports up to QXGA panel resolutions
Supports HDTV panel resolutions and frame
rates up to 1920 x 1080p
•
•
•
•
•
LVDS 30-bit, 24-bit or 18-bit color data inputs
Supports single pixel and dual pixel interfaces
Supports spread spectrum clocking
Two-wire serial communication interface
Programmable clock edge and control strobe
select
•
•
•
•
Power down mode
+3.3V supply voltage
128-pin TQFP Package
Compliant to TIA/EIA-644-A-2001 LVDS
Standard
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
DS90C3202
SNLS191D –APRIL 2005–REVISED APRIL 2013
www.ti.com
Block Diagram
7
7
7
7
7
7
7
7
7
7
RXOA-/+
RXOB-/+
RXOC-/+
RXOD-/+
RXOE-/+
RXEA-/+
RXEB-/+
RXEC-/+
RXED-/+
RXEE-/+
RCLKIN-/+
RXOA[6:0]
RXOB[6:0]
RXOC[6:0]
RXOD[6:0]
RXOE[6:0]
RXEA[6:0]
RXEB[6:0]
RXEC[6:0]
RXED[6:0]
RXEE[6:0]
RCLKOUT
PLL
RFB
PWDNB
MODE0
MODE1
S2CLK
S2DAT
Figure 1. Receiver Block Diagram
Typical Application Diagram
Host
Display
LVDS
(PC, Graphics Board, Video Processor)
(LCD Monitor, LCD TV, Digital TV)
5 Pairs
DE
DE
Pixel Data
Pixel Data
5 Pairs
DS90C3201
FPD-Link
Transmitter
HSYNC
DS90C3202
FPD-Link
Receiver
Clock
Clock
HSYNC
VSYNC
Digital
Display
Video
Source
LVDS Clock
VSYNC
2-Wire Serial
Interface
Figure 2. LCD Panel Application Diagram
Functional Description
The DS90C3201 and DS90C3202 are a dual 10-bit color Transmitter and Receiver FPD-Link chipset designed to
transmit data at clocks speeds from 8 to 135 MHz. DS90C3201 and DS90C3202 are designed to interface
between the digital video processor and the display using a LVDS interface. The DS90C3201 transmitter
serializes 2 channels of video data (10-bit each for RGB for each channel, totaling 60 bits) and control signals
(HSYNC, VSYNC, DE and two user-defined signals) along with clock signal to 10 channels of LVDS signals and
transmits them. The DS90C3202 receiver converts 10 channels of LVDS signals into parallel signals and outputs
2
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C3202
DS90C3202
www.ti.com
SNLS191D –APRIL 2005–REVISED APRIL 2013
2 channels of video data (10-bit each for RGB for each channel, totaling 60 bits) and control signals (HSYNC,
VSYNC, DE and two user-defined signals) along with clock signal. The dual high speed LVDS channels supports
single pixel in-single pixel out and dual pixel in-dual pixel out transmission modes. The FPD-Link chipset is
suitable for a variety of display applications including LCD Monitors, LCD TV, Digital TV, and DLP TV, and
Plasma Display Panels.
Using a true 10-bit color depth system, the 30-bit RGB color produces over 1.07 billion colors to represent High
Definition (HD) displays in their most natural color, surpassing the maximum 16.7 million colors achieved by 6/8-
bit color conventionally used for large-scale LCD televisions and LCD monitors.
LVDS RECEIVER
The LVDS Receiver receives input RGB video data and control signal timing.
SELECTABLE OUTPUT DATA STROBE
The Receiver output data edge strobe can be latched on the rising or falling edges of clock signal. The dedicated
RFB pin is used to program output strobe select on the rising edge of RCLK or the falling edge of RCLK.
2-WIRE SERIAL COMMUNICATION INTERFACE
Optional Two-Wire serial interface programming allows fine tuning in development and production environments.
The Two-Wire serial interface provides several capabilities to reduce EMI and to customize output timing. These
capabilities are selectable/programmable via Two-Wire serial interface: Programmable Skew Rates, Progress
Turn On Function, Input/Output Channel Control.
PROGRAMMABLE SKEW RATES
Programmable edge rates allow the LVCMOS/LVTTL Data and Clock outputs to be adjusted for better
impedance matching for noise and EMI reduction. The individual output drive control registers for Rx data out
and Rx clock out are programmable via Two-Wire serial interface.
PROGRESS TURN ON FUNCTION
Progress Turn On (PTO) function aligns the two output channels of LVCMOS/LVTLL in either a non-skew data
format (simultaneous switching) or a skewed data format (staggered). The skewed format delays the selected
channel data and staggers the outputs. This reduces the number of outputs switching simultaneously, which
lowers EMI radiation and minimizes ground bounce. Feature is controlled via Two-Wire serial interface.
INPUT/OUTPUT CHANNEL CONTROL
Full independent control for input/output channels can be disabled to minimize power supply line noise and
overall power dissipation. Feature is configured via Two-Wire serial interface
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: DS90C3202
DS90C3202
SNLS191D –APRIL 2005–REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
Absolute Maximum Ratings
Supply Voltage (VDD
)
−0.3V to +4V
−0.3V to (VDD + 0.3V)
−0.3V to (VDD + 0.3V)
−0.3V to (VDD + 0.3V)
+150°C
LVCMOS/LVTTL Input Voltage
LVCMOS/LVTTL Output Voltage
LVDS Receiver Input Voltage
Junction Temperature
Storage Temperature
−65°C to +150°C
+260°C
Lead Temperature (Soldering, 10 seconds)
Maximum Package Power Dissipation Capacity at 25°C
Package Derating
128 TQFP Package
1.4W
25.6mW/°C above +25°C
> 2 kV
ESD Rating:
HBM, 1.5kΩ, 100pF
EIAJ, 0Ω, 200pF
> 200 V
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Recommended Operating Conditions
Min
3.15
0
Nom
3.3
Max
3.6
Unit
V
Supply Voltage (VDD
)
Operating Free Air Temperature (TA)
+25
+70
±100
VDD
135
°C
Supply Noise Voltage (VP-P
)
mVp-p
V
Receiver Input Range
0
8
Input Clock Frequency (f)
MHz
4
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C3202
DS90C3202
www.ti.com
SNLS191D –APRIL 2005–REVISED APRIL 2013
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CMOS/TTL DC SPECIFICATIONS (Rx outputs, control inputs and outputs)
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
2.0
0
VDD
0.8
V
V
V
VOH
Rx clock out
Rx data out
Rx clock out
Rx data out
ICL = −18 mA
VIN = VDD
IOH = −4 mA
IOH = −2 mA
IOL = +4 mA
IOL = +2 mA
2.4
VOL
Low Level Output Voltage
0.4
V
VCL
IIN
Input Clamp Voltage
Input Current
−0.8
−1.5
V
+10
µA
µA
mA
VIN = 0V
−10
IOS
Output Short Circuit Current
VOUT = 0V
−120
LVDS RECEIVER DC SPECIFICATIONS
VTH
VTL
VIN
Differential Input High Threshold VCM = +1.2V
Differential Input Low Threshold
+100
mV
mV
V
−100
Input Voltage Range (Single-
ended)
0
VDD
|VID
|
Differential Input Voltage
0.200
0.2
0.600
V
V
VCM
Differential Common Mode
Voltage
1.2
VDD−0.1
IIN
Input Current
VIN = +2.4V, VDD = 3.6V
±10
±10
µA
µA
VIN = 0V, VDD = 3.6V
RECEIVER SUPPLY CURRENT
ICCRW
ICCRG
ICCRZ
Receiver Supply Current, Worst CL = 8 pF,
f = 8 MHz
65
130
550
mA
mA
Case
Worst Case Pattern,
f = 135 MHz
375
(Figure 4 , Figure 6)
Default Register Settings
Receiver Supply Current,
Incremental Test Pattern
(Figure 5 , Figure 6)
CL = 8 pF,
Worst Case Pattern,
Default Register Settings
f = 8 MHz
55
120
400
mA
mA
f = 135 MHz
245
Receiver Supply Current, Power PDWNB = Low,
Down Receiver Outputs stay low during
2
mA
Powerdown mode,
Default Register Settings
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: DS90C3202
DS90C3202
SNLS191D –APRIL 2005–REVISED APRIL 2013
www.ti.com
Receiver Switching Characteristics(1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
CLHT
Parameter
Condition or
Reference
Min
Typ
Max
Unit
LVCMOS/LVTTL Low-to-High Transition Time, CL Rx clock out
1.45
2.40
2.10
3.50
ns
ns
(2)
= 8pF, (Figure 7)
Rx data out
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
CHLT
LVCMOS/LVTTL High-to-Low Transition Time, CL Rx clock out
1.35
2.40
2.20
3.60
ns
ns
(2)
= 8pF, (Figure 7)
Rx data out
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
CLHT
Programmable
adjustment
LVCMOS/LVTTL Low-to-High Transition Time, CL Rx clock out
2.45
3.40
ns
ns
(2)
= 8pF, (Figure 7)
Rx data out
Register addr 28d/1ch,
bit [2] (RCLK)=1b (Default),
bit [1] (RXE) =1b (Default),
bit [0] (RXO) =1b (Default)
CHLT
Programmable
adjustment
LVCMOS/LVTTL High-to-Low Transition Time, CL Rx clock out
2.35
3.40
ns
ns
(2)
= 8pF, (Figure 7)
Rx data out
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
(2)
RCOP
RCOH
RCOL
RSRC
RCLK OUT Period (Figure 13, Figure 14)
RCLK OUT High Time (Figure 13 , Figure 14)
RCLK OUT Low Time (Figure 13 , Figure 14)
8–135 MHz
Rx clock out
7.4
T
125
0.6T
0.6T
ns
ns
ns
ns
0.4T
0.4T
2.60
0.5T
0.5T
0.5T
Rx clock out
(2) (3)
RxOUT Setup to RCLK OUT (Figure 13, Figure 14)
Register addr 29d/1dh [2:1]= 00b (Default)
(2) (3)
RHRC
RxOUT Hold to RCLK OUT (Figure 13 , Figure 14)
Register addr 29d/1dh [2:1]= 00b (Default)
3.60
0.5T
ns
ns
(4)
RSRC/RHRC
Programmable
Adjustment
Register addr 29d/1dh [2:1] = 01b, (Figure 15, Figure 16)
RSRC increased from default by 1UI
+1UI / -1UI
RHRC decreased from default by 1UI
(4)
(4)
Register addr 29d/1dh [2:1] = 10b, (Figure 15 Figure 16)
RSRC decreased from default by 1UI
RHRC increased from default by 1UI
-1UI / +1UI
+2UI / -2UI
ns
ns
Register addr 29d/1dh [2:1] = 11b, (Figure 15 Figure 16)
RSRC increased from default by 2UI
RHRC decreased from default by 2UI
RPLLS
RPDD
RPDL
RITOL
Receiver Phase Lock Loop Set (Figure 8)
Receiver Powerdown Delay (Figure 9)
10
100
ms
ns
ns
UI
Receiver Propagation Delay — Latency (Figure 10)
4*RCLK
0.25
Receiver Input Tolerance
VCM = 1.25V,
VID = 350mV
(2) (4)
(Figure 12 Figure 18)
(1) Typical values are given for VDD = 3.3V and T A = +25°C.
(2) Specification is ensured by characterization.
(3) A Clock Unit Symbol (T) is defined as 1/ (Line rate of RCLK). E.g. For Line rate of RCLK at 85MHz, 1 T = 11.76ns
(4) A Unit Interval (UI) is defined as 1/7th of an ideal clock period (RCLK/7). E.g. For an 11.76ns clock period (85MHz), 1 UI = 1.68ns
6
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C3202
DS90C3202
www.ti.com
SNLS191D –APRIL 2005–REVISED APRIL 2013
Two-Wire Serial Communication Interface
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
fSC
Parameter
S2CLK Clock Frequency
Clock Low Period
Conditions
Min
Typ
Max
Unit
kHz
us
400
SC:LOW
SC:HIGH
SCD:TR
SCD:TF
SU:STA
HD:STA
HD:STO
SC:SD
SD:SC
SCL:SD
BUF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
RP = 4.7KΩ, CL = 50pF
1.5
0.6
Clock High Period
us
S2CLK and S2DAT Rise Time
S2CLK and S2DAT Fall Time
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Hold Time
Clock Falling Edge to Data
Data to Clock Rising Edge
S2CLK Low to S2DAT Data Valid
Bus Free Time
0.3
0.3
us
us
0.6
0.6
0.6
0
us
us
us
us
0.1
0.1
13
us
0.9
us
us
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: DS90C3202
DS90C3202
SNLS191D –APRIL 2005–REVISED APRIL 2013
www.ti.com
AC Timing Diagrams
SCD:TF
SCD:TR
f
SC
SC:LOW
SC:HIGH
S2CLK
HD:STO
SU:STA
HD:STA
S2DAT
Data in
SD:SC
SC:SD
S2DAT
Data out
SCL:SD
Figure 3. Two-Wire Serial Communication Interface Timing Diagram
Figure 4. “Worst Case” Test Pattern
TCLKIN
TXOA, TXEA
TXOB, TXEB
TXOC, TXEC
TXOD, TXED
TXOE, TXEE
Figure 5. Incremental Test Pattern
600
Worst Case
(max)
500
400
Worst Case
(typ)
300
200
100
Incr. Pattern
(typ)
Incr. Pattern
(max)
0
0
20 40 60 80 100 120 140 160
FREQUENCY (MHz)
Figure 6. Typical and Max ICC with Worse Case and Incremental Pattern
8
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C3202
DS90C3202
www.ti.com
SNLS191D –APRIL 2005–REVISED APRIL 2013
AC Timing Diagrams (continued)
Figure 7. LVCMOS/LVTTL Output Load and Transition Times
2V
PWDNB
3.15V
V
DD
RPLLS
RCLK IN
2V
RCLKOUT
Figure 8. Receiver Phase Lock Loop Wake-up Time
1.5V
PWDNB
Low
RCLK IN
RPDD
RCLKOUT
Low
Figure 9. Powerdown Delay
+
VDIFF
0V
=
RCLKIN
Rx IN
-
+
-
RPDL
RCLKOUT
(RFB=1)
1.5V
Rx OUT
Figure 10. Receiver Propagation Delay
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: DS90C3202
DS90C3202
SNLS191D –APRIL 2005–REVISED APRIL 2013
www.ti.com
AC Timing Diagrams (continued)
RCLKOUT
RxOUT
RFB = 0
RFB = 1
Figure 11. RFB: LVTTL Level Programmable Strobe Select
Sampling
Window
Ideal Bit Stop
Ideal Bit Start
RITOL
(Left)
RITOL
(Right)
Ideal Strobe Position
t
BIT
( )
2
t
BIT
(1UI)
RITOL ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Please see AN-1217 (SNLA053) for more details.
Cycle-to-cycle jitter is less than 100 ps (worse case estimate).
ISI is dependent on interconnect length; may be zero.
Figure 12. Receiver Input Tolerance and Sampling Window
RCOP
RCOH
RSRC
RCOL
RHRC
RFB=0
RFB=1
RCLK OUT
V
/2
V
DD
/2
DD
RXOA,B,C,D,E[6:0]
RXEA,B,C,D,E[6:0]
V
/2
V
DD
/2
DD
Register address 29d/1dh bit [2:1] = 00b
Figure 13. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Disabled
10
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C3202
DS90C3202
www.ti.com
SNLS191D –APRIL 2005–REVISED APRIL 2013
AC Timing Diagrams (continued)
RCOP
RCOH
RCOL
RFB=0
RCLK OUT
V
DD
/2
V
DD
/2
RFB=1
RXEB,D[6:0]
RXOA,C,E[6:0]
V
DD
/2
V
DD
/2
RXEA,C,E[6:0]
RXOB,D[6:0]
V
DD
/2
1/2 UI
1/2 UI
RegisterAddress 29d/1dh bit [2:1] = 00b
Figure 14. Receiver RSRC and RHRC Output Setup/Hold Time — PTO Enabled
RCOP
RCOH
RCOL
RFB=0
RFB=1
Balanced RSRC / RHRC
Register addr 29d/1dh bit[2:1]=00b (default)
RCLK OUT
RCLK OUT
RCLK OUT
RCLK OUT
V
/2
V
/2
DD
DD
RSRC
RHRC
RSRC Increased by 1UI, RHRC Decreased by 1UI
Register addr 29d/1dh bit[2:1]=01b
V
/2
V
/2
DD
DD
+1 UI
-1 UI
RSRC
RHRC
RSRC Decreased by 1UI, RHRC Increased by 1UI
Register addr 29d/1dh bit[2:1]=10b
V
/2
V
DD
/2
DD
-1 UI
+1 UI
RSRC
RHRC
-2 UI
RSRC Increased by 2UI, RHRC Decreased by 2UI
Register addr 29d/1dh bit[2:1]=11b
V
DD
/2
V
DD
/2
+2 UI
RXOA,B,C,D,E[6:0]
RXEA,B,C,D,E[6:0]
V
DD
/2
V
DD
/2
Figure 15. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Disabled
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: DS90C3202
DS90C3202
SNLS191D –APRIL 2005–REVISED APRIL 2013
www.ti.com
AC Timing Diagrams (continued)
RCOP
RFB=0
Balanced RSRC / RHRC
Register addr 29d/1dh bit[2:1]=00b (default)
RCLK OUT
RCLK OUT
RCLK OUT
RCLK OUT
V
/2
V
V
/2
DD
DD
RFB=1
RSRC Increased by 1UI, RHRC Decreased by 1 UI
Register addr 29d/1dh bit[2:1]=01b
RSRC
RHRC
V
DD
/2
/2
DD
RSRC Decreased by 1UI, RHRC Increased by 1 UI
Register addr 29d/1dh bit[2:1]=10b
RSRC
RHRC
V
/2
V
/2
DD
DD
RSRC Increased by 2UI, RHRC Decreased by 2 UI
Register addr 29d/1dh bit[2:1]=11b
RSRC
RHRC
V
/2
V
DD
/2
DD
RXEB,D[6:0]
RXOA,C,E[6:0]
V
/2
V
/2
DD
DD
/2
RXEA,C,E[6:0]
RXOB,D[6:0]
V
/2
V
DD
DD
-0.5 UI Less RHRC on
RXEA,C,E[6:0]; RXOB,D[6:0]
Additional +0.5 UI RSRC on
RXEA,C,E[6:0]; RXOB,D[6:0]
Figure 16. Receiver RSRC and RHRC Output Setup/Hold Time Adjustment — PTO Enabled
12
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C3202
DS90C3202
www.ti.com
SNLS191D –APRIL 2005–REVISED APRIL 2013
AC Timing Diagrams (continued)
RCLK IN
(Differential)
V
= 0V
V
DIFF
= 0V
DIFF
Previous
cycle
Current
Cycle
Next
cycle
OA1-1
OB1-1
OC1-1
OD1-1
OE1-1
EA1-1
EB1-1
EC1-1
ED1-1
EE1-1
OA0-1
OB0-1
OC0-1
OD0-1
OE0-1
EA0-1
EB0-1
EC0-1
ED0-1
EE0-1
OA6
OB6
OC6
OD6
OE6
EA6
EB6
EC6
ED6
EE6
OA5
OB5
OC5
OD5
OE5
EA5
EB5
EC5
ED5
EE5
OA4
OB4
OC4
OD4
OE4
EA4
EB4
EC4
ED4
EE4
OA3
OB3
OC3
OD3
OE3
EA3
EB3
EC3
ED3
EE3
OA2
OB2
OC2
OD2
OE2
EA2
EB2
EC2
ED2
EE2
OA1
OA0
OB0
OC0
OD0
OE0
EA0
EB0
EC0
ED0
EE0
RXOA+/-
RXOB+/-
RXOC+/-
RXOD+/-
RXOE+/-
RXEA+/-
RXEB+/-
RXEC+/-
RXED+/-
RXEE+/-
OB1
OC1
OD1
OE1
EA1
EB1
EC1
ED1
EE1
Figure 17. LVDS Input Mapping
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: DS90C3202
DS90C3202
SNLS191D –APRIL 2005–REVISED APRIL 2013
www.ti.com
AC Timing Diagrams (continued)
RCLK IN
(Differential)
V
= 0V
V
DIFF
= 0V
DIFF
Previous
cycle
Current
Cycle
Next
cycle
OA1
OB1
OC1
OD1
OE1
EA1
EB1
EC1
ED1
EE1
OA0
OB0
OC0
OD0
OE0
EA0
EB0
EC0
ED0
EE0
RXOA+/-
RXOB+/-
RXOC+/-
RXOD+/-
RXOE+/-
RXEA+/-
RXEB+/-
RXEC+/-
RXED+/-
RXEE+/-
RITOL 1 min
RITOL 1 max
RITOL 0 min
RITOL 0 max
RITOL 6 min
RITOL 6 max
RITOL 5 min
RITOL 5 max
RITOL 4 min
RITOL 4 max
RITOL 3 min
RITOL 3 max
RITOL 2 min
RITOL 2 max
Figure 18. Receiver RITOL Min and Max
14
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C3202
DS90C3202
www.ti.com
SNLS191D –APRIL 2005–REVISED APRIL 2013
PIN ASSIGNMENTS
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
RESRVD
97
98
99
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VSS4
MODE1
VSSL
RXOD0
RXOE6
RXOE5
RXOE4
RXOE3
RXOE2
RXOE1
RXOE0
VDD3
VDDL
100
RXOA-
RXOA+
RXOB-
RXOB+
RXOC-
RXOC+
RXOD-
RXOD+
RXOE-
RXOE+
VSSL
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
VSS3
RXEA6
RXEA5
RXEA4
RXEA3
RXEA2
RXEA1
RXEA0
VDD2
VSSL
2
DS90C320
VDDL
VDDL
RCLKIN-
RCLKIN+
RXEA-
VSS2
RCLKOUT
VDDR1
VSSR1
RXEB6
RXEB5
RXEB4
RXEB3
RXEB2
RXEB1
RXEB0
RXEC6
VDD1
+
118
119
120
RXEA
RXEB
-
RXEB+
RXEC-
RXEC+
RXED-
RXED+
RXEE-
RXEE+
MODE0
121
122
123
124
125
126
127
128
RFB
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 19. DS90C3202 Receiver
DS90C3202 PIN DESCRIPTIONS
Pin No.
Pin Name
S2DAT
S2CLK
VDDP1
VSSP1
VSSP0
VDDP0
PWDNB
I/O
I/OP
I/P
Pin Type
Description
1
2
3
4
5
6
7
Digital
Digital
PLL
Two-wire Serial Interface – Data
Two-wire Serial Interface – Clock
Power supply for PLL circuitry
Ground pin for PLL circuitry
Ground pin for PLL circuitry
Power supply for PLL circuitry
VDD
GND
GND
VDD
I/P
PLL
PLL
PLL
LVTTL I/P (pulldown)
Powerdown Bar (Active LOW)
0 = DEVICE DISABLED
1 = DEVICE ENABLED
8
RXEE0
O/P
LVTTL O/P
LVTTL level data output
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: DS90C3202
DS90C3202
SNLS191D –APRIL 2005–REVISED APRIL 2013
www.ti.com
DS90C3202 PIN DESCRIPTIONS (continued)
Pin No.
9
Pin Name
RXEE1
RXEE2
RXEE3
RXEE4
RXEE5
RXEE6
VSS0
I/O
O/P
O/P
O/P
O/P
O/P
O/P
GND
VDD
Pin Type
LVTTL O/P
Description
LVTTL level data output
10
LVTTL O/P
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
11
LVTTL O/P
12
LVTTL O/P
13
LVTTL O/P
14
LVTTL O/P
15
LVTTL O/P PWR
LVTTL O/P PWR
Ground pin for LVTTL outputs and digital circuitry
16
VDD0
Power supply pin for LVTTL outputs and digital
circuitry
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
RXED0
RXED1
RXED2
RXED3
RXED4
RXED5
RXED6
VSSR0
VDDR0
RXEC0
RXEC1
RXEC2
RXEC3
RXEC4
RXEC5
VSS1
O/P
O/P
O/P
O/P
O/P
O/P
O/P
GND
VDD
O/P
O/P
O/P
O/P
O/P
O/P
GND
VDD
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
RX LOGIC
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
Ground pin for logic
RX LOGIC
Power supply for logic
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P PWR
LVTTL O/P PWR
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
Ground pin for LVTTL outputs and digital circuitry
VDD1
Power supply pin for LVTTL outputs and digital
circuitry
34
35
36
37
38
39
40
41
42
43
44
45
46
RXEC6
RXEB0
RXEB1
RXEB2
RXEB3
RXEB4
RXEB5
RXEB6
VSSR1
VDDR1
RCLKOUT
VSS2
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
GND
VDD
O/P
GND
VDD
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
RX LOGIC
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
Ground pin for logic
RX LOGIC
Power supply for logic
LVTTL O/P
LVTTL O/P PWR
LVTTL O/P PWR
LVTTL level clock output
Ground pin for LVTTL outputs and digital circuitry
VDD2
Power supply pin for LVTTL outputs and digital
circuitry
47
48
49
50
51
52
53
RXEA0
RXEA1
RXEA2
RXEA3
RXEA4
RXEA5
RXEA6
O/P
O/P
O/P
O/P
O/P
O/P
O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
16
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C3202
DS90C3202
www.ti.com
SNLS191D –APRIL 2005–REVISED APRIL 2013
DS90C3202 PIN DESCRIPTIONS (continued)
Pin No.
54
Pin Name
VSS3
I/O
Pin Type
LVTTL O/P PWR
Description
GND
VDD
Ground pin for LVTTL outputs and digital circuitry
55
VDD3
LVTTL O/P PWR
Power supply pin for LVTTL outputs and digital
circuitry
56
57
58
59
60
61
62
63
64
65
RXOE0
RXOE1
RXOE2
RXOE3
RXOE4
RXOE5
RXOE6
RXOD0
VSS4
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
GND
VDD
LVTTL O/P
LVTTL level data output
LVTTL O/P
LVTTL level data output
LVTTL O/P
LVTTL level data output
LVTTL O/P
LVTTL level data output
LVTTL O/P
LVTTL level data output
LVTTL O/P
LVTTL level data output
LVTTL O/P
LVTTL level data output
LVTTL O/P
LVTTL level data output
LVTTL O/P PWR
LVTTL O/P PWR
Ground pin for LVTTL outputs and digital circuitry
VDD4
Power supply pin for LVTTL outputs and digital
circuitry
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
RXOD1
RXOD2
RXOD3
RXOD4
RXOD5
RXOD6
RXOC0
RXOC1
RXOC2
RXOC3
RXOC4
RXOC5
RXOC6
RXOB0
RXOB1
RXOB2
RXOB3
RXOB4
RXOB5
RXOB6
VDDR2
VSSR2
RXOA0
RXOA1
RXOA2
RXOA3
RXOA4
RXOA5
RXOA6
VDD5
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
O/P
VDD
GND
O/P
O/P
O/P
O/P
O/P
O/P
O/P
VDD
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
RX LOGIC
RX LOGIC
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P
LVTTL O/P PWR
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
Power supply for logic
Ground pin for logic
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
LVTTL level data output
Power supply pin for LVTTL outputs and digital
circuitry
96
97
VSS5
GND
I/P
LVTTL O/P PWR
Ground pin for LVTTL outputs and digital circuitry
Tie to VSS for correct functionality
RESRVD
LVTTL I/P (pulldown)
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: DS90C3202
DS90C3202
SNLS191D –APRIL 2005–REVISED APRIL 2013
www.ti.com
DS90C3202 PIN DESCRIPTIONS (continued)
Pin No.
Pin Name
I/O
Pin Type
Digital (pulldown)
Description
98
MODE1
I/P
“ODD” Bank Enable
0 = LVTTL ODD OUTPUTS DISABLED
(Data Output Low)
1 = LVTTL ODD OUTPUTS ENABLED
99
VSSL
VDDL
GND
VDD
I/P
LVDS PWR
LVDS PWR
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS PWR
LVDS PWR
LVDS PWR
LVDS PWR
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
LVDS I/P
Digital (pulldown)
Ground pin for LVDS
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
Power supply pin for LVDS
RXOA-
RXOA+
RXOB-
RXOB+
RXOC-
RXOC+
RXOD-
RXOD+
RXOE-
RXOE+
VSSL
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Ground pin for LVDS
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
GND
GND
VDD
VDD
I/P
VSSL
Ground pin for LVDS
VDDL
Power supply pin for LVDS
VDDL
Power supply pin for LVDS
RCLKIN-
RCLKIN+
RXEA-
RXEA+
RXEB-
RXEB+
RXEC-
RXEC+
RXED-
RXED+
RXEE-
RXEE+
MODE0
Negative LVDS differential clock input
Positive LVDS differential clock input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
Negative LVDS differential data input
Positive LVDS differential data input
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
“EVEN” Bank Enable
0 = LVTTL EVEN OUTPUTS DISABLED
(Data Output Low)
1 = LVTTL EVEN OUTPUTS ENABLED
128
RFB
I/P
Digital (pulldown)
Rising Falling Bar (Figure 11)
0 = FALLING EDGE DATA STROBE
1 = RISING EDGE DATA STROBE
18
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C3202
DS90C3202
www.ti.com
SNLS191D –APRIL 2005–REVISED APRIL 2013
APPLICATION INFORMATION
Two-Wire Serial Communication Interface Description
The DS90C3202 operates as a slave on the Serial Bus, so the S2CLK line is an input (no clock is generated by
the DS90C3202) and the S2DAT line is bi-directional. DS90C3202 has a fixed 7bit slave address. The address is
not user configurable in anyway.
A zero in front of the register address is required. For example, to access register 0x0Fh, “0F” is the correct way
of accessing the register.
COMMUNICATING WITH THE DS90C3202 CONTROL REGISTERS
There are 32 data registers (one byte each) in the DS90C3202, and can be accessed through 32 addresses. All
registers are predefined as read only or read and write. The DS90C3202 slave state machine does not require
an internal clock and it supports only byte read and write. Page mode is not supported. The 7bit binary address
is 0111110 All seven bits are hardwired internally.
Reading the DS90C3202 can take place either of three ways:
1. If the location latched in the data register addresses is correct, then the read can simply consist of a slave
address byte, followed by retrieving the data byte.
2. If the data register address needs to be set, then a slave address byte, data register address will be sent
first, then the master will repeat start, send the slave address byte and data byte to accomplish a read.
3. When performing continuous read operations, another write (or read) instruction in between reads needs to
be completed in order for the two-wire serial interface module to read repeatedly.
The data byte has the most significant bit first. At the end of a read, the DS90C3202 can accept either
Acknowledge or No Acknowledge from the Master (No Acknowledge is typically used as a signal for the slave
that the Master has read its last byte).
AC
K
Bus Activity:
Master
Register
Address
Slave Address
Slave Address
A
2
A
1
A
0
A
2
A
1
A
0
S
P
SDA Line
S
0
1
AC
K
AC
K
AC
K
Data
Bus Activity:
DS90C3202
Figure 20. Byte Read
The master must generate a Start by sending the 7-bit slave address plus a 0 first, and wait for acknowledge
from DS90C3202. When DS90C3202 acknowledges (the 1st ACK) that the master is calling, the master then
sends the data register address byte and waits for acknowledge from the slave. When the slave acknowledges
(the 2nd ACK), the master repeats the “Start” by sending the 7-bit slave address plus a 1 (indicating that READ
operation is in progress) and waits for acknowledge from DS90C3202. After the slave responds (the 3rd ACK),
the slave sends the data to the bus and waits for acknowledge from the master. When the master acknowledges
(the 4th ACK), it generates a “Stop”. This completes the “ READ”.
A Write to the DS90C3202 will always include the slave address, data register address byte, and a data byte.
Bus Activity:
Master
Register
Address
Slave
Address
Data
A
2
A
1
A
0
SDA Line
P
S
0
AC
K
AC
K
AC
K
Bus Activity:
DS90C3202
Figure 21. Byte Write
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: DS90C3202
DS90C3202
SNLS191D –APRIL 2005–REVISED APRIL 2013
www.ti.com
The master must generate a “Start” by sending the 7-bit slave address plus a 0 and wait for acknowledge from
DS90C3202. When DS90C3202 acknowledges (the 1st ACK) that the master is calling, the master then sends
the data register address byte and waits for acknowledge from the slave. When the slave acknowledges (the 2nd
ACK), the master sends the data byte and wait for acknowledge from the slave. When the slave acknowledges
(the 3rd ACK), the master generates a “ Stop”. This completes the “WRITE”.
DS90C3202 Two-Wire Serial Interface Register Table
Address
0d/0h
1d/1h
2d/2h
3d/3h
4d/4h
5d/5h
6d/6h
R/W
R
RESET
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
PWDN
Bit #
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Description
Vender ID low byte[7:0] = 05h
Default Value
0000_0101
0001_0011
0010_1000
0110_0111
0000_0000
0000_1000
1000_0111
R
Vender ID high byte[15:8] =13h
Device ID low byte[7:0] = 28h
R
R
Device ID high byte 15:8] = 67h
Device revision [7:0] = 00h to begin with
Low frequency limit, 8Mhz = 8h
R
R
R
High frequency limit 135Mhz = 87h =
0000_0000_1000_0111
7d/7h
8d/8h
R
R
PWDN
PWDN
PWDN
PWDN
PWDN
None
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:3]
[2:0]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
9d/9h
R
10d/ah
11d/bh
20d/14h
21d/15h
22d/16h
R
R
R/W
R/W
R/W
None
None
LVDS input skew control for CLK channel,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Tsetup improvement
23d/17h
24d/18h
25d/19h
R/W
R/W
R/W
None
None
None
[7]
Reserved
0000_0000
0000_0000
0000_0000
[6:4]
LVDS input skew control for RXO channel B,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
[3]
Reserved
[2:0]
LVDS input skew control for RXO channel C,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
[7]
Reserved
[6:4]
LVDS input skew control for RXO channel D,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
[3]
Reserved
[2:0]
LVDS input skew control for RXO channel E,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
[7]
Reserved
[6:4]
LVDS input skew control for RXO channel A,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
[3]
Reserved
[2:0]
LVDS input skew control for RXE channel A,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
20
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C3202
DS90C3202
www.ti.com
SNLS191D –APRIL 2005–REVISED APRIL 2013
Address
R/W
RESET
Bit #
[7]
Description
Default Value
26d/1ah
R/W
None
Reserved
0000_0000
[6:4]
LVDS input skew control for RXE channel B,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
[3]
Reserved
[2:0]
LVDS input skew control for RXE channel C,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
27d/1bh
R/W
None
[7]
Reserved
0000_0000
[6:4]
LVDS input skew control for RXE channel D,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment
[3]
Reserved
[2:0]
LVDS input skew control for RXE channel E,
000 (default) applies to no delay added, ONE buffer delay
per step adjustment towards Thold improvements
28d/1ch
R/W
None
[7:3]
[2]
Reserved
0000_0000
LVTTL output transition time control for CLK
0: Tr/Tf = 1.0ns (default)
1: Tr/Tf = 1.5ns
[1]
[0]
LVTTL output transition time control for RXE
0: Tr/Tf = 1.5ns (default)
1: Tr/Tf = 2.5ns
LVTTL output transition time control for RXO
0: Tr/Tf = 1.5ns (default)
1: Tr/Tf = 2.5ns
29d/1dh
R/W
None
[7:3]
[2:1]
Reserved
0000_0000
LVTTL output setup and hold time control
00: balanced setup and hold time (default)
01: setup time is increased from default position by 1UI &
hold time is reduced from default position by 1UI
10: setup time is decreased from default position by 1UI &
hold time is reduced from default position by 1UI
11: setup time is increased from default position by 2UI &
hold time is increased from default position by 2UI
[0]
LVTTL output PTO control
1: PTO disabled, all outputs setup time are only controlled
by contents of [2:1]
0: PTO enabled (default)
Group1: CLK to latch Data is re-assigned earlier by 0.5UI
respect to the normal centered position if only PTO option
enabled; but PTO option and (Tsetup or Thold) adjustment
can co-exist
Group2: CLK to latch Data stays as the normal centered
position if only PTO option enabled; but PTO option and
(Tsetup or Thold) adjustment can co-exist
30d/1eh
R/W
None
[7:5]
[4]
Reserved
0000_0000
I/O disable control for RXE channel A,
1: disable, 0: enable (default)
[3]
[2]
[1]
[0]
I/O disable control for RXE channel B,
1: disable, 0: enable (default)
I/O disable control for RXE channel C,
1: disable, 0: enable (default)
I/O disable control for RXE channel D,
1: disable, 0: enable (default)
I/O disable control for RXE channel E,
1: disable, 0: enable (default)
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: DS90C3202
DS90C3202
SNLS191D –APRIL 2005–REVISED APRIL 2013
www.ti.com
Address
R/W
RESET
Bit #
Description
Default Value
31d/1fh
R/W
None
[7:6]
11; LVTTL Outputs available as long as "NO CLK" is at
HIGH regardless PLL lock or not
0000_0000
10; LVTTL Outputs available after 1K of CLK cycles
detected & PLL generated strobes are within 0.5UI respect
to REFCLK
01; LVTLL Outputs available after 2K of CLK cycles
detected
00: default ; LVTTL Outputs available after 1K of CLK cycles
detected
[5]
[4]
[3]
[2]
[1]
[0]
0: default; to select the size of wait counter between 1K or
2K, default is 1K
I/O disable control for RXO channel A,
1: disable, 0: enable (default)
I/O disable control for RXO channel B,
1 disable, 0: enable (default)
I/O disable control for RXO channel C,
1: disable, 0: enable (default)
I/O disable control for RXO channel D,
1: disable, 0: enable (default)
I/O disable control for RXO channel E,
1: disable, 0: enable (default)
22
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C3202
DS90C3202
www.ti.com
SNLS191D –APRIL 2005–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
Page
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: DS90C3202
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90C3202VS/NOPB
ACTIVE
TQFP
PDT
128
90
RoHS & Green
SN
Level-3-260C-168 HR
0 to 70
DS90C3202VS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DS90C3202VS/NOPB
PDT
TQFP
128
90
6 X 15
150
322.6 135.9 7620 20.3
15.4 15.45
Pack Materials-Page 1
MECHANICAL DATA
MPQF013 – NOVEMBER 1995
PDT (S-PQFP-G128)
PLASTIC QUAD FLATPACK
0,23
0,13
M
0,40
96
0,05
65
64
97
33
128
0,13 NOM
1
32
12,40 TYP
Gage Plane
14,05
SQ
13,95
0,25
16,10
SQ
0,05 MIN
15,90
0°–5°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4087726/A 11/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
相关型号：
DS90C363
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) LinkΑ65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) LinkΑ65 MHz
NSC
DS90C363A
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHz
NSC
DS90C363AMTD
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHz
NSC
DS90C363AMTDX
IC QUAD LINE DRIVER, PDSO48, LOW PROFILE, PLASTIC, TSSOP-48, Line Driver or Receiver
NSC
©2020 ICPDF网 联系我们和版权申明