DS90C402MX/NOPB [TI]
双路低电压差动信号接收器 | D | 8 | -40 to 85;
| 型号： | DS90C402MX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路低电压差动信号接收器 | D | 8 | -40 to 85 光电二极管 接口集成电路 |
| 文件： | 总17页 (文件大小：548K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90C402
www.ti.com
SNLS001C –JUNE 1998–REVISED APRIL 2013
DS90C402 Dual Low Voltage Differential Signaling (LVDS) Receiver
Check for Samples: DS90C402
1
FEATURES
DESCRIPTION
The DS90C402 is a dual receiver device optimized
for high data rate and low power applications. This
device along with the DS90C401 provides a pair chip
solution for a dual high speed point-to-point interface.
The device is in a PCB space saving 8 lead small
outline package. The receiver offers ±100 mV
threshold sensitivity, in addition to common-mode
noise protection.
2
•
•
•
•
•
•
Ultra Low Power Dissipation
Operates above 155.5 Mbps
Standard TIA/EIA-644
8 Lead SOIC Package saves PCB space
VCM ±1V center around 1.2V
±100 mV Receiver Sensitivity
Connection Diagram
See Package Number D (SOIC)
Functional Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2013, Texas Instruments Incorporated
DS90C402
SNLS001C –JUNE 1998–REVISED APRIL 2013
www.ti.com
Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC
Input Voltage (RIN+, RIN−
Output Voltage (ROUT
)
−0.3V to +6V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
1025 mW
)
)
D Package
Maximum Package Power Dissipation @ +25°C
Storage Temperature Range
Derate D Package
8.2 mW/°C above +25°C
−65°C to +150°C
Lead Temperature Range
Soldering (4 sec.)
+260°C
+150°C
≥ 3,500V
≥ 250V
Maximum Junction Temperature
ESD Rating(3)
(HBM, 1.5 kΩ, 100 pF)
(EIAJ, 0 Ω, 200 pF)
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) ESD Rating: HBM (1.5 kΩ, 100 pF) ≥ 3,500V EIAJ (0Ω, 200 pF) ≥ 250V
Recommended Operating Conditions
Min
+4.5
GND
−40
Typ
Max
+5.5
2.4
Units
V
Supply Voltage (VCC
)
+5.0
Receiver Input Voltage
V
Operating Free Air Temperature (TA)
+25
+85
°C
Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1)(2)
Symbol
VTH
Parameter
Differential Input High Threshold
Differential Input Low Threshold
Input Current
Conditions
Pin
Min
Typ
Max
Units
mV
mV
μA
µA
V
VCM = + 1.2V
RIN+
RIN−
,
+100
VTL
−100
−10
−10
3.8
IIN
VIN = +2.4V
VIN = 0V
VCC = 5.5V
±1
± 1
4.9
4.9
4.9
4.9
0.07
−60
3.5
+10
+10
VOH
Output High Voltage
IOH = −0.4 mA, VID = +200 mV
IOH = −0.4mA, Inputs terminated
IOH = −0.4mA, Inputs Open
IOH = −0.4mA, Inputs Shorted
IOL = 2 mA, VID = −200 mV
VOUT = 0V(3)
ROUT
3.8
V
3.8
V
V
VOL
IOS
ICC
Output Low Voltage
0.3
−100
10
V
Output Short Circuit Current
No Load Supply Current
−15
mA
mA
Inputs Open
VCC
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
unless otherwise specified.
(2) All typicals are given for: VCC = +5.0V, TA = +25°C.
(3) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted
at a time, do not exceed maximum junction temperature specification.
2
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Product Folder Links: DS90C402
DS90C402
www.ti.com
SNLS001C –JUNE 1998–REVISED APRIL 2013
Switching Characteristics
VCC = +5.0V ± 10%, TA = −40°C to +85°C(1)(2)(3)(4)(5)
Symbol
tPHLD
tPLHD
tSKD
Parameter
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Conditions
CL = 5 pF,
VID = 200 mV
Min
1.0
1.0
0
Typ
3.40
3.48
0.08
0.6
Max
6.0
6.0
1.2
1.5
5.0
2.5
2.5
Units
ns
ns
(Figure 1 and Figure 2)
Differential Skew |tPHLD − tPLHD
Channel-to-Channel Skew(3)
Chip to Chip Skew(4)
Rise Time
|
ns
tSK1
0
ns
tSK2
ns
tTLH
0.5
0.5
ns
tTHL
Fall Time
ns
(1) All typicals are given for: VCC = +5.0V, TA = +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0%–100%) ≤ 1 ns for RIN
.
(3) Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same
chip with an event on the inputs.
(4) Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
(5) CL includes probe and jig capacitance.
Parameter Measurement Information
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
Copyright © 1998–2013, Texas Instruments Incorporated
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3
Product Folder Links: DS90C402
DS90C402
SNLS001C –JUNE 1998–REVISED APRIL 2013
www.ti.com
TYPICAL APPLICATION
Figure 3. Point-to-Point Application
Applications Information
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 3. This configuration provides a clean signaling environment for the quick edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the
range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to
the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a
voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration,
but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination loading must be taken into account.
The DS90C402 differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V common-
mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The
driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be
the result of a ground potential difference between the driver's ground reference and the receiver's ground
reference, the common-mode effects of coupled noise, or a combination of the two. Both receiver input pins
should honor their specified operating input voltage range of 0V to +2.4V (measured from each pin to ground),
exceeding these limits may turn on the ESD protection circuitry which will clamp the bus voltages.
Fail-Safe Feature:
The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS
logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from
appearing as a valid signal.
The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe
protection (a stable known state HIGH output voltage) for floating, terminated or shorted receiver inputs.
1. Open Input Pins. The DS90C402 is a dual receiver device, and if an application requires only one receiver,
the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other
voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a
HIGH state. This internal circuitry will ensure a HIGH, stable output state for open inputs.
2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a power-off condition,
the receiver output will again be in a HIGH state, even with the end of cable 100Ω termination resistor across
the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable
picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch.
To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be
used. Twisted pair cable will offer better balance than flat ribbon cable
3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V
differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not
supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs
shorted and no external common-mode voltage applied.
4
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Product Folder Links: DS90C402
DS90C402
www.ti.com
SNLS001C –JUNE 1998–REVISED APRIL 2013
PIN DESCRIPTIONS
Pin No.
Name
Description
2, 6
3, 7
4, 8
5
ROUT
Receiver output pin
RIN+
Positive receiver input pin
Negative receiver input pin
Ground pin
RIN
-
GND
VCC
1
Positive power supply pin, +5V ± 10%
Copyright © 1998–2013, Texas Instruments Incorporated
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5
Product Folder Links: DS90C402
DS90C402
SNLS001C –JUNE 1998–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics
Output High Voltage vs
Power Supply Voltage
Output High Voltage vs
Ambient Temperature
Figure 4.
Figure 5.
Output Low Voltage vs
Power Supply Voltage
Output Low Voltage vs
Ambient Temperature
Figure 6.
Figure 7.
Output Short Circuit Current
vs Power Supply Voltage
Output Short Circuit Current
vs Ambient Temperature
Figure 8.
Figure 9.
6
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Product Folder Links: DS90C402
DS90C402
www.ti.com
SNLS001C –JUNE 1998–REVISED APRIL 2013
Typical Performance Characteristics (continued)
Differential Propagation Delay
vs
Power Supply Voltage
Differential Propagation Delay
vs Ambient Temperature
Figure 10.
Figure 11.
Differential Skew vs
Power Supply Voltage
Differential Skew vs
Ambient Temperature
Figure 12.
Figure 13.
Transition Time vs
Power Supply Voltage
Transition Time vs
Ambient Temperature
Figure 14.
Figure 15.
Copyright © 1998–2013, Texas Instruments Incorporated
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7
Product Folder Links: DS90C402
DS90C402
SNLS001C –JUNE 1998–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 7
8
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Copyright © 1998–2013, Texas Instruments Incorporated
Product Folder Links: DS90C402
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90C402M
NRND
SOIC
SOIC
SOIC
D
D
D
8
8
8
95
Non-RoHS
& Green
Call TI
Level-1-235C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
DS90C
402M
DS90C402M/NOPB
DS90C402MX/NOPB
ACTIVE
ACTIVE
95
RoHS & Green
SN
SN
DS90C
402M
2500 RoHS & Green
DS90C
402M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90C402MX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
DS90C402MX/NOPB
D
8
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DS90C402M
DS90C402M
D
D
D
SOIC
SOIC
SOIC
8
8
8
95
95
95
495
495
495
8
8
8
4064
4064
4064
3.05
3.05
3.05
DS90C402M/NOPB
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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