DS90CF366MTDX/NOPB [TI]
+3.3V LVDS 接收器 18 位平板显示器 (FPD) 链路 - 85MHz | DGG | 48 | -10 to 70;
| 型号： | DS90CF366MTDX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | +3.3V LVDS 接收器 18 位平板显示器 (FPD) 链路 - 85MHz | DGG | 48 | -10 to 70 驱动 光电二极管 接口集成电路 线路驱动器或接收器 显示器 驱动程序和接口 |
| 文件： | 总20页 (文件大小：1154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90CF366, DS90CF386
www.ti.com
SNLS055I –NOVEMBER 1999–REVISED APRIL 2013
DS90CF386/DS90CF366 +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 85
MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 85 MHz
Check for Samples: DS90CF366, DS90CF386
1
FEATURES
DESCRIPTION
The DS90CF386 receiver converts the four LVDS
data streams (Up to 2.38 Gbps throughput or 297.5
Megabytes/sec bandwidth) back into parallel 28 bits
of CMOS/TTL data (24 bits of RGB and 4 bits of
Hsync, Vsync, DE and CNTL). Also available is the
DS90CF366 that converts the three LVDS data
streams (Up to 1.78 Gbps throughput or 223
Megabytes/sec bandwidth) back into parallel 21 bits
of CMOS/TTL data (18 bits of RGB and 3 bits of
Hsync, Vsync and DE). Both Receivers' outputs are
Falling edge strobe. A Rising edge or Falling edge
strobe transmitter (DS90C385/DS90C365) will
interoperate with a Falling edge strobe Receiver
without any translation logic.
•
•
20 to 85 MHz Shift Clock Support
Rx Power Consumption <142 mW (typ)
@85MHz Grayscale
•
•
•
Rx Power-Down Mode <1.44 mW (max)
ESD Rating >7 kV (HBM), >700V (EIAJ)
Supports VGA, SVGA, XGA and Single Pixel
SXGA.
•
•
•
PLL Requires No External Components
Compatible with TIA/EIA-644 LVDS Standard
Low Profile 56-Lead or 48-lead TSSOP
Package
•
DS90CF386 Also Available in a 64 Ball, 0.8mm
Fine Pitch Ball Grid Array (NFBGA) Package
The DS90CF386 is also offered in a 64 ball, 0.8mm
fine pitch ball grid array (NFBGA) package which
provides a 44 % reduction in PCB footprint compared
to the 56L TSSOP package.
This chipset is an ideal means to solve EMI and
cable size problems associated with wide, high speed
TTL interfaces.
BLOCK DIAGRAM
Figure 1. DS90CF386
Figure 2. DS90CF366
See Package Number DGG-48 (TSSOP)
See Package Number DGG-56 (TSSOP) or
NZC0064A-64 (NFBGA)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
DS90CF366, DS90CF386
SNLS055I –NOVEMBER 1999–REVISED APRIL 2013
www.ti.com
Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
+150°C
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
Junction Temperature
Storage Temperature
−65°C to +150°C
+260°C
Lead Temperature(Soldering, 4 sec for TSSOP)
Solder Reflow Temperature (Soldering, 20 sec for NFBGA)
+220°C
DGG0056A (TSSOP) Package
DS90CF386MTD
DS90CF366MTD
DS90CF386MTD
DS90CF366MTD
DS90CF386SLC
1.61 W
Maximum Package Power Dissipation
Capacity @ 25°C
DGG0048A (TSSOP) Package
1.89 W
12.4 mW/°C above +25°C
15 mW/°C above +25°C
Package Derating
Maximum Package Power Dissipation
Capacity @ 25°C
NZC0064A Package
2.0 W
10.2 mW/°C above +25°C
> 7 kV
Package Derating
DS90CF386SLC
(HBM, 1.5 kΩ, 100 pF)
(EIAJ, 0Ω, 200 pF)
ESD Rating
> 700V
(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(2) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Recommended Operating Conditions
Min
3.0
−10
0
Nom
3.3
Max
3.6
Units
V
Supply Voltage (VCC
)
Operating Free Air Temperature (TA)
Receiver Input Range
+25
+70
2.4
°C
V
Supply Noise Voltage (VCC
)
100
mVPP
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Clamp Voltage
Input Current
2.0
GND
2.7
VCC
0.8
V
V
VOH
VOL
VCL
IIN
IOH = - 0.4 mA
IOL = 2 mA
3.3
V
0.06
0.3
V
ICL = −18 mA
-0.79 -1.5
V
VIN = 0.4V, 2.5V or VCC
VIN = GND
+1.8
0
+15
-120
+100
uA
uA
mA
-10
IOS
Output Short Circuit Current
VOUT = 0V
-60
LVDS RECEIVER DC SPECIFICATIONS
VTH
VTL
I IN
Differential Input High Threshold
Differential Input Low Threshold
Input Current
V CM = +1.2V
mV
mV
μA
−100
V IN = +2.4V, VCC = 3.6V
V IN = 0V, VCC = 3.6V
±10
±10
μA
(1) Typical values are given for VCC = 3.3V and TA = +25C.
2
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SNLS055I –NOVEMBER 1999–REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RECEIVER SUPPLY CURRENT
ICCRW
ICCRW
ICCRG
ICCRZ
Receiver Supply Current Worst Case
CL = 8 pF, Worst Case
Pattern,
DS90CF386 Figure 3,
Figure 6
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
f = 85 MHz
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
f = 85 MHz
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
f = 85 MHz
49
53
81
96
49
53
78
90
28
30
43
43
140
70
75
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
114
135
60
Receiver Supply Current Worst Case
Receiver Supply Current, 16 Grayscale
Receiver Supply Current Power Down(2)
CL = 8 pF, Worst Case
Pattern,
DS90CF366 Figure 3,
Figure 6
65
100
115
45
CL = 8 pF, 16 Grayscale
Pattern, Figure 4, Figure 5,
Figure 6
47
60
70
Power Down = Low Receiver Outputs Stay Low
during Power Down Mode
400
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VOD and ΔV OD).
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified(1)
Symbol
CLHT
Parameter
CMOS/TTL Low-to-High Transition Time Figure 6
CMOS/TTL High-to-Low Transition Time Figure 6
Min
Typ(1)
2.0
Max
3.5
Units
ns
CHLT
1.8
3.5
ns
RSPos0
Receiver Input Strobe Position for Bit 0 Figure 13,
Figure 14
f = 85 MHz
0.49
0.84
1.19
ns
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin(2) Figure 15
2.17
3.85
5.53
7.21
8.89
10.57
290
11.76
4.5
2.52
4.20
5.88
7.56
9.24
10.92
2.87
4.55
6.23
7.91
9.59
11.27
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ms
μs
f = 85 MHz
f = 85 MHz
RCOP
RxCLK OUT Period Figure 7
T
5
5
50
7
RCOH
RCOL
RxCLK OUT High Time Figure 7
RxCLK OUT Low Time Figure 7
4.0
6.5
RSRC
RxOUT Setup to RxCLK OUT Figure 7
RxOUT Hold to RxCLK OUT Figure 7
2.0
RHRC
3.5
RCCD
RxCLK IN to RxCLK OUT Delay @ 25°C, VCC = 3.3V Figure 8
Receiver Phase Lock Loop Set Figure 9
5.5
7.0
9.5
10
1
RPLLS
RPDD
Receiver Power Down Delay Figure 12
(1) Typical values are given for VCC = 3.3V and TA = +25C.
(2) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows
for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 150 ps).
Copyright © 1999–2013, Texas Instruments Incorporated
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SNLS055I –NOVEMBER 1999–REVISED APRIL 2013
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AC Timing Diagrams
Figure 3. “Worst Case” Test Pattern
(1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
(2) The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
(3) Figure 3 and Figure 5 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
(4) Recommended pin to signal mapping. Customer may choose to define differently.
Figure 4. “16 Grayscale” Test Pattern (DS90CF386)
4
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SNLS055I –NOVEMBER 1999–REVISED APRIL 2013
Device Pin Name
Signal
Signal Pattern
Signal Frequency
TxCLK IN / RxCLK OUT
TxIN0 / RxOUT0
TxIN1 / RxOUT1
TxIN2 / RxOUT2
TxIN3 / RxOUT3
TxIN4 / RxOUT4
TxIN5 / RxOUT5
TxIN6 / RxOUT6
TxIN7 / RxOUT7
TxIN8 / RxOUT8
TxIN9 / RxOUT9
TxIN10 / RxOUT10
TxIN11 / RxOUT11
TxIN12 / RxOUT12
TxIN13 / RxOUT13
TxIN14 / RxOUT14
TxIN15 / RxOUT15
TxIN16 / RxOUT16
TxIN17 / RxOUT17
TxIN18 / RxOUT18
TxIN19 / RxOUT19
TxIN20 / RxOUT20
Dot Clk
R0
f
f / 16
R1
f / 8
R2
f / 4
R3
f / 2
R4
Steady State, Low
Steady State, Low
f / 16
R5
G0
G1
f / 8
G2
f / 4
G3
f / 2
G4
Steady State, Low
Steady State, Low
f / 16
G5
B0
B1
f / 8
B2
f / 4
B3
f / 2
B4
Steady State, Low
Steady State, Low
Steady State, High
Steady State, High
Steady State, High
B5
HSYNC
VSYNC
ENA
(1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
(2) The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
(3) Figure 3 and Figure 5 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
(4) Recommended pin to signal mapping. Customer may choose to define differently.
Figure 5. “16 Grayscale” Test Pattern (DS90CF366)
Figure 6. DS90CF386/DS90CF366 (Receiver) CMOS/TTL Output Load and Transition Times
Figure 7. DS90CF386/DS90CF366 (Receiver) Setup/Hold and High/Low Times
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Figure 8. DS90CF386/DS90CF366 (Receiver) Clock In to Clock Out Delay
Figure 9. DS90CF386/DS90CF366 (Receiver) Phase Lock Loop Set Time
Figure 10. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF386
Figure 11. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF366
6
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SNLS055I –NOVEMBER 1999–REVISED APRIL 2013
Figure 12. DS90CF386/DS90CF366 (Receiver) Power Down Delay
Figure 13. DS90CF386 (Receiver) LVDS Input Strobe Position
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Figure 14. DS90CF366 (Receiver) LVDS Input Strobe Position
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(1) + ISI (Inter-symbol interference)(2)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
(1) Cycle-to-cycle jitter is less than 250 ps at 85 MHz.
(2) ISI is dependent on interconnect length; may be zero.
Figure 15. Receiver LVDS Input Skew Margin
8
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SNLS055I –NOVEMBER 1999–REVISED APRIL 2013
DS90CF386 DGG0056A Package PIN DESCRIPTIONS—24-Bit FPD Link Receiver
Pin Name
I/O No.
Description
RxIN+
RxIN−
RxOUT
I
I
4
4
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
O
28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V CC
I
I
1
1
1
1
4
5
1
2
1
3
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
O
I
I
GND
I
PLL V CC
PLL GND
LVDS V CC
LVDS GND
I
Power supply for PLL.
I
Ground pin for PLL.
I
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
I
DS90CF366 DGG0048A Package PIN DESCRIPTIONS—18-Bit FPD Link Receiver
Pin Name
RxIN+
I/O No.
Description
I
I
3
3
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
RxIN−
RxOUT
O
21 TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V CC
I
I
1
1
1
1
4
5
1
2
1
3
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
O
I
I
GND
I
PLL V CC
PLL GND
LVDS V CC
LVDS GND
I
Power supply for PLL.
I
Ground pin for PLL.
I
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
I
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DS90CF386 — 64 ball NFBGA package PIN DESCRIPTIONS — FPD Link Receiver
Pin Name
RxIN+
I/O No.
Description
I
I
4
4
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
RxIN−
RxOUT
O
28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+
RxCLK IN−
FPSHIFT OUT
PWR DOWN
VCC
I
I
1
1
1
1
4
5
1
2
1
3
6
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
O
I
I
GND
I
PLL VCC
PLL GND
LVDS VCC
LVDS GND
NC
I
Power supply for PLL.
I
Ground pin for PLL.
I
Power supply pin for LVDS inputs.
I
Ground pins for LVDS inputs.
Pins not connected.
DS90CF386 Pin Descriptions — 64 ball NFBGA Package — FPD Link Receiver
By Pin
Pin Name
RxOUT17
VCC
By Pin Type
Pin Name
GND
Pin
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
C1
C2
C3
C4
C5
C6
C7
C8
D1
D2
D3
D4
D5
Type
O
Pin
A4
B1
B6
D8
E3
E5
G3
G7
H5
F6
G8
E6
H6
H7
H2
H3
F4
G4
G5
F5
G6
H8
E7
E8
C8
D5
B4
A5
D4
Type
G
G
G
G
G
G
G
G
G
G
G
I
P
GND
RxOUT15
GND
O
GND
G
GND
RxOUT12
RxOUT8
RxOUT7
RxOUT6
GND
O
GND
O
LVDS GND
LVDS GND
LVDS GND
LVDS GND
PLL GND
PLL GND
PWR DWN
RxCLKIN-
RxCLKIN+
RxIN0-
O
O
G
NC
RxOUT16
RxOUT11
VCC
O
O
P
I
GND
G
O
O
O
I
RxOUT5
RxOUT3
RxOUT21
NC
I
RxIN0+
I
RxIN1-
I
RxIN1+
I
RxOUT18
RxOUT14
RxOUT9
RxOUT4
NC
O
O
O
O
RxIN2-
I
RxIN2+
I
RxIN3-
I
RxIN3+
I
RxCLKOUT
RxOUT0
RxOUT1
RxOUT10
RxOUT11
RxOUT12
RxOUT13
O
O
O
O
O
O
O
RxOUT1
VCC
O
P
RxOUT20
RxOUT19
RxOUT13
RxOUT10
O
O
O
O
10
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SNLS055I –NOVEMBER 1999–REVISED APRIL 2013
DS90CF386 Pin Descriptions — 64 ball NFBGA Package — FPD Link Receiver (continued)
By Pin
VCC
By Pin Type
RxOUT14
RxOUT15
RxOUT16
RxOUT17
RxOUT18
RxOUT19
RxOUT2
RxOUT20
RxOUT21
RxOUT22
RxOUT23
RxOUT24
RxOUT25
RxOUT26
RxOUT27
RxOUT3
RxOUT4
RxOUT5
RxOUT6
RxOUT7
RxOUT8
RxOUT9
LVDS VCC
LVDS VCC
PLL VCC
VCC
D6
D7
D8
E1
E2
E3
E4
E5
E6
E7
E8
F1
F2
F3
F4
F5
F6
F7
F8
G1
G2
G3
G4
G5
G6
G7
G8
H1
H2
H3
H4
H5
H6
H7
H8
P
O
G
O
O
G
P
G
I
C4
A3
B3
A1
C3
D3
D7
D2
C1
E1
F1
E2
G1
F2
H1
B8
C6
B7
A8
A7
A6
C5
E4
H4
F7
A2
B5
D1
D6
B2
C2
C7
F3
F8
G2
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
P
RxOUT2
GND
RxOUT22
RxOUT24
GND
LVDS VCC
LVDS GND
PWR DWN
RxCLKOUT
RxOUT0
RxOUT23
RxOUT26
NC
O
O
O
O
RxIN1-
I
I
RxIN2+
PLL GND
PLL VCC
NC
G
P
RxOUT25
NC
O
LVDS GND
RxIN1+
G
I
RxIN2-
I
P
RxIN3-
I
P
LVDS GND
PLL GND
RxOUT27
RxIN0-
G
G
O
I
P
VCC
P
VCC
P
VCC
P
RxIN0+
I
NC
LVDS VCC
LVDS GND
RxCLKIN-
RxCLKIN+
RxIN3+
P
G
I
NC
NC
NC
I
NC
I
NC
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Pin Diagrams for TSSOP Packages
Figure 16. DS90CF386MTD
Figure 17. DS90CF366MTD
APPLICATIONS INFORMATION
POWER SEQUENCING AND POWERDOWN MODE
Outputs of the transmitter remain in TRI-STATE until the power supply reaches 2V. Clock and data outputs will
begin to toggle 10 ms after VCC has reached 3V and the Powerdown pin is above 1.5V. Either device may be
placed into a powerdown mode at any time by asserting the Powerdown pin (active low). Total power dissipation
for each device will decrease to 5 μW (typical).
The transmitter input clock may be applied prior to powering up and enabling the transmitter. The transmitter
input clock may also be applied after power up; however, the use of the PWR DOWN pin is required. Do not
power up and enable (PWR DOWN = HIGH) the transmitter without a valid clock signal applied to the TxCLK IN
pin.
The FPD Link chipset is designed to protect itself from accidental loss of power to either the transmitter or
receiver. If power to the transmit board is lost, the receiver clocks (input and output) stop. The data outputs
(RxOUT) retain the states they were in when the clocks stopped. When the receiver board loses power, the
receiver inputs are controlled by a failsafe bias circuitry. The LVDS inputs are High-Z during initial power on and
power off conditions. Current is limited (5 mA per input) by the fixed current mode drivers, thus avoiding the
potential for latchup when powering the device.
12
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90CF366 DS90CF386
DS90CF366, DS90CF386
www.ti.com
SNLS055I –NOVEMBER 1999–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision H (April 2013) to Revision I
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 12
Copyright © 1999–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: DS90CF366 DS90CF386
PACKAGE OPTION ADDENDUM
www.ti.com
21-Apr-2013
PACKAGING INFORMATION
Orderable Device
DS90CF366MTD/NOPB
DS90CF366MTDX/NOPB
DS90CF386MTD
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-10 to 70
-10 to 70
-10 to 70
-10 to 70
-10 to 70
-10 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
NFBGA
DGG
48
48
56
56
56
64
38
Green (RoHS
& no Sb/Br)
CU SN
CU SN
Call TI
CU SN
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
DS90CF366MTD
>B
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DGG
DGG
DGG
DGG
NZC
1000
34
Green (RoHS
& no Sb/Br)
DS90CF366MTD
>B
TBD
DS90CF386MTD
>B
DS90CF386MTD/NOPB
DS90CF386MTDX/NOPB
DS90CF386SLC/NOPB
34
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-4-260C-72 HR
DS90CF386MTD
>B
1000
360
Green (RoHS
& no Sb/Br)
DS90CF386MTD
>B
Green (RoHS POST-PLATE
& no Sb/Br)
DS90CF386
SLC
>B
DS90CF386SLCX/NOPB
ACTIVE
NFBGA
NZC
64
2000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-4-260C-72 HR
-10 to 70
DS90CF386
SLC
>B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Apr-2013
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90CF366MTDX/NOPB TSSOP
DS90CF386MTDX/NOPB TSSOP
DS90CF386SLCX/NOPB NFBGA
DGG
DGG
NZC
48
56
64
1000
1000
2000
330.0
330.0
330.0
24.4
24.4
16.4
8.6
8.6
8.3
13.2
14.5
8.3
1.6
1.8
2.3
12.0
12.0
12.0
24.0
24.0
16.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90CF366MTDX/NOPB
DS90CF386MTDX/NOPB
DS90CF386SLCX/NOPB
TSSOP
TSSOP
NFBGA
DGG
DGG
NZC
48
56
64
1000
1000
2000
367.0
367.0
367.0
367.0
367.0
367.0
45.0
45.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
NZC0064A
SLC64A (Rev C)
www.ti.com
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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