DS90CF564MTDX/NOPB [TI]
LVDS 18 位色彩平板显示 (FPD) 链接 - 65 MHz | DGG | 48 | -10 to 70;
| 型号： | DS90CF564MTDX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LVDS 18 位色彩平板显示 (FPD) 链接 - 65 MHz | DGG | 48 | -10 to 70 光电二极管 接口集成电路 |
| 文件： | 总22页 (文件大小：963K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90CF563, DS90CF564
www.ti.com
SNLS107E –JULY 1997–REVISED APRIL 2013
DS90CF563/DS90CF564 LVDS 18-Bit Color Flat Panel Display (FPD) Link - 65 MHz
Check for Samples: DS90CF563, DS90CF564
1
FEATURES
DESCRIPTION
The DS90CF563 transmitter converts 21 bits of
CMOS/TTL data into three LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a fourth LVDS link. Every cycle of the
transmit clock 21 bits of input data are sampled and
transmitted. The DS90CF564 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL
data. At a transmit clock frequency of 65 MHz, 18 bits
of RGB data and 3 bits of LCD timing and control
data (FPLINE, FPFRAME, DRDY) are transmitted at
a rate of 455 Mbps per LVDS data channel. Using a
65 MHz clock, the data throughput is 171 Mbytes per
second. These devices are offered with falling edge
data strobes for convenient interface with a variety of
graphics and LCD panel controllers.
2
•
20 to 65 MHz Shift Clk Support
•
•
•
•
•
•
•
•
•
•
•
•
Up to 171 Mbytes/s Bandwidth
Cable Size is Reduced to Save Cost
290 mV Swing LVDS Devices for Low EMI
Low Power CMOS Design (< 550 mW typ)
Power-down Mode Saves Power (< 0.25 mW)
PLL Requires No External Components
Low Profile 48-Lead TSSOP Package
Falling Edge Data Strobe
Compatible with TIA/EIA-644 LVDS Standard
Single Pixel Per Clock XGA (1024 x 768)
Supports VGA, SVGA, XGA and Higher
1.3 Gbps Throughput
This chipset is an ideal means to solve EMI and
cable size problems associated with wide, high speed
TTL interfaces.
Block Diagram
Figure 1. DS90CF563
DS90CF563MTD is no longer available.
Figure 2. DS90CF564
See Package Number DGG0048A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2013, Texas Instruments Incorporated
DS90CF563, DS90CF564
SNLS107E –JULY 1997–REVISED APRIL 2013
www.ti.com
Application
Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC
)
−0.3V to +6V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
Continuous
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Duration
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
+260°C
Lead Temperature (Soldering, 4 sec)
Maximum Package Power Dissipation @ +25°C DGG0048A (TSSOP)
Package:
DS90CF563
DS90CF564
DS90CF563
DS90CF564
1.98W
1.89W
Package Derating:
16 mW/°C above +25°C
15 mW/°C above +25°C
(3)
This device does not meet 2000V ESD rating
.
(1) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(2) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be verified. They are not meant to imply
that the device should be operated at these limits. The “Electrical Characteristics” specify conditions for device operation.
(3) ESD Rating: HBM (1.5 kΩ, 100 pF) PLL V CC ≥ 1000V All other pins ≥ 2000V EIAJ (0Ω, 200 pF) ≥ 150V
Recommended Operating Conditions
Min
4.75
−10
0
Nom
5.0
Max
5.25
+70
2.4
Units
V
Supply Voltage (VCC
)
Operating Free Air Temperature (TA)
Receiver Input Range
+25
°C
V
Supply Noise Voltage (VCC
)
100
mVP-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min Typ Max Units
CMOS/TTL DC SPECIFICATIONS
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
2.0
GND
3.8
VCC
0.8
V
V
V
V
VOH
VOL
IOH = −0.4 mA
4.9
0.1
IOL = 2 mA
0.3
2
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Copyright © 1997–2013, Texas Instruments Incorporated
Product Folder Links: DS90CF563 DS90CF564
DS90CF563, DS90CF564
www.ti.com
SNLS107E –JULY 1997–REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Input Clamp Voltage
Conditions
Min Typ Max Units
VCL
ICL = −18 mA
−0.7 −1.5
V
9
IIN
Input Current
VIN = VCC, GND, 2.5V or 0.4V
VOUT = 0V
±5.1 ±10
μA
IOS
Output Short Circuit Current
−120
mA
LVDS DRIVER DC SPECIFICATIONS
VOD
Differential Output Voltage
R L = 100Ω
250
1.1
290
450
35
mV
mV
V
ΔVOD
Change in VOD between
Complementary Output States
VCM
Common Mode Voltage
1.25 1.37
5
ΔVCM
Change in VCM between
Complementary Output States
35
mV
VOH
VOL
IOS
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
Output TRI-STATE Current
1.3
1.01
−2.9
±1
1.6
V
V
0.9
VOUT = 0V, RL = 100Ω
−5
mA
μA
IOZ
Power Down = 0V, VOUT = 0V or VCC
±10
LVDS RECEIVER DC SPECIFICATIONS
VTH
VTL
IIN
Differential Input High Threshold
Differential Input Low Threshold
Input Current
V CM = +1.2V
+100
mV
mV
μA
−100
VIN = +2.4V
VIN = 0V
VCC = 5.5V
±10
±10
μA
TRANSMITTER SUPPLY CURRENT
ICCTW
Transmitter Supply Current,
Worst Case
RL = 100Ω, CL = 5 pF,
Worst Case Pattern
(Figure 3, Figure 5)
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
49
51
70
40
41
55
63
64
84
55
55
67
mA
mA
mA
mA
mA
mA
ICCTG
Transmitter Supply Current,
16 Grayscale
RL = 100Ω, CL = 5 pF,
16 Grayscale Pattern
(Figure 4, Figure 5)
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
ICCTZ
Transmitter Supply Current,
Power Down
Power Down = Low
1
25
μA
RECEIVER SUPPLY CURRENT
ICCRW
ICCRG
ICCRZ
Receiver Supply Current,
Worst Case
CL = 8 pF,
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
64
70
110
35
37
55
1
77
85
mA
mA
mA
mA
mA
mA
μA
Worst Case Pattern
(Figure 3, Figure 6)
CL = 8 pF,
140
55
Receiver Supply Current,
16 Grayscale
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
16 Grayscale Pattern
(Figure 4, Figure 6)
Power Down = Low
55
67
Receiver Supply Current,
Power Down
10
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
Parameter
LVDS Low-to-High Transition Time (Figure 5)
LVDS High-to-Low Transition Time (Figure 5)
TxCLK IN Transition Time (Figure 7)
Min
Typ
Max
Units
ns
0.75
0.75
1.5
1.5
8
LHLT
TCIT
ns
ns
TCCS
TxOUT Channel-to-Channel Skew (1) (Figure 8)
350
ps
(1) This limit based on bench characterization.
Copyright © 1997–2013, Texas Instruments Incorporated
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www.ti.com
Transmitter Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
TxCLK IN to TxCLK OUT Delay @ 25°C, VCC = 5.0V
(Figure 11)
Min
Typ
Max
Units
TCCD
3.5
8.5
ns
TCIP
TxCLK IN Period (Figure 9)
15
0.35T
0.35T
5
T
50
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
TCIH
TxCLK IN High Time (Figure 9)
0.5T
0.5T
3.5
0.65T
0.65T
TCIL
TxCLK IN Low Time (Figure 9)
TSTC
TxIN Setup to TxCLK IN (Figure 9 )
TxIN Hold to TxCLK IN (Figure 9)
Transmitter Powerdown Delay (Figure 20)
Transmitter Phase Lock Loop Set (Figure 13)
Transmitter Output Pulse Position 0 (Figure 15)
Transmitter Output Pulse Position 1
Transmitter Output Pulse Position 2
Transmitter Output Pulse Position 3
Transmitter Output Pulse Position 4
Transmitter Output Pulse Position 5
Transmitter Output Pulse Position 6
f = 65 MHz
THTC
2.5
1.5
TPDD
100
10
TPLLS
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
−0.30
1.70
0
0.30
2.50
4.50
6.75
9.00
11.10
13.40
1/7 Tclk
2/7 Tclk
3/7 Tclk
4/7 Tclk
5/7 Tclk
6/7 Tclk
3.60
5.90
8.30
10.40
12.70
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
CLHT
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 6)
CMOS/TTL High-to-Low Transition Time (Figure 6)
RxCLK OUT Period
Min
Typ
2.5
2.0
T
Max
Units
ns
4.0
3.5
50
CHLT
ns
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
15
7.8
3.8
2.5
4.0
6.4
ns
RxCLK OUT High Time
f = 65 MHz
f = 65 MHz
f = 65 MHz
f = 65 MHz
9
ns
RxCLK OUT Low Time
5
ns
RxOUT Setup to RxCLK OUT
4.2
5.2
ns
RxOUT Hold to RxCLK OUT
ns
RxCLK IN to RxCLK OUT Delay @ 25°C, VCC = 5.0V
(Figure 12)
10.7
10
1
ns
RPLLS
RSKM
RPDD
Receiver Phase Lock Loop Set (Figure 14)
RxIN Skew Margin (1) (Figure 16)
Receiver Powerdown (Figure 19)
ms
ps
μs
VCC = 5V, TA =25°C
600
(1) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter
output skew (TCCS) and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on
type/length and source clock (TxCLK IN) jitter.
RSKM ≥ cable skew (the, length) + source clock jitter (cycle to cycle)
4
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Product Folder Links: DS90CF563 DS90CF564
DS90CF563, DS90CF564
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SNLS107E –JULY 1997–REVISED APRIL 2013
AC Timing Diagrams
Figure 3. “Worst Case” Test Pattern
Device Pin Name
Signal
Signal Pattern
Signal Frequency
TxCLK IN / RxCLK OUT
TxIN0 / RxOUT0
TxIN1 / RxOUT1
TxIN2 / RxOUT2
TxIN3 / RxOUT3
TxIN4 / RxOUT4
TxIN5 / RxOUT5
TxIN6 / RxOUT6
TxIN7 / RxOUT7
TxIN8 / RxOUT8
TxIN9 / RxOUT9
TxIN10 / RxOUT10
TxIN11 / RxOUT11
TxIN12 / RxOUT12
TxIN13 / RxOUT13
TxIN14 / RxOUT14
TxIN15 / RxOUT15
TxIN16 / RxOUT16
TxIN17 / RxOUT17
TxIN18 / RxOUT18
TxIN19 / RxOUT19
TxIN20 / RxOUT20
Dot Clk
R0
f
f / 16
R1
f / 8
R2
f / 4
R3
f / 2
R4
Steady State, Low
Steady State, Low
f / 16
R5
G0
G1
f / 8
G2
f / 4
G3
f / 2
G4
Steady State, Low
Steady State, Low
f / 16
G5
B0
B1
f / 8
B2
f / 4
B3
f / 2
B4
Steady State, Low
Steady State, Low
Steady State, High
Steady State, High
Steady State, High
B5
HSYNC
VSYNC
ENA
(1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
(2) The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
(3) Figure 3 and Figure 4 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
(4) Recommended pin to signal mapping. Customer may choose to define differently.
Figure 4. “16 Grayscale” Test Pattern
Copyright © 1997–2013, Texas Instruments Incorporated
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Product Folder Links: DS90CF563 DS90CF564
DS90CF563, DS90CF564
SNLS107E –JULY 1997–REVISED APRIL 2013
www.ti.com
Figure 5. DS90CF563 (Transmitter) LVDS Output Load and Transition Times
Figure 6. DS90CF564 (Receiver) CMOS/TTL Output Load and Transition Times
Figure 7. DS90CF563 (Transmitter) Input Clock Transition Time
Note: Measurements at Vdiff = 0V
Note: TCSS measured between earliest and latest LVDS edges.
Note: TxCLK Differential High→Low Edge
Figure 8. DS90CF563 (Transmitter) Channel-to-Channel Skew and Pulse Width
Figure 9. DS90CF563 (Transmitter) Setup/Hold and High/Low Times
6
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Copyright © 1997–2013, Texas Instruments Incorporated
Product Folder Links: DS90CF563 DS90CF564
DS90CF563, DS90CF564
www.ti.com
SNLS107E –JULY 1997–REVISED APRIL 2013
Figure 10. DS90CF564 (Receiver) Clock In to Clock Out Delay
Figure 11. DS90CF563 (Transmitter) Clock In to Clock Out Delay
Figure 12. DS90CF564 (Receiver) Clock In to Clock Out Delay
Figure 13. DS90CF563 (Transmitter) Phase Lock Loop Set Time
Copyright © 1997–2013, Texas Instruments Incorporated
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SNLS107E –JULY 1997–REVISED APRIL 2013
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Figure 14. DS90CF564 (Receiver) Phase Lock Loop Set Time
Figure 15. Transmitter LVDS Output Pulse Position Measurement
8
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DS90CF563, DS90CF564
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SNLS107E –JULY 1997–REVISED APRIL 2013
SW—Setup and Hold Time (Internal Data Sampling Window)
TCCS—Transmitter Output Skew
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)
Cable Skew—typically 10 ps–40 ps per foot
Figure 16. Receiver LVDS Input Skew Margin
Figure 17. Seven Bits of LVDS in One Clock Cycle
Figure 18. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CF563)
Figure 19. Receiver Powerdown Delay
Copyright © 1997–2013, Texas Instruments Incorporated
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SNLS107E –JULY 1997–REVISED APRIL 2013
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Figure 20. Transmitter Powerdown Delay
DS90CF563 Pin Descriptions—FPD Link Transmitter
Pin Name
TxIN
I/O No.
Description
I
21 TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME, DRDY (also
referred to as HSYNC, VSYNC, Data Enable)
TxOUT+
O
O
I
3
3
1
1
1
1
4
5
1
2
1
3
Positive LVDS differential data output
Negative LVDS differential data output
TTL level clock input. The falling edge acts as data strobe
Positive LVDS differential clock output
Negative LVDS differential clock output
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down
Power supply pins for TTL inputs
TxOUT−
FPSHIFT IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
VCC
O
O
I
I
GND
I
Ground pins for TTL inputs
PLL VCC
I
Power supply pin for PLL
PLL GND
LVDS VCC
LVDS GND
I
Ground pins for PLL
I
Power supply pin for LVDS outputs
I
Ground pins for LVDS outputs
DS90CF564 Pin Descriptions—FPD Link Receiver
Description
Pin Name
RxIN+
I/O No.
I
I
3
3
Positive LVDS differential data inputs
Negative LVDS differential data inputs
RxIN−
RxOUT
O
21 TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY(also referred to as HSYNC, VSYNC, Data Enable)
RxCLK IN+
RxCLK IN−
FPSHIFT OUT
PWR DOWN
VCC
I
I
1
1
1
1
4
5
1
2
1
3
Positive LVDS differential clock input
Negative LVDS differential clock input
TTL level clock output. The falling edge acts as data strobe
TTL level input. Assertion (low input) maintains the receiver outputs in the previous state
Power supply pins for TTL outputs
O
I
I
GND
I
Ground pins for TTL outputs
PLL VCC
I
Power supply for PLL
PLL GND
LVDS VCC
LVDS GND
I
Ground pin for PLL
I
Power supply pin for LVDS inputs
I
Ground pins for LVDS inputs
10
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Product Folder Links: DS90CF563 DS90CF564
DS90CF563, DS90CF564
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SNLS107E –JULY 1997–REVISED APRIL 2013
Connection Diagram
DS90CF563
DS90CF564
Copyright © 1997–2013, Texas Instruments Incorporated
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SNLS107E –JULY 1997–REVISED APRIL 2013
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REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
12
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90CF564MTD/NOPB
DS90CF564MTDX/NOPB
ACTIVE
TSSOP
TSSOP
DGG
48
48
38
RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-10 to 70
-10 to 70
DS90CF564MTD
>B
ACTIVE
DGG
1000 RoHS & Green
SN
DS90CF564MTD
>B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90CF564MTDX/NOPB TSSOP
DGG
48
1000
330.0
24.4
8.6
13.2
1.6
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 48
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
DS90CF564MTDX/NOPB
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
DGG TSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DS90CF564MTD/NOPB
48
38
495
10
2540
5.79
Pack Materials-Page 3
PACKAGE OUTLINE
DGG0048A
TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
3
5
0
SMALL OUTLINE PACKAGE
C
8.3
7.9
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
46X 0.5
48
1
12.6
12.4
NOTE 3
2X
11.5
24
B
25
0.27
0.17
48X
6.2
6.0
1.2
1.0
0.08
C A B
(0.15) TYP
0.25
GAGE PLANE
0 - 8
SEE DETAIL A
0.15
0.75
0.05
0.50
DETAIL A
TYPICAL
4214859/B 11/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
DGG0048A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
48X (1.5)
SYMM
1
48
48X (0.3)
46X (0.5)
(R0.05)
TYP
SYMM
24
25
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214859/B 11/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DGG0048A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
48X (1.5)
SYMM
1
48
48X (0.3)
46X (0.5)
SYMM
(R0.05) TYP
24
25
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4214859/B 11/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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