DS90CP22M-8 [TI]
DS90CP22 800 Mbps 2x2 LVDS Crosspoint Switch; DS90CP22达到800Mbps的2x2 LVDS交叉点开关
| 型号： | DS90CP22M-8 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DS90CP22 800 Mbps 2x2 LVDS Crosspoint Switch |
| 文件： | 总17页 (文件大小：1016K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90CP22
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SNLS053E –MARCH 2000–REVISED APRIL 2013
DS90CP22 800 Mbps 2x2 LVDS Crosspoint Switch
Check for Samples: DS90CP22
1
FEATURES
DESCRIPTION
DS90CP22 is a 2x2 crosspoint switch utilizing LVDS
(Low Voltage Differential Signaling) technology for
low power, high speed operation. Data paths are fully
differential from input to output for low noise
generation and low pulse width distortion. The non-
blocking design allows connection of any input to any
output or outputs. LVDS I/O enable high speed data
transmission for point-to-point interconnects. This
device can be used as a high speed differential
crosspoint, 2:1 mux, 1:2 demux, repeater or 1:2
signal splitter. The mux and demux functions are
useful for switching between primary and backup
circuits in fault tolerant systems. The 1:2 signal
splitter and 2:1 mux functions are useful for
distribution of serial bus across several rack-mounted
backplanes.
2
•
•
DC - 800 Mbps Low Jitter, Low Skew Operation
65 ps (typ) of Pk-Pk Jitter with PRBS = 223−1
Data Pattern at 800 Mbps
•
•
Single +3.3 V Supply
Less than 330 mW (typ) Total Power
Dissipation
•
•
•
•
Non-Blocking "'Switch Architecture"'
Balanced Output Impedance
Output Channel-to-Channel Skew is 35 ps (typ)
Configurable as 2:1 mux, 1:2 demux, Repeater
or 1:2 Signal Splitter
•
•
•
•
•
LVDS Receiver Inputs Accept LVPECL Signals
Fast Switch Time of 1.2ns (typ)
The DS90CP22 accepts LVDS signal levels, LVPECL
levels directly or PECL with attenuation networks.
Fast Propagation Delay of 1.3ns (typ)
Receiver Input Threshold < ±100 mV
The individual LVDS outputs can be put into TRI-
STATE by use of the enable pins.
Available in 16 Lead TSSOP and SOIC
Packages
•
•
Conforms to ANSI/TIA/EIA-644-1995 LVDS
Standard
For more details, please refer to the Application
Information section of this datasheet.
Operating Temperature: −40°C to +85°C
Connection Diagram
Figure 1. SOIC-16 Package
or
TSSOP-16 Package
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
DS90CP22
SNLS053E –MARCH 2000–REVISED APRIL 2013
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Figure 2. Diff. Output Eye-Pattern in 1:2 split mode @ 800 Mbps
Conditions: 3.3 V, PRBS = 223−1 data pattern,
VID = 300mV, VCM = +1.2 V, 200 ps/div, 100 mV/div
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to +4V
−0.3V to +4V
Continuous
CMOS/TTL Input Voltage (EN0, EN1, SEL0, SEL1)
LVDS Receiver Input Voltage (IN+, IN−)
LVDS Driver Output Voltage (OUT+, OUT−)
LVDS Output Short Circuit Current
Junction Temperature
+150°C
Storage Temperature Range
−65°C to +150°C
+260°C
Lead Temperature (Soldering, 4 sec.)
Maximum Package Power Dissipation at
25°C
16L SOIC
1.435 W
16L SOIC Package Derating
16L TSSOP
11.48 mW/°C above +25°C
0.866 W
16L TSSOP Package Derating
(HBM, 1.5kΩ, 100pF)
(EIAJ, 0Ω, 200pF)
9.6 mW/°C above +25°C
> 5 kV
ESD Rating
> 250 V
(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(2) “Absolute Maximum Ratings” are these beyond which the safety of the device cannot be verified. They are not meant to imply that the
device should be operated at these limits. “Electrical Characteristics” provides conditions for actual device operation.
Recommended Operating Conditions
Min
3.0
0
Typ
Max
3.6
Units
V
Supply Voltage (VCC
)
3.3
Receiver Input Voltage
VCC
+85
V
Operating Free Air Temperature
-40
+25
°C
2
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Electrical Characteristics(1)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS (EN0,EN1,SEL0,SEL1)
VIH
VIL
IIH
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Clamp Voltage
2.0
VCC
0.8
V
V
GND
VIN = 3.6V or 2.0V; VCC = 3.6V
VIN = 0V or 0.8V; VCC = 3.6V
ICL = −18 mA
+7
±1
+20
±10
−1.5
μA
μA
V
IIL
VCL
−0.8
LVDS OUTPUT DC SPECIFICATIONS (OUT0,OUT1)
VOD
Differential Output Voltage
RL = 75Ω
270
285
365
365
475
440
35
mV
mV
mV
V
RL = 75Ω, VCC = 3.3V, TA = 25°C
ΔVOD
VOS
Change in VOD between Complimentary Output States
Offset Voltage(2)
1.0
1.2
±1
1.45
35
ΔVOS
IOZ
Change in VOS between Complimentary Output States
mV
μA
Output TRI-STATE Current
TRI-STATE Output,
±10
VOUT = VCC or GND
IOFF
IOS
Power-Off Leakage Current
Output Short Circuit Current
Both Outputs Short Circuit Current
VCC = 0V; VOUT = 3.6V or GND
VOUT+ OR VOUT− = 0V
VOUT+ AND VOUT− = 0V
±1
±10
−25
−50
μA
mA
mA
−15
−30
IOSB
LVDS RECEIVER DC SPECIFICATIONS (IN0,IN1)
VTH
VTL
VCMR
IIN
Differential Input High Threshold
Differential Input Low Threshold
Common Mode Voltage Range
VCM = +0.05V or +1.2V or +3.25V,
Vcc = 3.3V
0
0
+100
mV
mV
V
−100
VID = 100mV, Vcc = 3.3V
VIN = +3.0V, VCC = 3.6V or 0V
VIN = 0V, VCC = 3.6V or 0V
0.05
3.25
±10
±10
±1
±1
μA
μA
Input Current
SUPPLY CURRENT
ICCD Total Supply Current
ICCZ TRI-STATE Supply Current
RL = 75Ω, CL = 5 pF, EN0 = EN1 = High
98
43
125
55
mA
mA
EN0 = EN1 = Low
(1) All typical are given for VCC = +3.3V and TA = +25°C, unless otherwise stated.
(2) VOS is defined and measured on the ATE as (VOH + VOL) / 2.
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified(1)
Symbol
TSET
Parameter
Conditions
Min
0.7
1.0
0.9
Typ
0.5
Max
Units
ns
Input to SEL Setup Time(2), (Figure 3 and Figure 4)
Input to SEL Setup Time(2), (Figure 3 and Figure 4)
SEL to Switched Output, (Figure 3 and Figure 4)
Disable Time (Active to TRI-STATE) High to Z, Figure 5
Disable Time (Active to TRI-STATE) Low to Z, Figure 5
Enable Time (TRI-STATE to Active) Z to High, Figure 5
Enable Time (TRI-STATE to Active) Z to Low, Figure 5
Output Low-to-High Transition Time, 20% to 80%, Figure 7
Output High-to-Low Transition Time, 80% to 20%, Figure 7
THOLD
TSWITCH
TPHZ
TPLZ
0.5
ns
1.2
1.7
4.0
ns
2.1
ns
3.0
4.5
ns
TPZH
TPZL
25.5
25.5
400
400
55.0
55.0
580
580
ns
ns
TLHT
290
290
ps
THLT
ps
(1) The parameters are specified by design. The limits are based on statistical analysis of the device performance over PVT (process,
voltage and temperature) range.
(2) TSET and THOLD time specify that data must be in a stable state before and after the SEL transition.
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AC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified(1)
Symbol
TJIT
Parameter
Conditions
Min
Typ
Max
Units
VID = 300mV; 50% Duty Cycle; VCM
1.2V at 800Mbps
VID = 300mV; PRBS=223-1 data
pattern; VCM = 1.2V at 800Mbps
=
40
90
ps
LVDS Data Path Peak to Peak Jitter(3)
65
120
ps
TPLHD
Propagation Low to High Delay, Figure 8
Propagation Low to High Delay, Figure 8
Propagation High to Low Delay, Figure 8
Propagation High to Low Delay, Figure 8
0.9
1.0
0.9
1.0
1.3
1.3
1.3
1.3
0
1.6
1.5
1.6
1.5
225
80
ns
ns
ns
ns
ps
ps
VCC = 3.3V, TA = 25°C
VCC = 3.3V, TA = 25°C
TPHLD
TSKEW
TCCS
Pulse Skew |TPLHD - TPHLD
|
Output Channel-to-Channel Skew, Figure 9
35
(3) The parameters are specified by design. The limits are based on statistical analysis of the device performance over PVT range with the
following equipment test setup: HP70004A (display mainframe) with HP70841B (pattern generator), 5 feet of RG-142 cable with DUT
test board and HP83480A (digital scope mainframe) with HP83483A (20GHz scope module).
AC Timing Diagrams
Figure 3. Input-to-Select rising edge setup and hold times and mux switch time
Figure 4. Input-to-Select falling edge setup and hold times and mux switch time
4
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Figure 5. Output active to TRI-STATE and TRI-STATE to active output time
Figure 6. LVDS Output Load
Figure 7. LVDS Output Transition Time
Figure 8. Propagation Delay Low-to-High and High-to-Low
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Figure 9. Output Channel-to-Channel Skew in 1:2 splitter mode
PIN DESCRIPTIONS
Pin Name
IN+
# of Pin
Input/Output
Description
2
2
2
2
I
Non-inverting LVDS input
Inverting LVDS input
IN -
I
OUT+
OUT -
O
O
Non-inverting LVDS Output
Inverting LVDS Output
A logic low on the Enable puts the LVDS output into TRI-STATE and
reduces the supply current
EN
2
I
SEL
GND
VCC
NC
2
1
1
2
I
2:1 mux input select
Ground
P
P
Power Supply
No Connect
6
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APPLICATION INFORMATION
MODES OF OPERATION
The DS90CP22 provides three modes of operation. In the 1:2 splitter mode, the two outputs are copies of the
same single input. This is useful for distribution / fan-out applications. In the repeater mode, the device operates
as a 2 channel LVDS buffer. Repeating the signal restores the LVDS amplitude, allowing it to drive another
media segment. This allows for isolation of segments or long distance applications. The switch mode provides a
crosspoint function. This can be used in a system when primary and redundant paths are supported in fault
tolerant applications.
INPUT FAIL-SAFE
The receiver inputs of the DS90CP22 do not have internal fail-safe biasing. For point-to-point and multidrop
applications with a single source, fail-safe biasing may not be required. When the driver is off, the link is in-
active. If fail-safe biasing is required, this can be accomplished with external high value resistors. The IN+ should
be pull to Vcc with 10kΩ and the IN− should be pull to Gnd with 10kΩ. This provides a slight positive differential
bias, and sets a known HIGH state on the link with a minimum amount of distortion.
UNUSED LVDS INPUTS
Unused LVDS Receiver inputs should be tied off to prevent the high-speed sensitive input stage from picking up
noise signals. The open input to IN+ should be pull to Vcc with 10kΩ and the open input to IN− should be pull to
Gnd with 10kΩ.
UNUSED CONTROL INPUTS
The SEL and EN control input pins have internal pull down devices. Unused pins may be tied off or left as no-
connect (if a LOW state is desired).
EXPANDING THE NUMBER OF OUTPUT PORTS
To expand the number of output ports, more than one DS90CP22 can be used. Total propagation delay through
the devices should be considered to determine the maximum expansion. For example, if 2 X 4 is desired, than
three of the DS90CP22 are required. A minimum of two device propagation delays (2 x 1.3ns = 2.6ns (typ)) can
be achieved. For a 2 X 8, a total of 7 devices must be used with propagation delay of 3 x 1.3ns = 3.9ns (typ).
The power consumption will increase proportional to the number of devices used.
PCB LAYOUT AND POWER SYSTEM BYPASS
Circuit board layout and stack-up for the DS90CP22 should be designed to provide noise-free power to the
device. Good layout practice also will separate high frequency or high level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the
PCB power system which improves power supply filtering, especially at high frequencies, and makes the value
and placement of external bypass capacitors less critical. External bypass capacitors should include both RF
ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 µF to 0.1 µF. It is
recommended practice to use two vias at each power pin of the DS90CP22 as well as all RF bypass capacitor
terminals. Dual vias reduce the interconnect inductance by up to half, thereby reducing interconnect inductance
and extending the effective frequency range of the bypass components.
The outer layers of the PCB may be flooded with additional ground plane. These planes will improve shielding
and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be
effective, these planes must be tied to the ground supply plane at frequent intervals with vias. Frequent via
placement also improves signal integrity on signal transmission lines by providing short paths for image currents
which reduces signal distortion.
There are more common practices which should be followed when designing PCBs for LVDS signaling.
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COMPATIBILITY WITH LVDS STANDARD
The DS90CP22 is compatible with LVDS and Bus LVDS Interface devices. It is enhanced over standard LVDS
drivers in that it is able to driver lower impedance loads with standard LVDS levels. Standard LVDS drivers
provide 330mV differential output with a 100Ω load. The DS90CP22 provides 365mV with a 75Ω load or 400mV
with 100Ω loads. This extra drive capability is useful in certain multidrop applications.
In backplane multidrop configurations, with closely spaced loads, the effective differential impedance of the line is
reduced. If the mainline has been designed for 100Ω differential impedance, the loading effects may reduce this
to the 70Ω range depending upon spacing and capacitance load. Terminating the line with a 75Ω load is a better
match than with 100Ω and reflections are reduced.
BLOCK DIAGRAM
Table 1. Function Table
SEL0
SEL1
OUT0
IN0
OUT1
IN0
Mode
1:2 splitter
repeater
switch
0
0
1
1
0
1
0
1
IN0
IN1
IN1
IN0
IN1
IN1
1:2 splitter
8
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Typical Performance Characteristics
Diff. Output Voltage (VOD) vs. Resistive Load (RT)
Peak-to-Peak Output Jitter at VCM = +0.4V vs. VID
Figure 10.
Figure 11.
Peak-to-Peak Output Jitter at VCM = +1.2V vs. VID
Peak-to-Peak Output Jitter at VCM = +1.6V vs. VID
Figure 12.
Figure 13.
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REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 9
10
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
DS90CP22M-8
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
NRND
SOIC
SOIC
D
16
16
16
16
16
16
48
TBD
Call TI
CU SN
Call TI
CU SN
CU SN
CU SN
Call TI
DS90CP22M
-8
DS90CP22M-8/NOPB
DS90CP22MT
ACTIVE
NRND
D
48
92
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Call TI
DS90CP22M
-8
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
D
TBD
DS90CP
22MT
DS90CP22MT/NOPB
DS90CP22MTX/NOPB
DS90CP22MX-8/NOPB
ACTIVE
ACTIVE
ACTIVE
92
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
DS90CP
22MT
2500
2500
Green (RoHS
& no Sb/Br)
DS90CP
22MT
Green (RoHS
& no Sb/Br)
DS90CP22M
-8
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90CP22MTX/NOPB
DS90CP22MX-8/NOPB
TSSOP
SOIC
PW
D
16
16
2500
2500
330.0
330.0
12.4
16.4
6.95
6.5
8.3
1.6
2.3
8.0
8.0
12.0
16.0
Q1
Q1
10.3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90CP22MTX/NOPB
DS90CP22MX-8/NOPB
TSSOP
SOIC
PW
D
16
16
2500
2500
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
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