DS90CR213MTD/NOPB [TI]
TRIPLE LINE DRIVER, PDSO48, PLASTIC, TSSOP-48;
| 型号： | DS90CR213MTD/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TRIPLE LINE DRIVER, PDSO48, PLASTIC, TSSOP-48 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总15页 (文件大小：472K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OBSOLETE
DS90CR213, DS90CR214
www.ti.com
SNLS125C –JULY 1997–REVISED APRIL 2013
DS90CR213/DS90CR214 21-Bit Channel Link—66 MHz
Check for Samples: DS90CR213, DS90CR214
1
FEATURES
DESCRIPTION
The DS90CR213 transmitter converts 21 bits of
23
•
66 MHz Clock Support
CMOS/TTL data into three LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a fourth LVDS link. Every cycle of the
transmit clock 21 bits of input data are sampled and
transmitted. The DS90CR214 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL
data. At a transmit clock frequency of 66 MHz, 21 bits
of TTL data are transmitted at a rate of 462 Mbps per
LVDS data channel. Using a 66 MHz clock, the data
throughput is 1.386 Gbit/s (173 Mbytes/s).
•
Up to 173 Mbytes/s Bandwidth
•
•
•
•
•
•
•
•
•
Low Power CMOS Design (<610 mW)
Power-down Mode (<0.5 mW total)
Up to 1.386 Gbit/s Data Throughput
Narrow Bus Reduces Cable Size and Cost
290 mV Swing LVDS Devices for Low EMI
PLL Requires No External Components
Low Profile 48-Lead TSSOP Package
Rising Edge Data Strobe
The multiplexing of the data lines provides
a
Compatible with TIA/EIA-644 LVDS Standard
substantial cable reduction. Long distance parallel
single-ended buses typically require a ground wire
per active signal (and have very limited noise
rejection capability). Thus, for a 21-bit wide data and
one clock, up to 44 conductors are required. With the
Channel Link chipset as few as 9 conductors (3 data
pairs, 1 clock pair and a minimum of one ground) are
needed. This provides an 80% reduction in required
cable width, which provides a system cost savings,
reduces connector physical size and cost, and
reduces shielding requirements due to the cable's
smaller form factor.
The 21 CMOS/TTL inputs can support a variety of
signal combinations. For example, 5 4-bit nibbles
(byte + parity) or 2 9-bit (byte + 3 parity) and 1
control.
BLOCK DIAGRAM
Figure 1. DS90CR213
See Package Number DGG0048A
Figure 2. DS90CR214
See NS Package Number DGG0048A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TRI-STATE is a registered trademark of Texas Instruments.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2013, Texas Instruments Incorporated
OBSOLETE
DS90CR213, DS90CR214
SNLS125C –JULY 1997–REVISED APRIL 2013
www.ti.com
Connection Diagrams
Figure 3. DS90CR213
Typical Application
Figure 4. DS90CR214
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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OBSOLETE
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SNLS125C –JULY 1997–REVISED APRIL 2013
Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC
)
−0.3V to +6V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
Continuous
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Duration
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
+260°C
Lead Temperature (Soldering, 4 sec)
Maximum Package Power Dissipation Capacity
DGG0048A (TSSOP) Package
@25°C
DS90CR213
1.98W
DS90CR214
DS90CR213
DS90CR214
1.89W
Package Derating:
16 mW/°C above +25°C
15 mW/°C above +25°C
ESD Rating(3)This device does not meet 2000V
(1) Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(2) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to
imply that the device should be operated at these limits. “Electrical Characteristics” specify conditions for device operation.
(3) ESD Rating: HBM (1.5 kΩ, 100 pF) PLL VCC ≥ 1000V All Other Pins ≥ 2000V EIAJ (0Ω, 200 pF) ≥ 150V
Recommended Operating Conditions
Min
4.75
−10
0
Nom
5.0
Max
5.25
+70
2.4
Units
V
Supply Voltage (VCC
)
Operating Free Air Temperature (TA)
Receiver Input Range
+25
°C
V
Supply Noise Voltage (VCC
)
100
mVP-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Clamp Voltage
2.0
VCC
0.8
V
V
GND
3.8
VOH
VOL
VCL
IIN
IOH = −0.4 mA
IOL = 2 mA
4.9
0.1
V
0.3
−1.5
±10
V
ICL = −18 mA
−0.79
±5.1
V
Input Current
VIN = VCC, GND, 2.5V or 0.4V
VOUT = 0V
μA
mA
IOS
Output Short Circuit Current
−120
LVDS DRIVER DC SPECIFICATIONS
VOD
Differential Output Voltage
RL = 100Ω
250
1.1
290
450
35
mV
mV
ΔVOD
Change in VOD between
Complimentary Output States
VOS
Offset Voltage
1.25
1.375
35
V
ΔVOS
Change in Magnitude of VOS
between Complimentary Output
States
mV
IOS
IOZ
Output Short Circuit Current
Output TRI-STATE® Current
VOUT = 0V, R L = 100Ω
−2.9
−5
mA
Powerdown = 0V, VOUT = 0V or VCC
±1
±10
μA
LVDS RECEIVER DC SPECIFICATIONS
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
VTH
Parameter
Differential Input High Threshold
Differential Input Low Threshold
Input Current
Conditions
Min
Typ
Max
Units
mV
mV
μA
VCM = +1.2V
+100
VTL
IIN
−100
VIN = +2.4V, VCC = 5.0V
VIN = 0V, VCC = 5.0V
±10
±10
μA
TRANSMITTER SUPPLY CURRENT
ICCTW
Transmitter Supply Current
Worst Case
RL = 100Ω, C L = 5 pF,
Worst Case Pattern
(Figure 5 and Figure 6 )
Powerdown = Low
f = 32.5 MHz
f = 37.5 MHz
f = 66 MHz
49
51
70
63
64
84
mA
mA
mA
ICCTZ
Transmitter Supply Current
Power Down
Driver Outputs in TRI-STATE under
Powerdown Mode
1
25
μA
RECEIVER SUPPLY CURRENT
ICCRW
Receiver Supply Current
Worst Case
CL = 8 pF,
f = 32.5 MHz
64
70
77
85
mA
mA
mA
Worst Case Pattern
(Figure 5 and Figure 7 )
Powerdown = Low
f = 37.5 MHz
f = 66 MHz
110
140
ICCRZ
Receiver Supply Current
Power Down
Receiver Outputs in Previous State during
Power Down Mode.
1
10
μA
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
Parameter
LVDS Low-to-High Transition Time (Figure 6 )
LVDS High-to-Low Transition Time (Figure 6 )
TxCLK IN Transition Time (Figure 8 )
Min
Typ
0.75
0.75
Max
1.5
Units
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
LHLT
1.5
TCIT
8
TCCS
TxOUT Channel-to-Channel Skew (1) (Figure 9)
350
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 20 )
TPPos1 Transmitter Output Pulse Position for Bit 1
TPPos2 Transmitter Output Pulse Position for Bit 2
TPPos3 Transmitter Output Pulse Position for Bit 3
TPPos4 Transmitter Output Pulse Position for Bit 4
TPPos5 Transmitter Output Pulse Position for Bit 5
TPPos6 Transmitter Output Pulse Position for Bit 6
−0.30
1.70
3.60
5.90
8.30
10.40
12.70
15
0
0.30
2.50
4.50
6.75
9.00
11.10
13.40
50
(1/7)Tclk
(2/7)Tclk
(3/7)Tclk
(4/7)Tclk
(5/7)Tclk
(6/7)Tclk
T
f = 66 MHz
TCIP
TxCLK IN Period (Figure 10 )
TCIH
TxCLK IN High Time (Figure 10 )
0.35T
0.35T
5
0.5T
0.65T
0.65T
TCIL
TxCLK IN Low Time (Figure 10 )
0.5T
TSTC
THTC
TCCD
TPLLS
TPDD
TxIN Setup to TxCLK IN (Figure 10 )
TxIN Hold to TxCLK IN (Figure 10 )
3.5
2.5
1.5
TxCLK IN to TxCLK OUT Delay @25°C, VCC = 5.0V (Figure 12 )
Transmitter Phase Lock Loop Set (Figure 14 )
Transmitter Powerdown Delay (Figure 18 )
3.5
8.5
10
100
(1) This limit based on bench characterization.
4
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SNLS125C –JULY 1997–REVISED APRIL 2013
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
Parameter
Min
Typ
2.5
2.0
Max
4.0
Units
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
μs
CMOS/TTL Low-to-High Transition Time (Figure 7 )
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 7 )
4.0
(1)
RSKM
RxIN Skew Margin
V
= 5V,TA = 25°C(Figure 21)
f = 40 MHz
f = 66 MHz
700
600
15
CC
RCOP
RCOH
RxCLK OUT Period (Figure 11 )
T
5
50
RxCLK OUT High Time (Figure 11 )
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
6
4.3
10.5
7.0
4.5
2.5
6.5
4
RCOL
RSRC
RHRC
RxCLK OUT Low Time (Figure 11 )
9
RxOUT Setup to RxCLK OUT (Figure 11 )
RxOUT Hold to RxCLK OUT (Figure 11 )
4.2
5.2
RCCD
RPLLS
RPDD
RxCLK IN to RxCLK OUT Delay @25°C, VCC = 5.0V (Figure 13 )
Receiver Phase Lock Loop Set (Figure 15 )
6.4
10.7
10
1
Receiver Powerdown Delay (Figure 19 )
(1) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter
output skew (TCCS) and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependent on type/length
and source clock (TxCLK IN) jitter.RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle)
AC Timing Diagrams
Figure 5. “Worst Case” Test Pattern
Figure 6. DS90CR213 (Transmitter) Input Clock Transition Time
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Figure 7. DS90CR214 (Receiver) CMOS/TTL Output Load and Transition Times
Figure 8. DS90CR213 (Transmitter) Input Clock Transition Time
(1) Measurements at Vdiff = 0V
(2) TCSS measured between earliest and latest LVDS edges.
(3) TxCLK Differential Low→High Edge
Figure 9. DS90CR213 (Transmitter) Channel-to-Channel Skew
Figure 10. DS90CR213 (Transmitter) Setup/Hold and High/Low Times
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SNLS125C –JULY 1997–REVISED APRIL 2013
Figure 11. DS90CR214 (Receiver) Setup/Hold and High/Low Times
Figure 12. DS90CR213 (Transmitter) Clock In to Clock Out Delay
Figure 13. DS90CR214 (Receiver) Clock In to Clock Out Delay
Figure 14. DS90CR213 (Transmitter) Phase Lock Loop Set Time
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Figure 15. DS90CR214 (Receiver) Phase Lock Loop Set Time
Figure 16. Seven Bits of LVDS in One Clock Cycle
Figure 17. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs
Figure 18. Transmitter Powerdown Delay
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SNLS125C –JULY 1997–REVISED APRIL 2013
Figure 19. Receiver Powerdown Delay
Figure 20. Transmitter LVDS Output Pulse Position Measurement
SW—Setup and Hold Time (Internal Data Sampling Window)
TCCS—Transmitter Output Skew
RSKM ≥ Cable Skew (Type, Length) + Source Clock Jitter (Cycle to Cycle)
Cable Skew—Typically 10 ps–40 ps per foot
Figure 21. Receiver LVDS Input Skew Margin
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DS90CR213 Pin Description—Channel Link Transmitter
Pin Name
TxIN
I/O
I
No.
Description
21
3
3
1
1
1
1
4
5
1
2
1
3
TTL level inputs.
TxOUT+
O
O
I
Positive LVDS differential data output.
Negative LVDS differentiaI data output.
TxOUT−
TxCLK IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
VCC
TTL level clock input. The rising edge acts as data strobe.
Positive LVDS differential clock output.
O
O
I
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down.
Power supply pins for TTL inputs.
I
GND
I
Ground pins for TTL inputs.
PLL VCC
I
Power supply pin for PLL.
PLL GND
LVDS VCC
LVDS GND
I
Ground pins for PLL.
I
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
I
DS90CR214 Pin Description—Channel Link Receiver
Description
Pin Name
RxIN+
I/O
No.
I
I
3
3
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
TTL level outputs.
RxIN−
RxOUT
O
I
21
1
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
VCC
Positive LVDS differential clock input.
Negative LVDS differentiaI clock input.
TTL level clock output. The rising edge acts as data strobe.
TTL Ievel input. Locks the previous receiver output state.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
I
1
O
I
1
1
I
4
GND
I
5
PLL VCC
PLL GND
LVDS VCC
LVDS GND
I
1
Power supply for PLL.
I
2
Ground pin for PLL.
I
1
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
I
3
10
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SNLS125C –JULY 1997–REVISED APRIL 2013
APPLICATIONS INFORMATION
The Channel Link devices are intended to be used in a wide variety of data transmission applications. Depending
upon the application the interconnecting media may vary. For example, for lower data rate (clock rate) and
shorter cable lengths (< 2m), the media electrical performance is less critical. For higher speed/long distance
applications the media's performance becomes more critical. Certain cable constructions provide tighter skew
(matched electrical length between the conductors and pairs). Twin-coax for example, has been demonstrated at
distances as great as 5 meters and with the maximum data transfer of 1.38 Gbit/s. Additional applications
information can be found in the following Interface Application Notes:
AN = ####
AN-1041 (SNLA218)
AN-1035 (SNOA355)
Topic
Introduction to Channel Link
PCB Design Guidelines for LVDS
and Link Devices
AN-806 (SNLA026)
AN-905 (SNLA035)
Transmission Line Theory
Transmission Line Calculations
and Differential Impedance
AN-916 (SNLA219)
Cable Information
CABLES
A cable interface between the transmitter and receiver needs to support the differential LVDS pairs. The 21-bit
CHANNEL LINK chipset (DS90CR213/214) requires four pairs of signal wires and the 28-bit CHANNEL LINK
chipset (DS90CR283/284) requires five pairs of signal wires. The ideal cable/connector interface would have a
constant 100Ω differential impedance throughout the path. It is also recommended that cable skew remain below
350 ps (@ 66 MHz clock rate) to maintain a sufficient data sampling window at the receiver.
In addition to the four or five cable pairs that carry data and clock, it is recommended to provide at least one
additional conductor (or pair) which connects ground between the transmitter and receiver. This low impedance
ground provides a common mode return path for the two devices. Some of the more commonly used cable types
for point-to-point applications include flat ribbon, flex, twisted pair and Twin-Coax. All are available in a variety of
configurations and options. Flat ribbon cable, flex and twisted pair generally perform well in short point-to-point
applications while Twin-Coax is good for short and long applications. When using ribbon cable, it is
recommended to place a ground line between each differential pair to act as a barrier to noise coupling between
adjacent pairs. For Twin-Coax cable applications, it is recommended to utilize a shield on each cable pair. All
extended point-to-point applications should also employ an overall shield surrounding all cable pairs regardless
of the cable type. This overall shield results in improved transmission parameters such as faster attainable
speeds, longer distances between transmitter and receiver and reduced problems associated with EMS or EMI.
The high-speed transport of LVDS signals has been demonstrated on several types of cables with excellent
results. However, the best overall performance has been seen when using Twin-Coax cable. Twin-Coax has very
low cable skew and EMI due to its construction and double shielding. All of the design considerations discussed
here and listed in the supplemental application notes provide the subsystem communications designer with many
useful guidelines. It is recommended that the designer assess the tradeoffs of each application thoroughly to
arrive at a reliable and economical cable solution.
BOARD LAYOUT
To obtain the maximum benefit from the noise and EMI reductions of LVDS, attention should be paid to the
layout of differential lines. Lines of a differential pair should always be adjacent to eliminate noise interference
from other signals and take full advantage of the noise canceling of the differential signals. The board designer
should also try to maintain equal length on signal traces for a given differential pair. As with any high speed
design, the impedance discontinuities should be limited (reduce the numbers of vias and no 90 degree angles on
traces). Any discontinuities which do occur on one signal line should be mirrored in the other line of the
differential pair. Care should be taken to ensure that the differential trace impedance match the differential
impedance of the selected physical media (this impedance should also match the value of the termination
resistor that is connected across the differential pair at the receiver's input). Finally, the location of the CHANNEL
LINK TxOUT/RxIN pins should be as close as possible to the board edge so as to eliminate excessive pcb runs.
All of these considerations will limit reflections and crosstalk which adversely effect high frequency performance
and EMI.
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UNUSED INPUTS
All unused inputs at the TxIN inputs of the transmitter must be tied to ground. All unused outputs at the RxOUT
outputs of the receiver must then be left floating.
TERMINATION
Use of current mode drivers requires a terminating resistor across the receiver inputs. The CHANNEL LINK
chipset will normally require a single 100Ω resistor between the true and complement lines on each differential
pair of the receiver input. The actual value of the termination resistor should be selected to match the differential
mode characteristic impedance (90Ω to 120Ω typical) of the cable. Figure 22 shows an example. No additional
pull-up or pull-down resistors are necessary as with some other differential technologies such as PECL. Surface
mount resistors are recommended to avoid the additional inductance that accompanies leaded resistors. These
resistors should be placed as close as possible to the receiver input pins to reduce stubs and effectively
terminate the differential lines.
DECOUPLING CAPACITORS
Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a
conservative approach three parallel-connected decoupling capacitors (Multi-Layered Ceramic type in surface
mount form factor) between each VCC and the ground plane(s) are recommended. The three capacitor values are
0.1 μF, 0.01μF and 0.001 μF. An example is shown in Figure 23. The designer should employ wide traces for
power and ground and ensure each capacitor has its own via to the ground plane. If board space is limiting the
number of bypass capacitors, the PLL VCC should receive the most filtering/bypassing. Next would be the LVDS
VCC pins and finally the logic VCC pins.
Figure 22. LVDS Serialized Link Termination
Figure 23. CHANNEL LINK
Decoupling Configuration
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CLOCK JITTER
The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS
interface. The width of each bit in the serialized LVDS data stream is one-seventh the clock period. For example,
a 66 MHz clock has a period of 15 ns which results in a data bit width of 2.16 ns. Differential skew (Δt within one
differential pair), interconnect skew (Δt of one differential pair to another) and clock jitter will all reduce the
available window for sampling the LVDS serial data streams. Care must be taken to ensure that the clock input
to the transmitter be a clean low noise signal. Individual bypassing of each VCC to ground will minimize the noise
passed on to the PLL, thus creating a low jitter LVDS clock. These measures provide more margin for channel-
to-channel skew and interconnect skew as a part of the overall jitter/skew budget.
COMMON MODE vs. DIFFERENTIAL MODE NOISE MARGIN
The typical signal swing for LVDS is 300 mV centered at +1.2V. The CHANNEL LINK receiver supports a 100
mV threshold therefore providing approximately 200 mV of differential noise margin. Common mode protection is
of more importance to the system's operation due to the differential data transmission. LVDS supports an input
voltage range of Ground to +2.4V. This allows for a ±1.0V shifting of the center point due to ground potential
differences and common mode noise.
POWER SEQUENCING AND POWERDOWN MODE
Outputs of the CHANNEL LINK transmitter remain in TRI-STATE until the power supply reaches 3V. Clock and
data outputs will begin to toggle 10 ms after VCC has reached 4.5V and the Powerdown pin is above 2V. Either
device may be placed into a powerdown mode at any time by asserting the Powerdown pin (active low). Total
power dissipation for each device will decrease to 5 μW (typical).
The CHANNEL LINK chipset is designed to protect itself from accidental loss of power to either the transmitter or
receiver. If power to the transmit board is lost, the receiver clocks (input and output) stop. The data outputs
(RxOUT) retain the states they were in when the clocks stopped. When the receiver board loses power, the
receiver inputs are shorted to V
through an internal diode. Current is limited (5 mA per input) by the fixed
CC
current mode drivers, thus avoiding the potential for latchup when powering the device.
Figure 24. Single-Ended and Differential Waveforms
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 13
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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