DS90CR286ATDGGQ1 [TI]
3.3V 上升沿数据选通信号 LVDS 接收器 28 位 Channel Link 66MHz | DGG | 56 | -40 to 105;
| 型号： | DS90CR286ATDGGQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3V 上升沿数据选通信号 LVDS 接收器 28 位 Channel Link 66MHz | DGG | 56 | -40 to 105 通信 |
| 文件： | 总30页 (文件大小：1887K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DS90CR286AT-Q1
ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
DS90CR286AT-Q1 3.3V 上升沿数据选通信号
LVDS 接收器 28 位 Channel Link 66MHz
1 特性
3 说明
1
•
•
•
•
20MHz 至 66MHz 移位时钟支持
DS90CR286AT-Q1 接收器可将四条 LVDS（低压差分
信令）数据流转换回 28 位并行 LVCMOS 数据。接收
器数据在输出时钟的上升沿输出选通信号。
接收器输出时钟的占空比为 50%
接收端输出拥有出色的建立和保持时间
66MHz（最差情况下）时的接收功耗 < 270mW
（典型值）
接收器 LVDS 时钟的工作速率为 20MHz 至 66MHz。
DS90CR286AT-Q1 会锁相至输入 LVDS 时钟、对
LVDS 数据线路上的串行位流进行采样、然后将其转换
为 28 位并行输出数据。在 66MHz 的传入时钟速率
下，每条 LVDS 输入线路均以 462Mbps 的位速率运
行，最大吞吐量达 1.848Gbps。
•
•
•
•
•
•
•
接收端省电模式 < 200μW（最大值）
静电放电 (ESD) 额定值：4kV (HBM)，1kV (CDM)
锁相环 (PLL) 无需外部组件
与 TIA/EIA-644 LVDS 标准兼容
薄型 56 引脚 DGG (TSSOP) 封装
工作温度范围：−40°C 至 +105°C
符合汽车类 AEC-Q100 2 级标准
DS90CR286AT-Q1 器件的接收器输出拥有更长的数据
有效时间，相比上一代接收器有显著提升。
DS90CR286AT-Q1 针对 PCB 电路板芯片间 OpenLDI
至 RGB 桥接转化而设计。对于这款器件，不建议通过
电缆互连的方式传输 LVDS 数据。
2 应用
•
•
•
•
•
•
视频显示
车用信息娱乐
用户使用兼容的 OpenLDI 发送器和 DS90CR286AT-
Q1 接收器设计子系统时，需要确保偏差裕度预算
(RSKM) 在可接受的范围内。有关 RSKM 的详细信
息，可参见“应用信息”部分。
工业用打印机和成像
数字视频传输
机器视觉
OpenLDI 至 RGB 桥接器
器件信息(1)
器件型号
封装
封装尺寸（标称值）
DS90CR286AT-Q1
TSSOP (56)
14.00mm x 6.10mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
典型应用方框图
ꢀ/. Çrꢁce
5{90/w286!Ç-v1 28-.it wx
24-.it wD. 5isplꢁy Ünit
wxhÜÇꢂ27:0]
[ë5{ 5ꢁtꢁ
Graphics Processor Unit (GPU)
28-Bit Tx Data
(4 LVDS Data, 1 LVDS Clock)
[ë5{ /lock
wx/[Y
PLL
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNLS498
DS90CR286AT-Q1
ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
www.ti.com.cn
目录
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 14
Power Supply Recommendations...................... 19
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 6
6.7 Typical Characteristics............................................ 10
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
8
9
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 器件和文档支持 ..................................................... 21
11.1 文档支持 ............................................................... 21
11.2 社区资源................................................................ 21
11.3 商标....................................................................... 21
11.4 静电放电警告......................................................... 21
11.5 Glossary................................................................ 21
12 机械、封装和可订购信息....................................... 21
7
4 修订历史记录
Changes from Original (November 2015) to Revision A
Page
•
已更改 产品预览至完整的数据表量产数据版本....................................................................................................................... 1
2
Copyright © 2015, Texas Instruments Incorporated
DS90CR286AT-Q1
www.ti.com.cn
ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
5 Pin Configuration and Functions
DGG Package
56-Pin TSSOP
Top View
Pin Functions
PIN
I/O , TYPE
PIN DESCRIPTION
NAME
NO.
RxIN0+, RxIN0-,
RxIN1+, RxIN1-,
RxIN2+, RxIN2-,
RxIN3+, RxIN3-
10, 9,
Positive and negative LVDS differential data inputs. 100 Ω termination resistors
should be placed between RxIN+ and RxIN- receiver inputs as close as
possible to the receiver pins for proper signaling.
12, 11,
16, 15,
20, 19
I, LVDS
I, LVDS
Positive and negative LVDS differential clock input. 100 Ω termination resistor
should be placed between RxCLKIN+ and RxCLKIN- receiver inputs as close
as possible to the receiver pins for proper signaling.
RxCLKIN+,
RxCLKIN-
18,
17
7, 6, 5, 3,
2, 1, 55, 54,
53, 51, 50, 49,
47, 46, 45, 43,
42, 41, 39, 38,
37, 35, 34, 33,
32, 30, 29, 27
RxOUT[27:0]
O, LVCMOS
LVCMOS level data outputs.
RxCLK OUT
PWR DWN
VCC
26
O, LVCMOS
I, LVCMOS
Power
LVCMOS Ievel clock output. The rising edge acts as the data strobe.
LVCMOS level input. When asserted low, the receiver outputs are low.
Power supply pins for LVCMOS outputs.
25
56, 48, 40, 31
52, 44, 36,
28, 4
GND
Power
Ground pins for LVCMOS outputs.
PLL VCC
23
Power
Power
Power
Power
Power supply for PLL.
PLL GND
LVDS VCC
LVDS GND
24, 22
13
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
21, 14, 8
Copyright © 2015, Texas Instruments Incorporated
3
DS90CR286AT-Q1
ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
−0.3
−0.3
−0.3
MAX
4
UNIT
V
Supply Voltage (VCC
)
LVCMOS Output Voltage
(VCC + 0.3)
(VCC + 0.3)
150
V
LVDS Receiver Input Voltage
Operating Junction Temperature
Lead Temperature (Soldering, 4 sec)
Storage temperature, Tstg
V
°C
°C
°C
260
−65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.0
−40
0
NOM
3.3
MAX
3.6
UNIT
Supply Voltage (VCC
)
V
°C
Operating Free Air Temperature (TA)
Receiver Input Range
25
105
2.4
V
Supply Noise Voltage (VNoise
)
100
mVp-p
6.4 Thermal Information
DS90CR286AT-Q1
THERMAL METRIC(1)
DGG (TSSOP)
56 PINS
64.6
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
20.6
33.3
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.0
ψJB
33.0
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
DS90CR286AT-Q1
www.ti.com.cn
ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
6.5 Electrical Characteristics(1)(2)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS DC SPECIFICATIONS (For PWR DWN Pin)
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
2.0
VCC
0.8
V
V
GND
VCL
ICL = −18 mA
−0.79
+1.8
0
−1.5
+10
V
VIN = 0.4 V, 2.5 V or VCC
V IN = GND
μA
μA
IIN
Input Current
−10
LVCMOS DC SPECIFICATIONS
VOH
VOL
IOS
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
IOH = −0.4 mA
IOL = 2 mA
2.7
3.3
0.06
−60
V
V
0.3
VOUT = 0 V
−120
mA
LVDS RECEIVER DC SPECIFICATIONS
Differential Input High
Threshold
VCM = 1.2 V
VCM = 1.2 V
+100
mV
mV
VTH
Differential Input Low
Threshold
−100
VTL
VIN = 2.4 V, VCC = 3.6 V
VIN = 0V , VCC = 3.6 V
±10
±10
65
μA
μA
IIN
Input Current
CL = 8 pF, Worst Case Pattern,
DS90CR286AT-Q1 (Figure 1
Figure 2), TA=−40°C to 105°C
f = 33 MHz
f = 40 MHz
f = 66 MHz
49
53
81
mA
mA
mA
Receiver Supply Current
Worst Case
ICCRW
ICCRZ
70
105
Receiver Supply Current
Power Down
PWR DWN = Low; Receiver Outputs Stay Low
during Power Down Mode
10
55
μA
(1) Typical values are given for VCC = 3.3 V and TA = 25ºC.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VOD and ΔV OD).
Copyright © 2015, Texas Instruments Incorporated
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DS90CR286AT-Q1
ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
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6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CLHT
LVCMOS Low-to-High Transition Time
2
5
ns
(Figure 2)
CHLT
LVCMOS High-to-Low Transition Time
(Figure 2)
1.8
1.4
5
ns
ns
RSPos0
Receiver Input Strobe Position for Bit 0
1.01
2.45
(Figure 8)
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSPos0
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
4.52
8.08
5.0
8.5
5.99
9.35
ns
ns
ns
ns
ns
ns
f = 40 MHz, T = 25ºC
f = 66 MHz, T = -40ºC
f = 66 MHz, T = 25ºC
f = 66 MHz, T = 105ºC
11.59
15.15
18.86
22.34
11.9
15.6
19.2
22.9
12.89
16.53
20.20
23.91
Receiver Input Strobe Position for Bit 0
(Figure 8)
0.58
1.1
1.55
ns
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSPos0
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
2.77
5.01
3.3
5.4
3.80
5.77
ns
ns
ns
ns
ns
ns
7.11
7.5
7.88
9.24
9.7
10.12
12.32
14.50
11.44
13.62
11.9
14.1
Receiver Input Strobe Position for Bit 0
(Figure 8)
0.68
1.2
1.64
ns
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSPos0
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
2.88
5.08
3.4
5.5
3.88
5.87
ns
ns
ns
ns
ns
ns
7.20
7.6
7.98
9.30
9.7
10.24
12.40
14.57
11.50
13.70
12.0
14.2
Receiver Input Strobe Position for Bit 0
(Figure 8)
0.84
1.3
1.74
ns
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RCOP
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxCLK OUT Period (Figure 3)
3.00
5.14
7.30
9.42
11.59
13.83
15
3.6
5.6
4.05
6.02
8.14
10.40
12.57
14.73
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.8
9.9
12.1
14.3
RCOH
RCOL
RxCLK OUT High Time (Figure 3)
RxCLK OUT Low Time (Figure 3)
10.0
10.0
6.5
12.2
11.0
11.6
11.6
7.6
f = 40 MHz
f = 66 MHz
RSRC
RxOUT Setup to RxCLK OUT (Figure 3)
RxOUT Hold to RxCLK OUT (Figure 3)
RxCLK OUT High Time (Figure 3)
RxCLK OUT Low Time (Figure 3)
RHRC
6.0
RCOH
RCOL
5.0
5.0
6.3
RSRC
RxOUT Setup to RxCLK OUT (Figure 3)
RxOUT Hold to RxCLK OUT (Figure 3)
4.5
7.3
RHRC
4.0
6.3
6
Copyright © 2015, Texas Instruments Incorporated
DS90CR286AT-Q1
www.ti.com.cn
ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
Switching Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RCCD
RxCLK IN to RxCLK OUT Delay at 25°C,
3.5
5.0
7.5
ns
VCC = 3.3V(1) (Figure 4)
RPLLS
RPDD
Receiver Phase Lock Loop Set (Figure 5)
Receiver Power Down Delay (Figure 7)
10
1
ms
μs
(1) Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver
(RCCD). The total latency for the DS90CR285 transmitter and DS90CR286AT-Q1 receiver is: (T + TCCD) + (2*T + RCCD), where T =
Clock period. If another transmitter is used, the alternative transmitter's TCCD must be used to calculate total latency.
Figure 1. "Worst Case" Test Pattern
[ë/ah{ hutput
Figure 2. LVCMOS Output Load and Transition Times
Figure 3. Setup/Hold and High/Low Times
Copyright © 2015, Texas Instruments Incorporated
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DS90CR286AT-Q1
ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
www.ti.com.cn
Figure 4. Clock In to Clock Out Delay
Figure 5. Phase Lock Loop Set Time
wx/[Y Lb
(ꢁifferential)
wxLb3
({ingle-ꢀnded)
wxhÜÇ5-1
wxhÜÇ20-1
wxhÜÇ9-1
wxhÜÇ1-1
wxhÜÇ23
wxhÜÇ26
wxhÜÇ18
wxhÜÇ7
wxhÜÇ16
wxhÜÇ24
wxhÜÇ14
wxhÜÇ4
wxhÜÇ5
wxhÜÇ20
wxhÜÇ9
wxhÜÇ1
wxhÜÇ27-1
wxhÜÇ19-1
wxhÜÇ8-1
wxhÜÇ0-1
wxhÜÇ17
wxhÜÇ25
wxhÜÇ15
wxhÜÇ6
wxhÜÇ11
wxhÜÇ22
wxhÜÇ13
wxhÜÇ3
wxhÜÇ10
wxhÜÇ21
wxhÜÇ12
wxhÜÇ2
wxhÜÇ27
wxhÜÇ19
wxhÜÇ8
wxhÜÇ0
wxLb2
({ingle-ꢀnded)
wxLb1
({ingle-ꢀnded)
wxLb0
({ingle-ꢀnded)
Figure 6. Mapping of 28 LVCMOS Parallel Data to 4D + C LVDS Serialized Data
8
Copyright © 2015, Texas Instruments Incorporated
DS90CR286AT-Q1
www.ti.com.cn
ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
Figure 7. Power Down Delay
Figure 8. LVDS Input Strobe Position
Copyright © 2015, Texas Instruments Incorporated
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DS90CR286AT-Q1
ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
www.ti.com.cn
6.7 Typical Characteristics
2
4.5
4
1.5
1
3.5
3
Max
Max
0.5
0
2.5
2
Nominal
Min
Nominal
Min
20
50
80
110
20
50
80
110
œ40
œ10
œ40
œ10
Temperature (°C)
Temperature (°C)
C001
C002
Figure 9. Rx Strobe Position 0 versus Temperature
Operating Frequency: 66 MHz
Figure 10. Rx Strobe Position 1 versus Temperature
Operating Frequency: 66 MHz
6.5
8.5
6
5.5
5
8
7.5
7
Max
Max
4.5
4
Nominal
Min
Nominal
Min
6.5
20
50
80
110
20
50
80
110
œ40
œ10
œ40
œ10
Temperature (°C)
Temperature (°C)
C003
C004
Figure 11. Rx Strobe Position 2 versus Temperature
Operating Frequency: 66 MHz
Figure 12. Rx Strobe Position 3 versus Temperature
Operating Frequency: 66 MHz
10.5
13
12.5
10
9.5
9
12
11.5
11
Max
Max
Nominal
Min
Nominal
Min
8.5
10.5
20
50
80
110
20
50
80
110
œ40
œ10
œ40
œ10
Temperature (°C)
Temperature (°C)
C005
C006
Figure 13. Rx Strobe Position 4 versus Temperature
Operating Frequency: 66 MHz
Figure 14. Rx Strobe Position 5 versus Temperature
Operating Frequency: 66 MHz
10
Copyright © 2015, Texas Instruments Incorporated
DS90CR286AT-Q1
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ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
Typical Characteristics (continued)
15
14.5
14
Max
13.5
Nominal
Min
13
20
50
80
110
œ40
œ10
Temperature (°C)
C007
Figure 15. Rx Strobe Position 6 versus Temperature
Operating Frequency: 66 MHz
Çime (20.0 ns/5Lë)
Çime (5.0 ns/ꢀLë)
Figure 16. Parallel PRBS-7 on LVCMOS Outputs at 66 MHz
Figure 17. Typical RxOUT Timing Diagram at 66 MHz
Çime (5.0 ns/ꢀLë)
Çime (5.0 ns/ꢀLë)
Figure 18. Typical RxOUT Setup Time at 66 MHz
(RSRC = 7.1 ns)
Figure 19. Typical RxOUT Hold Time at 66 MHz
(RHRC = 7.0 ns)
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DS90CR286AT-Q1
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7 Detailed Description
7.1 Overview
The DS90CR286AT-Q1 is an AEC-Q100 Grade 2 receiver that converts four LVDS (Low Voltage Differential
Signaling) data streams back into parallel 28 bits of LVCMOS data (24 bits of RGB and 4 bits of HSYNC,
VSYNC, DE, and CNTL). An internal PLL locks to the incoming LVDS clock ranging from 20 to 66 MHz. The
locked PLL then ensures a stable clock to sample the output LVCMOS data on the Receiver Clock Out rising
edge. The DS90CR286AT-Q1 features a PWR DWN pin to put the device into low power mode when there is no
active input data.
7.2 Functional Block Diagram
4 x [ë5{ 5ꢀtꢀ
(140 to 462 abps on
9ꢀcꢁ [ë5{ /ꢁꢀnnel)
28 x [ë/ah{
hutputs
[ë5{ /lock
(20 to 66 aIz)
PLL
weceiver /lock hut
ꢂíw 5íꢃ
Figure 20. DS90CR286AT-Q1 Block Diagram
7.3 Feature Description
The DS90CR286AT-Q1 consists of several key blocks:
•
•
•
•
LVDS Receivers
Phase Locked Loop (PLL)
Serial LVDS-to-Parallel LVCMOS Converter
LVCMOS Drivers
7.3.1 LVDS Receivers
There are five differential LVDS inputs to the DS90CR286AT-Q1. Four of the LVDS inputs contain serialized data
originating from a 28-bit source transmitter. The remaining LVDS input contains the LVDS clock associated with
the data pairs.
12
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ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
Feature Description (continued)
7.3.1.1 Input Termination
The DS90CR286AT-Q1 requires a single 100 Ω terminating resistor across the positive and negative lines on
each differential pair of the receiver input. To prevent reflections due to stubs, this resistor should be placed as
close to the device input pins as possible. Figure 21 shows an example.
wxLb+
ÇxhÜÇ+
100 Q
[ë5{ Lnterface
wxLb-
ÇxhÜÇ-
Figure 21. LVDS Serialized Link Termination
7.3.2 Phase Locked Loop (PLL)
The Channel Link I devices use an internal PLL to recover the clock transmitted across the LVDS interface. The
recovered clock is then used as a reference to determine the sampling position of the seven serial bits received
per clock cycle. The width of each bit in the serialized LVDS data stream is one-seventh the clock period.
Differential skew (Δt within one differential pair), interconnect skew (Δt of one differential pair to another), and
clock jitter will all reduce the available window for sampling the LVDS serial data streams. Individual bypassing of
each VCC to ground will minimize the noise passed on to the PLL, thus creating a low jitter LVDS clock to
improve the overall jitter budget.
7.3.3 Serial LVDS-to-Parallel LVCMOS Converter
After the PLL locks to the incoming LVDS clock, the receiver deserializes each LVDS differential data pair into
seven parallel LVCMOS data outputs per clock cycle. For the DS90CR286AT-Q1, the LVDS data inputs map to
LVCMOS outputs according to Figure 6.
7.3.4 LVCMOS Drivers
The LVCMOS outputs from the DS90CR286AT-Q1 are the deserialized single-ended data from the serialized
LVDS data pairs. Each LVCMOS output is clocked by the PLL and should be strobed on the RxCLKOUT rising
edge by the endpoint device. All unused DS90CR286AT-Q1 RxOUT outputs can be left floating.
7.4 Device Functional Modes
7.4.1 Power Down Mode
The DS90CR286AT-Q1 receiver may be placed into a power down mode at any time by asserting the PWR
DWN pin (active low). The DS90CR286AT-Q1 is also designed to protect from accidental loss of power to either
the transmitter or receiver. If power to the transmitter is lost, the receiver clocks (input and output) stop. The data
outputs (RxOUT) retain the states they were in when the clocks stopped. When the receiver loses power, the
receiver inputs are shorted to VCC through an internal diode. Current is limited to 5 mA per input, thus avoiding
the potential for latch-up when powering the device.
Copyright © 2015, Texas Instruments Incorporated
13
DS90CR286AT-Q1
ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DS90CR286AT-Q1 is designed for a wide variety of data transmission applications. The use of serialized
LVDS data lines in these applications allows for efficient signal transmission over a narrow bus width, thereby
reducing cost, power, and space. The DS90CR286AT-Q1 is designed for PCB board chip-to-chip OpenLDI-to-
RGB (LVDS-to-parallel) bridge conversion. LVDS data transmission over cable interconnect is not recommended
for this device. Users designing a sub-system with a compatible OpenLDI transmitter and DS90CR286AT-Q1
receiver must ensure an acceptable skew margin budget (RSKM).
8.2 Typical Application
ꢀ/. Çrꢁce
5{90/w286!Ç-v1 28-.it wx
24-.it wD. 5isplꢁy Ünit
wxhÜÇꢂ27:0]
[ë5{ 5ꢁtꢁ
Graphics Processor Unit (GPU)
28-Bit Tx Data
(4 LVDS Data, 1 LVDS Clock)
[ë5{ /lock
wx/[Y
PLL
Figure 22. Typical DS90CR286AT-Q1 Application Block Diagram
8.2.1 Design Requirements
For this design example, ensure that the following requirements are observed.
Table 1. DS90CR286AT-Q1 Design Parameters
DESIGN PARAMETER
Operating Frequency
Bit Resolution
DESIGN REQUIREMENTS
LVDS clock must be within 20-66 MHz.
No higher than 24 bpp. The maximum supported resolution is 8-bit RGB.
Determine the appropriate mapping required by the panel display following the
DS90CR286AT-Q1 outputs.
Bit Data Mapping
Ensure that there is acceptable margin between Tx pulse position and Rx
strobe position.
RSKM (Receiver Skew Margin)
100 Ω ± 10% resistor across each LVDS differential pair. Place as close as
possible to IC input pins.
Input Termination for RxIN±
RxIN± Board Trace Impedance
Design differential trace impedance with 100 Ω ± 5%.
If unused, leave pins floating. Series resistance on each LVCMOS output
optional to reduce reflections from long board traces. If used, 33 Ω series
resistance is typical.
LVCMOS Outputs
Use a 0.1 µF capacitor to minimize power supply noise. Place as close as
possible to Vcc pins.
DC Power Supply Coupling Capacitors
14
Copyright © 2015, Texas Instruments Incorporated
DS90CR286AT-Q1
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ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
8.2.2 Detailed Design Procedure
To begin the design process with the DS90CR286AT-Q1, determine the following:
•
•
•
•
Operating Frequency
Bit Resolution of the Panel
Bit Mapping from Receiver to Endpoint Panel Display
RSKM Interoperability with Transmitter Pulse Position Margin
8.2.2.1 Bit Resolution and Operating Frequency Compatibility
The bit resolution of the endpoint panel display reveals whether there are enough bits available in the
DS90CR286AT-Q1 to output the required data per pixel. The DS90CR286AT-Q1 has 28 parallel LVCMOS
outputs and can therefore provide a bit resolution up to 24 bpp (bits per pixel). In each clock cycle, the remaining
bits are the three control signals (HSync, VSync, DE) and one spare bit.
The number of pixels per frame and the refresh rate of the endpoint panel display indicate the required operating
frequency of the receiver clock. To determine the required clock frequency, refer to the following formula:
f_Clk = [H_Active + H_Blank] × [V_Active + V_Blank] × f_Vertical
where
•
•
•
•
•
•
H_Active = Active Display Horizontal Lines
H_Blank = Blanking Period Horizontal Lines
V_Active = Active Display Vertical Lines
V_Blank = Blanking Period Vertical Lines
f_Vertical = Refresh Rate (in Hz)
f_Clk = Operating Frequency of LVDS clock
(1)
In each frame, there is a blanking period associated with horizontal rows and vertical columns that are not
actively displayed on the panel. These blanking period pixels must be included to determine the required clock
frequency. Consider the following example to determine the required LVDS clock frequency:
•
•
•
•
•
H_Active = 640
H_Blank = 40
V_Active = 480
V_Blank = 41
f_Vertical = 59.95 Hz
Thus, the required operating frequency is determined below:
[640 + 40] x [480 + 41] x 59.95 = 21239086 Hz ≈ 21.24 MHz
(2)
Since the operating frequency for the PLL in the DS90CR286AT-Q1 ranges from 20-66 MHz, the
DS90CR286AT-Q1 can support a panel display with the aforementioned requirements.
If the specific blanking interval is unknown, the number of pixels in the blanking interval can be approximated to
20% of the active pixels. The following formula can be used as a conservative approximation for the operating
LVDS clock frequency:
f_Clk ≈ H_Active x V_Active x f_Vertical x 1.2
(3)
Using this approximation, the operating frequency for the example in this section is estimated below:
640 x 480 x 59.95 x 1.2 = 22099968 Hz ≈ 22.10 MHz
(4)
8.2.2.2 Data Mapping between Receiver and Endpoint Panel Display
Ensure that the LVCMOS outputs are mapped to align with the endpoint display RGB mapping requirements
following the deserializer. Two popular mapping topologies for 8-bit RGB data are shown below:
1. LSBs are mapped to RxIN3±.
2. MSBs are mapped to RxIN3±.
The following tables depict how these two popular topologies can be mapped to the DS90CR286AT-Q1 outputs.
Copyright © 2015, Texas Instruments Incorporated
15
DS90CR286AT-Q1
ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
www.ti.com.cn
Table 2. 8-Bit Color Mapping with LSBs on RxIN3±
LVDS INPUT
CHANNEL
LVDS BIT STREAM
POSITION
LVCMOS OUTPUT
CHANNEL
COLOR MAPPING
COMMENTS
TxIN0
TxIN1
RxOUT0
RxOUT1
RxOUT2
RxOUT3
RxOUT4
RxOUT6
RxOUT7
RxOUT8
RxOUT9
RxOUT12
RxOUT13
RxOUT14
RxOUT15
RxOUT18
RxOUT19
RxOUT20
RxOUT21
RxOUT22
RxOUT24
RxOUT25
RxOUT26
RxOUT27
RxOUT5
RxOUT10
RxOUT11
RxOUT16
RxOUT17
RxOUT23
R2
R3
TxIN2
R4
RxIN0
TxIN3
R5
TxIN4
R6
TxIN6
R7
MSB
MSB
TxIN7
G2
TxIN8
G3
TxIN9
G4
TxIN12
TxIN13
TxIN14
TxIN15
TxIN18
TxIN19
TxIN20
TxIN21
TxIN22
TxIN24
TxIN25
TxIN26
TxIN27
TxIN5
G5
RxIN1
G6
G7
B2
B3
B4
B5
B6
RxIN2
B7
MSB
Horizontal Sync
Vertical Sync
Data Enable
LSB
HSYNC
VSYNC
DE
R0
R1
TxIN10
TxIN11
TxIN16
TxIN17
TxIN23
G0
LSB
LSB
RxIN3
G1
B0
B1
GP
General Purpose
Table 3. 8-Bit Color Mapping with MSBs on RxIN3±
LVDS INPUT
CHANNEL
LVDS BIT STREAM
LVCMOS OUTPUT
CHANNEL
COLOR MAPPING
COMMENTS
POSITION
TxIN0
RxOUT0
RxOUT1
RxOUT2
RxOUT3
RxOUT4
RxOUT6
RxOUT7
RxOUT8
RxOUT9
RxOUT12
RxOUT13
RxOUT14
RxOUT15
RxOUT18
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
LSB
TxIN1
TxIN2
RxIN0
TxIN3
TxIN4
TxIN6
TxIN7
LSB
LSB
TxIN8
TxIN9
TxIN12
TxIN13
TxIN14
TxIN15
TxIN18
RxIN1
16
Copyright © 2015, Texas Instruments Incorporated
DS90CR286AT-Q1
www.ti.com.cn
ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
Table 3. 8-Bit Color Mapping with MSBs on RxIN3± (continued)
LVDS INPUT
CHANNEL
LVDS BIT STREAM
POSITION
LVCMOS OUTPUT
CHANNEL
COLOR MAPPING
COMMENTS
TxIN19
TxIN20
TxIN21
TxIN22
TxIN24
TxIN25
TxIN26
TxIN27
TxIN5
RxOUT19
RxOUT20
RxOUT21
RxOUT22
RxOUT24
RxOUT25
RxOUT26
RxOUT27
RxOUT5
B2
B3
B4
RxIN2
B5
HSYNC
VSYNC
DE
Horizontal Sync
Vertical Sync
Data Enable
R6
R7
MSB
MSB
TxIN10
TxIN11
TxIN16
TxIN17
TxIN23
RxOUT10
RxOUT11
RxOUT16
RxOUT17
RxOUT23
G6
RxIN3
G7
B6
B7
MSB
GP
General Purpose
In situations where the DS90CR286AT-Q1 must support 18 bpp, Table 2 is commonly used. With this mapping,
MSBs of RGB data are retained on RXIN0±, RXIN1±, and RXIN2± while the two LSBs for the original 8-bit RGB
resolution are ignored from RxIN3±.
8.2.2.3 RSKM Interoperability
One of the most important factors when designing the receiver into a system application is assessing how much
RSKM (Receiver Skew Margin) is available. In each LVDS clock cycle, the LVDS data stream carries seven
serialized data bits. Ideally, the Transmit Pulse Position for each bit will occur every (n x T)/7 seconds, where n =
Bit Position and T = LVDS Clock Period. Likewise, ideally the Receive Strobe Position for each bit will occur
every ((n + 0.5) x T)/7 seconds. However, due to the effects of clock jitter and ISI, both LVDS transmitter and
receiver in real systems will have a minimum and maximum pulse and strobe position, respectively, for each bit
position. This concept is illustrated in Figure 23:
wspos1
wspos0
max
min
max
min
Çppos0
.it 0 [eft aꢀrgin
.it 0 wight aꢀrgin
Çppos1
.it 1 [eft aꢀrgin
.it 1 wight aꢀrgin
Çppos2
Ldeal wx {trobe
ꢀosition
Ldeal wx {trobe
ꢀosition
max
max
min
min
max
min
.it0
.it1
Figure 23. RSKM Measurement Example
All left and right margins for Bits 0-6 must be considered in order to determine the absolute minimum for the
whole LVDS bit stream. This absolute minimum corresponds to the RSKM.
To improve RSKM performance between LVDS transmitter and receiver, designers may either advance or delay
the LVDS clock compared to the LVDS data. Moving the LVDS clock compared to the LVDS data can improve
the Rx strobe position compared to the Tx pulse position of the transmitter.
Copyright © 2015, Texas Instruments Incorporated
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DS90CR286AT-Q1
ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
www.ti.com.cn
If there is less left bit margin than right bit margin, the LVDS clock can be delayed so that the Rx strobe position
for incoming data appears to be delayed. If there is less right bit margin than left bit margin, all the LVDS data
pairs can be delayed uniformly so that the LVDS clock and Rx strobe position for incoming data appear to
advance. To delay an LVDS data or clock pair, designers can either add more PCB trace length or install a
capacitor between the LVDS transmitter and receiver. It is important to note that when using these techniques, all
serialized bit positions are shifted right or left uniformly.
When designing the DS90CR286AT-Q1 receiver with a third-party OpenLDI transmitter, users must calculate the
skew margin budget (RSKM) based on the Tx pulse position and the Rx strobe position to ensure error-free
transmission. For more information about calculating RSKM, refer to Application Note SNLA249.
8.2.3 Application Curves
The following application curves are examples taken with a DS90C385 serializer interfacing to a DS90CR286AT-
Q1 deserializer in nominal temperature (25ºC) at an operating frequency of 66 MHz.
ÇxLb7
ÇxLb6
ÇxLb4
ÇxLb3
ÇxLb2
ÇxLb1
ÇxLb0
Çime (ꢁ.0 nsꢀ5Lë)
Çime (2.ꢂ nsꢀ5Lë)
Figure 25. LVDS CLKIN aligned with LVCMOS RxCLKOUT
Figure 24. LVDS RxIN0± aligned with LVCMOS RxCLKOUT
Çime (ꢁ.0 nsꢀ5Lë)
Çime (20.0 nsꢀ5Lë)
Figure 26. RxOUT and RxCLKOUT Timing Diagram
Figure 27. PRBS-7 Output on RxOUT Channels
18
Copyright © 2015, Texas Instruments Incorporated
DS90CR286AT-Q1
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ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
9 Power Supply Recommendations
Proper power supply decoupling is important to ensure a stable power supply with minimal power supply noise.
Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a
conservative approach, three parallel-connected decoupling capacitors (Multi-Layered Ceramic type in surface
mount form factor) between each VCC and the ground plane(s) are recommended. The three capacitor values are
0.1 μF, 0.01 μF and 0.001 μF. The preferred capacitor size is 0402. An example is shown in Figure 28. The
designer should place bypass capacitors as close as possible to the VCC pins and ensure each capacitor has its
own via to connect the ground plane. If board space is limiting the number of bypass capacitors, the PLL VCC
should receive the most filtering or bypassing. Next would be the LVDS VCC pins and finally the logic VCC pins.
Figure 28. Recommended Bypass Capacitor Decoupling Configuration
10 Layout
10.1 Layout Guidelines
As with any high speed design, board designers must maximize signal integrity by limiting reflections and
crosstalk that can adversely affect high frequency and EMI performance. The following practices are
recommended layout guidelines to optimize device performance.
•
Ensure that differential pair traces are always closely coupled to eliminate noise interference from other
signals and take full advantage of the common mode noise canceling effect of the differential signals.
•
•
•
•
Maintain equal length on signal traces for a given differential pair.
Limit impedance discontinuities by reducing the number of vias on signal traces.
Eliminate any 90º angles on traces and use 45º bends instead.
If a via must exist on one signal polarity, mirror the via implementation on the other polarity of the differential
pair.
•
•
Match the differential impedance of the selected physical media. This impedance should also match the value
of the termination resistor that is connected across the differential pair at the receiver's input.
When possible, use short traces for LVDS inputs.
10.2 Layout Example
The following images show an example layout of the DS90CR286AT-Q1. Traces in blue correspond to the top
layer and the traces in green correspond to the bottom layer. Note that differential pair inputs to the
DS90CR286AT-Q1 are tightly coupled and close to the connector pins. In addition, observe that the power
supply decoupling capacitors are placed as close as possible to the power supply pins with through vias in order
to minimize inductance.
Copyright © 2015, Texas Instruments Incorporated
19
DS90CR286AT-Q1
ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
www.ti.com.cn
Layout Example (continued)
Figure 29. Example Layout with DS90CR286AT-Q1 (U1).
100-Q [ë5{
Çerminations close to
wxLb pins
33 Q {ꢀŒ]ꢀ• wꢀ•]•š}Œ•
occasionally used to
reduce reflections
Figure 30. Example Layout Close-up.
20
版权 © 2015, Texas Instruments Incorporated
DS90CR286AT-Q1
www.ti.com.cn
ZHCSET3A –NOVEMBER 2015–REVISED DECEMBER 2015
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
应用报告《IC 封装热指标》，SPRA953
《如何计算和提高 Channel Link I 器件的接收器偏差裕度》应用笔记，SNLA249
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。要获得这份数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90CR286ATDGGQ1
DS90CR286ATDGGRQ1
ACTIVE
TSSOP
TSSOP
DGG
56
56
34
RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
DS90CR286ATQ
DGG
ACTIVE
DGG
2000 RoHS & Green
SN
DS90CR286ATQ
DGG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90CR286ATDGGRQ1 TSSOP
DGG
56
2000
330.0
24.4
8.6
14.5
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 56
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
DS90CR286ATDGGRQ1
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
DGG TSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DS90CR286ATDGGQ1
56
34
495
10
2540
5.79
Pack Materials-Page 3
PACKAGE OUTLINE
DGG0056A
TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
2
0
0
SMALL OUTLINE PACKAGE
C
8.3
7.9
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
54X 0.5
56
1
14.1
13.9
NOTE 3
2X
13.5
28
B
29
0.27
0.17
6.2
6.0
56X
1.2 MAX
0.08
C A
B
(0.15) TYP
0.25
GAGE PLANE
0 - 8
SEE DETAIL A
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4222167/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05)
TYP
SYMM
28
29
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222167/A 07/2015
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05) TYP
SYMM
28
29
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4222167/A 07/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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