DS90CR483 [TI]
48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz;
| 型号： | DS90CR483 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz |
| 文件： | 总27页 (文件大小：1634K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90CR483, DS90CR484
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SNLS047H –FEBRUARY 2000–REVISED APRIL 2013
DS90CR483 / DS90CR484 48-Bit LVDS Channel Link SER/DES — 33 - 112 MHz
Check for Samples: DS90CR483, DS90CR484
1
FEATURES
DESCRIPTION
The DS90CR483 transmitter converts 48 bits of
CMOS/TTL data into eight LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a ninth LVDS link. Every cycle of the
transmit clock 48 bits of input data are sampled and
transmitted. The DS90CR484 receiver converts the
LVDS data streams back into 48 bits of CMOS/TTL
data. At a transmit clock frequency of 112MHz, 48
bits of TTL data are transmitted at a rate of 672Mbps
per LVDS data channel. Using a 112MHz clock, the
data throughput is 5.38Gbit/s (672Mbytes/s).
2
•
Up to 5.38 Gbits/sec Bandwidth
•
•
33 MHz to 112 MHz Input Clock Support
LVDS SER/DES Reduces Cable and connector
Size
•
•
Pre-Emphasis Reduces Cable Loading Effects
DC Balance Data Transmission Provided by
Transmitter Reduces ISI Distortion
•
Cable Deskew of +/−1 LVDS Data Bit Time (up
to 80 MHz Clock Rate)
•
•
•
•
•
5V Tolerant TxIN and Control Input Pins
Flow Through Pinout for Easy PCB Design
+3.3V Supply Voltage
The multiplexing of data lines provides a substantial
cable reduction. Long distance parallel single-ended
buses typically require a ground wire per active signal
(and have very limited noise rejection capability).
Thus, for a 48-bit wide data and one clock, up to 98
conductors are required. With this Channel Link
chipset as few as 19 conductors (8 data pairs, 1 clock
pair and a minimum of one ground) are needed. This
provides an 80% reduction in cable width, which
provides a system cost savings, reduces connector
physical size and cost, and reduces shielding
requirements due to the cables' smaller form factor.
Transmitter Rejects Cycle-to-Cycle Jitter
Conforms to ANSI/TIA/EIA-644-1995 LVDS
Standard
•
Both Devices are Available in 100 Lead TQFP
Package
The 48 CMOS/TTL inputs can support a variety of
signal combinations. For example, 6 8-bit words or 5
9-bit (byte + parity) and 3 controls.
The DS90CR483/DS90CR484 chipset is improved
over prior generations of Channel Link devices and
offers higher bandwidth support and longer cable
drive with three areas of enhancement. To increase
bandwidth, the maximum clock rate is increased to
112 MHz and
8 serialized LVDS outputs are
provided. Cable drive is enhanced with a user
selectable pre-emphasis feature that provides
additional output current during transitions to
counteract cable loading effects. Optional DC
balancing on a cycle-to-cycle basis, is also provided
to reduce ISI (Inter-Symbol Interference). With pre-
emphasis and DC balancing, a low distortion eye-
pattern is provided at the receiver end of the cable. A
cable deskew capability has been added to deskew
long cables of pair-to-pair skew of up to +/−1 LVDS
data bit time (up to 80 MHz Clock Rate). These three
enhancements allow cables 5+ meters in length to be
driven.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
DS90CR483, DS90CR484
SNLS047H –FEBRUARY 2000–REVISED APRIL 2013
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DESCRIPTION (CONTINUED)
The chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL
interfaces.
For more details, please refer to the APPLICATIONS INFORMATION section of this datasheet.
Generalized Block Diagrams
Generalized Transmitter Block Diagram
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Generalized Receiver Block Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to +5.5V
−0.3V to (VCC + 0.3V)
−0.3V to +3.6V
−0.3V to +3.6V
Continuous
CMOS/TTL Input Voltage
LVCMOS/TTL Output Voltage
LVDS Receiver Input Voltage
LVDS Driver Output Voltage
LVDS Output Short Circuit Duration
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
+260°C
Lead Temperature (Soldering, 4 sec.)
100L TQFP
DS90CR483VJD
DS90CR484VJD
DS90CR483VJD
DS90CR484VJD
DS90CR483
2.3W
Maximum Package Power Dissipation Capacity @
25°C
100 TQFP Package
2.3W
18.1mW/°C above +25°C
18.1mW/°C above +25°C
Package Derating
ESD Rating
(HBM, 1.5kΩ, 100pF)
(EIAJ, 0Ω, 200pF)
DS90CR484
> 6 kV
> 300 V
(HBM, 1.5kΩ, 100pF)
(EIAJ, 0Ω, 200pF)
> 2 kV
> 200 V
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the device should be operated at these limits. “Electrical Characteristics” specify conditions for device operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Recommended Operating Conditions
Min
3.0
−10
0
Nom
3.3
Max
3.6
Units
V
Supply Voltage (VCC
)
Operating Free Air Temperature (TA)
Receiver Input Range
+25
+70
2.4
°C
V
Supply Noise Voltage
100
mVp-p
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Recommended Operating Conditions (continued)
Min
Nom
Max
Units
Input Clock (TX)
33
112
MHz
Electrical Characteristics(1)(2)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
2.0
GND
2.7
V
V
0.8
VOH
IOH = −0.4 mA
IOH = −2mA
IOL = 2 mA
3.3
2.85
0.1
V
High Level Output Voltage
2.7
V
VOL
VCL
IIN
Low Level Output Voltage
Input Clamp Voltage
0.3
−1.5
+15
V
ICL = −18 mA
−0.79
+1.8
0
V
VIN = 0.4V, 2.5V or VCC
VIN = GND
µA
µA
mA
Input Current
−15
IOS
Output Short Circuit Current
VOUT = 0V
−120
LVDS DRIVER DC SPECIFICATIONS
|VOD
|
Differential Output Voltage
250
345
450
35
mV
mV
ΔVOD
Change in VOD between
Complimentary Output States
RL = 100Ω
VOS
Offset Voltage
1.125
1.25
1.375
35
V
ΔVOS
Change in VOS between
mV
Complimentary Output States
IOS
IOZ
Output Short Circuit Current
Output TRI-STATE Current
VOUT = 0V, RL = 100Ω
−3.5
−5
mA
µA
PD = 0V, VOUT = 0V or VCC
±1
±10
LVDS RECEIVER DC SPECIFICATIONS
VTH
VTL
IIN
Differential Input High
Threshold
+100
mV
mV
VCM = +1.2V
Differential Input Low
Threshold
−100
Input Current
VIN = +2.4V, VCC = 3.6V
VIN = 0V, VCC = 3.6V
±10
±10
µA
µA
TRANSMITTER SUPPLY CURRENT
ICCTW
ICCTZ
Transmitter Supply Current
Worst Case
RL = 100Ω, CL = 5 pF,
BAL = High,
Worst Case Pattern
(Figure 1 Figure 2)
f = 33 MHz
f = 66 MHz
f = 112 MHz
91.4
106
155
5
140
160
210
50
mA
mA
mA
µA
Transmitter Supply Current
Power Down
PD = Low
Driver Outputs in TRI-STATE during power down Mode
RECEIVER SUPPLY CURRENT
ICCRW
f = 33 MHz
125
200
250
20
150
210
280
100
mA
mA
mA
µA
CL = 8 pF, BAL = High,
Worst Case Pattern
(Figure 1 Figure 3)
Receiver Supply Current
Worst Case
f = 66 MHz
f = 112 MHz
ICCRZ
Receiver Supply Current
Power Down
PD = Low
Receiver Outputs stay low during power down mode.
(1) Typical values are given for VCC = 3.3V and T A = +25°C.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VTH, VTL, VOD and ΔVOD).
4
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Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
TCIT
Parameter
TxCLK IN Transition Time (Figure 4)
TxCLK IN Period (Figure 5)
TxCLK in High Time (Figure 5)
TxCLK in Low Time (Figure 5)
TxIN Transition Time
Min
1.0
Typ
2.0
Max
3.0
Units
ns
TCIP
TCIH
TCIL
TXIT
8.928
0.35T
0.35T
1.5
T
30.3
0.65T
0.65T
6.0
ns
0.5T
0.5T
ns
ns
ns
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Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
LLHT
Parameter
Min
Typ
Max
Units
LVDS Low-to-High Transition Time (Figure 2), PRE =
0.75V (disabled)
0.14
0.7
ns
LVDS Low-to-High Transition Time (Figure 2), PRE = Vcc
(max)
0.11
0.16
0.11
0.6
0.8
0.7
ns
ns
ns
LHLT
LVDS High-to-Low Transition Time (Figure 2), PRE =
0.75V (disabled)
LVDS High-to-Low Transition Time (Figure 2), PRE = Vcc
(max)
TBIT
Transmitter Bit Width
1/7 TCIP
ns
ps
ps
ps
ps
ns
ns
ns
ms
ns
TPPOS
f = 33 to 70 MHz
f = 70 to 112 MHz
−250
−200
0
0
+250
+200
100
Transmitter Pulse Positions -
Normalized
TJCC
TCCS
TSTC
THTC
TPDL
TPLLS
TPDD
Transmitter Jitter - Cycle-to-Cycle(1)
TxOUT Channel to Channel Skew
TxIN Setup to TxCLK IN, (Figure 5)
TxIN Hold to TxCLK IN, (Figure 5)
50
40
2.5
0
Transmitter Propagation Delay - Latency, (Figure 7)
Transmitter Phase Lock Loop Set, (Figure 9)
Transmitter Powerdown Delay, (Figure 11)
1.5(TCIP)+3.72
1.5(TCIP)+4.4
1.5(TCIP)+6.24
10
100
(1) TJCC is a function of input clock quality and also PLLVCC noise. At 112MHz operation, with a +/−300ps input impulse at a 2us rate,
TJCC has been measured to be in the 70-80ps range (<100ps). With a nominal input clock quality (no input impulse jitter, jitter <
500kHz), TJCC is typically 50ps or less. For RSKM/RSKMD calculations 100ps is typically used as the TJCC budget. See Clock Jitter
discussion in the APPLICATIONS INFORMATION section of this datasheet for further information.
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Units
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 3), Rx
data out
2.0
ns
CMOS/TTL Low-to-High Transition Time (Figure 3), Rx
clock out
1.0
2.0
ns
ns
ns
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 3), Rx
data out
CMOS/TTL High-to-Low Transition Time (Figure 3), Rx
clock out
1.0
RCOP
RCOH
RxCLK OUT Period, (Figure 6)
8.928
T
30.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
f = 112 MHz
RxCLK OUT High Time, (Figure 6)(1)
f = 66 MHz
3.5
6.0
RCOL
RSRC
RHRC
f = 112 MHz
RxCLK OUT Low Time, (Figure 6)(1)
f = 66 MHz
3.5
6.0
2.4
f = 112 MHz
f = 66 MHz
f = 112 MHz
f = 66 MHz
RxOUT Setup to RxCLK OUT
(Figure 6)(1)
3.6
3.4
RxOUT Hold to RxCLK OUT
(Figure 6)(1)
7.0
RPDL
RPLLS
RPDD
Receiver Propagation Delay - Latency, (Figure 8)
Receiver Phase Lock Loop Set, (Figure 10)
Receiver Powerdown Delay, (Figure 12)
3(TCIP)+4.0
3(TCIP)+4.8
3(TCIP)+6.5
10
1
(1) The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges.
This parameter is functionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts
have been bench tested to verify functional performance.
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Chipset RSKM Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified(1)(2). See APPLICATIONS
INFORMATION section for more details on this parameter and how to apply it.
Symbol
Parameter
Min
170
170
300
300
170
170
250
250
300
Typ
Max
Units
ps
RSKM
f = 112 MHz
f = 100 MHz
f = 85MHz
f = 66MHz
f = 112 MHz
f = 100 MHz
f = 85 MHz
f = 66 MHz
f = 50MHz
240
350
350
ps
Receiver Skew Margin without Deskew
in non-DC Balance Mode, (Figure 13)(3)
ps
ps
RSKM
ps
200
300
300
350
ps
Receiver Skew Margin without Deskew
in DC Balance Mode, (Figure 13)(3)
ps
ps
ps
RSKMD
Receiver Skew Margin with Deskew in
DC Balance, (Figure 14)(4)
f = 33 to 80 MHz
0.25TBIT
± 1
ps
RDR
Receiver Deskew Range
f = 80 MHz
f = 80 MHz
TBIT
ns
RDSS
Receiver Deskew Step Size
0.3 TBIT
(1) The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges.
This parameter is functionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts
have been bench tested to verify functional performance.
(2) Typical values for RSKM and RSKMD are applicable for fixed VCC and T A for the Transmitter and Receiver (both are assumed to be at
the same VCC and T A points).
(3) Receiver Skew Margin (RSKM) is defined as the valid data sampling region at the receiver inputs. This margin takes into account
transmitter output pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS).
This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable) and clock
jitter.RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle, TJCC) + ISI (if any). See APPLICATIONS INFORMATION
section for more details.
(4) Receiver Skew Margin with Deskew (RSKMD) is defined as the valid data sampling region at the receiver inputs. The DESKEW function
will constrain the receiver’s sampling strobes to the middle half of the LVDS bit and removes (adjusts for) fixed interconnect skew. This
margin (RSKMD) allows for inter-symbol interference (dependent on type/length of cable), Transmitter Pulse Position (TPPOS) variance,
and LVDS clock jitter (TJCC).RSKMD ≥ ISI + TPPOS(variance) + source clock jitter (cycle to cycle). See APPLICATIONS
INFORMATION section for more details.
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AC Timing Diagrams
The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Figure 1. “Worst Case” Test Pattern
Figure 2. DS90CR483 (Transmitter) LVDS Output Load and Transition Times
Figure 3. DS90CR484 (Receiver) CMOS/TTL Output Load and Transition Times
Figure 4. DS90CR483 (Transmitter) Input Clock Transition Time
Figure 5. DS90CR483 (Transmitter) Setup/Hold and High/Low Times
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Figure 6. DS90CR484 (Receiver) Setup/Hold and High/Low Times
Figure 7. DS90CR483 (Transmitter) Propagation Delay - Latency
Figure 8. DS90CR484 (Receiver) Propagation Delay - Latency
Figure 9. DS90CR483 (Transmitter) Phase Lock Loop Set Time
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Figure 10. DS90CR484 (Receiver) Phase Lock Loop Set Time
Figure 11. DS90CR483 (Transmitter) Power Down Delay
Figure 12. DS90CR484 (Receiver) Power Down Delay
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C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
TPPOS — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + LVDS Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
Cable Skew — typically 10 ps to 40 ps per foot, media dependent
TJCC — Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
ISI is dependent on interconnect length; may be zero
See APPLICATIONS INFORMATION section for more details.
Figure 13. Receiver Skew Margin (RSKM) without DESKEW
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
RSKMD ≥ TPPOSvariance (d) + TJCC (output jitter)(f) + ISI (m)
d = Tppos — Transmitter output pulse position (min and max)
f = TJCC — Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
m = extra margin - assigned to ISI in long cable applications
See APPLICATIONS INFORMATION section for more details.
Figure 14. Receiver Skew Margin (RSKMD)with DESKEW
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LVDS Interface
Optional features supported: Pre-emphasis, and Deskew
Figure 15. 48 Parallel TTL Data Bits Mapped to LVDS Outputs with DC Balance Enabled
Optional feature supported: Pre-emphasis
Figure 16. 48 Parallel TTL Data Bits Mapped to LVDS Outputs with DC Balance Disabled
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APPLICATIONS INFORMATION
The DS90CR483/DS90CR484 chipset is improved over prior generations of Channel Link devices and offers
higher bandwidth support and longer cable drive with three areas of enhancement. To increase bandwidth, the
maximum clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided. Cable drive is
enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to
counteract cable loading effects. This requires the use of one pull up resistor to Vcc; please refer to Table 1 to
set the level needed. Optional DC balancing on a cycle-to-cycle basis, is also provided to reduce ISI (Inter-
Symbol Interference). With pre-emphasis and DC balancing, a low distortion eye-pattern is provided at the
receiver end of the cable. A cable deskew capability has been added to deskew long cables of pair-to-pair skew
of up to ±1 LVDS data bit time (up to 80 MHz clock rates). For details on deskew, refer to “Deskew” section
below. These three enhancements allow cables 5+ meters in length to be driven depending upon media and
clock rate.
The DS90CR483/484 chipset may also be used in a non-DC Balance mode. In this mode pre-emphasis is
supported. In this mode, the chipset is also compatible with 21 and 28-bit Channel Link Receivers. See Figure 16
for the LVDS mapping.
New features Description:
1. Pre-emphasis: Adds extra current during LVDS logic transition to reduce the cable loading effects. Pre-
emphasis strength is set via a DC voltage level applied from min to max (0.75V to Vcc) at the “PRE” pin. A
higher input voltage on the ”PRE” pin increases the magnitude of dynamic current during data transition. The
“PRE” pin requires one pull-up resistor (Rpre) to Vcc in order to set the DC level. There is an internal resistor
network, which cause a voltage drop. Please refer to the tables below to set the voltage level.
The waveshape at the Receiver input should not exhibit over or undershoot with the proper amount of pre-
emphasis set. Too much pre-emphasis generates excess noise and increases power dissipation. Cables less
than 2 meters in length typically do not require pre-emphasis.
Table 1. Pre-emphasis DC voltage level with (Rpre)
Rpre
1MΩ or NC
50kΩ
Resulting PRE Voltage
Effect
0.75V
1.0V
1.5V
2.0V
2.6V
Vcc
Standard LVDS
9kΩ
50% pre-emphasis
100% pre-emphasis
3kΩ
1kΩ
100Ω
Table 2. Pre-emphasis needed per cable length
Frequency
112MHz
112MHz
80MHz
PRE Voltage
1.0V
Typical cable length
2 meters
1.5V
5 meters
1.0V
2 meters
80MHz
1.2V
5+ meters
66MHz
1.5V
7 meters
2. DC Balance: In addition to data information an additional bit is transmitted on every LVDS data signal line
during each cycle as shown in Figure 15. This bit is the DC balance bit (DCBAL). The purpose of the DC
Balance bit is to minimize the short- and long-term DC bias on the signal lines. This is achieved by selectively
sending the data either unmodified or inverted.
The value of the DC balance bit is calculated from the running word disparity and the data disparity of the current
word to be sent. The data disparity of the current word shall be calculated by subtracting the number of bits of
value 0 from the number of bits value 1 in the current word. Initially, the running word disparity may be any value
between +7 and −6. The running word disparity shall be calculated as a continuous sum of all the modified data
disparity values, where the unmodified data disparity value is the calculated data disparity minus 1 if the data is
sent unmodified and 1 plus the inverse of the calculated data disparity if the data is sent inverted. The value of
the running word disparity shall saturate at +7 and −6.
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The value of the DC balance bit (DCBAL) shall be 0 when the data is sent unmodified and 1 when the data is
sent inverted. To determine whether to send data unmodified or inverted, the running word disparity and the
current data disparity are used. If the running word disparity is positive and the current data disparity is positive,
the data shall be sent inverted. If the running word disparity is positive and the current data disparity is zero or
negative, the data shall be sent unmodified. If the running word disparity is negative and the current data
disparity is positive, the data shall be sent unmodified. If the running word disparity is negative and the current
data disparity is zero or negative, the data shall be sent inverted. If the running word disparity is zero, the data
shall be sent inverted.
DC Balance mode is set when the BAL pin on the transmitter is tied HIGH - see . DC Balancing is useful on long
cable applications which are typically greater than 5 meters in length.
3. Deskew:
Deskew is supported in the DC Balance mode only (BAL = high on DS90CR483). The “DESKEW” pin on the
receiver when set high will deskew a minimum of ±1 LVDS data bit time skew from the ideal strobe location
between signals arriving on independent differential pairs (pair-to-pair skew). It is required that the “DS_OPT” pin
on the Transmitter must be applied low for a minimum of four clock cycles to complete the deskew operation. It is
also required that this must be performed at least once at any time after the PLLs have locked to the input clock
frequency. If power is lost, or if the cable has been switched, this procedure must be repeated or else the
receiver may not sample the incoming LVDS data correctly. When the receiver is in the deskew mode, all
receiver data outputs are set to a LOW state, but the receiver clock output is still active and switching. Setting
the “DESKEW” pin to low will disable the deskew operation and allow the receiver to operation on a fixed data
sampling strobe. In this case, the ”DS_OPT” pin on the transmitter must then be set high.
The DS_OPT pin at the input of the transmitter (DS90CR483) is used to initiate the deskew calibration pattern. It
must be applied low for a minimum of four clock cycles in order for the receiver to complete the deskew
operation. For this reason, the LVDS clock signal with DS_OPT applied high (active data sampling) shall be
1111000 or 1110000 pattern. During the deskew operation with DS_OPT applied low, the LVDS clock signal
shall be 1111100 or 1100000 pattern. The transmitter will also output a series of 1111000 or 1110000 onto the
LVDS data lines (TxOUT 0-7) during deskew so that the receiver can automatically calibrated the data sampling
strobes at the receiver inputs. Each data channel is deskewed independently and is tuned with a step size of 1/3
of a bit time over a range of +/−1 TBIT from the ideal strobe location. The Deskew feature operates up to clock
rates of 80 MHz only. If the Receiver is enabled in the deskew mode, then it must be trained before data transfer.
Clock Jitter:
The transmitter is designed to reject cycle-to-cycle jitter which may be seen at the transmitter input clock. Very
low cycle-to-cycle jitter is passed on to the transmitter outputs. Cycle-to-cycle jitter has been measured over
frequency to be less than 100 ps with input step function jitter applied. This should be subtracted from the
RSKM/RSKMD budget as shown and described in Figure 13 and Figure 14. This rejection capability significantly
reduces the impact of jitter at the TXinput clock pin, and improves the accuracy of data sampling in the receiver.
Transmitter output jitter is effected by PLLVCC noise and input clock jitter - minimize supply noise and use a low
jitter clock source to limit output jitter. The falling edge of the input clock to the transmitter is the critical edge and
is used by the PLL circuit.
RSKM - Receiver Skew Margin
RSKM is a chipset parameter and is explained in AN-1059 in detail. It is the difference between the transmitter’s
pulse position and the receiver’s strobe window. RSKM must be greater than the summation of: Interconnect
skew, LVDS Source Clock Jitter (TJCC), and ISI (if any). See Figure 13. Interconnect skew includes PCB traces
differences, connector skew and cable skew for a cable application. PCB trace and connector skew can be
compensated for in the design of the system. Cable skew is media type and length dependant.
14
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RSKMD - Receiver Skew Margin with DESKEW
RSKMD is a chipset parameter and is applicable when the DESKEW feature of the DS90CR484 is employed. It
is the difference between the receiver’s strobe window and the ideal pulse locations. The DESKEW feature
adjusts for skew between each data channel and the clock channel. This feature is supported up to 80 MHz clock
rate. RSKMD must be greater than the summation of: Transmitter’s Pulse Position variance, LVDS Source Clock
Jitter (TJCC), and ISI (if any). See Figure 14. With Deskew, RSKMD is ≥ 25% of TBIT. Deskew compensates for
interconnect skew which includes PCB traces differences, connector skew and cable skew (for a cable
application). PCB trace and connector skew can be compensated for in the design of the system. Note, cable
skew is media type and length dependant. Cable length may be limited by the RSKMD parameter prior to the
interconnect skew reaching 1 TBIT in length due to ISI effects.
Power Down:
Both transmitter and receiver provide a power down feature. When asserted current draw through the supply pins
is minimized and the PLLs are shut down. The transmitter outputs are in TRI-STATE when in power down mode.
The receiver outputs are forced to a active LOW state when in the power down mode. (See and tables). The PD
pin should be driven HIGH to enable the device once VCC is stable.
Configurations:
The transmitter is designed to be connected typically to a single receiver load. This is known as a point-to-point
configuration. It is also possible to drive multiple receiver loads if certain restrictions are made. Only the final
receiver at the end of the interconnect should provide termination across the pair. In this case, the driver still
sees the intended DC load of 100 Ohms. Receivers connected to the cable between the transmitter and the final
receiver must not load down the signal. To meet this system requirement, stub lengths from the line to the
receiver inputs must be kept very short.
Cable Termination
A termination resistor is required for proper operation to be obtained. The termination resistor should be equal to
the differential impedance of the media being driven. This should be in the range of 90 to 132 Ohms. 100 Ohms
is a typical value common used with standard 100 Ohm twisted pair cables. This resistor is required for control of
reflections and also to complete the current loop. It should be placed as close to the receiver inputs to minimize
the stub length from the resistor to the receiver input pins.
How to configure for backplane applications:
In a backplane application with differential line impedance of 100Ω the differential line pair-to-pair skew can
controlled by trace layout. The transmitter-DS90CR483 “DS_OPT” pin may be set high. In a backplane
application with short PCB distance traces, pre-emphasis from the transmitter is typically not required. The “PRE”
pin should be left open (do not tie to ground). A resistor pad provision for a pull up resistor to Vcc can be
implemented in case pre-emphasis is needed to counteract heavy capacitive loading effects.
How to configure for cable interconnect applications:
In applications that require the long cable drive capability. The DS90CR483/DS90CR484 chipset is improved
over prior generations of Channel Link devices and offers higher bandwidth support and longer cable drive with
the use of DC balanced data transmission, pre-emphasis. Cable drive is enhanced with a user selectable pre-
emphasis feature that provides additional output current during transitions to counteract cable loading effects.
This requires the use of one pull up resistor to Vcc; please refer to Table 1 to set the level needed. Optional DC
balancing on a cycle-to-cycle basis, is also provided to reduce ISI (Inter-Symbol Interference) for long cable
applications. With pre-emphasis and DC balancing, a low distortion eye-pattern is provided at the receiver end of
the cable. These enhancements allow cables 5+ meters in length to be driven. Depending upon clock rate and
the media being driven, the cable Deskew feature may also be employed - see discussion on DESKEW, RSKM
and RSKMD above.
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Supply Bypass Recommendations:
Bypass capacitors must be used on the power supply pins. Different pins supply different portions of the circuit,
therefore capacitors should be nearby all power supply pins except as noted in the and tables. Use high
frequency ceramic (surface mount recommended) 0.1µF capacitors close to each supply pin. If space allows, a
0.01µF capacitor should be used in parallel, with the smallest value closest to the device pin. Additional scattered
capacitors over the printed circuit board will improve decoupling. Multiple (large) via should be used to connect
the decoupling capacitors to the power plane. A 4.7 to 10 µF bulk cap is recommended near the PLLVCC pins
and also the LVDSVCC (pin #40) on the Transmitter. Connections between the caps and the pin should use wide
traces.
Input Signal Quality Requirements - Transmitter:
The input signal quality must comply to the datasheet requirements, please refer to the Recommended
Transmitter Input Characteristics table for specifications. In addition undershoots in excess of the ABS MAX
specifications are not recommended. If the line between the host device and the transmitter is long and acts as a
transmission line, then termination should be employed. If the transmitter is being driven from a device with
programmable drive strengths, data inputs are recommended to be set to a weak setting to prevent transmission
line effects. The clock signal is typically set higher to provide a clean edge that is also low jitter.
Unused LVDS Outputs:
Unused LVDS output channels should be terminated with 100 Ohm at the transmitter’s output pin.
Receiver output drive strength:
The DS90CR484 output specify a 8pF load, VOH and VOL are tested at ± 2mA, which is intended for only 1 or
maybe 2 loads. If high fan-out is required or long transmission line driving capability, buffering the receiver output
is recommended. Receiver outputs do not support / provide a TRI-STATE function.
LVDS Interconnect Guidelines:
See AN-1108 and AN-905 for full details.
•
•
Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
–
–
–
S = space between the pair
2S = space between pairs
3S = space to TTL signal
•
•
•
•
•
•
Minimize the number of VIA
Use differential connectors when operating above 500Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Minimize skew between pairs
Terminate as close to the RXinputs as possible
DS90CR481/482 and PLLSEL Function
The DS90CR481/2 chipset is electrically similar to the DS90CR483/4. The DS90CR481/2 differ only in the
control circuit of the internal PLL and are specified for 65 to 112 MHz operation. The devices will directly inter-
operate within the scope of the respective datasheets. The DS90CR483/4 supports a wide operating range from
33 to 112 MHz. The PLLSEL pin is used to select an auto-range feature. It shifts between the two ranges (High
and Low) in the 55 to 68 MHz range. For operation in the 65 to 70 MHz range, the DS90CR481/2 is
recommended as it will select High gear only and offer more margin to the system.
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For more information:
Channel Link Applications Notes currently available:
•
•
•
•
•
AN-1041 Introduction to Channel Link
AN-1059 RSKM Calculations
AN-1108 PCB and Interconnect Guidelines
AN-905 Differential Impedance
LVDS Owner’s Manual
Typical Data Rate vs Cable Length Curve
1000
100
10
V
=3.3V, Pre=100%
CC
V
CC
=3.3V, Pre=0%
1 2 3 4 5 6 7 10 1112131415161718
CABLE LENGTH (m)
DATA RATE VS CABLE LENGTH TEST PROCEDURE
The Data Rate vs Cable Length graph was generated using CLINK3V48BT-112 Evaluation Kit and 3M’s Mini D
Ribbon (MDR) Cable under typical conditions (Vcc = 3.3V, Temp = +25°C). A Tektronix MB100 Bit-Error-Rate
Tester (BERT) was used to send a PRBS (215) pattern to 32 of the 48 input channels on the transmitter
(DS90CR483). The BERT was also used to monitor the corresponding 32 receiver (DS90CR484) output
channels for bit errors. The frequency of the input signal were increased until bit errors were reported on the
BERT. The frequency on the graph is the highest frequency without error.
Results:
The DS90CR483/4 link was error free at 100MHz over 10 meters of 3M cable using pre-emphasis and DC
balance mode off.
DS90CR483 PIN DESCRIPTION—Channel Link Transmitter
Pin Name
I/O
Description
TxIN
I
TTL level input(1)
TxOUTP
TxOUTM
TxCLKIN
TxCLKP
TxCLKM
PD
O
O
I
Positive LVDS differential data output.
Negative LVDS differential data output.
TTL level clock input. The rising edge acts as data strobe.
Positive LVDS differential clock output.
O
O
I
Negative LVDS differential clock output.
TTL level input. Assertion (low input) tri-states the outputs, ensuring low current at power down(1)
PLLSEL
PLL range select. This pin should be tied to VCC for auto-range. Tied to ground or NC will force the
PLL to low range only. Typical shift point is between 55 and 68 MHz for auto-range.(1)(2)
I
(1) Inputs default to “low” when left open due to internal pull-down resistor.
(2) The PLL range shift point is in the 55 - 68 MHz range, typically the shift will occur during the lock time. For 65-70 MHz applications, the
DS90CR481/2 is recommended since its shift point is below its operation range. See Applications Information section.
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DS90CR483 PIN DESCRIPTION—Channel Link Transmitter (continued)
Pin Name
I/O
Description
PRE
Pre-emphasis “level” select. Pre-emphasis is active when input is tied to VCC through external pull-
up resistor. Resistor value determines Pre-emphasis level (See APPLICATIONS INFORMATION
Section). For normal LVDS drive level (No Pre-emphasis) leave this pin open (do not tie to
ground).
I
DS_OPT
BAL
Cable Deskew performed when TTL level input is low. No TxIN data is sampled during Deskew.
To perform Deskew function, input must be held low for a minimum of 4 clock cycles. The Deskew
operation is normally conducted after the TX and RX PLLs have locked. It should also be
conducted after a system reset, or a reconfiguration event. It must be performed at least once
when "DESKEW" is enabled.(1) Deskew is only supported in the DC Balance mode (BAL = High).
I
I
TTL level input. This pin was previously labeled as VCC, which enabled the DC Balance function.
But when tied low or left open, the DC Balance function is disabled. Please refer to Figure 15 and
Figure 16 for LVDS data bit mapping respectively.(1)(3)
VCC
I
I
I
I
I
I
Power supply pins for TTL inputs and digital circuitry. Bypass not required on Pins 20 and 21.
Ground pins for TTL inputs and digital circuitry.
Power supply pin for PLL circuitry.
GND
PLLVCC
PLLGND
LVDSVCC
LVDSGND
NC
Ground pins for PLL circuitry.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
No Connect. Make NO Connection to these pins - leave open.
(3) The DS90CR484 is design to automatically detect the DC Balance or non-DC Balance transmitted data from the DS90CR483 and
deserialize the LVDS data according to the define bit mapping.
DS90CR484 PIN DESCRIPTION—Channel Link Receiver
Pin Name
I/O
Description
RxINP
RxINM
RxOUT
I
I
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. In PowerDown (PD = Low) mode, receiver outputs are
forced to a Low state.
O
RxCLKP
RxCLKM
RxCLKOUT
PLLSEL
I
I
Positive LVDS differential clock input.
Negative LVDS differential clock input.
O
TTL level clock output. The rising edge acts as data strobe.
PLL range select. This pin should be tied to VCC for auto-range. Tied to ground or
NC will force the PLL to low range only. Typical shift point is between 55 and 68
I
I
(1) (2)
MHz for auto-range.
DESKEW
Deskew / Oversampling “on/off” select. When using the Deskew / Oversample
feature this pin must be tied to VCC. Tieing this pin to ground disables this
feature. Deskew is only supported in the DC Balance mode.(1)
PD
I
I
TTL level input. When asserted (low input) the receiver outputs are Low.(1)
VCC
Power supply pins for TTL outputs and digital circuitry. Bypass not required on
Pins 6 and 77.
GND
I
I
I
I
I
Ground pins for TTL outputs and digital circuitry.
Power supply for PLL circuitry.
PLLVCC
PLLGND
LVDSVCC
LVDSGND
NC
Ground pin for PLL circuitry.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
No Connect. Make NO Connection to these pins - leave open.
(1) Inputs default to “low” when left open due to internal pull-down resistor.
(2) The PLL range shift point is in the 55 - 68 MHz range, typically the shift will occur during the lock time. For 65-70 MHz applications, the
DS90CR481/2 is recommended since its shift point is below its operation range. See Applications Information section.
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Pin Diagram
Figure 17. Transmitter - DS90CR483 - TQFP (TOP VIEW)
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Pin Diagram
Figure 18. Receiver - DS90CR484 - TQFP (TOP VIEW)
20
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SNLS047H –FEBRUARY 2000–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision G (April 2013) to Revision H
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 20
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2013
PACKAGING INFORMATION
Orderable Device
DS90CR483VJD
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-10 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
NRND
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
NEZ
100
100
100
100
100
100
90
Green (RoHS
& no Sb/Br)
CU SN
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Call TI
DS90CR483VJD
>B
DS90CR483VJD/NOPB
DS90CR483VJDX
NRND
NRND
NRND
NRND
NRND
NEZ
NEZ
NEZ
NEZ
NEZ
90
Green (RoHS
& no Sb/Br)
-10 to 70
DS90CR483VJD
>B
1000
1000
90
Green (RoHS
& no Sb/Br)
CU SN
SN
-10 to 70
DS90CR483VJD
>B
DS90CR483VJDX/NOPB
DS90CR484VJD/NOPB
DS90CR484VJDX/NOPB
Green (RoHS
& no Sb/Br)
-10 to 70
DS90CR483VJD
>B
Green (RoHS
& no Sb/Br)
SN
DS90CR484VJD
>B
1000
TBD
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90CR483VJDX
TQFP
NEZ
NEZ
100
100
1000
1000
330.0
330.0
32.4
32.4
18.0
18.0
18.0
18.0
1.6
1.6
24.0
24.0
32.0
32.0
Q2
Q2
DS90CR483VJDX/NOPB TQFP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90CR483VJDX
TQFP
TQFP
NEZ
NEZ
100
100
1000
1000
367.0
367.0
367.0
367.0
55.0
55.0
DS90CR483VJDX/NOPB
Pack Materials-Page 2
MECHANICAL DATA
NEZ0100A
TYPICAL
VJD100A (Rev C)
www.ti.com
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相关型号：
DS90CR483AVJD/NOPB
48-bit LVDS channel link serializer with input clock support from 33 MHz to 112 MHz 100-TQFP -10 to 70
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