DS90CR486 [TI]
133MHz 48 位 Channel Link 解串器;
| 型号： | DS90CR486 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 133MHz 48 位 Channel Link 解串器 |
| 文件： | 总23页 (文件大小：911K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90CR486
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SNLS149C –FEBRUARY 2003–REVISED MARCH 2013
DS90CR486 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)
Check for Samples: DS90CR486
The DS90CR486 deserializer is improved over prior
1
FEATURES
generations of Channel Link devices and offers
higher bandwidth support and longer cable drive with
three areas of enhancement. To increase bandwidth,
the maximum clock rate is increased to 133 MHz and
8 serialized LVDS outputs are provided. Cable drive
is enhanced with a user selectable pre-emphasis (on
DS90CR485) feature that provides additional output
current during transitions to counteract cable loading
effects. Optional DC balancing on a cycle-to-cycle
basis, is also provided to reduce ISI (Inter-Symbol
Interference). With pre-emphasis and DC balancing,
a low distortion eye-pattern is provided at the receiver
end of the cable. A cable deskew capability has been
added to deskew long cables of pair-to-pair skew.
These three enhancements allow long cables to be
driven.
2
•
•
•
•
•
•
Up to 6.384 Gbps Throughput
66MHz to 133MHz Input Clock Support
Reduces Cable and Connector Size and Cost
Cable Deskew Function
DC Balance Reduces ISI Distortion
For Point-to-Point Backplane or Cable
Applications
•
•
•
•
•
Low Power, 890 mW Typ at 133MHz
Flow through Pinout for Easy PCB Design
+3.3V Supply Voltage
100-pin TQFP Package
Conforms to TIA/EIA-644-A-2001 LVDS
Standard
The DS90CR486 is intended to be used with the
DS90CR485 Channel Link Serializer. It is also
backward compatible with serializers DS90CR481
and DS90CR483. The DS90CR486 is footprint
compatible with the DS90CR484.
DESCRIPTION
The DS90CR486 receiver converts eight Low Voltage
Differential Signaling (LVDS) data streams back into
48 bits of LVCMOS/LVTTL data. Using a 133MHz
clock, the data throughput is 6.384Gbit/s
(798Mbytes/s).
The chipset is an ideal solution to solve EMI and
interconnect size problems for high-throughput point-
to-point applications.
The multiplexing of data lines provides a substantial
cable reduction. Long distance parallel single-ended
buses typically require a ground wire per active signal
(and have very limited noise rejection capability).
Thus, for a 48-bit wide data and one clock, up to 98
conductors are required. With this Channel Link
chipset as few as 19 conductors (8 data pairs, 1 clock
pair and a minimum of one ground) are needed. This
provides an 80% reduction in interconnect width,
which provides a system cost savings, reduces
connector physical size and cost, and reduces
shielding requirements due to the cables' smaller
form factor.
For more details, please refer to the APPLICATIONS
INFORMATION section of this datasheet.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
DS90CR486
SNLS149C –FEBRUARY 2003–REVISED MARCH 2013
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Generalized Block Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
Value
Unit
Supply Voltage (VCC
)
−0.3 to +3.6
V
V
LVCMOS/LVTTL Output Voltage
LVDS Receiver Input Voltage
−0.3 to (VCC + 0.3)
−0.3 to +3.6
V
Junction Temperature
+150
°C
°C
°C
W
Storage Temperature
−65 to +150
Lead Temperature (Soldering, 4 sec.)
Maximum Package Power Dissipation Capacity @ 25°C 100 TQFP Package:
Package Derating:
+260
2.9
23.8 mW/°C above +25°C
ESD Rating: (HBM, 1.5kΩ, 100pF)
ESD Rating: (EIAJ, 0Ω, 200pF)
> 2
kV
V
> 200
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the device should be operated at these limits. “Electrical Characteristics” specify conditions for device operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Min
3.14
−10
0
Nom
3.3
Max
3.46
+70
2.4
Units
V
Supply Voltage (VCC
)
Operating Free Air Temperature (TA)
Receiver Input Range
+25
°C
V
Supply Noise Voltage (VCC
)
100
133
mVp-p
MHz
Clock Rate
66
2
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Electrical Characteristics(1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ(2)
Max
Units
LVCMOS/LVTTL DC SPECIFICATIONS
VIH
High Level Input Voltage
All LVCMOS/LVTTL inputs except PD .
For PD input only.
2.0
2.5
VCC
VCC
0.8
V
V
VIL
IIN
Low Level Input Voltage
Input Current
GND
V
(3)
VIN = 0.4V, 2.5V, or VCC
+1.8
0
+15
µA
µA
V
VIN = GND
−15
VOH
VOL
IOS
High Level Output Voltage IOH = −2 mA
2.0
Low Level Output Voltage IOL = +2 mA
0.4
V
Output Short Circuit
Current
VOUT = 0V
−120
mA
VCL
Input Clamp Voltage
ICL = −18 mA
−0.8
−1.5
V
LVDS RECEIVER DC SPECIFICATIONS
VTH
VTL
IIN
Differential Input High
Threshold
VCM = +1.2V
+100
mV
mV
Differential Input Low
Threshold
−100
Input Current
VIN = +2.4V, VCC = 3.6V
VIN = 0V, VCC = 3.6V
±10
±10
µA
µA
RECEIVER SUPPLY CURRENT
ICCRW
Receiver Supply Current
Worst Case
CL = 8 pF, BAL = Low,
Worst Case Pattern
(Figure 1 and Figure 2)
f = 66 MHz
f = 100 MHz
f = 133 MHz
190
230
270
60
245
325
340
110
mA
mA
mA
µA
ICCRZ
Receiver Supply Current
Power Down
PD = Low
Receiver Outputs stay low during Power down mode.
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VTH, VTL and ΔVID).
(2) Typical values are given for VCC = 3.3V and T A = +25°C.
(3) The IIN parameter for the PD pin is not tested at 2.5V.
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Units
CLHT
LVCMOS/LVTTL Low-to-High Transition Time, (Figure 2), Rx
data out,
0.8
1.3
ns
(1)
LVCMOS/LVTTL Low-to-High Transition Time, (Figure 2), Rx
clock out,
0.7
0.9
0.8
T
1.0
1.3
ns
ns
ns
(1)
CHLT
LVCMOS/LVTTL High-to-Low Transition Time, (Figure 2), Rx
(1)
data out,
LVCMOS/LVTTL High-to-Low Transition Time, (Figure 2), Rx
1.0
(1)
clock out,
RCOP
RCOH
RxCLK OUT Period, (Figure 3)
7.518
2.7
15.152
ns
ns
ns
ns
ns
ns
ns
RxCLK OUT High Time, (Figure 3)
RxCLK OUT Low Time, (Figure 3)
f = 133 MHz
f = 100 MHz
f = 66 MHz
f = 133 MHz
f = 100 MHz
f = 66 MHz
3.8
6.0
RCOL
2.7
3.8
6.0
(1) CLHT and CHLT are measurements of the receiver data outputs low-to-high and high-to-low time over the recommended frequency
range. The limits are based on bench characterization and Specified By Design (SBD) using statistical analysis.
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Receiver Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
2.0
Typ
3.5
Max
Units
ns
RSRC
RxOUT Data valid before RxCLK OUT,
(Figure 3)
f = 133 MHz
f = 100 MHz
f = 66 MHz
3.0
4.7
ns
5.0
7.0
ns
RHRC
RxOUT Data valid after RxCLK OUT, (Figure 3) f = 133 MHz
f = 100 MHz
2.5
4.1
ns
3.5
5.0
ns
f = 66 MHz
6.0
8.0
ns
RPDL
Receiver Propagation Delay - Latency, (Figure 4)
Receiver Phase Lock Loop Set ,(Figure 5)
Receiver Powerdown Delay, (Figure 6)
Receiver Skew Margin with Deskew, BAL=Low f = 133 MHz
2(TCIP)+5
2(TCIP)+10
2(TCIP)+15
ns
RPLLS
RPDD
RSKMD
10
1
ms
µs
ps
275
400
(2)
(Figure 7),
f = 100 MHz
ps
f = 66 MHz
500
ps
RDR
Receiver Deskew Range
f = 133 MHz
f = 100 MHz
f = 66 MHz
−150
−200
−200
+150
+200
+200
ps
ps
ps
(2) Receiver Skew Margin with Deskew (RSKMD) is defined as the valid data sampling region at the receiver inputs. The DESKEW function
will constrain the receiver’s sampling strobes to the middle half of the LVDS bit and removes (adjusts for) fixed interconnect skew. This
margin (RSKMD) allows for inter-symbol interference (dependent on type/length of cable), Transmitter Pulse Position (TPPOS) variance,
and LVDS clock jitter (TJCC).RSKMD ≥ ISI + TPPOS(variance) + LVDS Source Clock Jitter (cycle to cycle). See APPLICATIONS
INFORMATION section for more details.
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AC Timing Diagrams
The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/LVTTL I/O.
Figure 1. “Worst Case” Test Pattern
Figure 2. DS90CR486 LVCMOS/LVTTL Output Load and Transition Times
Figure 3. DS90CR486 Setup/Hold and High/Low Times
Figure 4. DS90CR486 Propagation Delay - Latency
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Figure 5. DS90CR486 Phase Lock Loop Set Time (VCC > 3.0V)
Figure 6. DS90CR486 Power Down Delay
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
RSKMD = ISI (Inter-symbol interference) + TPPOS(variance) + LVDS Source Clock Jitter (cycle to cycle)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Refer to transmitter datasheet for Cycle-to-cycle LVDS Output jitter specification.
ISI is dependent on interconnect length; may be zero. Pre-emphasis in the transimitter is used to reduce the ISI.
Refer to transmitter datasheet for more information.
Figure 7. Receiver Skew Margin with DESKEW (RSKMD)
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SNLS149C –FEBRUARY 2003–REVISED MARCH 2013
LVDS Interface
Figure 8. 48 LVCMOS/LVTTL Outputs Mapped to 8 LVDS Inputs
(DC Balance Mode- Disable, BAL = Low)
(E1 - Falling Edge; E2 - Rising Edge)
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Figure 9. 48 LVCMOS/LVTTL Outputs Mapped to 8 LVDS Inputs
(DC Balance Mode - Enable, BAL = High)
(E1 - Falling Edge; E2 - Rising Edge)
Table 1. DS90CR486 Outputs Mapped to DS90CR485 Outputs/DS90CR483 Inputs
DS90CR486 Receiver Output
DS90CR485 Transmitter Input *
DS90CR483 Transmitter Input
RxOUT0
RxOUT1
RxOUT2
RxOUT3
RxOUT4
RxOUT5
RxOUT6
RxOUT7
RxOUT8
RxOUT9
RxOUT10
RxOUT11
RxOUT12
RxOUT13
RxOUT14
RxOUT15
RxOUT16
E2-D0
E2-D1
E2-D2
E2-D3
E2-D4
E2-D5
E2-D6
E2-D7
E2-D8
E2-D9
E2-D10
E2-D11
E2-D12
E2-D13
E2-D14
E2-D15
E2-D16
TxIN0
TxIN1
TxIN2
TxIN3
TxIN4
TxIN5
TxIN6
TxIN7
TxIN8
TxIN9
TxIN10
TxIN11
TxIN12
TxIN13
TxIN14
TxIN15
TxIN16
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Table 1. DS90CR486 Outputs Mapped to DS90CR485 Outputs/DS90CR483 Inputs (continued)
DS90CR486 Receiver Output
RxOUT17
RxOUT18
RxOUT19
RxOUT20
RxOUT21
RxOUT22
RxOUT23
RxOUT24
RxOUT25
RxOUT26
RxOUT27
RxOUT28
RxOUT29
RxOUT30
RxOUT31
RxOUT32
RxOUT33
RxOUT34
RxOUT35
RxOUT36
RxOUT37
RxOUT38
RxOUT39
RxOUT40
RxOUT41
RxOUT42
RxOUT43
RxOUT44
RxOUT45
RxOUT46
RxOUT47
DS90CR485 Transmitter Input *
E2-D17
E2-D18
E2-D19
E2-D20
E2-D21
E2-D22
E2-D23
E1-D0
DS90CR483 Transmitter Input
TxIN17
TxIN18
TxIN19
TxIN20
TxIN21
TxIN22
TxIN23
TxIN24
E1-D1
TxIN25
E1-D2
TxIN26
E1-D3
TxIN27
E1-D4
TxIN28
E1-D5
TxIN29
E1-D6
TxIN30
E1-D7
TxIN31
E1-D8
TxIN32
E1-D9
TxIN33
E1-D10
E1-D11
E1-D12
E1-D13
E1-D14
E1-D15
E1-D16
E1-D17
E1-D18
E1-D19
E1-D20
E1-D21
E1-D22
E1-D23
TxIN34
TxIN35
TxIN36
TxIN37
TxIN38
TxIN39
TxIN40
TxIN41
TxIN42
TxIN43
TxIN44
TxIN45
TxIN46
TxIN47
* E1 = Falling Edge and E2 = Rising Edge of RxCLK P/M Input Clock Edge
DS90CR486 PIN DESCRIPTIONS — CHANNEL LINK RECEIVER(1)
Pin Name
I/O
No.
8
Description
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
RxINP
RxINM
I
I
8
RxOUT
O
48
LVCMOS/LVTTL level data outputs. In PowerDown (PD = Low) mode, receiver
outputs are forced to a Low state.
RxCLKP
RxCLKM
RxCLKOUT
PLLSEL
I
I
1
1
1
1
Positive LVDS differential clock input.
Negative LVDS differential clock input.
O
I
LVCMOS/LVTTL level clock output. The rising edge acts as data strobe.
Control input for PLL range select. This pin must be tied to VCC. No connect or
tied to GND is reserved for future use.
(1) These receivers have input fail-safe bias circuitry to ensure a stable receiver output for floating or terminated receiver inputs. Under
these conditions receiver inputs will be in a HIGH state. If a clock signal is present, outputs will all be HIGH; if the cable inter-connects
are disconnected which results in floating/terminated inputs, the outputs will remain in the last valid state. A floating/terminated clock
input will result in a LOW clock output.
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Pin Name
I/O
No.
Description
PD
I
1
Power Down pin. This pin must be tied to input level of 2.5V to Vcc for normal
operation. When de-asserted (low input) the receiver outputs are Low. Please refer
to the APPLICATIONS INFORMATION on the back for more information.
DESKEW
BAL
I
I
1
1
This pin must be tied to logic High or Vcc for normal operation of Deskew function.
De-asserting a pulse of duration greater than 4 clock cycles will restart the deskew
initialization. Do NOT tie this pin to LOW. Please refer to the APPLICATIONS
INFORMATION on the back for more information.
LVCMOS/LVTTL level input. This pin must be tied to logic High or Vcc to enable
DC Balance function(Figure 9). When tied low or left open, the DC Balance function
is disabled(Figure 8). Please refer to the APPLICATIONS INFORMATION on the
back for more infomation.
CON1
I
I
I
I
I
I
I
1
6
8
1
2
2
3
6
Control Pin. This pin must be tied to logic High or Vcc.
Power supply pins for LVCMOS/LVTTL outputs and digital circuitry.
Ground pins for LVCMOS/LVTTL outputs and digital circuitry.
Power supply for PLL circuitry.
VCC
GND
PLLVCC
PLLGND
LVDSVCC
LVDSGND
NC
Ground pin for PLL circuitry.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
No Connect. Make NO Connection to these pins - leave open.
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APPLICATIONS INFORMATION
DC BALANCE
In addition to data information an additional bit is transmitted on every LVDS data signal line during each cycle
as shown in Figure 9. This bit is the DC balance bit (DCB). The purpose of the DC Balance bit is to minimize the
short- and long-term DC bias on the signal lines. This is achieved by selectively sending the data either
unmodified or inverted.
The value of the DC balance bit is calculated from the running word disparity and the data disparity of the current
word to be sent. The data disparity of the current word shall be calculated by subtracting the number of bits of
value 0 from the number of bits value 1 in the current word. Initially, the running word disparity may be any value
between +7 and −6. The running word disparity shall be calculated as a continuous sum of all the modified data
disparity values, where the unmodified data disparity value is the calculated data disparity minus 1 if the data is
sent unmodified and 1 plus the inverse of the calculated data disparity if the data is sent inverted. The value of
the running word disparity shall saturate at +7 and −6.
The value of the DC balance bit (DCB) shall be 0 when the data is sent unmodified and 1 when the data is sent
inverted. To determine whether to send data unmodified or inverted, the running word disparity and the current
data disparity are used. If the running word disparity is positive and the current data disparity is positive, the data
shall be sent inverted. If the running word disparity is positive and the current data disparity is zero or negative,
the data shall be sent unmodified. If the running word disparity is negative and the current data disparity is
positive, the data shall be sent unmodified. If the running word disparity is negative and the current data disparity
is zero or negative, the data shall be sent inverted. If the running word disparity is zero, the data shall be sent
inverted.
DC Balance mode is set when the BAL pin on the transmitter and receiver are tied HIGH - see DS90CR486 PIN
DESCRIPTIONS — CHANNEL LINK RECEIVER.
DESKEW
The "DESKEW” function on this receiver will deskew or compensate fixed interconnect skew between data
signals, with respect to the rising edge of the LVDS clock, on each of the independent differential pairs (pair-to-
pair skew). The deskew initialization or calibration is done automatically when the device is powered up. The
control pin CON1 must set High and the Deskew pin must set to High on the DS90CR486. However, the Deskew
calibration can also be performed after the device is powered up. De-asserting with a pulse of duration greater
than four clock cycles to the Deskew pin to restart the calibration of deskew. The calibration takes 4096 clock
cycles to complete after the TX and RX PLLs lock (20ms). No RxIN data is sampled during this period. The data
outputs during this period will be Low. For normal operation, deskew pin must set to High. Setting the deskew pin
to Low or No Connect will continuously re-calibrate the sampling strobes. Data outputs are Low during this
period.
In order for the deskew function to work properly, it must be intialized. The DS90CR486 deskew can be initialized
with any data pattern with a minimum of 1 transition per clock cycle; however, having multiple transition per clock
cycle will further improve the chance for the deskew circuit to find the optimal edge. Therefore, there are mulitiple
ways to initialize the deskew function depending on the setup configuration (Please refer to Figure 10). For
example, to initialize the operation of deskew using DS90CR485 and DS90CR486 in DC balance mode, the
DS_OPT pin at the input of the transmitter DS90CR485 can be set High OR Low when powered up. The period
of this input to the DS_OPT pin must be at least 20ms (TX and RX PLLs lock time) plus 4096 clock cycles in
order for the receiver to complete the deskew operation. For other configuration setup with DS90CR483 and
DS90CR484, please refer to the flow chart on Figure 10.
The DS_OPT pin at the input of the transmitter (DS90CR485) can be used to initiate the deskew calibration
pattern. Depends on the configuration, it can be set High or applied Low when power up in order for the receiver
to complete the deskew operation. For this reason, the LVDS clock signal with DS_OPT applied high (active data
sampling) shall be 1111000 or 1110000 pattern and the LVDS data lines (TxOUT 0-7) shall be High for one clock
cycle and Low for the next clock cycle. During the deskew operation with DS_OPT applied low, the LVDS clock
signal shall be 1111100 or 1100000 pattern. The transmitter will also output a series of 1111000 or 1110000 onto
the LVDS data lines (TxOUT 0-7) during deskew so that the receiver can automatically calibrated the data
sampling strobes at the receiver inputs. Each data channel is deskewed independently and is tuned over a
specific range. Please refer to corresponding receiver datasheet for a list of deskew ranges.
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Note that the deskew initialization must be performed at least once after the PLL has locked to the input clock
frequency, and it must be done at the time when the receiver is powered up and PLL has locked. If power is lost,
or if the cable has been swithcd or disconnected, the initialization procedure must be repeated or else the
receiver may not sample the incoming LVDS data correctly.
POWER DOWN
The receiver provides a power down feature. When de-asserted current draw through the supply pins is
minimized and the PLLs are shut down. The receiver outputs are forced to an active LOW state when in the
power down mode. (See DS90CR486 Pin Descriptions — Channel Link Receiver Table). This is not a
LVCMOS/LVTTL input pin and has a high input threshold. For normal operation, this pin must be tied to an input
level of 2.5V to Vcc.
CONFIGURATIONS
The chipset is designed to be connected typically to a single receiver load. This is known as a point-to-point
configuration. It is also possible to drive multiple receiver loads if certain restrictions are made(i.e. low data rate).
Only the final receiver at the end of the interconnect should provide termination across the pair. In this case, the
driver still sees the intended DC load of 100 Ohms. Receivers connected to the cable between the transmitter
and the final receiver must not load down the signal. To meet this system requirement, stub lengths from the line
to the receiver inputs must be kept very short.
CABLE TERMINATION
A termination resistor is required for proper operation to be obtained. The termination resistor should be equal to
the differential impedance of the media being driven. This should be in the range of 90 to 132 Ohms. 100 Ohms
is a typical value common used with standard 100 Ohm twisted pair cables. This resistor is required for control of
reflections and also to complete the current loop. It should be placed as close to the receiver inputs to minimize
the stub length from the resistor to the receiver input pins.
HOW TO CONFIGURE FOR BACKPLANE APPLICATIONS
In a backplane application with differential line impedance of 100Ω the differential line pair-to-pair skew can
controlled by trace layout. The transmitter-DS90CR485 “DS_OPT” pin may be set high. In a backplane
application with short PCB distance traces, pre-emphasis from the transmitter is typically not required. The “PRE”
pin should be left open (do not tie to ground). A resistor pad provision for a pull up resistor to Vcc can be
implemented in case pre-emphasis is needed to counteract heavy capacitive loading effects.
SUPPLY BYPASS RECOMMENDATIONS
Bypass capacitors must be used on the power supply pins. Different pins supply different portions of the circuit,
therefore capacitors should be nearby all power supply pins except as noted in the DS90CR486 Pin
Descriptions — Channel Link Receiver table. Use high frequency ceramic (surface mount recommended) 0.1μF
capacitors close to each supply pin. If space allows, a 0.01μF capacitor should be used in parallel, with the
smallest value closest to the device pin. Additional scattered capacitors over the printed circuit board will improve
decoupling. Multiple (large) via should be used to connect the decoupling capacitors to the power plane. A 4.7 to
10μF bulk cap is recommended near the PLLVCC pins and also the LVDSVCC pins. Connections between the
caps and the pin should use wide traces.
RECEIVER OUTPUT DRIVE STRENGTH
The DS90CR486 output specifies a 8pF load, VOH and VOL are tested at ± 2mA, which is intended for only 1 or
maybe 2 loads. The DS90CR486 receiver’s output driving capability has improved over prior generation of
Channel Link devices. Additional buffering at the receiver output is not necessary. If high fan-out is required or
long transmission line driving capability, buffering the receiver output is recommended. Receiver outputs do not
support / provide a TRI-STATE function.
LVDS INTERCONNECT GUIDELINES
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
•
•
Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
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SNLS149C –FEBRUARY 2003–REVISED MARCH 2013
–
–
–
S = space between the pair
2S = space between pairs
3S = space to TTL signal
•
•
•
•
•
•
Minimize the number of VIA
Use differential connectors when operating above 500Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Minimize skew between pairs
Terminate as close to the RXinputs as possible
For more information:
Channel Link Applications Notes currently available:
•
•
•
•
AN-1041 Introduction to Channel Link (literature number SNLA218)
AN-1108 PCB and Interconnect Guidelines (literature number SNLA008)
AN-905 Differential Impedance (literature number SNLA035)
TI’s LVDS Owner’s Manual (literature number SNLA187)
Select TX
Select RX
Select RX
Balance
Mode
Balance
Mode
Balance
Mode
Balance
Mode
DESKEW
Not supported
DESKEW
Not supported
Configuration 1
Configuration 2
Configuration 3
Configuration 4
Configuration 5
Configuration 6
Figure 10. Deskew Configuration Setup Chart
CONFIGURATION 1
DS90CR481/483 and DS90CR484 with DC Balance ON (BAL=High, 33MHz to 80MHz) − The DS_OPT pin at
the input of the transmitter DS90CR481/483 must be applied low for a minimum of four clock cycles in order for
the receiver to complete the deskew operation. The input to the DS_OPT pin can be applied at any time after the
PLL has locked to the input clock frequency. In this particular setup, the "DESKEW" pin on the receiver
DS90CR484 must set High.
CONFIGURATION 2
DS90CR481/483 and DS90CR486 with DC Balance ON (BAL=High, CON1=High, 66MHz to 112MHz) − The
DS_OPT pin at the input of the transmitter DS90CR481/483 can be set to High OR Low when power up. The
period of this input to the DS_OPT pin must be at least 20ms (TX and RX PLLs lock time) plus 4096 clock cycles
in order for the receiver to complete the deskew operation. The "DESKEW" and CON1 pins on the receiver
DS90CR486 must be tied to High for this setup.
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CONFIGURATION 3
DS90CR481/483 and DS90CR486 with DC Balance OFF (BAL=Low, CON1=High, 66MHz to 112MHz) − The
input to the DS_OPT pin of the transmitter DS90CR481/483 in this configuration is completely ignored by the
transimitters. In order to initialize the deskew operation on the receiver DS90CR486, data and clcok must be
applied to the transimitter when power up. The "DESKEW" and CON1 pins on the receiver DS90CR486 must be
tied to High for this setup.
CONFIGURATION 4
DS90CR485 and DS90CR484 with DC Balance ON (BAL=High, 66MHz to 80MHz) − The DS_OPT pin at the
input of the transmitter DS90CR485 must be applied low for a minimum of four clock cycles in order for the
receiver to complete the deskew operation. The input to the DS_OPT pin can be applied at any time after the
PLL has locked to the input clock frequency. In this setup, the "DESKEW" pin on the receiver DS90CR484 must
set High.
CONFIGURATION 5
DS90CR485 and DS90CR486 with DC Balance ON (BAL=Hiigh, CON1=High, 66MHz to 133MHz) − The
DS_OPT pin at the input of the transmitter DS90CR485 can be set to High OR Low when power up. The period
of this input to the DS_OPT pin must be at least 20ms (TX and RX PLLs lock time) plus 4096 clock cycles in
order for the receiver to complete the deskew operation. The "DESKEW" and CON1 pins on the receiver
DS90CR486 must set High.
CONFIGURATION 6
DS90CR485 and DS90CR486 with DC Balance OFF (BAL=Low, CON1=High, 66MHz to 133MHz) −The input to
the DS_OPT pin of the transmitter DS90CR485 in this configuration is completely ignored. In order to initialize
the deskew operation on the receiver DS90CR486, data and clcok must be applied to the transimitter when
power up. The "DESKEW" and CON1 pins on the receiver DS90CR486 must set High.
DESKEW NOT SUPPORTED
Deskew function is NOT supported in these configuration setups. The deskew feature is only supported with DC
Balance ON (BAL=High) for DS90CR484. Note that the deskew function in the DS90CR486 works in both DC
Balance and NON-DC Balance modes.
NOTE
For more details on Deskew operation, please refer to the APPLICATIONS
INFORMATION section.
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SNLS149C –FEBRUARY 2003–REVISED MARCH 2013
Pin Diagram
Figure 11. Receiver - DS90CR486
(Top View)
See Package Number NEZ0100A
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REVISION HISTORY
Changes from Revision B (March 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90CR486VS/NOPB
DS90CR486VSX/NOPB
ACTIVE
TQFP
TQFP
NEZ
100
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-10 to 70
-10 to 70
DS90CR486VS
>B
Samples
Samples
ACTIVE
NEZ
1000 RoHS & Green
SN
DS90CR486VS
>B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90CR486VSX/NOPB
TQFP
NEZ
100
1000
330.0
32.4
18.0
18.0
1.6
24.0
32.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TQFP NEZ 100
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 55.0
DS90CR486VSX/NOPB
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DS90CR486VS/NOPB
NEZ
TQFP
100
90
6 x 15
150
322.6 135.9 7620 20.3
15.4 15.45
Pack Materials-Page 3
MECHANICAL DATA
NEZ0100A
TYPICAL
VJD100A (Rev C)
www.ti.com
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