DS90LV031AQML-SP [TI]
3V LVDS 四路 CMOS 差动线路驱动器;
| 型号： | DS90LV031AQML-SP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3V LVDS 四路 CMOS 差动线路驱动器 驱动 驱动器 |
| 文件： | 总19页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90LV031AQML
www.ti.com
SNLS204A –NOVEMBER 2011–REVISED APRIL 2013
DS90LV031AQML 3V LVDS Quad CMOS Differential Line Driver
Check for Samples: DS90LV031AQML
1
FEATURES
DESCRIPTION
The DS90LV031A is a quad CMOS differential line
driver designed for applications requiring ultra low
power dissipation and high data rates. The device is
designed to support data rates in excess of 400 Mbps
(200 MHz) utilizing Low Voltage Differential Signaling
(LVDS) technology.
23
•
High impedance LVDS outputs with power-off
Low differential skew
•
•
•
•
•
•
•
Low propagation delay
3.3V power supply design
±350 mV differential signaling
Low power dissipation
The DS90LV031A accepts low voltage TTL/CMOS
input levels and translates them to low voltage (350
mV) differential output signals. In addition the driver
supports a TRI-STATE® function that may be used to
disable the output stage, disabling the load current,
and thus dropping the device to an ultra low idle
power state of 13 mW typical.
Interoperable with existing 5V LVDS devices
Compatible with IEEE 1596.3 SCI LVDS
standard
•
Compatible with proposed TIA/EIA-644 LVDS
standard
The EN and EN* inputs allow active Low or active
High control of the TRI-STATE outputs. The enables
are common to all four drivers. The DS90LV031A and
companion line receiver (DS90LV032A) provide a
new alternative to high power psuedo-ECL devices
for high speed point-to-point interface applications.
•
•
•
Pin compatible with DS26C31
Typical Rise/Fall times of 800pS.
Typical Tri-State Enable/Disable delays of less
than 5nS.
Connection Diagram
Figure 1. Dual-In-Line
See Package Number NAC0016A or
NAD0016A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TRI-STATE is a registered trademark of Texas Instruments.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
DS90LV031AQML
SNLS204A –NOVEMBER 2011–REVISED APRIL 2013
www.ti.com
Functional Diagram
Figure 2.
Truth Table – Driver
Enables
Input
Outputs
En
En*
DI
X
L
DO+
Z
DO−
L
H
Z
H
L
L
All other combinations of ENABLE inputs
H
H
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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SNLS204A –NOVEMBER 2011–REVISED APRIL 2013
(1)
Absolute Maximum Ratings
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to +3.9V
−65°C ≤ TA ≤ +150°C
+260°C
Input Voltage (DI)
Enable Input Voltage (En, En*)
Output Voltage (DO+, DO−)
Storage Temperature Range
Lead Temperature Range (Soldering 4 sec.)
Maximum Junction Temperature
+150°C
(2)
Maximum Power Dissipation @ +25°C
16LD CLGA (NAC and NAD)
Thermal Resistance
θJA
845mW
16LD CLGA (NAC and NAD)
θJC
148°C/W
16LD CLGA (NAC and NAD)
22°C/W
6KV
(3)
ESD Rating
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) Derate (NAD & NAC packages) at 6.8mW/°C for temperatures above +25°C.
(3) Human body model, 1.5 kΩ in series with 100 pF
Recommended Operating Conditions
Min
Typ
Max
+3.6V
+125°C
Supply Voltage (VCC
)
+3.0V
-55°C
+3.3V
+25°C
Operating Free Air Temperature (TA)
Table 1. Quality Conformance InspectionMil-Std-883, Method 5005 - Group A
Subgroup
Description
Static tests at
Temp °C
+25
1
2
Static tests at
+125
-55
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling time at
Settling time at
Settling time at
+25
5
+125
-55
6
7
+25
8A
8B
9
+125
-55
+25
10
11
12
13
14
+125
-55
+25
+125
-55
Copyright © 2011–2013, Texas Instruments Incorporated
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DS90LV031A Electrical Characteristics DC Parameters
The following conditions apply, unless otherwise specified.
DC:
VCC = 3.0/3.6V
Sub-
groups
Symbol
Parameter
Conditions
RL = 100Ω
Notes
Min
Max
Units
VOD1
Differential Ouput Voltage
Figure 3
Figure 3
250
450
50
mV
mV
1, 2, 3
1, 2, 3
ΔVOD1
Δ in magnitude of VOD1 for
RL = 100Ω
complementary output States
VOS
Offset Voltage
RL = 100Ω
RL = 100Ω
Figure 3
Figure 3
1.125
1.625
50
V
1, 2, 3
1, 2, 3
ΔVOS
Δ in Magnitude of VOS for
mV
Complementary Output States
VOH
VOL
VIH
VIL
IIH
Output Voltage High
Output Voltage Low
Input Voltage High
Input Voltage Low
Input Current
RL = 100Ω
RL = 100Ω
Figure 3
1.85
V
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Figure 3
0.9
2.0
(1)
VCC
0.8
V
(1)
Gnd
V
VI = VCC or 2.5V, VCC = 3.6V
VI = Gnd or 0.4V, VCC = 3.6V
ICl = -8mA, VCC = 3.0V
±10
±10
-1.5
µA
µA
V
IIL
Input Current
VCl
IOS
Input Clamp Voltage
Output Short Circuit Current
Enabled,
-9.0
mA
DI = VCC, DO+ = 0V or
DI = Gnd, DO- = 0V
IOff
Power-off Leakage
VO = 0V or 3.6V
VCC = 0V or VCC = Open
±20
±10
18
µA
µA
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
IOZ
Output TRI-STATE Current
En = 0.8V and En* = 2.0V
VO = 0V or VCC, VCC = 3.6V
ICC
No Load Drivers Enabled
Supply Current
DI = VCC or Gnd
mA
mA
mA
ICCL
ICCZ
Loaded Drivers Enabled
Supply Current
RL = 100Ω All Channels,
DI = VCC or Gnd (all inputs)
35
Loaded or No Load Drivers
Disabled Supply Current
DI = VCC or Gnd, En = Gnd,
En* = VCC
12
(1) Tested during VOH/VOL tests.
DS90LV031A Electrical Characteristics AC Parameters
The following conditions apply, unless otherwise specified.
AC:
VCC = 3.0/3.3/3.6V, RL = 100Ω, CL = 20pF.
Sub-
groups
Symbol
tPHLD
Parameter
Conditions
Notes
Min Max
Units
Differential Propagation Delay
High to Low
Figure 4
and
0.3
3.5
ns
9, 10, 11
Figure 5
tPLHD
Differential Propagation Delay
Low to High
Figure 4
and
0.3
3.5
ns
9, 10, 11
Figure 5
tSkD
tSk1
tSk2
Differential Skew tPHLD - tPLHD
Channel to Channel Skew
Chip to Chip Skew
1.5
1.75
3.2
ns
ns
ns
9, 10, 11
9, 10, 11
9, 10, 11
(1)
(2)
(1) Channel to Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same
chip with any event on the inputs.
(2) Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
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SNLS204A –NOVEMBER 2011–REVISED APRIL 2013
PARAMETER MEASUREMENT INFORMATION
Figure 3. Driver VOD and VOS Test Circuit
Figure 4. Driver Propagation Delay and Transition Time Test Circuit
Figure 5. Driver Propagation Delay and Transition Time Waveforms
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TYPICAL APPLICATION
Figure 6. Point-to-Point Application
APPLICATION INFORMATION
General application guidelines and hints for LVDS drivers and receivers may be found in the LVDS Owner's
Manual at http://www.ti.com/ww/en/analog/interface/lvds.shtml.
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 6. This configuration provides a clean signaling environment for the quick edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media
is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as
close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver
into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver
configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as
well as ground shifting, noise margin limits, and total termination loading must be taken into account.
The DS90LV031A differential line driver is a balanced current source design. A current mode driver, generally
speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode
driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in
one direction to produce a logic state and in the other direction to produce the other logic state. The output
current is typically 3.5 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode requires (as
discussed above) that a resistive termination be employed to terminate the signal and to complete the loop as
shown in Figure 6. AC or unterminated configurations are not allowed. The 3.5 mA loop current will develop a
differential voltage of 350 mV across the 100Ω termination resistor which the receiver detects with a 250 mV
minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (350
mV – 100 mV = 250 mV)). The signal is centered around +1.2V (Driver Offset, VOS) with respect to ground as
shown in Figure 7. Note that the steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage
(VOD) and is typically 700 mV.
The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its
quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver
increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows
between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed
current between its output without any substantial overlap current. This is similar to some ECL and PECL
devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires > 80% less
current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing
RS-422 drivers.
The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when
the transmission of data is not required.
The footprint of the DS90LV031A is the same as the industry standard 26LS31 Quad Differential (RS-422) Driver
and is a step down replacement for the 5V DS90C031 Quad Driver.
Power Decoupling Recommendations
Bypass capacitors must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1μF
in parallel with 0.01μF, in parallel with 0.001μF at the power supply pin as well as scattered capacitors over the
printed circuit board. Multiple vias should be used to connect the decoupling capacitors to the power planes. A
10μF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit
board.
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PC Board considerations
Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL
and LVDS signals on different layers which are isolated by a power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
Differential Traces
Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable)
and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave
the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as
common-mode. Lab experiments show that differential signals which are 1mm apart radiate far less noise than
traces 3mm apart since magnetic field cancellation is greater with the closer traces. Plus, noise induced on the
differential lines is much more likely to appear as common-mode which is rejected by the receiver.
Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase
difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI
will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118
in/ps). Do not rely solely on the auto-route function for differential traces. Carefully review dimensions to match
differential impedance and provide isolation for the differential lines. Minimize the number of vias and other
discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode
rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid
discontinuities in differential impedance. Minor violations at connection points are allowable.
Termination
Use a resistor which best matches the differential impedance of your transmission line. The resistor should be
between 90Ω and 130Ω. Remember that the current mode outputs need the termination resistor to generate the
differential voltage. LVDS will not work without resistor termination. Typically, connect a single resistor across the
pair at the receiver end.
Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination
to the receiver inputs should be minimized. The distance between the termination resistor and the receiver
should be < 10mm (12mm MAX).
Probing LVDS Transmission Lines
Always use high impedance (> 100kΩ), low capacitance (< 2pF) scope probes with a wide bandwidth (1GHz)
scope. Improper probing will give deceiving results.
Cables and Connectors, General Comments
When choosing cable and connectors for LVDS it is important to remember:
Use controlled impedance media. The cables and connectors you use should have a matched differential
impedance of about 100Ω. They should not introduce major impedance discontinuities.
Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for
noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and
also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by
the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤
10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive.
Fail-safe Feature
The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS
logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from
appearing as a valid signal.
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The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs.
1. Open Input Pins. The DS90LV032A is a quad receiver device, and if an application requires only 1, 2 or 3
receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output
to a HIGH state. This internal circuitry will ensure a HIGH, stable output state for open inputs.
2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or
power-off condition, the receiver output will again be in a HIGH state, even with the end of cable 100Ω
termination resistor across the input pins. The unplugged cable can become a floating antenna which can
pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a
valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced
interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable.
3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V
differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not
supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs
shorted and no external common-mode voltage applied.
External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the
presence of higher noise levels. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to
minimize loading and waveform distortion to the driver. The common-mode bias point should be set to
approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry.
Figure 7. Driver Output Levels
Pin Descriptions
Pin No.
Name
DI
Description
Driver input pin, TTL/CMOS compatible
1, 7, 9, 15
2, 6, 10, 14
DO+
DO−
En
Non-inverting driver output pin, LVDS levels
Inverting driver output pin, LVDS levels
Active high enable pin, OR-ed with En*
Active low enable pin, OR-ed with En
Power supply pin, +3.3V ± 0.3V
Ground pin
3, 5, 11, 13
4
12
16
8
En*
VCC
Gnd
8
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Typical Performance Curves
Figure 8. Typical DS90LV031, TA = 25°C
DO (single ended) vs RL
Figure 9. Typical DS90LV031, DO vs RL,
VCC = 3.3V, TA = 25°C
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REVISION HISTORY
Changes from Original (April 2013) to Revision A
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 9
10
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962-9865101QFA
ACTIVE
CFP
CFP
CFP
NAD
16
16
16
19
Non-RoHS
& Green
Call TI
Level-1-NA-UNLIM
Level-1-NA-UNLIM
Level-1-NA-UNLIM
-55 to 125
DS90LV031AW
-QML Q
5962-98651
01QFA ACO
01QFA >T
DS90LV031AW-QML
DS90LV031AWGMLS
ACTIVE
ACTIVE
NAD
NAC
19
42
Non-RoHS
& Green
Call TI
Call TI
-55 to 125
-55 to 125
DS90LV031AW
-QML Q
5962-98651
01QFA ACO
01QFA >T
Non-RoHS
& Green
DS90LV031AWG
MLS ACO
MLS >T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DS90LV031AQML, DS90LV031AQML-SP :
Military : DS90LV031AQML
•
Space : DS90LV031AQML-SP
•
NOTE: Qualified Version Definitions:
Military - QML certified for Military and Defense Applications
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
5962-9865101QFA
NAD
NAD
CFP
CFP
16
16
19
19
502
502
23
23
9398
9398
9.78
9.78
DS90LV031AW-QML
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
DS90LV031AWGMLS
NAC
CFP
16
42
7 X 6
NA
101.6 101.6 8001 2.84 15.24 15.24
Pack Materials-Page 2
PACKAGE OUTLINE
NAC0016A
CFP - 2.33mm max height
S
C
A
L
E
1
.
5
0
0
CERAMIC FLATPACK
SUPPLIER OPTION
NOTE 3
LEAD 1 ID
NOTE 3
.018 MAX TYP
[0.46]
.010 .002
[0.254 0.0508]
.00 MIN TYP
[0.0]
1
16
14X .050 .002
[1.27 0.0508]
.3870 .0030
[9.83 0.076]
16X .017 .002
[0.4318 0.0508]
9
8
+.010
+.020
-.005
.070
.250
-.020
+0.254
+0.508
-0.127
1.778
6.35
[
-0.508
]
[
]
.410 .010
[10.414 0.254]
.008 .004
[0.2032 0.1016]
TYP
SEE DETAIL A
.004 [0.1]
SEATING PLANE
.006 .002
TYP
[0.1524 0.0508]
R.015 .002
[0.381 0.0508]
.040 .003
[1.016 0.0762]
0 -4
D
SCALE
:E1
2
T
.0
A
00
IL
A
[
DETAIL A
TYPICAL
4215198/C 08/2022
NOTES:
1. Controlling dimension is Inch. Values in [ ] are milimeters. Dimensions in ( ) for reference only.
2. For solder thickness and composition, see the "Lead Finish Composition/Thickness" link in the packaging section of the
Texas Instruments website
3. Lead 1 identification shall be:
a) A notch or other mark within this area
b) A tab on lead 1, either side
4. No JEDEC registration as of December 2021
www.ti.com
EXAMPLE BOARD LAYOUT
NAC0016A
CFP - 2.33mm max height
CERAMIC FLATPACK
(16X .090 )
[2.29]
SYMM
(14X .050 )
[1.27]
(16X .027 )
[0.69]
SYMM
R.002 TYP
[0.05]
(.37 )
[9.4]
RECOMMENDED LAND PATTERN
.003 MAX
[0.07]
ALL AROUND
.003 MIN
[0.07]
ALL AROUND
METAL
SOLDERMASK
OPENING
METAL UNDER
SOLDER MASK
SOLDERMASK
OPENING
SOLDERMASK
DEFINED
NON SOLDERMASK
DEFINED
4215198/C 08/2022
www.ti.com
REVISIONS
REV
A
DESCRIPTION
E.C.N.
DATE
BY/APP'D
RELEASE TO DOCUMENT CONTROL
2197879
2198832
2200917
12/30/2021
02/15/2022
08/08/2022
TINA TRAN / ANIS FAUZI
K. SINCERBOX
B
NO CHANGE TO DRAWING; REVISION FOR YODA RELEASE;
.387 .003 WAS .39000 .00012;
C
D. CHIN / K. SINCERBOX
REV
SCALE
SIZE
PAGE
OF
4215198
C
4
4
A
MECHANICAL DATA
NAD0016A
W16A (Rev T)
www.ti.com
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