DS90LV032AQML [TI]

DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver; DS90LV032AQML 3V LVDS四通道CMOS差分线路接收器


型号：	DS90LV032AQML
厂家：	TEXAS INSTRUMENTS
描述：	DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver DS90LV032AQML 3V LVDS四通道CMOS差分线路接收器
文件：	总14页 (文件大小：269K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS90LV032AQML

DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver

Literature Number: SNLS205

November 15, 2011

DS90LV032AQML

3V LVDS Quad CMOS Differential Line Receiver

General Description

Features

The DS90LV032A is a quad CMOS differential line receiver

designed for applications requiring ultra low power dissipation

and high data rates.

Low chip to chip skew

■

Low differential skew

High impedance LVDS inputs with power-off

Low power dissipation

■

The DS90LV032A accepts low voltage (350 mV typical) dif-

ferential input signals and translates them to 3V CMOS output

levels. The receiver supports a TRI-STATE^®function that

may be used to multiplex outputs.

Accepts small swing (330 mV) differential signal levels.

Compatible with ANSI/TIA/EIA-644

Operating temperature range (-55°C to +85°C)

Pin compatible with DS90C032A and DS26C32A.

Typical Rise/Fall time is 350pS.

The DS90LV032A and companion LVDS line driver (eg.

DS90LV031A) provide a new alternative to high power PECL/

ECL devices for high speed point-to-point interface applica-

tions.

In addition, the DS90LV032A provides power-off high

impedance LVDS inputs. This feature assures minimal load-

ing effect on the LVDS bus lines when V_CCis not present.

Ordering Information

NS Part Number

SMD Part Number

5962–9865201QFA

5962–9865201QXA

NS Package Number

Package Description

16LD Ceramic Flatpack

16LD Ceramic SOIC

16LD Ceramic Flatpack

16LD Ceramic SOIC

BARE DIE

DS90LV032AW-QML

DS90LV032AWGQML

DS90LV032AW-MLS

DS90LV032AWGMLS

DS90LV032 MDS

W16A

WG16A

W16A

WG16A

(Note 10)

Connection Diagram

Functional Diagram

Dual-in-Line Pictured

20163901

See NS Package Number W16A or WG16A

20163902

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

201639

www.ti.com

Absolute Maximum Ratings (Note 1)

Supply Voltage (V_CC

)

−0.3V to +4V

−0.3V to +3.9V

Input Voltage (R_I+, R_I−)

Enable Input Voltage (En, En*)

Output Voltage (R_O)

−0.3V to (V_CC+ 0.3V)

Storage Temperature Range

−65°C ≤ T_A≤ +150°C

Lead Temperature Range (Soldering 4 sec.)

+260°C

Maximum Package Power Dissipation @ +25°C (Note 2)

W Package

WG Package

Thermal Resistance

ꢀθ_JA

845 mW

W Package

WG Package

148°C/W

ꢀθ_JC

W Package

21°C/W

+150°C

4.5 KV

WG Package

Maximum Junction Temperature

ESD Rating (Note 3)

Recommended Operating Conditions

Min

+3.15

Gnd

−55

Max

+3.45

+3.0

+85

Unit

Supply Voltage (V_CC

)

Receiver Input Voltage

Operating Free Air Temperature (T_A)

°C

Quality Conformance Inspection

Mil-Std-883, Method 5005 - Group A

Subgroup

Description

Static tests at

Temp °C

+25

Static tests at

+125

-55

Static tests at

Dynamic tests at

Functional tests at

Switching tests at

Settling time at

+25

+125

-55

+25

+125

-55

+25

+125

-55

+25

+125

-55

www.ti.com

DS90LV032A Electrical Characteristics

DC Parameters

The following conditions apply, unless otherwise specified.

Over supply voltage range of 3.15V to 3.45V and operating temperature of −55°C to +85°C.

Sub-

groups

Symbol

V_TL

Parameter

Conditions

Notes

Min Max

Units

Differential Input Low Threshold V_CM= +1.2V

Differential Input High Threshold V_CM= +1.2V

Common Mode Voltage Range V_ID= 200mV peak to peak

(Note 4)

-100

100

1, 2, 3

V_Th

VCMR

(Note 4),

(Note 6)

0.1

2.3

I_I

Input Current

V_CC= 3.45V or 0V,

V_I= 2.8V or 0V

±10

µA

1, 2, 3

V_CC= 0V, V_I= 3.45V

±20

µA

1, 2, 3

V_OH

Output High Voltage

I_OH= -0.4 mA, V_ID= 200mV

I_OH= -0.4 mA, Inputs Open

I_OL= 2 mA, V_ID= -200mV

Enabled, V_O= 0V

2.7

V_OL

I_OS

I_OZ

V_IH

V_IL

I_L

Output Low Voltage

Output Short Circuit Current

Output TRI-STATE Current

Input High Voltage

0.25

(Note 8)

-15 -120

±10

µA

Disabled, V_O= 0V or V_CC

(Note 9)

2.0

V_CC

0.8

Input Low Voltage

Gnd

Input Current

V_I= V_CCor 0V,

±10

µA

Other Input = V_CCor Gnd

V_Cl

I_CC

Input Clamp Voltage

I_Cl= -18mA

-1.5

1, 2, 3

No Load Supply Current

Receivers Enabled

En, En* = V_CCor Gnd,

Inputs Open

En, En* = 2.4 or 0.5,

Inputs Open

1, 2, 3

I_CCZ

No Load Supply Current

Receivers Disabled

En = Gnd, En* = V_CC

Inputs Open

5.0

AC Parameters

The following conditions apply, unless otherwise specified.

AC:

V_CC= 3.15 / 3.3 / 3.45V, C_L= 20pF

Sub-

groups

Symbol

Parameter

Conditions

Notes

Min Max

Units

t_PHLD

Differential Propagation Delay

High to Low

V_ID= 200mV,

Fig 1 & 2

0.5

3.5

9, 10, 11

Input pulse = 1.1V to 1.3V,

V_I= 1.2V (0V differential) to

V_O= 1/2 V_CC

t_PLHD

Differential Propagation Delay

Low to High

V_ID= 200mV,

Fig 1 & 2

0.5

3.5

9, 10, 11

Input pulse = 1.1V to 1.3V,

V_I= 1.2V (0V differential) to

V_O= 1/2 V_CC

t_SkD

t_Sk1

t_Sk2

t_PLZ

Differential Skew |t_PHLD- t_PLHD

Channel to Channel Skew

Chip to Chip Skew

C_L= 20pF, V_ID= 200mV

Fig 1 & 2

(Note 7)

(Note 5)

Fig 3 & 4

1.5

1.75

3.0

9, 10, 11

Disable Time Low to Z

Input pulse = 0V to 3.0V,

V_I= 1.5V, V_O= V_OL+0.5V,

R_L= 1kΩ.

www.ti.com

Sub-

groups

Symbol

t_PHZ

Parameter

Conditions

Notes

Min Max

Units

Disable Time High to Z

Input pulse = 0V to 3.0V,

V_I= 1.5V, V_O= V_OH-0.5V,

Fig 3 & 4

9, 10, 11

R_L= 1kΩ.

t_PZH

Enable Time Z to High

Enable Time Z to Low

Input pulse = 0V to 3.0V,

V_I= 1.5V, V_O= 50%,

Fig 3 & 4

R_L= 1kΩ.

t_PZL

Input pulse = 0V to 3.0V,

V_I= 1.5V, V_O= 50%,

R_L= 1kΩ.

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device

is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: Derate @ 6.8mW/°C

Note 3: Human body model, 1.5 kΩ in series with 100 pF.

Note 4: Tested during V_OH/V_OLtests by applying appropriate voltage levels to the input pins of the device under test.

Note 5: Chip to chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.

Note 6: The VCMR range is reduced for larger V_ID. Example: if V_ID= 400mV, the VCMR is 0.2V to 2.2V. The fail-safe condition with inputs shorted is valid over

a common-mode range of 0V to 2.3V. A V_IDup to V_CC− 0V may be applied to the R_IN+/ R_I−inputs with the Common-Mode voltage set to V_CC/2. Propagation delay

and Differential Pulse skew decrease when V_IDis increased from 200mV to 400mV. Skew specifications apply for 200mV ≤ V_ID≤ 800mV over the common-

mode range .

Note 7: Channel-to-Channel Skew, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any

event on the inputs.

Note 8: Output short circuit current (I_OS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not

exceed maximum junction temperature.

Note 9: Tested during I_OZtests by applying appropriate threshold voltage levels to the En and En* pins.

Note 10: FOR ADDITIONAL DIE INFORMATION, PLEASE VISIT THE HI REL WEB SITE AT: www.national.com/analog/space/level_die

Parameter Measurement Information

20163903

FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit

20163904

FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms

www.ti.com

20163905

C_Lincludes load and test jig capacitance.

S₁= V_CCfor t_PZL, and t_PLZmeasurements.

S₁= Gnd for t_PZHand t_PHZmeasurements.

FIGURE 3. Receiver TRI-STATE Delay Test Circuit

20163906

FIGURE 4. Receiver TRI-STATE Delay Waveforms

Typical Performance Characteristics

20163909

20163908

FIGURE 6. Typical Common-Mode Range variation with

respect to amplitude of differential input

FIGURE 5. I_CCvs Frequency, four channels switching

www.ti.com

20163910

20163911

FIGURE 7. Typical Pulse Skew variation versus common-

mode voltage

FIGURE 8. Variation in High to Low Propagation Delay

versus V_CM

20163912

FIGURE 9. Variation in Low to High Propagation Delay versus V_CM

Typical Application

Balanced System

20163907

FIGURE 10. Point-to-Point Application

www.ti.com

noise induced on the differential lines is much more likely to

appear as common-mode which is rejected by the receiver.

Applications Information

General application guidelines and hints for LVDS drivers and

receivers may be found in the following application notes:

www.national.com/lvds.

Match electrical lengths between traces to reduce skew.

Skew between the signals of a pair means a phase difference

between signals which destroys the magnetic field cancella-

tion benefits of differential signals and EMI will result. (Note

the velocity of propagation, v = c/Er where c (the speed of

light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on

the autoroute function for differential traces. Carefully review

dimensions to match differential impedance and provide iso-

lation for the differential lines. Minimize the number of vias

and other discontinuities on the line.

LVDS drivers and receivers are intended to be primarily used

in an uncomplicated point-to-point configuration as is shown

in Figure 10. This configuration provides a clean signaling

environment for the fast edge rates of the drivers . The re-

ceiver is connected to the driver through a balanced media

which may be a standard twisted pair cable, a parallel pair

cable, or simply PCB traces. Typically the characteristic

impedance of the media is in the range of 100Ω. A termination

resistor of 100Ω should be selected to match the media, and

is located as close to the receiver input pins as possible. The

termination resistor converts the driver output (current mode)

into a voltage that is detected by the receiver. Other configu-

rations are possible such as a multi-receiver configuration,

but the effects of a mid-stream connector(s), cable stub(s),

and other impedance discontinuities as well as ground shift-

ing, noise margin limits, and total termination loading must be

taken into account.

Avoid 90° turns (these cause impedance discontinuities). Use

arcs or 45° bevels.

Within a pair of traces, the distance between the two traces

should be minimized to maintain common-mode rejection of

the receivers. On the printed circuit board, this distance

should remain constant to avoid discontinuities in differential

impedance. Minor violations at connection points are allow-

able.

TERMINATION

The DS90LV032A differential line receiver is capable of de-

tecting signals as low as 100 mV, over a ±1V common-mode

range centered around +1.2V. This is related to the driver off-

set voltage which is typically +1.2V. The driven signal is

centered around this voltage and may shift ±1V around this

center point. The ±1V shifting may be the result of a ground

potential difference between the driver's ground reference

and the receiver's ground reference, the common-mode ef-

fects of coupled noise, or a combination of the two. Both

receiver input pins have a recommended operating input volt-

age range of 0V to +2.4V (measured from each pin to ground),

exceeding these limits may turn on the ESD protection cir-

cuitry which will clamp the bus voltages.

Use a resistor which best matches the differential impedance

of your transmission line. The resistor should be between

90Ω and 130Ω. Remember that the current mode outputs

need the termination resistor to generate the differential volt-

age. LVDS will not work without resistor termination. Typical-

ly, connect a single resistor across the pair at the receiver end.

Surface mount 1% to 2% resistors are best. PCB stubs, com-

ponent lead, and the distance from the termination to the

receiver inputs should be minimized. The distance between

the termination resistor and the receiver should be <10mm

(12mm MAX)

PROBING LVDS TRANSMISSION LINES

Always use high impedance (> 100kΩ), low capacitance

(< 2 pF) scope probes with a wide bandwidth (1 GHz) scope.

Improper probing will give deceiving results.

POWER DECOUPLING RECOMMENDATIONS

Bypass capacitors must be used on power pins. High fre-

quency ceramic (surface mount is recommended) 0.1μF in

parallel with 0.01μF, in parallel with 0.001μF at the power

supply pin as well as scattered capacitors over the printed

circuit board. Multiple vias should be used to connect the de-

coupling capacitors to the power planes A 10μF (35V) or

greater solid tantalum capacitor should be connected at the

power entry point on the printed circuit board.

CABLES AND CONNECTORS, GENERAL COMMENTS

When choosing cable and connectors for LVDS it is important

to remember:

Use controlled impedance media. The cables and connectors

you use should have a matched differential impedance of

about 100Ω. They should not introduce major impedance dis-

continuities.

PC BOARD CONSIDERATIONS

Balanced cables (e.g. twisted pair) are usually better than

unbalanced cables (ribbon cable, simple coax.) for noise re-

duction and signal quality. Balanced cables tend to generate

less EMI due to field canceling effects and also tend to pick

up electromagnetic radiation as common-mode (not differen-

tial mode) noise which is rejected by the receiver. For cable

distances < 0.5M, most cables can be made to work effec-

tively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (category 3)

twisted pair cable works well, is readily available and relatively

inexpensive.

Use at least 4 PCB layers (top to bottom); LVDS signals,

ground, power, TTL signals.

Isolate TTL signals from LVDS signals, otherwise the TTL

may couple onto the LVDS lines. It is best to put TTL and

LVDS signals on different layers which are isolated by a pow-

er/ground plane(s).

Keep drivers and receivers as close to the (LVDS port side)

connectors as possible.

DIFFERENTIAL TRACES

Use controlled impedance traces which match the differential

impedance of your transmission medium (ie. cable) and ter-

mination resistor. Run the differential pair trace lines as close

together as possible as soon as they leave the IC (stubs

should be < 10mm long). This will help eliminate reflections

and ensure noise is coupled as common-mode. Lab experi-

ments show that differential signals which are 1mm apart

radiate far less noise than traces 3mm apart since magnetic

field cancellation is much better with the closer traces. Plus,

FAIL-SAFE FEATURE

The LVDS receiver is a high gain, high speed device that am-

plifies a small differential signal (20mV) to CMOS logic levels.

Due to the high gain and tight threshold of the receiver, care

should be taken to prevent noise from appearing as a valid

signal.

The receiver's internal fail-safe circuitry is designed to source/

sink a small amount of current, providing fail-safe protection

www.ti.com

(a stable known state of HIGH output voltage) for floating,

terminated or shorted receiver inputs.

2.4V). It is only supported with inputs shorted and no

external common-mode voltage applied.

1. Open Input Pins. The DS90LV032A is a quad receiver

device, and if an application requires only 1, 2 or 3

receivers, the unused channel(s) inputs should be left

OPEN. Do not tie unused receiver inputs to ground or any

other voltages. The input is biased by internal high value

pull up and pull down resistors to set the output to a HIGH

state. This internal circuitry will guarantee a HIGH, stable

output state for open inputs.

External lower value pull up and pull down resistors (for a

stronger bias) may be used to boost fail-safe in the presence

of higher noise levels. The pull up and pull down resistors

should be in the 5kΩ to 15kΩ range to minimize loading and

waveform distortion to the driver. The common-mode bias

point should be set to approximately 1.2V (less than 1.75V)

to be compatible with the internal circuitry.

The footprint of the DS90LV032A is the same as the industry

standard 26LS32 Quad Differential (RS-422) Receiver.

2. Terminated Input. If the driver is disconnected (cable

unplugged), or if the driver is in a TRI-STATE or power-

off condition, the receiver output will again be in a HIGH

state, even with the end of cable 100Ω termination

resistor across the input pins. The unplugged cable can

become a floating antenna which can pick up noise. If the

cable picks up more than 10mV of differential noise, the

receiver may see the noise as a valid signal and switch.

To insure that any noise is seen as common-mode and

not differential, a balanced interconnect should be used.

Twisted pair cable will offer better balance than flat ribbon

cable.

Pin Descriptions

Pin No. Name

Description

2, 6,

10, 14

1, 7,

9, 15

3, 5,

11, 13

R_I+Non-inverting receiver input pin

R_I−Inverting receiver input pin

R_OReceiver output pin

3. Shorted Inputs. If a fault condition occurs that shorts

the receiver inputs together, thus resulting in a 0V

Active high enable pin, OR-ed with En*

En* Active low enable pin, OR-ed with En

V_CCPower supply pin, +3.3V ± 0.3V

Gnd Ground pin

differential input voltage, the receiver output will remain

in a HIGH state. Shorted input fail-safe is not supported

across the common-mode range of the device (GND to

Truth Table

ENABLES

INPUTS

R_I+− R_I−

OUTPUT

En*

R_O

V_ID≥ 0.1V

V_ID≤ −0.1V

All other combinations of enable inputs

Full Fail-safe Open/Short or

Terminated

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Revision History Section

Released

Revision

Section

Originator

Changes

New Release, Corporate format

L. Lytle

1 MDS data sheet converted into one Corp.

data sheet format. MNDS90LV032A-X Rev

0D0 will be archived.

15–Nov-2011

Ordering Information, Quality

Conformance Inspection, AC

Parameters, Applications Information

Addeded Part Numbers

Kruckmeyer DS90LV032AWGMLS and DS90LV032AW-

MLS along with DS90LV032 MDS and

associated footnote reference to Ordering

Information. Added missing '+' sign on the

Temp's for 25 and 125 deg C from QCI section.

For AC Parameters changed units from nS to

ns, changed 1K to 1k and added Fig 1, 2, 3 and

4 as needed for notes. Added Note 10 for die

sales. For Application Information change

minor typo errors under several sections.

Revision A will be archived.

www.ti.com

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Ceramic Flatpack

NS Package Number W16A

16-Lead Ceramic SOIC

NS Package Number WG16A

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Notes

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Notes

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DS90LV032AQML [TI]

相关型号：

DS90LV032AQML-SP

DS90LV032ATM

DS90LV032ATM

DS90LV032ATM/NOPB

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