DS90LVRA2 [TI]
1.8V、600Mbps LVDS 双路差分线路接收器;
| 型号： | DS90LVRA2 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.8V、600Mbps LVDS 双路差分线路接收器 |
| 文件： | 总19页 (文件大小：1239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90LVRA2
ZHCSRF0 –DECEMBER 2022
DS90LVRA2 LVDS 双路差分线路接收器
1 特性
3 说明
• 600Mbps (300MHz) 转换速率
• 50ps 差分延迟（典型值）
• 0.1ns 通道间延迟（典型值）
• 1.8V 电源
• 直通引脚排列
• 在断电模式下，LVDS 输入端具有高阻抗
• 输出压摆率控制
• LVDS 输入可接受LVDS/CML/LVPECL 信号
• 符合ANSI/TIA/EIA-644 标准
• 引脚与DS90LV028A-Q1 兼容
• OPN 型号
DS90LVRA2 是一款专为需要高输入共模范围、高数据
速率和具有压摆率控制 CMOS 输出的应用而设计的双
路 CMOS 差分线路接收器。该器件旨在利用低电压差
分信号 (LVDS) 技术支持 600Mbps (300MHz) 的数据
速率。
DS90LVRA2 可接受低电压（350mV 典型值）差分输
入信号，并根据电源电压将其转换为1.8V CMOS 输出
电平。DS90LVRA2 采用直通式设计，可简化 PCB 布
局。
DS90LVRA2 和 配 套 的 LVDS 线 路 驱 动 器
DS90LV027AQ 可为高速点对点接口应用提供针对高
功耗PECL/ECL 器件的全新替代方案。
– 标准：0°C 至70°C
– 工业：-40°C 至+85°C
封装信息(1)
2 应用
封装尺寸（标称值）
器件型号
DS90LVRA2
封装
• 通信设备
• 企业系统
• 工业
DEM（WSON，8） 2.00mm × 2.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 个人电子产品
RIN1-
RIN1+
RIN2-
RIN2+
R
ROUT1
R
ROUT2
功能图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNLS728
DS90LVRA2
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Table of Contents
8.4 Device Functional Modes............................................9
9 Application and Implementation..................................10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
9.3 Application Curves.................................................... 11
10 Power Supply Recommendations..............................11
11 Layout........................................................................... 11
11.1 Layout Guidelines....................................................11
11.2 Layout Examples.....................................................12
12 Device and Documentation Support..........................13
12.1 Documentation Support.......................................... 13
12.2 接收文档更新通知................................................... 13
12.3 支持资源..................................................................13
12.4 Trademarks.............................................................13
12.5 静电放电警告.......................................................... 13
12.6 术语表..................................................................... 13
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................5
6.7 Typical Characteristics................................................7
7 Parameter Measurement Information............................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
8.3 Feature Description.....................................................9
Information.................................................................... 13
4 Revision History
DATE
REVISION
NOTES
December 2022
*
Initial Release
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5 Pin Configuration and Functions
RIN1-
8
7
6
5
1
2
3
4
VCC
RIN1+
ROUT
1
RIN2+
RIN2-
ROUT
2
GND
图5-1. DEM Package, WSON 8 Pin (Top View)
表5-1. Pin Functions
DESCRIPTION
PIN
TYPE(1)
NAME
GND
NO.
5
G
I
Ground pin
RIN1-
RIN2-
RIN1+
RIN2+
1
Inverting receiver input pin
4
I
2
I
Non-inverting receiver input pin
3
I
ROUT
ROUT
VCC
2
6
O
O
P
Receiver output pin
Power supply pin
1
7
8
(1) I = input, O = output, G = ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)((1))
MIN
–0.3
–5
MAX
4
UNIT
V
Supply Voltage (VCC
)
6
V
Input Voltage (RIN+, RIN−)
0
3
V
Differential Voltage (RIN+ - RIN−) for LVDS
Output Voltage (ROUT
)
1.98
260
135
150
V
–0.3
Lead Temperature Range Soldering
Maximum Junction Temperature
Storage temperature, Tstg
(4 sec.)
°C
°C
°C
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, and performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
±5000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JS-002((2))
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. .
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.62
0
NOM
MAX
1.98
3.0
70
UNIT
V
VCC
VR
Supply voltage (1.8 V mode)
1.80
Receiver input voltage (LVDS)
Operating free-air temperature (Standard)
Operating free-air temperature (Industrial)
PCB temperature (Standard)
V
TA
0
°C
°C
°C
°C
°C
°C
TA
85
–40
TPCB
TPCB
TJ
80
PCB temperature (Industrial)
95
Junction temperature (Standard)
Junction temperature (Industrial)
95
TJ
110
6.4 Thermal Information
DEM
THERMAL METRIC(1)
(WSON)
8 PINS
143.7
77.9
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-board thermal resistance
69.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
5.0
69.6
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Positive-going differential input
voltage threshold
VITH
100
VIB = -1 V or 2 V, VCC = 1.62 V to 1.98 V
mV
Negative-going differential input
VITL
voltage
threshold
-100
20
Differential input voltage
hysteresis,
VIT1 –VIT2
VCC = 1.62 V to 1.98 V
VCC = 1.62 - 1.98 V
VHYS
40
90
2
mV
V
Input common mode voltage
range
VCM_RANGE
-1
1.2
VOH_1V8
VOL_1V8
High-level output voltage
Low-level output voltage
1.3
V
V
IOH = –4 mA, VCC=1.8 V ±10%
IOL = 4 mA, VCC=1.8 V ±10%
0.2
25
VCC = 1.98 V, No load, Steady-state,
VID=200 mV/-200 mV
ICC_ACTIVE
Supply current
mA
µA
µA
µA
µA
Input current
(A or B inputs)
II
VI = -1.0 V, Other input open
VI = 2.0 V, Other input open
VY or VZ = 1.98 V, VCC = 0 V
VA or VB = -1 V or 2.0 V, VCC = 0 V
±35
±20
±20
±35
Input current
(A or B inputs)
II
Power-off output current
(Y or Z outputs)
II(OFF)
II(OFF)
Power-off input current
(A or B inputs)
(1) All typical values are at 25°C and with a 1.8 V supply.
6.6 Switching Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(2) (3) (4)
Symbol
tPHLD_1p8
tPHLD_1p8_5
tPLHD_1p8
Parameter
Conditions
MIN
TYP
MAX UNIT
VID = 200 mV, CL = 10 pF,
trf=1 ns, VCC 1.8 V ±10%
Differential Propagation Delay High to Low
2.7
2.8
4.3
7.7
7.1
7.7
7.1
500
400
ns
ns
ns
ns
ps
ps
VID = 200 mV, CL = 10 pF,
trf=1 ns, VCC 1.8 V ±5%
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
4.3
4.4
4.4
VID = 200 mV, CL = 10 pF,
trf=1 ns, VCC 1.8 V ±10%
2.7
VID = 200 mV, CL = 10 pF,
trf=1 ns, VCC 1.8 V ±5%
tPLHD_1p8_5
tSKD1_1p8_S
tSKD1_1p8_5_S
Differential Propagation Delay Low to High
2.8
VID = 200 mV, CL = 10 pF,
trf=1 ns, VCC=1.8 V±10%
((7))
-500
-400
Differential Pulse Skew (tPHLD –tPLHD
Differential Pulse Skew (tPHLD –tPLHD
)
VID = 200 mV, CL = 10 pF,
trf=1 ns, VCC=1.8 V±5%
((7))
((7))
)
VID = 200 mV, CL = 10 pF,
trf=0.25 ns DR=400M,
VCC=1.8 V±10%
tSKD1_1p8_S_400
-500
-400
500
400
0.5
ps
ps
ns
Differential Pulse Skew (tPHLD –tPLHD
)
M
VID = 200 mV, CL = 10 pF,
trf=0.25 ns
DR=400M,VCC=1.8
V±5%
tSKD1_1p8_5_S_4
((7))
Differential Pulse Skew (tPHLD –tPLHD
)
00M
VID = 200 mV, CL = 10 pF,
trf=0.25 ns VCC=1.8
V±10%
tSKD2_1p8
Differential Channel-to-Channel Skew-same device (6)
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MAX UNIT
6.6 Switching Characteristics (continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(2) (3) (4)
Symbol
Parameter
Conditions
MIN
TYP
VID = 200 mV, CL = 10 pF,
trf=0.25 ns VCC=1.8
V±5%
tSKD2_1p8_5
Differential Channel-to-Channel Skew-same device ((8))
0.4
2.7
ns
ns
VID = 200 mV, CL = 10 pF,
trf=0.25 ns VCC=1.8
V±5% at same
tSKD3_1p8_5
Differential Part to Part Skew ((9))
temperature
VID = 200 mV, CL = 10 pF,
trf=0.25 ns VCC=1.8
V±5% at TJ =25℃
tSKD3_1p8_5_25C Differential Part to Part Skew ((9))
tSKD3_1p8_5_70C Differential Part to Part Skew ((9))
2.6
2.7
2.7
ns
ns
ns
VID = 200 mV, CL = 10 pF,
trf=0.25 ns VCC=1.8
V±5% at TJ =70℃
VID = 200 mV, CL = 10 pF,
trf=0.25 ns VCC=1.8
V±5% at TJ= 125℃
tSKD3_1p8_5_125
Differential Part to Part Skew ((9))
C
tTLH_1p8
tTHL_1p8
fMAX
Rise Time
250
250
300
500
500
720
720
ps
ps
Fall Time
Maximum Operating Frequency ((11))
MHz
(1) “Absolute Maximum Ratings”are those values beyond which the safety of the device cannot be ensured. They are not meant to
imply that the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation.
(2) All typicals are given for: VCC = 1.8V and TA = +25°C.
(3) CL includes probe and jig capacitance.
(4) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0% to 100%) ≤3 ns for RIN.
(5) tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge
of the same channel.
(6) tSKD2 is the differential channel-to-channel skew of any event on the same device. This specification applies to devices having multiple
receivers within the integrated circuit.
(7) tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
at the same VCC and within 5°C of each other within the operating temperature range.
(8) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria:
60%/40% duty cycle, VOL (max), VOH (min), load = 15 pF (stray plus probes).
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6.7 Typical Characteristics
Typical power supply current -vs- data rate (VCC 1.8 V, 5 pF output load, 2 channels)
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7 Parameter Measurement Information
图7-1. Receiver Propagation Delay and Transition Time Test Circuit
图7-2. Receiver Propagation Delay and Transition Time Waveforms
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8 Detailed Description
8.1 Overview
图 9-1 shows how LVDS drivers and receivers are intended to be primarily used in a simple point-to-point
configuration. This configuration provides a clean signaling environment for the fast edge rates of the drivers.
The receiver is connected to the source through a impedance controlled 100 Ω differential PCB traces. A
termination resistor of 100 Ω should be used, and is located as close to the receiver input pins as possible. The
termination resistor converts the driver output (current mode) into a voltage that is detected by the receiver.
8.2 Functional Block Diagram
RIN1-
R
ROUT1
RIN1+
RIN2-
RIN2+
R
ROUT2
8.3 Feature Description
The DS90LVRA2 differential line receiver is capable of detecting signals as low as 100 mV, over a common-
mode range of −1 V to 2 V (VCC at 1.8 V). This is related to the driver offset voltage which is typically +1.2 V. The
driven signal is centered around this voltage and may shift around this center point. The shifting may be the
result of a ground potential difference between the driver's ground reference and the receiver's ground
reference, the common-mode effects of coupled noise, or a combination of the two. The AC parameters of both
receiver input pins are optimized for a recommended operating input voltage range of +0 V to +3 V (measured
from each pin to ground).
8.4 Device Functional Modes
表8-1. Truth Table
INPUTS
[RIN+] − [RIN−]
VID ≥0.1 V
OUTPUT
ROUT
H
L
VID ≤−0.1 V
(1)
?
−0.1 V ≤VID ≤0.1 V
(1) ? indicates state is indeterminate
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
For general application guidelines and hints about LVDS drivers and receivers, refer to the LVDS application
notes and design guides.
9.2 Typical Application
½ DS90LVRX2
图9-1. Balanced System Point-to-Point Application
9.2.1 Design Requirements
When using LVDS devices, it is important to remember to specify controlled impedance PCB traces. All
components of the transmission media must have a matched differential impedance of 100 Ω. They must not
introduce major impedance discontinuities.
9.2.2 Detailed Design Procedure
9.2.2.1 Power Decoupling Recommendations
Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)
0.1 μF and 0.01 μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to
the device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling.
Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10 μF (35 V) or
greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board
between the supply and ground.
9.2.2.2 Termination
Use a termination resistor which best matches the differential impedance or your transmission line. The resistor
should be between 90 Ω and 110 Ω. Remember that the current mode outputs need the termination resistor to
generate the differential voltage. LVDS will not work correctly without resistor termination. Typically, connecting a
single resistor across the pair at the receiver end will suffice.
Surface mount 1% resistors are the best. PCB stubs, component lead, and the distance from the termination to
the receiver inputs should be minimized. The distance between the termination resistor and the receiver should
be < 10 mm (12 mm maximum).
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9.2.2.3 Input Failsafe Biasing
External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe
under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor
and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors
should be in the 5 kΩ to 15 kΩ range to minimize loading and waveform distortion to the driver. The common-
mode bias point ideally should be set to approximately 1.2 V to be compatible with the internal circuitry. For more
information, refer to application note AN-1194 Failsafe Biasing of LVDS Interfaces.
9.2.2.4 Probing LVDS Transmission Lines
Always use high impedance (> 100 kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
9.3 Application Curves
图9-2. Typical Propagation Delay -vs- Temperature (VCC 1.8 V, 10 pF Output Load, Average of 2
Channels)
10 Power Supply Recommendations
Bypass capacitors must be used on power pins. TI recommends using high-frequency, ceramic, 0.1-µF and
0.01-µF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device
supply pin. Additional scattered capacitors over the printed-circuit board improves decoupling. Multiple vias must
be used to connect the decoupling capacitors to the power planes. A 10-µF bulk capacitor, 35-V (or greater)
solid tantalum capacitor must be connected at the power entry point on the printed-circuit board between the
supply and ground.
11 Layout
11.1 Layout Guidelines
11.1.1 Differential Traces
Use controlled impedance traces which match the differential impedance of your transmission trace and
termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the
IC (stubs should be < 10 mm long). This will help eliminate reflections and ensure noise is coupled as common-
mode. In fact, we have seen that differential signals which are 1 mm apart radiate far less noise than traces 3
mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise induced on
the differential lines is much more likely to appear as common-mode which is rejected by the receiver.
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Match electrical lengths between traces to reduce skew. It is important to note: skew between the signals of a
pair means a phase difference between signals which destroys the magnetic field cancellation benefits of
differential signals and EMI will result. (Note that the velocity of propagation, v = c/E r where c (the speed of light)
= 0.2997 mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Carefully
review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the
number of vias and other discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode
rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid
discontinuities in differential impedance. Minor violations at connection points are allowable.
11.1.2 PC Board Considerations
Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, and TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL signals may couple onto the LVDS lines. It is best to
put TTL and LVDS signals on different layers which are isolated by one or more power or ground planes.
11.2 Layout Examples
Di eren al 100 Ω
Single ended 50 Ω
图11-1. EVM Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Failsafe Biasing of LVDS Interfaces application note
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
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13
Product Folder Links: DS90LVRA2
English Data Sheet: SNLS728
PACKAGE OPTION ADDENDUM
www.ti.com
31-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
D9LVRA2DEMR
D9LVRA2DEMT
D9LVRA2IDEMR
D9LVRA2IDEMT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
DEM
DEM
DEM
DEM
8
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
LR2
LR2
LR2
LR2
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
-40 to 85
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Dec-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
DEM0008A
WSON - 0.8 mm max height
S
C
A
L
E
6
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.05 C
0.05
0.00
SYMM
(0.2) TYP
4
5
SYMM
2X 1.5
6X 0.5
8
1
0.3
8X
0.2
0.1
0.05
PIN 1 ID
(45 X 0.125)
C A B
0.85
0.65
8X
4228323/A 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DEM0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SEE SOLDER MASK
DETAIL
SYMM
8X (0.95)
8
8X (0.25)
1
SYMM
6X (0.5)
(R0.05) TYP
4
5
(1.45)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4228323/A 12/2021
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DEM0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.95)
8X (0.25)
1
8
SYMM
6X (0.5)
(R0.05) TYP
5
4
SYMM
(1.45)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 30X
4228323/A 12/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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