DS90UB638TRGZTQ1 [TI]
具有单个 CSI-2 输出端口的汽车级 4.16Gbps FPD-Link III 解串器 | RGZ | 48 | -40 to 105;
| 型号： | DS90UB638TRGZTQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有单个 CSI-2 输出端口的汽车级 4.16Gbps FPD-Link III 解串器 | RGZ | 48 | -40 to 105 光电二极管 |
| 文件： | 总141页 (文件大小：3911K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS90UB638-Q1
ZHCSOU1 –FEBRUARY 2023
DS90UB638-Q1 具有MIPI CSI-2 输出的FPD-Link III 4.16Gbps 单输入解串器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
DS90UB638-Q1 是一款多功能解串器，可通过 FPD-
Link III 接口从一个源接收串行传感器数据。与
DS90UB635-Q1 串行器配合使用时，DS90UB638-Q1
接收来自成像仪的数据，支持 2MP/60fps 和 4MP/
30fps 摄像头以及卫星雷达和其他传感器（如ToF 和激
光雷达）。接收的数据在符合 MIPI CSI-2 标准的输出
端呈现，从而与下游处理器互连。为 2 通道运行配置
CSI-2 接口时，会提供一个完全相同的 MIPI CSI-2 时
钟通道，以提供复制输出。复制模式可创建两个接收视
频流副本，用于数据记录和并行处理。
– 器件温度等级2：-40℃至+105℃环境工作温
度范围
• 符合ISO 10605 和IEC 61000-4-2 ESD 标准
• 同轴电缆供电(PoC) 兼容收发器
• 符合MIPI DPHY 版本1.2/CSI-2 版本1.3 标准
– CSI-2 数据速率可扩展：每个数据通道支持
400Mbps/800Mbps/1.5Gbps/1.6Gbps
– 支持1、2、3、4 个数据通道
– 支持多达四个虚拟通道
– 可编程数据类型
DS90UB638-Q1 符合 AEC-Q100 标准，旨在通过
50Ω 单端同轴电缆接收数据。该解串器非常适合同轴
电缆供电应用，接收均衡器会自动适应来补偿电缆损耗
特性（无需额外的编程），包括随时间推移而出现的电
缆老化。
– 高级数据保护和诊断，包括CRC 数据保护、传
感器数据完整性检查、I2C 写保护、远程电压和
温度测量、可编程警报、BIST、图形生成以及
线路故障检测
• 超低数据和控制路径延迟
• 支持单端同轴电缆
• 单输入解串器
• 自适应接收均衡
• 具有快速模式增强版（高达1Mbps）的I2C
• 用于摄像头同步和诊断的灵活GPIO
• 用于防伪认证的唯一芯片ID
• 支持单端同轴或屏蔽双绞线(STP) 电缆
• 与DS90UB635-Q1 和DS90UB633A-Q1 串行器兼
容
每个 FPD-Link III 接口包括一个单独的低延迟双向控制
通道 (BCC)，该通道可连续传送 I2C、GPIO 和其他控
制信息。用于传感器同步和诊断功能的 GPIO 信号也
使用BCC。
器件信息
封装(1)
封装尺寸（标称值）
器件型号
DS90UB638-Q1
VQFN (48)
7.00mm × 7.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
MIPI CSI-2
• 高级驾驶辅助系统(ADAS)
D3P/N
– 自动驾驶汽车(AV)
– 汽车卫星雷达和激光雷达模块
– 摄像头监控系统(CMS)
– 前视摄像头(FC)
– 飞行时间(ToF) 和激光雷达传感器模块
– 环视系统(SVS)
D2P/N
FPD-Link III
Coax
DS90UB635
FPD-Link III
D1P/N
D0P/N
DS90UB638-Q1
Processor
SoC
Serializer
FPD-Link III Deserializer
CLKP/N
I2C
GPIO
– 后视摄像头(RVC)
– 驾驶员监控系统(DMS)
– 侧后视镜显示(SMD)
• 安全和监控
CMLOUT
典型应用原理图
• 工业和医疗成像
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNLS708
DS90UB638-Q1
ZHCSOU1 –FEBRUARY 2023
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Table of Contents
7.5 Programming............................................................ 39
7.6 Unique ID..................................................................52
7.7 Register Maps...........................................................53
8 Application and Implementation................................ 116
8.1 Application Information............................................116
8.2 Typical Application.................................................. 120
8.3 System Examples................................................... 123
9 Power Supply Recommendations..............................124
9.1 VDD and VDDIO Power Supply..............................124
9.2 Power-Up Sequencing............................................124
10 Layout.........................................................................127
10.1 PCB Layout Guidelines.........................................127
10.2 Layout Examples.................................................. 130
11 Device and Documentation Support........................133
11.1 Documentation Support........................................ 133
11.2 支持资源................................................................133
11.3 Trademarks........................................................... 133
11.4 静电放电警告.........................................................133
11.5 术语表................................................................... 133
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 7
6.1 Absolute Maximum Ratings........................................ 7
6.2 ESD Ratings............................................................... 7
6.3 Recommended Operating Conditions.........................8
6.4 Thermal Information....................................................8
6.5 DC Electrical Characteristics ..................................... 9
6.6 AC Electrical Characteristics.....................................11
6.7 AC Electrical Characteristics CSI-2.......................... 12
6.8 Recommended Timing for the Serial Control Bus.....15
6.9 Timing Diagrams.......................................................17
6.10 Typical Characteristics............................................20
7 Detailed Description......................................................21
7.1 Overview...................................................................21
7.2 Functional Block Diagram.........................................22
7.3 Feature Description...................................................22
7.4 Device Functional Modes..........................................22
Information.................................................................. 134
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
February 2023
*
Initial Release
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5 Pin Configuration and Functions
MODE
CMLOUTP
CMLOUTN
CSI_D3P
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
CSI_D3N
CSI_D2P
DAP = GND
CSI_D2N
VDD11_CSI
CSI_CLK1P
VDD18_FPD0
RIN0+
DS90UB638-Q1
48L QFN
RIN0-
VDD11_FPD0
RES0
CSI_CLK1N
VDD18_CSI
CSI_D1P
(Top View)
VDD18_P0
VDD_SEL
CSI_D1N
CSI_D0P
PASS
LOCK
CSI_D0N
图5-1. RGZ Package
48-Pin VQFN
Top View
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表5-1. Pin Functions
PIN
NAME
I/O
TYPE
DESCRIPTION
NO.
RECEIVE DATA CSI-2 OUTPUT
CSI_CLK0N
CSI_CLK0P
CSI_CLK1N
CSI_CLK1P
CSI_D0N
11
12
18
19
13
14
15
16
21
22
23
24
RECEIVE DATA OUTPUT: This signal carries data from the FPD-LINK III Deserializer to the
processor over CSI-2 interface. Receive data is CSI-2 configured with DPHY outputs as one
differential clock lane (CSI_CLK0P/N) and up to four differential data lanes (CSI_D0P/N:
CSI_D3P/N) or two clock lanes (CSI_CLK0P/N, CSI_CLK1P/N) and two differential data lanes
for each clock. When in replicate mode data lanes CSI_D2P/N and CSI_D3P/N are associated
with clock lane CSI_CLK1P/N to provide the replicated output. Leave unused outputs as no
connect.
CSI_D0P
O
CSI_D1N
CSI_D1P
CSI_D2N
CSI_D2P
CSI_D3N
CSI_D3P
CLOCK INTERFACE
Reference clock input or crystal oscillator input. Pin is shared with XIN and REFCLK. Typically
REFCLK connected to 23-MHz to 26-MHz reference oscillator output (100 ppm) or XIN
configured with external 23-MHz to 26-MHz crystal to XOUT. See 节7.4.4.
XIN/REFCLK
XOUT
5
4
S, I
O
Crystal oscillator output: Output Pin for providing crystal oscillator reference. Leave this pin NC
when reference clock input is driving XIN/REFCLK.
SYNCHRONIZATION AND GPIO
GPIO0
GPIO1
GPIO2
GPIO4
GPIO5
GPIO6
28
27
26
10
9
General-Purpose Input/Output: Pins can be used to control and respond to various commands.
They may be configured to be the input signals for the corresponding GPIOs on the serializer, or
they may be configured to be outputs to follow local register settings. At power up, the GPIO are
disabled and include a 35-kΩ(typical) pulldown resistor by default. See 节7.4.12 for
programmability. Unused GPIOs can be left open or no connect.
I/O, PD
I/O, OD
8
General-Purpose Input/Output: Pin GPIO3 can be configured as input signals for GPOs on the
serializer. Pin 25 is shared with INTB. Pul lup with 4.7 kΩto V(VDDIO). The programmable input
and output pin is an active-low open drain and controlled by the status registers. See 节7.4.12
for programmability. Unused GPIO can be left open or no connect.
GPIO3/INTB
25
FPD-LINK III INTERFACE
Receive Input Channel 0: Differential FPD-Link receiver and bidirectional control back channel
output. The IO must be AC-coupled. For applications that use single-ended, coaxial channel,
connect RIN0+ with 33nF, AC-coupling capacitor and terminate RIN0–to GND with a 15nF
capacitor and 50-Ωresistor. For STP applications, connect both RIN0+ and RIN0–with 33nF,
AC-coupling capacitor. If connecting to a DS90UB633A-Q1, please follow the capacitor values
suggested in Design Requirements.
42
41
RIN0–
I/O
RIN0+
I2C PINS
I2C Serial Clock: Clock line for the bidirectional control bus communication.
An external 2-kΩto 4.7-kΩpullup resistor to 1.8-V or 3.3-V supply rail is recommended per I2C
interface standards. I2C_SCL and I2C_SDA inputs are 3.3-V tolerant. See 节7.5.1 for more
information.
I2C_SCL
2
1
I/O, OD
I/O, OD
I2C Serial Data: Data line for bidirectional control bus communication.
An external 2-kΩto 4.7-kΩpullup resistor to 1.8-V or 3.3-V supply rail is recommended per I2C
interface standards. I2C_SCL and I2C_SDA inputs are 3.3-V tolerant. See 节7.5.1 for more
information.
I2C_SDA
CONFIGURATION AND CONTROL PINS1.2
Input. I2C Serial Control Bus Primary Device ID Address Select.
Once enabled, the voltage at this pin will be sampled to configure the default I2C device
address. This pin is typically connected with external pullup resistor to VDD18 and pulldown
resistor to GND to create a voltage divider. See Serial Control Bus Addresses for IDX.
IDX
35
37
S, PD
S, PD
Mode select configuration input to set operating mode based on input voltage level.
This pin is typically connected to voltage divider through an external pullup to VDD18 and
pulldown to GND. 表7-2.
MODE
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表5-1. Pin Functions (continued)
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
Power-down inverted Input Pin. This pin is typically connected to processor GPIO with a
pulldown resistor. When PDB input is brought HIGH, the device is enabled and internal register
and state machines are reset to default values. Asserting PDB signal low will power down the
device and consume minimum power. The default function of this pin is PDB = LOW; POWER
DOWN with internal 50-kΩinternal pulldown enabled. PDB should remain low until after power
supplies are applied and reach minimum required levels. PDB INPUT IS 3.3-V TOLERANT.
See 节9.2 for more information.
PDB
30
I, PD
PDB = 1.8V, device is enabled (normal operation).
PDB = 0 V, device is powered down.
VDD Select: Configuration pin to select internal LDO regulator supply. When VDD_SEL = LOW,
internal 1.1V supply mode is selected. Feed 1.8V to VDD18 inputs = 1.8V ±5%. An internal 1.1V
regulator will supply the VDD11. VDD11 inputs should be terminated with bypass capacitors.
When VDD_SEL = HIGH, external 1.1V supply mode is selected. After 1.8V supply is applied to
VDD18 inputs, then apply 1.1V to VDD11 inputs = 1.1 V ±5%. Voltage at VDD11 supply pins
must always be less than main voltage applied to VDD18 when using external 1.1V
supply. VDD_SEL IS 3.3V TOLERANT.
VDD_SEL
46
S, PD
DIAGNOSTIC PINS
BIST Enable: BISTEN = H, BIST Mode is enabled BISTEN = L, BIST Mode is disabled. If
unused, connect BISTEN directly to GND. See 节7.5.10 for more information.
BISTEN
6
S, PD
O
CMLOUTP
CMLOUTN
38
39
Monitor Loop-Through Driver differential output which supports functional checks. This pin is
typically routed to test points and not connected. For monitoring, CMLOUT should be
terminated with 100-Ωdifferential load. See 节7.4.9 for more information.
LOCK Status: Output Pin for monitoring lock status of FPD-Link III channel that may be used for
Link Status. When LOCK = H, the FPD-Link III receiver is locked and the Rx Port is active.
When LOCK = L, the receiver is unlocked. See 节7.4.7 for more information. Leave pin as no
connect if unused.
LOCK
PASS
48
47
O
O
PASS Output: PASS = H indicates pass conditions are met, and PASS = L indicates that pass
conditions are not met. This pin is typically routed to the processor input pin or test point for
monitoring. See 节7.4.7 for more information. For BIST operation, PASS = H indicates that
ERROR FREE Transmission is in forward channel operation. PASS = L in BIST operation
indicates that one or more errors were detected in the received payload. See 节7.5.10 for more
information. Leave pin as no connect if unused.
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表5-1. Pin Functions (continued)
PIN
NAME
I/O
TYPE
DESCRIPTION
NO.
POWER AND GROUND
DAP is the large metal contact at the bottom side, located at the center of the QFN package.
Connect to the ground plane (GND).
GND
DAP
G
When VDD_SEL = LOW:
Do not connect to 1.1-V power rail
Requires 0.1 to 0.01-µF and minimum 4.7-µF capacitors to GND
When VDD_SEL = HIGH:
Connect to external 1.1-V power rail
Requires a 0.01-μF to GND
VDD11_CSI
20
D, P
D, P
When VDD_SEL = LOW:
Do not connect to 1.1-V power rail
Requires 0.1 to 0.01-µF and minimum 4.7-µF capacitors to GND
When VDD_SEL = HIGH:
VDD11_D
3
Connect to external 1.1-V power rail
Requires a 0.01-μF to GND
When VDD_SEL = LOW:
Do not connect to 1.1-V power rail
Requires 0.1 to 0.01-µF and minimum 4.7-µF capacitors to GND
When VDD_SEL = HIGH:
VDD11_FPD0
43
D, P
Connect to external 1.1-V power rail
Requires a 0.01-μF to GND Requires a 10-μF to GND shared with VDD11_FPD1
See sections 节9and 节8.2 for more information
When VDD_SEL = LOW:
Do not connect to 1.1-V power rail
Requires 0.1 to 0.01-µF and minimum 4.7-µF capacitors to GND
When VDD_SEL = HIGH:
Connect to external 1.1-V power rail
VDD11_FPD1
VDD18_CSI
34
17
D, P
Requires a 0.01-μF to GND Requires a 10-μF to GND shared with VDD11_FPD0
1.8-V (±5%) Power Supply.
See 节8.2 for decoupling capacitor requirements.
P
P
P
1.8-V (±5%) Power Supplies.
See 节8.2 for decoupling capacitor requirements.
VDD18_P0
VDD18_P1
45
36
1.8-V (±5%) Analog Power Supplies.
See 节8.2 for decoupling capacitor requirements.
VDD18_FPD0
VDD18_FPD1
40
31
VDDIO voltage supply input. The single-ended outputs and control input are powered from
VDDIO. VDDIO can be connected to either a 1.8-V or 3.3-V supply rail. When VDDIO is
connected to 1.8-V supply, VDDIO must be within ±100 mV of VDD18 to ensure the output
timing requirements are met. See 节8.2 for decoupling capacitor requirements.
VDDIO
7, 29
P
OTHER
RES0
RES1
RES2
44
32,
33
PD
—
RES0 must be tied to GND for normal operation.
These pins should be left floating.
These pins should be left floating.
—
The definitions below define the functionality of the I/O cells for each pin. TYPE:
•
•
•
•
I = Input
O = Output
I/O = Input/Output
S = Configuration pin (All strap pins have internal pulldowns. If the default strap value is needed to be changed then use an external
resistor.)
•
•
•
•
PD = Internal pulldown
OD = Open Drain
P, G = Power supply, ground
D = Decoupling pin for internal voltage rail
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
UNIT
VDD18 (VDD18_CSI, VDD18_P1 , VDD18_P0 , VDD18_FPD0, VDD18_FPD1)
VDD11 (VDD11_CSI, VDD11_D , VDD11_FPD0, VDD11_FPD1)
2.16
V
–0.3
1.32
and <
Supply voltage
V
–0.3
V(VDD18)
VDDIO
3.96
2.75
V
V
–0.3
–0.3
Device powered up (VDD18, VDD11 and VDDIO within recommended
operating conditions)
RIN0+,
RIN0–,
Device powered down (VDD18, VDD11 and VDDIO below
recommended operating conditions) Transient Voltage
FPD-Link III input voltage
1.45
1.35
V
V
–0.3
–0.3
Device powered down (VDD18, VDD11 and VDDIO below
recommended operating conditions) DC Voltage
GPIO0, GPIO1, GPIO2, GPIOI4, GPIO5, GPIO6, XIN/REFCLK, VDD_SEL, XOUT,
BISTEN, LOCK, PASS, CSI_D3P/N, CSI_D2P/N, CSI_D1P/N, CSI_D0P/N,
CSI_CLK1P/N, CSI_CLK0P/N
V(VDDIO)
+
V
–0.3
0.3
LVCMOS IO voltage
PDB
3.96
V
V
–0.3
–0.3
–0.3
V(VDD18)
+
Configuration input voltage
MODE, IDX
0.3
Open-drain voltage
GPIO3/INTB, I2C_SDA, I2C_SCL
3.96
150
150
V
Junction temperature
Storage temperature, Tstg
°C
°C
–65
(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office or Distributors for availability
and specifications.
(2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±4500
±8000
±1250
UNIT
All pins except 32, 33, 41 and 42
Pins 32, 33, 41 and 42
Human body model (HBM), per AEC
Q100-002(1)
Charged device model (CDM), per AEC Q100-011
Contact Discharge
(RIN0+, RIN0-)
±8000
±18000
±8000
IEC 61000-4-2, powered-up only
RD = 330 Ω , CS = 150 pF
V(ESD)
Electrostatic discharge
V
Air Discharge
(RIN0+, RIN0-)
Contact Discharge
(RIN0+, RIN0-)
ISO 10605
RD= 330 Ω, CS= 150 pF and 330 pF
RD= 2 kΩ, CS= 150 pF and 330 pF
Air Discharge
(RIN0+, RIN0-)
±18000
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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MAX UNIT
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
1.71
1.045
-50
NOM
1.8
V(VDD18)
1.89
1.155
50
V
V
Supply voltage
V(VDD11) (VDD_SEL = HIGH ONLY)
1.1
Supply voltage offset
V(VDD11) - V(VDDIO), V(VDDIO) = 1.8V
mV
V
1.71
3
1.8
3.3
1.89
3.6
V(VDDIO) = 1.8 V
OR V(VDDIO) = 3.3 V
LVCMOS supply voltage
V
Open-drain voltage
GPIO3/INTB = V(INTB), I2C_SDA, I2C_SCL = V(I2C)
1.71
–40
368
184
23
3.6
V
Operating free-air temperature, TA
MIPI data rate (per CSI-2 lane)
MIPI CSI-2 HS clock frequency
Reference clock oscillator frequency
25
105
°C
1664 Mbps
832 MHz
26 MHz
REFCLK or XIN/XOUT
Center Spread
-0.5
-1
0.5
0
%
%
Spread-spectrum reference clock modulation percentage
Local I2C frequency, fI2C
Down Spread
1
MHz
V(VDD11)
25 mVP-P
50 mVP-P
V(VDD18)
Supply noise(1)
V(VDDIO) = 1.8 V
V(VDDIO) = 3.3 V
RIN0+
50
mVP-P
100
10
mVP-P
(1) DC-50 MHz
6.4 Thermal Information
DS90UB638-Q1
THERMAL METRIC(1)
RGC (VQFN)
48 PINS
30.2
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(TOP)
RθJC(BOT)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
15.7
1.1
6.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.2
ψJT
6.7
ψJB
(1) Thermal data in accordance with JESD51. For more information about traditional and new thermal metrics, see the Semiconductor and
IC Package Thermal Metrics application report, SPRA953.
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6.5 DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PIN OR
FREQUENCY
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TOTAL POWER CONSUMPTION
FPD-Link III Input, FPD-Link III line-rate = 4.0
Gbps
CSI-2 line-rate = 1.6 Gbps, CSI-2 = 4 DATA
lanes + 1 CLK lane
V(VDD18)= 1.89 V,
V(VDDIO) = 3.6 V
473
564
450
mW
mW
Total power consumption for
MIPI CSI-2 output mode,
normal operation
VDD_SEL = LOW, default registers
PT
FPD-Link III Input, FPD-Link III line-rate = 4.0
Gbps
V(VDD18)= 1.89 V,
V(VDD11) = 1.155 V
V(VDDIO) = 3.6 V
CSI-2 line-rate = 1.6 Gbps, CS-I2 = 4 DATA
lanes + 1 CLK lane
VDD_SEL = HIGH, default registers
DESERIALIZER SUPPLY CURRENT - FPD-Link III Rx Port0 WITH DS90UB635
1 x FPD-Link III Input, FPD-Link III line-rate =
4.0 Gbps
CSI-2 line-rate = 800 Mbps per lane, CSI-2 = 4
DATA lanes + 1 CLK lane
VDD18
VDDIO
170
5
188
10
mA
mA
VDD_SEL=LOW, default registers, includes
CSI-2 load current
Deserializer supply current 1
Rx 4 Tx
IDD-R1T4
1 x FPD-Link III Input, FPD-Link III line-rate =
4.0 Gbps
CSI-2 line-rate = 800 Mbps per lane, CSI2 = 4
DATA lanes + 1 CLK lane
VDD18
VDD11
65
80
80
100
VDD_SEL=HIGH, default registers, includes
CSI-2 load current
VDDIO
5
10
DESERIALIZER SUPPLY CURRENT - FPD-Link III Rx Port0 WITH DS90UB633A
1 x FPD-Link III Input, FPD-Link III line-rate =
1.867 Gbps
CSI-2 line-rate = 800 Mbps, CSI-2 = 4 DATA
lanes + 1 CLK lane
VDD18
VDDIO
150
5
205
10
mA
mA
VDD_SEL=LOW, includes CSI-2 load current
Deserializer supply current
2G 1 Rx 4 Tx
IDD2-R1T4
1 x FPD-Link III Input, FPD-Link III line-rate =
1.867 Gbps
CSI-2 line-rate = 800 Mbps, CSI-2 = 4 DATA
lanes + 1 CLK lane
VDD_SEL=HIGH, includes CSI-2 load current
VDD18
VDD11
65
75
86
110
VDDIO
5
10
DESERIALIZER SUPPLY CURRENT
- Power Down
VDD18
VDIO
82
2.5
10
115
5
PDB = HIGH to LOW, VDD_SEL = LOW
Deserializer shutdown
current
IDDZ
VDD18
VDD11
VDDIO
15
110
5
mA
PDB = HIGH to LOW, VDD_SEL = HIGH
30
2.5
1.8-V LVCMOS I/O
GPIO[6:4],
GPIO[2:0], LOCK,
PASS
V(VDDIO)
–0.45
IOH = –2 mA, V(VDDIO) = 1.71 to 1.89 V;
V(VDDIO) = VDD18 ±50 mV
VOH
High level output voltage
Low level output voltage
V(VDDIO)
V
IOL = 2 mA, V(VDDIO) = 1.71 to 1.89 V;
V(VDDIO) = VDD18 ±50 mV
GPIO[6:0], LOCK,
PASS
VOL
GND
0.45
V(VDDIO)
V(VDDIO)
V(VDDIO)
V
V
V
V
V
V
V
V(VDDIO) = 1.71 to 1.89 V; V(VDDIO) = VDD18
±50 mV
0.65 ×
V(VDDIO)
GPIO[6:0], BISTEN
PDB, VDD_SEL
XIN/REFCLK
V(VDDIO) = 1.71 to 1.89 V; V(VDDIO) = VDD18
±50 mV
VIH
High level input voltage
1.17
1.15
V(VDDIO) = 1.71 to 1.89 V; V(VDDIO) = VDD18
±50 mV
V(VDDIO) = 1.71 to 1.89V; V(VDDIO) = VDD18
±50 mV
0.35 ×
V(VDDIO)
GPIO[6:0], BISTEN
PDB, VDD_SEL
XIN/REFCLK
GND
GND
GND
V(VDDIO) = 1.71 to 1.89V; V(VDDIO) = VDD18
±50 mV
VIL
Low level input voltage
0.63
0.7
V(VDDIO) = 1.71 to 1.89V; V(VDDIO) = VDD18
±50 mV
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MAX UNIT
6.5 DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PIN OR
FREQUENCY
PARAMETER
TEST CONDITIONS
MIN
TYP
VIN = V(VDDIO) = 1.71 to
1.89 V,
Internal
pulldown enabled
GPIO[6:0], PDB,
BISTEN
IIH
Input high current
100
30
–100
μA
μA
GPIO[6:0], XIN/
REFCLK,
VDD_SEL
VIN = V(VDDIO) = 1.71 to
1.89 V,
Internal pulldown
disabled
IIH
Input high current
Input low current
–20
–20
GPIO[6:0], PDB,
XIN/REFCLK,
VDD_SEL,
IIL
VIN = 0V
30
25
μA
BISTEN
IOS
IOZ
3.3-V LVCMOS I/O
VOH High level output voltage
Output short circuit current
VOUT = 0 V
VOUT = 0 V
mA
–25
VOUT = 0 V or VDDIO, PDB VOUT = 0 V or
= L VDDIO, PDB = L
TRI-STATE Output Current
–25
μA
GPIO[6:4],
GPIO[2:0], LOCK,
PASS
2.4
V(VDDIO)
V
V
IOH = –4 mA, V(VDDIO) = 3.0 to 3.6 V
GPIO[6:0], LOCK,
PASS
VOL
Low level output voltage
High level input voltage
IOL = 4 mA, V(VDDIO) = 3.0 to 3.6 V
GND
0.4
GPIO[6:0], XIN/
REFCLK,
VDD_SEL,
BISTEN
V(VDDIO) = 3 to 3.6 V
2
V(VDDIO)
V
VIH
V(VDDIO) = 3 to 3.6 V
V(VDDIO) = 3 to 3.6 V
PDB, VDD_SEL
XIN/REFCLK
1.17
1.15
V(VDDIO)
V(VDDIO)
V
V
GPIO[6:0], XIN/
REFCLK,
VDD_SEL,
BISTEN
V(VDDIO) = 3 to 3.6 V
GND
0.8
V
VIL
Low level input voltage
V(VDDIO) = 3 to 3.6 V
V(VDDIO) = 3 to 3.6 V
PDB, VDD_SEL
XIN/REFCLK
GND
GND
0.63
0.7
V
V
GPIO[6:0], PDB,
BISTEN
VIN = 3 to 3.6 V, internal pulldown enabled
VIN = 3 to 3.6 V, internal pulldown disabled
190
30
–190
–20
μA
μA
IIH
Input high current
Input low current
GPIO[6:0], XIN/
REFCLK,
VDD_SEL
GPIO[6:0], PDB,
XIN/REFCLK,
VDD_SEL,
IIL
VIN = 0 V
30
–20
–25
μA
BISTEN
GPIO[7:0], LOCK,
PASS
IOS
IOZ
Output short circuit current
TRI-STATE output current
VOUT = 0 V
mA
–40
GPIO[7:0], LOCK,
PASS
VOUT = 0 V or V(VDDIO), PDB = L
35
μA
SERIAL CONTROL BUS(1)
0.7 ×
V(I2C)
VIH
Input high level
V(I2C)
V
V
0.3 ×
V(I2C)
VIL
Input low level
GND
VHY
Input hysteresis
50
mV
V
I2C_SDA,
I2C_SCL
Standard-mode/Fast-mode IOL = 3 mA
Fast-mode Plus IOL = 20 mA
VIN = V(I2C)
0
0
0.4
0.4
10
VOL
Output low level
V
IIH
Input high current
Input low current
Input capacitance
µA
µA
pF
–10
–10
IIL
VIN = 0V
10
CIN
5
FPD-LINK III
INPUT
VCM
Common mode voltage
RIN0+, RIN0-
1.2
V
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6.5 DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PIN OR
FREQUENCY
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Single-ended
Differential
RIN0+
40
80
50
60
Ω
Ω
RT
Internal termination resistor
RIN0+, RIN0-
100
120
FPD-LINK III BIDIRECTIONAL CONTROL CHANNEL
Back Channel Output Single-
ended voltage
RL = 50 Ω, coaxial configuration, forward
VOUT-BC
190
380
225
450
260
520
mV
mV
channel disabled
RIN0+, RIN0-
Back channel output
differential
RL = 100 Ω, STP configuration, forward
channel disabled
VOD-BC
HSTX DRIVER
VCMTX
HS transmit static common-
mode voltage
150
140
200
200
250
5
mV
mVP-P
mV
VCMTX mismatch when
output is 1 or 0
|ΔVCMTX(1,0)
|VOD
|
HS transmit differential
voltage
CSI_D3P/N,
CSI_D2P/N,
CSI_D1P/N,
CSI_D0P/N,
CSI_CLK1P/N,
CSI_CLK0P/N
|
270
VOD mismatch when output
is 1 or 0
14
360
mV
mV
Ω
|ΔVOD
VOHHS
ZOS
|
HS output high voltage
Single-ended output
impedance
40
50
62.5
Mismatch in single-ended
output impedance
10
%
ΔZOS
LPTX DRIVER
Applicable when the supported data rate is
≤1.5 Gbps
1.1
1.2
1.3
V
V
CSI_D3P/N,
CSI_D2P/N,
CSI_D1P/N,
CSI_D0P/N,
CSI_CLK1P/N,
CSI_CLK0P/N
VOH
High level output voltage
Applicable when the supported data rate is >
1.5 Gbps
0.95
1.3
50
VOL
Low level output voltage
Output impedance
-50
mV
ZOLP
110
Ω
(1) V(VDDIO) = 1.8 V ± 5% OR 3.3 V ± 10%
6.6 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN OR FREQUENCY
MIN
TYP
MAX
UNIT
LVCMOS I/O
LVCMOS low-to-high transition
time
tCLH
2.5
2.5
ns
V(VDDIO) = 1.71 to 1.89 V = VDD18
±50 mV OR V(VDDIO) = 3V to 3.6 V,
CL = 8pF
GPIO[6:0]
PDB
LVCMOS high-to-low transition
time
tCHL
tPDB
ns
PDB reset pulse width
Voltage supplies applied and stable
2
ms
FPD-LINK III RECEIVER INPUT
Coaxial configuration, attenuation =
20dB @ 2.1 GHz
VIN
VID
Single ended input voltage
Differential input voltage
RIN0+
40
80
mV
mV
STP configuration, attenuation =
25dB @ 2.1 GHz
RIN0+, RIN0-
AEQ full range 0x00
to 0x3F,
SFILTER_CFG =
0xA9
CSI mode paired with DS90UB635-
Q1, coaxial cable, attenuation = 20
dB @ 2.1GHz
tDDLT
Deserializer data lock time
20
300
ms
CSI mode paired with DS90UB635-
Q1, coaxial cable, attenuation = 20
dB @ 2.1GHz
AEQ range +/- 3,
SFILTER_CFG = 0xA9
tDDLT
Deserializer data lock time
Deserializer data lock time
15
15
30
ms
ms
RAW mode paired with
DS90UB633A-Q1, coaxial cable,
attenuation = 14 dB @ 1.2 GHz
AEQ full range 0x00 to
0x3F, SFILTER_CFG =
0xA9
tDDLT
200
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6.6 AC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN OR FREQUENCY
MIN
TYP
MAX
UNIT
RAW mode paired with
DS90UB633A-Q1, coaxial cable,
attenuation = 14 dB @ 1.2 GHz
AEQ range +/- 3,
SFILTER_CFG = 0xA9
tDDLT
Deserializer data lock time
15
30
ms
CSI-2 mode paired with DS90UB635-
Q1, coaxial configuration (attenuation
= 20 dB) or STP configuration
Jitter Frequency >
FPD3_PLCK/15
tIJIT
Input Jitter
0.4
UI
(attenuation = 25 dB) @ 2.1 GHz
FPD-LINK III BI-DIRECTIONAL CONTROL CHANNEL
Coaxial configuration, fBC = 52 MHz
STP configuration, fBC = 52 MHz
RIN0+
130
260
160
320
mV
mV
EH-BC
Back channel output eye height
Back channel output eye width
RIN0+, RIN0-
Coaxial or STP configuration, fBC
= 52 MHz
EW-BC
RIN0+, RIN0-
0.7
0.8
UI
Signal applied to
REFCLK input
2×
REFCLK
Mbps
Synchronous CSI-2 input mode,
default register settings
fBC
Back channel datarate(1)
No signal present at
REFCLK input
46
56 Mbps
(1) The backchannel data rate (Mbps) listed is for the encoded back channel data stream. The internal reference frequency used to
generate the encoded back channel data stream is two times the back channel datarate.
6.7 AC Electrical Characteristics CSI-2
Over recommended operating supply and temperature ranges unless otherwise specified.
PIN OR
FREQUENCY
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HSTX DRIVER
AC SPECIFICATIONS
REFCLK = 23 MHz
CSI_D0P/N,
CSI_D1P/N,
CSI_D2P/N,
CSI_D3P/N,
CSI_CLK0P/N,
CSI_CLK1P/N
368
400
736
800
1472
1600
Mbps
Mbps
REFCLK = 25 MHz
HSTXDBR
Data bit rate
REFCLK = 26 MHz
416
832
1664
Mbps
REFCLK = 23 MHz
REFCLK = 25 MHz
CSI_D0P/N,
CSI_D1P/N,
CSI_D2P/N,
CSI_D3P/N,
CSI_CLK0P/N,
CSI_CLK1P/N
184
200
368
400
736
800
MHz
MHz
fCLK
DDR clock frequency
REFCLK = 26 MHz
208
416
832
MHz
Common-level variations above
450MHz
CSI_D0P/N,
CSI_D1P/N,
CSI_D2P/N,
CSI_D3P/N,
CSI_CLK0P/N,
CSI_CLK1P/N
Common mode voltage variations HF
Common mode voltage variations LF
15 mVRMS
25 mVRMS
ΔVCMTX(HF)
Common-level variations between 50
and 450MHz
ΔVCMTX(LF)
0.3
UI
UI
HS bit rates ≤1 Gbps (UI ≥1 ns)
HS bit rates > 1 Gbps (UI
0.35
Applicable for all HS bit rates.
However, to avoid excessive
radiation, bit rates ≤1 Gbps (UI ≥1
ns), should not use values below 150
ps
100
ps
UI
CSI_D0P/N,
CSI_D1P/N,
CSI_D2P/N,
CSI_D3P/N,
CSI_CLK0P/N,
CSI_CLK1P/N
tRHS tFHS
20% to 80% rise and fall HS
Applicable for all HS bit rates when
supporting > 1.5 Gbps
0.4
Applicable for all HS bit rates when
supporting > 1.5 Gbps. However, to
avoid excessive radiation, bit rates ≤
1.5 Gbps should not use values
50
ps
below 100 ps and bit rates ≤1 Gbps
should not use values below 150 ps.
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6.7 AC Electrical Characteristics CSI-2 (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PIN OR
FREQUENCY
PARAMETER
TEST CONDITIONS
MIN
TYP
–18
–9
MAX
UNIT
dB
fLPMAX
HSData rates <
1.5 Gbps
dB
CSI_D0P/N,
CSI_D1P/N,
CSI_D2P/N,
CSI_D3P/N,
CSI_CLK0P/N,
CSI_CLK1P/N
fH
HSData rates >
1.5 Gbps
-4.5
–-3
dB
dB
dB
SDDTX
TX differential return loss
HSData rates <
1.5 Gbps
fMAX
HSData rates >
1.5 Gbps
–-2.5
CSI_D0P/N,
CSI_D1P/N,
CSI_D2P/N,
CSI_D3P/N,
CSI_CLK0P/N,
CSI_CLK1P/N
fLPMAX
fH
dB
dB
–20
–15
SCCTX
TX common mode return loss
fMAX
dB
–9
LPTX DRIVER
AC SPECIFICATIONS
tRLP Rise time LP
tFLP
15% to 85% rise time
15% to 85% fall time
CSI_D0P/N,
CSI_D1P/N,
CSI_D2P/N,
CSI_D3P/N,
CSI_CLK0P/N,
CSI_CLK1P/N
25
25
ns
ns
Fall time LP
tREOT
Rise time post-EoT
30%-85% rise time
35
ns
ns
First LP exclusive-OR clock pulse
after Stop state or last pulse before
Stop state
CSI_D0P/N,
CSI_D1P/N,
CSI_D2P/N,
CSI_D3P/N,
CSI_CLK0P/N,
CSI_CLK1P/N
40
Pulse width of the LP exclusive-OR
clock
tLP-PULSE-TX
All other pulses
20
90
ns
ns
Pulse width of the LP exclusive-OR
clock
tLP-PER-TX
CLoad = 0pF
CLoad = 5pF
CLoad = 20pF
CLoad = 70pF
500 mV/ns
300 mV/ns
250 mV/ns
150 mV/ns
CLoad = 0 to 70pF (Falling Edge
Only) Data rate < 1.5 Gbps
30
30
25
mV/ns
mV/ns
mV/ns
mV/ns
CLoad = 0 to 70pF (Rising Edge
Only) Data rate < 1.5 Gbps
CSI_D0P/N,
CSI_D1P/N,
CSI_D2P/N,
CSI_D3P/N,
CSI_CLK0P/N,
CSI_CLK1P/N
CLoad = 0 to 70pF (Falling Edge
Only) Data rate > 1.5 Gbps
DV/DtSR
Slew rate
CLoad = 0 to 70pF (Rising Edge
Only) Data rate > 1.5 Gbps
25
CLoad = 0 to 70pF (Rising Edge
Only) Applicable when the supported
Data rate is < 1.5 Gbps
0 - 0.075 ×
(VO,INST
-
mV/ns
mV/ns
700)
25 -
0.0625 ×
CLoad = 0 to 70pF (Rising Edge
Only) Applicable when the supported
Data rate is > 1.5 Gbps
(VO,INST
-
550)
CSI_D0P/N,
CSI_D1P/N,
CSI_D2P/N,
CSI_D3P/N,
CSI_CLK0P/N,
CSI_CLK1P/N
CLOAD
Load capacitance
0
50
pF
DATA-CLOCK
TIMING SPECIFICATIONS
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6.7 AC Electrical Characteristics CSI-2 (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PIN OR
FREQUENCY
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UIINST
UI instantaneous
In 1, 2, 3, or 4 Lane Configuration
CSI_D0P/N,
CSI_D1P/N,
CSI_D2P/N,
CSI_D3P/N,
CSI_CLK0P/N,
CSI_CLK1P/N
0.6
2.7
ns
UI
-10%
10%
UI ≥1ns
UI variation
ΔUI
-5%
5%
UI
0.667ns ≤UI
CSI_D0P/N,
CSI_D1P/N,
CSI_D2P/N,
CSI_D3P/N,
CSI_CLK0P/N,
CSI_CLK1P/N
-0.15
0.15
UIINST
Data rate ≤1 Gbps
Data to Clock Skew (measured at
transmitter) Skew between clock and
data from ideal center
tSKEW(TX)
Data rate: 1 Gbps to 1.5 Gbps
-0.2
0.2
UIINST
tSKEW(TX)STATIC Static Data to Clock Skew (TX)
CSI_D0P/N,
CSI_D1P/N,
CSI_D2P/N,
CSI_D3P/N,
CSI_CLK0P/N,
CSI_CLK1P/N
-0.2
0.2
UIINST
UIINST
tSKEW(TX)DYNAM
Dynamic Data to Clock Skew (TX)
-0.15
0.15
Data rate > 1.5 Gbps
IC
ISI
Channel ISI
0.2
UIINST
CSI-2 TIMING
SPECIFICATIONS
Timeout for receiver to detect absence
tCLK-MISS
of clock transitions and disable the
clock lane HS-RX
60
ns
ns
UI
ns
ns
tCLK-POST
tCLK-PRE
tCLK-PREPARE
tCLK-SETTLE
HS exit
60 + 52×UI
Time HS clock shall be driver prior to
any associated data lane beginning
the transition from LP to HS mode
8
38
95
Clock lane HS entry
95
CSI_D0P/N,
CSI_D1P/N,
CSI_D2P/N,
CSI_D3P/N,
CSI_CLK0P/N,
CSI_CLK1P/N
Time interval during which the HS
receiver shall ignore any clock lane
HS transitions
300
Time for
Dn to
reach
VTERM-
EN
Time-out at clock lane display module
to enable HS termination
tCLK-TERM-EN
38
ns
Time that the transmitter drives the
HS-0 state after the last payload clock
bit of a HS transmission burst
tCLK-TRAIL
60
ns
ns
TCLK-PREPARE + time that the
transmitter drives the HS-0 state prior
to starting the clock
tCLK-PREPARE
tCLK-ZERO
+
300
Time for
Dn to
reach
Time for the data lane receiver to
enable the HS line termination
tD-TERM-EN
35 + 4×UI
ns
ns
VTERM-EN
Transmitted time interval from the start
of tHS-TRAIL to the start of the LP-11
state following a HS burst
CSI_D0P/N,
CSI_D1P/N,
CSI_D2P/N,
CSI_D3P/N,
CSI_CLK0P/N,
CSI_CLK1P/N
105 +
12×UI
tEOT
Time that the transmitter drives LP-11
following a HS burst
tHS-EXIT
100
ns
ns
tHS-PREPARE
Data lane HS entry
40 + 4×UI
85 + 6×UI
tHS-PREPARE + time that the transmitter
drives the HS-0 state prior to
transmitting the Sync sequence
tHS PREPARE
tHS-ZERO
-
+
145 +
10×UI
ns
ns
Time interval during which the HS
receiver shall ignore any data lane HS
transitions, starting from the beginning
of tHS-SETTLE
145 +
10×UI
tHS-SETTLE
85 + 6×UI
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6.7 AC Electrical Characteristics CSI-2 (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PIN OR
FREQUENCY
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Time interval during which the HS-RX
should ignore any transitions on the
data lane, following a HS burst. The
end point of the interval is defined as
the beginning of the LP-11 state
following the HS burst.
tHS-SKIP
40
55 + 4×UI
ns
tHS-TRAIL
tLPX
Data lane HS exit
60 + 4×UI
50
ns
ns
Transmitted length of LP state
Recovery Time from Ultra Low Power
State (ULPS)
tWAKEUP
tINIT
1
ms
µs
Initialization period
100
6.8 Recommended Timing for the Serial Control Bus
Over I2C supply and temperature ranges unless otherwise specified.
MIN
TYP
MAX UNIT
Standard-mode
>0
>0
100
400
1
kHz
kHz
MHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
fSCL
SCL Clock Frequency
SCL Low Period
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
>0
4.7
1.3
0.5
4.0
0.6
0.26
4.0
0.6
0.26
4.7
0.6
0.26
0
tLOW
tHIGH
tHD;STA
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
Fast-mode Plus
Standard-mode
Fast-mode
SCL High Period
Fast-mode Plus
Standard-mode
Fast-mode
Hold time for a start or a repeated start
condition
Fast-mode Plus
Standard-mode
Fast-mode
Set up time for a start or a repeated start
condition
Fast-mode Plus
Standard-mode
Fast-mode
Data hold time
0
Fast-mode Plus
Standard-mode
Fast -mode
0
250
100
50
Data set up time
Fast-mode Plus
Standard-mode
Fast-mode
4.0
0.6
0.26
4.7
1.3
0.5
Set up time for STOP condition
Bus free time between STOP and START
SCL & SDA rise time
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
1000
300
120
300
300
120
tr
Fast-mode Plus
Standard-mode
Fast-mode
tf
SCL & SDA fall time
Fast-mode Plus
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MAX UNIT
6.8 Recommended Timing for the Serial Control Bus (continued)
Over I2C supply and temperature ranges unless otherwise specified.
MIN
TYP
Standard-mode
400
400
550
3.45
0.9
pF
pF
pF
µs
µs
µs
µs
µs
µs
ns
ns
Cb
Capacitive load for each bus line
Data valid time
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
tVD:DAT
Fast-mode Plus
Standard-mode
Fast-mode
0.45
3.45
0.9
tVD;ACK
Data vallid acknowledge time
Input filter
Fast-mode Plus
Fast-mode
0.45
50
tSP
Fast-mode Plus
50
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6.9 Timing Diagrams
V(VDDIO)
80%
20%
tCHL
GND
tCLH
图6-1. LVCMOS Transition Times
Single
Ended
RIN+
or RIN
VIN
VIN
œ
VCM
ö
0 V
图6-2. FPD-Link III Receiver VID, VIN, VCM
PDB=H
tDDLT
RIN
GPIOx
(LOCK)
VDDIO/2
图6-3. Deserializer Data Lock Time
SDA
t
BUF
t
f
t
t
HD;STA
t
r
LOW
t
t
r
f
SCL
t
t
HD;STA
SU;STA
t
SU;STO
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
图6-4. I2C Serial Control Bus Timing
CSI_D[3:0]P
CSI_D[3:0]N
0.5UI
+ tSKEW
CSI_CLK0/1P
CSI_CLK0/1N
1 UI
图6-5. Clock and Data Timing in HS Transmission
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Clock
Lane
Data Lane
Dp/Dn
TLPX
THS-ZERO
THS-SYNC
Disconnect
Terminator
VOH
THS-PREPARE
VIH(min)
VIL(max)
VOL
TREOT
Capture
1st Data Bit
TD-TERM-EN
THS-SKIP
TEOT
THS-TRAIL
LP-11
LP-11
LP-01
LP-00
THS-SETTLE
THS-EXIT
LOW-POWER TO
HIGH-SPEED
TRANSITION
START OF
HS-ZERO TRANSMISSION
SEQUENCE
HIGH-SPEED TO
HS-TRAIL LOW-POWER
TRANSITION
HIGH-SPEED DATA
TRANSMISSION
图6-6. High-Speed Data Transmission Burst
Disconnect
Terminator
Clock Lane
Dp/Dn
T
CLK-SETTLE
T
T
EOT
CLK-POST
TCLK-TERM-EN
T
CLK-MISS
VIH(min)
VIL(max)
T
T
T
LPX
T
T
CLK-PRE
CLK-TRAIL
HS-EXIT
CLK-ZERO
T
CLK-PREPARE
Data Lane
Dp/Dn
T
HS-PREPARE
Disconnect
Terminator
T
LPX
VIH(min)
VIL(max)
T
HS-SKIP
T
D-TERM-EN
T
HS-SETTLE
图6-7. Switching the Clock Lane Between Clock Transmission and Low-Power Mode
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VVALID
(internal Node)
Vertical Blanking
1st
Line
2nd
Line
Last
Line
HVALID
(internal Node)
CSI0_D[3:0]
or
CSI1_D[3:0]
1 to 216
t
LPX
Line
Packet
Line
Packet
Line
Packet
Line
Packet
FS
FE
FS
LPS
LPS
LPS
LPS
LPS
LPS
LPS
LPS
Frame
Sync
Packet
Line
Packet
图6-8. Long Line Packets and Short Frame Sync Packets
Frame Blanking
FS
Line Blanking
Line Data
FE
Frame Blanking
FS
Line Blanking
Line Data
FE
Frame Blanking
图6-9. CSI-2 General Frame Format
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HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 4
HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 3
LANE 0
LANE 1
LANE 2
LANE 3
SOT
SOT
SOT
SOT
BYTE 0
BYTE1
BYTE2
BYTE 3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE 8
BYTE9
BYTE n-4
BYTE n-3
BYTE n-2
BYTE n-1
EOT
EOT
EOT
EOT
SOT
SOT
SOT
BYTE0
BYTE 1
BYTE2
BYTE3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE8
BYTE n-3
BYTE n-2
BYTE n-1
EOT
EOT
EOT
LANE 0
LANE 1
LANE 2
BYTE 10
BYTE 11
HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 3
HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 4
SOT
SOT
SOT
BYTE0
BYTE 1
BYTE2
BYTE3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE8
BYTE n-2
BYTE n-1
EOT
EOT
EOT
LANE 0
LANE 1
LANE 2
LANE 0
LANE 1
LANE 2
LANE 3
SOT
SOT
SOT
SOT
BYTE 0
BYTE1
BYTE2
BYTE 3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE 8
BYTE9
BYTE n-3
BYTE n-2
BYTE n-1
EOT
EOT
EOT
EOT
BYTE 10
BYTE 11
HS BYTES TRANSMITTED (n) IS 2 LESS THAN INTEGER MULTIPLE OF 3
SOT
SOT
SOT
BYTE0
BYTE 1
BYTE2
BYTE3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE8
BYTE n-1
EOT
EOT
LANE 0
LANE 1
LANE 2
HS BYTES TRANSMITTED (n) IS 2 LESS THAN INTEGER MULTIPLE OF 4
LANE 0
LANE 1
LANE 2
LANE 3
SOT
SOT
SOT
SOT
BYTE 0
BYTE1
BYTE2
BYTE 3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE 8
BYTE9
BYTE n-2
BYTE n-1
EOT
EOT
EOT
EOT
BYTE 10
BYTE 11
3 CSI-2 Data Lane Configuration
EOT
HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 2
HS BYTES TRANSMITTED (n) IS 3 LESS THAN INTEGER MULTIPLE OF 4
LANE 0
LANE 1
LANE 2
LANE 3
SOT
SOT
SOT
SOT
BYTE 0
BYTE1
BYTE2
BYTE 3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE 8
BYTE9
BYTE n-1
EOT
EOT
LANE 0
LANE 1
SOT
SOT
BYTE 0
BYTE1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE n-2
BYTE n-1
EOT
EOT
BYTE 10
BYTE 11
EOT
HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 2
EOT
LANE 0
LANE 1
SOT
SOT
BYTE 0
BYTE1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE n-1
EOT
EOT
4 CSI-2 Data Lane Configuration (default)
2 CSI-2 Data Lane Configuration
图6-10. MIPI CSI-2 Data Lane Configuration
6.10 Typical Characteristics
图6-11. Forward Channel Monitor Loop Through Typical Rx
图6-12. Back Channel Output Typical Waveform
Waveform (CMLOUT)
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7 Detailed Description
7.1 Overview
The DS90UB638-Q1 is a versatile deserializer that receives an FPD-Link III stream and transmits the received
data over a MIPI camera serial interface (CSI-2). When coupled with an ADAS FPD-Link III serializer
(DS90UB63x-Q1), the DS90UB638-Q1 receives a data stream from a remote sensor, then transmits that data as
one or two CSI-2 outputs.
表7-1. Serializer Compatibility
SERIALIZER
DS90UB635-Q1
DS90UB633A-Q1
Compatibility
Yes
Yes
7.1.1 Functional Description
The DS90UB638-Q1 FPD-Link III deserializer, in conjunction with an ADAS FPD-Link III serializer, supports the
video transport needs with an ultra-high speed forward channel and an embedded bidirectional control channel.
The DS90UB638-Q1 received data is output from a configurable MIPI CSI-2 port. The CSI-2 port may be
configured as either a single CSI-2 output with four lanes up to 1.6 Gbps per lane or as two 2 lane CSI-2 outputs
for sending replicated data on both ports. A second differential clock is available for the second replicated output
when configured for dual CSI-2 outputs supporting one clock lane and one or two data lanes each. The
DS90UB638-Q1 can support multiple data formats and different resolutions as provided by the sensor.
Conversion between different data formats is not supported. The CSI-2 Tx module accommodates both image
data and non-image data (including synchronization or embedded data packets).
The DS90UB638-Q1 CSI-2 interface converts the sensor data stream into packets designated for each virtual
channel. Each virtual channel is identified by a unique channel identification number in the packet header.
When the DS90UB638-Q1 is paired with a DS90UB635-Q1 serializer, the received FPD-Link III forward channel
is constructed in 40-bit long frames and when it is paired with a DS90UB633A-Q1 serializer, the received FPD-
Link III forward channel is constructed in 28-bit long frames. Each encoded frame contains video payload data,
I2C forward channel data, and additional information on framing, data integrity and link diagnostics. The high-
speed, serial bit stream from the DS90UB635-Q1 or DS90UB633A-Q1 contains an embedded clock and DC-
balancing ensuring sufficient data line transitions for enhanced signal quality. When paired with ADAS serializers
in RAW input mode, the received FPD-Link III forward channel is similarly constructed at a lower line rate in 28-
bit long frames. The DS90UB638-Q1 device recovers a high-speed, FPD-Link III forward channel signal and
generates a bidirectional control channel control signal in the reverse channel direction. The DS90UB638-Q1
converts the FPD-Link III stream into a MIPI CSI-2 output interface designed to support automotive sensors,
including 2MP/60fps and 4MP/30fps image sensors.
The DS90UB638-Q1 device has one receive input port to accept sensor streams. The control channel function of
the DS90UB63x-Q1 chipset provides bidirectional communication between the image sensors and ECU. The
integrated control channel transfers data bidirectionally over the same cable used for video data interface. This
interface offers advantages over other chipsets by eliminating the need for additional wires for programming and
control. The bidirectional control channel bus is controlled through an I2C port. The bidirectional control channel
offers continuous low latency communication and is not dependent on video blanking intervals.
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7.2 Functional Block Diagram
CDR
4
8
CSI_CLK[0,1]
R
R
T
T
CSI_DATA[3:0]
RIN0+
RIN0-
7
GPIO[6:0]
XIN/REFCLK
XOUT
Clock
Gen
PDB
VDD_SEL
Timing and
Control
MODE
LDO
LDO
LDO
IDX
SDA
SCL
LDO
CMLOUTP
CMLOUTN
LOCK
PASS
BISTEN
Diagnostics
7.3 Feature Description
The DS90UB638-Q1 provides a flexible deserializer for automotive sensor applications.
7.4 Device Functional Modes
The DS90UB638-Q1 supports two main the FPD-Link III operating modes:
• CSI-2 Mode (DS90UB635-Q1 compatible)
• RAW Mode (DS90UB633A-Q1 compatible)
The two modes mainly control the FPD-Link III receiver operation of the device. In both cases, the output format
for the device is CSI-2 through the CSI-2 transmit port.
The input mode of operation is controlled by the FPD3_MODE (Register 0x6D[1:0]) setting in the Port
Configuration register. The input mode may also be controlled by the MODE strap pin.
7.4.1 CSI-2 Mode
The DS90UB638-Q1 receives CSI-2 formatted data on an FPD-Link III input port and forwards the data to the
CSI-2 transmit port. The deserializer can operate in CSI-2 mode with synchronous back channel reference or
non-synchronous mode. The forward channel line rate is independent of the CSI-2 rate in synchronous or non-
synchronous with external clock mode. The CSI-2 mode supports remapping of Virtual Channel IDs at the input
of the receive port.
The deserializer Rx Port can support an FPD-Link line rate up to 4.16 Gbps, where the forward channel and
back channel rates are based on the reference frequency used for the serializer:
• In Synchronous mode based on REFCLK input frequency reference, the FPD-Link line rate is a fixed value of
160 × REFCLK. FPD3_PCLK = 4 × REFCLK and Back channel rate = 2 × REFCLK. For example with
REFCLK = 25 MHz, line rate = 4.0 Gbps, FPD3_PCLK = 100 MHz, back channel data rate = 50 Mbps. The
sensor CSI-2 rate is independent of the line rate and Tx CSI-2 rate in synchronous clocking mode and can be
up to 3.328 Gbps.
• In Non-synchronous clocking mode when the DS90UB635-Q1 uses external reference clock (fCLKIN) the
FPD-Link line rate is typically fCLKIN × 80, FPD3_PCLK = 2 × fCLKIN or 1 x fCLKIN and back channel data rate is
set to 10 Mbps. For example, with fCLKIN = 50 MHz, line rate = 4Gbps, FPD3_PCLK = 100 MHz, and the back
channel rate is 10 Mbps. The sensor CSI-2 rate is independent of the fCLKIN
.
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7.4.2 RAW Mode
When operating in Raw FPD-Link IV input mode, the DS90UB638-Q1 receives RAW10 or RAW12 data from a
DS90UB633A-Q1 serializer. The data is translated into a RAW10 or RAW12 CSI-2 video stream for forwarding
to the CSI-2 transmit port. For each input port, the CSI-2 packet header VC-ID and Data Type are
programmable.
In RAW mode the DS90UB638-Q1 deserializer each Rx Port can support up to:
• 12-bits of DATA + 2 SYNC bits for an input PCLK range of 56.25 MHz to 100 MHz in the 12-bit high
frequency mode. Line rate = FPD3_PCLK × (2/3) × 28; for example, FPD3_PCLK = 100 MHz, line rate = (100
MHz) × (2/3) × 28 = 1.87 Gbps. Note: No HS/VS restrictions (raw).
• 10-bits of DATA + 2 SYNC bits for an input PCLK range of 75 MHz to 100 MHz in the 10-bit mode. Line rate =
FPD3_PCLK/2 × 28; for example, FPD3_PCLK = 100 MHz, line rate = (100 MHz/2) × 28 = 1.40 Gbps Note:
HS/VS restricted to no more than one transition per 10 PCLK cycles.
When operating with DVP serializer, the DS90UB638-Q1 deserializer also supports DVP formats such as
YUV-422 which have the same pixel packing as RAW8, RAW10 or RAW12. For example; there are 3 YUV CSI-2
data types that have the same pixel packing as RAW10: YUV420 10 bit, YUV420 10 bit Chroma shifted or
YUV422 10bit. These formats can be used as well as 8 bit and 12 bit YUV formats which adhere to the same
structure as RAW8 and RAW12 respectively.
7.4.3 RX MODE Pin
Configuration of the FPD-Link III operating input mode may be done through the MODE input strap pin, or
through the configuration register bits. A pullup resistor and a pull-down resistor of suggested values may be
used to set the voltage ratio of the MODE input (VTARGET) and V(VDD18) to select one of the mode. The
DS90UB638-Q1 waits 1 ms after PDB goes high to allow time for power supply transients before sampling the
MODE pin strap value and configuring the device to set the I2C address. The DS90UB638-Q1 operating mode
is:
• CSI-2 input Rx REFCLK mode
• 12-bit HF / 10-bit DVP Rx modes
VDD18
R
HIGH
MODE
or IDX
V
TARGET
R
LOW
Deserializer
GND
图7-1. Strap Pin Connection Diagram
表7-2. Strap Configuration Mode Select
VTARGET STRAP SUGGESTED STRAP RESISTORS (1%
VTARGET VOLTAGE RANGE
MODE
NO.
VOLTAGE
VDD18 = 1.8 V
0
TOL)
RX MODE
VMIN
VTYP
VMAX
RHIGH (kΩ)
RLOW (kΩ)
0
0
0
0.131 × V(VDD18)
OPEN
10.0
CSI-2 non-
synchronous Back
Channel
1
2
3
0.296 × V(VDD18)
0.761 × V(VDD18)
0.412 × V(VDD18)
0.876 × V(VDD18)
0.525 × V(VDD18)
0.330 × V(VDD18)
0.792 × V(VDD18)
0.443 × V(VDD18)
V(VDD18)
0.362 × V(VDD18)
0.823 × V(VDD18)
0.474 × V(VDD18)
V(VDD18)
0.582
1.420
0.792
1.8
75.0
25.5
71.5
10.0
78.7
35.7
95.3
RAW12 HF
56.2
RAW10
OPEN
97.6
0.559 × V(VDD18)
0.592 × V(VDD18)
0.995
CSI-2 Synchronous
Back Channel
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The strapped values can be viewed and modified in the following locations:
• RX Mode –Port Configuration FPD3_MODE (Register 0x6D[1:0])
• Clock Mode –Device Status and CSI_PLL_CTL (Register bits 0x04[4] and 0x1F[0])
7.4.4 REFCLK
A valid 23-MHz to 26-MHz reference clock is required on the REFCLK pin 5 for precise frequency operation. The
REFCLK frequency defines all internal clock timers, including the back channel rate, I2C timers, CSI-2 datarate,
FrameSync signal parameters, and other timing critical internal circuitry. REFCLK input must be continuous. If
the REFCLK input does not detect a transition more than 20 µS, this may cause a disruption in the CSI-2 output.
REFCLK should be applied to the DS90UB638-Q1 only when the supply rails are above minimum levels (see 节
9.2). At start-up, the DS90UB638-Q1 defaults to an internal oscillator to generate an backup internal reference
clock at nominal frequency of 25 MHz ±10%.
The REFCLK LVCMOS input oscillator specifications are listed in 表7-3.
表7-3. REFCLK Oscillator Specifications
PARAMETER
REFERENCE CLOCK
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±50
±50
ppm
ppm
Frequency tolerance
Frequency stability
Amplitude
–40°C ≤TA ≤105°C
Aging
800
1200
50%
V(VDDIO)
60%
5
mVp-p
Symmetry
Duty Cycle
40%
ns
Rise and fall time
Jitter
10% –90%
50
25
1000
26
ps p-p
MHz
200 kHz –10 MHz
Frequency
23
7.4.5 Crystal Recommendations
A 25-MHz, parallel, 18-pF load crystal resonator should be used if a crystal source is desired. 图 7-2 shows a
typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors;
check with the vendor for the recommended loads.
XIN
XOUT
R1
CL1
CL2
图7-2. Crystal Oscillator Circuit
As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, CL1 and
CL2 should be set at 27 pF and R1 should be set at 0 Ω. Specification for 25-MHz crystal are listed in 表7-4.
表7-4. 25-MHz Crystal Specifications
PARAMETER
REFERENCE CLOCK
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Frequency
25
MHz
ppm
Across operational temperature and
aging
Frequency Tolerance and Stability
±100
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7.4.6 Receiver Port Control
After the device is powered up, the following register settings are required:
• Program 0x0c bit 1 to 0
• Program 0x21 bit 6 to 1
The DS90UB638-Q1 can support a single input to Rx port 0. The Receiver port control register RX_PORT_CTL
0x0C (表 7-29) allows for disabling the Rx input when not in use. These bits can only be written by a local I2C
controller at the deserializer side of the FPD-Link.
As an alternative to paging to access FPD-Link III Receive unique port registers, separate I2C addresses may
be enabled to allow direct access to the port-specific registers. The Port I2C address registers allow
programming a separate 7-bit I2C address to allow access to unique, port-specific registers without paging. I2C
commands to these assigned I2C addresses are also allowed access to all shared registers (see 表7-161).
7.4.7 LOCK and PASS Status
The DS90UB638-Q1 provides dedicated PASS and LOCK outputs for monitoring status as well as through the
DEVICE_STS register (address 0x04).The source of the deserializer LOCK and PASS signals for pin monitoring
and interrupt operation is also controlled by the LOCK_SEL and PASS_SEL fields in the RX_PORT_CTL
register. The source of the LOCK and PASS can be allocated to Port 0 Receiver. At start-up, the deserializer will
synchronize with the input signal provided by the serializer and assert the LOCK indication once stable. The lock
detect circuit includes an option to check for link bit errors as part of the lock detection and determine if LOCK is
lost. The Receive Port Lock status is available through the RX_PORT_STS1 register 0x4D. The LOCK status
may also be used to enable video forwarding and other options. I2C communication across the FPD-Link should
be attempted only during LOCK condition.
If the deserializer loses LOCK, the receiver will reset and perform the LOCK algorithm again to reacquire the
serial data stream sent by the serializer. The receive port will truncate video frames containing errors and
resume forwarding the video when LOCK is re-established.
The Receive port will indicate Pass status once specific conditions are met, including a number of valid frames
received. Valid frames may include requiring no link bit errors and consistent frame size including video line
length or number of video lines. The receive port may be programmed to truncate video frames containing errors
and prevent the forwarding of video until the Pass conditions are met.
7.4.8 Adaptive Equalizer
The FPD-Link III receiver inputs incorporates an adaptive equalizer (AEQ), to compensate for signal degradation
from the communications channel and interconnect components. The RX port signal path continuously monitors
cable characteristics for long-term cable aging and temperature changes. The AEQ is primarily intended to adapt
and compensate for channel losses over the lifetime of a cable installed in an automobile. The AEQ attempts to
optimize the equalization setting of the RX receiver. This adaption includes compensating insertion loss from
temperature effects and aging degradation due to bending and flexion. To determine the maximum cable reach,
factors that affect signal integrity such as jitter, skew, inter-symbol interference (ISI), crosstalk, and so forth, must
also be considered. The equalization configuration and status are programmed in registers 0xD2–0xD3 (see 表
7-141).
7.4.8.1 Adaptive Equalizer Algorithm
The AEQ process steps through allowed values of the equalizer controls find a value that allows the Clock Data
Recovery (CDR) circuit to maintain valid lock condition. For each EQ setting, the circuit waits for a programmed
re-lock time period, then checks results for valid lock. If valid lock is detected, the circuit will stop at the current
EQ setting and maintain constant value as long as lock state persists. If the deserializer loses LOCK, the
adaptive equalizer will resume the LOCK algorithm and the EQ setting is incremented to the next valid state.
Once lock is lost, the circuit will continue searching EQ settings to find a valid setting to reacquire the serial data
stream sent by the serializer that remains locked.
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7.4.8.2 AEQ Settings
7.4.8.2.1 AEQ Start-Up and Initialization
The AEQ circuit can be restarted at any time by setting the AEQ_RESTART bit in the AEQ_CTL2 register 0xD2
(see 表 7-141). Once the deserializer is powered on, the AEQ is continually searching through EQ settings and
could be at any setting when signal is supplied from the serializer. If the Rx Port CDR locks to the signal, it may
be good enough for low bit errors, but could be not optimized or overequalized. The DS90UB638-Q1 when
connected to an ADAS serializer (DS90UB63x-Q1) will by default restart the AEQ adaption upon achieving first
positive lock indication in order to provide more consistent start-up from known conditions. With this feature
disabled, the AEQ may lock at a relatively random EQ setting based on when the FPD-Link III input signal is
initially present. Alternatively, AEQ_RESTART or DIGITAL_RESET0 could be applied once the ADAS serializer
input signal frequency is stable to restart adaption from the minimum EQ gain value. These techniques allow for
a more consistent initial EQ setting following adaption.
7.4.8.2.2 AEQ Range
AEQ Min/Max settings: The AEQ circuit can be programmed with minimum and maximum settings used during
the EQ adaption. Using the full AEQ range will provide the most flexible solution, however if the channel
conditions are known an improved deserializer lock time can be achieved by narrowing the search window for
allowable EQ gain settings. For example in a system use case with a longer cable and multiple interconnects
creating higher channel attenuation, the AEQ would not adapt to the minimum EQ gain settings. Likewise in a
system use case with short cable and low channel attenuation AEQ would not generally adapt to the highest EQ
gain settings. The AEQ range is determined by the AEQ_MIN_MAX register 0xD5 (see 节 7.7.128) where
AEQ_MAX sets the maximum value of EQ gain. The ADAPTIVE_EQ_FLOOR_VALUE determines the starting
value for EQ gain adaption. To enable the minimum AEQ limit, SET_AEQ_FLOOR bit in the AEQ_CTL2 register
0xD2[2] must also be set. An AEQ range (AEQ_MAX - AEQ_FLOOR) to allow a variation around the nominal
setting of –2/+4 or ±3 around the nominal AEQ value specific to Rx port channel characteristics provides a good
trade off in lock time and adaptability. The setting for the AEQ after adaption can be readback from the
AEQ_STATUS register 0xD3 (see 节7.7.126).
7.4.8.2.3 AEQ Timing
The dwell time for AEQ to wait for lock or error free status is also programmable. When checking each EQ
setting the AEQ will wait for a time interval, controlled by the ADAPTIVE_EQ_RELOCK_TIME field in the
AEQ_CTL2 register (see 表 7-141) before incrementing to the next allowable EQ gain setting. The default wait
time is set to 2.62 ms based on REFCLK = 25 MHz. Once the maximum setting is reached, if there is no lock
acquired during the programmed relock time, the AEQ will restart adaption at the minimum setting or
AEQ_FLOOR value.
7.4.8.2.4 AEQ Threshold
The DS90UB638-Q1 receiver will by default adapt based on FPD-Link error checking during the Adaptive
Equalization process. The specific errors linked to equalizer adaption, FPD-Link III clock recovery error, packet
encoding error, and parity error can be individually selected in AEQ_CTL1 register 0x42 (see 节 7.7.54). Errors
are accumulated over 1/2 of the period of the timer set by the ADAPTIVE_EQ_RELOCK_TIME. If the number of
errors is greater than the programmed threshold (AEQ_ERR_THOLD), the AEQ will attempt to increase the EQ
setting.
7.4.9 Channel Monitor Loop-Through Output Driver (CMLOUT)
The DS90UB638-Q1 includes an internal Channel Monitor Loop-through output on the CMLOUTP and
CMLOUTN pins which provides a functional check of the receive channel. CMLOUT is useful in identifying gross
signal conditioning issues.
表 7-5 includes details on selecting the RX receiver of CMLOUTP and CMLOUTN configuration. To disable the
CMLOUT, either follow the instructions in table to reload register default values, or reset the DS90UB638-Q1.
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VOD (+)
Ew
0V
VOD (-)
t
(1 UI)
BIT
图7-3. CMLOUT Output Driver
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表7-5. Channel Monitor Loop-Through Output Configuration
FPD-Link III RX Port 0
0xB0 = 0x14; 0xB1 = 0x00; 0xB2 = 0x80
0xB1 = 0x03; 0xB2 = 0x28
ENABLE MAIN LOOP-THROUGH DRIVER
0xB1 = 0x04; 0xB2 = 0x28
SELECT CHANNEL MUX
SELECT RX PORT
0xB1 = 0x02; 0xB2 = 0x20
0xB0 = 0x04; 0xB1 = 0x0F; 0xB2 = 0x01
0xB1 = 0x10; 0xB2 = 0x02
0xB0 = 0x14; 0xB1 = 0x00; 0xB2 = 0x00
0xB1 = 0x03 ; 0xB2 = 0x08
DISABLE MAIN LOOP-THROUGH DRIVER
0xB1 = 0x04; 0xB2 = 0x08
DESELECT CHANNEL MUX
DESELECT RX PORT
0xB1 = 0x02; 0xB2 = 0x20
0xB0 = 0x04; 0xB1 = 0x0F; 0xB2 = 0x00
0xB1 = 0x10; 0xB2 = 0x00
7.4.9.1 Code Example for CMLOUT FPD-Link III RX Port 0:
WriteI2C(0xB0,0x14)
WriteI2C(0xB1,0x00)
WriteI2C(0xB2,0x80)
WriteI2C(0xB1,0x03)
WriteI2C(0xB2,0x28)
WriteI2C(0xB1,0x04)
WriteI2C(0xB2,0x28)
#
WriteI2C(0xB1,0x02)
WriteI2C(0xB2,0x20)
#
WriteI2C(0xB0,0x04)
WriteI2C(0xB1,0x0F)
WriteI2C(0xB2,0x01)
WriteI2C(0xB1,0x10)
WriteI2C(0xB2,0x02)
# FPD-Link III RX Shared, page 0
# Offset 0
# Enable loop through driver
#
#
#
#
#
#
# Offset 4
#
#
#
# Enable CML data output
7.4.10 RX Port Status
In addition to the Lock and PASS indications, the deserializer is able to monitor and detect several other RX
conditions and interrupt states. This information is latched into the RX port status registers RX_PORT_STS1
(0x4D) and RX_PORT_STS2 (0x4E). There are bits to flag any change in LOCK status (LOCK_STS_CHG) or
detect any errors in the control channel over the forward link (BCC_CRC_ERROR, BCC_SEQ_ERROR) which
are cleared upon read. The Rx Port status registers also allow the user to monitor the presence of the stable
input signal, along with parity and CRC errors, line length, and lines per video frame.
7.4.10.1 RX Parity Status
The FPD-Link III receiver checks the decoded data parity to detect any errors in the received FPD-Link III frame.
Parity errors are counted up and accessible through the RX_PAR_ERR_HI and RX_PAR_ERR_LO registers
0x55 and 0x56 to provide combined 16-bit error counter. In addition, a parity error flag can be set once a
programmed number of parity errors have been detected. This condition is indicated by the PARITY_ERROR
flag in the RX_PORT_STS1 register. Reading the counter value will clear the counter value and
PARITY_ERROR flag. An interrupt may also be generated based on assertion of the parity error flag. By default,
the parity error counter will be cleared and the flag will be cleared on loss of Receiver lock. To ensure an exact
read of the parity error counter, parity checking should be disabled in the GENERAL_CFG register 0x02 before
reading the counter.
7.4.10.2 FPD-Link Decoder Status
The FPD-Link III receiver also checks the decoded data for encoding or sequence errors in the received FPD-
Link III frame. If either of these error conditions are detected the FPD3_ENC_ERROR bit will be latched in the
RX_PORT_STS2 register 0x4E[5]. An interrupt may also be generated based on assertion of the encoded error
flag. To detect FPD-Link III Encoder errors, the LINK_ERROR_COUNT must be enabled with a
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LINK_ERR_THRESH value greater than 1. Otherwise, the loss of Receiver Lock will prevent detection of the
Encoder error. The FPD3_ENC_ERROR flag is cleared on read.
When partnered with a DS90UB63x-Q1, the FPD3 Encoder may be configured to include a CRC check of the
FPD3 encoder sequence. The CRC check provides an extra layer of error checking on the encoder sequence.
This CRC checking adds protection to the encoder sequence used to send link information comprised of
Datapath Control (registers 0x59 and 0x5A), Sensor Status (registers 0x51-0x54), and Serializer ID (register
0x5B). TI recommends enabling the CRC error checking on the FPD3 Encoder sequence to prevent any updates
of link information values from encoded packets that do not pass CRC check. The FPD3 Encoder CRC is
enabled by setting the FPD3_ENC_CRC_DIS (register 0xBA[7] 表 7-137) to 0. In addition, the
FPD3_ENC_CRC_CAP flag should be set in register 0x4A[4] (see 节7.7.57).
7.4.10.3 RX Port Input Signal Detection
The DS90UB638-Q1 can detect and measure the approximate input frequency and frequency stability of the RX
input port and indicate status in bits [2:1] of RX_PORT_STS2. Frequency measurement stable FREQ_STABLE
indicates the FPD-Link III input clock frequency is stable. When no FPD-Link III input clock is detected at the RX
input port the NO_FPD3_CLK bit indicates that condition has occurred. Setting of these error flags is dependent
on the stability control settings in the FREQ_DET_CTL register 0x77. The NO_FPD3_CLK bit will be set if the
input frequency is below the setting programmed in the FREQ_LO_THR setting in the FREQ_DET_CTL register.
A change in frequency FREQ_STABLE = 0, is defined as any change in MHz greater than the value
programmed in the FREQ_HYST value. The frequency is continually monitored and provided for readback
through the I2C interface less than every 1 ms. A 16-bit value is used to provide the frequency in units of 2 to 8
MHz. An interrupt can also be generated for the RX ports to indicate if a change in frequency is detected on the
port.
7.4.10.4 Line Counter
For each video frame received, the deserializer will count the number of video lines in the frame. In CSI-2 input
mode, any long packet will be counted as a video line. The LINE_COUNT_1 and LINE_COUNT_0 registers in
0x73 and 0x74 can be used to read the line count for the most recent video frame. An interrupt may be enabled
based on a change in the LINE_COUNT value. If interrupts are enabled, the LINE_COUNT registers will be
latched at the interrupt and held until read back by the processor through I2C.
7.4.10.5 Line Length
For each video line, the length (in bytes) will be determined. The LINE_LEN_1 and LINE_LEN_0 registers 0x75
and 0x76 can be used to read the line count for the most recent video frame. If the line length is not stable
throughout the frame, the length of the last line of the frame will be reported. Line Count may not be consistent
when receiving multiple CSI-2 video streams differentiated by VC-ID. An interrupt may be enabled based on a
change in the LINE_LEN value. If interrupts are enabled, the LINE_LEN registers will be latched at the interrupt
and held until read by the processor through I2C.
7.4.11 Sensor Status
When paired with the DS90UB63x-Q1 CSI-2 serializer, the DS90UB638-Q1 is capable of receiving diagnostic
indicators from the serializer. The sensor alarm and status diagnostic information are reported in the
SENSOR_STS_X registers (0x51 to 0x54 in 表 7-80). The interrupt capability from detected status changes in
sensor are described in 节 7.5.7.2.2. Sensor Status This interrupt condition will be cleared by reading the
SEN_INT_RISE_STS and SEN_INT_FALL_STS registers.
7.4.12 GPIO Support
In addition to the dedicated LOCK and PASS output pins, the DS90UB638-Q1 supports seven pins, GPIO0
through GPIO6, which can be monitored, configured, and controlled through I2C in registers 0x0E - 0x16. GPIO3
programmable I/O pin is an active-low open drain and is shared with INTB. The current status of all GPIO can be
readback from register 0x0E. Each GPIO is programmable for multiple uses options through the
GPIOx_PIN_CTL registers 0x10 - 0x16.
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7.4.12.1 GPIO Input Control and Status
Upon initialization GPIO0 through GPIO6 are enabled as inputs by default. Each GPIO pin has an input disable
and a pulldown disable control bit, with the exception of GPIO3 which is open drain. By default, the GPIO pin
input paths are enabled and the internal pulldown circuit for the GPIO is enabled. The GPIO_INPUT_CTL (0x0F)
and GPIO_PD_CTL (0xBE) registers allow control of the input enable and the pulldown, respectively. For
example, to disable GPIO1 and GPIO2 as inputs the user would program in register 0x0F[2:1] = 11. For most
applications, there is no need to modify the default register settings for the pulldown resistors. The status HIGH
or LOW of each GPIO pin 0 through 6 may be read through the GPIO_PIN_STS register 0x0E. This register
read operation provides the status of the GPIO pin independent of whether the GPIO pin is configured as an
input or output.
7.4.12.2 GPIO Output Pin Control
Individual GPIO output pin control is programmable through the GPIOx_PIN_CTL registers 0x10 to 0x16 (表
7-33). To enable any of the GPIO as output, set bit 0 = 1 in the respective register 0x10 to 0x16 after clearing the
corresponding input enable bit in register 0x0F (表 7-32). The configuration register for each GPIO is listed in 表
7-6.
图7-4. GPIOx Register Content (0x10 - 0x16)
7
6
5
4
3
2
1
0
GPIOX_OUTPUT_SEL[2:0]
GPIOX_OUT_SRC[2:0]
GPIOX_OUT_V GPIOX_OUT_E
AL
N
表7-6. GPIOx Output Function Programming
GPIOX OUTPUT
SOURCE SELECT
GPIOX_OUT_SRC[2:0]
GPIOX OUTPUT
GPIO OUTPUT
ENABLE (GPIOX_OUT
EN)
FUNCTION SELECT
GPIOX_OUTPUT_SEL[2
:0]
GPIOX OUTPUT VALUE
(GPIOX_OUT_VAL)
GPIO OUTPUT FUNCTION
OUTPUT
SIGNAL
SOURCE
VALUE
No output.
GPIO is
Disabled or set
to input mode
GPIOX output disabled
X
X
X
0
GPIOX linked to Forward channel received GPIO0
from RX Port 0 Serializer
000
001
010
011
X
X
X
X
1
1
1
1
GPIOX linked to Forward channel received GPIO1
from RX Port 0 Serializer
GPIOX linked to Forward channel received GPIO2
from RX Port 0 Serializer
000 RX Port 0
GPIOX linked to Forward channel received GPIO3
from RX Port 0 Serializer
RX Port 0 Lock indication
RX Port 0 Pass indication
RX Port 0 Frame Valid signal
RX Port 0 Line Valid signal
Reserved
100
101
110
111
X
X
X
X
X
X
0
1
1
1
1
X
1
1
1
1
1
1
1
1
X
010 Reserved
100 Device Status
100 Reserved
Set GPI0X = LOW value programmed by register
Set GPIOX = HIGH value programmed by register
Lock indication from enabled RX port
RESERVED
000
000
001
010
011
100
101
110
111
1
X
X
X
X
X
X
X
RESERVED
FrameSync signal (internal or external)
Device interrupt active high
Device interrupt active low
Reserved
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表7-6. GPIOx Output Function Programming (continued)
GPIOX OUTPUT
SOURCE SELECT
GPIOX_OUT_SRC[2:0]
GPIOX OUTPUT
GPIO OUTPUT
ENABLE (GPIOX_OUT
FUNCTION SELECT
GPIOX_OUTPUT_SEL[2
:0]
GPIOX OUTPUT VALUE
(GPIOX_OUT_VAL)
GPIO OUTPUT FUNCTION
OUTPUT
SIGNAL
SOURCE
EN)
VALUE
Reserved
Pass
000
001
X
X
1
1
Frame Valid signal corresponding to video frame
recovered at deserializer
010
011
X
X
1
1
101 CSI-2 Tx Port
Line Valid signal corresponding to video frame
recovered at deserializer
Reserved
100
101
110
111
X
X
X
X
X
X
X
1
1
CSI-2 TX Port Interrupt active high
Reserved
Reserved
Reserved
Reserved
101 Reserved
101 Reserved
110 Reserved
X
X
X
X
111
Reserved
X
7.4.12.3 Forward Channel GPIO
The DS90UB638-Q1 seven GPIO pins can output data received from the forward channel when paired with the
DS90UB63x-Q1 CSI-2 serializer. The remote Serializer GPIO are mapped to a Deserializer GPIO. Each GPIO
pin can be programmed for output mode and mapped. Up to four GPIOs are supported in the forward direction
on the FPD-Link III Receive port (see 表 7-87). Each forward channel GPIO can be mapped to any GPIO output
pin.
The timing for the forward channel GPIO is dependant on the number of GPIOs assigned at the serializer. When
a single GPIO input from the DS90UB63x-Q1 CSI-2 serializer is linked to a DS90UB638-Q1 deserializer, the
GPIO output value is sampled every forward channel transmit frame. Two linked GPIO are sampled every two
forward channel frames and three or four linked GPIO are sampled every five frames. The typical minimum
latency for the GPIO remains consistent (approximately 200 ns), but as the information gets spread over multiple
frames, the jitter is typically increased on the order of the sampling period (number of forward channel frames).
TI recommends maintaining a 4x over-sampling ratio for linked GPIO throughput. For example, when operating
at -Gbps with REFCLK = 25 MHz, the maximum recommended GPIO input frequency based on the number of
GPIO linked over the forward channel is shown in 表7-7.
表7-7. Forward Channel GPIO Typical Timing
NUMBER OF LINKED
FORWARD CHANNEL GPIOs
(FC_GPIO_EN 表7-87)
SAMPLING FREQUENCY (MHz)
AT FPD-Link III LINE RATE =
Gbps
MAXIMUM RECOMMENDED
FORWARD CHANNEL GPIO
FREQUENCY (MHz)
TYPICAL JITTER (ns)
1
2
4
121.25
60.63
30.31
30.31
15.15
7.57
12
24
60
In addition to mapping remote serializer GPI, an internally generated FrameSync (see 节 7.4.25) or other control
signals may be output from any of the deserializer GPIOs for synchronization with a local processor or another
deserializer.
7.4.12.4 Back Channel GPIO
Each DS90UB638-Q1 GPIO pin defaults to input mode at start-up. The deserializer can link GPIO pin input data
on up to four available slots to send on the back channel per each remote serializer connection. Any of the
seven GPIO pin data can be mapped to send over the available back channel slots for each FPD-Link III Rx port.
The same GPIO on the deserializer pin can be mapped to multiple back channel GPIO signals. For 10-Mbps
back channel operation, the frame period is 3 µs (30 bits × 100 ns/bit). As the back channel GPIOs are sampled
and sent each back channel frame by the DS90UB638-Q1 deserializer, the latency and jitter timing are each on
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the order of one back channel frame. The back channel GPIO is effectively sampled at a rate of 1/30 of the back
channel rate or 333 kHz at fBC = 10 Mbps. TI recommends that the input to back channel GPIO switching
frequency is < 1/4 of the sampling rate or 83 kHz at fBC = 10 Mbps. For example, when operating at Gbps with
REFCLK = 25 MHz, the maximum recommended GPIO input frequency based on the data rate when linked over
the back channel is shown in 表7-8.
表7-8. Back Channel GPIO Typical Timing
MAXIMUM
BACK CHANNEL RATE SAMPLING FREQUENCY RECOMMENDED BACK
TYPICAL LATENCY (us)
TYPICAL JITTER (us)
(Mbps)
(kHz)
CHANNEL GPIO
FREQUENCY (kHz)
10
334
83.5
3.2
3
In addition to sending GPIO from pins, an internally generated FrameSync or external FrameSync input signal
may be mapped to any of the back channel GPIOs for synchronization of multiple sensors with extremely low
skew. (see 节7.4.25).
For each port, GPIO control is available through the BC_GPIO_CTL0 register 0x6E (see 表 7-108) and
BC_GPIO_CTL1 register 0x6F (see 表7-109).
7.4.12.5 Other GPIO Pin Controls
Each GPIO pin can has a input disable and a pulldown disable. By default, the GPIO pin input paths are enabled
and the internal pulldown circuit in the GPIO is enabled. The GPIO_INPUT_CTL register 0x0F and
GPIO_PD_CTL register 0xBE allow control of the input enable and the pulldown respectively. For most
applications, there is no need to modify the default register settings.
7.4.13 Line Valid and Frame Valid Indicators
The FrameValid (FV) and LineValid (LV) indications from the Receive Port indicate approximate frame and line
boundaries at the FPD-Link III Receiver input. These signals may not be accurate if the receiver is in CSI-2 input
mode and multiple video streams are present at the Receive Port input. A common example of this scenario
would be multiple Virtual Channel IDs received on a single port.
The DS90UB638-Q1 allows setting the polarity of these signals by register programming. The FV and LV polarity
are controlled on a per-port basis and can be independently set in the PORT_CONFIG2 register 0x7C.
To prevent false detection of FrameValid, FV must be asserted for a minimum number of clocks prior to first
video line to be considered valid. The minimum FrameValid time is programmable in the FV_MIN_TIME register
0xBC.
FV
TFV_LV
LV
图7-5. Minimum FV to LV
For other settings of FV_MIN_TIME, the required FV to LV setup in Serializer PCLKs can be determined by:
Absolute Min + (FV_MIN_TIME × Conversion factor)
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表7-9. Minimum FV to LV Setup Requirement (in RAW Mode Serializer FPD-Link III PCLKs)
FV_MIN_TIME
CONVERSION FACTOR
ABSOLUTE MIN
(FV_MIN_TIME = 0)
DEFAULT
(FV_MIN_TIME = 128)
MODE
RAW12 HF
RAW10
1.5
2
3
5
195
261
For other settings of FV_MIN_TIME, the required FV to LV setup in Serializer PCLKs can be determined by:
Absolute Min + (FV_MIN_TIME × Conversion factor)
7.4.14 CSI-2 Protocol Layer
The DS90UB638-Q1 implements High-Speed mode to forward CSI-2 Low Level Protocol data. This includes
features as described in the Low Level Protocol section of the MIPI CSI-2 Specification. It supports short and
long packet formats.
The feature set of the protocol layer implemented by the CSI-2 TX is:
• Transport of arbitrary data (payload-independent)
• 8-bit word size
• Support for up to four interleaved virtual channels on the same link
• Special packets for frame start, frame end, line start and line end information
• Descriptor for the type, pixel depth and format of the Application Specific Payload data
• 16-bit Checksum Code for error detection
图7-6 shows the CSI-2 protocol layer with short and long packets.
DATA:
Short
Packet
Long
Packet
Long
Packet
Short
Packet
ST SP ET
ST PH
DATA
PF ET
ST PH
DATA
PF ET
ST SP ET
LPS
LPS
LPS
KEY:
ST œ Start of Transmission
ET œ End of Transmission
LPS œ Low Power State
PH œ Packet Header
PF œ Packet Footer
图7-6. CSI-2 Protocol Layer With Short and Long Packets
7.4.15 CSI-2 Short Packet
The short packet provides frame or line synchronization. 图 7-7 shows the structure of a short packet. A short
packet is identified by data types 0x00 to 0x0F.
32-bit SHORT PACKET (SH)
Data Type (DT) = 0x00 œ 0x0F
图7-7. CSI-2 Short Packet Structure
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7.4.16 CSI-2 Long Packet
A long packet consists of three elements: a 32-bit packet header (PH), an application-specific data payload with
a variable number of 8-bit data words, and a 16-bit packet footer (PF). The packet header is further composed of
three elements: an 8-bit data identifier, a 16-bit word count field, and an 8-bit ECC. The packet footer has one
element, a 16-bit checksum. 图7-8 shows the structure of a long packet.
32-bit
PACKET
HEADER
(PH)
PACKET DATA:
16-bit
PACKET
FOOTER
(PF)
Length = Word Count (WC) * Data Word
Width (8-bits). There are NO restrictions
on the values of the data words
图7-8. CSI-2 Long Packet Structure
表7-10. CSI-2 Long Packet Structure Description
PACKET PART
FIELD NAME
SIZE (BIT)
DESCRIPTION
VC / Data ID
Word Count
8
Contains the virtual channel identifier and the data-type information.
Number of data words in the packet data. A word is 8 bits.
16
Header
ECC for data ID and WC field. Allows 1-bit error recovery and 2-bit
error detection.
ECC
8
Data
Data
WC × 8
16
Application-specific payload (WC words of 8 bits).
16-bit cyclic redundancy check (CRC) for packet data.
Footer
Checksum
7.4.17 CSI-2 Data Type Identifier
The DS90UB638-Q1 MIPI CSI-2 protocol interface transmits the data identifier byte containing the values for the
virtual channel ID (VC) and data type (DT) for the application specific payload data, as shown in 图 7-9. The
virtual channel ID is contained in the 2 MSBs of the data identifier byte and identify the data as directed to one of
four virtual channels. The value of the data type is contained in the six LSBs of the data identifier byte. When
partnered with DS90UB63x-Q1 CSI-2 serializer, the Data Type is passed through from the received CSI-2
packets.
Data Identifier (DI) Byte
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
VC
DT
Virtual Channel
Indentifier
(VC)
Data Type
(DT)
图7-9. CSI-2 Data Identifier Structure
7.4.18 Virtual Channel and Context
The CSI-2 protocol layer transports virtual channels. Each virtual channel is identified by a unique channel
identification number in the packet header. Therefore, a CSI-2 TX context can be associated with a virtual
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channel and a data type. Virtual channels are defined by a 2-bit field. This channel identification number is
encoded in the 2-bit code.
The CSI-2 TX transmits the channel identifier number. The CSI-2 TX supports up to four concurrent virtual
channels.
7.4.19 CSI-2 Transmitter Frequency
The CSI-2 Transmitters may operate nominally at 400 or 800 Mbps, or 1.6 Gbps. This operation is controlled
through the CSI_PLL_CTL 0x1F register (see 表 7-48). The actual CSI-2 rate is proportional to the REFCLK
frequency.
表7-11. Net CSI-2 Bandwidth Options
CSI-2 TX DATA RATE PER
LANE (Mbps)
NET CSI-2 VIDEO BANDWIDTH
(Gbps)
CSI_PLL_CTL[1:0]
REFCLK FREQUENCY (MHz)
1664
1600
26
25
3.328
3.2
00
1472
23
2.944
Reserved
1.6
01
10
11
Reserved
800
Reserved
25
400
25
0.8
When configuring to 800 Mbps or 1.6 Gbps, the CSI-2 timing parameters are automatically set based on the
CSI_PLL_CTL 0x1F register. In the case of alternate settings, the respective CSI-2 timing parameters registers
must be programmed, and the appropriate override bit must be set. For the 1.664-Gbps and 1.472-Gbps options,
these settings will also affect internal device timing for back channel operation, I2C, Bidirectional Control
Channel, and FrameSync operation which scale with the REFCLK frequency.
To operate CSI-2 at speed of 400-Mbps mode, set CSI_PLL_CTL to 11b (0x1F[1:0] =11) to enable 400-Mbps
operation for the CSI-2 Transmitters. Internal PLL and Timers are then automatically adjusted for the reduced
reference clock frequency. Software control of CSI-2 Transmitter timing registers is required to provide proper
interface timing on the CSI-2 Output. The following are the recommended timer settings for 400-Mbps operation.
# Set CSI-2 Timing parameters
WriteI2C(0xB0,0x2)
WriteI2C(0xB1,0x40)
WriteI2C(0xB2,0x83)
WriteI2C(0xB2,0x8D)
WriteI2C(0xB2,0x87)
WriteI2C(0xB2,0x87)
WriteI2C(0xB2,0x83)
WriteI2C(0xB2,0x86)
WriteI2C(0xB2,0x84)
WriteI2C(0xB2,0x86)
WriteI2C(0xB2,0x84)
# set auto-increment, page 0
# CSI-2 Port 0
# TCK Prep
# TCK Zero
# TCK Trail
# TCK Post
# THS Prep
# THS Zero
# THS Trail
# THS Exit
# TLPX
7.4.20 CSI-2 Replicate Mode
In CSI-2 Replicate mode, both ports can be programmed to output the same data. The output from CSI-2 port 0
is also presented on CSI-2 port 1.
To configure this mode of operation, set the CSI_REPLICATE bit in the FWD_CTL2 register (Address 0x21 in 表
7-50). Enabling replicate mode will automatically enable the second CSI-2 Clock output signal. The CSI-2
transmitter must be programmed for one or two lanes only through the CSI_LANE_COUNT field in the CSI_CTL
register as only one or two lanes are supported.
7.4.21 CSI-2 Transmitter Output Control
Two register bits allow controlling the CSI-2 Transmitter output state. If the OUTPUT_SLEEP_STATE_SELECT
(OSS_SEL) control is set to 0 in the GENERAL_CFG 0x02 register (see 表 7-19), the CSI-2 Transmitter outputs
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are forced to the HS-0 state. If the OUTPUT_ENABLE (OEN) register bit is set to 0 in the GENERAL_CFG
register, the CSI-2 pins are set to the high-impedance state.
For normal operation (OSS_SEL and OEN both set to 1), activity on either of the Rx Port determines the state of
the CSI-2 outputs. The CSI-2 Pin State during FPD-Link III inactive includes two options, controlled by the
OUTPUT_EN_MODE bit in the GENERAL_CFG register and FWD_PORTx_DIS in the FWD_CTL1 register
0x20. If OUTPUT_EN_MODE is set to 0, a lack of activity will force the outputs to Hi-Z condition. If
OUTPUT_EN_MODE is set to 1, or if the forwarding for the Rx Port is disabled (FWD_PORTx_DIS = 1), the
output enters LP-11 state as there is no data available to the CSI-2 Transmitter input. The FPD-Link III input is
considered active if the Receiver indicates valid lock to the incoming signal. For a CSI-2 TX port, lock is
considered valid if the Received port mapped to the TX port is indicating Lock. See section 节 7.4.6 for
description of Rx port forwarding.
表7-12. CSI-2 Output Control Options
OUTPUT_O
EN_MODE
PDB PIN
OSS_SEL
OEN
FWD_PORTx_DIS
FPD-Link III INPUT
CSI-2 PIN STATE
0
1
1
1
1
1
1
X
0
1
1
1
1
1
X
X
0
1
1
1
1
X
X
X
0
X
X
X
X
X
1
X
Hi-Z
HS-0
Hi-Z
X
X
All inactive
All inactive
Any active
Any active
Hi-Z
1
LP-11
LP-11
Valid
X
X
0
7.4.22 CSI-2 Transmitter Status
The status of the CSI-2 Transmitter may be monitored by readback of the CSI_STS register 0x35, or brought to
one of the configurable GPIO pins as an output. The TX_PORT_PASS 0x35[0] indicates valid CSI-2 data being
presented on CSI-2 port. If no data is being forwarded or if error conditions have been detected on the video
data, the CSI-2 Pass signal will be cleared. Interrupts may also be generated based on changes in the CSI-2
port status.
7.4.23 Video Buffers
The DS90UB638-Q1 implements a video line buffer and FIFO. The video buffer provides storage of data payload
and forward requirements for sending multiple video streams on the CSI-2 transmit ports. The total line buffer
memory size is a 16-kB block.
The CSI-2 transmitter waits for an entire packet to be available before pulling data from the video buffer.
7.4.24 CSI-2 Line Count and Line Length
The DS90UB638-Q1 counts the number of received lines (long packets) to determine line count on
LINE_COUNT_1 and LINE_COUNT_0 registers 0x73–74. For received line length, DS90UB638-Q1 reads the
number of bytes per line in LINE_LEN_1 and LINE_LEN_0 registers 0x75–0x76. Line Count and Line Length
values are valid when receiving a single video stream. If multiple virtual channels are received on a FPD-Link III
Receive port in CSI-2 input mode, the values in registers 0x73-74 may not be accurate
7.4.25 FrameSync Operation
A frame synchronization signal (FrameSync) can be sent through the back channel using any of the back
channel GPIOs. The signal can be generated in two different methods. The first option offers sending the
external FrameSync using one of the available GPIO pins on the DS90UB638-Q1 and mapping that GPIO to a
back channel GPIO on the FPD-Link III port.
The second option is to have the DS90UB638-Q1 internally generate a FrameSync signal to send through the
back channel GPIO to the attached Serializer.
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7.4.25.1 External FrameSync Control
In External FrameSync mode, an external signal is input to the DS90UB638-Q1 through one of the GPIO pins on
the device. The external FrameSync signal may be propagated to one or more of the attached FPD-Link III
Serializers through a GPIO signal in the back channel. The expected skew timing for external FrameSync mode
is on the order of one back channel frame period or 3 µs when operating at 10 Mbps.
638 Deserializer
FPD-Link III
GPIOx
BC_GPIOx
Serializer
GPIOy
External
Frame Synch
图7-10. External FrameSync
Enabling the external FrameSync mode is done by setting the FS_MODE control in the FS_CTL register to a
value between 0x8 (GPIO0 pin) to 0xF (GPIO7 pin). Set FS_GEN_ENABLE to 0 for this mode.
To send the FrameSync signal on a port’s BC_GPIOx signal, the BC_GPIO_CTL0 or BC_GPIO_CTL1 register
should be programmed for that port to select the FrameSync signal.
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7.4.25.2 Internally Generated FrameSync
In Internal FrameSync mode, an internally generated FrameSync signal is sent to the attached FPD-Link III
Serializer through a GPIO signal in the back channel.
FrameSync operation is controlled by the FS_CTL 0x18, FS_HIGH_TIME_x, and FS_LOW_TIME_x 0x19–0x1A
registers. The resolution of the FrameSync generator clock (FS_CLK_PD) is derived from the back channel
frame period (see BC_FREQ_SELECT[2:0] in 表7-86). For example, each 50-Mbps back channel operation, the
frame period is 600 ns (30 bits × 20 ns/bit), and for 2.5-Mbps back channel operation, the frame period is 12 μs
(30 bits × 400 ns/bit).
Once enabled, the FrameSync signal is sent continuously based on the programmed conditions.
Enabling the internal FrameSync mode is done by setting the FS_GEN_ENABLE control in the FS_CTL register
to a value of 1. The FS_MODE field controls the clock source used for the FrameSync generation. The
FS_GEN_MODE field configures whether the duty cycle of the FrameSync is 50/50 or whether the high and low
periods are controlled separately. The FrameSync high and low periods are controlled by the FS_HIGH_TIME
and FS_LOW_TIME registers.
The accuracy of the internally generated FrameSync is directly dependent on the accuracy of the 25-MHz
oscillator used as the reference clock and timing values should be scaled if reference other than 25 MHz is used.
638 Deserializer
FPD-Link III
GPIOx
BC_GPIOx
Serializer
FrameSync
Generator
图7-11. Internal FrameSync With DS90UB638 Deserializer
FS_HIGH
FS_LOW
FS_LOW = FS_LOW_TIME * FS_CLK_PD
FS_HIGH = FS_HIGH_TIME * FS_CLK_PD
where FS_CLK_PD is the resolution of the FrameSync generator clock
图7-12. Internal FrameSync Signal
The following example shows generation of a FrameSync signal at 60 pulses per second. Mode settings:
• Programmable High/Low periods: FS_GEN_MODE 0x18[1]=0
• Use port 0 back channel frame period: FS_MODE 0x18[7:4]=0x0
• Back channel rate of 50 Mbps: BC_FREQ_SELECT for port 0 0x58[2:0]=110b
• Initial FS state of 0: FS_INIT_STATE 0x18[2]=0
Based on mode settings, the FrameSync is generated based upon FS_CLK_PD of 600 ns.
The total period of the FrameSync is (1 / 60 hz) / 600 ns or approximately 27778 counts. The high time is
programmed to 2778 and the low time is programmed to 25000.
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For a 10% duty cycle, set the high time to 2777 (0x0AD9) cycles, and the low time to 24999 (0x61A7) cycles:
• FS_HIGH_TIME_1: 0x19=0x0A
• FS_HIGH_TIME_0: 0x1A=0xD9
• FS_LOW_TIME_1: 0x1B=0x61
• FS_LOW_TIME_0: 0x1C=0xA7
7.4.25.2.1 Code Example for Internally Generated FrameSync
WriteI2C(0x4C,0x01) # RX0
WriteI2C(0x6E,0xAA) # BC_GPIO_CTL0: FrameSync signal to GPIO0/1
WriteI2C(0x10,0x91A) # FrameSync signal; Device Status; Enabled
WriteI2C(0x19,0x0A) # FS_HIGH_TIME_1
WriteI2C(0x1A,0xD9) # FS_HIGH_TIME_0
WriteI2C(0x1B,0x61) # FS_LOW_TIME_1
WriteI2C(0x1C,0xA7) # FS_LOW_TIME_0
WriteI2C(0x18,0x01) # Enable FrameSync
7.5 Programming
7.5.1 Serial Control Bus and Bidirectional Control Channel
The DS90UB638-Q1 implements an I2C-compatible serial control bus. The I2C is for local device configuration
and incorporates a bidirectional control channel (BCC) that allows communication across the FPD-Link cable
with remote serializers, as well as with remote I2C target devices. The DS90UB638-Q1 implements an I2C-
compatible target that can be compliant with the standard, fast, and fast-plus modes of operation. This allows
I2C operation at up to 1-MHz clock frequencies. When paired with a DS90UB63x-Q1 serializer, the DS90UB638-
Q1 supports a combined format I2C read and write access. The timing for the I2C interface is shown in 图6-4.
For accesses to local registers, the I2C target operates without stretching the clock. Accesses to remote devices
over the bidirectional control channel results in clock stretching to allow for response time across the link. The
DS90UB638-Q1 can also act as I2C controller for regenerating bidirectional control channel accesses originating
from the remote devices across FPD-Link. Set I2C_CONTROLLER_EN in register 0x02[5] = 1 to enable the
proxy controller functionality of the deserializer.
7.5.1.1 Bidirectional Control
The bidirectional control channel (BCC) supports 10-Mbps operation when attached to the DS90UB63x-Q1. The
bidirectional control channel is compatible with I2C devices, which allows local I2C target access to device
registers as well as bidirectional I2C operation across the link to the serializer and attached devices. I2C access
should not be attempted across the link when Rx Port Lock status is low. In addition to providing BCC operation,
the back channel signaling also supports GPIO operations and advertising device capabilities to the attached
serializer device. The default back channel frequency is selected by the strap setting of the MODE pin.
7.5.1.2 Device Address
The primary device address is set through a resistor divider (RHIGH and RLOW — see Serial Control Bus
Connection below) connected to the IDX pin. Note that the voltage of VI2C must match the voltage of VVDDIO
.
The DS90UB638-Q1 waits 1 ms after PDB goes high to allow time for power supply transients before the IDX
value is sampled and the device is configured to set the I2C address. The primary I2C target address is stored in
the I2C Device ID register at address 0x0. In addition to the primary I2C target address, the DS90UB638-Q1
may be programmed to respond to up to 2 other I2C addresses. The two RX Port ID addresses provide direct
access to the Receive Port 0 registers, which means the user does not need to set the paging controls normally
required to access the port registers. The I2C_RX0_ID register is located in register address 0xF8.
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VDD18
R
HIGH
VI2C VI2C
IDX
RPU
RPU
R
LOW
HOST
Deserializer
SCL
SDA
SCL
SDA
To other Devices
图7-13. Serial Control Bus Connection
The IDX pin configures the control interface to one of eight possible device addresses. A pullup resistor and a
pulldown resistor may be used to set the appropriate voltage ratio between the IDX input pin (VIDX) and V(VDD18)
,
each ratio corresponding to a specific device address. See Serial Control Bus Addresses for IDX for more
information.
表7-13. Serial Control Bus Addresses for IDX
VIDX VOLTAGE RANGE
VIDX TARGET
VOLTAGE
SUGGESTED STRAP
RESISTORS (1% TOL)
PRIMARY ASSIGNED I2C
ADDRESS
NO
.
VMIN
VTYP
VMAX
(V); VDD1P8 =
1.8 V
RHIGH ( kΩ )
RLOW ( kΩ )
7-BIT
0x30
8-BIT
0x60
0
1
0
0
0.131 × V(VDD18)
0.247 × V(VDD18)
0
OPEN
88.7
10.0
23.2
0.179 ×
V(VDD18)
0.213 ×
V(VDD18)
0.374
0x32
0x34
0x36
0x38
0x3A
0x3C
0x3D
0x64
0x68
0x6C
0x70
0x74
0x78
0x7A
2
3
4
5
6
7
0.296 ×
V(VDD18)
0.330 ×
V(VDD18)
0.362 × V(VDD18)
0.474 × V(VDD18)
0.592 × V(VDD18)
0.704 × V(VDD18)
0.823 × V(VDD18)
V(VDD18)
0.582
0.792
0.995
1.202
1.420
1.8
75.0
71.5
78.7
39.2
25.5
10.0
35.7
56.2
0.412 ×
V(VDD18)
0.443 ×
V(VDD18)
0.525 ×
V(VDD18)
0.559 ×
V(VDD18)
97.6
0.642 ×
V(VDD18)
0.673 ×
V(VDD18)
78.7
0.761 ×
V(VDD18)
0.792 ×
V(VDD18)
95.3
0.876 ×
V(VDD18)
V(VDD18)
OPEN
7.5.1.3 Basic I2C Serial Bus Operation
The serial control bus consists of two signals, SCL and SDA. SCL is a serial bus clock input, and SDA is the
serial bus data input / output signal. Both SCL and SDA signals require an external pullup resistor to 1.8-V or
3.3-V nominal V(VDDIO). For most applications, TI recommends a 4.7-kΩ pullup resistor to V(VDDIO). However, the
pullup resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either
pulled high or driven low.
The serial bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions low while SDA is high. A STOP occurs when SDA transitions high while SCL is also high. See 图
7-14.
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SDA
SCL
S
P
START condition, or
START repeat condition
STOP condition
图7-14. START and STOP Conditions
To communicate with a target device, the host controller (controller) sends the target address and listens for a
response from the target. This response is referred to as an acknowledge bit (ACK). If a target on the bus is
addressed correctly, it acknowledges (ACKs) the controller by driving the SDA bus low. If the address does not
match the target address of the device, it not-acknowledges (NACKs) the controller by letting SDA be pulled
high. ACKs also occur on the bus when data is being transmitted. When the controller is writing data, the target
ACKs after every data byte is successfully received. When the controller is reading data, the controller ACKs
after every data byte is received to let the target know that the controller wants to receive another data byte.
When the controller wants to stop reading, it NACKs after the last data byte and creates a stop condition on the
bus. All communication on the bus begins with either a START or START-Repeated condition. All communication
on the bus ends with a STOP condition. A READ is shown in 图7-15 and a WRITE is shown in 图7-16.
N
A
C
K
Bus Activity:
Controller
Register
Address
Target
Address
Target
Address
S
P
SDA
Line
S
7-bit Address
7-bit Address
0
1
A
C
K
A
C
K
A
C
K
Data
Bus Activity:
Target
图7-15. Serial Control Bus —READ
Bus Activity:
Controller
Register
Address
Tagret
Address
Data
SDA Line
7-bit Address
P
S
0
A
C
K
A
C
K
A
C
K
Bus Activity:
Target
图7-16. Serial Control Bus —WRITE
For more information on I2C interface requirements and throughput considerations, refer to I2C Communication
Over FPD-Link III With Bidirectional Control Channel (SNLA131A).
7.5.2 I2C Target Operation
The DS90UB638-Q1 implements an I2C-compatible target that can be compliant with the Standard, Fast, and
Fast-plus modes of operation, which allows I2C operation at up to 1-MHz clock frequencies. Local I2C
transactions to access DS90UB638-Q1 registers can be conducted 2 ms after power supplies are stable and
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PDB is brought high. For accesses to local registers, the I2C target operates without stretching the clock. The
primary I2C target address is set through the IDx pin. The primary I2C target address is stored in the I2C Device
ID register at address 0x0. In addition to the primary I2C target address, the DS90UB638-Q1 may be
programmed to respond to up to two other I2C addresses. The RX Port ID address provides direct access to the
Receive Port registers without the need to set the paging controls normally required to access the port registers.
7.5.3 Remote Target Operation
The bidirectional control channel provides a mechanism to read or write I2C registers in remote devices over the
FPD-Link III interface. The I2C controller located at the deserializer must support I2C clock stretching. Accesses
to serializer or remote target devices over the bidirectional control channel will result in clock stretching to allow
for response time across the link. The DS90UB638-Q1 acts as an I2C target on the local bus, forwards read and
write requests to the remote device, and returns the response from the remote device to the local I2C bus. To
allow for the propagation and regeneration of the I2C transaction at the remote device, the DS90UB638-Q1 will
stretch the I2C clock while waiting for the remote response. The I2C address of the serializer is populated in
register 0x5B of the DS90UB638-Q1. The BCC_CONFIG register 0x58 must also have bit 6,
I2C_PASS_THROUGH, set to 1. If enabled, local I2C transactions with a valid address decode are then
forwarded through the bidirectional control channel to the remote I2C bus. When I2C_PASS_THROUGH is set,
the deserializer will only propagate messages that the deserializer recognizes, such as the registered serializer
alias address (SER_ALIAS), or the registered remote target alias attached to the serializer I2C bus
(TARGET_ALIAS). Setting PASS_THROUGH_ALL and AUTO_ACK are less common use cases and are
primarily used for debugging I2C messaging because they will respectively pass all addresses regardless of
valid I2C address (PASS_THROUGH_ALL) and acknowledge all I2C commands without waiting for a response
from serializer (AUTO_ACK).
7.5.4 Remote Target Addressing
Eight pairs of TargetAlias and TargetID registers are allocated for the FPD-Link III Receive port in registers 0x5C
through 0x6C. The TargetAlias register allows programming a virtual address which the host controller uses to
access the remote device. The TargetID register provides the actual target address for the device on the remote
I2C bus.
7.5.5 I2C Controller Proxy
The DS90UB638-Q1 implements an I2C controller that acts as a proxy controller to regenerate I2C accesses
originating from a remote serializer. By default, the I2C Controller Enable bit (I2C_CONTROLLER_EN) in
register 0x05[2] = 0 to block controller access to the local deserialilzer I2C from remote serializers. Set
I2C_CONTROLLER_EN] = 1 if system requires the deserializer to act as proxy controller for remote serializers
on the local deserializer I2C bus. The proxy controller is an I2C-compatible controller, capable of operating with
Standard-mode, Fast-mode, or Fast-mode Plus I2C timing. The deserializer is also capable of arbitration with
other controllers, which allows multiple controllers and targets to exist on the I2C bus. A separate I2C proxy
controller is implemented for each Receive port. This allows independent operation for all sources to the I2C
interface. Arbitration between multiple sources is handled automatically using I2C multi-controller arbitration.
7.5.6 I2C Controller Proxy Timing
The proxy controller timing parameters are based on the REFCLK timing. Timing accuracy for the I2C proxy
controller is based on the REFCLK or XTL clock source attached to the DS90UB638-Q1 deserializer. Before
REFCLK is applied, the deserializer will default to an internal reference clock with 25-MHz ±10% accuracy. The
I2C controller regenerates the I2C read or write access using timing controls in the registers 0xA and 0xB to
regenerate the clock and data signals to meet the desired I2C timing in Standard, Fast, or Fast-plus modes of
operation.
I2C controller SCL high time is set in register 0x0A[7:0]. This field configures the high pulse width of the SCL
output when the serializer is the controller on the local deserializer I2C bus. The default value is set to provide a
minimum 5-µs SCL high time with the reference clock at 25 MHz + 100 ppm, including four additional oscillator
clock periods or synchronization and response time. Units are 40 ns for the nominal oscillator clock frequency,
giving Min_delay = 40 ns × (SCL_HIGH_TIME + 4).
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I2C controller SCL low time is set in register 0x0B[7:0]. This field configures the low pulse width of the SCL
output when the serializer is the controller on the local deserializer I2C bus. This value is also used as the SDA
setup time by the I2C target to provide data before SCL is released during accesses over the bidirectional
control channel. The default value is set to provide a minimum 5-µs SCL high time with the reference clock at 25
MHz + 100 ppm, including four additional oscillator clock periods or synchronization and response time. Units
are 40 ns for the nominal oscillator clock frequency, giving Min_delay = 40 ns × (SCL_HIGH_TIME + 4). See 表
7-14 example settings for Standard mode, Fast mode, and Fast Mode Plus timing.
表7-14. Typical I2C Timing Register Settings
SCL HIGH TIME
SCL LOW TIME
I2C MODE
NOMINAL DELAY AT
REFCLK = 25 MHz
NOMINAL DELAY AT
REFCLK = 25 MHz
0x0A[7:0]
0x0B[7:0]
Standard
Fast
0x7A
0x13
0x06
5.04 µs
0.920 µs
0.400 s
0x7A
0x25
0x0C
5.04 µs
1.64 µs
0.640 µs
Fast - Plus
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7.5.6.1 Code Example for Configuring Fast Mode Plus I2C Operation
#
"RX0 I2C Controller Fast Plus Configuration"
WriteI2C(0x02,0x3E) # Enable Proxy
WriteI2C(0x4c,0x01) # Select RX_PORT0
# Set SCL High and Low Time delays
WriteI2C(0x0a,0x06) # SCL High
WriteI2C(0x0b,0x0C) # SCL Low
7.5.7 Interrupt Support
Interrupts can be brought out on the INTB pin as controlled by the INTERRUPT_CTL 0x23 and
INTERRUPT_STS 0x24 registers. The main interrupt control registers provide control and status for interrupts
from the individual sources. Sources include the FPD-Link III receive port as well as the CSI-2 transmit port.
Clearing interrupt conditions requires reading the associated status register for the source. The setting of the
individual interrupt status bits is not dependent on the related interrupt enable controls. The interrupt enable
controls whether an interrupt is generated based on the condition, but does not prevent the interrupt status
assertion.
The DS90UB638-Q1 devices have built-in flexibility such that the main interrupt may be brought to any GPIO pin
through the GPIOx_PIN_CTL register for that pin (see 表 7-33). Note that the GPIO3 pin is the only GPIO that is
implemented as open-drain, so this is the preferred pin for signaling the interrupt.
For an interrupt to be generated based on one of the interrupt status assertions, both the individual interrupt
enable and the INT_EN control must be set in the INTERRUPT_CTL 0x23 register. For example, to generate an
interrupt if IS_RX0 is set, both the IE_RX0 and INT_EN bits must be set. If IE_RX0 is set but INT_EN is not, the
INT status is indicated in the INTERRUPT_STS register, and the INTB pin does not indicate the interrupt
condition.
See the INTERRUPT_CTL 0x23 and INTERRUPT_STS 0x24 registers for details.
7.5.7.1 Code Example to Enable Interrupts
#
"RX0/1 INTERRUPT_CTL enable"
WriteI2C(0x23,0xBF) # RX all & INTB PIN EN
# Individual RX0/1 INTERRUPT_CTL enable
# "RX0 INTERRUPT_CTL enable"
WriteI2C(0x4C,0x01) # RX0
WriteI2C(0x23,0x81) # RX0 & INTB PIN EN
7.5.7.2 FPD-Link III Receive Port Interrupts
For the FPD-Link III Receive port, multiple options are available for generating interrupts. Interrupt generation is
controlled through the PORT_ICR_HI 0xD8 and PORT_ICR_LO 0xD9 registers. In addition, the PORT_ISR_HI
0xDA and PORT_ISR_LO 0xDB registers provide read-only status for the interrupts. Clearing of interrupt
conditions is handled by reading the RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS registers. The
status bits in the PORT_ISR_HI/LO registers are copies of the associated bits in the main status registers.
To enable interrupts from one of the receive port interrupt sources:
1. Enable the interrupt source by setting the appropriate interrupt enable bit in the PORT_ICR_HI or
PORT_ICR_LO register.
2. Set the RX Port X Interrupt control bit (IE_RXx) in the INTERRUPT_CTL register.
3. Set the INT_EN bit in the INTERRUPT_CTL register to allow the interrupt to assert the INTB pin low.
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To clear interrupts from one of the receive port interrupt sources:
1. (optional) Read the INTERRUPT_STS register to determine which RX Port caused the interrupt.
2. (optional) Read the PORT_ISR_HI and PORT_ISR_LO registers to determine source of interrupt.
3. Read the appropriate RX_PORT_STS1, RX_PORT_STS2, or CSI_RX_STS register to clear the interrupt.
The first two steps are optional. The interrupt can be determined and cleared by just reading the status registers.
7.5.7.2.1 Interrupts on Forward Channel GPIO
When connected to the DS90UB63x-Q1 CSI-2 serializer, interrupts can be generated on changes in any of the
four forward channel GPIOs per port. Interrupts are enabled by setting bits in the FC_GPIO_ICR register.
Interrupts may be generated on rising and/or falling transitions on the GPIO signal. The GPIO interrupt status is
cleared by reading the FC_GPIO_STS register.
Interrupts should only be used for GPIO signals operating at less than 10 MHz. High or low pulses that are less
than 100 ns might not be detected at the DS90UB638-Q1. To avoid false interrupt indications, the interrupts
should not be enabled until after the forward channel GPIOs are enabled at the serializer.
7.5.7.2.2 Interrupts on Change in Sensor Status
The FPD-Link III receiver can recover 32 bits of sensor status from the attached DS90UB63x-Q1 CSI-2
serializer. Interrupts may be generated based on changes in the sensor status values received from the forward
channel. The sensor status has 4 bytes of data, which may be read from the SENSOR_STS_x registers for each
receive port. Interrupts may be generated based on a change in any of the bits in the first byte
(SENSOR_STS_0). Each bit can be individually masked for rising and/or falling interrupts.
Two registers control the interrupt masks for the SENSOR_STS bits: SEN_INT_RISE_CTL and
SEN_INT_FALL_CTL.
Two registers provide interrupt status: SEN_INT_RISE_STS, SEN_INT_FALL_STS.
If a mask bit is set, a change in the associated SENSOR_STS_0 bit will be detected and latched in the
SEN_INT_RISE_STS or SEN_INT_FALL_STS registers. If the mask bit is not set, the associated interrupt status
bit will always be 0. If any of the SEN_INT_RISE_STS or SEN_INT_FALL_STS bits is set, the IS_FC_SEN_STS
bit will be set in the PORT_ISR_HI register.
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7.5.7.3 Code Example to Readback Interrupts
INTERRUPT_STS = ReadI2C(0x24) # 0x24 INTERRUPT_STS
if ((INTERRUPT_STS & 0x80) >> 7):
print "# GLOBAL INTERRUPT DETECTED "
if ((INTERRUPT_STS & 0x40) >> 6):
print "# RESERVED "
if ((INTERRUPT_STS & 0x10) >> 4):
print "# IS_CSI_TX DETECTED "
if ((INTERRUPT_STS & 0x01) ):
print "# IS_RX0 DETECTED "
# "################################################"
#
"RX0 status"
# "################################################"
WriteReg(0x4C,0x01) # RX0
PORT_ISR_LO = ReadI2C(0xDB)
print "0xDB PORT_ISR_LO : ", hex(PORT_ISR_LO) # readout; cleared by RX_PORT_STS2
if ((PORT_ISR_LO & 0x40) >> 6):
print "# IS_LINE_LEN_CHG INTERRUPT DETECTED "
if ((PORT_ISR_LO & 0x20) >> 5):
print "# IS_LINE_CNT_CHG DETECTED "
if ((PORT_ISR_LO & 0x10) >> 4):
print "# IS_BUFFER_ERR DETECTED "
if ((PORT_ISR_LO & 0x08) >> 3):
print "# IS_CSI_RX_ERR DETECTED "
if ((PORT_ISR_LO & 0x04) >> 2):
print "# IS_FPD3_PAR_ERR DETECTED "
if ((PORT_ISR_LO & 0x02) >> 1):
print "# IS_PORT_PASS DETECTED "
if ((PORT_ISR_LO & 0x01) ) :
print "# IS_LOCK_STS DETECTED "
################################################
PORT_ISR_HI = ReadI2C(0xDA)
print "0xDA PORT_ISR_HI : ", hex(PORT_ISR_HI) # readout; cleared by RX_PORT_STS2
if ((PORT_ISR_HI & 0x04) >> 2):
print "# IS_FPD3_ENC_ERR DETECTED "
if ((PORT_ISR_HI & 0x02) >> 1):
print "# IS_BCC_SEQ_ERR DETECTED "
if ((PORT_ISR_HI & 0x01) ) :
print "# IS_BCC_CRC_ERR DETECTED "
################################################
RX_PORT_STS1 = ReadI2C(0x4D) # R/COR
if ((RX_PORT_STS1 & 0xc0) >> 6) == 0:
print "# RX_PORT_NUM = RX0"
if ((RX_PORT_STS1 & 0x20) >> 5):
print "# BCC_CRC_ERR DETECTED "
if ((RX_PORT_STS1 & 0x10) >> 4):
print "# LOCK_STS_CHG DETECTED "
if ((RX_PORT_STS1 & 0x08) >> 3):
print "# BCC_SEQ_ERROR DETECTED "
if ((RX_PORT_STS1 & 0x04) >> 2):
print "# PARITY_ERROR DETECTED "
if ((RX_PORT_STS1 & 0x02) >> 1):
print "# PORT_PASS=1 "
if ((RX_PORT_STS1 & 0x01) ):
print "# LOCK_STS=1 "
################################################
RX_PORT_STS2 = ReadI2C(0x4E)
if ((RX_PORT_STS2 & 0x80) >> 7):
print "# LINE_LEN_UNSTABLE DETECTED "
if ((RX_PORT_STS2 & 0x40) >> 6):
print "# LINE_LEN_CHG "
if ((RX_PORT_STS2 & 0x20) >> 5):
print "# FPD3_ENCODE_ERROR DETECTED "
if ((RX_PORT_STS2 & 0x10) >> 4):
print "# BUFFER_ERROR DETECTED "
if ((RX_PORT_STS2 & 0x08) >> 3):
print "# CSI_ERR DETECTED "
if ((RX_PORT_STS2 & 0x04) >> 2):
print "# FREQ_STABLE DETECTED "
if ((RX_PORT_STS2 & 0x02) >> 1):
print "# NO_FPD3_CLK DETECTED "
if ((RX_PORT_STS2 & 0x01) ):
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print "# LINE_CNT_CHG DETECTED "
################################################
7.5.7.4 CSI-2 Transmit Port Interrupts
The following interrupts are available for each CSI-2 Transmit Port:
• Pass indication
• Deassertion of Pass indication for an input port assigned to the CSI-2 TX port
• RX Port Interrupt –interrupts from the RX port mapped to this CSI-2 transmit port
See the CSI_TX_ICR address 0x36 and CSI_TX_ISR address 0x37 registers for details.
The setting of the individual interrupt status bits is not dependent on the related interrupt enable controls. The
interrupt enable controls whether an interrupt is generated based on the condition, but does not prevent the
interrupt status assertion.
7.5.8 Error Handling
In the DS90UB638-Q1, the FPD-Link III receiver transfers incoming video frames to internal video buffers for
forwarding to the CSI-2 Transmit ports. When the DS90UB638-Q1 detects an error condition, the standard
operation would be to flag this error condition and truncate sending the CSI-2 frame to avoid sending corrupted
data downstream. When the DS90UB638-Q1 recovers from an error condition, it will provide Start of Frame and
resume sending valid data. Consequently, when the downstream CSI-2 input receives a repeated Start of Frame
condition, this will indicate that the data received in between the prior start of frame is suspect, and the signal
processor can then discard the suspected data. The settings in registers PORT_CONFIG2 (0x7C) and
PORT_PASS_CTL (0x7D) can be used to change how the DS90UB638-Q1 handles errors when passing video
frames. The receive port may be configured to qualify the incoming video, providing a status indication and
preventing the forward of video frames until certain error-free conditions are met. The Pass indication may be
used to prevent forwarding packets to the internal video buffers by setting the PASS_DISCARD_EN bit in the
PORT_PASS_CTL register. When this bit is set, video input will be discarded until the Pass signal indicates valid
receive data. The receive port will indicate Pass status once specific conditions are met, including a number of
valid frames received. Valid frames may include requiring no FPD-Link III parity errors and consistent frame size
including video line length and/or number of video lines.
In addition, the receive port may be programmed to truncate video frames containing errors or prevent the
forwarding of video until the Pass conditions are met. Register settings in PORT_CONFIG2 register 0x7C can be
used to truncate frames on different line/frame sizes or a CSI-2 parity error is detected. When the deserializer
truncates frames in cases of different line/frame sizes different line/frame sizes, the video frame will stop
immediately with no frame end packet. Often the condition will not be cleared until the next valid frame is
received.
The Rx port PASS indication may be used to prevent forwarding packets to the internal video buffers by setting
the PASS_DISCARD_EN bit in the PORT_PASS_CTL register 0x7D. When this bit is set, video input will be
discarded until the Pass signal indicates valid receive data. The incoming video frames may be truncated based
on error conditions or change in video line size or number of lines. These functions are controlled by bits in the
PORT_CONFIG2 register. When truncating video frames, the video frame may be truncated after sending any
number of video lines. A truncated frame will not send a Frame End packet to the CSI-2 transmit port.
7.5.8.1 Receive Frame Threshold
The FPD-Link III receiver may be programmed to require a specified number of valid video frames prior to
indicating a Pass condition and forwarding video frames. The number of required valid video frames is
programmable through the PASS_THRESH field in the PORT_PASS_CTL register 0x7D (表 7-121). The
threshold can be programmed from 0 to 3 video frames. If set to 0, Pass will typically be indicated as soon as the
FPD-Link III receiver reports lock to the incoming signal. If set greater than 0, the receiver will require that
number of valid frames before indicating Pass. Determination of valid frames will be dependent on the control
bits in the PORT_PASS_CTL register. In the case of a parity error, when PASS_PARITY_ERR is set to 1,
forwarding will be enabled one frame early. To ensure at least one good frame occurs following a parity error, the
counter should be set to 2 or higher when PASS_PARITY_ERR = 1.
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7.5.8.2 Port PASS Control
When the PASS_LINE_SIZE control is set in the PORT_PASS_CTL register, the receiver will qualify received
frames based on having a consistent video line size. For PASS_LINE_SIZE to be clear, the deserializer checks
that the received line length remains consistent during the frame and between frames. For each video line, the
length (in bytes) will be determined. If it varies then we will flag this condition. Each video line in the packet must
be the same size, and the line size must be consistent across video frames. A change in video line size will
restart the valid frame counter.
When the PASS_LINE_CNT control is set in the PORT_PASS_CTL register, the receiver will qualify received
frames based on having a consistent frame size in number of lines. A change in number of video lines will restart
the valid frame counter.
When the PASS_PARITY_ERR control is set in the PORT_PASS_CTL register, the receiver will clear the Pass
indication on receipt of a parity error on the FPD-Link III interface. The valid frame counter will also be cleared on
the parity error event. When PASS_PARITY_ERR is set to 1, TI also recommends setting PASS_THRESHOLD
to 2 or higher to ensure at least one good frame occurs following a parity error.
7.5.9 Pattern Generation
The DS90UB638-Q1 supports an internal pattern generation feature to provide a simple way to generate video
test patterns for the CSI-2 transmitter outputs. Two types of patterns are supported—the reference color bar
pattern and fixed color pattern—accessed by the Pattern Generator page 0 in the indirect register set.
Prior to enabling the Pattern Generator, the following should be done:
1. Disable video forwarding by setting bits [5:4] of the FWD_CTL1 register (that is, set register 0x20 to 0x30).
2. Configure CSI-2 Transmitter operating speed using the CSI_PLL_CTL register.
3. Enable the CSI-2 Transmitter for port 0 using the CSI_CTL register.
7.5.9.1 Reference Color Bar Pattern
The reference color bar patterns are based on the pattern defined in Appendix D of the mipi_CTS_for_D-
PHY_v1-1_r03 specification. The pattern is an eight color bar pattern designed to provide high, low, and medium
frequency outputs on the CSI-2 transmit data lanes.
The CSI-2 reference pattern provides eight color bars by default with the following byte data for the color bars: X
bytes of 0xAA (high-frequency pattern, inverted) X bytes of 0x33 (mid-frequency pattern) X bytes of 0xF0 (low-
frequency pattern, inverted) X bytes of 0x7F (lone 0 pattern) X bytes of 0x55 (high-frequency pattern) X bytes of
0xCC (mid-frequency pattern, inverted) X bytes of 0x0F (low-frequency pattern) Y bytes of 0x80 (lone 1 pattern)
In most cases, Y will be the same as X. For certain data types, the last color bar may need to be larger than the
others to properly fill the video line dimensions.
The Pattern Generator is programmable with the following options:
• Number of color bars (1, 2, 4, or 8)
• Number of bytes per line
• Number of bytes per color bar
• CSI-2 DataType field and VC-ID
• Number of active video lines per frame
• Number of total lines per frame (active plus blanking)
• Line period (possibly program in units of 10 ns)
• Vertical front porch –number of blank lines prior to FrameEnd packet
• Vertical back porch –number of blank lines following FrameStart packet
The pattern generator relies on proper programming by software to ensure the color bar widths are set to
multiples of the block (or word) size required for the specified DataType. For example, the block size is 3 bytes
for RGB888, which also matches the pixel size. In this case, the number of bytes per color bar must be a
multiple of 3. The Pattern Generator is implemented in the CSI-2 transmit clock domain, providing the pattern
directly to the CSI-2 transmitter. The circuit generates the CSI-2 formatted data.
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7.5.9.2 Fixed Color Patterns
When programmed for fixed color pattern mode, Pattern Generator can generate a video image with a
programmable fixed data pattern. The basic programming fields used for image dimensions are the same ones
used for the color bar patterns. When sending fixed color patterns, the color bar controls allow alternating
between the fixed pattern data and the bit-wise inverse of the fixed pattern data.
The fixed color patterns assume a fixed block size for the byte pattern to be sent. The block size is
programmable through the register and is designed to support most 8-bit, 10-bit, and 12-bit pixel formats. The
block size should be set based on the pixel size converted to blocks that are an integer multiple of bytes. For
example, an RGB888 pattern would consist of 3-byte pixels and therefore require a 3-byte block size. A 2x12-bit
pixel image would also require 3-byte block size, while a 3x12-bit pixel image would require nine bytes (two
pixels) to send an integer number of bytes.
The fixed color patterns support block sizes up to 16 bytes in length, allowing additional options for patterns in
some conditions. For example, an RGB888 image could alternate between four different pixels by using a
twelve-byte block size. An alternating black and white RGB888 image could be sent with a block size of 6-bytes
and setting first three bytes to 0xFF and next three bytes to 0x00.
To support up to 16-byte block sizes, a set of sixteen registers are implemented to allow programming the value
for each data byte. The line period is calculated in units of 10 ns, unless the CSI-2 mode is set to 400-Mb
operation in which case the unit time dependancy is 20 ns.
7.5.9.3 Packet Generator Programming
The information in this section provides details on how to program the Pattern Generator to provide a specific
color bar pattern, based on datatype, frame size, and line size.
Most basic configuration information is determined directly from the expected video frame parameters. The
requirements should include the datatype, frame rate (frames per second), number of active lines per frame,
number of total lines per frame (active plus blanking), and number of pixels per line.
• PGEN_ACT_LPF –Number of active lines per frame
• PGEN_TOT_LPF –Number of total lines per frame
• PGEN_LSIZE –Video line length size in bytes. Compute based on pixels per line multiplied by pixel size in
bytes
• CSI-2 DataType field and VC-ID
• Optional: PGEN_VBP –Vertical back porch. This is the number of lines of vertical blanking following Frame
Valid
• Optional: PGEN_VFP –Vertical front porch. This is the number of lines of vertical blanking preceding Frame
Valid
• PGEN_LINE_PD –Line period in 10-ns units. Compute based on Frame Rate and total lines per frame
• PGEN_BAR_SIZE –Color bar size in bytes. Compute based on datatype and line length in bytes (see
details below)
7.5.9.3.1 Determining Color Bar Size
The color bar pattern should be programmed in units of a block or word size dependent on the datatype of the
video being sent. The sizes are defined in the Mipi CSI-2 specification. For example, RGB888 requires a 3-byte
block size which is the same as the pixel size.
When programming the Pattern Generator, software should compute the required bar size in bytes based on the
line size and the number of bars. For the standard eight color bar pattern, that would require the following
algorithm:
• Select the desired datatype, and a valid length for that datatype (in pixels).
• Convert pixels/line to blocks/line (by dividing by the number of pixels/block, as defined in the datatype
specification).
• Divide the blocks/line result by the number of color bars (8), giving blocks/bar
• Round result down to the nearest integer
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• Convert blocks/bar to bytes/bar and program that value into the PGEN_BAR_SIZE register
As an alternative, the blocks/line can be computed by converting pixels/line to bytes/line and divide by bytes/
block.
7.5.9.4 Code Example for Pattern Generator
#Patgen Fixed Colorbar 1280x720p30
WriteI2C(0x33,0x01) # CSI0 enable
WriteI2C(0xB0,0x00) # Indirect Pattern Gen Registers
WriteI2C(0xB1,0x01) # PGEN_CTL
WriteI2C(0xB2,0x01)
WriteI2C(0xB1,0x02) # PGEN_CFG
WriteI2C(0xB2,0x33)
WriteI2C(0xB1,0x03) # PGEN_CSI_DI
WriteI2C(0xB2,0x24)
WriteI2C(0xB1,0x04) # PGEN_LINE_SIZE1
WriteI2C(0xB2,0x0F)
WriteI2C(0xB1,0x05) # PGEN_LINE_SIZE0
WriteI2C(0xB2,0x00)
WriteI2C(0xB1,0x06) # PGEN_BAR_SIZE1
WriteI2C(0xB2,0x01)
WriteI2C(0xB1,0x07) # PGEN_BAR_SIZE0
WriteI2C(0xB2,0xE0)
WriteI2C(0xB1,0x08) # PGEN_ACT_LPF1
WriteI2C(0xB2,0x02)
WriteI2C(0xB1,0x09) # PGEN_ACT_LPF0
WriteI2C(0xB2,0xD0)
WriteI2C(0xB1,0x0A) # PGEN_TOT_LPF1
WriteI2C(0xB2,0x04)
WriteI2C(0xB1,0x0B) # PGEN_TOT_LPF0
WriteI2C(0xB2,0x1A)
WriteI2C(0xB1,0x0C) # PGEN_LINE_PD1
WriteI2C(0xB2,0x0C)
WriteI2C(0xB1,0x0D) # PGEN_LINE_PD0
WriteI2C(0xB2,0x67)
WriteI2C(0xB1,0x0E) # PGEN_VBP
WriteI2C(0xB2,0x21)
WriteI2C(0xB1,0x0F) # PGEN_VFP
WriteI2C(0xB2,0x0A)
7.5.10 FPD-Link BIST Mode
An optional at-speed built-in self test (BIST) feature supports high-speed serial link and the back channel testing
without external data connections. The BIST mode is enabled by either applying a logic high level to the BISTEN
pin or by programming the BIST configuration register 0xB3. This is useful in the prototype stage, equipment
production, in-system test, and system diagnostics.
When BIST is activated, the DS90UB638-Q1 sends register writes to the serializer through the back channel.
The control channel register writes configure the serializer for BIST mode operation. The serializer outputs a
continuous stream of a pseudo-random sequence and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The serializer also tracks errors indicated by the CRC fields in each back
channel frame.
The LOCK, PASS and CMLOUT output functions are all available during BIST mode. While the lock indications
are required to identify the beginning of proper data reception, for any link failures or data corruption, the best
indication is the contents of the error counter in the BIST_ERR_COUNT register 0x57 for the RX port. The test
may select whether the serializer uses an external or internal clock as reference for the BIST pattern frequency.
7.5.10.1 BIST Operation Through BISTEN Pin
One method to enable BIST is by driving a logic high level on the BISTEN pin. During pin control BIST, the
values on GPIO1 and GPIO0 pins will control whether the serializer uses an external or internal clock for the
BIST pattern. The values on GPIO1 and GPIO0 will be written to the serializer register 0x14[2:1]. A value of 00
will select an external clock. A non-zero value will enable an internal clock of the frequency defined in the
serializer register 0x14. The GPIO1 and GPIO0 values are sampled at the start of BIST (when BISTEN pin
transitions to high). Changing this value after BIST is enabled will not change operation. Link BIST can also be
enabled by register control through the BIST control register (address 0xB3)
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7.5.10.2 BIST Operation Through Register Control
The FPD-Link III BIST is configured and enabled by programming the BIST control register (address 0xB3).
BIST pass or fail status may be brought to GPIO pins by selecting the Pass indication for each receive port using
the GPIOx_PIN_CTL registers. The Pass/Fail status will be deasserted low for each data error detected on the
selected port input data. In addition, it is advisable to bring the receiver lock status for the port to the GPIO pins
as well. After completion of BIST, the BIST error counter may be read to determine if errors occurred during the
test. If the DS90UB638-Q1 failed to lock to the input signal or lost lock to the input signal, the BIST error counter
will indicate 0xFF. The maximum normal count value will be 0xFE. The SER_BIST_ACT register bit 0xD0[5] can
be monitored during testing to ensure BIST is activated in the serializer.
During BIST, DS90UB638-Q1 output activity are gated by BIST_Control[7:6] (BIST_OUT_MODE[1:0]). as
follows:
00 : Outputs disabled during BIST
10 : Outputs enabled during BIST
When enabling the outputs by setting BIST_OUT_MODE = 10, the CSI-2 will be inactive by default (LP11 state).
To exercise the CSI-2 interface during BIST mode, it is possible to enable the Pattern Generator to send a video
data pattern on the CSI-2 outputs.
The BIST clock frequency is controlled by the BIST_CLOCK_SOURCE field in the BIST Control register. This 2-
bit value will be written to the serializer register 0x14[2:1]. A value of 00 will select an external clock. A non-zero
value will enable an internal clock of the frequency defined in the serializer register 0x14. The
BIST_CLOCK_SOURCE field is sampled at the start of BIST. Changing this value after BIST is enabled will not
change operation.
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7.6 Unique ID
Each device is programmed with a Unique DIE-ID that is burnt into devices at wafer level; Unique DIE-ID with a
16 bytes customer readable value indicating wafer lot and position of each IC inside a wafer. Combination of
Unique DIE-IDs can be read and maintained by customer in a database or in a Hash table. Each system can be
identified by the Unique DIE-ID programmed into the devices. Authenticity of the overall system can be
established at the powerup/initialization or periodically by checking the Unique DIE-ID.
A Unique DIE-ID is programmed into each device and can be read using I2C reads. To read the Unique DIE-ID,
set the IA_SEL (0xB0[5:2]) register to Unique DIE ID Registers (1001), then set register IND_ACC_ADDR
(0xB1) address to the Unique ID register being read, and then read the IND_ACC_DATA (0xB2) register to get
the Unique DIE-ID. There are 16 Unique ID registers, each of the registers contain 8 bits of the total unique DIE-
ID. The table below lists the Unique ID registers addresses.
表7-15. Unique ID Registers
Unique ID register
UNIQUE_ID_0
UNIQUE_ID_1
UNIQUE_ID_2
UNIQUE_ID_3
UNIQUE_ID_4
UNIQUE_ID_5
UNIQUE_ID_6
UNIQUE_ID_7
UNIQUE_ID_8
UNIQUE_ID_9
UNIQUE_ID_10
UNIQUE_ID_11
UNIQUE_ID_12
UNIQUE_ID_13
UNIQUE_ID_14
UNIQUE_ID_15
IND_ACC_ADDR address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
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7.7 Register Maps
The DS90UB638-Q1 implements the following register blocks, accessible via I2C as well as the bi-directional
control channel:
• Main Registers
• FPD-Link III RX Port Registers
• CSI-2 Port Registers (separate register block for each of the CSI-2 ports)
表7-16. Main Register Map Descriptions
ADDRESS RANGE
0x00-0x31
DESCRIPTION
ADDRESS MAP
Digital Shared Registers
Shared
0x32-0x3A
Digital CSI-2 Tx Port Registers
Reserved
Shared
0x3B - 0x4B
0x4C-0x7F
Reserved
Digital RX Port Registers
(paged, broadcast write allowed)
FPD3 RX Port 0
R: 0x4C[5:4]=00
W: 0x4C[0]=1
0x80-0x9F
0xA0-0xAF
0xB0-0xB2
0xB0-0xBF
0xC0-0xCF
0xD0-0xDF
0xE0-0xEF
0xF0-0xF5
0xF8-0xFB
Reserved
Reserved
Reserved
Shared
Reserved
Indirect Access Registers
Digital Share Registers
Reserved
Shared
Reserved
FPD3 RX Port 0
Reserved
Shared
Digital RX Port Debug Registers
Reserved
FPD3 RX ID
Port I2C Addressing
Reserved
Shared
0xF6-0xF7
0xFC-0xFF
Reserved
LEGEND:
•
•
•
•
RW = Read Write
RW/SC = RW/SC = Read Write access/Self Clearing bit
R = Read Only, Permanent value
R/COR = Read Only, Clear On Read
7.7.1 I2C Device ID Register
The I2C Device ID Register field always indicates the current value of the I2C ID. When bit 0 of this register is 0,
this field is read-only and shows the strapped ID from device initialization after power on. When bit 0 of this
register is 1, this field is read/write and can be used to assign any valid I2C ID address to the deserializer.
表7-17. I2C Device ID (Address 0x00)
BIT
FIELD
TYPE
DEFAULT DESCRIPTION
7:1
DEVICE_ID
RW
0x3D
0
7-bit I2C ID of Deserializer.
0: Device ID is from strap
1: Register I2C Device ID overrides strapped value
0
DES_ID
RW
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7.7.2 Reset Register
The Reset register allows for soft digital reset of the DS90UB638-Q1 device internal circuitry without using PDB
hardware analog reset. Digital Reset 0 is recommended if desired to reset without overwriting configuration
registers to default values.
表7-18. Reset (Address 0x01)
BIT
FIELD
TYPE
DEFAULT DESCRIPTION
7:3
RESERVED
RW
0x00
Reserved
Restart Auto-load
Setting this bit to 1 causes a re-load of the default settings including
MODE and IDX. This bit is self-clearing. Software may check for Auto-
load complete by checking the CFG_INIT_DONE bit in the
DEVICE_STS register.
RESTART
_AUTOLOAD
2
RW/SC
0
Digital Reset 1
Resets the entire digital block including registers. This bit is self-
1
0
DIGITAL_RESET1
DIGITAL_RESET0
RW/SC
RW/SC
0
0
clearing.
1: Reset
0: Normal operation
Digital Reset 0
Resets the entire digital block except registers. This bit is self-clearing.
1: Reset
0: Normal operation
7.7.3 General Configuration Register
The general configuration register enables and disables high level block functionality.
表7-19. General Configuration (Address 0x02)
BIT
FIELD
TYPE
DEFAULT DESCRIPTION
7:6
RESERVED
RW
0
Reserved
I2C Controller Enable. This bit must be set if system requires the
deserializer to act as proxy controller for remote I2C access to the local
I2C bus from remote serializers.
0: Block proxy Controller access to local I2C from remote serializers
1: Enable proxy Controller access to local I2C from remote serializers
I2C_CONTROLLER
_ENABLE
5
RW
0
Output Enable Mode. If set to 0, the CSI TX output port will be forced to
the high-impedance state the assigned RX port has an active Receiver
lock. If set to 1 and no assigned RX ports have an active Receiver lock
the CSI TX output port will continue in normal operation and enter the
LP-11 state. CSI TX operation will remain under register control via the
CSI_CTL register for each port.
4
3
OUTPUT_EN_MODE RW
1
1
Output Enable Control (usage dependant on Output Sleep State
Select). If OUTPUT_SLEEP_STATE_SEL is set to 1 and
OUTPUT_ENABLE is set to 0, the CSI TX outputs will be forced into a
high impedance state.
OUTPUT_ENABLE
RW
OSS Select to control output state when LOCK is low (usage
dependant on Output Enable) When OUTPUT_SLEEP _STATE
_SELECT is set to 0, the CSI TX outputs will be forced into a HS-0
state.
OUTPUT_SLEEP
_STATE _SELECT
2
1
0
RW
RW
RW
1
1
0
RX_PARITY
_CHECKER
_ENABLE
FPD-Link III Parity Checker Enable
0: Disable
1: Enable
Force indication of external reference clock
0: Normal operation, reference clock detect circuit indicates the
presence of an external reference clock
FORCE_REFCLK
_DET
1: Force reference clock to be indicated present
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7.7.4 Revision/Mask ID Register
Revision ID field for production silicon version can be read back from this register.
表7-20. Revision/Mask ID (Address 0x03)
BIT
7:4
3:0
FIELD
TYPE
DEFAULT
DESCRIPTION
REVISION_ID
MASK_ID
R
R
0x2
0
Revision ID field (Note that 0x2 corresponds to the production device)
Mask ID
7.7.5 DEVICE_STS Register
Device status register provides read back access to high level link diagnostics.
表7-21. DEVICE_STS (Address 0x04)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Configuration Checksum Passed. CFG_CKSUM_STS bit is set to one
following initialization if the Configuration data had a valid checksum
7
CFG_CKSUM_STS
R
1
Power-up initialization complete. CFG_INIT_DONE bit is set to one
after Initialization is complete.
6
5
CFG_INIT_DONE
RESERVED
R
R
1
0
Reserved
REFCLK valid frequency bit indicates when a valid frequency has
been detected on the REFCLK pin.
0 : Invalid frequency detected
4
3
REFCLK_VALID
PASS
R
R
0
0
1 : REFCLK frequency between 12MHz and 64MHz.
Device PASS status This bit indicates the PASS status for the device.
The value in this register matches the indication on the PASS pin.
Device LOCK status This bit indicates the LOCK status for the device.
The value in this register matches the indication on the LOCK pin.
2
LOCK
R
R
0
1:0
RESERVED
11
Reserved
7.7.6 PAR_ERR_THOLD_HI Register
If the FPD-Link III receiver detects a number of parity errors greater than or equal to total value in
PAR_ERR_THOLD[15:0], the PARITY_ERROR flag is set in the RX_PORT_STS1 register.
PAR_ERR_THOLD_HI contains bits [15:8] of the 16 bit parity error threshold PAR_ERR_THOLD[15:0].
表7-22. PAR_ERR_THOLD_HI (Address 0x05)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
FPD3 Parity Error Threshold High byte
This register provides the 8 most significant bits [15:8] of the Parity
Error Threshold value PAR_ERR_THOLD[15:0].
PAR_ERR_THOLD
_HI
7:0
RW
0x01
7.7.7 PAR_ERR_THOLD_LO Register
If the FPD-Link III receiver detects a number of parity errors greater than or equal to total value in
PAR_ERR_THOLD[15:0], the PARITY_ERROR flag is set in the RX_PORT_STS1 register.
PAR_ERR_THOLD_LO contains bits [7:0] of the 16 bit parity error threshold PAR_ERR_THOLD[15:0].
表7-23. PAR_ERR_THOLD_LO (Address 0x06)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
FPD3 Parity Error Threshold Low byte
This register provides the 8 least significant bits [7:0] of the Parity
Error Threshold value PAR_ERR_THOLD[15:0].
PAR_ERR_THOLD
_LO
7:0
RW
0
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7.7.8 BCC Watchdog Control Register
The BCC watchdog timer allows termination of a control channel transaction if it fails to complete within a
programmed amount of time.
表7-24. BCC Watchdog Control (Address 0x07)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
BCC_WATCHDOG
_TIMER
Sets the Bidirectional Control Channel Watchdog Timeout value in
units of 2 milliseconds. This field should not be set to 0.
7:1
RW
0x7F
Disable Bidirectional Control Channel Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation
BCC_WATCHDOG
_TIMER_DISABLE
0
RW
0
7.7.9 I2C Control 1 Register
表7-25. I2C Control 1 (Address 0x08)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Disable Remote Writes to Local Registers
Setting this bit to a 1 will prevent remote writes to local device
registers from across the control channel. This prevents writes to the
Deserializer registers from an I2C controller attached to the
Serializer. Setting this bit does not affect remote access to I2C
targets at the Deserializer.
LOCAL_WRITE
_DISABLE
7
RW
0
Internal SDA Hold Time
6:4
3:0
I2C_SDA_HOLD
RW
0x1
This field configures the amount of internal hold time provided for the
SDA input relative to the SCL input. Units are 40 nanoseconds.
I2C Glitch Filter Depth
This field configures the maximum width of glitch pulses on the SCL
and SDA inputs that will be rejected. Units are 5 nanoseconds.
I2C_FILTER_DEPTH RW
0xC
7.7.10 I2C Control 2 Register
表7-26. I2C Control 2 (Address 0x09)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Remote Ack SDA Output Setup
When a Control Channel (remote) access is active, this field
configures setup time from the SDA output relative to the rising edge
of SCL during ACK cycles. Setting this value will increase setup time
SDA_OUTPUT_SET
UP
in units of 640ns. The nominal output setup time value for SDA to
SCL are:
7:4
RW
1
00 : 80ns
01: 720ns
10: 1400ns
11: 2080ns
SDA Output Delay
This field configures additional delay on the SDA output relative to
the falling edge of SCL. Setting this value increases output delay in
SDA_OUTPUT_DEL
AY
units of 40ns. Nominal output delay values for SCL to SDA are:
3:2
RW
RW
0
0
00 : 240ns
01: 280ns
10: 320ns
11: 360ns
Speed up I2C Bus Watchdog Timer
1: Watchdog Timer expires after approximately 50 microseconds
0: Watchdog Timer expires after approximately 1 second.
I2C_BUS_TIMER
_SPEEDUP
1
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BIT
表7-26. I2C Control 2 (Address 0x09) (continued)
FIELD
TYPE
DEFAULT
DESCRIPTION
Disable I2C Bus Watchdog Timer
When enabled, the I2C Watchdog Timer may be used to detect
when the I2C bus is free or hung up following an invalid termination
of a transaction. If SDA is high and no signalling occurs for
approximately 1 second, the I2C bus is assumed to be free. If SDA
is low and no signaling occurs, the device will attempt to clear the
bus by driving 9 clocks on SCL
I2C_BUS_TIMER
_DISABLE
0
RW
0
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7.7.11 SCL High Time Register
The SCL High Time register field configures the high pulse width of the I2C SCL output when the Serializer is the
Controller on the local I2C bus. Units are 40 ns for the nominal oscillator clock frequency. The default value is set
to approximately 100 kHz with the internal oscillator clock running at nominal 25 MHz. Delay includes 4
additional oscillator clock periods. The internal oscillator has ±10% variation when REFCLK is not applied, which
must be taken into account when setting the SCL High and Low Time registers.
表7-27. SCL High Time (Address 0x0A)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
I2C Controller SCL high time
7:0
SCL_HIGH_TIME
RW
0x7A
Default set to approximately 100 kHz when REFCLK = 25 MHz.
Nominal High Time = 40 ns × (SCL HIGH TIME + 4)
7.7.12 SCL Low Time Register
The SCL Low Time register field configures the low pulse width of the SCL output when the serializer is the
controller on the local I2C bus. This value is also used as the SDA setup time by the I2C Target for providing
data prior to releasing SCL during accesses over the Bidirectional control channel. Units are 40 ns for the
nominal oscillator clock frequency. The default value is set to approximately 100 kHz with the internal oscillator
clock running at nominal 25 MHz. Delay includes 4 additional oscillator clock periods. The internal oscillator has
±10% variation when REFCLK is not applied, which must be taken into account when setting the SCL High and
Low Time registers.
表7-28. SCL Low Time (Address 0x0B)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
I2C SCL low time
7:0
SCL_LOW_TIME
RW
0x7A
Default set to approximately 100 kHz when REFCLK = 25 MHz.
Nominal low time = 40 ns × (SCL LOW TIME + 4)
7.7.13 RX_PORT_CTL Register
Receiver port control register assigns rules for lock and pass in the general status register and allows for
enabling and disabling the Rx port.
表7-29. RX_PORT_CTL (Address 0x0C)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:6
RESERVED
R
10
Reserved
Pass Output Select
This field controls the source of the PASS output.
00: Port 0 Receiver Pass
This field can only be written via a local I2C controller.
5:4
3:2
PASS_SEL
LOCK_SEL
RW
RW
00
0
Lock Output Select
This field controls the source of the LOCK output.
00: Port 0 Receiver Lock
This field can only be written via a local I2C controller.
1
0
RESERVED
PORT0_EN
RW
RW
1
1
Set to 0 at start-up. This is required for proper operation.
Port 0 Receiver Enable
0: Disable Port 0 Receiver
1: Enable Port 0 Receiver
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7.7.14 IO_CTL Register
表7-30. IO_CTL (Address 0x0D)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
3.3V I/O Select on I2C_SCL, I2C_SDA, and INTB pins.
0: 1.8V I/O Supply
7
SEL3P3V
RW
0
1: 3.3V I/O Supply
If IO_SUPPLY_MODE_OV is 0, a read of this register will return the
detected I/O voltage level.
Override I/O Supply Mode bit
0: Detected I/O voltage level will be used for both SEL3P3V and
IO_SUPPLY_MODE controls.
1: Register values written to the SEL3P3V and IO_SUPPLY_MODE
fields will be used.
IO_SUPPLY
_MODE_OV
6
RW
0
I/O Supply Mode
00: 1.8V
01: Reserved
5:4
3:0
IO_SUPPLY_MODE RW
0x0
0x9
10: Reserved
11: 3.3V
If IO_SUPPLY_MODE_OV is 0, a read of this register will return the
detected I/O voltage level.
RESERVED
RW
Reserved
7.7.15 GPIO_PIN_STS Register
This register reads the current values on each of the 7 GPIO pins.
表7-31. GPIO_PIN_STS (Address 0x0E)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7
RESERVED
R
0
Reserved
GPIO Pin High/ Low Status.
Bit 6 reads GPIO6 and bit 0 reads GPIO0.
6:0
GPIO_STS
R
0x0
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7.7.16 GPIO_INPUT_CTL Register
表7-32. GPIO_INPUT_CTL (Address 0x0F)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7
RESERVED
R
0
Reserved
GPIO6 Input Enable. Must be set to zero if GPIO6 is configured as
an output by setting 0x16[0] = 1
0: Disabled
1: Enabled
6
5
4
3
2
1
0
GPIO6_INPUT_EN
GPIO5_INPUT_EN
GPIO4_INPUT_EN
GPIO3_INPUT_EN
GPIO2_INPUT_EN
GPIO1_INPUT_EN
GPIO0_INPUT_EN
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
GPIO5 Input Enable. Must be set to zero if GPIO5 is configured as
an output by setting 0x15[0] = 1
0: Disabled
1: Enabled
GPIO4 Input Enable. Must be set to zero if GPIO4 is configured as
an output by setting 0x14[0] = 1
0: Disabled
1: Enabled
GPIO3 Input Enable. Must be set to zero if GPIO3 is configured as
an output by setting 0x13[0] = 1
0: Disabled
1: Enabled
GPIO2 Input Enable. Must be set to zero if GPIO2 is configured as
an output by setting 0x12[0] = 1
0: Disabled
1: Enabled
GPIO1 Input Enable. Must be set to zero if GPIO1 is configured as
an output by setting 0x11[0] = 1
0: Disabled
1: Enabled
GPIO0 Input Enable. Must be set to zero if GPIO0 is configured as
an output by setting 0x10[0] = 1
0: Disabled
1: Enabled
7.7.17 GPIO0_PIN_CTL Register
表7-33. GPIO0_PIN_CTL (Address 0x10)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
GPIO0 Output Select
Determines the output data for the selected source. See 节7.4.12.2.
7:5
GPIO0_OUT_SEL
RW
0x0
GPIO0 Output Source Select
Selects output source for GPIO0 data: See 表7-6.
4:2
1
GPIO0_OUT_SRC
GPIO0_OUT_VAL
RW
RW
0x0
0
GPIO0 Output Value
This register provides the output data value when the GPIO pin is
enabled to output the local register controlled value by setting
GPIO0_OUT_SRC[2:0] = 100 and GPIO0_OUT_SEL[2:0] = 000.
GPIO0 Output Enable. Must be set to zero when configured as an
input in GPIO Input Control register, 0x0F[0] = 1
0: Disabled
1: Enabled
0
GPIO0_OUT_EN
RW
0
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7.7.18 GPIO1_PIN_CTL Register
表7-34. GPIO1_PIN_CTL (Address 0x11)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
GPIO1 Output Select
7:5
GPIO1_OUT_SEL
RW
0x0
Determines the output data for the selected source. See 节
7.4.12.2.
GPIO1 Output Source Select
Selects output source for GPIO1 data: See 表7-6.
4:2
1
GPIO1_OUT_SRC
GPIO1_OUT_VAL
RW
RW
0x0
0
GPIO1 Output Value
This register provides the output data value when the GPIO pin is
enabled to output the local register controlled value by setting
GPIO1_OUT_SRC[2:0] = 100 and GPIO1_OUT_SEL[2:0] = 000
GPIO1 Output Enable. Must be set to zero when configured as an
input in GPIO Input Control register, 0x0F[1] = 1.
0: Disabled
1: Enabled
0
GPIO1_OUT_EN
RW
0
7.7.19 GPIO2_PIN_CTL Register
表7-35. GPIO2_PIN_CTL (Address 0x12)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
GPIO2 Output Select
Determines the output data for the selected source. See 节7.4.12.2.
7:5
GPIO2_OUT_SEL
RW
0x0
GPIO2 Output Source Select
Selects output source for GPIO2 data: See 表7-6.
4:2
1
GPIO2_OUT_SRC
GPIO2_OUT_VAL
RW
RW
0x0
0
GPIO2 Output Value
This register provides the output data value when the GPIO pin is
enabled to output the local register controlled value by setting
GPIO2_OUT_SRC[2:0] = 100 and GPIO2_OUT_SEL[2:0] = 00
GPIO2 Output Enable. Must be set to zero when configured as an
input in GPIO Input Control register, 0x0F[2] = 1.
0: Disabled
1: Enabled
0
GPIO2_OUT_EN
RW
0
7.7.20 GPIO3_PIN_CTL Register
表7-36. GPIO3_PIN_CTL (Address 0x13)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
GPIO3 Output Select
Determines the output data for the selected source. See 节7.4.12.2.
7:5
GPIO3_OUT_SEL
RW
0x0
GPIO3 Output Source Select
Selects output source for GPIO3 data. See 表7-6.
4:2
1
GPIO3_OUT_SRC
GPIO3_OUT_VAL
RW
RW
0x0
0
GPIO3 Output Value
This register provides the output data value when the GPIO pin is
enabled to output the local register controlled value by setting
GPIO3_OUT_SRC[2:0] = 100 and GPIO3_OUT_SEL[2:0] = 000
GPIO3 Output Enable. Must be set to zero when configured as an
input in GPIO Input Control register, 0x0F[3] = 1.
0: Disabled
1: Enabled
0
GPIO3_OUT_EN
RW
0
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7.7.21 GPIO4_PIN_CTL Register
表7-37. GPIO4_PIN_CTL (Address 0x14)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
GPIO4 Output Select
Determines the output data for the selected source. See 节7.4.12.2.
7:5
GPIO4_OUT_SEL
RW
0x0
GPIO4 Output Source Select
Selects output source for GPIO4 data. See 节7.4.12.2.
4:2
1
GPIO4_OUT_SRC
GPIO4_OUT_VAL
RW
RW
0x0
0
GPIO4 Output Value
This register provides the output data value when the GPIO pin is
enabled to output the local register controlled value by setting
GPIO4_OUT_SRC[2:0] = 100 and GPIO4_OUT_SEL[2:0] = 000
GPIO4 Output Enable. Must be set to zero when configured as an
input in GPIO Input Control register, 0x0F[4] = 1.
0: Disabled
1: Enabled
0
GPIO4_OUT_EN
RW
0
7.7.22 GPIO5_PIN_CTL Register
表7-38. GPIO5_PIN_CTL (Address 0x15)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
GPIO5 Output Select
Determines the output data for the selected source. See 节7.4.12.2.
7:5
GPIO5_OUT_SEL
RW
0x0
GPIO5 Output Source Select
Selects output source for GPIO5 data: See 表7-6.
4:2
1
GPIO5_OUT_SRC
GPIO5_OUT_VAL
RW
RW
0x0
0
GPIO5 Output Value
This register provides the output data value when the GPIO pin is
enabled to output the local register controlled value by setting
GPIO5_OUT_SRC[2:0] = 100 and GPIO5_OUT_SEL[2:0] = 00
GPIO5 Output Enable. Must be set to zero when configured as an
input in GPIO Input Control register, 0x0F[5] = 1.
0: Disabled
1: Enabled
0
GPIO5_OUT_EN
RW
0
7.7.23 GPIO6_PIN_CTL Register
表7-39. GPIO6_PIN_CTL (Address 0x16)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
GPIO6 Output Select
Determines the output data for the selected source. See 节7.4.12.2.
7:5
GPIO6_OUT_SEL
RW
0x0
GPIO6 Output Source Select
Selects output source for GPIO6 data: See 表7-6
4:2
1
GPIO6_OUT_SRC
GPIO6_OUT_VAL
RW
RW
0x0
0
GPIO6 Output Value
This register provides the output data value when the GPIO pin is
enabled to output the local register controlled value by setting
GPIO6_OUT_SRC[2:0] = 100 and GPIO6_OUT_SEL[2:0] = 00
GPIO6 Output Enable. Must be set to zero when configured as an
input in GPIO Input Control register, 0x0F[6] = 1.
0: Disabled
1: Enabled
0
GPIO6_OUT_EN
RW
0
7.7.24 RESERVED Register
表7-40. RESERVED (Address 0x17)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
R
0x0
Reserved.
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7.7.25 FS_CTL Register
表7-41. FS_CTL (Address 0x18)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
FrameSync Mode
0000: Internal Generated FrameSync, use back channel frame clock
from port 0
0001: Reserved
0010: Reserved.
0011: Reserved
01xx: Internal Generated FrameSync, use 25MHz clock
1000: External FrameSync from GPIO0
1001: External FrameSync from GPIO1
1010: External FrameSync from GPIO2
1011: External FrameSync from GPIO3
1100: External FrameSync from GPIO4
1101: External FrameSync from GPIO5
1110: External FrameSync from GPIO6
1111: Reserved
7:4
FS_MODE
RW
0
Generate Single FrameSync pulse
When this bit is set, a single FrameSync pulse will be generated.
The system should wait for the full duration of the desired pulse
before generating another pulse. When using this feature, the
FS_GEN_ENABLE bit should remain set to 0. This bit is self-
clearing and will always return 0.
3
2
FS_SINGLE
RW, SC
RW
0
0
Initial State. This register controls the initial state of the FrameSync
signal.
0: FrameSync initial state is 0
1: FrameSync initial state is 1
FS_INIT_STATE
FrameSync Generation Mode
This control selects between Hi/Lo and 50/50 modes. In Hi/Lo mode,
the FrameSync generator uses the FS_HIGH_TIME [15:0] and
FS_LOW_TIME [15:0] register values to separately control the High
and Low periods for the generated FrameSync signal. In 50/50
mode, the FrameSync generator uses the values in the
FS_HIGH_TIME_0, FS_LOW_TIME_1 and FS_LOW_TIME_0
registers as a 24-bit value for both the High and Low periods of the
generated FrameSync signal.
1
0
FS_GEN_MODE
RW
RW
0
0
0: Hi/Lo
1: 50/50
FrameSync Generation Enable
0: Disabled
FS_GEN_ENABLE
1: Enabled
7.7.26 FS_HIGH_TIME_1 Register
表7-42. FS_HIGH_TIME_1 (Address 0x19)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
FrameSync High Time bits 15:8
The value programmed to the FS_HIGH_TIME register should be
reduced by 1 from the desired delay. For example, a value of 0 in
the FRAMESYNC_HIGH_TIME field will result in a 1 cycle high
pulse on the FrameSync signal.
FRAMESYNC_HIGH_
TIME_1
7:0
RW
0
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7.7.27 FS_HIGH_TIME_0 Register
表7-43. FS_HIGH_TIME_0 (Address 0x1A)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
FrameSync High Time bits 7:0
The value programmed to the FS_HIGH_TIME register should be
reduced by 1 from the desired delay. For example, a value of 0 in
the FRAMESYNC_HIGH_TIME field will result in a 1 cycle high
pulse on the FrameSync signal.
FRAMESYNC
_HIGH_TIME_0
7:0
RW
0
7.7.28 FS_LOW_TIME_1 Register
表7-44. FS_LOW_TIME_1 (Address 0x1B)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
FrameSync Low Time bits 15:8
The value programmed to the FS_LO_TIME register should be
reduced by 1 from the desired delay. For example, a value of 0 in
the FRAMESYNC_LO_TIME field will result in a 1 cycle high pulse
on the FrameSync signal.
FRAMESYNC
_LOW_TIME_1
7:0
RW
0
7.7.29 FS_LOW_TIME_0 Register
表7-45. FS_LOW_TIME_0 (Address 0x1C)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
FrameSync Low Time bits 7:0
The value programmed to the FS_LO_TIME register should be
reduced by 1 from the desired delay. For example, a value of 0 in
the FRAMESYNC_LO_TIME field will result in a 1 cycle high pulse
on the FrameSync signal.
FRAMESYNC_LOW_
TIME_0
7:0
RW
0
7.7.30 MAX_FRM_HI Register
表7-46. MAX_FRM_HI (Address 0x1D)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
MAX_FRAME_HI
RW
0x00
CSI-2 Maximum Frame Count bits 15:8
7.7.31 MAX_FRM_LO Register
表7-47. MAX_FRM_LO (Address 0x1E)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
MAX_FRAME_LO
RW
0x04
CSI-2 Maximum Frame Count bits 7:0
7.7.32 CSI_PLL_CTL Register
表7-48. CSI_PLL_CTL (Address 0x1F)
BIT
7:4
3:2
FIELD
TYPE
DEFAULT
DESCRIPTION
RESERVED
RESERVED
R
0
0
Reserved
RW
Reserved
CSI Transmitter Speed select:
Controls the CSI Transmitter frequency.
00 : 1.6 Gbps serial rate
01 : Reserved
1:0
CSI_TX_SPEED
RW
10
10 : 800 Mbps serial rate
11 : 400 Mbps serial rate
7.7.33 FWD_CTL1 Register
Forwarding control enables or disables video stream from the Rx Port.
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表7-49. FWD_CTL1 (Address 0x20)
BIT
7:6
5
FIELD
TYPE
RW
DEFAULT
DESCRIPTION
RESERVED
RESERVED
0x0
1
Reserved.
RW
Reserved
Disable forwarding of RX Port 0
0: Forwarding enabled for RX Port 0
1: Forwarding disabled for RX Port 0
4
FWD_PORT0_DIS
RESERVED
RW
R
1
3:0
0x0
Reserved.
7.7.34 FWD_CTL2 Register
表7-50. FWD_CTL2 (Address 0x21)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
CSI Replicate Mode. When set to a 1, the CSI output from port 0 will
also be generated on CSI port 1. In this mode, each CSI port may be
one or two lanes only. The same output data will be presented on both
ports.
7
CSI_REPLICATE
RW
0
FWD_SYNC
_AS_AVAIL
6
RW
0
Set to 1 after start-up
5:4
3:2
1
RESERVED
RESERVED
RESERVED
R
0
Reserved.
Reserved
Reserved.
RW
RW
00
0
Enable round robin forwarding for CSI TX output port. When this mode
is enabled, no attempt is made to synchronize the video traffic. When
multiple sources have data available to forward, the data will tend to be
forwarded in a round-robin fashion.
0
CSI0_RR_FWD
RW
1
0: Round robin forwarding disabled
1: Round robin forwarding enabled Only one of CSI0_RR_FWD and
CSI0_SYNC_FWD must be set at a time.
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7.7.35 FWD_STS Register
表7-51. FWD_STS (Address 0x22)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
R
0
Reserved
7.7.36 INTERRUPT_CTL Register
表7-52. INTERRUPT_CTL (Address 0x23)
BIT
FIELD
TYPE
DEFAULT DESCRIPTION
Global Interrupt Enable:
Enables interrupt on the interrupt signal to the controller.
7
INT_EN
RW
R
0
0
0
6:5
4
RESERVED
IE_CSI_TX0
Reserved
CSI Transmit Port Interrupt:
Enable interrupt from CSI Transmitter Port.
RW
3:2
1
RESERVED
RESERVED
R
0
0
Reserved
Reserved
RW
RX Port 0 Interrupt:
Enable interrupt from Receiver Port 0.
0
IE_RX0
RW
0
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7.7.37 INTERRUPT_STS Register
表7-53. INTERRUPT_STS (Address 0x24)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Global Interrupt:
Set if any enabled interrupt is indicated in the individual status bits in this
register. The setting of this bit is not dependent on the INT_EN bit in the
INTERRUPT_CTL register but does depend on the IE_xxx bits. For
example, if IE_RX0 and IS_RX0 are both asserted, the
INTERRUPT_STS bit is set to 1.
7
INTERRUPT_STS
R
0
6:5
4
RESERVED
IS_CSI_TX0
R
R
0
0
Reserved
CSI Transmit Port Interrupt:
An interrupt has occurred for CSI Transmitter Port 0. This interrupt is
cleared upon reading the CSI_TX_ISR register for CSI Transmit Port.
3:2
1
RESERVED
RESERVED
R
R
0
0
Reserved
Reserved
RX Port 0 Interrupt:
An interrupt has occurred for Receive Port 0. This interrupt is cleared by
reading the associated status register(s) for the event(s) that caused the
interrupt. The status registers are RX_PORT_STS1, RX_PORT_STS2,
and CSI_RX_STS.
0
IS_RX0
R
0
7.7.38 RESERVED Register
表7-54. RESERVED (Address 0x25 –0x32)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
R
0x00
Reserved
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7.7.39 CSI_CTL Register
表7-55. CSI_CTL (Address 0x33)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7
RESERVED
R
0
Reserved
Enable initial CSI Skew-Calibration sequence
When the initial skew-calibration sequence is enabled, the CSI
Transmitter will send the sequence at initialization, prior to sending any
HS data. This bit should be set when operating at 1.6 Gbps CSI speed
(as configured in the CSI_PLL_CTL register).
0: Disabled
6
CSI_CAL_EN
RW
0
1: Enabled
CSI lane count
00: 4 lanes
01: 3 lanes
5:4
3:2
CSI_LANE_COUNT RW
0x0
10: 2 lanes
11: 1 lane
If CSI_REPLICATE is set in the FWD_CTL2 register, the device must
be programmed for 1 or 2 lanes only.
Force LP00 state on data/clock lanes
00: Normal operation
01: LP00 state forced only on data lanes
10: Reserved
CSI_ULP
RW
0
11: LP00 state forced on data and clock lanes
Enable CSI continuous clock mode. CSI-2 Tx outputs will provide a
CSI_CONTS
_CLOCK
continuous clock output signal once first packet is received.
0: Disabled
1: Enabled
1
0
RW
RW
0
0
Enable CSI output
0: Disabled
CSI_ENABLE
1: Enabled
7.7.40 CSI_CTL2 Register
表7-56. CSI_CTL2 (Address 0x34)
BIT
7:4
3
FIELD
TYPE
R
DEFAULT
DESCRIPTION
RESERVED
RESERVED
RESERVED
RESERVED
0x4
0
RW
CSI Calibration Inverted Data pattern
During the CSI skew-calibration pattern, the CSI Transmitter will send a
sequence of 01010101 data (first bit 0). Setting this bit to a 1 will invert
the sequence to 10101010 data.
2
CSI_CAL_INV
RW
0
Enable single periodic CSI Skew-Calibration sequence
Setting this bit will send a single skew-calibration sequence from the
CSI Transmitter. The skew-calibration sequence is the 1010 bit
sequence required for periodic calibration. The calibration sequence is
sent at the next idle period on the CSI interface. This bit is self-clearing
and will reset to 0 after the calibration sequence is sent.
CSI_CAL
_SINGLE
1
RW/SC
0
Enable periodic CSI Skew-Calibration sequence
When the periodic skew-calibration sequence is enabled, the CSI
Transmitter will send the periodic skew-calibration sequence following
the sending of Frame End packets.
CSI_CAL
_PERIODIC
0
RW
0
0: Disabled
1: Enabled
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7.7.41 CSI_STS Register
表7-57. CSI_STS (Address 0x35)
BIT
7:2
1
FIELD
TYPE
DEFAULT
DESCRIPTION
RESERVED
RESERVED
R
R
0x0
0
Reserved
Reserved
TX Port Pass
The TX_PORT_PASS indicates the CSI port is actively delivering valid
video data. The status is cleared based on detection of an error
condition that interrupts transmission.
0
TX_PORT_PASS
R
0
7.7.42 CSI_TX_ICR Register
表7-58. CSI_TX_ICR (Address 0x36)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:5
RESERVED
R
0x0
Reserved
RX Port Interrupt Enable
4
3
2
IE_RX_PORT_INT
RW
RW
RW
0
0
0
Enable interrupt based on receiver port interrupt for the RX Port being
forwarded to the CSI Transmit Port.
IE_CSI_SYNC
_ERROR
CSI Sync Error interrupt Enable
Enable interrupt on CSI Synchronization enable.
CSI Synchronized interrupt Enable
Enable interrupts on CSI Transmit Port assertion of CSI Synchronized
Status.
IE_CSI_SYNC
IE_CSI_PASS
_ERROR
CSI RX Pass Error interrupt Enable
Enable interrupt on CSI Pass Error
1
0
RW
RW
0
0
CSI Pass interrupt Enable
Enable interrupt on CSI Transmit Port assertion of CSI Pass.
IE_CSI_PASS
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7.7.43 CSI_TX_ISR Register
表7-59. CSI_TX_ISR (Address 0x37)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:5
RESERVED
R
0x0
Reserved
RX Port Interrupt
A Receiver port interrupt has been generated for the RX Ports being
forwarded to the CSI Transmit Port. A read of the associated port receive
status registers will clear this interrupt. See the PORT_ISR_HI and
PORT_ISR_LO registers for details.
4
IS_RX_PORT_INT
R
0
CSI Sync Error interrupt
A synchronization error has been detected for multiple video stream
inputs to the CSI Transmitter.
IS_CSI_SYNC_ERR
OR
3
2
1
0
R/COR
R/COR
R/COR
R/COR
0
0
0
0
CSI Synchronized interrupt
CSI Transmit Port assertion of CSI Synchronized Status. Current status
for CSI Sync can be read from the TX_PORT_SYNC flag in the
CSI_STS register.
IS_CSI_SYNC
CSI RX Pass Error interrupt
A deassertion of CSI Pass has been detected on the RX Ports being
forwarded to the CSI Transmit Port
IS_CSI_PASS_ERR
OR
CSI Pass interrupt
CSI Transmit Port assertion of CSI Pass detected. Current status for the
CSI Pass indication can be read from the TX_PORT_PASS flag in the
CSI_STS register
IS_CSI_PASS
7.7.44 CSI_TEST_CTL Register
表7-60. CSI_TEST_CTL (Address 0x38)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
RW
0x00
Reserved
7.7.45 CSI_TEST_PATT_HI Register
表7-61. CSI_TEST_PATT_HI (Address 0x39)
BIT
FIELD
TYPE
DEFAULT DESCRIPTION
7:0
CSI_TEST_PATT
RW
0x00 Bits 15:8 of fixed pattern for characterization test
7.7.46 CSI_TEST_PATT_LO Register
表7-62. CSI_TEST_PATT_LO (Address 0x3A)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
CSI_TEST_PATT
RW
0x00
Bits 7:0 of fixed pattern for characterization test
7.7.47 RESERVED Register
表7-63. RESERVED (Address 0x3B)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
RW
0x01
Reserved
7.7.48 RESERVED Register
表7-64. RESERVED (Address 0x3C)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
RW
0x14
Reserved
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7.7.49 RESERVED Register
表7-65. RESERVED (Address 0x3D)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
RW
0x6F
Reserved
7.7.50 RESERVED Register
表7-66. RESERVED (Address 0x3E)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
RW
0x00
Reserved
7.7.51 RESERVED Register
表7-67. RESERVED (Address 0x3F)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
RW
0x40
Reserved
7.7.52 RESERVED Register
表7-68. RESERVED (Address 0x40)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
RW
0x00
Reserved
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7.7.53 SFILTER_CFG Register
The SFilter configuration register controls the minimum and maximum values allow for the clock to data sample
timing. It is recommended to program this register to 0xA9 during initialization for optimal startup time and
ensure consistent AEQ performance across different channel characteristics.
表7-69. SFILTER_CFG (Address 0x41)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
SFILTER maximum setting This field controls the maximum SFILTER
setting. Allowed values are 0-14 with 7 being the mid point. These
values are used for both AEQ adaption and dynamic SFILTER control.
The maximum setting must be greater than or equal to the minimum
setting.
7:4
SFILTER_MAX
RW
0xA
SFILTER minimum setting. This field controls the maximum SFILTER
setting. Allowed values are 0-14, where 7 is the mid point. These values
are used for both AEQ adaption and dynamic SFILTER control. The
minimum setting must be less than or equal to the SFILTER_MAX.
Recommend to set SFILTER_MIN = 0x9 for normal operation in typical
system use cases.
3:0
SFILTER_MIN
RW
0x7
7.7.54 AEQ_CTL1 Register
表7-70. AEQ_CTL1 (Address 0x42)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7
RESERVED
R
0
Reserved
AEQ Error Control
Setting any bits in AEQ_ERR_CTL will enable FPD3 error checking
during the Adaptive Equalization process. Errors are accumulated over
1/2 of the period of the timer set by the
ADAPTIVE_EQ_RELOCK_TIME filed in the AEQ_CTL2 register. If the
number of errors is greater than the programmed threshold
(AEQ_ERR_THOLD), the AEQ will attempt to increase the EQ setting.
The errors may also be checked as part of EQ setting validation if
AEQ_2STEP_EN is set. The following errors are checked based on this
three bit field:
6:4
AEQ_ERR_CTL
RW
0x7
[6] FPD-Link III clock errors
[5] Packet encoding errors
[4] Parity errors
3
2
RESERVED
RW
RW
0
0
Reserved
AEQ 2-step enable
This bit enables a two-step operation as part of the Adaptive EQ
algorithm. If disabled, the state machine will wait for a programmed
period of time, then check status to determine if setting is valid. If
enabled, the state machine will wait for 1/2 the programmed period,
then check for errors over an additional 1/2 the programmed period. If
errors occur during the 2nd step, the state machine will immediately
move to the next setting.
AEQ_2STEP_EN
0 : Wait for full programmed delay, then check instantaneous lock value
1 : Wait for 1/2 programmed time, then check for errors over 1/2
programmed time. The programmed time is controlled by the
ADAPTIVE_EQ_RELOCK_TIME field in the AEQ_CTL2 register
AEQ outer loop control
This bit controls whether the Equalizer or SFILTER adaption is the outer
loop when the AEQ adaption includes SFILTER adaption.
0 : AEQ is inner loop, SFILTER is outer loop
1 : AEQ is outer loop, SFILTER is inner loop
1
0
AEQ_OUTER_LOOP RW
0
1
Enable SFILTER Adaption with AEQ
Setting this bit allows SFILTER adaption as part of the Adaptive
Equalizer algorithm.
AEQ_SFILTER_EN
RW
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7.7.55 AEQ_ERR_THOLD Register
表7-71. AEQ_ERR_THOLD (Address 0x43)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
AEQ Error Threshold
AEQ_ERR
_THRESHOLD
This register controls the error threshold to determine when to re-adapt
the EQ settings. This register should not be programmed to a value of
0.
7:0
RW
0x1
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7.7.56 RESERVED Register
表7-72. RESERVED (Address 0x44 –0x49)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
R
0x00
Reserved
7.7.57 FPD3_CAP Register
Recommended to set bit four in the FPD-Link III capabilities register to one in order to flag errors detected from
enhanced CRC on encoded link control information. The FPD-Link III Encoder CRC must also be enabled by
setting the FPD3_ENC_CRC_DIS (register 0xBA[7]) to 0.
表7-73. FPD3_CAP (Address 0x4A)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:5
RESERVED
RW
0x0
Reserved
FPD3_ENC_CRC_C
AP
0: Disable CRC error flag from FPD-Link III encoder
1: Disable CRC error flag from FPD-Link III encoder (recommended)
4
RW
RW
0
3:0
RESERVED
0x0
Reserved
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7.7.58 FPD3_PORT_SEL Register
The FPD-Link III Port Select register configures which port is accessed in I2C commands to unique Rx Port
registers 0x4D - 0x7F and 0xD0 - 0xDF. A 2-bit RX_READ_PORT field provides for reading values from a single
port. The 4-bit RX_WRITE_PORT field provides individual enables for each port, allowing simultaneous writes
broadcast to both of the FPD-Link III Receive port register blocks in unison. The DS90UB638-Q1 maintains
separate page control, preventing conflict between sources.
表7-74. FPD3_PORT_SEL (Address 0x4C)
BIT
7
FIELD
TYPE
DEFAULT
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
R
0
0
0
0
0
0
6
R
5
R
4
RW
R
3:2
1
RW
Write Enable for RX port 0 registers
This bit enables writes to RX port 0 registers. This applies to all paged
FPD-Link III Receiver port registers.
0: Writes disabled
0
0
RX_WRITE_PORT_0 RW
1 for RX Port 0
1: Writes enabled
When accessed via Bi-directional Control Channel, the default value is
1 if accessed over RX port 0.
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7.7.59 RX_PORT_STS1 Register
RX port specific register dependent on the settings in register 0x4C.
表7-75. RX_PORT_STS1 (Address 0x4D)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7
RESERVED
R
0
Reserved
RX Port Number. This read-only field indicates the number of the
currently selected RX read port.
6
5
RX_PORT_NUM
R
0
0
Bi-directional Control Channel CRC Error Detected
This bit indicates a CRC error has been detected in the forward control
channel. If this bit is set, an error may have occurred in the control
channel operation. This bit is cleared on read.
BCC_CRC_ERROR
R/COR
Lock Status Changed
This bit is set if a change in receiver lock status has been detected
since the last read of this register. Current lock status is available in
the LOCK_STS bit of this register.
4
3
LOCK_STS_CHG
R/COR
R/COR
0
0
This bit is cleared on read.
Bi-directional Control Channel Sequence Error Detected
This bit indicates a sequence error has been detected in the forward
control channel. If this bit is set, an error may have occurred in the
control channel operation. This bit is cleared on read.
BCC_SEQ_ERROR
FPD-Link III parity errors detected
This flag is set when the number of parity errors detected is greater
than the threshold programmed in the PAR_ERR_THOLD registers.
1: Number of FPD-Link III parity errors detected is greater than the
threshold
2
PARITY_ERROR
R
0
0: Number of FPD-Link III parity errors is below the threshold
This bit is cleared when the RX_PAR_ERR_HI/LO registers are
cleared.
Receiver PASS indication.
This bit indicates the current status of the Receiver PASS indication.
The requirements for setting the Receiver PASS indication are
controlled by the PORT_PASS_CTL register.
1: Receive input has met PASS criteria
1
0
PORT_PASS
LOCK_STS
R
R
0
0
0: Receive input does not meet PASS criteria
FPD-Link III receiver is locked to incoming data
1: Receiver is locked to incoming data
0: Receiver is not locked
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7.7.60 RX_PORT_STS2 Register
表7-76. RX_PORT_STS2 (Address 0x4E)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Line Length Unstable
If set, this bit indicates the line length was detected as unstable during
a previous video frame. The line length is considered to be stable if all
the lines in the video frame have the same length. This flag will remain
set until read.
LINE_LEN
_UNSTABLE
7
R/COR
0
Line Length Changed
1: Change of line length detected
0: Change of line length not detected
This bit is cleared on read.
6
5
LINE_LEN_CHG
R/COR
R/COR
0
0
FPD-Link III Encoder error detected
If set, this flag indicates an error in the FPD-Link III encoding has been
detected by the FPD-Link III receiver.
FPD3_ENCODE
_ERROR
This bit is cleared on read.
Note, to detect FP3 Encoder errors, the LINK_ERROR_COUNT must
be enabled with a LINK_ERR_THRESH value greater than 1.
Otherwise, the loss of Receiver Lock will prevent detection of the
Encoder error.
Packet buffer error detected. If this bit is set, an overflow condition has
occurred on the packet buffer FIFO.
4
BUFFER_ERROR
R/COR
0
1: Packet Buffer error detected
0: No Packet Buffer errors detected
This bit is cleared on read.
3
2
1
CSI_ERROR
R
R
R
0
0
0
CSI Receive error detected. See the CSI_RX_STS register for details.
Frequency measurement stable
FREQ_STABLE
NO_FPD3_CLK
No FPD-Link III input clock detected
Line Count Changed
1: Change of line count detected
0: Change of line count not detected
This bit is cleared on read.
0
LINE_CNT_CHG
R/COR
0
7.7.61 RX_FREQ_HIGH Register
表7-77. RX_FREQ_HIGH (Address 0x4F)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Frequency Counter High Byte (MHz)
7:0
FREQ_CNT_HIGH
R
0x00
The Frequency counter reports the measured frequency for the FPD-
Link III Receiver. This portion of the field is the integer value in MHz.
7.7.62 RX_FREQ_LOW Register
表7-78. RX_FREQ_LOW (Address 0x50)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Frequency Counter Low Byte (1/256 MHz)
The Frequency counter reports the measured frequency for the FPD-
Link III Receiver. This portion of the field is the fractional value in
1/256 MHz.
7:0
FREQ_CNT_LOW
R
0x00
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7.7.63 SENSOR_STS_0 Register
Sensor Status Register 0 field provides additional status information when paired with a DS90UB63x-Q1 CSI-2
Serializer. This field is automatically loaded from the forward channel.
表7-79. SENSOR_STS_0 (Address 0x51)
BIT
7:6
5
FIELD
TYPE
DEFAULT
DESCRIPTION
RESERVED
CSI_ALARM
BCC_ALARM
R
R
R
00
0
Reserved
Alarm flag for CSI error from serializer
Alarm flag for back channel error from serializer
4
0
LINK_DETECT_ALA
RM
3
2
1
0
R
R
R
R
0
0
0
0
Alarm flag for link detect from serializer
Alarm flag for temp sensor from serializer
Alarm flag for voltage sensor 1 from serializer
Alarm flag for voltage sensor 0 from serializer
TEMP_SENSE_ALA
RM
VOLT1_SENSE_ALA
RM
VOLT0_SENSE_ALA
RM
7.7.64 SENSOR_STS_1 Register
Sensor Status Register 1 field provides additional status information when paired with a DS90UB63x-Q1 CSI-2
Serializer. This field is automatically loaded from the forward channel.
表7-80. SENSOR_STS_1 (Address 0x52)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7
RESERVED
R
0
Reserved
VOLT1_SENSE_LEV
EL
6:4
3
R
R
R
0x0
0
Voltage sensor sampled value from serializer
Reserved
RESERVED
VOLT0_SENSE_LEV
EL
2:0
0x0
Voltage sensor sampled value from serializer
7.7.65 SENSOR_STS_2 Register
Sensor Status Register 2 field provides additional status information when paired with a DS90UB63x-Q1 CSI-2
Serializer. This field is automatically loaded from the forward channel.
表7-81. SENSOR_STS_2 (Address 0x53)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:3
RESERVED
R
0
TEMP_SENSE_LEVE
L
2:0
R
0x0
Temperature sensor sampled value from serializer
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7.7.66 SENSOR_STS_3 Register
Sensor Status Register 3 field provides additional status information on the CSI-2 input when paired with a
DS90UB63x-Q1 CSI-2 Serializer. This field is automatically loaded from the forward channel.
表7-82. SENSOR_STS_3 (Address 0x54)
BIT
7:5
4
FIELD
TYPE
DEFAULT
DESCRIPTION
RESERVED
R
R
R
R
R
R
0
0
0
0
0
0
Reserved
CSI_ECC_2BIT_ERR
CSI_CHKSUM_ERR
CSI_SOT_ERR
CSI_SYNC_ERR
CSI_CNTRL_ERR
CSI -2 ECC error flag from serializer
CSI-2 checksum error from serializer
CSI-2 start of transmission error from serializer
CSI-2 synchronization error from serializer
CSI-2 control error from serializer
3
2
1
0
7.7.67 RX_PAR_ERR_HI Register
表7-83. RX_PAR_ERR_HI (Address 0x55)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Number of FPD-Link III parity errors
8 most significant bits. The parity error counter registers return the
number of data parity errors that have been detected on the FPD-Link
III Receiver data since the last detection of valid lock or last read of
the RX_PAR_ERR_LO register. For accurate reading of the parity
error count, disable the RX_PARITY_CHECKER_ENABLE bit in
register 0x02 prior to reading the parity error count registers. This
register is cleared upon reading the RX_PAR_ERR_LO register.
PAR_ERROR line
_ BYTE_1
7:0
R/COR
0
7.7.68 RX_PAR_ERR_LO Register
表7-84. RX_PAR_ERR_LO (Address 0x56)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Number of FPD-Link III parity errors
8 least significant bits. The parity error counter registers return the
number of data parity errors that have been detected on the FPD-Link
III Receiver data since the last detection of valid lock or last read of
the RX_PAR_ERR_LO register. For accurate reading of the parity
error count, disable the RX_PARITY_CHECKER_ENABLE bit in
register 0x02 prior to reading the parity error count registers. This
register is cleared on read.
PAR_ERROR
_BYTE_0
7:0
R/COR
0
7.7.69 BIST_ERR_COUNT Register
表7-85. BIST_ERR_COUNT (Address 0x57)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
BIST_ERROR
_COUNT
Bist Error Count
Returns BIST error count
7:0
R
0
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7.7.70 BCC_CONFIG Register
表7-86. BCC_CONFIG (Address 0x58)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
I2C Pass-Through All Transactions
0: Disabled
1: Enabled
I2C_PASS
_THROUGH_ALL
7
RW
0
I2C Pass-Through to Serializer if decode matches
0: Pass-Through Disabled
1: Pass-Through Enabled
I2C_PASS
_THROUGH
6
5
RW
RW
0
0
Automatically Acknowledge all I2C writes independent of the forward
channel lock state or status of the remote Acknowledge
1: Enable
0: Disable
AUTO_ACK_ALL
BC_ALWAYS_ON
Back channel enable
1: Back channel is always enabled independent of
I2C_PASS_THROUGH and I2C_PASS_THROUGH_ALL
0: Back channel enable requires setting of either
I2C_PASS_THROUGH and I2C_PASS_THROUGH_ALL
This bit may only be written through a local I2C controller.
4
3
RW
RW
1
1
BC_CRC
_GENERATOR
_ENABLE
Back Channel CRC Generator Enable
0: Disable
1: Enable
Back Channel Frequency Select. Default value set by strap condition
upon asserting PDB = HIGH.
000- 001: Reserved
010: 10 Mbps (select for non-synchronous back channel
compatibility)
011-111: Reserved
000: 2.5 Mbps (select for DS90UB633-Q1 compatibility)
001- 011: Reserved
010: 10 Mbps (select for non-synchronous back channel
compatibility)
2:0
BC_FREQ_SELECT RW
S
101: 25 Mbps
110: 50 Mbps (default for DS90UB635-Q1 CSI Synchronous back
channel compatibility)
111: Reserved Note that changing this setting will result in some
errors on the back channel for a short period of time. If set over the
control channel, the Deserializer should first be programmed to Auto-
Ack operation to avoid a control channel timeout due to lack of
response from the Serializer.
7.7.71 DATAPATH_CTL1 Register
表7-87. DATAPATH_CTL1 (Address 0x59)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
1: Disable loading of the DATAPATH_CTL registers from the forward
channel, keeping locally written values intact
0: Allow forward channel loading of DATAPATH_CTL registers
OVERRIDE_FC
_CONFIG
7
RW
0
0
6:2
RESERVED
RW
Reserved
Forward Channel GPIO Enable
Configures the number of enabled forward channel GPIOs
00: GPIOs disabled
01: One GPIO
10: Two GPIOs
1:0
FC_GPIO_EN
RW
0
11: Four GPIOs
This field is normally loaded from the remote serializer. It can be
overwritten if the OVERRIDE_FC_CONFIG bit in this register is 1.
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7.7.72 DATAPATH_CTL2 Register
表7-88. DATAPATH_CTL2 (Address 0x5A)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
RW
0
Reserved
7.7.73 SER_ID Register
表7-89. SER_ID (Address 0x5B)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Remote Serializer ID
7:1
SER_ID
RW
0x00
This field is normally loaded automatically from the remote
Serializer.
Freeze Serializer Device ID
0
FREEZE_DEVICE_ID RW
0
Prevent auto-loading of the Serializer Device ID from the Forward
Channel. The ID is frozen at the value written.
7.7.74 SER_ALIAS_ID Register
表7-90. SER_ALIAS_ID (Address 0x5C)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7-bit Remote Serializer Alias ID
Configures the decoder for detecting transactions designated for
an I2C Target device attached to the remote serializer. The
transaction is remapped to the address specified in the Target ID
register. A value of 0 in this field disables access to the remote I2C
Target.
7:1
SER_ALIAS_ID
RW
0
Automatically Acknowledge all I2C writes to the remote Serializer
independent of the forward channel lock state or status of the
0
SER_AUTO_ACK
RW
0
remote Serializer Acknowledge
1: Enable
0: Disable
7.7.75 TargetID[0] Register
表7-91. TargetID[0] (Address 0x5D)
BIT
7:1
0
FIELD
TYPE
RW
R
DEFAULT
DESCRIPTION
7-bit Remote Target Device ID 0
Configures the physical I2C address of the remote I2C Target
device attached to the remote Serializer. If an I2C transaction is
addressed to the Target Alias ID0, the transaction is remapped to
this address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
TARGET_ID0
RESERVED
0
0
Reserved.
7.7.76 TargetID[1] Register
表7-92. TargetID[1] (Address 0x5E)
BIT
7:1
0
FIELD
TYPE
RW
R
DEFAULT
DESCRIPTION
7-bit Remote Target Device ID 1
Configures the physical I2C address of the remote I2C Target
device attached to the remote Serializer. If an I2C transaction is
addressed to the Target Alias ID1, the transaction is remapped to
this address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
TARGET_ID1
RESERVED
0
0
Reserved.
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7.7.77 TargetID[2] Register
表7-93. TargetID[2] (Address 0x5F)
BIT
7:1
0
FIELD
TYPE
RW
R
DEFAULT
DESCRIPTION
7-bit Remote Target Device ID 2
Configures the physical I2C address of the remote I2C Target
device attached to the remote Serializer. If an I2C transaction is
addressed to the Target Alias ID2, the transaction is remapped
to this address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
TARGET_ID2
RESERVED
0
0
Reserved.
7.7.78 TargetID[3] Register
表7-94. TargetID[3] (Address 0x60)
BIT
7:1
0
FIELD
TYPE
RW
R
DEFAULT
DESCRIPTION
7-bit Remote Target Device ID 3
Configures the physical I2C address of the remote I2C Target
device attached to the remote Serializer. If an I2C transaction is
addressed to the Target Alias ID3, the transaction is remapped
to this address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
TARGET_ID3
RESERVED
0
0
Reserved.
7.7.79 TargetID[4] Register
表7-95. TargetID[4] (Address 0x61)
BIT
7:1
0
FIELD
TYPE
RW
R
DEFAULT
DESCRIPTION
7-bit Remote Target Device ID 4
Configures the physical I2C address of the remote I2C Target
device attached to the remote Serializer. If an I2C transaction is
addressed to the Target Alias ID4, the transaction is remapped
to this address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
TARGET_ID4
RESERVED
0
0
Reserved.
7.7.80 TargetID[5] Register
表7-96. TargetID[5] (Address 0x62)
BIT
7:1
0
FIELD
TYPE
RW
R
DEFAULT
DESCRIPTION
7-bit Remote Target Device ID 5
Configures the physical I2C address of the remote I2C Target
device attached to the remote Serializer. If an I2C transaction is
addressed to the Target Alias ID5, the transaction is remapped
to this address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
TARGET_ID5
RESERVED
0
0
Reserved.
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7.7.81 TargetID[6] Register
表7-97. TargetID[6] (Address 0x63)
BIT
7:1
0
FIELD
TYPE
RW
R
DEFAULT
DESCRIPTION
7-bit Remote Target Device ID 6
Configures the physical I2C address of the remote I2C Target
device attached to the remote Serializer. If an I2C transaction is
addressed to the Target Alias ID6, the transaction is remapped
to this address before passing the transaction across the
Bidirectional Control Channel to the Serializer.
TARGET_ID6
RESERVED
0
0
Reserved.
7.7.82 TargetID[7] Register
表7-98. TargetID[7] (Address 0x64)
BIT
7:1
0
FIELD
TYPE
RW
R
DEFAULT
DESCRIPTION
7-bit Remote Target Device ID 7
Configures the physical I2C address of the remote I2C Target
device attached to the remote Serializer. If an I2C transaction
is addressed to the Target Alias ID7, the transaction is
remapped to this address before passing the transaction
across the Bidirectional Control Channel to the Serializer.
TARGET_ID7
RESERVED
0
0
Reserved.
7.7.83 TargetAlias[0] Register
表7-99. TargetAlias[0] (Address 0x65)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7-bit Remote Target Device Alias ID 0
Configures the decoder for detecting transactions designated
for an I2C Target device attached to the remote Serializer. The
transaction is remapped to the address specified in the Target
ID0 register. A value of 0 in this field disables access to the
remote I2C Target.
7:1
TARGET_ALIAS_ID0 RW
0
Automatically Acknowledge all I2C writes to the remote Target
0 independent of the forward channel lock state or status of the
remote Serializer Acknowledge
1: Enable
TARGET_AUTO_AC
K_0
0
RW
0
0: Disable
7.7.84 TargetAlias[1] Register
表7-100. TargetAlias[1] (Address 0x66)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7-bit Remote Target Device Alias ID 1
Configures the decoder for detecting transactions designated
for an I2C Target device attached to the remote Serializer. The
transaction is remapped to the address specified in the Target
ID1 register. A value of 0 in this field disables access to the
remote I2C Target.
7:1
TARGET_ALIAS_ID1 RW
0
Automatically Acknowledge all I2C writes to the remote Target
1 independent of the forward channel lock state or status of
the remote Serializer Acknowledge
1: Enable
TARGET_AUTO_AC
K_1
0
RW
0
0: Disable
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7.7.85 TargetAlias[2] Register
表7-101. TargetAlias[2] (Address 0x67)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7-bit Remote Target Device Alias ID 2
Configures the decoder for detecting transactions designated
for an I2C Target device attached to the remote Serializer. The
transaction is remapped to the address specified in the Target
ID2 register. A value of 0 in this field disables access to the
remote I2C Target.
7:1
TARGET_ALIAS_ID2 RW
0
Automatically Acknowledge all I2C writes to the remote Target
2 independent of the forward channel lock state or status of
the remote Serializer Acknowledge
1: Enable
TARGET_AUTO_ACK
2
0
RW
0
0: Disable
7.7.86 TargetAlias[3] Register
表7-102. TargetAlias[3] (Address 0x68)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7-bit Remote Target Device Alias ID 3
Configures the decoder for detecting transactions designated
for an I2C Target device attached to the remote Serializer. The
transaction is remapped to the address specified in the Target
ID3 register. A value of 0 in this field disables access to the
remote I2C Target.
7:1
TARGET_ALIAS_ID3 RW
0
Automatically Acknowledge all I2C writes to the remote Target
3 independent of the forward channel lock state or status of
the remote Serializer Acknowledge
1: Enable
TARGET_AUTO_ACK
_3
0
RW
0
0: Disable
7.7.87 TargetAlias[4] Register
表7-103. TargetAlias[4] (Address 0x69)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7-bit Remote Target Device Alias ID 4
Configures the decoder for detecting transactions designated
for an I2C Target device attached to the remote Serializer. The
transaction is remapped to the address specified in the Target
ID4 register. A value of 0 in this field disables access to the
remote I2C Target.
7:1
TARGET_ALIAS_ID4 RW
0
Automatically Acknowledge all I2C writes to the remote Target
4 independent of the forward channel lock state or status of
the remote Serializer Acknowledge
1: Enable
TARGET_AUTO_AC
K_4
0
RW
0
0: Disable
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7.7.88 TargetAlias[5] Register
表7-104. TargetAlias[5] (Address 0x6A)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7-bit Remote Target Device Alias ID 5
Configures the decoder for detecting transactions designated
for an I2C Target device attached to the remote Serializer. The
transaction is remapped to the address specified in the Target
ID5 register. A value of 0 in this field disables access to the
remote I2C Target.
7:1
TARGET_ALIAS_ID5 RW
0
Automatically Acknowledge all I2C writes to the remote Target
5 independent of the forward channel lock state or status of the
remote Serializer Acknowledge
1: Enable
TARGET_AUTO_AC
K_5
0
RW
0
0: Disable
7.7.89 TargetAlias[6] Register
表7-105. TargetAlias[6] (Address 0x6B)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7-bit Remote Target Device Alias ID 6
Configures the decoder for detecting transactions designated
for an I2C Target device attached to the remote Serializer. The
transaction is remapped to the address specified in the Target
ID6 register. A value of 0 in this field disables access to the
remote I2C Target.
7:1
TARGET_ALIAS_ID6 RW
0
Automatically Acknowledge all I2C writes to the remote Target
6 independent of the forward channel lock state or status of the
remote Serializer Acknowledge
1: Enable
TARGET_AUTO_ACK
_6
0
RW
0
0: Disable
7.7.90 TargetAlias[7] Register
表7-106. TargetAlias[7] (Address 0x6C)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7-bit Remote Target Device Alias ID 7
Configures the decoder for detecting transactions designated
for an I2C Target device attached to the remote Serializer. The
transaction is remapped to the address specified in the Target
ID7 register. A value of 0 in this field disables access to the
remote I2C Target.
7:1
TARGET_ALIAS_ID7 RW
0
Automatically Acknowledge all I2C writes to the remote Target
7 independent of the forward channel lock state or status of
the remote Serializer Acknowledge
1: Enable
TARGET_AUTO_AC
K 7
0
RW
0
0: Disable
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7.7.91 PORT_CONFIG Register
表7-107. PORT_CONFIG (Address 0x6D)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
CSI Wait for FrameStart packet with count 1
7
CSI_WAIT_FS1
RW
0
The CSI Receiver will wait for a Frame Start packet with count
of 1 before accepting other packets
CSI Wait for FrameStart packet
6
5
4
CSI_WAIT_FS
RW
RW
RW
1
1
1
CSI-2 Receiver will wait for a Frame Start packet before
accepting other packets
Forward CSI packets with checksum errors
0: Do not forward packets with errors
1: Forward packets with errors
CSI_FWD_CKSUM
CSI_FWD_ECC
Forward CSI packets with ECC errors
0: Do not forward packets with errors
1: Forward packets with errors
In CSI FPD-Link III Input Mode, Forward CSI packets with
length errors.
0: CSI: Do not forward packets with errors.
1: CSI: Forward packets with errors.
CSI_FWD_LEN/
DISCARD_1ST
_LINE_ON_ERR
3
2
RW
RW
1
RESERVED
S
Reserved
FPD-Link III Input Mode
Default value set by strap condition of MODE pin upon
asserting PDB = HIGH at start-up.
1:0
FPD3_MODE
RW
S
00: CSI Mode (DS90UB635-Q1 compatible)
10: RAW12 HF Mode (56.25-100MHz) (DS90UB633A
compatible)
11: RAW10 Mode (75-100MHz) (DS90UB633A compatible)
7.7.92 BC_GPIO_CTL0 Register
表7-108. BC_GPIO_CTL0 (Address 0x6E)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Back channel GPIO1 Select:
Determines the data sent on GPIO1 for the port back channel.
0xxx : Pin GPIOx where x is BC_GPIO1_SEL[2:0]
0111 : Reserved
7:4
BC_GPIO1_SEL
RW
0x8
1000 : Constant value of 0
1001 : Constant value of 1
1010 : FrameSync signal
1011 - 1111 : Reserved
Back channel GPIO0 Select:
Determines the data sent on GPIO0 for the port back channel.
0xxx : Pin GPIOx where x is BC_GPIO0_SEL[2:0]
0111 : Reserved
3:0
BC_GPIO0_SEL
RW
0x8
1000 : Constant value of 0
1001 : Constant value of 1
1010 : FrameSync signal
1011 - 1111 : Reserved
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7.7.93 BC_GPIO_CTL1 Register
表7-109. BC_GPIO_CTL1 (Address 0x6F)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Back channel GPIO3 Select:
Determines the data sent on GPIO3 for the port back
channel.
0xxx : Pin GPIOx where x is BC_GPIO3_SEL[2:0]
0111 : Reserved
7:4
BC_GPIO3_SEL
RW
0x8
1000 : Constant value of 0
1001 : Constant value of 1
1010 : FrameSync signal
1011 - 1111 : Reserved
Back channel GPIO2 Select:
Determines the data sent on GPIO2 for the port back
channel.
0xxx : Pin GPIOx where x is BC_GPIO2_SEL[2:0]
0111 : Reserved
3:0
BC_GPIO2_SEL
RW
0x8
1000 : Constant value of 0
1001 : Constant value of 1
1010 : FrameSync signal
1011 - 1111 : Reserved
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7.7.94 CSI_VC_MAP Register
CSI virtual channel mapping only applies when FPD-Link III operating in CSI-2 input mode..
表7-110. CSI_VC_MAP (Address 0x72)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
CSI-2 Virtual Channel Mapping Register
This register provides a method for replacing the Virtual
Channel Identifier (VC-ID) of incoming CSI packets.
[7:6] : Map value for VC-ID of 3
7:0
CSI_VC_MAP
RW
0xE4
[5:4] : Map value for VC-ID of 2
[3:2] : Map value for VC-ID of 1
[1:0] : Map value for VC-ID of 0
7.7.95 LINE_COUNT_HI Register
表7-111. LINE_COUNT_HI (Address 0x73)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
High byte of Line Count
The Line Count reports the line count for the most recent
video frame. When interrupts are enabled for the Line Count
(via the IE_LINE_CNT_CHG register bit), the Line Count
value is frozen until read.
7:0
LINE_COUNT_HI
R
0x0
7.7.96 LINE_COUNT_LO Register
表7-112. LINE_COUNT_LO (Address 0x74)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Low byte of Line Count
The Line Count reports the line count for the most recent
video frame. When interrupts are enabled for the Line Count
(via the IE_LINE_CNT_CHG register bit), the Line Count
value is frozen until read. In addition, when reading the
LINE_COUNT registers, the LINE_COUNT_LO is latched
upon reading LINE_COUNT_HI to ensure consistency
between the two portions of the Line Count.
7:0
LINE_COUNT_LO
R
0x0
7.7.97 LINE_LEN_1 Register
表7-113. LINE_LEN_1 (Address 0x75)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
High byte of Line Length
The Line Length reports the line length recorded during the
most recent video frame. If line length is not stable during
the frame, this register will report the length of the last line
in the video frame. When interrupts are enabled for the Line
Length (via the IE_LINE_LEN_CHG register bit), the Line
Length value is frozen until read.
7:0
LINE_LEN_HI
R
0
7.7.98 LINE_LEN_0 Register
表7-114. LINE_LEN_0 (Address 0x76)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Low byte of Line Length
The Line Length reports the length of the most recent video
line. When interrupts are enabled for the Line Length (via
the IE_LINE_LEN_CHG register bit), the Line Length value
is frozen until read. In addition, when reading the LINE_LEN
registers, the LINE_LEN_LO is latched upon reading
LINE_LEN_HI to ensure consistency between the two
portions of the Line Length.
7:0
LINE_LEN_LO
R
0
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7.7.99 FREQ_DET_CTL Register
表7-115. FREQ_DET_CTL (Address 0x77)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Frequency Detect Hysteresis
The Frequency detect hysteresis setting allows ignoring minor
fluctuations in frequency. A new frequency measurement will
be captured only if the measured frequency differs from the
current measured frequency by more than the FREQ_HYST
setting. The FREQ_HYST setting is in MHz.
7:6
FREQ_HYST
RW
0x3
Frequency Stable Threshold
The Frequency detect circuit can be used to detect a stable
clock frequency. The Stability Threshold determines the
amount of time required for the clock frequency to stay within
5:4
3:0
FREQ_STABLE_THR RW
0x0
0x5
the FREQ_HYST range to be considered stable:
00 : 40 µs
01 : 80 µs
10 : 320 µs
11 : 1.28 ms
Frequency Low Threshold
Sets the low threshold for the Clock frequency detect circuit in
MHz. This value is used to determine if the clock frequency is
too low for proper operation.
FREQ_LO_THR
RW
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7.7.100 MAILBOX_1 Register
表7-116. MAILBOX_1 (Address 0x78)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Mailbox Register
This register is an unused read/write register that can be used
for any purpose such as passing messages between I2C
controllers on opposite ends of the link.
7:0
MAILBOX_0
RW
0x00
7.7.101 MAILBOX_2 Register
表7-117. MAILBOX_2 (Address 0x79)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Mailbox Register
This register is an unused read/write register that can be used
for any purpose such as passing messages between I2C
controllers on opposite ends of the link.
7:0
MAILBOX_1
RW
0x01
7.7.102 CSI_RX_STS Register
表7-118. CSI_RX_STS (Address 0x7A)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:4
RESERVED
R
0
Reserved
Packet Length Error detected for received CSI packet
If set, this bit indicates a packet length error was detected on
at least one CSI packet received from the sensor. Packet
length errors occur if the data length field in the packet header
does not match the actual data length for the packet.
1: One or more Packet Length errors have been detected
0: No Packet Length errors have been detected
This bit is cleared on read.
3
LENGTH_ERR
R/COR
0
Data Checksum Error detected for received CSI packet
If set, this bit indicates a data checksum error was detected on
at least one CSI packet received from the sensor. Data
checksum errors indicate an error was detected in the packet
data portion of the CSI packet.
2
CKSUM_ERR
R/COR
0
1: One or more Data Checksum errors have been detected
0: No Data Checksum errors have been detected
This bit is cleared on read.
2-bit ECC Error detected for received CSI packet
If set, this bit indicates a multi-bit ECC error was detected on
at least one CSI packet received from the sensor. Multi-bit
errors are not corrected by the device.
1: One or more multi-bit ECC errors have been detected
0: No multi-bit ECC errors have been detected
This bit is cleared on read.
1
0
ECC2_ERR
ECC1_ERR
R/COR
R/COR
0
0
1-bit ECC Error detected for received CSI packet
If set, this bit indicates a single-bit ECC error was detected on
at least one CSI packet received from the sensor. Single-bit
errors are corrected by the device.
1: One or more 1-bit ECC errors have been detected
0: No 1-bit ECC errors have been detected
This bit is cleared on read.
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7.7.103 CSI_ERR_COUNTER Register
表7-119. CSI_ERR_COUNTER (Address 0x7B)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
CSI Error Counter Register
7:0
CSI_ERR_CNT
R/COR
0x00
This register counts the number of CSI packets received with
errors since the last read of the counter.
7.7.104 PORT_CONFIG2 Register
表7-120. PORT_CONFIG2 (Address 0x7C)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:6
RESERVED
RW
0x0
RESERVED
Discard frames on Parity Error
0 : Forward packets with parity errors
1 : Truncate Frames if a parity error is detected
DISCARD_ON
_PAR_ERR
5
4
RW
RW
1
0
Discard frames on Line Size
0 : Allow changes in Line Size within packets
1 : Truncate Frames if a change in line size is detected
DISCARD_ON
_LINE_SIZE
Discard frames on change in Frame Size
When enabled, a change in the number of lines in a frame will
result in truncation of the packet. The device will resume
forwarding video frames based on the PASS_THRESHOLD
setting in the PORT_PASS_CTL register.
DISCARD_ON
_FRAME_SIZE
3
RW
0
0 : Allow changes in Frame Size
1 : Truncate Frames if a change in frame size is detected
2
1
0
RESERVED
RESERVED
RESERVED
RW
RW
RW
0
0
0
Reserved
Reserved
Reserved
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7.7.105 PORT_PASS_CTL Register
表7-121. PORT_PASS_CTL (Address 0x7D)
BIT
7
FIELD
TYPE
DEFAULT
DESCRIPTION
Pass Discard Enable
Discard packets if PASS is not indicated.
0 : Ignore PASS for forwarding packets
1 : Discard packets when PASS is not true
PASS_DISCARD_EN RW
0
0
6
RESERVED
RW
Reserved
Pass Line Count Control
This register controls whether the device will include line
count in qualification of the Pass indication:
0 : Don't check line count
5
4
3
PASS_LINE_CNT
RW
0
0
0
1 : Check line count
When checking line count, Pass is deasserted upon detection
of a change in the number of video lines per frame. Pass will
not be reasserted until the PASS_THRESHOLD setting is
met.
Pass Line Size Control
This register controls whether the device will include line size
in qualification of the Pass indication:
0 : Don't check line size
PASS_LINE_SIZE
RW
1 : Check line size
When checking line size, Pass is deasserted upon detection
of a change in video line size. Pass will not be reasserted until
the PASS_THRESHOLD setting is met.
Parity Error Mode
If this bit is set to 0, the port Pass indication is deasserted for
every parity error detected on the FPD-Link III Receive
interface. If this bit is set to a 1, the port Pass indication is
cleared on a parity error and remain clear until the
PASS_THRESHOLD is met. When PASS_PARITY_ERR is
set to 1, TI also recommends setting PASS_THRESHOLD to
2 or higher to ensure at least one good frame occurs following
a parity error
PASS_PARITY_ERR RW
RX Port Pass Watchdog disable
When enabled, if the FPD Receiver does not detect a valid
frame end condition within two video frame periods, the Pass
indication is deasserted. The watchdog timer will not have any
effect if the PASS_THRESHOLD is set to 0.
0 : Enable watchdog timer for RX Pass
2
PASS_WDOG_DIS
RW
0
1 : Disable watchdog timer for RX Pass
Pass Threshold Register
This register controls the number of valid frames before
asserting the port Pass indication. If set to 0, PASS is
asserted after Receiver Lock detect. If non-zero, PASS is
asserted following reception of the programmed number of
valid frames.
1:0
PASS_THRESHOLD RW
0x0
7.7.106 SEN_INT_RISE_CTL Register
表7-122. SEN_INT_RISE_CTL (Address 0x7E)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Sensor Interrupt Rise Mask
This register provides the interrupt mask for detecting rising
edge transitions on the bits in SENSOR_STS_0. If a mask bit
is set in this register, a rising edge transition on the
corresponding SENSOR_STS_0 bit will generate an interrupt
that will be latched in the SEN_INT_RISE_STS register.
SEN_INT
_RISE_MASK
7:0
RW
0x0
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7.7.107 SEN_INT_FALL_CTL Register
表7-123. SEN_INT_FALL_CTL (Address 0x7F)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Sensor Interrupt Fall Mask
This register provides the interrupt mask for detecting falling
edge transitions on the bits in SENSOR_STS_0. If a mask bit
is set in this register, a falling edge transition on the
SEN_INT
_FALL_MASK
7:0
RW
0x0
corresponding SENSOR_STS_0 bit will generate an interrupt
that will be latched in the SEN_INT_FALL_STS register.
7.7.108 RESERVED Register
表7-124. RESERVED (Address 0xA0 –0xA4)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
RW
0x00
Reserved
7.7.109 REFCLK_FREQ Register
表7-125. REFCLK_FREQ (Address 0xA5)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
REFCLK frequency measurement in MHz. REFCLK_FREQ
measurement is not synchronized. Value in this register
should read twice and only considered valid if
7:0
REFCLK_FREQ
R
0x00
REFCLK_FREQ is unchanged between reads.
7.7.110 RESERVED Register
表7-126. RESERVED (Address 0xA7 –0xAF)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
R
0x00
Reserved
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7.7.111 IND_ACC_CTL Register
表7-127. IND_ACC_CTL (Address 0xB0)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:6
RESERVED
R
0x0
Reserved
Indirect Access Register Select:
Selects target for register access
0000 : CSI-2 Pattern Generator & Timing Registers
0001 : FPD-Link III RX Port 0 Reserved Registers
00011–0100: Reserved
0101 : FPD-Link III RX Shared Reserved Registers
0110 : Simultaneous write to FPD-Link III RX Reserved
Registers
5:2
IA_SEL
RW
0x0
0111 : CSI-2 Reserved Registers
1000 : Reserved Registers
1001 : Unique DIE ID Registers
1010–1111 : Reserved
Indirect Access Auto Increment:
Enables auto-increment mode. Upon completion of a read or
write, the register address will automatically be incremented
by 1
1
0
IA_AUTO_INC
IA_READ
RW
RW
0
0
Indirect Access Read:
Setting this allows generation of a read strobe to the selected
register block upon setting of the IND_ACC_ADDR register.
In auto-increment mode, read strobes will also be asserted
following a read of the IND_ACC_DATA register. This function
is only required for blocks that need to pre-fetch register data.
7.7.112 IND_ACC_ADDR Register
表7-128. IND_ACC_ADDR (Address 0xB1)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Indirect Access Register Offset:
This register contains the 8-bit register offset for the indirect
access.
7:0
IA_ADDR
RW
0x0
7.7.113 IND_ACC_DATA Register
表7-129. IND_ACC_DATA (Address 0xB2)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Indirect Access Data:
Writing this register will cause an indirect write of the
IND_ACC_DATA value to the selected analog block register.
Reading this register will return the value of the selected block
register
7:0
IA_DATA
RW
0x0
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7.7.114 BIST Control Register
表7-130. BIST Control (Address 0xB3)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
BIST Output Mode
00 : Outputs disabled during BIST
01 : Reserved
7:6
BIST_OUT_MODE
RW
0x0
10 : Outputs enabled during BIST
11 : Reserved
5:4
3
RESERVED
RW
RW
0x0
1
Reserved
Bist Configured through Pin.
1: Bist configured through pin.
BIST_PIN_CONFIG
0: Bist configured through bits 2:0 in this register
BIST Clock Source
This register field selects the BIST Clock Source at the
Serializer. These register bits are automatically written to the
CLOCK SOURCE bits (register offset 0x14) in the Serializer
after BIST is enabled. See the appropriate Serializer register
descriptions for details.
BIST_CLOCK
_SOURCE
2:1
0
RW
RW
00
0
BIST Control
1: Enabled
0: Disabled
BIST_EN
7.7.115 RESERVED Register
表7-131. RESERVED (Address 0xB4)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
RW
0x25
Reserved
7.7.116 RESERVED Register
表7-132. RESERVED (Address 0xB5)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
RW
0x00
Reserved
7.7.117 RESERVED Register
表7-133. RESERVED (Address 0xB6)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
RW
0x18
Reserved
7.7.118 RESERVED Register
表7-134. RESERVED (Address 0xB7)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
RW
0x00
Reserved
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7.7.119 MODE_IDX_STS Register
表7-135. MODE_IDX_STS (Address 0xB8)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
IDX Done
7
IDX_DONE
R
1
If set, indicates the IDX decode has completed and latched
into the IDX status bits.
IDX Decode
3-bit decode from IDX pin
6:4
3
IDX
R
R
R
S
1
MODE Done
MODE_DONE
MODE
If set, indicates the MODE decode has completed and
latched into the MODE status bits.
MODE Decode
3-bit decode from MODE pin
2:0
S
7.7.120 LINK_ERROR_COUNT Register
表7-136. LINK_ERROR_COUNT (Address 0xB9)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:6
RESERVED
R
0x0
Reserved
During SFILTER adaption, setting this bit will cause the
Lock detect circuit to ignore errors during the SFILTER wait
period after the SFILTER control is updated.
1: Errors during SFILTER Wait period will be ignored
0: Errors during SFILTER Wait period will not be ignored
and may cause loss of Lock
5
4
LINK_SFIL_WAIT
RW
RW
1
1
Enable serial link data integrity error count
1: Enable error count
0: DISABLE
LINK_ERR
_COUNT_EN
Link error count threshold.
The Link Error Counter monitors the forward channel link
and determines when link will be dropped. The link error
counter is pixel clock based. FPD Link parity, clock, and
control are monitored for link errors. If the error counter is
enabled, the deserializer will lose lock once the error
counter reaches the LINK_ERR_THRESH value. If the link
error counter is disabled, the deserilizer will lose lock after
one error. The control bits in DIGITAL_DEBUG_2 register
can be used to disable error conditions individually.
LINK_ERR
_THRESH
3:0
RW
0x3
7.7.121 FPD3_ENC_CTL Register
Recommended to set bit seven in the FPD-Link III encoder control register to 0 in order to prevent any updates
of link information values from encoded packets that do not pass CRC check. The FPD-Link III Encoder CRC
flag must also be in place by setting FPD3_ENC_CRC_DIS (register 0x4A[4]) to 1.
表7-137. FPD3_ENC_CTL (Address 0xBA)
BIT
7
FIELD
TYPE
DEFAULT
DESCRIPTION
0: Enable FPD-Link III encoder CRC (recommended)
1: Disable FPD-Link III encoder CRC
RESERVED
RESERVED
RW
1
6:0
RW
0x03
Reserved
7.7.122 RESERVED Register
表7-138. RESERVED (Address 0xBD)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
RW
0x00
Reserved
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7.7.123 GPIO_PD_CTL Register
表7-139. GPIO_PD_CTL (Address 0xBE)
BIT
7
FIELD
TYPE
DEFAULT
DESCRIPTION
RESERVED
R
0
0
0
0
0
0
0
0
Reserved
6
GPIO6_PD_DIS
GPIO5_PD_DIS
GPIO4_PD_DIS
GPIO3_PD_DIS
GPIO2_PD_DIS
GPIO1_PD_DIS
GPIO0_PD_DIS
RW
RW
RW
RW
RW
RW
RW
GPIOX Pulldown Resistor Disable:
5
The GPIO pins by default include a 35-kΩtypical
pulldown resistor that is automatically enabled when the
GPIO is not in an output mode. When this bit is set, the
corresponding pulldown resistor will also be disabled
when the GPIO pin is in an input only mode.
1 : Disable GPIO pulldown resistor
4
3
2
1
0 : Enable GPIO pulldown resistor
0
7.7.124 PORT_DEBUG Register
表7-140. PORT_DEBUG (Address 0xD0)
BIT
7
FIELD
TYPE
DEFAULT
DESCRIPTION
RESERVED
RESERVED
RW
0
0
Reserved
6
RW
Reserved
Serializer BIST active
This register indicates the Serializer is in BIST mode.
When in BIST mode this flag can be checked to ensure
BIST is activated in the serializer during the test. If the
Deserializer is not in BIST mode, this could indicate an
error condition.
5
SER_BIST_ACT
RESERVED
R
0
4:2
1
RW
RW
0x0
0
Reserved
FORCE
_BC_ERRORS
Setting this bit introduces continuous single bit errors
into Back Channel Frames
FORCE
_1_BC_ERROR
Setting this bit introduces a single bit error into one Back
Channel Frame
0
RW
0
7.7.125 AEQ_CTL2 Register
表7-141. AEQ_CTL2 (Address 0xD2)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Time to wait for lock before incrementing the EQ to next
setting
000 : 164 µs
001 : 328 µs
010 : 655 µs
011 : 1.31 ms
100 : 2.62 ms
101 : 5.24 ms
110 : 10.5 ms
111 : 21.0 ms
ADAPTIVE_EQ
_RELOCK_TIME
7:5
RW
0x4
AEQ First Lock Mode.
This register bit controls the Adaptive Equalizer algorithm
operation at initial Receiver Lock.
0 : Initial AEQ lock may occur at any value
1 : Initial Receiver lock will restart AEQ at 0, providing a
more deterministic initial AEQ value
AEQ_1ST_LOCK
_MODE
4
3
RW
1
0
Set high to restart AEQ adaptation from initial value. This
bit is self clearing. Adaption is restarted.
AEQ_RESTART
RW/SC
AEQ adaptation starts from a pre-set floor value rather
than from zero - good in long cable situations
2
SET_AEQ_FLOOR
RESERVED
RW
R
1
1:0
0x0
Reserved
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7.7.126 AEQ_STATUS Register
表7-142. AEQ_STATUS (Address 0xD3)
BIT
7:6
5:0
FIELD
TYPE
DEFAULT
DESCRIPTION
RESERVED
EQ_STATUS
R
R
0x0
Reserved
0x00
Adaptive EQ Status
7.7.127 ADAPTIVE EQ BYPASS Register
表7-143. ADAPTIVE EQ BYPASS (Address 0xD4)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
EQ_STAGE_1
_SELECT_VALUE
7:5
RW
0x3
EQ select value [5:3] - Used if adaptive EQ is bypassed.
Adaptive Equalizer lock mode
When set to a 1, Receiver Lock status requires the
Adaptive Equalizer to complete adaption.
When set to a 0, Receiver Lock is based only on the Lock
circuit itself. AEQ may not have stabilized.
4
AEQ_LOCK_MODE RW
0
EQ_STAGE_2
RW
3:1
0
0x0
0
EQ select value [2:0] - Used if adaptive EQ is bypassed.
_SELECT_VALUE
ADAPTIVE_EQ
RW
1: Disable adaptive EQ
0: Enable adaptive EQ
_BYPASS
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7.7.128 AEQ_MIN_MAX Register
表7-144. AEQ_MIN_MAX (Address 0xD5)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Adaptive Equalizer Maximum value
This register sets the maximum value for the Adaptive EQ
algorithm. Must be higher than
7:4
AEQ_MAX
RW
0xF
ADAPTIVE_EQ_FLOOR_VALUE when
SET_AEQ_FLOOR is enabled.
When AEQ floor is enabled by register 0xD2[2] the
starting EQ gain setting for AEQ adaption is given by this
register.
ADAPTIVE_EQ
_FLOOR_VALUE
3:0
RW
0x2
7.7.129 RESERVED Register
表7-145. RESERVED (Address 0xD6)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
RW
0x00
Reserved
7.7.130 RESERVED Register
表7-146. RESERVED (Address 0xD7)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
RW
0x00
Reserved
7.7.131 PORT_ICR_HI Register
表7-147. PORT_ICR_HI (Address 0xD8)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:3
RESERVED
R
0x0
Reserved
Interrupt on FPD-Link III Receiver Encoding Error
When enabled, an interrupt is generated on detection of
an encoding error on the FPD-Link III interface for the
receive port as reported in the FPD3_ENC_ERROR bit in
the RX_PORT_STS2 register
2
1
IE_FPD3_ENC_ERR RW
IE_BCC_SEQ_ERR RW
0
0
Interrupt on BCC SEQ Sequence Error.
When enabled, an interrupt is generated if a Sequence
Error is detected for the Bi-directional Control Channel
forward channel receiver as reported in the
BCC_SEQ_ERROR bit in the RX_PORT_STS1 register.
Interrupt on BCC CRC error detect
When enabled, an interrupt is generated if a CRC error is
detected on a Bi-directional Control Channel frame
received over the FPD-Link III forward channel as
reported in the BCC_CRC_ERROR bit in the
RX_PORT_STS1 register.
0
IE_BCC_CRC_ERR RW
0
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7.7.132 PORT_ICR_LO Register
表7-148. PORT_ICR_LO (Address 0xD9)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7
RESERVED
RW
0
Reserved
Interrupt on Video Line length
When enabled, an interrupt is generated if the length of
the video line changes. Status is reported in the
LINE_LEN_CHG bit in the RX_PORT_STS2 register.
6
5
4
IE_LINE_LEN_CHG RW
IE_LINE_CNT_CHG RW
0
0
0
Interrupt on Video Line count
When enabled, an interrupt is generated if the number of
video lines per frame changes. Status is reported in the
LINE_CNT_CHG bit in the RX_PORT_STS2 register.
Interrupt on Receiver Buffer Error
When enabled, an interrupt is generated if the Receive
Buffer overflow is detected as reported in the
BUFFER_ERROR bit in the RX_PORT_STS2 register.
IE_BUFFER_ERR
IE_CSI_RX_ERR
RW
RW
Interrupt on CSI Receiver Error.
When enabled, an interrupt will be generated on
detection of an error by the CSI Receiver. CSI Receiver
errors are reported in the CSI_RX_STS register (address
0x7A).
3
2
0
0
Interrupt on FPD-Link III Receiver Parity Error
When enabled, an interrupt is generated on detection of
parity errors on the FPD-Link III interface for the receive
port. Parity error status is reported in the
IE_FPD3_PAR_ERR RW
PARITY_ERROR bit in the RX_PORT_STS1 register.
Interrupt on change in Port PASS status
When enabled, an interrupt is generated on a change in
receiver port valid status as reported in the PORT_PASS
bit in the PORT_STS1 register.
1
0
IE_PORT_PASS
IE_LOCK_STS
RW
RW
0
0
Interrupt on change in Lock Status
When enabled, an interrupt is generated on a change in
lock status. Status is reported in the LOCK_STS_CHG
bit in the RX_PORT_STS1 register.
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7.7.133 PORT_ISR_HI Register
表7-149. PORT_ISR_HI (Address 0xDA)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:5
Reserved
R
0x0
Reserved
FC GPIO Interrupt Status
A change in forward channel GPIO signal has been
detected. Forward Channel GPIO status is reported in
the FC_GPIO_STS register. This interrupt condition will
be cleared by reading the FC_GPIO_STS register.
4
3
IE_FC_GPIO
R
R
0
0
Interrupt on change in Sensor Status
A change in Sensor Status has been detected. Camera
Status is reported in the SENSOR_STS_X registers. This
interrupt condition will be cleared by reading the
SEN_INT_RISE_STS and SEN_INT_FALL_STS
registers.
IE_FC_SENS_STS
FPD-Link III Receiver Encode Error Interrupt Status
An encoding error on the FPD-Link III interface for the
receive port has been detected. Status is reported in the
FPD3_ENC_ERROR bit in the RX_PORT_STS2 register.
This interrupt condition is cleared by reading the
RX_PORT_STS2 register.
2
1
IS_FPD3_ENC_ERR
IS_BCC_SEQ_ERR
R
R
0
0
BCC CRC Sequence Error Interrupt Status
A Sequence Error has been detected for the Bi-
directional Control Channel forward channel receiver.
Status is reported in the BCC_SEQ_ERROR bit in the
RX_PORT_STS1 register.
This interrupt condition is cleared by reading the
RX_PORT_STS1 register.
BCC CRC error detect Interrupt Status
A CRC error has been detected on a Bi-directional
Control Channel frame received over the FPD-Link III
forward channel. Status is reported in the
BCC_CRC_ERROR bit in the RX_PORT_STS1 register.
This interrupt condition is cleared by reading the
RX_PORT_STS1 register.
0
IS_BCC_CRC_ERR
R
0
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7.7.134 PORT_ISR_LO Register
表7-150. PORT_ISR_LO (Address 0xDB)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7
RESERVED
R
0
Reserved
Video Line Length Interrupt Status
A change in video line length has been detected. Status is
reported in the LINE_LEN_CHG bit in the RX_PORT_STS2
register.
This interrupt condition is cleared by reading the
RX_PORT_STS2 register.
6
5
IS_LINE_LEN_CHG
IS_LINE_CNT_CHG
R
R
0
0
Video Line Count Interrupt Status
A change in number of video lines per frame has been
detected. Status is reported in the LINE_CNT_CHG bit in
the RX_PORT_STS2 register.
This interrupt condition is cleared by reading the
RX_PORT_STS2 register.
Receiver Buffer Error Interrupt Status
A Receive Buffer overflow has been detected as reported in
the BUFFER_ERROR bit in the RX_PORT_STS2 register.
This interrupt condition is cleared by reading the
RX_PORT_STS2 register.
4
3
IS_BUFFER_ERR
IS_CSI_RX_ERR
R
R
0
0
CSI Receiver Error Interrupt Status
The CSI Receiver has detected an error. CSI Receiver
errors are reported in the CSI_RX_STS register (address
0x7A). This interrupt condition will be cleared by reading the
CSI_RX_STS register.
FPD-Link III Receiver Parity Error Interrupt Status
A parity error on the FPD-Link III interface for the receive
port has been detected. Parity error status is reported in the
PARITY_ERROR bit in the RX_PORT_STS1 register.
This interrupt condition is cleared by reading the
RX_PORT_STS1 register.
2
1
0
IS_FPD3_PAR_ERR
IS_PORT_PASS
IS_LOCK_STS
R
R
R
0
0
0
Port Valid Interrupt Status
A change in receiver port valid status as reported in the
PORT_PASS bit in the PORT_STS1 register. This interrupt
condition is cleared by reading the RX_PORT_STS1
register.
Lock Interrupt Status
A change in lock status has been detected. Status is
reported in the LOCK_STS_CHG bit in the RX_PORT_STS1
register.
This interrupt condition is cleared by reading the
RX_PORT_STS1 register.
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7.7.135 FC_GPIO_STS Register
表7-151. FC_GPIO_STS (Address 0xDC)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
GPIO3 Interrupt Status.
7
GPIO3_INT_STS
R/COR
0
This bit indicates an interrupt condition has been met for
GPIO3. This bit is cleared on read.
GPIO2 Interrupt Status.
6
5
4
3
2
1
0
GPIO2_INT_STS
GPIO1_INT_STS
GPIO0_INT_STS
FC_GPIO3_STS
FC_GPIO2_STS
FC_GPIO1_STS
FC_GPIO0_STS
R/COR
0
0
0
0
0
0
0
This bit indicates an interrupt condition has been met for
GPIO2. This bit is cleared on read.
GPIO1 Interrupt Status.
This bit indicates an interrupt condition has been met for
GPIO1. This bit is cleared on read.
R/COR
GPIO0 Interrupt Status.
This bit indicates an interrupt condition has been met for
GPIO0. This bit is cleared on read.
R/COR
Forward Channel GPIO3 Status.
This bit indicates the current value for forward channel
GPIO3.
R
R
R
R
Forward Channel GPIO2 Status.
This bit indicates the current value for forward channel
GPIO2.
Forward Channel GPIO1 Status.
This bit indicates the current value for forward channel
GPIO1.
Forward Channel GPIO0 Status.
This bit indicates the current value for forward channel
GPIO0.
7.7.136 FC_GPIO_ICR Register
表7-152. FC_GPIO_ICR (Address 0xDD)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
GPIO3 Fall Interrupt Enable.
7
GPIO3_FALL_IE
RW
0
If this bit is set, an interrupt will be generated based on
detection of a falling edge on GPIO3.
GPIO3 Rise Interrupt Enable.
6
5
4
3
2
1
0
GPIO3_RISE_IE
GPIO2_FALL_IE
GPIO2_RISE_IE
GPIO1_FALL_IE
GPIO1_RISE_IE
GPIO0_FALL_IE
GPIO0_RISE_IE
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
If this bit is set, an interrupt will be generated based on
detection of a rising edge on GPIO3.
GPIO2 Fall Interrupt Enable.
If this bit is set, an interrupt will be generated based on
detection of a falling edge on GPIO2.
GPIO2 Rise Interrupt Enable.
If this bit is set, an interrupt will be generated based on
detection of a rising edge on GPIO2.
GPIO1 Fall Interrupt Enable.
If this bit is set, an interrupt will be generated based on
detection of a falling edge on GPIO1.
GPIO1 Rise Interrupt Enable.
If this bit is set, an interrupt will be generated based on
detection of a rising edge on GPIO1.
GPIO0 Fall Interrupt Enable.
If this bit is set, an interrupt will be generated based on
detection of a falling edge on GPIO0.
GPIO0 Rise Interrupt Enable.
If this bit is set, an interrupt will be generated based on
detection of a rising edge on GPIO0.
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7.7.137 SEN_INT_RISE_STS Register
表7-153. SEN_INT_RISE_STS (Address 0xDE)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Sensor Interrupt Rise Status.
This register provides the interrupt status for rising edge
transitions on the bits in SENSOR_STS_0. If a mask bit is
set in the SEN_INT_RISE_MASK register, a rising edge
transition on the corresponding SENSOR_STS_0 bit will
generate an interrupt that will be latched in this register.
7:0
SEN_INT_RISE
R/COR
0x00
7.7.138 SEN_INT_FALL_STS Register
表7-154. SEN_INT_FALL_STS (Address 0xDF)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Sensor Interrupt Fall Status.
This register provides the interrupt status for falling edge
transitions on the bits in SENSOR_STS_0. If a mask bit is
set in the SEN_INT_RISE_MASK register, a falling edge
transition on the corresponding SENSOR_STS_0 bit will
generate an interrupt that will be latched in this register.
7:0
SEN_INT_FALL
R/COR
0x00
7.7.139 FPD3_RX_ID0 Register
表7-155. FPD3_RX_ID0 (Address 0xF0)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
FPD3_RX_ID0
R
0x5F
FPD3_RX_ID0: First byte ID code: ‘_’
7.7.140 FPD3_RX_ID1 Register
表7-156. FPD3_RX_ID1 (Address 0xF1)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
FPD3_RX_ID1
R
0x55
FPD3_RX_ID1: 2nd byte of ID code: ‘U’
7.7.141 FPD3_RX_ID2 Register
表7-157. FPD3_RX_ID2 (Address 0xF2)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
FPD3_RX_ID2
R
0x42
FPD3_RX_ID2: 3rd byte of ID code: ‘B’
7.7.142 FPD3_RX_ID3 Register
表7-158. FPD3_RX_ID3 (Address 0xF3)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
FPD3_RX_ID3
R
0x39
FPD3_RX_ID3: 4th byte of ID code: ‘9’
7.7.143 FPD3_RX_ID4 Register
表7-159. FPD3_RX_ID4 (Address 0xF4)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
FPD3_RX_ID4
R
0x35
FPD3_RX_ID4: 5th byte of ID code: '5'
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7.7.144 FPD3_RX_ID5 Register
表7-160. FPD3_RX_ID5 (Address 0xF5)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
FPD3_RX_ID5
R
0x34
FPD3_RX_ID5: 6th byte of ID code: '4'
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7.7.145 I2C_RX0_ID Register
As an alternative to paging to access FPD-Link III receive port0 registers, a separate I2C address may be
enabled to allow direct access to the port 0 specific registers. The I2C_RX_0_ID register provides a simpler
method of accessing device registers specifically for port 0 without having to use the paging function to select
the register page. Using this address also allows access to all shared registers.
表7-161. I2C_RX0_ID (Address 0xF8)
BIT
7:1
0
FIELD
TYPE
RW
R
DEFAULT
DESCRIPTION
7-bit Receive Port 0 I2C ID
Configures the decoder for detecting transactions
designated for Receiver port 0 registers. A value of 0x00
in this field disables the Port0 decoder.
RX_PORT0_ID
RESERVED
0x0
0
Reserved
7.7.146 RESERVED Register
表7-162. RESERVED (Address 0xFA)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
R
0x00
Reserved
7.7.147 RESERVED Register
表7-163. RESERVED (Address 0xFB)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
R
0x00
Reserved
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7.7.148 Indirect Access Registers
Several functional blocks include register sets contained in the Indirect Access map (表 7-164); that is, Pattern
Generator, CSI-2 timing, and Analog controls. Register access is provided via an indirect access mechanism
through the Indirect Access registers (IND_ACC_CTL, IND_ACC_ADDR, and IND_ACC_DATA). These registers
are located at offsets 0xB0-0xB2 in the main register space.
The indirect address mechanism involves setting the control register to select the desired block, setting the
register offset address, and reading or writing the data register. In addition, an auto-increment function is
provided in the control register to automatically increment the offset address following each read or write of the
data register.
For writes, the process is as follows:
1. Write to the IND_ACC_CTL register to select the desired register block
2. Write to the IND_ACC_ADDR register to set the register offset
3. Write the data value to the IND_ACC_DATA register
If auto-increment is set in the IND_ACC_CTL register, repeating step 3 will write additional data bytes to
subsequent register offset locations
For reads, the process is as follows:
1. Write to the IND_ACC_CTL register to select the desired register block
2. Write to the IND_ACC_ADDR register to set the register offset
3. Read from the IND_ACC_DATA register
If auto-increment is set in the IND_ACC_CTL register, repeating step 3 will read additional data bytes from
subsequent register offset locations.
7.7.149
表7-164. Indirect Register Map Description
IA SELECT
0xB0[5:2]
PAGE/BLOCK
INDIRECT REGISTERS
ADDRESS RANGE
DESCRIPTION
Pattern Gen Registers
0x01-0x1F
0x40-0x48
Digital Page 0 Indirect
Registers
0000
0
1
CSI TX port 0 Timing Registers
Test and Debug registers
FPD-Link III Channel 0
Reserved Registers
0001
0x00-0x14
0010
0011
0100
2
3
4
Reserved
Reserved
Reserved
0x00-0x14
0x00-0x14
0x00-0x14
Reserved
Reserved
Reserved
FPD-Link III Share Reserved
Registers
0101
0110
5
6
0x00-0x04
0x00-0x14
Test and Debug registers
Write All FPD-Link III Reserved
Registers
Test and Debug registers
Test and Debug registers
0111
1001
7
9
CSI TX Reserved Registers
Unique DIE ID Registers
0x00-0x1D
0x00-0x0F
Hold 16 bytes that correspond to Die
ID data.
7.7.150 Reserved Register
表7-165. Reserved (Indirect Address Page 0x00; Register 0x00)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
R
0x0
Reserved
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7.7.151 PGEN_CTL Register
表7-166. PGEN_CTL (Indirect Address Page 0x00; Register 0x01)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:1
RESERVED
RW
0x0
Reserved
Pattern Generator Enable
1: Enable Pattern Generator
0: Disable Pattern Generator
0
PGEN_ENABLE
RW
0
7.7.152 PGEN_CFG Register
表7-167. PGEN_CFG (Indirect Address Page 0x00; Register 0x02)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Fixed Pattern Enable
Setting this bit enables Fixed Color Patterns.
0 : Send Color Bar Pattern
1 : Send Fixed Color Pattern
7
PGEN_FIXED_EN
RESERVED
RW
0
0
6
RW
Reserved
Number of Color Bars
00 : 1 Color Bar
5:4
3:0
NUM_CBARS
BLOCK_SIZE
RW
RW
0x3
0x3
01 : 2 Color Bars
10 : 4 Color Bars
11 : 8 Color Bars
Block Size
For Fixed Color Patterns, this field controls the size of the fixed
color field in bytes. Allowed values are 1 to 15.
7.7.153 PGEN_CSI_DI Register
表7-168. PGEN_CSI_DI (Indirect Address Page 0x00; Register 0x03)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
CSI Virtual Channel Identifier
7:6
PGEN_CSI_VC
RW
0x0
This field controls the value sent in the CSI packet for the Virtual
Channel Identifier
CSI Data Type
5:0
PGEN_CSI_DT
RW
0x24
This field controls the value sent in the CSI packet for the Data
Type. The default value (0x24) indicates RGB888.
7.7.154 PGEN_LINE_SIZE1 Register
表7-169. PGEN_LINE_SIZE1 (Indirect Address Page 0x00; Register 0x04)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Most significant byte of the Pattern Generator line size. This is the
active line length in bytes. Default setting is for 1920 bytes for a
640 pixel line width.
PGEN_LINE_SIZE[1
5:8]
7:0
RW
0x07
7.7.155 PGEN_LINE_SIZE0 Register
表7-170. PGEN_LINE_SIZE0 (Indirect Address Page 0x00; Register 0x05)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Least significant byte of the Pattern Generator line size. This is
the active line length in bytes. Default setting is for 1920 bytes
for a 640 pixel line width.
PGEN_LINE_SIZE[7:
0]
7:0
RW
0x80
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7.7.156 PGEN_BAR_SIZE1 Register
表7-171. PGEN_BAR_SIZE1 (Indirect Address Page 0x00; Register 0x06)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Most significant byte of the Pattern Generator color bar size.
This is the active length in bytes for the color bars. This value is
used for all except the last color bar. The last color bar is
determined by the remaining bytes as defined by the
PGEN_LINE_SIZE value.
PGEN_BAR_SIZE[15
:8]
7:0
RW
0x0
7.7.157 PGEN_BAR_SIZE0 Register
表7-172. PGEN_BAR_SIZE0 (Indirect Address Page 0x00; Register 0x07)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Least significant byte of the Pattern Generator color bar size.
This is the active length in bytes for the color bars. This value is
used for all except the last color bar. The last color bar is
determined by the remaining bytes as defined by the
PGEN_LINE_SIZE value.
PGEN_BAR_SIZE[7:
0]
7:0
RW
0xF0
7.7.158 PGEN_ACT_LPF1 Register
表7-173. PGEN_ACT_LPF1 (Indirect Address Page 0x00; Register 0x08)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Active Lines Per Frame
Most significant byte of the number of active lines per frame.
Default setting is for 480 active lines per frame.
PGEN_ACT_LPF[15:
8]
7:0
RW
0x01
7.7.159 PGEN_ACT_LPF0 Register
表7-174. PGEN_ACT_LPF0 (Indirect Address Page 0x00; Register 0x09)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Active Lines Per Frame
7:0
PGEN_ACT_LPF[7:0] RW
0xE0
Least significant byte of the number of active lines per frame.
Default setting is for 480 active lines per frame.
7.7.160 PGEN_TOT_LPF1 Register
表7-175. PGEN_TOT_LPF1 (Indirect Address Page 0x00; Register 0x0A)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Total Lines Per Frame
Most significant byte of the number of total lines per frame
including vertical blanking
PGEN_TOT_LPF[15:
8]
7:0
RW
0x02
7.7.161 PGEN_TOT_LPF0 Register
表7-176. PGEN_TOT_LPF0 (Indirect Address Page 0x00; Register 0x0B)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Total Lines Per Frame
7:0
PGEN_TOT_LPF[7:0] RW
0x0D
Least significant byte of the number of total lines per frame
including vertical blanking
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7.7.162 PGEN_LINE_PD1 Register
表7-177. PGEN_LINE_PD1 (Indirect Address Page 0x00; Register 0x0C)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Line Period
PGEN_LINE_PD[15:8
]
Most significant byte of the line period in 10ns units. The
default setting for the line period registers sets a line period of
31.75 microseconds.
7:0
RW
0x0C
7.7.163 PGEN_LINE_PD0 Register
表7-178. PGEN_LINE_PD0 (Indirect Address Page 0x00; Register 0x0D)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Line Period
Least significant byte of the line period in 10ns units. The
default setting for the line period registers sets a line period of
31.75 microseconds.
7:0
PGEN_LINE_PD[7:0] RW
0x67
7.7.164 PGEN_VBP Register
表7-179. PGEN_VBP (Indirect Address Page 0x00; Register 0x0E)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Vertical Back Porch
This value provides the vertical back porch portion of the
vertical blanking interval. This value provides the number of
blank lines between the FrameStart packet and the first video
data packet.
7:0
PGEN_VBP
RW
0x21
7.7.165 PGEN_VFP Register
表7-180. PGEN_VFP (Indirect Address Page 0x00; Register 0x0F)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Vertical Front Porch
This value provides the vertical front porch portion of the
vertical blanking interval. This value provides the number of
blank lines between the last video line and the FrameEnd
packet.
7:0
PGEN_VFP
RW
0x0A
7.7.166 PGEN_COLOR0 Register
表7-181. PGEN_COLOR0 (Indirect Address Page 0x00; Register 0x10)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Pattern Generator Color 0
For Reference Color Bar Patterns, this register controls the
byte data value sent during color bar 0.For Fixed Color
Patterns, this register controls the first byte of the fixed color
pattern.
7:0
PGEN_COLOR0
RW
0xAA
7.7.167 PGEN_COLOR1 Register
表7-182. PGEN_COLOR1 (Indirect Address Page 0x00; Register 0x11)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Pattern Generator Color 1
For Reference Color Bar Patterns, this register controls the
byte data value sent during color bar 1. For Fixed Color
Patterns, this register controls the second byte of the fixed
color pattern.
7:0
PGEN_COLOR1
RW
0x33
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7.7.168 PGEN_COLOR2 Register
表7-183. PGEN_COLOR2 (Indirect Address Page 0x00; Register 0x12)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Pattern Generator Color 2
For Reference Color Bar Patterns, this register controls the
byte data value sent during color bar 2. For Fixed Color
Patterns, this register controls the third byte of the fixed color
pattern.
7:0
PGEN_COLOR2
RW
0xF0
7.7.169 PGEN_COLOR3 Register
表7-184. PGEN_COLOR3 (Indirect Address Page 0x00; Register 0x13)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Pattern Generator Color 3
For Reference Color Bar Patterns, this register controls the
byte data value sent during color bar 3. For Fixed Color
Patterns, this register controls the fourth byte of the fixed color
pattern.
7:0
PGEN_COLOR3
RW
0x7F
7.7.170 PGEN_COLOR4 Register
表7-185. PGEN_COLOR4 (Indirect Address Page 0x00; Register 0x14)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Pattern Generator Color 4
For Reference Color Bar Patterns, this register controls the
byte data value sent during color bar 4. For Fixed Color
Patterns, this register controls the fifth byte of the fixed color
pattern.
7:0
PGEN_COLOR4
RW
0x55
7.7.171 PGEN_COLOR5 Register
表7-186. PGEN_COLOR5 (Indirect Address Page 0x00; Register 0x15)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Pattern Generator Color 5
For Reference Color Bar Patterns, this register controls the
byte data value sent during color bar 5. For Fixed Color
Patterns, this register controls the sixth byte of the fixed color
pattern.
7:0
PGEN_COLOR5
RW
0xCC
7.7.172 PGEN_COLOR6 Register
表7-187. PGEN_COLOR6 (Indirect Address Page 0x00; Register 0x16)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Pattern Generator Color 6
For Reference Color Bar Patterns, this register controls the
byte data value sent during color bar 6. For Fixed Color
Patterns, this register controls the seventh byte of the fixed
color pattern.
7:0
PGEN_COLOR6
RW
0x0F
7.7.173 PGEN_COLOR7 Register
表7-188. PGEN_COLOR7 (Indirect Address Page 0x00; Register 0x17)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Pattern Generator Color 7
For Reference Color Bar Patterns, this register controls the
byte data value sent during color bar 7. For Fixed Color
Patterns, this register controls the eighth byte of the fixed
color pattern.
7:0
PGEN_COLOR7
RW
0x80
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7.7.174 PGEN_COLOR8 Register
表7-189. PGEN_COLOR8 (Indirect Address Page 0x00; Register 0x18)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Pattern Generator Color 8
7:0
PGEN_COLOR8
RW
0x0
For Fixed Color Patterns, this register controls the ninth byte
of the fixed color pattern.
7.7.175 PGEN_COLOR9 Register
表7-190. PGEN_COLOR9 (Indirect Address Page 0x00; Register 0x19)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Pattern Generator Color 9
7:0
PGEN_COLOR9
RW
0x0
For Fixed Color Patterns, this register controls the tenth
byte of the fixed color pattern.
7.7.176 PGEN_COLOR10 Register
表7-191. PGEN_COLOR10 (Indirect Address Page 0x00; Register 0x1A)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Pattern Generator Color 10
7:0
PGEN_COLOR10
RW
0x0
For Fixed Color Patterns, this register controls the eleventh
byte of the fixed color pattern.
7.7.177 PGEN_COLOR11 Register
表7-192. PGEN_COLOR11 (Indirect Address Page 0x00; Register 0x1B)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Pattern Generator Color 11
7:0
PGEN_COLOR11
RW
0x0
For Fixed Color Patterns, this register controls the twelfth
byte of the fixed color pattern.
7.7.178 PGEN_COLOR12 Register
表7-193. PGEN_COLOR12 (Indirect Address Page 0x00; Register 0x1C)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Pattern Generator Color 12
7:0
PGEN_COLOR12
RW
0x0
For Fixed Color Patterns, this register controls the thirteenth
byte of the fixed color pattern.
7.7.179 PGEN_COLOR13 Register
表7-194. PGEN_COLOR13 (Indirect Address Page 0x00; Register 0x1D)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Pattern Generator Color 13
7:0
PGEN_COLOR13
RW
0x0
For Fixed Color Patterns, this register controls the fourteenth
byte of the fixed color pattern.
7.7.180 PGEN_COLOR14 Register
表7-195. PGEN_COLOR14 (Indirect Address Page 0x00; Register 0x1E)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Pattern Generator Color 14
7:0
PGEN_COLOR14
RW
0x0
For Fixed Color Patterns, this register controls the fifteenth byte
of the fixed color pattern.
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7.7.181 RESERVED Register
表7-196. RESERVED (Indirect Address Page 0x00; Register 0x1F)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
7:0
RESERVED
RW
0x0
Reserved
7.7.182 CSI0_TCK_PREP Register
表7-197. CSI0_TCK_PREP (Indirect Address Page 0x00; Register 0x40)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Override CSI Tck-prep parameter
7
MR_TCK_PREP_OV RW
0
0: Tck-prep is automatically determined
1: Override Tck-prep with value in bits 6:0 of this register
Tck-prep value
R
MR_TCK_PREP
RW
If bit 7 of this register is 0, this field is read-only, indicating
current automatically determined value.
If bit 7 of this register is 1, this field is read/write.
6:0
0x0
7.7.183 CSI0_TCK_ZERO Register
表7-198. CSI0_TCK_ZERO (Indirect Address Page 0x00; Register 0x41)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Override CSI Tck-zero parameter
7
MR_TCK_ZERO_OV RW
0
0: Tck-zero is automatically determined
1: Override Tck-zero with value in bits 6:0 of this register
Tck-zero value
R
MR_TCK_ZERO
RW
If bit 7 of this register is 0, this field is read-only, indicating
current automatically determined value.
If bit 7 of this register is 1, this field is read/write.
6:0
0x0
7.7.184 CSI0_TCK_TRAIL Register
表7-199. CSI0_TCK_TRAIL (Indirect Address Page 0x00; Register 0x42)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Override CSI Tck-trail parameter
7
MR_TCK_TRAIL_OV RW
0
0: Tck-trail is automatically determined
1: Override Tck-trail with value in bits 6:0 of this register
Tck-trail value
R
MR_TCK_TRAIL
RW
If bit 7 of this register is 0, this field is read-only, indicating
current automatically determined value.
If bit 7 of this register is 1, this field is read/write.
6:0
0x0
7.7.185 CSI0_TCK_POST Register
表7-200. CSI0_TCK_POST (Indirect Address Page 0x00; Register 0x43)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Override CSI Tck-post parameter
7
MR_TCK_POST_OV RW
0
0: Tck-post is automatically determined
1: Override Tck-post with value in bits 6:0 of this register
Tck-post value
R
MR_TCK_POST
RW
If bit 7 of this register is 0, this field is read-only, indicating
current automatically determined value.
If bit 7 of this register is 1, this field is read/write.
6:0
0x0
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7.7.186 CSI0_THS_PREP Register
表7-201. CSI0_THS_PREP (Indirect Address Page 0x00; Register 0x44)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Override CSI Ths-prep parameter
7
MR_THS_PREP_OV RW
0
0: Ths-prep is automatically determined
1: Override Ths-prep with value in bits 6:0 of this register
Ths-prep value
R
MR_THS_PREP
RW
If bit 7 of this register is 0, this field is read-only, indicating
current automatically determined value.
If bit 7 of this register is 1, this field is read/write.
6:0
0x0
7.7.187 CSI0_THS_ZERO Register
表7-202. CSI0_THS_ZERO (Indirect Address Page 0x00; Register 0x45)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Override CSI Ths-zero parameter
7
MR_THS_ZERO_OV RW
0
0: Ths-zero is automatically determined
1: Override Ths-zero with value in bits 6:0 of this register
Ths-zero value
R
MR_THS_ZERO
RW
If bit 7 of this register is 0, this field is read-only, indicating current
automatically determined value.
6:0
0x0
If bit 7 of this register is 1, this field is read/write.
7.7.188 CSI0_THS_TRAIL Register
表7-203. CSI0_THS_TRAIL (Indirect Address Page 0x00; Register 0x46)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Override CSI Ths-trail parameter
7
MR_THS_TRAIL_OV RW
0
0: Ths-trail is automatically determined
1: Override Ths-trail with value in bits 6:0 of this register
Ths-trail value
R
MR_THS_TRAIL
RW
If bit 7 of this register is 0, this field is read-only, indicating current
automatically determined value.
6:0
0x0
If bit 7 of this register is 1, this field is read/write.
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7.7.189 CSI0_THS_EXIT Register
表7-204. CSI0_THS_EXIT (Indirect Address Page 0x00; Register 0x47)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Override CSI Ths-exit parameter
7
MR_THS_EXIT_OV RW
0
0: Ths-exit is automatically determined
1: Override Ths-exit with value in bits 6:0 of this register
Ths-exit value
R
MR_THS_EXIT
RW
If bit 7 of this register is 0, this field is read-only, indicating current
automatically determined value.
6:0
0x0
If bit 7 of this register is 1, this field is read/write.
7.7.190 CSI0_TPLX Register
表7-205. CSI0_TPLX (Indirect Address Page 0x00; Register 0x48)
BIT
FIELD
TYPE
DEFAULT
DESCRIPTION
Override CSI Tplx parameter
7
MR_TPLX_OV
RW
0
0: Tplx is automatically determined
1: Override Tplx with value in bits 6:0 of this register
Tplx value
R
RW
If bit 7 of this register is 0, this field is read-only, indicating
current automatically determined value.
If bit 7 of this register is 1, this field is read/write.
6:0
MR_TPLX
0x0
7.7.191
LEGEND:
•
•
•
•
RW = Read Write
RW/SC = RW/SC = Read Write access/Self Clearing bit
R/P = Read Only, Permanent value
R/COR = Read Only, Clear On Read
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
8.1.1 System
The DS90UB638-Q1 is a highly integrated sensor chip that includes a single FPD-Link III input targeted at ADAS
applications, such as front, rear, and surround view cameras, camera monitoring systems, and sensor fusion.
8.1.2 Power-over-Coax
The DS90UB638-Q1 is designed to support the Power-over-Coax (PoC) method of powering remote sensor
systems. With this method, the power is delivered over the same medium (a coaxial cable) used for high-speed
digital video data and bidirectional control and diagnostics data transmission. The method uses passive
networks or filters that isolate the transmission line from the loading of the DC/DC regulator circuits and their
connecting power traces on both sides of the link as shown in 图8-1.
Sensor Module
Automotive ECU
DC-DC
Regulators
Power
Source
PoC
PoC
Coaxial Cable
POWER
CAC1
CAC1
FPD-Link III
Serializer
FPD-Link III
Deserializer
Processor
SoC
Image Sensor
FPD-Link III
Braided
Shield
CAC2
CAC2
RTERM
RTERM
图8-1. Power-over-Coax (PoC) System Diagram
The PoC networks' impedance of ≥ 1 kΩ over a specific frequency band is recommended to isolate the
transmission line from the loading of the regulator circuits. Higher PoC network impedance will contribute to
favorable insertion loss and return loss characteristics in the high-speed channel. The lower limit of the
frequency band is defined as ½ of the frequency of the back channel, fBC. The upper limit of the frequency band
is the frequency of the forward high-speed channel, fFC. However, the main criteria that need to be met in the
total high-speed channel, which consists of a serializer PCB, a deserializer PCB, and a cable, are the insertion
loss and return loss limits defined in the Total Channel Requirements, while the system is under maximum
#unique_301/
current load and extreme temperature conditions#unique_301/unique_301_Connect_42_X123333referenceTitle
unique_301_Connect_42_GUID-8667EFDD-57CE-44FD-BBD6-65D2BF97AE31referenceTitle
.
1. Contact TI for more information on the required Channel Specifications defined for each individual FPD-Link device.
2. The PoC network and any components along the high-speed trace on the PCB will contribute to the PCB loss budget. TI has
recommendations for the loss budget allocation for each individual PCB and cable component in the overall high-speed channel, but
the loss limits defined for the total channel in the Channel Specifications must be met.
图 8-2 shows a PoC network recommended for a 4G FPD-Link III consisting of DS90UB63x-Q1 CSI-2 and
DS90UB638-Q1 pair with the bidirectional channel operating at 50 Mbps (fBCC = 50 MHz) and the forward
channel operating at 4.16 Gbps (fFC ≈2 GHz).
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VPoC
R1
4.02 kW
L1
C1
C2
10 mH
0.1 mF
> 10 mF
FB3
FB2
FB1
CAC1
DOUT+
DOUT-
33 nF to 100 nF
CAC2
R2
49.9 W
15 nF to 47 nF
图8-2. Typical PoC Network for a 4 Gbps FPD-Link III
表8-1 lists essential components for this particular PoC network.
表8-1. Suggested Components for a 4 Gbps FPD-Link PoC Network
COUNT REF DES
DESCRIPTION
PART NUMBER
LQH3NPN100MJR
LQH3NPZ100MJR
MFR
Inductor, 10 µH, 0.288 Ωmaximum, 530 mA minimum (Isat, Itemp)
30-MHz SRF min, 3 mm × 3 mm, General-Purpose
Murata
Murata
Inductor, 10 µH, 0.288 Ωmaximum, 530 mA minimum (Isat, Itemp)
30-MHz SRF min, 3 mm × 3 mm, AEC-Q200
Inductor, 10 µH, 0.360 Ωmaximum, 450 mA minimum (Isat, Itemp)
30-MHz SRF min, 3.2 mm × 2.5 mm, AEC-Q200
1
L1
NLCV32T-100K-EFD
TYS3010100M-10
TYS3015100M-10
BLM18HE152SN1
BLM18HE152SZ1
TDK
Laird
Inductor, 10 µH, 0.400 Ωtypical, 550 mA minimum (Isat, Itemp)
39-MHz SRF typ, 3 mm × 3 mm, AEC-Q200
Inductor, 10 µH, 0.325 Ωmaximum, 725 mA minimum (Isat, Itemp)
41-MHz SRF typ, 3 mm × 3 mm, AEC-Q200
Laird
Ferrite Bead, 1.5 kΩat 1 GHz, 0.5 Ωmaximum at DC
500 mA at 85°C, SM0603, General Purpose
Murata
Murata
3
FB1-FB3
Ferrite Bead, 1.5 kΩat 1 GHz, 0.5 Ωmaximum at DC
500 mA at 85°C, SM0603, AEC-Q200
图8-3 shows a PoC network recommended for a 2G FPD-Link III consisting of a DS90UB633A-Q1 serializer and
DS90UB638-Q1 with the bidirectional channel operating at the data rate of 2.5 Mbps (½ fBCC = 2.5 MHz) and the
forward channel operating at the data rate as high as 1.87 Gbps (fFC ≈1 GHz).
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VPoC
R1
2.0 kW
L1
C1
C2
100 mH
0.1 mF
>10 mF
R2
L2
2.0 kW
4.7 mH œ 22 mH
FB1
CAC1
RIN+
RIN-
100 nF
CAC2
R3
49.9 W
47 nF
图8-3. Typical PoC Network for a 2G FPD-Link III
表8-2 lists essential components for this particular PoC network.
表8-2. Suggested Components for a 2G FPD-Link III PoC Network
COUNT REF DES
DESCRIPTION
PART NUMBER
MFR
Inductor, 100 µH, 0.310 Ωmaximum, 710 mA minimum (Isat, Itemp)
7.2-MHz SRF typical, 6.6 mm × 6.6 mm, AEC-Q200
1
1
L1
L2
MSS7341-104ML
Coilcraft
Inductor, 4.7 µH, 0.350 Ωmaximum, 700 mA minimum (Isat, Itemp)
160-MHz SRF typical, 3.8 mm x 3.8 mm, AEC-Q200
1008PS-472KL
Coilcraft
CBC3225T4R7MRV
Taiyo Yuden
Inductor, 4.7 µH, 0.130 Ωmaximum, 830 mA minimum (Isat, Itemp),
70-MHz SRF typical, 3.2 mm × 2.5 mm, AEC-Q200
Ferrite Bead, 1.5 kΩat 1 GHz, 0.5 Ωmaximum at DC
500-mA at 85°C, SM0603, General-Purpose
BLM18HE152SN1
BLM18HE152SZ1
Murata
Murata
1
FB1
Ferrite Bead, 1.5 kΩat 1 GHz, 0.5 Ωmaximum at DC
500-mA at 85°C, SM0603, AEC-Q200
Application report Power-over-Coax Design Guidelines for DS90UB953-Q1 (SNLA272) discusses PoC networks
in more detail.
In addition to the PoC network components selection, their placement and layout play a critical role as well.
• Place the smallest component, typically a ferrite bead or a chip inductor, as close to the connector as
possible. Route the high-speed trace through one of its pads to avoid stubs.
• Use the smallest component pads as allowed by manufacturer's design rules. Add anti-pads in the inner
planes below the component pads to minimize impedance drop.
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• Consult with the connector manufacturer for the optimized connector footprint. If the connector is mounted on
the same side as the IC, minimize the impact of the through-hole connector stubs by routing the high-speed
signal traces on the opposite side of the connector mounting side.
• Use coupled 100-Ωdifferential signal traces from the device pins to the AC-coupling caps. Use 50-Ωsingle-
ended traces from the AC-coupling capacitors to the connector.
• Terminate the inverting signal traces close to the connectors with standard 49.9-Ωresistors.
The suggested characteristics for single-ended PCB traces (microstrips or striplines) for serializer or deserializer
boards are detailed in 表8-3. The effects of the PoC networks must be accounted for when testing the traces for
compliance to the suggested limits.
表8-3. Suggested Characteristics for Single-Ended PCB Traces With Attached PoC Networks
PARAMETER
MIN
TYP
MAX UNIT
Ltrace Single-ended PCB trace length from the device pin to the connector pin
Ztrace Single-ended PCB trace characteristic impedance
5
55
60
cm
Ω
45
40
50
50
Zcon
Connector (mounted) characteristic impedance
Ω
tΔ
Allowable electrical length of the connector impedance discontinuity as measured with a
TDR (100 ps edge)
20
ps
Z_con
The VPOC noise must be kept 10 mVp-p or lower on the source / deserializer side of the system. The VPOC
fluctuations on the serializer side, caused by the transient current draw of the sensor and the DC resistance of
cables and PoC components, must be kept at minimum as well. Increasing the VPOC voltage and adding extra
decoupling capacitance (> 10 µF) help reduce the amplitude and slew rate of the VPOC fluctuations.
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8.2 Typical Application
VDD18_P0
VDD18_P1
1.8 V
VDD11_FPD0
0.01 µF
– µF
FB1
0.01 µF
µF
0.1 µF
10 uF
4.7 µF
–
0.01 µF
µF
VDD11_FPD1
VDD11_CSI
–
0.01 µF
µF
4.7 µF
4.7 µF
4.7 µF
–
VDD18_CSI
0.01 µF
µF
FB2 (opt)
FB3 (opt)
0.1 µF
0.1 µF
10 µF
–
0.01 µF
µF
–
VDD11_D
0.01 µF
µF
VDD18_FPD0
VDD18_FPD1
–
0.01 µF
µF
10 µF
–
0.01 µF
µF
23-26 MHz
(100 ppm)
–
XIN/REFCLK
XOUT
V(VDDIO)
VDDIO
VDDIO
0.01 µF
µF
FB4
0.1 µF
1 µF
–
C1
C2
RIN0+
RIN0-
0.01 µF
µF
–
FPD Link III
RTERM
VDD_SEL
1.8 V
CMLOUTP
CMLOUTN
TEST
PAD
R1
R2
0.1 µF
R3
R4
RES0
IDx
MODE
0.1 µF
RES1
RES2
1.8 V
HW control option
33 k
CSI0_CLKN
CSI0_CLKP
CSI0_D0N
CSI0_D0P
CSI0_D1N
CSI0_D1P
CSI0_D2N
CSI0_D2P
SW Control
V(VDDIO)
PDB
>10 µF
4.7 k
CSI-2 Outputs
GPIO3/INTB
GPIO0
CSI0_D3N
GPIO1
GPIO
GPIO2
CSI0_D3P
GPIO4
GPIO5
CSI1_CLKN
CSI1_CLKP
GPIO6
LOCK
PASS
Status
NOTE:
- FB2, FB3 may be required depending on system power supply noise levels
- FB1-FB4: DCR 25mΩ; Z = 120Ω@100MHz
- C1, C2, C3, C4 (see Design Parameters Values Table)
- R1, R2 (see IDX Resistor Values Table)
- R3, R4 (see MODE Resistor Values Table)
- RTERM = 50
1.8 V or
3.3 V
DAP
4.7 k 4.7 k
I2C_SDA
I2C_SCL
I2C
DS90UB638-Q1 Deserializer
图8-4. Typical Connection Diagram Coaxial With Internal 1.1-V LDO
备注
- The decoupling capacitors for VDD11 are different between the two typical application diagrams
because VDD_SEL is pulled to different levels. See the 节5 table for more information.
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1.1 V
VDD18_P0
VDD18_P1
1.8 V
VDD11_FPD0
0.01 µF
µF
FB1
0.01 µF
µF
0.1 µF
10 uF
FB7
10 uF 1.0 µF
–
–
0.01 µF
µF
VDD11_FPD1
VDD11_CSI
–
0.01 µF
µF
–
VDD18_CSI
0.01 µF
µF
FB2
FB3
0.1 µF
0.1 µF
10 µF
–
0.01 µF
µF
FB6
FB5
1.0 µF
1.0 µF
–
VDD11_D
0.01 µF
µF
VDD18_FPD0
VDD18_FPD1
–
0.01 µF
µF
10 µF
–
0.01 µF
µF
23-26 MHz
(100 ppm)
–
XIN/REFCLK
XOUT
V(VDDIO)
VDDIO
VDDIO
0.01 µF
µF
FB4
0.1 µF
1 µF
–
C1
C2
RIN0+
RIN0-
0.01 µF
µF
FPDNLink III
–
VDD_SEL
1.8 V
CMLOUTP
CMLOUTN
TEST
PAD
R1
R2
0.1 µF
R3
R4
RES0
IDx
MODE
RES1
RES2
0.1 µF
1.8 V
HW control option
33 k
CSI0_CLKN
CSI0_CLKP
CSI0_D0N
CSI0_D0P
CSI0_D1N
CSI0_D1P
CSI0_D2N
CSI0_D2P
SW Control
V(VDDIO)
PDB
RES
>10 µF
4.7 k
CSI-2 Outputs
GPIO3/INTB
GPIO0
CSI0_D3N
GPIO1
GPIO
GPIO2
CSI0_D3P
GPIO4
GPIO5
CSI1_CLKN
CSI1_CLKP
GPIO6
LOCK
PASS
Status
NOTE:
- FB1-FB4: DCR 25mΩ; Z = 120Ω@100MHz
- C1, C2, C3, C4 (see Design Parameters Values Table)
- R1, R2 (see IDX Resistor Values Table)
1.8 V or
3.3 V
DAP
- R3, R4 (see MODE Resistor Values Table)
4.7 k 4.7 k
I2C_SDA
I2C_SCL
I2C
DS90UB638-Q1 Deserializer
图8-5. Typical Connection Diagram With External 1.1-V Supply
备注
- The decoupling capacitors for VDD11 are different between the two typical application diagrams
because VDD_SEL is pulled to different levels. See the 节5 table for more information.
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8.2.1 Design Requirements
For the typical design application, use the parameters listed in 表8-4.
表8-4. Design Parameters
DESIGN PARAMETER
V(VDDIO)
EXAMPLE VALUE
1.8 V or 3.3 V
1.8 V
V(VDD18)
V(VDD11)( When VDD_SEL = HIGH)
1.1 V
AC-coupling Capacitor for Synchronous Modes, Coaxial Connection:
RIN+
33 nF - 100nF (50 WV 0402)
15 nF - 47nF (50 WV 0402)
33 nF - 100nF (50 WV 0402)
100 nF (50 WV 0402)
AC-coupling Capacitor for Synchronous Modes, Coaxial Connection:
RIN-
AC-coupling Capacitor for Synchronous Modes, STP Connection:
RIN±
AC-coupling Capacitor for Non-Synchronous and DVP Backwards
Compatible Modes, Coaxial Connection: RIN+
AC-coupling Capacitor for Non-Synchronous and DVP Backwards
Compatible Modes, Coaxial Connection: RIN-
47 nF (50 WV 0402)
AC-coupling Capacitor for Non-Synchronous and DVP Backwards
Compatible Modes, STP Connection: RIN±
100 nF (50 WV 0402)
The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme.
External AC-coupling capacitors must be placed in series in the FPD-Link III signal path as shown in 图 8-6. For
applications using single-ended, 50-Ω coaxial cable, terminate the unused data pins (RIN–) with an AC-
coupling capacitor and a 50-Ωresistor.
D
+
OUT
R
IN
+
SER
DES
R
IN
-
D
-
OUT
50Q
50Q
图8-6. AC-Coupled Connection (Coaxial)
D
+
OUT
R
IN
+
SER
DES
R
IN
-
D
-
OUT
图8-7. AC-Coupled Connection (STP)
For high-speed FPD–Link III transmissions, use the smallest available package for the AC-coupling capacitor to
help minimize degradation of signal quality due to package parasitics.
8.2.2 Detailed Design Procedure
图 8-4 and 图 8-5 show typical applications of the DS90UB638-Q1 for multi-camera surround view system. From
图8-4, the FPD-Link III is AC-coupled external 100-nF and 47-nF capacitors for coaxial interconnects. The same
AC-coupling capacitor values should be matched on the paired serializer boards. The deserializer has an
internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, 0.1-μF or 0.01-
μF capacitors should be used for each of the core supply pins for local device bypassing. Additional bulk
decoupling capacitors and ferrite beads are placed on the VDD18 supplies for effective noise suppression.
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8.2.3 Application Curves
Time (50 ns/DIV)
Time (50 ns/DIV)
图8-8. CSI-2 DATA and CLK Output
图8-9. CSI-2 DATA and Continuous CLK Output
P
LP11
LP01
LP00
HS0
HS Data
P
N
LP11
HS Data
HS0
N
Time (50 ns/DIV)
Time (50 ns/DIV)
图8-10. CSI-2 Start of Transmission (SoT)
图8-11. CSI-2 End of Transmission (EoT)
8.3 System Examples
The DS90UB638-Q1 has one input port that is capable of operating a single sensor. (图 8-12). Rx data can be
replicated onto two 2-lane CSI-2 outputs for interconnect to two separate CSI-2 Rx inputs for parallel
downstream processing.
DS90UB638-Q1
Deserializer
DS90UB638-Q1
Serializer
MIPI CSI-2
3.2 Gbps
MIPI CSI-2
1.6 Gbps/lane X 2
Host / ISP
MIPI CSI-2
1.6 Gbps/lane X 2
图8-12. DS90UB638-Q1 Sensor Data Replicated onto 2x 2-Lane CSI-2
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9 Power Supply Recommendations
This device provides separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. The Pin Configuration and Functions section provides guidance on which circuit blocks are connected
to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive
circuits such as PLLs.
9.1 VDD and VDDIO Power Supply
Each VDD power supply pin must have a 10-nF (or 100-nF) capacitor to ground connected as close as possible
to DS90UB638-Q1 device. When operating VDDIO at 1.8-V nominal supply, the voltage at VDDIO must be
within ±100 mV of VDD18 to ensure VIH, VIL specifications. TI recommends having additional decoupling
capacitors (1 µF or 10 µF) connected to a common GND plane. Note that although average current for VDDIO is
less than 10 mA maximum, the peak current into VDDIO may exceed 100 mA on device start-up.
9.2 Power-Up Sequencing
The power-up sequence for the DS90UB638-Q1 is as follows:
VDD18
T0
VDDIO
T5
T6
T1
T4
Hard
Reset
PDB
REFCLK
DON’T CARE
图9-1. Power Supply Sequencing VDD_SEL = LOW, Internal VDD 1.1-V Supply
VDD18
T0
VDDIO
T1
T2
VDD11
T5
T6
T3
T4
Hard
Reset
PDB
REFCLK
图9-2. Power Supply Sequencing VDD_SEL = HIGH, External VDD 1.1-V Supply
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表9-1. Timing Diagram for the Power Supply Start-Up Sequence
PARAMETER
MIN
0.05
0.2
0
TYP
MAX
UNIT
NOTES
at 10/90%
at 10/90%
T0
T1
T2
VDD18 rise time
ms
ms
ms
VDDIO rise time
1
VDD18 High to VDD11 applied
N/A when VDD_SEL
= LOW
T3
T4
VDD11 rise time
VDD to PDB
0.2
0
1
ms
ms
at 10/90%
After all VDD are
stable
T5
T6
T7
PDB high time before PDB hard reset
PDB high to low pulse width
1
2
2
ms
ms
ms
Hard reset (optional)
PDB to I2C ready (IDX and MODE valid)
delay
Note: VDDIO can come up either before or after VDD18.
9.2.1 PDB Pin
The PDB pin is active high and has internal 50-kΩ pulldown resistor. PDB input must remain low while the VDD
pin power supplies are in transition. Typically PDB will be connected to GPIO from processor also with internal
pulldown. Alternatively, when VDD_SEL = LOW, an external RC network on the PDB pin may be connected to
ensure PDB arrives after all the supply pins have settled to the recommended operating voltage. When PDB pin
is pulled up to VDD18, a 10-kΩ pullup and a > 10-μF capacitor to GND are recommended to delay the PDB
input signal rise. All inputs must not be driven until both power supplies have reached steady state. When
VDD_SEL = HIGH, TI does not recommend that he user connect the PDB pin through a RC circuit, as this may
conflict with the sequencing of the external 1.1-V supply rail.
表9-2. PDB Pin Pulse Width
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PDB
tLRST
PDB Reset Low Pulse
2
3
ms
9.2.2 System Initialization
When initializing the communications link between the DS90UB638-Q1 deserializer and a DS90UB635-Q1
serializer, the sensor module requires a local reference clock and timing would follow 图9-3.
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VDD18
VDDIO
VDD11
(int)
PDB
T1
MODE,
IDX Valid
REFCLK
LOCK
638 Lock Time
I2C
Local
638
Config
CSI Tx enable,
RX Port Forward
I2C
Remote
Sensor
Config
RIN+
EXTCLK Reference to SER
CSI TX
CLK
图9-3. Power-Up Sequencing Non-Synchronous Back Channel Clocking Mode, VDD_SEL = LOW
Note that in order to speed up access to remote target I2C devices attached to the DS90UB635-Q1 from the
DS90UB638-Q1 deserializer device, it is recommended to program the watchdog timer speedup by setting 0x0A
= 0x12 after LOCK is established with the remote deserializer.
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10 Layout
10.1 PCB Layout Guidelines
Circuit board layout and stack-up for the FPD-Link III devices must be designed to provide low-noise power feed
to the device. Good layout practice also separates high-frequency or high-level inputs and outputs to minimize
unwanted noise pickup, feedback, and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power or ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies, and makes the value and placement of external bypass capacitors less critical. External bypassing
should be low-ESR ceramic capacitors with high-quality dielectric. The voltage rating of the ceramic capacitors
must be at least 2× the power supply voltage being used.
TI recommends surface-mount capacitors due to their smaller parasitics. When using multiple capacitors per
supply pin, place the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 47-µF to 100-µF range, which smooths low frequency switching noise. TI
recommends connecting power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor increases the inductance of the path.
A small body size X7R chip capacitor, such as 0603 or 0402, is recommended for external bypass. Its small
body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance
frequency of these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective
bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the
frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins
to the planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs (see Pin Configuration and Functions). In some cases, an external filter may be used to provide clean
power to sensitive circuits such as PLLs.
Use at least a four-layer board with a power and ground plane. Place the CSI-2 signals away from the single-
ended or differential FPD RX input traces to prevent coupling from the CSI-2 signals to the RX inputs. The
following sections provide important details for routing the FPD-Link III traces, PoC filter, and CSI-2 traces.
10.1.1 Ground
TI recommends that a consistent ground plane reference for the high-speed signals in the PCB design to provide
the best image plane for signal traces running parallel to the plane. Connect the thermal pad of the DS90UB638-
Q1 to the GND plane with vias.
10.1.2 Routing FPD-Link III Signal Traces and PoC Filter
Routing the FPD-Link III signal traces between the RIN pins and the connector as well as connecting the PoC
filter to these traces are the most critical pieces of a successful DS90UB638-Q1 PCB layout. 图 10-1 shows an
example PCB layout of the DS90UB638-Q1 configured for interface to remote sensor modules over coaxial
cables. The layout example also uses a footprint of an edge-mount FAKRA connector provided by Rosenberger
(P/N: 59S20X-40ML5-Z). For additional PCB layout details of the example, check the DS90UB954-Q1EVM
user's guide. Note that the DS90UB638-Q1 shares this user guide with other related products such as the
DS90UB954-Q1.
The following list provides essential recommendations for routing the FPD-Link III signal traces between the
DS90UB638-Q1 receiver input pins (RIN) and the FAKRA connector, and connecting the PoC filter.
• The routing of the FPD-Link III traces may be all on the top layer (as shown in the example) or partially
embedded in middle layers if EMI is a concern.
• The AC-coupling capacitors should be on the top layer and very close to the DS90UB638-Q1 receiver input
pins to minimize the length of coupled differential trace pair between the pins and the capacitors.
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• Route the RIN+ trace between the AC-coupling capacitor and the FAKRA connector as a 50-Ωsingle-ended
micro-strip with tight impedance control (±10%). Calculate the proper width of the trace for a 50-Ω
impedance based on the PCB stack-up. Ensure that the trace can carry the PoC current for the maximum
load presented by the remote sensor module.
• The PoC filter should be connected to the RIN+ trace through the first ferrite bead (FB1). The FB1 should be
touching the high-speed trace to minimize the stub length seen by the transmission line. Create an anti-pad
or a moat under the FB1 pad that touches the trace. The anti-pad should be a plane cutout of the ground
plane directly underneath the top layer without cutting out the ground reference under the trace. The purpose
of the anti-pad is to maintain the impedance as close to 50 Ωas possible.
• Route the RIN–trace loosely coupled to the RIN+ trace for the length similar to the RIN+ trace length when
possible. This will help the differential nature of the receiver to cancel out any common-mode noise that may
be present in the environment that may couple on to the RIN+ and RIN–signal traces. When routing on
inner layers, length matching for single-ended traces does not provide as significant benefit.
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10.1.3 Routing CSI-2 Signal Traces
Routing the CSI-2 signal traces between the CSI-2 pins and the CSI-2 connector is also important for a
successful DS90UB638-Q1 PCB layout. 图 10-3 shows essential details for routing the CSI-2 traces. Additional
recommendations are given in the following list:
1. Route CSI_D0N, CSI_D0P, CSI_D1N, and CSI_D1P pairs as differential coupled striplines with controlled
100-Ωdifferential impedance (±10%)
2. Keep the trace length difference between CSI-2 traces to 5 mils of each other.
3. Length matching should be near the location of mismatch.
4. Each pair should be separated at least by 5 times the signal trace width.
5. Keep away from other high-speed signals.
6. Keep the use of bends in differential traces to a minimum. When bends are used, the number of left and right
bends must be as equal as possible, and the angle of the bend should be ≥135 degrees. This arrangement
minimizes any length mismatch caused by the bends and therefore minimizes the impact that bends have on
EMI.
7. Route all differential pairs on one or two inner layers.
8. Keep the number of signal vias to a minimum —TI recommends keeping the via count to the maximum of
two per CSI-2 trace.
9. Keep traces on layers adjacent to ground plane.
10. Do NOT route differential pairs over any plane split.
11. Adding Test points causes impedance discontinuity and therefore negatively impacts signal performance. If
test points are used, place them in series and symmetrically. Test points must not be placed in a manner that
causes a stub on the differential pair.
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10.2 Layout Examples
Follow PCB footprint
recommendations
from the connector
manufacturer to
maintain 50-W
impedance through
the connector
Route RIN+ trace as a
50-W single-ended
trace with tight
impedance control
( 10%)
Ensure RIN+ trace
can carry PoC current
without significant
temperature rise
(<10°C)
Place the smallest
ferrite bead or RF
inductor orthogonally
right next to the RIN+
trace
49.9W
PoC Filter
Route RIN- trace
loosely coupled to the
RIN+ trace (S > 3W)
FB1
FB2
R1
L1
Moat the GND plane
underneath the FB1
pad touching the RIN+
trace to minimize
parasitic capacitance,
but maintain the GND
plane underneath the
RIN+ trace
PoC Voltage
Entry Point
RIN-
RIN+
CAC
CAC
Place AC coupling
caps close to RIN
pins to minimize the
length of the RIN
differential traces
RIN Pins
Thermal vias
under device
PAD
*W is a trace width. S is a
gap between adjacent
traces.
图10-1. DS90UB638-Q1 PCB Layout Example: FPD-Link III Signal Traces and PoC Filter
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Follow PCB footprint
recommendations from the
connector manufacturer to
maintain 100-W differential
impedance through the
connector
Route RIN traces as 100-W
coupled striplines with
tight impedance control
( 10%)
Route RIN traces on an inner
signal layer close to the
bottom layer or the bottom
layer to minimize the
Optional common mode
choke
connector stub length
Back drill the top side of the
vias to minimize the via stub
length
L1
Place AC coupling caps
close to RIN pins to
minimize the length of
coupled microstrips
CAC
CAC
RIN Pins
Thermal vias under device
PAD
*W is a trace width. S is a
gap between adjacent
traces.
图10-2. DS90UB638-Q1 PCB Layout Example: FPD-Link III Differential Signal Traces
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Thermal vias under
device PAD
Optional 0-W resistors
Bring CSI traces to
the inner layers close
to the CSI pins
Route CSI traces as
100-W differential
coupled striplines
(S=2W*) with tight
impedance control
( 10%)
Ensure CSI trace
length is matched
within 5 mils for
minimal intra-pair and
pair-pair skew
Avoid acute angles
when routing CSI
traces
Ensure pair-pair gap
is >5W* for minimal
pair-pair coupling
Route CSI traces on 1
or 2 inner signal
layers each
sandwiched with GND
or power planes to
form coupled
striplines
CSI-2 Connector
*W is a trace width. S is a
gap between adjacent
traces.
图10-3. DS90UB638-Q1 PCB Layout Example: CSI-2 Traces
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• I2C Communication Over FPD-Link III With Bidirectional Control Channel (SNLA131)
• I2C Bus Pullup Resistor Calculation (SLVA689)
• FPD-Link Learning Center
• An EMC/EMI System-Design and Testing Methodology for FPD-Link III SerDes (SLYT719)
• Ten Tips for Successfully Designing With Automotive EMC/EMI Requirements (SLYT636)
• Power-over-Coax Design Guidelines for DS90UB953-Q1
• DS90UB953-Q1EVM user's guide (SNLU224)
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90UB638TRGZRQ1
DS90UB638TRGZTQ1
ACTIVE
ACTIVE
VQFN
VQFN
RGZ
RGZ
48
48
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
UB638Q
UB638Q
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2023
Addendum-Page 2
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
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PACKAGE OUTLINE
RGZ0048B
VQFN - 1 mm max height
S
C
A
L
E
2
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
7.15
6.85
A
B
PIN 1 INDEX AREA
7.15
6.85
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2X 5.5
4.1 0.1
(0.2) TYP
EXPOSED
THERMAL PAD
13
24
44X 0.5
12
25
49
SYMM
2X
5.5
0.30
0.18
36
48X
1
0.1
0.05
C B A
48
37
SYMM
PIN 1 ID
(OPTIONAL)
0.5
0.3
48X
4218795/B 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGZ0048B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.1)
(1.115) TYP
(0.685)
TYP
37
48
48X (0.6)
1
36
48X (0.24)
(1.115)
TYP
44X (0.5)
(0.685)
TYP
SYMM
49
(
0.2) TYP
VIA
(6.8)
(R0.05)
TYP
12
25
13
24
SYMM
(6.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218795/B 02/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGZ0048B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.37)
TYP
37
48
48X (0.6)
1
36
48X (0.24)
44X (0.5)
(1.37)
TYP
SYMM
49
(R0.05) TYP
(6.8)
9X
METAL
TYP
(
1.17)
12
25
13
24
SYMM
(6.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:12X
4218795/B 02/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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