DS90UR904Q-Q1 [TI]
10MHz 至 43MHz 18 位色彩 FPD-Link II 解串器;
| 型号： | DS90UR904Q-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10MHz 至 43MHz 18 位色彩 FPD-Link II 解串器 光电二极管 |
| 文件： | 总44页 (文件大小：1220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Sample &
Buy
Support &
Community
Product
Folder
Tools &
Software
Technical
Documents
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
DS90UR903Q/DS90UR904Q 10 - 43MHz
18 位彩色 FPD-Link II 串行器和解串器
1 特性
3 说明
1
•
•
•
•
10MHz 至 43MHz 输入并行端口时钟 (PCLK) 支持
DS90UR903Q/DS90UR904Q 芯片组提供一个具有高
速正向通道的 FPD-Link II 接口，用来实现单一差分对
上的数据传输。 此串化器/解串器对针对图形主机控制
器与显示模块间的直接连接。 这个芯片组非常适合于
将视频数据驱动至要求 18 位色深（RGB666 +
HS，VS 和 DE）的显示屏。 此串化器转换一个单个
高速串行数据流上的 21 位数据。 这个单个串行数据
流通过消除并行数据与时钟路径间的偏差，简化了印刷
电路板 (PCB) 走线和电缆上的宽数据总线传输。 这
样，通过限制数据路径的宽度，大大节省了系统成本，
相应地减少了 PCB 层数、电缆宽度以及连接器尺寸和
引脚数量。
210Mbps 至 903Mbps 数据吞吐量
单个差分对互连
具有 DC 平衡编码的嵌入式时钟以支持 AC 耦合互
连
•
•
•
•
•
•
•
•
能够驱动长达 10 米的屏蔽双绞线
用于器件配置的 I2C 兼容串口
单个硬件器件寻址引脚
LOCK（锁定）输出报告引脚以验证链路完整性
集成端接电阻器
1.8V 或 3.3V 兼容并行总线接口
1.8V 单电源
符合 ISO 10605 静电放电 (ESD) 以及 IEC 61000-
4-2 ESD 标准
解串器输入提供均衡控制来补偿较长距离介质上的损
耗。 内部 DC 均衡编码/解码被用来支持 AC 耦合互
连。
•
•
•
•
•
汽车应用级产品：符合 AEC-Q100 2 级要求
温度范围：-40°C 至 +105°C
解串器上无需基准时钟
此串化器采用 40 引脚超薄型四方扁平无引线 (WQFN)
封装，而解串器采用 48 引脚 WQFN 封装。
可编程接收均衡
电磁干扰 (EMI) / 电磁兼容性 (EMC) 迁移
器件信息(1)
–
–
DES 可编程展频 (SSCG) 输出
DES 接收器交错输出
部件号
封装
封装尺寸（标称值）
DS90UR903Q-Q1
WQFN RTA (40)
6.00mm x 6.00mm
超薄四方扁平无引线
(WQFN) RHS (48)
DS90UR904Q-Q1
7.00mm x 7.00mm
2 应用范围
•
汽车显示系统
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
–
–
–
中央信息显示屏
导航显示屏
后座娱乐系统
典型眼图
简化电路原理图
DS90UR903Q
Serializer
DS90UR904Q
Deserializer
FPD-Link II
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
Timing
Controller
PCLK
Graphics
Controller
---
PLL
PCLK
Video
LCD
Display
Processor
PDB
MODE
PDB
MODE
Config.
Config.
PC
SDA
SCL
SDA
SCL
PC
Time (200 ps/DIV)
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SNLS346
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
www.ti.com.cn
目录
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 18
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 20
7.5 Programming .......................................................... 20
7.6 Register Maps......................................................... 22
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Applications ................................................ 26
Power Supply Recommendations...................... 31
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ..................................... 6
6.2 Handling Ratings ...................................................... 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information ................................................ 7
8
9
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Example .................................................... 32
11 器件和文档支持 ..................................................... 35
11.1 文档支持................................................................ 35
11.2 相关链接................................................................ 35
11.3 商标....................................................................... 35
11.4 静电放电警告......................................................... 35
11.5 术语表 ................................................................... 35
12 机械封装和可订购信息 .......................................... 35
6.5 Electrical Characteristics
................................................................................... 7
6.6 Recommended Serializer Timing for PCLK ............. 9
6.7 Serial Control Bus AC Timing Specifications (SCL,
SDA) - I2C Compliant (See Figure 1)....................... 10
6.8 Serial Control Bus DC Characteristics (SCL, SDA) -
I2C Compliant........................................................... 11
6.9 Serializer Switching Characteristics........................ 15
6.10 Deserializer Switching Characteristics.................. 16
6.11 Typical Characteristics.......................................... 17
Detailed Description ............................................ 18
7
4 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2013) to Revision C
Page
•
已添加 更改了数据表流程和布局以符合全新的 TI 标准。 添加了以下部分：应用和实施；电源相关建议；布局；器件
和文档支持；机械、封装和订购信息 ...................................................................................................................................... 1
Added additional thermal charateristics.................................................................................................................................. 7
Changed test condition Vin to Vddio ........................................................................................................................................ 7
Added power up sequencing information and timing diagram. ............................................................................................ 29
Added application graphics of the serializer CML output. .................................................................................................... 30
•
•
•
•
Changes from Revision A (April 2013) to Revision B
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 30
2
Copyright © 2011–2014, Texas Instruments Incorporated
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com.cn
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
5 Pin Configuration and Functions
40 Pin Serializer – DS90UR903Q
Package RTA
Top View
31
32
33
34
35
36
37
38
39
40
20 NC
19 NC
V
DDIO
DIN[8]
DIN[9]
DAP = GND
18
V
DDCML
17 DOUT+
16 DOUT-
V
DDD
DS90UR903Q
Serializer
40-Pin WQFN
(Top View)
DIN[10]
DIN[11]
15
14
V
V
DDT
DIN[12]
DIN[13]
DIN[14]
DIN[15]
DDPLL
13 PDB
12 MODE
11 RES
DS90UR903Q Serializer Pin Functions
PIN
I/O, TYPE
DESCRIPTION
NAME
NUMBER
LVCMOS PARALLEL INTERFACE
DIN[20:0]
PCLK
5, 4, 3, 2, 1, 40,
39, 38, 37, 36, 35,
33, 32, 30, 29, 28,
27, 26, 25, 24, 23
Inputs, LVCMOS Parallel data inputs.
w/ pull down
6
Input, LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register.
w/ pull down
SERIAL CONTROL BUS - I2C COMPATIBLE
Input,
Open Drain
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to VDDIO
SCL
SDA
7
8
.
Input/Output,
Open Drain
Data line for the serial control bus communication
SDA requires an external pull-up resistor to VDDIO
.
I2C Mode select
Input, LVCMOS
w/ pull down
MODE
ID[x]
12
9
MODE = H, -REQUIRED. The MODE pin must be set HIGH to allow I2C
configuration of the serializer.
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 1
Input, analog
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB = H, Serializer is enabled and is ON.
Input, LVCMOS
w/ pull down
PDB
13
PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power
Down, the PLL is shutdown, and IDD is minimized. Programmed control
register data are NOT retained and reset to default values
Input, LVCMOS Reserved.
w/ pull down This pin MUST be tied LOW.
RES
NC
10, 11
22, 21, 20, 19
No Connect
Copyright © 2011–2014, Texas Instruments Incorporated
3
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
www.ti.com.cn
DS90UR903Q Serializer Pin Functions (continued)
PIN
I/O, TYPE
DESCRIPTION
NAME
NUMBER
FPD-LINK II INTERFACE
Output, CML
Output, CML
Non-inverting differential output. The interconnect must be AC Coupled with a
100 nF capacitor.
DOUT+
17
16
DOUT-
Inverting differential output. The interconnect must be AC Coupled with a 100
nF capacitor.
POWER AND GROUND(1)
VDDPLL
VDDT
14
15
18
34
Power, Analog
Power, Analog
Power, Analog
Power, Digital
Power, Digital
PLL Power, 1.8V ±5%
Tx Analog Power, 1.8V ±5%
CML Power, 1.8V ±5%
Digital Power, 1.8V ±5%
VDDCML
VDDD
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from
VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
VDDIO
31
Ground, DAP
DAP must be grounded. DAP is the large metal contact at the bottom side,
located at the center of the WQFN package. Connected to the ground plane
(GND) with at least 16 vias.
VSS
DAP
(1) See Power Up Requirements and PDB PIN.
48 Pin Deserializer - DS90UR904Q
Package RHS
Top View
RES
RES
RES
ROUT[4]
ROUT[5]
ROUT[6]
ROUT[7]
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
DAP = GND
V
DDCML
RIN+
V
DDIO2
DS90UR904Q
RIN-
RES
RES
ROUT[8]
ROUT[9]
Deserializer
48-Pin WQFN
(Top View)
V
DDD
ROUT[10]
ROUT[11]
ROUT[12]
ROUT[13]
V
DDPLL
RES
MODE
ID[x]
4
Copyright © 2011–2014, Texas Instruments Incorporated
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com.cn
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
DS90UR904Q Deserializer Pin Descriptions
PIN
I/O, TYPE
DESCRIPTION
NAME
NUMBER
LVCMOS PARALLEL INTERFACE
5, 6, 8, 9, 10,
11, 12, 13, 14,
15, 16, 18, 19,
21, 22, 23, 24,
25, 26, 27, 28
Outputs,
LVCMOS
ROUT[20:0]
PCLK
Parallel data outputs.
Pixel Clock Output Pin.
Output,
LVCMOS
4
Strobe edge set by RRFB control register.
SERIAL CONTROL BUS - I2C COMPATIBLE
Input,
Open Drain
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to VDDIO.
SCL
SDA
2
1
Input/Output,
Open Drain
Data line for the serial control bus communication
SDA requires an external pull-up resistor to VDDIO
.
I2C Mode select
Input, LVCMOS
w/ pull up
MODE
ID[x]
47
9
MODE = H -REQUIRED. The MODE pin must be set HIGH to allow I2C configuration
of the deserializer.
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 2
Input, analog
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB = H, Deserializer is enabled and is ON.
PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power
Down. Programmed control register data are NOT retained and reset to default
values.
Input, LVCMOS
w/ pull down
PDB
35
34
LOCK Status Output Pin.
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL control register. May be used as Link Status.
Output,
LVCMOS
LOCK
Reserved.
37, 38, 39, 43,
44, 46
Pin 46: This pin MUST be tied LOW.
Pin 37, 43, 44: Leave pin open.
Pins 38, 39: Route to test point or leave open if unused.
RES
NC
-
30, 31, 32, 33
No Connect
FPD-LINK II INTERFACE
Noninverting differential input. The interconnect must be AC Coupled with a 100 nF
capacitor.
RIN+
41
Input, CML
Inputt, CML
Inverting differential input. The interconnect must be AC Coupled with a 100 nF
capacitor.
RIN-
42
(1)
POWER AND GROUND
VDDSSCG
SSCG Power, 1.8V ±5%
Power supply must be connected regardless if SSCG function is in operation.
3
Power, Digital
Power, Digital
LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered
from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
VDDIO1/2/3
29, 20, 7
VDDD
17
36
40
45
Power, Digital Digital Core Power, 1.8V ±5%
Power, Analog Rx Analog Power, 1.8V ±5%
Power, Analog 1.8V ±5%
VDDR
VDDCML
VDDPLL
Power, Analog PLL Power, 1.8V ±5%
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
VSS
DAP
Ground, DAP the center of the WQFN package. Connected to the ground plane (GND) with at least
16 vias.
(1) See Power Up Requirements and PDB PIN.
Copyright © 2011–2014, Texas Instruments Incorporated
5
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
www.ti.com.cn
6 Specifications
(1) (2)
6.1 Absolute Maximum Ratings
PARAMETER
MIN
−0.3
−0.3
−0.3
−0.3
−0.3
MAX
+2.5
UNIT
V
Supply Voltage – VDDn (1.8V)
Supply Voltage – VDDIO
+4.0V
V
LVCMOS Input Voltage I/O Voltage
(VDDIO + 0.3V)
(VDD + 0.3V)
(VDD + 0.3V)
+150
V
CML Driver I/O Voltage (VDD
)
V
CML Receiver I/O Voltage (VDD
)
V
Junction Temperature
°C
°C/W
Maximum Package Power Dissipation Capacity
1/θJA above +25°
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional; the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
6.2 Handling Ratings
MIN
–65
-8
MAX
150
+8
UNIT
Tstg
Storage temperature range
Electrostatic discharge
°C
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
Machine Model (MM)
kV
V
V(ESD)
-1
+1
-250
-25
+250
+25
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
ESD Rating (IEC 61000-4-2)
RD = 330Ω, CS = 150pF
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
-10
-15
-10
+10
+15
+10
kV
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
ESD Rating (ISO10605)
RD = 330Ω, CS = 150/330pF
RD = 2KΩ, CS = 150/330pF
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
1.71
1.71
3.0
NOM
1.8
MAX
1.89
1.89
3.6
UNIT
V
Supply Voltage (VDDn
)
LVCMOS Supply Voltage (VDDIO) (1.8V)
LVCMOS Supply Voltage (VDDIO) (3.3V)
Supply Noise
1.8
V
3.3
V
VDDn (1.8V)
VDDIO (1.8V)
VDDIO (3.3V)
25
mVp-p
mVp-p
mVp-p
°C
25
50
Operating Free Air Temperature (TA)
PCLK Clock Frequency
-40
10
+25
+105
43
MHz
6
Copyright © 2011–2014, Texas Instruments Incorporated
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com.cn
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
6.4 Thermal Information(1)
DS90UR903Q
40L WQFN
DS90UR904Q
48L WQFN
THERMAL METRIC(2)
UNIT
RTA
40 PINS
31.9
18.5
8.1
RHS
48 PINS
30.0
11.1
6.9
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
0.1
ψJB
8.1
6.9
RθJC(bot)
3.5
2.4
(1) For soldering specifications, see SNOA549
(2) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics(1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, CONTROL INPUTS AND OUTPUTS)
VIH
VIL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Current
VDDIO = 3.0V to 3.6V
VDDIO = 3.0V to 3.6V
2.0
VDDIO
0.8
V
V
GND
VIN = 0V or 3.6V
VDDIO = 3.0V to 3.6V
-20
2.4
±1
+20
VDDIO
0.4
µA
V
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
VDDIO = 3.0V to 3.6V
IOH = -4 mA
VDDIO = 3.0V to 3.6V
IOL = +4 mA
GND
V
IOS
IOZ
Output Short Circuit Current
TRI-STATE Output Current
VOUT = 0V
-39
±1
mA
µA
PDB = 0V,
VOUT = 0V or VDD
-20
+20
LVCMOS DC SPECIFICATIONS 1.8V I/O (SER INPUTS, DES OUTPUTS, CONTROL INPUTS AND OUTPUTS)
VIH
VIL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Current
VDDIO = 1.71V to 1.89V
VDDIO = 1.71V to 1.89V
0.65 VDDIO
GND
VDDIO +0.3
0.35 VDDIO
V
V
VIN = 0V or 1.89V
VDDIO = 1.71V to 1.89V
-20
±1
+20
VDDIO
0.45
µA
V
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
VDDIO = 1.71V to 1.89V
IOH = −4 mA
VDDIO
0.45
-
VDDIO = 1.71V to 1.89V
IOL = +4 mA
GND
V
IOS
IOZ
Output Short Circuit Current
TRI-STATE Output Current
VOUT = 0V
-20
±1
mA
µA
PDB = 0V,
VOUT = 0V or VDD
-20
+20
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
Copyright © 2011–2014, Texas Instruments Incorporated
7
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
www.ti.com.cn
Electrical Characteristics(1) (2) (3)
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
|VOD
|
Output Differential Voltage
RT = 100Ω, Figure 5
268
340
1
412
50
mV
mV
ΔVOD
Output Differential Voltage Unbalance
Output Differential Offset Voltage
RL = 100Ω
VOS
RL = 100Ω
Figure 5
VDD (MIN)
VOD (MAX)
-
VDD (MAX)
VOD (MIN)
-
VDD - VOD
V
ΔVOS
IOS
Offset Voltage Unbalance
Output Short Circuit Current
RL = 100Ω
1
50
mV
mA
DOUT+/- = 0V
-27
RT
Differential Internal Termination Resistance Differential across DOUT+ and
DOUT-
80
100
120
+90
Ω
CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-)
VTH
VTL
VIN
Differential Threshold High Voltage
Differential Threshold Low Voltage
Differential Input Voltage Range
Input Current
Figure 7
mV
-90
RIN+ - RIN-
180
mV
µA
VIN = VDD or 0V,
VDD = 1.89V
IIN
-20
80
±1
+20
120
RT
Differential Internal Termination Resistance Differential across RIN+ and
RIN-
100
Ω
SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD
IDDT
Serializer (Tx)
RT = 100Ω
VDDn = 1.89V
VDDn Supply Current (includes load
current)
WORST
CASE pattern Default
Figure 2
PCLK = 43 MHz
62
55
2
90
Registers
mA
RT = 100Ω
RANDOM
PRBS-7
pattern
IDDIOT
Serializer (Tx)
VDDIO Supply Current (includes load
current)
RT = 100Ω
WORST
CASE pattern Default
VDDIO = 1.89V
PCLK = 43 MHz
5
Figure 2
Registers
mA
µA
VDDIO = 3.6V
PCLK = 43 MHz
Default
7
15
Registers
IDDTZ
Serializer (Tx) Supply Current Power-down
PDB = 0V; All VDDn = 1.89V
370
55
775
125
135
other
IDDIOTZ
VDDIO = 1.89V
LVCMOS
VDDIO = 3.6V
Inputs = 0V
65
8
Copyright © 2011–2014, Texas Instruments Incorporated
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com.cn
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
Electrical Characteristics(1) (2) (3)
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IDDR
Deserializer (Rx) VDDn Supply Current
(includes load current)
VDDn = 1.89V PCLK = 43 MHz
CL = 8 pF
WORST
SSCG[3:0] =
ON
60
96
CASE Pattern Default
Figure 2
Registers
VDDn = 1.89V
CL = 8 pF
RANDOM
PRBS-7
PCLK = 43 MHz
Default
Registers
53
Pattern
mA
IDDIOR
Deserializer (Rx) VDDIO Supply Current
(includes load current)
VDDIO = 1.89V PCLK = 43 MHz
CL = 8 pF
WORST
Default
Registers
21
49
32
83
CASE Pattern
Figure 2
VDDIO = 3.6V
CL = 8 pF
WORST
PCLK = 43 MHz
Default
Registers
CASE Pattern
IDDRZ
Deserializer (Rx) Supply Current Power-
down
PDB = 0V; All VDDn = 1.89V
42
8
400
40
other
IDDIORZ
VDDIO = 1.89V
LVCMOS
µA
VDDIO = 3.6V
Inputs = 0V
350
800
6.6 Recommended Serializer Timing for PCLK(1)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
10 MHz – 43 MHz
MIN
23.3
0.4T
0.4T
TYP
T
MAX
100
UNIT
ns
tTCP
Transmit Clock Period
tTCIH
tTCIL
tCLKT
Transmit Clock Input High Time
Transmit Clock Input Low Time
0.5T
0.5T
0.6T
0.6T
ns
ns
PCLK Input Transition Time
Figure 8
0.5
3
ns
fOSC
Internal oscillator clock source
25
MHz
(1) Recommended Input Timing Requirements are input specifications and not tested in production.
Copyright © 2011–2014, Texas Instruments Incorporated
9
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
www.ti.com.cn
6.7 Serial Control Bus AC Timing Specifications (SCL, SDA) - I2C Compliant (See Figure 1)
Over recommended supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RECOMMENDED INPUT TIMING REQUIREMENTS(1)
fSCL
SCL Clock Frequency
SCL Low Period
>0
4.7
4.0
100
kHz
µs
tLOW
tHIGH
fSCL = 100 kHz
SCL High Period
µs
Hold time for a start or a repeated start
condition
tHD:STA
tSU:STA
4.0
4.7
µs
µs
Set Up time for a start or a repeated
start condition
tHD:DAT
tSU:DAT
tSU:STO
tr
Data Hold Time
0
3.45
µs
ns
µs
ns
ns
pF
Data Set Up Time
250
4.0
Set Up Time for STOP Condition
SCL & SDA Rise Time
SCL & SDA Fall Time
Capacitive load for bus
1000
300
tf
Cb
400
SWITCHING CHARACTERISTICS(2)
tHD:DAT
tSU:DAT
tf
Data Hold Time
0
3.45
300
µs
ns
ns
Data Set Up Time
SCL & SDA Fall Time
250
(1) Recommended Input Timing Requirements are input specifications and not tested in production.
(2) Specification is ensured by design.
SDA
t
BUF
t
f
t
t
HD;STA
t
r
LOW
t
t
f
r
SCL
t
t
HD;STA
SU;STA
t
SU;STO
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
Figure 1. Serial Control Bus Timing
10
Copyright © 2011–2014, Texas Instruments Incorporated
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com.cn
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
6.8 Serial Control Bus DC Characteristics (SCL, SDA) - I2C Compliant
Over recommended supply and temperature ranges unless otherwise specified.
PARAMETER
Input High Level
TEST CONDITIONS
SDA and SCL
MIN
TYP
MAX
UNIT
VIH
VIL
0.7 x
VDDIO
VDDIO
V
Input Low Level Voltage
SDA and SCL
SDA and SCL
0.3 x
VDDIO
GND
V
VHY
IOZ
Input Hysteresis
>50
±1
mV
µA
TRI-STATE Output Current
PDB = 0V
VOUT = 0V or VDD
-20
-20
+20
+20
IIN
Input Current
SDA or SCL,
Vin = VDDIO or GND
±1
<5
µA
pF
CIN
Input Pin Capacitance
VOL
Low Level Output Voltage
SCL and SDA
VDDIO = 3.0V
IOL = 1.5mA
0.36
0.36
V
V
SCL and SDA
VDDIO = 1.71V
IOL = 1mA
Device Pin Name
Signal Pattern
T
PCLK
(RFB = H)
D
/R
IN OUT
Figure 2. “Worst Case” Test Pattern
80%
20%
80%
Vdiff
Vdiff = 0V
20%
t
t
LHT
HLT
Vdiff = (D
+) - (D
-)
OUT
OUT
Figure 3. Serializer CML Output Load and Transition Times
100 nF
D
OUT
+
50:
50:
SCOPE
BW 8 4.0 GHz
Z
Diff
= 100:
100:
D
OUT
-
100 nF
Figure 4. Serializer CML Output Load and Transition Times
Copyright © 2011–2014, Texas Instruments Incorporated
11
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
www.ti.com.cn
D
D
+
OUT
21
R
D
IN
L
-
OUT
PCLK
Figure 5. Serializer VOD DC Diagram
D
OUT
-
Single Ended
V
V
V
OD-
OD
OD+
V
D
OUT
+
OS
|
0V
Differential
V
OD+
0V
(D +)-(D )
OUT OUT-
V
OD-
Figure 6. Serializer VOD DC Diagram
RIN+
RIN+
RIN-
V
TH
V
CM
V
TL
V
V
IN
V
ID
V
IN
ID
RIN-
GND
Figure 7. Differential VTH/VTL Definition Diagram
V
DD
80%
80%
PCLK
20%
20%
0V
t
t
CLKT
CLKT
Figure 8. Serializer Input Clock Transition Times
12
Copyright © 2011–2014, Texas Instruments Incorporated
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com.cn
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
t
TCP
PCLK
DINn
V
DDIO
/2
V
/2
V
V
/2
DDIO
DDIO
t
t
DIH
DIS
DDIO
Setup
Hold
V
/2
V
/2
DDIO
DDIO
0V
Figure 9. Serializer Setup/Hold Times
VDDIO/2
PDB
PCLK
t
PLD
TRI-STATE
TRI-STATE
Output Active
D
±
OUT
Figure 10. Serializer Data Lock Time
SYMBOL N
VDDIO/2
SYMBOL N+1
SYMBOL N+2
SYMBOL N+3
D
IN
t
SD
PCLK
SYMBOL N-4
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
0V
DOUT+-
Figure 11. Serializer Delay
VDDIO/2
PDB
t
DDLT
R
IN±
LOCK
TRI-STATE
VDDIO/2
Figure 12. Deserializer Data Lock Time
80%
20%
80%
Deserializer
20%
8 pF
lumped
t
t
CHL
CLH
Figure 13. Deserializer LVCMOS Output Load and Transition Times
Copyright © 2011–2014, Texas Instruments Incorporated
13
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
www.ti.com.cn
SYMBOL N
SYMBOL N + 1
SYMBOL N + 2
SYMBOL N + 3
SYMBOL N + 3
RIN±
0V
t
DD
PCLK
VDDIO/2
SYMBOL N - 3
SYMBOL N - 2
SYMBOL N - 1
SYMBOL N
SYMBOL N+1
ROUTn
Figure 14. Deserializer Delay
t
RCP
V
DDIO
PCLK
1/2 V
DDIO
1/2 V
DDIO
0V
V
DDIO
ROUT[n],
VS, HS
1/2 V
DDIO
1/2 V
DDIO
0V
t
t
ROH
ROS
Figure 15. Deserializer Output Setup/Hold Times
Ideal Data
Bit End
Sampling
Window
Ideal Data Bit
Beginning
V
TH
0V
RxIN_TOL
Left
RxIN_TOL
Right
V
TL
Ideal Center Position (t /2)
BIT
t
(1 UI)
BIT
t
= RxIN_TOL (Left + Right)
RJIT
Sampling Window = 1 UI - t
RJIT
Figure 16. Receiver Input Jitter Tolerance
Frequency
FPCLK+
FPCLK
FPCLK-
fdev (max)
fdev
fdev (min)
Time
1 / fmod
Figure 17. Spread Spectrum Clock Output Profile
14
Copyright © 2011–2014, Texas Instruments Incorporated
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com.cn
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
6.9 Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tLHT
tHLT
CML Low-to-High Transition
Time
RL = 100Ω
Figure 3
150
330
ps
CML High-to-Low Transition
Time
RL = 100Ω
Figure 3
150
330
ps
tDIS
tDIH
tPLD
tSD
Data Input Setup to PCLK
Data Input Hold from PCLK
Serializer PLL Lock Time
Serializer Delay
Serializer Data Inputs
Figure 9
2.0
2.0
ns
ns
RL = 100Ω(1) (2)
1
2
ms
RT = 100Ω
PCLK = 10–43 MHz
Register 0x03h b[0] (TRFB = 1)
Figure 11
6.386T
+ 5
6.386T
+ 12
6.386T
+ 19.7
ns
tJIND
Serializer Output Deterministic
Jitter
Serializer output intrinsic deterministic
jitter . Measured (cycle-cycle) with
PRBS-7 test pattern
0.13
0.04
UI
UI
PCLK = 43 MHz(3) (4)
tJINR
Serializer Output Random Jitter
Serializer output intrinsic random jitter
(cycle-cycle). Alternating-1,0 pattern.
PCLK = 43 MHz(3) (4)
tJINT
Peak-to-peak Serializer Output
Jitter
Serializer output peak-to-peak jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measured (cycle-cycle) with
PRBS-7 test pattern.
0.396
UI
PCLK = 43 MHz(3) (4)
λSTXBW
Serializer Jitter Transfer Function PCLK = 43 MHz
-3 dB Bandwidth
Default Registers
Figure 18
1.90
0.944
500
MHz
dB
(3)
δSTX
Serializer Jitter Transfer Function PCLK = 43 MHz
(Peaking)
Default Registers
(3)
Figure 18
δSTXf
Serializer Jitter Transfer Function PCLK = 43 MHz
(Peaking Frequency)
Default Registers
kHz
(3)
Figure 18
(1) tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
(2) Specification is ensured by design.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
(4) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
Copyright © 2011–2014, Texas Instruments Incorporated
15
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
www.ti.com.cn
6.10 Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
Receiver Output Clock Period
PCLK Duty Cycle
TEST CONDITIONS
PIN/FREQ.
PCLK
PCLK
MIN
TYP
MAX
UNIT
tRCP
tPDC
tRCP = tTCP
23.3
T
100
ns
Default Registers
SSCG[3:0] = OFF
45
50
55
%
LVCMOS Low-to-High Transition
Time
VDDIO: 1.71V to 1.89V or PCLK
3.0 to 3.6V,
tCLH
tCHL
1.3
2.0
2.8
2.8
3.3
3.3
CL = 8 pF (lumped load)
Default Registers
ns
LVCMOS High-to-Low Transition
Time
1.3
1.6
2.0
2.4
(1)
Figure 13
LVCMOS Low-to-High Transition
Time
VDDIO: 1.71V to 1.89V or Deserializer ROUTn
tCLH
tCHL
3.0 to 3.6V,
Data Outputs
CL = 8 pF (lumped load)
Default Registers
ns
LVCMOS High-to-Low Transition
Time
1.6
2.4
(1)
Figure 13
tROS
tROH
ROUT Setup Data to PCLK
ROUT Hold Data to PCLK
VDDIO: 1.71V to 1.89V or Deserializer ROUTn
0.38T
0.38T
0.5T
0.5T
3.0V to 3.6V,
Data Outputs
ns
ns
CL = 8 pF (lumped load)
Default Registers
Default Registers
Register 0x03h b[0]
(RRFB = 1)
10 MHz–43 MHz
4.571T
+ 8
4.571T
+ 12
4.571T
+ 16
tDD
Deserializer Delay
Figure 14
(2)
tDDLT
tRJIT
Deserializer Data Lock Time
Receiver Input Jitter Tolerance
Figure 12
10 MHz–43 MHz
43 MHz
10
ms
UI
(3)
Figure 16, Figure 19
0.53
(4)
tRCJ
Receiver Clock Jitter
10 MHz
300
120
425
320
320
300
550
250
600
480
500
500
PCLK
ps
ps
ps
SSCG[3:0] = OFF(1) (5)
43 MHz
tDPJ
Deserializer Period Jitter
10 MHz
PCLK
SSCG[3:0] = OFF
(1) (6)
43 MHz
tDCCJ
Deserializer Cycle-to-Cycle Clock
Jitter
10 MHz
PCLK
SSCG[3:0] = OFF(1) (7)
43 MHz
fdev
Spread Spectrum Clocking
Deviation Frequency
LVCMOS Output Bus
SSC[3:0] = ON
Figure 17
20 MHz–43 MHz
±0.5% to
±2.0%
%
fmod
Spread Spectrum Clocking
Modulation Frequency
20 MHz–43 MHz
9 kHz to
66 kHz
kHz
(1) Specification is ensured by characterization and is not tested in production.
(2) tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
(3) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
(4) tRJIT max (0.61UI) is limited by instrumentation and actual tRJIT of in-band jitter at low frequency (<2 MHz) is greater 1 UI.
(5) tDCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
(6) tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
(7) tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
16
Copyright © 2011–2014, Texas Instruments Incorporated
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com.cn
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
6.11 Typical Characteristics
2
0
0.62
0.61
-2
-4
-6
0.60
0.59
0.58
-8
0.57
0.56
-10
-12
-14
0.55
0.54
0.53
0.52
-16
-18
1.0E+06
JITTER FREQUENCY (Hz)
1.0E+04
1.0E+05
1.0E+07
1.0E+04
1.0E+05
1.0E+06
1.0E+07
MODULATION FREQUENCY (Hz)
Figure 19. Typical Deserializer Input Jitter
Tolerance Curve at 43 MHz
Figure 18. Typical Serializer Jitter
Transfer Function Curve at 43 MHz
Copyright © 2011–2014, Texas Instruments Incorporated
17
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
www.ti.com.cn
7 Detailed Description
7.1 Overview
The DS90UR903Q/904Q FPD-Link II chipset is intended for video display applications. The Serializer/
Deserializer chipset operates from a 10 MHz to 43 MHz pixel clock frequency. The DS90UR903Q transforms a
21-bit wide parallel LVCMOS data bus into a single high-speed differential pair. The high-speed serial bit stream
contains an embedded clock and DC-balance information which enhances signal quality to support AC coupling.
The DS90UR904Q receives the single serial data stream and converts it back into a 21-bit wide parallel data
bus.
7.2 Functional Block Diagram
7.2.1 Typical Application Diagram
FPD-Link II
Parallel
Data Out
18+3
Parallel
Data In
18+3
Graphics
Controller
--
Display
Module
Video
DS90UR903Q
DS90UR904Q
Processor
SCL
SDA
SCL
SDA
Serializer
Deserializer
Figure 20. Typical Application Circuit
7.2.2 Block Diagrams
R
T
R
T
R
T
R
T
DOUT+
DOUT-
21
RIN+
RIN-
R/G/B[5:0],
HS,VS,DE
21
R/G/B[5:0],
HS,VS,DE
PCLK
Clock
Gen
PCLK
PLL
LOCK
Clock
Gen
CDR
Timing
and
Control
PDB
PDB
MODE
Timing
and
Control
MODE
SDA
SCL
ID[x]
SDA
SCL
ID[x]
DS90UR903Q - SERIALIZER
DS90UR904Q - DESERIALIZER
Figure 21. Block Diagram
18
Copyright © 2011–2014, Texas Instruments Incorporated
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com.cn
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
DS90UR903Q
Serializer
DS90UR904Q
Deserializer
FPD-Link II
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
Timing
Controller
PCLK
Graphics
Controller
---
PLL
PCLK
Video
LCD
Display
Processor
PDB
MODE
PDB
MODE
Config.
Config.
PC
SDA
SCL
SDA
SCL
PC
Figure 22. Application Block Diagram
7.3 Feature Description
7.3.1 Serial Frame Format
The DS90UR903Q/904Q chipset will transmit and receive a pixel of data in the following format:
Bit 0 to Bit 20
Figure 23. Serial Bitstream for 28-bit Symbol
The High Speed Serial Channel is a 28-bit symbol composed of 21 bits of data containing video data & control
information transmitted from Serializer to Deserializer. CLK1 and CLK0 represent the embedded clock in the
serial stream. CLK1 is always HIGH and CLK0 is always LOW. This data payload is optimized for signal
transmission over an AC coupled link. Data is randomized, balanced and scrambled.
7.3.2 Signal Quality Enhancers
7.3.2.1 Des - Receiver Input Equalization (EQ)
The receiver inputs provided input equalization filter in order to compensate for loss from the media. The level of
equalization is controlled via register setting.
7.3.3 Emi Reduction
7.3.3.1 Des - Receiver Staggered Output
The Receiver staggered outputs allows for outputs to switch in a random distribution of transitions within a
defined window. Outputs transitions are distributed randomly. This minimizes the number of outputs switching
simultaneously and helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall
EMI.
7.3.3.2 Des Spread Spectrum Clocking
The DS90UR904Q parallel data and clock outputs have programmable SSCG ranges from 9 kHz–66 kHz and
±0.5%–±2% from 20 MHz to 43 MHz. The modulation rate and modulation frequency variation of output spread is
controlled through the SSC control registers.
Copyright © 2011–2014, Texas Instruments Incorporated
19
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
www.ti.com.cn
7.4 Device Functional Modes
7.4.1 LVCMOS VDDIO Option
1.8V or 3.3V SER Inputs and DES Outputs are user selectable to provide compatibility with 1.8V and 3.3V
system interfaces.
7.4.2 Powerdown
The SER has a PDB input pin to ENABLE or Powerdown the device. The modes can be controlled by the host
and is used to disable the Link to save power when the remote device is not operational. An auto mode is also
available. In this mode, the PDB pin is tied High and the SER switches over to an internal oscillator when the
PCLK stops or not present. When a PCLK starts again, the SER will then lock to the valid input PCLK and
transmits the data to the DES. In powerdown mode, the high-speed driver outputs are static (High).
The DES has a PDB input pin to ENABLE or Powerdown the device. This pin can be controlled by the system
and is used to disable the DES to save power. An auto mode is also available. In this mode, the PDB pin is tied
High and the DES will enter powerdown when the serial stream stops. When the serial stream starts up again,
the DES will lock to the input stream and assert the LOCK pin and output valid data. In powerdown mode, the
Data and PCLK outputs are set by the OSS_SEL control register.
7.4.3 Pixel Clock Edge Select (TRFB/RRFB)
The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge
that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register
is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the
data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0,
data is strobed on the Falling edge of the PCLK.
PCLK
DIN/
ROUT
TRFB/RRFB: 0
TRFB/RRFB: 1
Figure 24. Programmable PCLK Strobe Select
7.5 Programming
7.5.1 Description of Serial Control Bus
An integrated I2C slave controller is embedded in each of the DS90UR903Q Serializer and DS90UR904Q
Deserializer. It must be used to access and program the extra features embedded within the configuration
registers. Refer to Table 3 and Table 4 for details of control registers.
7.5.2 ID[X] Address Decoder
The ID[x] pin is used to decode and set the physical slave address of the Serializer/Deserializer (I2C only) to
allow up to six devices on the bus using only a single pin. The pin sets one of six possible addresses for each
Serializer/Deserializer device. The pin must be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor and a
pull down resistor (RID) of the recommended value to set the physical device address. The recommended
maximum resistor tolerance is 0.1% worst case (0.2% total tolerance).
20
Copyright © 2011–2014, Texas Instruments Incorporated
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com.cn
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
Programming (continued)
1.8V
10k
V
DDIO
ID[x]
RPU
RPU
SER
R
ID
HOST
or
DES
SCL
SDA
SCL
SDA
To other
Devices
Figure 25. Serial Control Bus Connection
Table 1. ID[x] Resistor Value – DS90UR903Q
ID[x] RESISTOR VALUE - DS90UR903Q Ser
RESISTOR RID Ω (±0.1%)
ADDRESS 7'b(1)
ADDRESS 8'b 0 APPENDED (WRITE)
0
7b' 101 1000 (h'58)
8b' 1011 0000 (h'B0)
GND
2.0k
4.7k
7b' 101 1001 (h'59)
7b' 101 1010 (h'5A)
7b' 101 1011 (h'5B)
7b' 101 1100 (h'5C)
7b' 101 1110 (h'5E)
8b' 1011 0010 (h'B2)
8b' 1011 0100 (h'B4)
8b' 1011 0110 (h'B6)
8b' 1011 1000 (h'B8)
8b' 1011 1100 (h'BC)
8.2k
12.1k
39.0k
(1) Specification is ensured by design.
Table 2. ID[x] Resistor Value – DS90UR904Q
ID[x] RESISTOR VALUE - DS90UR904Q Des
RESISTOR RID Ω (±0.1%)
ADDRESS 7'b(1)
ADDRESS 8'b 0 APPENDED (WRITE)
0
7b' 110 0000 (h'60)
8b' 1100 0000 (h'C0)
GND
2.0k
4.7k
7b' 110 0001 (h'61)
7b' 110 0010 (h'62)
7b' 110 0011 (h'63)
7b' 110 0100 (h'64)
7b' 110 0110 (h'66)
8b' 1100 0010 (h'C2)
8b' 1100 0100 (h'C4)
8b' 1101 0110 (h'C6)
8b' 1101 1000 (h'C8)
8b' 1100 1100 (h'CC)
8.2k
12.1k
39.0k
(1) Specification is ensured by design.
Copyright © 2011–2014, Texas Instruments Incorporated
21
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
www.ti.com.cn
7.6 Register Maps
Table 3. DS90UR903Q Control Registers
ADDR
(HEX)
NAME
BITS
7:1
0
FIELD
DEVICE ID
R/W
DEFAULT
DESCRIPTION
7-bit address of Serializer; 0x58'h
(1011_000X'b) default
0
I2C Device ID
RW
0xB0'h
0: Device ID is from ID[x]
SER ID SEL
1: Register I2C Device ID overrides ID[x]
7:3
2
RESERVED
RESERVED
0x00'h
Reserved
Reserved
RW
RW
0
0
DIGITAL
RESET0
1: Resets the device to default register values. Does not
1
2
Reset
1
0
self clear affect device I2C Bus or Device ID
0
1: Digital Reset, retains all register values
DIGITAL RESET1
RW
self clear
Reserved
Reserved
7:0
7:6
RESERVED
RESERVED
0x20'h
11'b
Reserved
Reserved
Auto VDDIO detect
Allows manual setting of VDDIO by register.
0: Disable
1: Enable (auto detect mode)
VDDIO Control
VDDIO Mode
5
4
VDDIO CONTOL
VDDIO MODE
RW
1
1
VDDIO voltage set
Only used when VDDIOCONTROL = 0
0: 1.8V
1: 3.3V
RW
RW
RESERVED
RESERVED
3
2
RESERVED
RESERVED
1
0
Reserved
Reserved
3
Switch over to internal 25 MHz Oscillator clock in the
absence of PCLK
0: Disable
1: Enable
PCLK_AUTO
1
PCLK_AUTO
RW
RW
1
Pixel Clock Edge Select:
0: Parallel Interface Data is strobed on the Falling Clock
TRFB 0 TRFB RW 1 Edge.
TRFB
0
TRFB
1
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
4
5
6
7
8
9
A
B
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:3
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0x80'h
0x40'h
0xC0'h
0x00'h
0x00'h
0x01'h
0x00'h
0x00'h
0x00'h
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
1: Valid PCLK detected
0: Valid PCLK not detected
PCLK Detect
2
PCLK DETECT
R
R
0
C
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
3
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
D
E
7:0
7:0
7:0
7:0
7:0
7:0
0x11'h
0x01'h
0x03'h
0x03'h
0x03'h
0x03'h
F
10
11
12
22
Copyright © 2011–2014, Texas Instruments Incorporated
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com.cn
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
Register Maps (continued)
Table 3. DS90UR903Q Control Registers (continued)
ADDR
(HEX)
NAME
BITS
FIELD
R/W
DEFAULT
DESCRIPTION
GPCR[7]
GPCR[6]
GPCR[5]
GPCR[4]
GPCR[3]
GPCR[2]
GPCR[1]
GPCR[0]
General Purpose
Control Reg
0: LOW
1: HIGH
13
7:0
RW
0x00'h
Table 4. DS90UR904Q Control Registers
ADDR
(HEX)
NAME
BITS
7:1
0
FIELD
R/W
DEFAULT
DESCRIPTION
RW
0xC0'h
7-bit address of Deserializer;
DEVICE ID
0x60h
(1100_000X) default
0
I2C Device ID
0: Device ID is from ID[x]
DES ID SEL
1: Register I2C Device ID overrides ID[x]
7:3
2
RESERVED
RESERVED
0x00'h
Reserved
RW
RW
0
0
Reserved
1: Resets the device to default register values. Does not
1
Reset
1
DIGITALRESET0
self clear affect device I2C Bus or Device ID
0
1: Digital Reset, retains all register values
0
7:6
5
DIGITALRESET1
RESERVED
RW
self clear
RESERVED
Auto Clock
00'b
Reserved
1: Output PCLK or Internal 25 MHz Oscillator clock
0: Only PCLK when valid PCLK present
AUTO_CLOCK
RW
RW
0
Output Sleep State Select
0: Outputs = TRI-STATE, when LOCK = L
1: Outputs = LOW , when LOCK = L
OSS Select
4
OSS_SEL
0
SSCG Select
0000: Normal Operation, SSCG OFF (default)
0001: fmod (kHz) PCLK/2168, fdev ±0.50%
0010: fmod (kHz) PCLK/2168, fdev ±1.00%
0011: fmod (kHz) PCLK/2168, fdev ±1.50%
0100: fmod (kHz) PCLK/2168, fdev ±2.00%
0101: fmod (kHz) PCLK/1300, fdev ±0.50%
0110: fmod (kHz) PCLK/1300, fdev ±1.00%
0111: fmod (kHz) PCLK/1300, fdev ±1.50%
1000: fmod (kHz) PCLK/1300, fdev ±2.00%
1001: fmod (kHz) PCLK/868, fdev ±0.50%
1010: fmod (kHz) PCLK/868, fdev ±1.00%
1011: fmod (kHz) PCLK/868, fdev ±1.50%
1100: fmod (kHz) PCLK/868, fdev ±2.00%
1101: fmod (kHz) PCLK/650, fdev ±0.50%
1110: fmod (kHz) PCLK/650, fdev ±1.00%
1111: fmod (kHz) PCLK/650, fdev ±1.50%
2
SSCG
3:0
SSCG
0000'b
Copyright © 2011–2014, Texas Instruments Incorporated
23
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
www.ti.com.cn
Table 4. DS90UR904Q Control Registers (continued)
ADDR
(HEX)
NAME
BITS
FIELD
R/W
DEFAULT
DESCRIPTION
RESERVED
7:6
RESERVED
11'b
Reserved
Auto voltage control
0: Disable
1: Enable (auto detect mode)
VDDIO Control
VDDIO Mode
5
4
VDDIO CONTROL
VDDIO MODE
RW
RW
1
0
VDDIO voltage set
0: 1.8V
1: 3.3V
3
RESERVED
RESERVED
RESERVED
3
2
1
RESERVED
RESERVED
RESERVED
RW
RW
1
0
0
Reserved
Reserved
Reserved
Pixel Clock Edge Select
0: Parallel Interface Data is strobed on the Falling Clock
RRFB
0
RRFB
RW
RW
1
Edge
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
EQ Gain
00'h = ~0.0 dB
01'h = ~4.5 dB
03'h = ~6.5 dB
07'h = ~7.5 dB
0F'h = ~8.0 dB
1F'h = ~11.0 dB
3F'h = ~12.5 dB
FF'h = ~14.0 dB
4
EQ Control
7:0
EQ
0x00'h
5
6
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
7:0
7
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0x00'h
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6:4
3:0
7:0
7:0
7:0
7:0
7:0
7:0
7:3
2
RW
RW
RW
RW
000'b
1111'b
0xB0'h
0x00'h
0x00'h
0x01'h
0x00'h
0x00'h
0x00'h
0
7
8:17
18
19
1A
1B
Signal Detect
Status
0: Active signal not detected
1: Active signal detected
1C
1
0
R
R
0
0
0: CDR/PLL Unlocked
1: CDR/PLL Locked
LOCK Pin Status
1D
1E
1F
20
21
22
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7:0
7:0
7:0
7:0
7:0
7:0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0x17'h
0x07'h
0x01'h
0x01'h
0x01'h
0x01'h
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GPCR[7]
GPCR[6]
GPCR[5]
GPCR[4]
GPCR[3]
GPCR[2]
GPCR[1]
GPCR[0]
General Purpose
Control Reg
0: LOW
1: HIGH
23
7:0
RW
0x00'h
24
Copyright © 2011–2014, Texas Instruments Incorporated
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com.cn
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
Table 4. DS90UR904Q Control Registers (continued)
ADDR
(HEX)
NAME
BITS
FIELD
R/W
DEFAULT
DESCRIPTION
24
25
RESERVED
RESERVED
0
RESERVED
RESERVED
RESERVED
RESERVED
RW
R
0
0x00'h
00'b
0
Reserved
Reserved
Reserved
Reserved
7:0
7:6
5:0
RW
RW
26
RESERVED
Copyright © 2011–2014, Texas Instruments Incorporated
25
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
www.ti.com.cn
8 Application and Implementation
8.1 Application Information
The DS90UR903Q/904Q chipset is intended for interface between a host (graphics processor) and a Display. It
supports a 21 bit parallel video bus for 18-bit color depth (RGB666) display format. In a RGB666 configuration,
18 color bits (R[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are supported
across the serial link.
The DS90UR903Q Serializer accepts a 21-bit parallel data bus. The parallel data is converted into a single
differential link. The DS90UR904Q Deserializer extracts the clock/control information from the incoming data
stream and reconstructs the 21-bit parallel data.
Camera applications are also supported by the DS90UR903Q/904Q chipset. The host controller/processsor is
connected to the deserializer, while the CMOS image sensor provides data to the serializer.
8.2 Typical Applications
DS90UR903Q
Serializer
DS90UR904Q
Deserializer
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
FPD-Link II
Graphics
Controller
---
Timing
Controller
LCD Display
PCLK
PCLK
Video
Processor
SDA
SCL
SDA
SCL
PC
PC
Config
Confg
Figure 26. Typical Display System Diagram
DS90UR903Q
Serializer
DS90UR904Q
Deserializer
ROUT[20:0]
PCLK
DIN[20:0]
PCLK
Host
--
FPGA
--
CMOS
Image
Video
Processor
Sensor
SDA
SCL
SDA
SCL
Config
Config
Figure 27. Typical Camera System Diagram
8.2.1 Design Requirements
For the typical design applications, use the following as input parameters.
Table 5. Design Parameters
Design Parameter
Example Value
1.8 V or 3.3 V
1.8 V
VDDIO
VDDn
AC Coupling Capacitor for DOUT± and RIN±
PCLK Frequency
100 nF
43 MHz
26
Copyright © 2011–2014, Texas Instruments Incorporated
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com.cn
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
8.2.2 Detailed Design Procedure
8.2.2.1 Typical Application Connection
Figure 28 shows a typical connection of the DS90UR903Q Serializer for an 18-bit application. The CML outputs
require 0.1 μF AC coupling capacitors to the line. The line driver includes internal termination. Bypass capacitors
are placed near the power supply Terminals. System GPO (General Purpose Output) signals control the PDB
and MODE Terminals. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO Terminal is
connected also to the 1.8V rail. The optional Serial Bus control is used in this example, thus SCL and SDA are
connected to the system and the ID[x] Terminal is connected to a resistor divider.
DS90UR903Q (SER)
1.8V
VDDIO
VDDT
VDDIO
C4
C3
FB2
FB3
FB1
C12
C8
C13
C9
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
VDDPLL
VDDCML
VDDD
C10
C11
C5
C6
C7
FB4
FB5
DIN7
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
LVCMOS
Parallel
Bus
C1
C2
Serial
DOUT+
DOUT-
DIN14
DIN15
DIN16
DIN17
DIN18
FPD-Link II
Interface
1.8V
DIN19
DIN20
PCLK
10 k:
LVCMOS
Control
Interface
ID[X]
MODE
PDB
RID
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C9 = 0.1 PF
C10 - C13 = 4.7 PF
C14 - C15 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB7: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
VDDIO
RPU
RPU
C15
I2C
SCL
SDA
Bus
FB6
Interface
RES
DAP (GND)
FB7
C14
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Optional
Optional
Figure 28. DS90UR903Q Typical Connection Diagram — Pin Control
40-Pin WQFN (RTA Package)
Figure 29 shows a typical connection of the DS90UR904Q Deserializer for an 18-bit application. The CML inputs
utilize 0.1 μF coupling capacitors to the line and the receiver provides internal termination. Bypass capacitors are
placed near the power supply Terminals. System GPO (General Purpose Output) signals control the PDB and
the MODE Terminals. The interface to the target display is with 3.3V LVCMOS levels, thus the VDDIO Terminal
is connected to the 3.3 V rail. The optional Serial Bus control is used in this example, thus SCL and SDA are
connected to the system and the ID[x] Terminal is connected to a resistor divider. LOCK is monitored by a
system GPI (General Purpose Input).
Copyright © 2011–2014, Texas Instruments Incorporated
27
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
www.ti.com.cn
DS90UR904Q (DES)
1.8V
VDDIO
VDDD
VDDIO1
VDDIO2
VDDIO3
FB1
C13
C11
C8
C12 C14
FB6
C3
C4
C5
VDDR
C9
FB2
FB3
FB4
VDDSSCG
VDDPLL
VDDCML
C10
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
C15
C6
C7
FB5
C16
C1
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
ROUT12
ROUT13
Serial
RIN+
RIN-
LVCMOS
Parallel
Bus
FPD-Link II
Interface
C2
ROUT14
ROUT15
ROUT16
ROUT17
ROUT18
ROUT19
ROUT20
TP_A
TP_B
RES_PIN38
RES_PIN39
LVCMOS
Control
Interface
MODE
PDB
PCLK
VDDIO
RPU
RPU
C18
I2C
Bus
Interface
SCL
SDA
FB7
LOCK
ID[X]
1.8V
FB8
C17
Optional
Optional
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C12 = 0.1 PF
C13 - C16 = 4.7 PF
C17 - C18 = >100 pF
RPU = 1 k: to 4.7 k:
10 k:
RES_PIN46
DAP (GND)
RID
RID (see ID[x] Resistor Value Table)
FB1 - FB8: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Figure 29. DS90UR904Q Typical Connection Diagram — Pin Control
48-Pin WQFN (RHS Package)
28
Copyright © 2011–2014, Texas Instruments Incorporated
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com.cn
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
8.2.2.2 AC Coupling
The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme.
External AC coupling capacitors must be placed in series in the FPD-Link II signal path as illustrated in
Figure 30.
D
+
OUT
R
+
IN
D
R
D
-
R
IN
-
OUT
Figure 30. AC-Coupled Connection
For high-speed FPD-Link II transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s require a 100
nF AC coupling capacitors to the line.
8.2.2.3 Power Up Requirements and PDB PIN
When power is applied, the VDDIO supply needs to reach the expected operating voltage (1.8V or 3.3V) before
the other supplies (VDDn) begin to ramp. It is also required to delay and release the PDB input signal after VDD
(VDDn and VDDIO) power supplies have settled to the recommended operating voltages. A external RC network
can be connected to the PDB pin to ensure PDB arrives after all the VDD have stabilized.
1.8V OR 3.3V
1.8V
VDDIO
VDD_CORE,
All other 1.8V Supplies
1.8V OR 3.3V
PDB
Figure 31. Power Up Sequence
8.2.2.4 Transmission Media
The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and
signal quality requirements. The Ser/Des employ internal termination providing a clean signaling environment.
The interconnect for FPD-Link II interface should present a differential impedance of 100 Ohms. Use of cables
and connectors that have matched differential impedance will minimize impedance discontinuities. Shielded or
un-shielded cables may be used depending upon the noise environment and application requirements. The
chipset's optimum cable drive performance is achieved at 43 MHz at 10 meters length. The maximum signaling
rate increases as the cable length decreases. Therefore, the chipset supports 50 MHz at shorter distances. Other
cable parameters that may limit the cable's performance boundaries are: cable attenuation, near-end crosstalk
and pair-to-pair skew.
For obtaining optimal performance, we recommend:
•
•
•
•
Use Shielded Twisted Pair (STP) cable
100Ω differential impedance and 24 AWG (or lower AWG) cable
Low skew, impedance matched
Ground and/or terminate unused conductors
Figure 32 shows the Typical Performance Characteristics demonstrating various lengths and data rates using
Rosenberger HSD and Leoni DACAR 538 Cable.
Copyright © 2011–2014, Texas Instruments Incorporated
29
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
www.ti.com.cn
70
60
50
40
30
20
10
0
1960
1680
1400
1120
840
DS90UR903Q/904Q
560
280
0
0
5
15
CABLE LENGTH (m)
20
25
10
*Note: Equalization is enabled for cable lengths greater than 7 meters
Figure 32. Rosenberger HSD & Leoni DACAR 538 Cable Performance
8.2.2.5 Serial Interconnect Guidelines
For full details, see the Channel-Link PCB and Interconnect Design-In Guidelines (literature number SNLA008)
and the Transmission Line RAPIDESIGNER Operation and Applications Guide (literature number SNLA035).
•
•
Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
–
–
–
S = space between the pair
2S = space between pairs
3S = space to LVCMOS signal
•
•
•
•
Minimize the number of Vias
Use differential connectors when operating above 500Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual (literature number SNLA187), which is
available in PDF format from the TI LVDS & CML Solutions web site.
8.2.2.6 Application Curves
Time (200 ps/DIV)
Time (4 ns/DIV)
Figure 33. Serializer Eye Diagram at 1.2 Gbps Line Rate
(43MHz Pixel Clock)
Figure 34. Serializer CML Output with 43MHz TX Pixel
Clock
30
Copyright © 2011–2014, Texas Instruments Incorporated
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com.cn
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
9 Power Supply Recommendations
These devices are designed to operate from an input core voltage supply of 1.8V. Some devices provide
separate power and ground Terminals for different portions of the circuit. This is done to isolate switching noise
effects between different sections of the circuit. Separate planes on the PCB are typically not required. Terminal
Description tables typically provide guidance on which circuit blocks are connected to which power Terminal
pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs.
Copyright © 2011–2014, Texas Instruments Incorporated
31
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
Circuit board layout and stack-up for the Ser/Des devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise
effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In
some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the
differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential
lines of 100 Ohms are typically recommended for differential interconnect. The closely coupled lines help to
ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled
lines will also radiate less.
Information on the LLP style package is provided in the AN-1187 Leadless Leadframe Package (LLP) Application
Report (literature number SNOA401).
10.2 Layout Example
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the LLP package is highly recommended to improve
board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:
32
Copyright © 2011–2014, Texas Instruments Incorporated
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com.cn
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
Layout Example (continued)
Figure 35. No Pullback LLP, Single Row Reference Diagram
Table 6. No Pullback LLP Stencil Aperture Summary for DS90UR903Q-Q1 and DS90UR904Q-Q1
Gap
Stencil
DAP
Aperture
(mm)
Number of
DAP
Aperture
Openings
Between
DAP
Aperture
(Dim A
mm)
PCB I/O
Pad Size
(mm)
PCB
Pitch
(mm)
Stencil I/O
Aperture
(mm)
Pin
Count
PCB DAP
size(mm)
Device
MKT Dwg
DS90UR903Q-Q1
DS90UR904Q-Q1
40
48
SNA40A
SNA48A
0.25 x 0.6
0.25 x 0.6
0.5
0.5
4.6 x 4.6
5.1 x 5.1
0.25 x 0.7
0.25 x 0.7
1.0 x 1.0
1.1 x 1.1
16
16
0.2
0.2
Figure 36. 48-Pin WQFN Stencil Example of Via and Opening Placement
The following PCB layout examples are derived from the layout design of the DS90UB903Q-Q1 and
DS90UB904Q-Q1 in the SERDESUB-21USB Evaluation Module User's Guide ( SNLU101). These graphics and
additional layout description are used to demonstrate both proper routing and proper solder techniques when
designing in the Ser/Des pair.
Copyright © 2011–2014, Texas Instruments Incorporated
33
DS90UR903Q-Q1, DS90UR904Q-Q1
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
www.ti.com.cn
Figure 37. DS90UR903Q-Q1 Serializer Example Layout
Figure 38. DS90UR904Q-Q1 Deserializer Example Layout
34
版权 © 2011–2014, Texas Instruments Incorporated
DS90UR903Q-Q1, DS90UR904Q-Q1
www.ti.com.cn
ZHCSB31C –AUGUST 2011–REVISED JUNE 2014
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
相关文档如下：
•
•
•
•
•
•
《焊接规范应用报告》，SNOA549
《IC 封装热指标应用报告》，SPRA953
《通道链路 PCB 和互连设计指南》，SNLA008
《传输线路 RAPIDESIGNER 操作和应用指南》，SNLA035
《无引线框架封装 (LLP) 应用报告》，SNOA401
《LVDS 所有者手册》，SNLA187
11.2 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 7. 相关链接
部件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
DS90UR903Q-Q1
DS90UR904Q-Q1
11.3 商标
All trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2011–2014, Texas Instruments Incorporated
35
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90UR903QSQ/NOPB
DS90UR903QSQE/NOPB
DS90UR903QSQX/NOPB
DS90UR904QSQ/NOPB
DS90UR904QSQE/NOPB
DS90UR904QSQX/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RTA
RTA
RTA
RHS
RHS
RHS
40
40
40
48
48
48
1000 RoHS & Green
250 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
UR903QSQ
SN
SN
SN
SN
SN
UR903QSQ
UR903QSQ
UR904QSQ
UR904QSQ
UR904QSQ
2500 RoHS & Green
1000 RoHS & Green
250
RoHS & Green
2500 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90UR903QSQ/NOPB WQFN
DS90UR903QSQE/NOPB WQFN
DS90UR903QSQX/NOPB WQFN
DS90UR904QSQ/NOPB WQFN
DS90UR904QSQE/NOPB WQFN
DS90UR904QSQX/NOPB WQFN
RTA
RTA
RTA
RHS
RHS
RHS
40
40
40
48
48
48
1000
250
330.0
178.0
330.0
330.0
178.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
6.3
6.3
6.3
7.3
7.3
7.3
6.3
6.3
6.3
7.3
7.3
7.3
1.5
1.5
1.5
1.3
1.3
1.3
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
2500
1000
250
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90UR903QSQ/NOPB
DS90UR903QSQE/NOPB
DS90UR903QSQX/NOPB
DS90UR904QSQ/NOPB
DS90UR904QSQE/NOPB
DS90UR904QSQX/NOPB
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RTA
RTA
RTA
RHS
RHS
RHS
40
40
40
48
48
48
1000
250
356.0
208.0
356.0
356.0
208.0
356.0
356.0
191.0
356.0
356.0
191.0
356.0
35.0
35.0
35.0
35.0
35.0
35.0
2500
1000
250
2500
Pack Materials-Page 2
PACKAGE OUTLINE
RTA0040A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
6.1
5.9
0.5
0.3
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
0.08
0.05
0.00
(0.2) TYP
(0.1) TYP
4.6 0.1
EXPOSED
THERMAL PAD
20
11
36X 0.5
10
21
4X
4.5
SEE TERMINAL
DETAIL
1
30
0.3
40X
40
31
0.2
PIN 1 ID
(OPTIONAL)
0.5
0.3
0.1
C A B
40X
0.05
4214989/B 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTA0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.6)
SYMM
40
31
40X (0.6)
40X (0.25)
1
30
36X (0.5)
SYMM
(5.8)
(0.74)
TYP
(
0.2) TYP
VIA
(1.31)
TYP
10
21
(R0.05) TYP
11
20
(0.74) TYP
(1.31 TYP)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214989/B 02/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTA0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.48) TYP
9X ( 1.28)
40
31
40X (0.6)
1
30
40X (0.25)
36X (0.5)
(1.48)
TYP
SYMM
(5.8)
METAL
TYP
10
21
(R0.05) TYP
11
20
SYMM
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
70% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
4214989/B 02/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
DS90UR905QSQENOPB
IC LINE DRIVER, QCC48, 7 X 7 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-48, Line Driver or Receiver
NSC
DS90UR905QSQNOPB
IC LINE DRIVER, QCC48, 7 X 7 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-48, Line Driver or Receiver
NSC
©2020 ICPDF网 联系我们和版权申明