DS92CK16 [TI]
3V BLVDS 1:6 时钟缓冲器/总线收发器;
| 型号： | DS92CK16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3V BLVDS 1:6 时钟缓冲器/总线收发器 时钟 总线收发器 |
| 文件： | 总20页 (文件大小：1120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS92CK16
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SNAS044C –NOVEMBER 1999–REVISED APRIL 2013
DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver
Check for Samples: DS92CK16
1
FEATURES
DESCRIPTION
The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver
is a one to six CMOS differential clock distribution
device utilizing Bus Low Voltage Differential Signaling
(BLVDS) technology. This clock distribution device is
designed for applications requiring ultra low power
dissipation, low noise, and high data rates. The
BLVDS side is a transceiver with a separate channel
acting as a return/source clock.
2
•
Master/Slave Clock Selection in a Backplane
Application
•
•
•
•
•
•
•
125 MHz Operation (Typical)
100 ps Duty Cycle Distortion (Typical)
50 ps Channel to Channel Skew (Typical)
3.3V Power Supply Design
Glitch-free Power on at CLKI/O Pins
Low Power Design (20 mA @ 3.3V Static)
The DS92CK16 accepts LVDS (300 mV typical)
differential input levels, and translates them to 3V
CMOS output levels. An output enable pin OE , when
high, forces all CLKOUT pins high.
Accepts Small Swing (300 mV Typical)
Differential Signal Levels
•
•
Industrial Temperature Operating Range (-40°C
to +85°C)
The device can be used as a source synchronous
driver. The selection of the source driving is
controlled by the CrdCLKIN and DE pins. This device
can be the master clock, driving the inputs of other
clock I/O pins in a multipoint environment. Easy
master/slave clock selection is achieved along a
backplane.
Available in 24-pin TSSOP Packaging
Function Diagram and Truth Table
Table 1. Receive Mode Truth Table
INPUT
OUTPUT
OE
H
DE
H
CrdCLKIN
(CLKI/O+)–(CLKI/O−)
X
CLKOUT
X
X
X
H
H
L
L
H
VID≥ 0.07V
VID≤ −0.07V
L
H
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
DS92CK16
SNAS044C –NOVEMBER 1999–REVISED APRIL 2013
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Table 2. Driver Mode Truth Table
INPUT
OUTPUT
OE
L
DE
L
CrdCLKIN
CLK/I/O+
CLKI/O−
CLKOUT
L
H
L
L
H
L
H
L
L
L
L
H
H
H
H
H
H
H
L
H
L
L
H
X
H
Z
H
Z
Connection Diagram
TSSOP Package
See Package Number PW (R-PDSO-G24)
TSSOP PACKAGE PIN DESCRIPTIONS
Description
Pin Name
CLKI/O+
CLKI/O−
OE
Pin #
Type
I/O
I/O
I
6
7
2
True (Positive) side of the differential clock input.
Complementary (Negative) side of the differential clock input.
OE; this pin is active Low. When High, this pin forces all CLKOUT pins High. When Low,
CLKOUT pins logic state is determined by either the CrdCLKIN or the VID at the CLK/I/O pins
with respect to the logic level at the DE pin. This pin has a weak pullup device to VCC. If OE
is floating, then all CLKOUT pins will be High.
DE
11
I
DE; this pin is active LOW. When Low, this pin enables the CardCLKIN signal to the CLKI/O
pins and CLKOUT pins. When High, the Driver is TRI-STATE, the CLKI/O pins are inputs and
determine the state of the CLKOUT pins. This pin has a weak pullup device to VCC. If DE is
floating, then CLKI/O pins are TRI-STATE.
CLKOUT
13, 15, 17,
19, 21, 23
O
6 Buffered clock (CMOS) outputs.
CrdCLKIN
VCC
9
I
Input clock from Card (CMOS level or TTL level).
16, 20, 24
Power
VCC; Analog VCCA (Internally separate from VCC, connect externally or use separate power
supplies). No special power sequencing required. Either VCCA or VCC can be applied first, or
simultaneously apply both power supplies.
GND
VCCA
1, 12, 14, 18,
22
Ground
Power
GND
4
Analog VCCA (Internally separate from VCC, connect externally or use separate power
supplies). No special power sequencing required. Either VCCA or VCC can be applied first, or
simultaneously apply both power supplies.
GNDA
NC
5, 8
Ground
Analog Ground (Internally separate from Ground must be connected externally).
No Connects
3, 10
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
Supply Voltage (VCC
)
−0.3V to +4V
Enable Input Voltage
(DE, OE, CrdCLKIN
)
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to +4V
Voltage (CLKOUT
)
Voltage (CLKI/O±)
Driver Short Circuit Current
Receiver Short Circuit Current
Maximum Package Power Dissipation at +25°C
PW Package
momentary
momentary
1500 mW
8.2 mW/°C above +25°C
95°C/W
Derate PW Package
θJA
θJC
30°C/W
Storage Temperature Range
Lead Temperature Range
(Soldering, 4 sec.)
−65°C to +150°C
260°C
>3000V
>1000V
>200V
(3)
ESD Ratings: HBM
(3)
CDM
(3)
Machine Model
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be verified. These ratings are not meant to
imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device
operation.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) ESD Rating: ESD qualification is performed per the following: HBM (1.5 kΩ, 100 pF), Machine Model (250V, 0Ω), IEC 1000-4-2. All VCC
pins connected together, all ground pins connected together.
Recommended Operating Conditions
Min
Typ
Max
Units
Supply Voltage (VCC
)
+3.0
+3.3
+3.6
V
CrdCLKIN, DE, OE
Input Voltage
0
VCC
+85
V
Operating Free Air
Temperature (TA)
−40
25
°C
DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified
(1) (2)
.
Symbol
VTH
Parameter
Input Threshold High
Input Threshold Low
Conditions
Pin
Min
Typ
Max
Units
CLKI/O+,
CLKI/O−
25
+70
mV
mV
VTL
−70
-35
VCMR Common Mode Voltage
VID = 250 mV pk to pk
|VID|/2
2.4 - |VID|/2
+20
V
(3)
Range
IIN
Input Current
VIN = 0V to VCC, DE = VCC, OE =
VCC, Other Input = 1.2V ± 50 mV
−20
±5
µA
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VID, VOD, VTH, and VTL.
(2) All typicals are given for: VCC = +3.3V and TA = +25°C.
(3) The VCMR range is reduced for larger VID. Example: If VID=400 mV, then VCMR is 0.2V to 2.2V A VID up to |VCC–0V| may be applied
between the CLKI/O+ and CLKI/O− inputs, with the Common Mode set to VCC/2.
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DC Electrical Characteristics (continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1) (2)
.
Symbol
VOH1R
VOH2R
VOL1R
VOL2R
IODHR
Parameter
Output High Voltage
Output High Voltage
Output Low Voltage
Output Low Voltage
CLKOUT Dynamic Output
Conditions
Pin
Min
Typ
2.9
Max
Units
VID = 250 mV, IOH = −1.0 mA
VID = 250 mV, IOH = −6 mA
IOL = 1.0 mA, VID = −250 mV
IOL = 6 mA, VID = −250 mV
VID = +250 mV, VOUT = VCC−1V
CLKOUT
V
CC−0.4
CC−0.8
V
V
V
V
V
2.5
0.06
0.3
0.4
0
−8
-16
21
-30
35
mA
mA
(4)
Current
IODLR
CLKOUT Dynamic Output
VID = −250 mV, VOUT = 1V
10
(4)
Current
VIH
VIL
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Current
DE, OE,
CrdCLKIN
2.0
GND
−10
−20
−5
VCC
0.8
V
V
IIH
VIN = VCC or 2.4V
OE, DE
−2
−5
+10
+20
+5
µA
µA
µA
IIL
VIN = GND or 0.4V
VIN = 0V to VCC, OE = VCC
IOUT = −1.5 mA
IINCRD
VCL
CrdCLKIN
Input Voltage Clamp
OE, DE,
CrdCLKIN
−0.8
V
ICC
No Load Supply Current
Outputs Enabled, No VID
Applied
OE = DE = 0V,
CrdCLKIN = VCC or GND,
CLKI/O (±) = Open
VCC
13
10
mA
CLKOUT (0:5) = Open Circuit
ICC1
No Load Supply Current
OE = GND
Outputs Enabled, VID over DE = VCC
Common Mode Voltage
Range
CrdCLKIN = VCC or GND,
VID = 250 mV
mA
(0.125V VCM 2.275V),
CLKOUT (0:5) = Open Circuit
ICCD
Driver Loaded Supply
Current
DE = OE = 0V,
CrdCLKIN = VCC or GND,
RL = 37.5Ω between CLKI/O+ and
CLKI/O−,
20
25
mA
mV
CLKOUT (0:5) = Open Circuit
VOD
Driver Output Differential
Voltage
RL = 37.5Ω, Figure 5
DE = 0V
CLKI/O+,
CLKI/O−
250
1.1
350
450
ΔVOD
Driver VOD Magnitude
Change
10
1.29
5
20
1.5
20
mV
V
VOS
Driver Offset Voltage
ΔVOS
Driver Offset Voltage
Magnitude Change
mV
VOHD
VOLD
IOS1D
Driver Output High
Driver Output Low
1.35
1.05
1.8
V
V
0.80
Driver Differential Short
CrdCLKIN = VCC or GND, VOD = 0V,
(outputs shorted together) DE = 0V
|30|
36
|50|
70
mA
mA
mA
mA
mA
µA
(5)
Circuit Current
IOS2D
IOS3D
IOS4D
IOS5D
IOFF
Driver Output Short Circuit CrdCLKIN = GND, DE = 0V, CLKI/O+
(5)
Current to VCC
= VCC
Driver Output Short Circuit CrdCLKIN = VCC, DE = 0V, CLKI/O−
34
70
(5)
Current to VCC
= VCC
Driver Output Short Circuit CrdCLKIN = VCC, DE = 0V, CLKI/O+
−47
−50
−70
−70
±20
(5)
Current to GND
= 0V
Driver Output Short Circuit CrdCLKIN = GND, DE = 0V, CLKI/O−
(5)
Current to GND
= 0V
Power Off Leakage Current VCC = 0V or Open,
VAPPLIED = 3.6V
(4) Only one output should be momentarily shorted at a time. Do not exceed package power dissipation rating.
(5) Only one output should be momentarily shorted at a time. Do not exceed package power dissipation rating.
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Switching Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified
(1) (2)
.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIFFERENTIAL RECEIVER CHARACTERISTICS
tPHLDR
tPLHDR
tSK1R
Differential Propagation Delay High to Low. CLKI/O to CLKOUT CL = 15 pF
1.3
1.3
2.8
2.9
3.8
3.8
ns
ns
VID = 250 mV
Figure 1 Figure 2
Differential Propagation Delay Low to High. CLKI/O to CLKOUT
Duty Cycle Distortion(3)
(pulse skew)
100
30
400
ps
|tPLH–tPHL
|
(4)
tSK2R
tSK3R
tTLHR
Channel to Channel Skew; Same Edge
80
ps
ns
(5)
Part to Part Skew
2.5
(6)
Transition Time Low to High
0.4
0.4
1.0
1.4
1.3
3
2.4
2.2
4.5
4.5
ns
ns
ns
(20% to 80% )
Transition Time High to Low(6)
(80% to 20% )
tTHLR
tPLHOER
tPHLOER
fMAX
Propagation Delay Low to High
CL = 15 pF
( OEto CLKOUT
Propagation Delay High to Low
(OE to CLKOUT
Maximum Operating Frequency
)
Figure 3 Figure 4
1.0
3
ns
)
(7)
100
125
MHz
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
tPHLDD
Differential Propagation Delay High to Low. CrdCLKIN to
CLKI/O
CL = 15 pF
RL = 37.5Ω
Figure 6 Figure 7
0.5
0.5
1.8
1.8
2.5
2.5
ns
ns
tPLHDD
Differential Propagation Delay Low to High. CrdCLKIN to
CLKI/O
tPHLCrd
tPLHCrd
tSK1D
CrdCLKIN to CLKOUT Propagation Delay High to Low
CrdCLKIN to CLKOUT Propagation Delay Low to High
CL = 15 pF
Figure 8 Figure 9
2.0
2.0
4.5
4.5
6.0
6.0
ns
ns
Duty Cycle Distortion (pulse skew)
600
2.0
1.4
ps
ns
ns
(8)
|tPLH–tPHL
|
(9)
tSK2D
tTLHD
Differential Part-to-Part Skew
(6)
Differential Transition Time
(20% to 80% )
0.4
0.4
0.75
0.75
(6)
tTHLD
Differential Transition Time
(80% to 20% )
1.4
ns
tPHZD
tPLZD
tPZHD
tPZLD
fMAX
Transition Time High to TRI-STATE. DE to CLKI/O
Transition Time Low to TRI-STATE. DE to CLKI/O
Transition Time TRI-STATE to High. DE to CLKI/O
Transition Time TRI-STATE to Low. DE to CLKI/O
10
10
32
32
ns
ns
VIN = 0V to VCC
CL = 15 pF,
RL = 37.5Ω
ns
ns
Figure 10 Figure 11
(7)
Maximum Operating Frequency
100
125
MHz
(1) CL includes probe and fixture capacitance.
(2) Generator waveform for all tests unless otherwise specified: f = 25 MHz, Zo = 50Ω, tr = 1 ns, tf = 1 ns (10%–90%). To ensure fastest
propagation delay and minimum skew, clock input edge rates should not be slower than 1 ns/V; control signals not slower than 3 ns/V.
In general, the faster the input edge rate, the better the AC performance.
(3) tSK1R is the difference in receiver propagation delay (|tPLH–tPHL|) of one device, and is the duty cycle distortion of the output at any given
temperature and VCC. The propagation delay specification is a device to device worst case over process, voltage and temperature.
(4) tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same
direction. This parameter is specified by design and characterization.
(5) tSK3R, part-to-part skew, is the difference in receiver propagation delay between devices of any outputs switching in the same direction.
This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution.
TSK3R is defined as Max–Min differential propagation delay.This parameter is specified by design and characterization.
(6) All device output transition times are based on characterization measurements and are specified by design.
(7) Generator input conditions: tr/tf < 1 ns, 50% duty cycle, differential (1.10V to 1.35V pk-pk). Output Criteria: 60%/40% duty cycle,
VOL(max) 0.4V, VOH(min) 2.7V, Load = 7 pF (stray plus probes).
(8) tSK1D is the difference in driver propagation delay (|tPLH–tPHL|) and is the duty cycle distortion of the CLKI/O outputs.
(9) tSK2D part-to-part skew, is the difference in driver propagation delay between devices of any outputs switching in the same direction.
This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution.
tSK2D is defined as Max–Min differential propagation delay.
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PARAMETER MEASUREMENT INFORMATION
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
Generator waveform for all test unless otherwise specified: f = 25 MHz, 50% Duty Cycle, Zo = 50Ω, tTLH = 1 ns, tTHL
=
1 ns.
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
Figure 3. Output Enable (OE) Delay Test Circuit
Figure 4. Output Enable (OE) Delay Waveforms
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Figure 5. Differential Driver DC Test
Figure 6. Driver Propagation Delay Test Circuit
Figure 7. Driver Propagation Delay and Transition Time Waveforms
Figure 8. CrdCLKIN Propagation Delay Time Test Circuit
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Figure 9. CrdCLKIN Propagation Delay Time Waveforms
Figure 10. Driver TRI-STATE Test Circuit
Figure 11. Driver TRI-STATE Waveforms
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APPLICATIONS INFORMATION
General application guidelines and hints for BLVDS/LVDS transceivers, drivers and receivers may be found in
the following application notes: LVDS Owner's Manual, AN805(SNOA233), AN807(SNLA027), AN808(SNLA028),
AN903(SNLA034), AN905(SNLA035), AN916(SNLA219), AN971(SNLA165), AN977(SNLA166) .
BLVDS drivers and receivers are intended to be used in a differential backplane configuration. Transceivers or
receivers are connected to the driver through a balanced media such as differential PCB traces. Typically, the
characteristic differential impedance of the media (Zo) is in the range of 50Ω to100Ω. Two termination resistors of
ZoΩ each are placed at the ends of the transmission line backplane. The termination resistor converts the
current sourced by the driver into a voltage that is detected by the receiver. The effects of mid-stream
connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits,
and total termination loading must be taken into account.
The DS92CK16 differential line driver is a balanced current source design. A current mode driver, generally
speaking has a high output impedance (100 ohms) and supplies a constant current for a range of loads (a
voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched
through the load in one direction to produce a logic state and in the other direction to produce the other logic
state. The output current is typically 9.330 mA. The current changes as a function of load resistor. The current
mode requires (as discussed above) that a resistive termination be employed to terminate the signal and to
complete the loop. Unterminated configurations are not allowed. The 9.33 mA loop current will develop a
differential voltage of about 350mV across 37.5Ω (double terminated 75Ω differential transmission backplane)
effective resistance, which the receiver detects with a 280 mV minimum differential noise margin neglecting
resistive line losses (driven signal minus receiver threshold (350 mV – 70 mV = 280 mV)). The signal is centered
around +1.2V (Driver Offset, VOS) with respect to ground. Note that the steady-state voltage (VSS) peak-to-peak
swing is twice the differential voltage (VOD) and is typically 700 mV.
The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its
quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver
increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows
between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed
current between its output without any substantial overlap current. This is similar to some ECL and PECL
devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires > 80% less
current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing
RS-422 drivers.
The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when
the transmission of data is not required.
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1µF
in parallel with 0.01µF, in parallel with 0.001µF at the power supply pin as well as scattered capacitors over the
printed circuit board. Multiple vias should be used to connect the decoupling capacitors to the power planes. A
4.7µF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed
circuit board.
PC BOARD CONSIDERATIONS
Use at least 4 PCB layers (top to bottom); BLVDS signals, ground, power, TTL signals.
Isolate TTL signals from BLVDS signals, otherwise the TTL may couple onto the BLVDS lines. It is best to put
TTL and BLVDS signals on different layers which are isolated by a power/ground plane(s).
Keep drivers and receivers as close to the (BLVDS port side) connectors as possible to create short stub
lengths.
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DIFFERENTIAL TRACES
Use controlled impedance traces which match the differential impedance of your transmission medium (ie.
backplane or cable) and termination resistor(s). Run the differential pair trace lines as close together as possible
as soon as they leave the IC . This will help eliminate reflections and ensure noise is coupled as common-mode.
In fact, we have seen that differential signals which are 1mm apart radiate far less noise than traces 3mm apart
since magnetic field cancellation is much better with the closer traces. Plus, noise induced on the differential
lines is much more likely to appear as common-mode which is rejected by the receiver.
Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase
difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI
will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118
in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match
differential impedance and provide isolation for the differential lines. Minimize the number or vias and other
discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode
rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid
discontinuities in differential impedance. Minor violations at connection points are allowable.
STUB LENGTH
Stub lengths should be kept to a minimum. The typical transition time of the DS92CK16 BLVDS output is 0.75ns
(20% to 80%). The 100 percent time is 0.75/0.6 or 1.25ns. For a general approximation, if the electrical length of
a trace is greater than 1/5 of the transition edge, then the trace is considered a transmission line. For example,
1.25ns/5 is 250 picoseconds. Let velocity equal 160ps per inch for a typical loaded backplane. Then maximum
stub length is 250ps/160ps/in or 1.56 inches. To determine the maximum stub for your backplane, you need to
know the propagation velocity for the actual conditions (refer to application notes AN– 905(SNLA035) and
AN–808(SNLA028)).
TERMINATION
Use a resistor which best matches the differential impedance of your loaded transmission line. Remember that
the current mode outputs need the termination resistor to generate the differential voltage. BLVDS will not work
without resistor termination.
Surface mount 1% to 2% resistors are best.
PROBING BLVDS TRANSMISSION LINES
Always use high impedance (> 100kΩ), low capacitance (< 2pF) scope probes with a wide bandwidth (1GHz)
scope. Improper probing will give deceiving results.
CABLES AND CONNECTORS, GENERAL COMMENTS
Use controlled impedance media. The connectors you use should have a matched differential impedance of
about Zo Ω. They should not introduce major impedance discontinuities.
Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for
noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and
also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by
the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤
10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive.
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Product Folder Links: DS92CK16
DS92CK16
www.ti.com
SNAS044C –NOVEMBER 1999–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
Copyright © 1999–2013, Texas Instruments Incorporated
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11
Product Folder Links: DS92CK16
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS92CK16TMTC
ACTIVE
TSSOP
TSSOP
TSSOP
PW
24
24
24
61
Non-RoHS
& Green
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
DS92CK16T
MTC
DS92CK16TMTC/NOPB
DS92CK16TMTCX/NOPB
ACTIVE
ACTIVE
PW
61
RoHS & Green
SN
SN
DS92CK16T
MTC
PW
2500 RoHS & Green
DS92CK16T
MTC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS92CK16TMTCX/NOPB TSSOP
PW
24
2500
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 24
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
DS92CK16TMTCX/NOPB
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
DS92CK16TMTC
DS92CK16TMTC
PW
PW
PW
TSSOP
TSSOP
TSSOP
24
24
24
61
61
61
495
495
495
8
8
8
2514.6
2514.6
2514.6
4.06
4.06
4.06
DS92CK16TMTC/NOPB
Pack Materials-Page 3
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
B
13
0.30
24X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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