DS92LV0421 [TI]
具有 LVDS 并行接口的 10MHz 至 75MHz Channel-Link II 串行器;
| 型号： | DS92LV0421 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 LVDS 并行接口的 10MHz 至 75MHz Channel-Link II 串行器 |
| 文件： | 总58页 (文件大小：1257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DS92LV0421, DS92LV0422
SNLS325D –MAY 2010–REVISED DECEMBER 2016
DS92LV042x 10-MHz to-75 MHz Channel Link II Serializer and Deserializer
With LVDS Parallel Interface
1 Features
3 Description
The DS92LV042x chipset translates a Channel Link
LVDS video interface (4 LVDS Data + LVDS Clock)
into a high-speed serialized interface over a single
CML pair. The DS92LV042x enables applications
currently using popular Channel Link or OpenLDI
LVDS style devices to upgrade seamlessly to an
embedded clock interface. This serial bus scheme
reduces interconnect cost and eases design
challenges. The parallel OpenLDI LVDS interface
also reduces FPGA I/O pins, board trace count, and
alleviates EMI issues when compared to traditional
single-ended wide bus interfaces.
1
•
5-Channel (4 Data + 1 Clock) Channel Link LVDS
Parallel Interface Supports 24-Bit Data 3-Bit
Control at 10 to 75 MHz
•
•
AC-Coupled STP Interconnect Up to 10 m
Integrated Terminations on Serializer and
Deserializer
•
•
•
•
•
•
•
At-Speed Link BIST Mode and Reporting Pin
Optional I2C-Compatible Serial Control Bus
Power-Down Mode Minimizes Power Dissipation
1.8-V or 3.3-V Compatible LVCMOS I/O Interface
>8-kV HBM
Programmable
transmit
de-emphasis,
receive
equalization, on-chip scrambling, and DC-balancing
enables longer distance transmission over lossy
–40° to 85°C Temperature Range
Serializer (DS92LV0421)
cables
and
backplanes.
The
DS92LV0422
–
–
–
Data Scrambler for Reduced EMI
automatically locks to incoming data without an
external reference clock or special sync patterns,
providing easy plug-and-go operation.
DC–Balance Encoder for AC Coupling
Selectable Output VOD and Adjustable De-
Emphasis
The DS92LV042x chipset is programmable through
an I2C interface as well as through pins. A built-in, at-
speed BIST feature validates link integrity and may
be used for system diagnostics. The DS92LV0421
and DS92LV0422 can be used interchangeably with
the DS92LV2421 or DS92LV2422. This allows
designers the flexibility to connect to the host device
and receiving devices with different interface types:
LVDS or LVCMOS.
•
Deserializer (DS92LV0422)
–
Fast Random Data Lock; No Reference Clock
Required
–
–
Adjustable Input Receiver Equalization
EMI Minimization on Output Parallel Bus
(SSCG and LVDS VOD Select)
Device Information(1)
2 Applications
•
•
•
•
•
Embedded Video and Displays
PART NUMBER
DS92LV0421
PACKAGE
WQFN (36)
WQFN (48)
BODY SIZE (NOM)
6.00 mm × 6.00 mm
7.00 mm × 7.00 mm
Medical Imaging and Factory Automation
Office Automation (Printers and Scanners)
Security and Video Surveillance
DS92LV0422
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
General-Purpose Data Communication
Typical Application Block Diagram
Channel Link
Channel Link II
Channel Link
VDDIO
(1.8V or 3.3V)
VDDIO
(1.8V or 3.3V)
1.8V
1.8V 3.3V
RxIN3+/-
RxIN2+/-
TxOUT3+/-
High-Speed Serial Link
1 Pair/AC Coupled
TxOUT2+/-
Camera/AFE
Or
HOST
Graphics
Processor
Frame Grabber
Or
RGB Display
QVGA to XGA
24-bit Color Depth
DOUT+
DOUT-
RIN+
RIN-
RxIN1+/-
RxIN0+/-
TxOUT1+/-
TxOUT0+/-
100 ohm STP Cable
RxCLKIN+/-
TxCLKOUT+/-
CMF
DS92LV0421
DS92LV0422
LOCK
PASS
SSC[2:0]
PDB
BISTEN
VODSEL
De-Emph
LFMODE
MAPSEL
CONFIG[1:0]
CONFIG[1:0]
PDB
BISTEN
MAPSEL
OEN
OSSEL
VODSEL
SCL
SDA
ID[x]
SCL
SDA
ID[x]
Optional
Optional
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS92LV0421, DS92LV0422
SNLS325D –MAY 2010–REVISED DECEMBER 2016
www.ti.com
Table of Contents
7.3 Feature Description................................................. 24
7.4 Device Functional Modes........................................ 36
7.5 Register Maps......................................................... 37
Application and Implementation ........................ 40
8.1 Application Information............................................ 40
8.2 Typical Application .................................................. 43
Power Supply Recommendations...................... 46
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 9
6.1 Absolute Maximum Ratings ...................................... 9
6.2 ESD Ratings.............................................................. 9
6.3 Recommended Operating Conditions....................... 9
6.4 Thermal Information................................................ 10
6.5 Electrical Characteristics: Serializer DC ................. 10
6.6 Electrical Characteristics: Deserializer DC ............. 11
8
9
10 Layout................................................................... 47
10.1 Layout Guidelines ................................................. 47
10.2 Layout Example .................................................... 49
11 Device and Documentation Support ................. 50
11.1 Device Support...................................................... 50
11.2 Documentation Support ........................................ 50
11.3 Related Links ........................................................ 50
11.4 Receiving Notification of Documentation Updates 50
11.5 Community Resources.......................................... 50
11.6 Trademarks........................................................... 50
11.7 Electrostatic Discharge Caution............................ 51
11.8 Glossary................................................................ 51
6.7 Electrical Characteristics: DC and AC Serial Control
Bus........................................................................... 13
6.8 Timing Requirements: Serial Control Bus............... 13
6.9 Switching Characteristics: Serializer....................... 14
6.10 Switching Characteristics: Deserializer................. 15
6.11 Typical Characteristics.......................................... 22
Detailed Description ............................................ 23
7.1 Overview ................................................................. 23
7.2 Functional Block Diagrams ..................................... 23
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 51
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2013) to Revision D
Page
•
Added Device Information table, Pin Configuration and Functions section, Specifications section, ESD Ratings table,
Thermal Information table, Typical Characteristics section, Detailed Description section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
Added OpenLDI LVDS as an acceptable parallel interface to the DS92LV024x chipset....................................................... 1
Changed RXIN and RXCLKIN to TXOUT and TXCLKOUT to correct pin name typos ........................................................ 6
Changed output state of deserializer when PDB = 1 to be TRI-STATE, not logic high......................................................... 6
Deleted Power dissipation rows from the Absolute Maximum Ratings table ......................................................................... 9
•
•
•
•
•
Changed Junction-to-ambient, RθJA, values in Thermal Information table From: 27.4°C/W To: 33.8°C/W (NJK) and
From: 27.7°C/W to: 28.8°C/W (RHS) ................................................................................................................................... 10
•
•
Changed Junction-to-case, RθJC(top), values in Thermal Information table From: 4.5°C/W To: 15.8°C/W (NJK) and
From: 3.0°C/W To: 9.3°C/W (RHS) ...................................................................................................................................... 10
Deleted note in Electrical Characteristics: Serializer DC table stating that conditions are verified by characterization
or design and not tested in production, as this note only applies to a subset of tested parameters ................................... 10
•
•
•
•
•
•
•
Changed minimum and maximum value of serializer IIN for LVDS receiver DC specification ............................................. 10
Changed de-emphasis test condition for serializer IDD supply current ................................................................................. 11
Changed IOL condition for serial bus VOL parameter from 3 mA to 0.5 mA ......................................................................... 13
Changed RPU = 10 kΩ condition for the Serial Control Bus Characteristics of tR and tF ................................................... 13
Changed tPLD footnote to include tDDLT parameter................................................................................................................ 14
Changed notation for serial bit stream UI footnote to clarify 1 UI = 1 / (28 x CLK) ............................................................. 14
Changed footnote for deserializer LVDS output units to clarify that parallel interface UI refers to Channel Link format
(1 UI = 1 / [7 × CLK]) instead of Channel Link II format (1 UI = 1 / [28 × CLK]) ................................................................. 15
•
•
Changed DS92LV0422 LVDS Transmitter Pulse Positions image to correct diagram labeling........................................... 18
Changed parallel interface description of deserializer From: wide parallel output bus To: Channel Link LVDS clock
2
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Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: DS92LV0421 DS92LV0422
DS92LV0421, DS92LV0422
www.ti.com
SNLS325D –MAY 2010–REVISED DECEMBER 2016
Revision History (continued)
and data bus......................................................................................................................................................................... 28
Deleted support for output data and clock slew rate control ............................................................................................... 28
Changed CMF cap recommendation from 0.1 µF to 4.7 µF ................................................................................................ 28
•
•
•
Changed SSCG Configuration (LFMODE = L) table and SSCG Configuration (LFMODE = H) table to clarify correct
SSC[2:0] behavior................................................................................................................................................................. 29
•
Changed PDB, OEN, and OSS_SEL Configuration table to clarify correct behavior with PDB, OEN, and OSS_SEL
pins ....................................................................................................................................................................................... 31
•
•
•
•
Changed BISTEN detail in BIST Waveforms image so that serializer and deserializer are generic ................................... 33
Changed description of Serializer VODSEL from Reg 0x00[4] to Reg 0x00[5] ................................................................... 37
Changed Serializer Reg 0x00[3:2] description from Reserved to Reverse-Compatibility Mode bits ................................... 37
Changed Deserializer Reg 0x00[3:2] description from Reserved to Reverse-Compatibility Mode bits ............................... 38
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1
Copyright © 2010–2016, Texas Instruments Incorporated
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Product Folder Links: DS92LV0421 DS92LV0422
DS92LV0421, DS92LV0422
SNLS325D –MAY 2010–REVISED DECEMBER 2016
www.ti.com
5 Pin Configuration and Functions
NJK Package
36-Pin WQFN
Top View
RXIN3œ
RXIN3+
RES6
1
2
3
4
5
6
7
8
9
27
26
25
24
23
22
21
20
19
RES4
MAPSEL
RES7
ID[X]
VDDRX
PDB
DAP
VDDL
SCL
VDDIO
BISTEN
VODSEL
DE-EMPH
SDA
RES0
CONFIG[0]
Not to scale
Pin Functions: DS92LV0421
PIN
TYPE(1)
DESCRIPTION(2)
NAME
NO.
CHANNEL LINK PARALLEL INPUT INTERFACE
True LVDS Clock Input
This pair must have a 100-Ω termination for standard LVDS levels.
RXCLKIN+
RXCLKIN–
RXIN[3:0]+
RXIN[3:0]–
35
34
I
I
I
I
Inverting LVDS Clock Input
This pair must have a 100-Ω termination for standard LVDS levels.
2, 33,
31, 29
True LVDS Data Input
This pair must have a 100-Ω termination for standard LVDS levels.
1, 32,
30, 28
Inverting LVDS Data Input
This pair must have a 100-Ω termination for standard LVDS levels.
CHANNEL LINK II SERIAL OUTPUT INTERFACE
True Output, CML
The output must be AC-coupled with a 0.1-µF capacitor.
DOUT+
DOUT–
16
15
O
O
Inverting Output, CML
The output must be AC-coupled with a 0.1-µF capacitor.
(1) G = Ground, I = Input, O = Output, and P = Power
(2) 1= HIGH, 0 = LOW
4
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Product Folder Links: DS92LV0421 DS92LV0422
DS92LV0421, DS92LV0422
www.ti.com
NAME
SNLS325D –MAY 2010–REVISED DECEMBER 2016
Pin Functions: DS92LV0421 (continued)
PIN
TYPE(1)
DESCRIPTION(2)
NO.
CONTROL AND CONFIGURATION
Operating Modes: Pin or Register Control, LVCMOS with pulldown.
Determines the device operating mode and interfacing device (see Table 10).
CONFIG[1:0] = 00: Interfacing to DS92LV2422 or DS92LV0422, Control Signal Filter DISABLED
CONFIG[1:0] = 01: Interfacing to DS92LV2422 or DS92LV0422, Control Signal Filter ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124Q-Q1
CONFIG[1:0]
10, 9
I
CONFIG [1:0] = 11: Interfacing to DS90C124
De-emphasis Control: Pin or Register Control, Analog with pullup.
De-emphasis = Open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to Ground or control through register (see
Table 2).
DE-EMPH
MAPSEL
19
26
I
I
Channel Link Map Select: Pin or Register Control, LVCMOS with pulldown.
MAPSEL = 1, MSB on RXIN3± (see Figure 23).
MAPSEL = 0, LSB on RXIN3± (see Figure 24).
Power-down Mode input, LVCMOS with pulldown.
PDB = 1, serializer is enabled (normal operation).
See Power Supply Recommendations for more information.
PDB = 0, serializer is powered down
PDB
23
I
When the serializer is in the power-down state, the driver outputs (DOUT±) are both logic high,
the PLL is shut down, and IDD is minimized. Control Registers are RESET.
25, 3, 36,
27, 18, 13,
12, 8
RES[7:0]
VODSEL
I
I
Reserved (tie low), LVCMOS with pulldown.
Differential Driver Output Voltage Select: Pin or Register Control, LVCMOS with pulldown.
VODSEL = 1, CML VOD is ±450 mV, 900 mVp-p (typical): long cable or de-emphasis
applications
20
VODSEL = 0, CML VOD is ±300 mV, 600 mVp-p (typical): short cable (no de-emphasis), low
power mode
OPTIONAL BIST MODE
BISTEN 21
BIST Mode: Optional, LVCMOS with pulldown.
BISTEN = 1, BIST is enabled
I
BISTEN = 0, BIST is disabled (normal operation)
OPTIONAL SERIAL BUS CONTROL
Serial Control Bus Device ID Address Select: Optional, Analog
Resistor to Ground and 10-kΩ pullup to 1.8-V rail (see Table 8).
ID[X]
SCL
SDA
4
6
7
I
I
Serial Control Bus Clock Input: Optional, LVCMOS (open-drain)
SCL requires an external pullup resistor to VDDIO
Serial Control Bus Data Input or Output: Optional, LVCMOS (open-drain)
SDA requires an external pullup resistor VDDIO
.
I/O
.
POWER AND GROUND(3)
DAP is the large metal contact at the bottom side, located at the center of the WQFN package.
Connect to the ground plane (GND) with at least 9 vias.
DAP
GND
G
VDDHS
VDDIO
VDDL
14
22
5
P
P
P
P
P
P
TX high-speed logic power, 1.8 V ±5%
LVCMOS I/O power and Channel Link I/O power, 1.8 V ±5% or 3.3 V ±10%
Logic power, 1.8 V ±5%
VDDP
11
24
17
PLL power, 1.8 V ±5%
VDDRX
VDDTX
RX power, 1.8 V ±5%
Output driver power, 1.8 V ±5%
(3) The VDD (VDDn and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. If slower than 1.5 ms, a capacitor on the PDB
pin is required to ensure PDB arrives after all the VDD supplies have settled to the recommended operating voltage.
Copyright © 2010–2016, Texas Instruments Incorporated
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Product Folder Links: DS92LV0421 DS92LV0422
DS92LV0421, DS92LV0422
SNLS325D –MAY 2010–REVISED DECEMBER 2016
www.ti.com
RHS Package
48-Pin WQFN
Top View
PDB
SSC[0]
SSC[1]
SDA
1
36
35
34
33
32
31
30
29
28
27
26
25
LFMODE
OSS_SEL
MAPSEL
VODSEL
GND
2
3
4
SCL
5
VDDL
6
VDDL
DAP
SSC[2]
VDDP
7
OEN
8
BISTEN
PASS/EQ
LOCK
GND
9
CONFIG[0]
CONFIG[1]
ID[X]
10
11
12
GND
VDDIO
Not to scale
Pin Functions: DS92LV0422
PIN
TYPE(1)
DESCRIPTION(2)
NAME
CHANNEL LINK II SERIAL INPUT INTERFACE
Common-mode filter, Analog
NO.
CMF
42
I
VCM center-tap is a virtual Ground which may be AC-coupled to Ground to increase receiver
common mode noise immunity. Recommended value is 4.7 µF or higher.
True Input, CML
The output must be AC-coupled with a 0.1-µF capacitor.
RIN+
RIN–
40
41
I
I
Inverting Input, CML
The output must be AC-coupled with a 0.1-µF capacitor.
CHANNEL LINK PARALLEL OUTPUT INTERFACE
True LVDS Clock Output
This pair must have a 100-Ω termination for standard LVDS levels.
TXCLKOUT+
TXCLKOUT–
TXOUT[3:0]+
TXOUT[3:0]–
17
18
O
O
O
O
Inverting LVDS Clock Output
This pair must have a 100-Ω termination for standard LVDS levels.
15, 19,
21, 23
True LVDS Data Output
This pair must have a 100-Ω termination for standard LVDS levels.
16, 20,
22, 24
Inverting LVDS Data Output
This pair must have a 100-Ω termination for standard LVDS levels.
(1) G = Ground, I = Input, O = Output, and P = Power
(2) 1= HIGH, 0 = LOW
6
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Product Folder Links: DS92LV0421 DS92LV0422
DS92LV0421, DS92LV0422
www.ti.com
NAME
SNLS325D –MAY 2010–REVISED DECEMBER 2016
Pin Functions: DS92LV0422 (continued)
PIN
TYPE(1)
DESCRIPTION(2)
NO.
LVCMOS OUTPUTS
LOCK Status Output, LVCMOS
LOCK = 1, PLL is locked, output stated determined by OEN.
LOCK = 0, PLL is unlocked, output states determined by OSS_SEL and OEN.
See Table 7.
LOCK
27
O
CONTROL AND CONFIGURATION
Operating Modes: Pin or Limited Register Control, LVCMOS with pulldown.
Determine the device operating mode and interfacing device. (see Table 10).
CONFIG[1:0] = 00: Interfacing to DS92LV2421 or DS92LV0421, Control Signal Filter DISABLED
CONFIG[1:0] = 01: Interfacing to DS92LV2421 or DS92LV0421, Control Signal Filter ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR241, DS99R421
CONFIG[1:0]
11, 10
I
CONFIG [1:0] = 11: Interfacing to DS90C124
SSCG Low Frequency Mode: Pin or Register Control, LVCMOS with pulldown.
LFMODE = 1, low frequency mode (TXCLKOUT = 10–20 MHz)
LFMODE = 0, high frequency mode (TXCLKOUT = 20–65 MHz)
SSCG not available above 65 MHz.
LFMODE
MAPSEL
36
34
I
I
Channel Link Map Select: Pin or Register Control, LVCMOS with pulldown.
MAPSEL = 1, MSB on TXOUT3± (see Figure 23).
MAPSEL = 0, LSB on TXOUT3± (see Figure 24).
Output Enable, LVCMOS with pulldown.
See Table 7 for details.
OEN
30
35
I
I
Output Sleep State Select Input, LVCMOS with pulldown.
See Table 7 for details.
OSS_SEL
Power-down Mode Input, LVCMOS with pulldown.
PDB = 1, deserializer is enabled (normal operation).
See Power Supply Recommendations for more information.
PDB = 0, deserializer is powered down.
PDB
1
I
When the deserializer is in the power-down state, the driver outputs (TXOUT±) are in TRI-
STATE. Control Registers are RESET.
RES
37
I
I
Reserved (tie low), LVCMOS with pulldown.
Spread Spectrum Clock Generation (SSCG) Range Select, LVCMOS with pulldown.
See Table 5 and Table 6.
SSC[2:0]
7, 3, 2
Parallel LVDS Driver Output Voltage Select: Pin or Register Control, LVCMOS with pulldown.
VODSEL = 1, LVDS VOD is ±400 mV, 800 mVp-p (typical)
VODSEL
33
I
VODSEL = 0, LVDS VOD is ±250 mV, 500 mVp-p (typical)
CONTROL AND CONFIGURATION — STRAP PIN
EQ Gain Control of Channel Link II Serial Input, STRAP, LVCMOS with pulldown
EQ
28 [PASS]
I
EQ = 1, EQ gain is enabled (~13 dB)
EQ = 0, EQ gain is disabled (~1.625 dB)
OPTIONAL BIST MODE
BIST Mode: Optional, LVCMOS with pulldown.
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
BISTEN
PASS
29
28
I
PASS Output (BIST Mode): Optional, LVCMOS
PASS =1, no errors detected
PASS = 0, errors detected
O
Leave open if unused. Route to a test point (pad) recommended.
OPTIONAL SERIAL BUS CONTROL
Serial Control Bus Device ID Address Select: Optional, Analog
Resistor to Ground and 10-kΩ pullup to 1.8-V rail (see Table 8).
ID[X]
SCL
SDA
12
5
I
I
Serial Control Bus Clock Input: Optional, LVCMOS (open drain)
SCL requires an external pullup resistor to 3.3 V.
Serial Control Bus Data Input or Output: Optional, LVCMOS (open drain)
SDA requires an external pullup resistor 3.3 V.
4
I/O
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Product Folder Links: DS92LV0421 DS92LV0422
DS92LV0421, DS92LV0422
SNLS325D –MAY 2010–REVISED DECEMBER 2016
www.ti.com
Pin Functions: DS92LV0422 (continued)
PIN
TYPE(1)
DESCRIPTION(2)
NAME
NO.
POWER AND GROUND(3)
DAP is the large metal contact at the bottom side, located at the center of the WQFN package.
Connect to the ground plane (GND) with at least 9 vias.
DAP
GND
DAP
G
G
9, 14, 26,
32, 39, 44,
45, 48
Ground
VDDA
VDDIO
VDDL
38, 43
25
P
P
P
P
P
P
Analog power, 1.8 V ±5%
LVCMOS I/O power and Channel Link I/O power, 1.8 V ± 5% or 3.3 V ±10%
Logic power, 1.8 V ±5%
6, 31
8
VDDP
VDDSC
VDDTX
PLL power, 1.8 V ±5%
46, 47
13
SSCG power, 1.8 V ±5%
Channel Link LVDS parallel output power, 3.3 V ±10%
(3) The VDD (VDDn and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. If slower than 1.5 ms, a capacitor on the PDB
pin is required to ensure PDB arrives after all the VDD supplies have settled to the recommended operating voltage.
8
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Product Folder Links: DS92LV0421 DS92LV0422
DS92LV0421, DS92LV0422
www.ti.com
SNLS325D –MAY 2010–REVISED DECEMBER 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
2.5
UNIT
VDDn (1.8 V)
VDDIO
4
Supply voltage
V
Serializer, VDDTX
2.5
Deserializer, VDDTX
4
LVCMOS I/O voltage
VDDIO + 0.3
VDDIO + 0.3
VDDTX + 0.3
VDDn + 0.3
VDD + 0.3
150
V
V
Serializer LVDS input voltage
Deserializer LVDS output voltage
Serializer CML driver output voltage
Deserializer CML receiver input voltage
Junction temperature,TJ
V
V
V
°C
°C
Storage temperature, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) For soldering specifications, see Absolute Maximum Ratings for Soldering (SNOA549).
6.2 ESD Ratings
VALUE
±8000
±1250
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Machine Model
Electrostatic
discharge
V(ESD)
V
IEC 61000-4-2, powered-up only contact discharge
>±8000
RD = 330 Ω, CS = 150 pF (RIN+, RIN–
IEC 61000-4-2, powered-up only air-gap discharge
RD = 330 Ω, CS = 150 pF (RIN+, RIN–
)
>±30000
)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.71
1.71
3
NOM
1.8
MAX
1.89
1.89
3.6
UNIT
VDDn
Supply voltage
V
V
VDDTX
VDDTX
VDDIO
VDDIO
Supply voltage (serializer)
Supply voltage (deserializer)
LVCMOS supply voltage (1.8-V nominal)
LVCMOS supply voltage (3.3-V nominal)
Clock frequency
1.8
3.3
V
1.71
3
1.8
1.89
3.6
V
3.3
V
10
75
MHz
mVp-p
°C
Supply noise(1)
100
85
TA
Operating free-air temperature
−40
25
(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the VDDn (1.8 V) supply with
amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the serializer and output of the deserializer
with 10 meter cable shows no error when the noise frequency on the serializer is less than 750 kHz. The deserializer, on the other hand,
shows no error when the noise frequency is less than 400 kHz.
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6.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
DS92LV0421
DS92LV0422
THERMAL METRIC(1)
NJK (WQFN)
36 PINS
33.8
RHS (WQFN)
UNIT
48 PINS
28.8
9.3
RθJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
15.8
7.2
5.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
0.1
ψJB
7.1
5.7
RθJC(bot)
2.6
1.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Based on nine thermal vias.
6.5 Electrical Characteristics: Serializer DC
over recommended operating supply and temperature ranges (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS INPUT DC SPECIFICATIONS
VDDIO = 3 V to 3.6 V (PDB, VODSEL, MAPSEL,
CONFIG[1:0], BISTEN pins)
2
VDDIO
VDDIO
0.8
VIH
High-level input voltage
V
VDDIO = 1.71 V to 1.89 V (PDB, VODSEL, MAPSEL,
CONFIG[1:0], BISTEN pins)
0.65 ×
VDDIO
VDDIO = 3 V to 3.6 V (PDB, VODSEL, MAPSEL,
CONFIG[1:0], BISTEN pins)
GND
VIL
Low-level input voltage
Input current
V
VDDIO = 1.71 V to 1.89 V (PDB, VODSEL, MAPSEL,
CONFIG[1:0], BISTEN pins)
0.35 ×
VDDIO
GND
−15
VDDIO = 3 V to 3.6 V
±1
±1
15
VIN = 0 V or VDDIO (PDB,
VODSEL, MAPSEL,
CONFIG[1:0], BISTEN pins)
IIN
µA
VDDIO = 1.7 V to
1.89 V
−15
15
CHANNEL LINK PARALLEL LVDS RECEIVER DC SPECIFICATIONS
Differential threshold, high
voltage
VCM = 1.2 V (see Figure 1),
RXIN[3:0]± and RXCLKIN± pins
VTH
VTL
|VID
100
600
mV
mV
mV
Differential threshold, low
voltage
VCM = 1.2 V (see Figure 1),
RXIN[3:0]± and RXCLKIN± pins
−100
Differential input voltage
swing
VCM = 1.2 V (see Figure 1),
RXIN[3:0]± and RXCLKIN± pins
|
200
VDDIO = 3.3 V (RXIN[3:0]± and RXCLKIN± pins)
VDDIO = 1.8 V (RXIN[3:0]± and RXCLKIN± pins)
RXIN[3:0]± and RXCLKIN± pins
0
0
1.2
1.2
±1
2.4
1.7
15
VCM
IIN
Common-mode voltage
Input current
V
−15
µA
CHANNEL LINK II SERIAL CML DRIVER DC SPECIFICATIONS
RL = 100 Ω,
de-emphasis = disabled
(see Figure 3), DOUT+ and
DOUT– pins
VODSEL = L
VODSEL = H
VODSEL = L
VODSEL = H
±225
±350
±300
±450
600
±375
±550
VOD
Differential output voltage
mV
RL = 100 Ω,
Differential output voltage
(DOUT+) – (DOUT–)
de-emphasis = disabled
(see Figure 3), DOUT+ and
DOUT– pins
VODp-p
mVp-p
mV
900
RL = 100 Ω, de-emphasis = disabled, VODSEL = L
(DOUT+ and DOUT– pins)
ΔVOD
Output voltage unbalance
1
50
(1) Typical values represent most likely parametric norms at VDD = 3.3 V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not verified.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH, and VTL, which are differential voltages.
10
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SNLS325D –MAY 2010–REVISED DECEMBER 2016
Electrical Characteristics: Serializer DC (continued)
over recommended operating supply and temperature ranges (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
At TP A and B (see Figure 2), VODSEL = L
1.65
Offset voltage
(single-ended)
RL = 100 Ω, de-emphasis =
disabled (DOUT+ and DOUT–
pins)
VOS
V
VODSEL = H
1.575
Offset voltage unbalance
(single-ended)
At TP A and B (see Figure 2), RL = 100 Ω,
de-emphasis = disabled (DOUT+ and DOUT– pins)
ΔVOS
IOS
1
mV
mA
Ω
DOUT± = 0 V, de-emphasis = disabled,
VODSEL = 0 (DOUT+ and DOUT– pins)
Output short-circuit current
−36
Internal output termination
resistor
RTO
DOUT+ and DOUT– pins
80
120
100
SERIALIZER SUPPLY CURRENT
RL = 100 Ω, f = 75 MHz, checker board pattern (see
Figure 15), de-emphasis = 3 kΩ, VODSEL = H,
VDD = 1.89 V (All VDD pins)
Serializer supply current
IDDT1
84
mA
mA
mA
mA
(includes load current)
RL = 100 Ω, f = 75 MHz
de-emphasis = 3 kΩ,
VODSEL = H,
checker board pattern (see
Figure 15)
VDDIO= 1.89 V
(VDDIO pin)
3
5
Serializer supply current
IDDIOT1
(includes load current)
VDDIO = 3.6 V
(VDDIO pin)
10
13
RL = 100 Ω, f = 75 MHz, checker board pattern (see
Figure 15), de-emphasis = 6 kΩ, VODSEL = L,
VDD = 1.89 V (All VDD pins)
Serializer supply current
IDDT2
77
90
(includes load current)
RL = 100 Ω, f = 75 MHz
de-emphasis = 6 kΩ,
VODSEL = L,
checker board pattern (see
Figure 15)
VDDIO= 1.89 V
(VDDIO pin)
3
5
Serializer supply current
IDDIOT2
(includes load current)
VDDIO = 3.6 V
(VDDIO pin)
10
13
Serializer supply current
power-down
PDB = 0 V, all other LVCMOS inputs = 0 V,
VDD = 1.89 V (All VDD pins)
IDDZ
100
0.5
1
1000
10
µA
µA
VDDIO= 1.89 V
(VDDIO pin)
Serializer supply current
power-down
PDB = 0 V, all other LVCMOS
inputs = 0 V
IDDIOZ
VDDIO = 3.6 V
(VDDIO pin)
30
6.6 Electrical Characteristics: Deserializer DC
over recommended operating supply and temperature ranges (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
3.3-V LVCMOS I/O DC SPECIFICATIONS (VDDIO = 3 V to 3.6 V)
PDB, VODSEL, OEN, MAPSEL, LFMODE, SSC[2:0],
and BISTEN pins
VIH
VIL
IIN
High level input voltage
Low level input voltage
Input current
2
GND
−15
VDDIO
0.8
V
V
PDB, VODSEL, OEN, MAPSEL, LFMODE, SSC[2:0],
and BISTEN pins
VIN = 0 V or VDDIO (PDB, VODSEL, OEN, MAPSEL,
LFMODE, SSC[2:0], and BISTEN pins)
±1
15
µA
V
VDDIO
–
VOH
High level output voltage
IOH = –0.5 mA (LOCK and PASS pins)
VDDIO
0.2
VOL
IOS
Low level output voltage
IOL = 0.5 mA (LOCK and PASS pins)
VOUT = 0 V (LOCK and PASS pins)
GND
–10
0.2
10
V
Output short-circuit current
mA
PDB = 0 V, OSS_SEL = 0 V, VOUT = 0 V or VDDIO
(LOCK and PASS pins)
IOZ
TRI-STATE output current
–10
µA
(1) Typical values represent most likely parametric norms at VDD = 3.3 V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not verified.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH, and VTL, which are differential voltages.
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Electrical Characteristics: Deserializer DC (continued)
over recommended operating supply and temperature ranges (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
1.8-V LVCMOS I/O DC SPECIFICATIONS (VDDIO = 1.71 V to 1.89 V)
PDB, VODSEL, OEN, MAPSEL, LFMODE, SSC[2:0],
and BISTEN pins
0.65 ×
VDDIO
VIH
VIL
IIN
High level input voltage
Low level input voltage
Input current
VDDIO
V
V
PDB, VODSEL, OEN, MAPSEL, LFMODE, SSC[2:0],
and BISTEN pins
0.35 ×
VDDIO
GND
VIN = 0 V or VDDIO (PDB, VODSEL, OEN, MAPSEL,
LFMODE, SSC[2:0], and BISTEN pins)
−15
±1
15
µA
V
VDDIO
–
VOH
High level output voltage
IOH = –0.5 mA (LOCK and PASS pins)
VDDIO
0.2
VOL
IOS
Low level output voltage
IOL = 0.5 mA (LOCK and PASS pins)
VOUT = 0 V (LOCK and PASS pins)
GND
–3
0.2
15
V
Output short-circuit current
mA
PDB = 0 V, OSS_SEL = 0 V, VOUT = 0 V or VDDIO
(LOCK and PASS pins)
IOZ
TRI-STATE output current
–15
µA
CHANNEL LINK PARALLEL LVDS DRIVER DC SPECIFICATIONS
RL = 100 Ω
(see Figure 3; TXOUT[3:0]± and
TXCLKOUT± pins)
VODSEL = L
VODSEL = H
VODSEL = L
VODSEL = H
100
200
250
400
500
800
400
600
|VOD
|
Differential output voltage
mV
RL = 100 Ω
(see Figure 3; TXOUT[3:0]± and
TXCLKOUT± pins)
Differential output voltage
A to B
VODp-p
ΔVOD
VOS
mVp-p
mV
RL = 100 Ω
Output voltage unbalance
1
50
(see Figure 3; TXOUT[3:0]± and TXCLKOUT± pins)
RL = 100 Ω
(see Figure 3; TXOUT[3:0]± and
TXCLKOUT± pins)
VODSEL = L
VODSEL = H
1
1.2
1.2
1.5
Offset voltage
(single-ended)
V
Offset voltage unbalance
(single-ended)
RL = 100 Ω (see Figure 3; TXOUT[3:0]± and
TXCLKOUT± pins)
ΔVOS
IOS
1
50
mV
mA
µA
RL = 100 Ω, VOUT = GND
(TXOUT[3:0]± and TXCLKOUT± pins)
Output short-circuit current
Output TRI-STATE current
–5
RL = 100 Ω, VOUT = VDDTX or GND
(TXOUT[3:0]± and TXCLKOUT± pins)
IOZ
–10
10
50
CHANNEL LINK II SERIAL CML RECEIVER DC SPECIFICATIONS
Differential input threshold
high voltage
VCM = 1.2 V (Internal VBIAS
(RIN+ and RIN- pins)
)
)
VTH
VTL
mV
mV
Differential input threshold
low voltage
VCM = 1.2 V (Internal VBIAS
(RIN+ and RIN- pins)
–50
85
Common mode voltage,
internal VBIAS
VCM
RT
RIN+ and RIN- pins
RIN+ and RIN- pins
1.2
V
Input termination
100
115
Ω
DESERIALIZER SUPPLY CURRENT
75 MHz clock, checker board pattern (see
Figure 15), VODSEL = H, SSCG[2:0] = 000'b,
VDDn = 1.89 V (All VDD(1.8) pins)
Deserializer supply current
IDD1
88
40
100
50
mA
mA
(Includes load current)
75 MHz clock, checker board pattern (see
Figure 15), VODSEL = H, SSCG[2:0] = 000'b,
VDDTX = 3.6 V (VDDTX pin)
Deserializer supply current
IDDTX1
(Includes load current)
VDDIO = 1.89 V
(VDDIO pin)
75 MHz clock,
0.3
0.8
0.8
1.5
2
Deserializer supply current
IDDIO1
checker board pattern (see
Figure 15), VODSEL = H,
SSCG[2:0] = 000'b
mA
(Includes load current)
VDDIO = 3.6 V
(VDDIO pin)
Deserializer supply current
power-down
PDB = 0 V, All other LVCMOS inputs = 0 V,
VDDn = 1.89 V (All VDD(1.8) pins)
IDDZ
0.15
0.01
mA
mA
Deserializer supply current
power-down
PDB = 0 V, All other LVCMOS inputs = 0 V,
VDDTX = 3.6 V (VDDTX pin)
IDDTXZ
0.1
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SNLS325D –MAY 2010–REVISED DECEMBER 2016
Electrical Characteristics: Deserializer DC (continued)
over recommended operating supply and temperature ranges (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDDIO = 1.89 V
(VDDIO pin)
0.01
0.08
mA
Deserializer supply current
power-down
PDB = 0 V,
all other LVCMOS inputs = 0 V
IDDIOZ
VDDIO = 3.6 V
(VDDIO pin)
0.01
0.08
6.7 Electrical Characteristics: DC and AC Serial Control Bus
over 3.3-V supply and temperature ranges (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.7 ×
VDDIO
VIH
VIL
Input high-level voltage
SDA and SCL
VDDIO
V
0.3 ×
VDDIO
Input low-level voltage
SDA and SCL
GND
V
VHY
VOL
IIN
Input hysteresis
>50
mV
V
Output low-level voltage
Input current
SDA, IOL = 0.5 mA
0
0.36
10
SDA or SCL, Vin = VDDIO or GND
–10
µA
SDA, RPU = 10 kΩ, Cb ≤ 400pF
(see Figure 18)
tR
tF
SDA rise time, READ
SDA fall time, READ
800
50
ns
ns
SDA, RPU = 10 kΩ, Cb ≤ 400pF
(see Figure 18)
tSU;DAT
tHD;DAT
tSP
Set-up time, READ
Hold time, READ
Input filter
See Figure 18
See Figure 18
540
600
50
ns
ns
ns
pF
CIN
Input capacitance
SDA or SCL
<5
6.8 Timing Requirements: Serial Control Bus
over 3.3-V supply and temperature ranges (unless otherwise noted)
MIN
TYP
MAX
100
UNIT
Standard mode
Fast mode
fSCL
SCL clock frequency
SCL low period
kHz
400
Standard mode
Fast mode
4.7
1.3
4
tLOW
µs
µs
µs
µs
µs
µs
µs
µs
ns
Standard mode
Fast mode
tHIGH
SCL high period
0.6
4
Standard mode
Fast mode
Hold time for a START or a repeated START condition
(see Figure 18)
tHD:STA
0.6
4.7
0.6
0
Standard mode
Fast mode
Set-up time for a START or a repeated START condition
(see Figure 18)
tSU:STA
Standard mode
Fast mode
3.45
0.9
tHD:DAT Data hold time (see Figure 18)
tSU:DAT Data set-up time (see Figure 18)
tSU:STO Set-up time for STOP (see Figure 18)
0
Standard mode
Fast mode
250
100
4
Standard mode
Fast mode
0.6
4.7
1.3
Standard mode
Fast mode
Bus free time between STOP and START
(see Figure 18)
tBUF
Standard mode
Fast mode
1000
300
tr
SCL and SDA rise time (see Figure 18)
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Timing Requirements: Serial Control Bus (continued)
over 3.3-V supply and temperature ranges (unless otherwise noted)
MIN
TYP
MAX
300
UNIT
Standard mode
Fast mode
tf
SCL and SDA fall time (see Figure 18)
ns
300
6.9 Switching Characteristics: Serializer
over recommended operating supply and temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CHANNEL LINK PARALLEL LVDS INPUT
RXCLKIN = 75 MHz, RXIN[3:0] pins
(see Figure 5)
tRSP0
tRSP1
tRSP2
tRSP3
tRSP4
tRSP5
tRSP6
LVDS Receiver Strobe Position (bit 0)
LVDS Receiver Strobe Position (bit 1)
LVDS Receiver Strobe Position (bit 2)
LVDS Receiver Strobe Position (bit 3)
LVDS Receiver Strobe Position (bit 4)
LVDS Receiver Strobe Position (bit 5)
LVDS Receiver Strobe Position (bit 6)
0.57
2.47
0.95
2.85
1.33
3.23
ns
ns
ns
ns
ns
ns
ns
RXCLKIN = 75 MHz, RXIN[3:0] pins
(see Figure 5)
RXCLKIN = 75 MHz, RXIN[3:0] pins
(see Figure 5)
4.37
4.75
5.13
RXCLKIN = 75 MHz, RXIN[3:0] pins
(see Figure 5)
6.27
6.65
7.03
RXCLKIN = 75 MHz, RXIN[3:0] pins
(see Figure 5)
8.17
8.55
8.93
RXCLKIN = 75 MHz, RXIN[3:0] pins
(see Figure 5)
10.07
11.97
10.45
12.35
10.83
12.73
RXCLKIN = 75 MHz, RXIN[3:0] pins
(see Figure 5)
CHANNEL LINK II CML OUTPUT
RL = 100 Ω, De-emphasis = disabled,
VODSEL = 0
100
100
130
100
200
200
260
200
5
300
300
390
300
15
Serializer output low-to-high transition time
(see Figure 4)
tLLHT
ps
ps
RL = 100 Ω, De-emphasis = disabled,
VODSEL = 1
RL = 100 Ω, De-emphasis = disabled,
VODSEL = 0
Serializer output high-to-low transition time
(see Figure 4)
tLHLT
RL = 100 Ω, De-emphasis = disabled,
VODSEL = 1
Serializer output active to OFF delay
(see Figure 9)(1)
tXZD
tPLD
tSD
ns
ms
Serializer PLL lock time
(see Figure 7)(1)(2)(3)
RL = 100 Ω
RL = 100 Ω
1.5
10
Serializer delay, latency
(see Figure 10)(1)
147 × T 148 × T
0.3
ns
Serializer output total jitter
(see Figure 12)
RL = 100 Ω, De-emphasis = disabled,
RANDOM pattern
tDJIT
UI(4)
RXCLKIN = 43 MHz
RXCLKIN = 75 MHz
RXCLKIN = 43 MHz
RXCLKIN = 75 MHz
2.2
3
Serializer jitter transfer
λSTXBW
MHz
dB
(function –3-dB bandwidth)(1)(5)
1
Serializer jitter transfer
(function peaking)(1)(5)
δSTX
1
(1) Specification is verified by characterization and is not tested in production.
(2) tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active
RXCLKIN.
(3) When the serializer output is at TRI-STATE, the deserializer loses PLL lock. Resynchronization and Re-lock must occur before data
transfer require tPLD
.
(4) UI: Unit Interval is equivalent to one serialized data bit width (1 UI = 1 / [28 × CLK]). The UI scales with clock frequency.
(5) Specification is verified by design and is not tested in production.
14
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6.10 Switching Characteristics: Deserializer
over recommended operating supply and temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CHANNEL LINK PARALLEL LVDS OUTPUT
RL = 100 Ω
TXCLKOUT±, TXOUT[3:0]± pins
tDLHT
tDHLT
Deserializer low-to-high transition time
Deserializer high-to-low transition time
0.3
0.3
0.6
0.6
ns
ns
RL = 100 Ω
TXCLKOUT±, TXOUT[3:0]± pins
TXCLKOUT± = 10 MHz
TXCLKOUT± = 75 MHz
900
75
2100
125
tDCCJ
Cycle-to-cycle output jitter(1)(2)(3)
ps
TXCLKOUT± = 10 to 75 MHz
(see Figure 6)
tTTP1
tTTP0
tTTP6
tTTP5
tTTP4
tTTP3
tTTP2
tDD
LVDS Transmitter Pulse Position for bit 1
LVDS Transmitter Pulse Position for bit 0
LVDS Transmitter Pulse Position for bit 6
LVDS Transmitter Pulse Position for bit 5
LVDS Transmitter Pulse Position for bit 4
LVDS Transmitter Pulse Position for bit 3
LVDS Transmitter Pulse Position for bit 2
0
1
2
3
4
5
6
UI(4)
UI(4)
UI(4)
UI(4)
UI(4)
UI(4)
UI(4)
ns
TXCLKOUT± = 10 to 75 MHz
(see Figure 6)
TXCLKOUT± = 10 to 75 MHz
(see Figure 6)
TXCLKOUT± = 10 to 75 MHz
(see Figure 6)
TXCLKOUT± = 10 to 75 MHz
(see Figure 6)
TXCLKOUT± = 10 to 75 MHz
(see Figure 6)
TXCLKOUT± = 10 to 75 MHz
(see Figure 6)
Deserializer delay, latency(3)
(see Figure 11)
TXCLKOUT± = 10 to 75 MHz
(see Figure 6)
142 × T 143 × T
Deserializer power-down delay,
active to OFF (see Figure 13)
tTPDD
tTXZR
TXCLKOUT± = 75 MHz
TXCLKOUT± = 75 MHz
6
10
55
ns
Deserializer enable delay,
OFF to active (see Figure 14)
40
ns
CHANNEL LINK II CML INPUT
TXCLKOUT± = 10 MHz, SSCG = OFF
TXCLKOUT± = 10 MHz, SSCG = ON
TXCLKOUT± = 75 MHz, SSCG = OFF
TXCLKOUT± = 65 MHz, SSCG = ON
7
14
6
Deserializer lock time(5)
(see Figure 8)
tDDLT
ms
8
EQ = OFF
SSCG = OFF
Jitter frequency > 10 MHz
Deserializer input jitter tolerance
(see Figure 16)
tDJIT
>0.45
UI(6)
LVCMOS OUTPUTS
Deserializer low-to-high transition time
tCLH
CL = 8 pF (LOCK and PASS pins)
CL = 8 pF (LOCK and PASS pins)
10
10
15
15
ns
ns
(see Figure 4)
Deserializer high-to-low transition time
(see Figure 4)
tCHL
10 MHz
(PASS pin)
220
40
230
65
BIST PASS valid time,
BISTEN = 1 (see Figure 17)
tPASS
ns
75 MHz
(PASS pin)
(1) tDCCJ is the maximum amount of jitter between adjacent clock cycles.
(2) Specification is verified by characterization and is not tested in production.
(3) Specification is verified by design and is not tested in production.
(4) UI: Unit Interval is equivalent to one serialized data bit width in the OpenLDI parallel interface format (1 UI = 1 / [7 × CLK]). The UI
scales with clock frequency.
(5) tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active
RXCLKIN.
(6) UI – Unit Interval is equivalent to one serialized data bit width (1 UI = 1 / [28 × CLK]). The UI scales with clock frequency.
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Switching Characteristics: Deserializer (continued)
over recommended operating supply and temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SSCG MODE
Spread spectrum clocking
deviation frequency(3)
TXCLKOUT± = 10 to 65 MHz,
SSCG = ON
fDEV
±0.5%
8
±2%
Spread spectrum clocking
modulation frequency(3)
TXCLKOUT± = 10 to 65 MHz,
SSCG = ON
fMOD
100
kHz
RxIN[3:0]+
RxCLKIN+
VTL
VCM=1.2V
VTH
RxIN[3:0]-
RxClkIN-
GND
Figure 1. Channel Link DC VTH/VTL Definition
A
B
A'
C
Scope
A
B
50W
50W
C
B'
50W
50W
Figure 2. Output Test Circuit
DOUT+
VOD-
VOD+
DOUT-
GND
VOS
VOD+
0 V
(DOUT+) - (DOUT+
)
VODp-p
VOD-
Figure 3. CML Output Waveforms
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+VOD
80%
(DOUT+) - (DOUT-)
0V
20%
-VOD
tLLHT
Figure 4. CML Output Transition Times
tLHLT
Figure 5. DS92LV0421 Channel Link Receiver Strobe Positions
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Cycle N
TxCLKOUT±
TxOUT[3:0]±
bit 1 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
t
t
TTP1
TTP0
0UI
1UI
2UI
t
t
t
t
t
TTP6
TTP5
TTP4
TTP3
TTP2
3UI
4UI
5UI
6UI
Figure 6. DS92LV0422 LVDS Transmitter Pulse Positions
PDB
VIH
MIN
RxCLKIN
"X"
active
t
PLD
DOUT
(Diff.)
Driver On
Driver OFF, V
OD
= 0V
Figure 7. DS92LV0421 Lock Time
PDB
VIH(min)
R ±
IN
tDDLT
LOCK
VOH(min)
TRI-STATE
Figure 8. DS92LV0422 Lock Time
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VIL
PDB
X
MA
RxCLKIN
active
"X"
t
XZD
DOUT
(Diff.)
active
Driver OFF, V
OD
= 0V
Figure 9. DS92LV0421 Disable Time
RxIN[3:0]
RxCLKIN
N-1
N
N+1
N+2
t
SD
STOP START
BIT BIT
STOP START
BIT BIT
STOP START
STOP START
BIT BIT
STOP
BIT
BIT BIT
SYMBOL N-4
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
D
0-23
OUT
DCA, DCB
Figure 10. DS92LV0421 Latency Delay
START
BIT
STOP
BIT
START
BIT
STOP
BIT
START
BIT
STOP
BIT
START STOP
BIT BIT
SYMBOLN+3
SYMBOLN
SYMBOLN+1
SYMBOLN+2
R
IN
+/-
t
RD
TxCLKOUT
TxOUT[3:0]
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
Figure 11. DS92LV0422 Latency Delay
t
t
DJIT
DJIT
VOD (+)
DOUT
(Diff.)
TxOUT_E_O
0V
VOD (-)
t
(1 UI)
BIT
Figure 12. DS92LV0421 Output Jitter
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PDB
RIN
VILmax
X
t
TPDD
LOCK
PASS
Z
Z
TxCLKOUT
TxOUT[3:0]
Z
Z
Figure 13. DS92LV0422 Power-Down Delay
PDB
LOCK
t
TXZR
OEN
VIHmin
Z
Z
TxCLKOUT
TxOUT[3:0]
Figure 14. DS92LV0422 Enable Delay
+V
OD
RxCLKIN
-V
OD
+V
OD
RxIN[odd]
-V
OD
+V
OD
RxIN[even]
-V
OD
Cycle N
Cycle N+1
Figure 15. Checkerboard Data Pattern
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Ideal Data
Bit End
Sampling
Window
Ideal Data Bit
Beginning
V
TH
0V
RIN_TOL
Left
RIN_TOL
Right
V
TL
Ideal Center Position (t /2)
BIT
t
(1 UI)
BIT
tIJIT = RIN_TOL (Left + Right)
Sampling Window = 1 UI - t
IJIT
Figure 16. DS92LV0422 Receiver Input Jitter Tolerance
VIL
BISTEN
MAX
t
PASS
PASS
(w/ errors)
VOL
MAX
Result Held
Prior BIST Result
Current BIST Test - Toggle on Error
Figure 17. BIST PASS Waveform
SDA
t
BUF
t
t
f
HD;STA
t
t
r
LOW
t
t
SP
t
f
r
SCL
t
t
HD;STA
SU;STA
t
SU;STO
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
Figure 18. Serial Control Bus Timing Diagram
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6.11 Typical Characteristics
85
80
75
70
VODSEL = H
65
60
VODSEL = L
55
50
45
40
0
10
20
30
40
50
60
70
RxCLK (MHz)
Figure 19. Typical IDDT (1.8-V Supply)
vs RXCLKIN
Figure 20. Serializer DOUT Voltage
vs Ambient Temperature
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7 Detailed Description
7.1 Overview
The DS92LV042x chipset transmits and receives 24 bits of data and 3 control signals, formatted as Channel Link
LVDS data, over a single serial CML pair operating at 280 Mbps to 2.1 Gbps. The serial stream contains an
embedded clock, video control signals, and the DC-balance information which enhances signal quality and
supports AC coupling.
The deserializer can attain lock to a data stream without the use of a separate reference clock source, which
greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the serializer
regardless of the data pattern, delivering true automatic plug and lock performance. It can lock to the incoming
serial stream without the requirement of special training patterns or sync characters. The deserializer recovers
the clock and data by extracting the embedded clock information, validating, and then deserializing the incoming
data stream, providing a parallel Channel Link LVDS bus to the display, ASIC, or FPGA.
The DS92LV042x chipset can operate with up to 24 bits of raw data with three slower speed control bits encoded
within the serial data stream. For applications that require less than the maximum 24 raw data bits per clock
cycle, the user must ensure that all unused bit spaces or parallel LVDS channels are set to valid logic states, as
all parallel lanes and 27 bit spaces are always sampled.
7.2 Functional Block Diagrams
VODSEL
De-Emph
SSC[2:0]
OEN
VODSEL
SSCG
RxIN3+/-
RxIN2+/-
CMF
TxOUT[3]
TxOUT[2]
DOUT+
DOUT-
RxIN1+/-
RIN+
RIN-
TxOUT[1]
TxOUT[0]
TxCLKOUT
RxIN0+/-
RxCLKIN+/-
EQ
Pattern
Generator
PLL
Error
PASS
LOCK
Detector
PDB
CONFIG[1:0]
MAPSEL
PDB
SCL
SCA
ID[x]
Timing and
Control
Timing and
Control
PLL
SCL
SCA
ID[x]
BISTEN
OSS_SEL
LFMODE
BISTEN
DS92LV0422
DS92LV0421
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Figure 21. Serializer Block Diagram
Figure 22. Deserializer Block Diagram
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7.3 Feature Description
7.3.1 Parallel LVDS Data Transfer (Color Bit Mapping Select)
The DS92LV042x can be configured to accept or transmit 24-bit data with two different LVDS parallel interface
mapping schemes:
•
The normal Channel Link LVDS format (MSBs on LVDS Channel 3) can be selected by configuring the
MAPSEL pin to high. See Figure 23 for the normal Channel Link LVDS mapping.
•
An alternate mapping scheme is available (LSBs on LVDS Channel 3) by configuring the MAPSEL pin to low.
See Figure 24 for the alternate LVDS mapping.
The mapping schemes can also be selected by register control. The alternate mapping scheme is useful in some
applications where the receiving system, typically a display, requires the LSBs for the 24-bit color data to be sent
on LVDS Channel 3.
NOTE
While the LVDS parallel interface has 28 bits defined, only 27 bits are recovered by the
serializer and sent to the deserializer. This chipset supports 24-bit RGB plus the three
video control signals. The 28th bit is not sampled, sent, or recovered.
RxCLKIN +/-
Previous cycle
Current cycle
R[7]
(bit 22)
R[6]
(bit 21)
B[6]
(bit 25)
G[7]
(bit 24)
G[6]
(bit 23)
B[7]
(bit 26)
RxIN3 +/-
RxIN2 +/-
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[5]
(bit 17)
B[4]
(bit 16)
B[3]
(bit 15)
B[2]
(bit 14)
G[3]
(bit 9)
G[2]
(bit 8)
G[1]
(bit 7)
B[1]
(bit 13)
B[0]
(bit 12)
G[5]
(bit 11)
G[4]
(bit 10)
RxIN1 +/-
RxIN0 +/-
G[0]
(bit 6)
R[5]
(bit 5)
R[4]
(bit 4)
R[3]
(bit 3)
R[2]
(bit 2)
R[1]
(bit 1)
R[0]
(bit 0)
Figure 23. 8–Bit Channel Link Mapping: MSB's on RXIN3
RxCLKIN +/-
RxIN3 +/-
Previous cycle
Current cycle
R[1]
(bit 22)
R[0]
(bit 21)
B[1]
(bit 26)
B[0]
(bit 25)
G[1]
(bit 24)
G[0]
(bit 23)
DE
VS
HS
B[7]
B[6]
B[5]
B[4]
RxIN2 +/-
RxIN1 +/-
(bit 20)
(bit 19)
(bit 18)
(bit 17)
(bit 16)
(bit 15)
(bit 14)
B[3]
(bit 13)
B[2]
(bit 12)
G[7]
(bit 11)
G[6]
(bit 10)
G[5]
(bit 9)
G[4]
(bit 8)
G[3]
(bit 7)
G[2]
(bit 6)
R[7]
(bit 5)
R[6]
(bit 4)
R[5]
(bit 3)
R[4]
(bit 2)
R[3]
(bit 1)
R[2]
(bit 0)
RxIN0 +/-
Figure 24. 8–Bit Channel Link Mapping: LSB's on RXIN3
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Feature Description (continued)
7.3.2 Serial Data Transfer
The DS92LV042x chipset transmits and receives a pixel of data in the following format: C1 and C0 represent the
embedded clock in the serial stream. C1 is always high and C0 is always low. The b[23:0] contains the
scrambled RGB data. DCB is the DC-Balanced control bit. DCB is used to minimize the short and long-term DC
bias on the signal lines. This bit determines if the data is unmodified or inverted. DCA is used to validate data
integrity in the embedded data stream and can also contain encoded control (VS, HS, DE). Both DCA and DCB
coding schemes are generated by the serializer and decoded by the deserializer automatically. Figure 25
illustrates the serial stream per clock cycle.
NOTE
Figure 25 only illustrates the bits but does not actually represent the bit location, as the
bits are scrambled and balanced continuously.
b
1
0
b
1
1
D
C
A
b
0
b
1
b
2
b
3
b
5
b
9
C
1
b
4
b
6
b
7
b
8
D
C
B
b
1
2
b
1
3
b
1
4
b
1
5
b
1
6
b
1
7
b
1
8
b
1
9
b
2
0
b
2
1
b
2
2
b
2
3
C
0
Figure 25. Channel Link II Serial Stream (DS92LV042x)
7.3.3 Video Control Signal Filter
The three control bits can be used to communicate any low speed signal. The most common use for these bits is
in the display or machine vision applications. In a display application, these bits are typically assigned as: Bit 26
to DE, Bit 24 to HS, and Bit 25 to VS. In the machine vision standard, Camera Link, these bits are typically
assigned: Bit 26 to DVAL, Bit 24 to LVAL, and Bit 25 to FVAL.
When operating the devices in Normal Mode, the video control signals (DE, HS, VS) have the following
restrictions:
•
•
•
Normal Mode with Control Signal Filter Enabled:
–
DE and HS: Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 clock
cycles or longer.
Normal Mode with Control Signal Filter Disabled:
–
DE and HS: Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition
pulse.
VS: Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Glitches of a control signal can cause a visual display error, and video control signals are defined as low
frequency signals with limited transitions. Therefore, the video control signal filter feature allows for the chipset to
validate and filter out any high frequency noise on the control signals (see Figure 26).
PCLK
IN
HS/VS/DE
IN
Latency
PCLK
OUT
Pulses 1 or 2
PCLKs wide
Filtered OUT
HS/VS/DE
OUT
Figure 26. Video Control Signal Filter Waveform
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Feature Description (continued)
7.3.4 Serializer Functional Description
The serializer converts a Channel Link LVDS clock and data bus to a single serial output data stream and also
acts as a signal generator for the chipset Built-In Self Test (BIST) mode. The device can be configured through
external pins or through the optional serial control bus. The serializer features enhanced signal quality on the link
by supporting: a selectable VOD level, a selectable de-emphasis for signal conditioning, and Channel Link II data
coding that provides randomization, scrambling, and DC-balancing of the data. The serializer includes multiple
features to reduce EMI associated with display data transmission. This includes the randomization and
scrambling of the serial data and system spread spectrum clock support. The serializer includes power-saving
features with a sleep mode, auto stop clock feature, and optional LVCMOS (1.8 V or 3.3 V) I/O compatibility (see
also Optional Serial Bus Control and Built-In Self Test (BIST)).
7.3.4.1 Signal Quality Enhancers
7.3.4.1.1 Serializer VOD Select (VODSEL)
The serializer differential output voltage may be increased by setting the VODSEL pin high. When VODSEL is
low, the DC VOD is at the standard (default) level. When VODSEL is high, the VOD is increased in level. The
increased VOD is useful in extremely high noise environments and extra long cable length applications. When
using de-emphasis, TI recommends setting VODSEL = H to avoid excessive signal attenuation, especially with
the larger de-emphasis settings. This feature may be controlled by external pin or by register.
Table 1. Serializer Differential Output Voltage
INPUT
EFFECT
VODSEL
VOD (mV)
±300
VOD (mVp-p)
L
600
900
H
±450
7.3.4.1.2 Serializer De-Emphasis (DE-EMPH)
The de-emphasis pin controls the amount of de-emphasis beginning one full bit time after a logic transition that
the serializer drives. This is useful to counteract loading effects of long or lossy cables. This pin must be left
open if used for standard switching currents (no de-emphasis) or if used under register control. De-emphasis is
selected by connecting a resistor on this pin to ground, with the R value between 0.5 kΩ and 1 MΩ, or by register
setting. When using de-emphasis, TI recommends setting VODSEL = H.
Table 2. De-Emphasis Resistor Value
RESISTOR VALUE (kΩ)
DE-EMPHASIS SETTING
Open
Disabled
–12 dB
–9 dB
0.6
1
2
–6 dB
5
–3 dB
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0.00
VDD = 1.8V,
= 25oC
T
A
-2.00
-4.00
-6.00
-8.00
-10.00
-12.00
-14.00
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
R VALUE - LOG SCALE (W)
Figure 27. De-Emphasis vs R Value
7.3.4.2 EMI Reduction Features
7.3.4.2.1 Data Randomization and Scrambling
Channel Link II serializers and deserializers feature a three-step encoding process that enables the use of AC-
coupled interconnects and also helps to manage EMI. The serializer first passes the parallel data through a
scrambler which randomizes the data. The randomized data is then DC-balanced. The DC-balanced and
randomized data then goes through a bit-shuffling circuit and is transmitted out on the serial line. This encoding
process helps to prevent static data patterns on the serial stream. The resulting frequency content of the serial
stream ranges from the parallel clock frequency to the Nyquist rate. For example, if the serializer and deserializer
chipset is operating at a parallel clock frequency of 50 MHz, the resulting frequency content of the serial stream
ranges from 50 MHz to 700 MHz (50 MHz × 28 bits = 1.4 GHz / 2 = 700 MHz).
7.3.4.2.2 Serializer Spread Spectrum Compatibility
The serializer RXCLKIN is capable of tracking spread spectrum clocking (SSC) from a host source. The
RXCLKIN accepts spread spectrum tracking up to 35-kHz modulation and ±0.5, ±1, or ±2% deviations (center
spread). The maximum conditions for the RXCLKIN input are: a modulation frequency of 35 kHz and amplitude
deviations of ±2% (4% total).
7.3.4.3 Power-Saving Features
7.3.4.3.1 Serializer Power-Down Feature (PDB)
The serializer has a PDB input pin to enable or power down the device. This pin is controlled by the host and is
used to save power, disabling the link when the display is not required. In power-down mode, the high-speed
driver outputs are both pulled to VDD and present a 0-V VOD state.
NOTE
In power-down, the optional serial bus control registers are RESET.
7.3.4.3.2 Serializer Stop Clock Feature
The serializer enters a low power SLEEP state when the RXCLKIN is stopped. A STOP condition is detected
when the input clock frequency is less than 3 MHz. The clock must be held at a static low or high state. When
the RXCLKIN starts again, the serializer locks to the valid input clock and then transmits the serial data to the
deserializer.
NOTE
In STOP CLOCK SLEEP, the optional serial bus control registers values are RETAINED.
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7.3.4.3.3 Serializer 1.8-V or 3.3-V VDDIO Operation
The serializer parallel control bus can operate with 1.8-V or 3.3-V levels (VDDIO) for host compatibility. The 1.8-V
levels offers lower noise (EMI) and also system power savings.
7.3.5 Deserializer Functional Description
The deserializer converts a single input serial data stream to a Channel Link LVDS clock and data bus and also
provides a signal check for the chipset Built-In Self Test (BIST) mode. The device can be configured through
external and strap pins or through the optional serial control bus. The deserializer features enhanced signal
quality on the link by supporting an integrated equalizer on the serial input and Channel Link II data encoding
which provides randomization, scrambling, and DC-balancing of the data. The deserializer includes multiple
features to reduce EMI associated with display data transmission. This includes the randomization and
scrambling of the data, Channel Link LVDS output interface, and output spread spectrum clock generation
(SSCG) support. The deserializer includes power saving features with a power-down mode and optional
LVCMOS (1.8-V) interface compatibility.
7.3.5.1 Signal Quality Enhancers
7.3.5.1.1 Deserializer Input Equalizer Gain (EQ)
The deserializer can enable receiver input equalization of the serial stream to increase the eye opening to the
deserializer input.
NOTE
This function cannot be seen at the RXIN± input. The equalization feature may be
controlled by the external pin or by register.
Table 3. Receiver Equalization Configuration
EQ (STRAP OPTION)
EFFECT
~1.625 dB (OFF)
~13 dB
L
H
7.3.5.2 EMI Reduction Features
7.3.5.2.1 Deserializer VOD Select (VODSEL)
The differential output voltage of the Channel Link parallel interface is controlled by the VODSEL input.
Table 4. Deserializer Differential Output Voltage
INPUT
EFFECT
VODSEL
VOD (mV)
±250
VOD (mVp-p)
L
500
800
H
±400
7.3.5.2.2 Deserializer Common-Mode Filter Pin (CMF) (Optional)
The deserializer provides access to the center tap of the internal termination. A capacitor may be placed on this
pin for additional common-mode filtering of the differential pair. This can be useful in high-noise environments for
additional noise rejection capability. A 4.7-µF capacitor may be connected from this pin to Ground.
7.3.5.2.3 Deserializer SSCG Generation (Optional)
The deserializer provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both
clock and data outputs are modulated. This aids to lower system EMI. Output SSCG deviations of ±2% (4% total)
at up to 100-kHz modulations are available (see Table 5). This feature may be controlled by external pins or by
register.
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NOTE
The deserializer supports the SSCG function with TXCLKOUT = 10 MHz to 65 MHz.
When the TXCLKOUT = 65 MHz to 75 MHz, it is required to disable the SSCG function
(SSC[2:0] = 000).
Frequency
fdev(max)
F
F
PCLK+
F
PCLK
fdev(min)
Time
PCLK-
1/fmod
Figure 28. SSCG Waveform
Table 5. SSCG Configuration (LFMODE = L): Deserializer Output
SSC[2:0] INPUTS
RESULT
LFMODE = L (20 TO 65 MHz)
SSC2
SSC1
SSC0
fdev (%)
Off
fmod (kHz)
L
L
L
L
L
H
L
Off
±0.9
±1.2
±1.9
±2.3
±0.7
±1.3
±1.7
L
H
H
L
CLK/2168
CLK/1300
L
H
L
H
H
H
H
L
H
L
H
H
H
Table 6. SSCG Configuration (LFMODE = H): Deserializer Output
SSC[2:0] INPUTS
RESULT
LFMODE = H (10 TO 20 MHz)
SSC2
SSC1
SSC0
fdev (%)
Off
fmod (kHz)
L
L
L
L
L
H
L
Off
±0.7
±1.3
±1.8
±2.2
±0.7
±1.2
±1.7
L
H
H
L
CLK/625
CLK/385
L
H
L
H
H
H
H
L
H
L
H
H
H
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7.3.5.2.4 Power-Saving Features
7.3.5.2.4.1 Deserializer Power-Down Feature (PDB)
The deserializer has a PDB input pin to enable or power down the device. This pin can be controlled by the
system to save power, disabling the deserializer when the display is not required. An auto-detect mode is also
available. In this mode, the PDB pin is tied high and the deserializer enters power-down when the serial stream
stops. When the serial stream starts up again, the deserializer locks to the input stream, asserts the LOCK pin,
and outputs valid data. In power-down mode, the LVDS data and clock output states are determined by the
OSS_SEL status.
NOTE
In power-down, the optional serial bus control registers are RESET.
7.3.5.2.4.2 Deserializer Stop Stream SLEEP Feature
The deserializer enters a low power SLEEP state when the input serial stream is stopped. A STOP condition is
detected when the embedded clock bits are not present. When the serial stream starts again, the deserializer
then locks to the incoming signal and recovers the data.
NOTE
In STOP STREAM SLEEP, the optional serial bus control registers values are RETAINED.
7.3.5.2.4.3 Deserializer 1.8-V or 3.3-V VDDIO Operation
The deserializer parallel control bus can operate with 1.8-V or 3.3-V levels (VDDIO) for target (display)
compatibility. The 1.8-V levels offers lower noise (EMI) and also system power savings.
7.3.5.3 Deserializer Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN), and Output State
Select (OSS_SEL)
When PDB is driven high, the CDR PLL begins locking to the serial input, and LOCK goes from TRI-STATE to
low (depending on the value of the OSS_SEL setting). After the DS92LV0422 completes its lock sequence to the
input serial data, the LOCK output is driven high, indicating valid data and clock recovered from the serial input is
available on the Channel Link outputs. The TXCLKOUT output is held at its current state at the change from
OSC_CLK (if this is enabled through OSC_SEL) to the recovered clock (or vice versa).
NOTE
The Channel Link outputs may be held in an inactive state (TRI-STATE) through the use
of the Output Enable pin (OEN).
If there is a loss of clock from the input serial stream, LOCK is driven low and the state of the outputs are based
on the OSS_SEL setting (configuration pin or register).
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Table 7. PDB, OEN, and OSS_SEL Configuration (Deserializer Outputs)
INPUTS
OUTPUTS
SERIAL
INPUT
PDB
OEN
OSS_SEL LOCK
OTHER OUTPUTS
TXCLKOUT is TRI-STATE
X
L
X
X
L
X
L
X
L
TXOUT[3:0] are TRI-STATE
PASS is TRI-STATE
TXCLKOUT is TRI-STATE
TXOUT[3:0] are TRI-STATE
PASS is HIGH
Static
Static
Static
Active
H
H
H
H
TXCLKOUT is TRI-STATE
TXOUT[3:0] are TRI-STATE
PASS is TRI-STATE
H
H
X
L
TXCLKOUT is TRI-STATE or Oscillator Output through Register bit
TXOUT[3:0] are TRI-STATE
PASS is TRI-STATE
H
L
L
TXCLKOUT is TRI-STATE
TXOUT[3:0] are TRI-STATE
PASS is Active
H
TXCLKOUT is Active
TXOUT[3:0] are Active
PASS is Active
Active
H
H
X
H
(Normal operating mode)
7.3.5.4 Deserializer Oscillator Output (Optional)
The deserializer provides an optional clock output when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled
by external pin or by register.
PDB
RIN
active serial stream
X
(Diff.)
H
H
LOCK
TxOUT[3:0]
TxCLKOUT
L
L
L
Z
Z
Z
Z
Z
Z
f
f
Z
Z
PASS
OFF
Active
OSC Output
Active
OFF
OSC Output
CONDITIONS: OEN = H, OSS_SEL = H, and OSC_SEL not equal to 000.
Figure 29. TXCLKOUT Output Oscillator Option Enabled
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7.3.6 Built-In Self Test (BIST)
An optional at-speed Built-In Self Test (BIST) feature supports the testing of the high-speed serial link. This is
useful in the prototype stage, equipment production, in-system test, and for system diagnostics. In BIST mode,
only an input clock is required along with control to the serializer and deserializer BISTEN input pins. The
serializer outputs a test pattern (PRBS-7) and drives the link at speed. The deserializer detects the PRBS-7
pattern and monitors it for errors. A PASS output pin toggles to flag any payloads that are received with 1 to 24
errors. Upon completion of the test, the result of the test is held on the PASS output until reset (new BIST test or
power-down). A high on PASS indicates NO ERRORS were detected. A low on PASS indicates one or more
errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN
pin.
Inter-operability is supported between this Channel Link II device and all Channel Link II generations (Gen 1/2/3);
see respective data sheets for details on entering BIST mode and control.
7.3.6.1 Sample BIST Sequence
See Figure 30 for the BIST mode flow diagram.
Step 1: Place the serializer in BIST Mode by setting serializer BISTEN = H. BIST Mode is enabled through the
BISTEN pin. An RXCLKIN is required for BIST. When the deserializer detects the BIST mode pattern and
command (DCA and DCB code), the data and control signal outputs are shut off.
Step 2: Place the deserializer in BIST mode by setting the BISTEN = H. The deserializer is now in BIST mode
and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS pin
switches low for one half of the clock period. During the BIST test, the PASS output can be monitored and
counted to determine the payload error rate.
Step 3: To stop BIST mode, the deserializer BISTEN pin is set low. The deserializer stops checking the data, and
the final test result is held on the PASS pin. If the test ran error free, the PASS output is high. If there is one or
more errors detected, the PASS output is low. The PASS output state is held until a new BIST is run, the device
is RESET, or powered down. The BIST duration is user controlled by the duration of the BISTEN signal.
Step 4: To return the link to normal operation, the serializer BISTEN input is set low. The link returns to normal
operation.
Figure 31 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error-free, and Case 2
shows one with multiple errors. In most cases, it is difficult to generate errors due to the robustness of the link
(differential data transmission and so forth), thus they may be introduced by greatly extending the cable length,
faulting the interconnect, or reducing signal condition enhancements (de-emphasis, VODSEL, or Rx
equalization).
Normal
Step 1: SER in BIST
BIST
Wait
Step 2: Wait, DES in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: SER in Normal
Figure 30. BIST Mode Flow Diagram
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BISTEN
(Serializer)
BISTEN
(Deserializer)
TxCLKOUT
(Diff.)
TxOUT[3:0]
(Diff.)
DATA
(internal)
PASS
Prior Result
Prior Result
PASS
FAIL
X = bit error(s)
DATA
(internal)
X
X
X
PASS
BIST
Result
Normal
PRBS
Normal
BIST Test
BIST Duration
Held
Figure 31. BIST Waveforms
7.3.6.2 BER Calculations
It is possible to calculate the approximate Bit Error Rate (BER). The following is required:
•
•
•
Clock Frequency (MHz)
BIST Duration (seconds)
BIST Test Result (PASS)
The BER is less than or equal to one over the product of 24 times the RXCLKIN rate times the test duration. If
we assume a 65-MHz clock, a 10-minute (600 seconds) test, and a PASS, the BER is ≤ 1.07 × 10E-12.
BIST mode runs a check on the data payload bits. The LOCK pin also provides a link status. If the recovery of
the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK pin switches low. The combination
of the LOCK and at-speed BIST PASS pin provides a powerful tool for system evaluation and performance
monitoring.
7.3.7 Optional Serial Bus Control
The serializer and deserializer may also be configured by the use of a serial control bus that is I2C protocol-
compatible. By default, the I2C Reg 0x00 = 0x00, and all configuration is set by control or strap pins. Writing Reg
0x00 = 0x01 enables or allows configuration by registers; this overrides the control or strap pins. Multiple devices
may share the serial control bus, because multiple addresses are supported (see Figure 32).
The serial bus is comprised of three pins. The SCL is a serial bus clock input. The SDA is the serial bus data
input or output signal. Both SCL and SDA signals require an external pullup resistor to VDDIO. For most
applications, a 4.7-kΩ pullup resistor to VDDIO may be used. The resistor value may be adjusted for capacitive
loading and data rate requirements. The signals are either pulled high or driven low.
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1.8V
10k
3.3V
ID[X]
4.7k
4.7k
R
ID
DS92LV0421/
DS92LV0422
SCL
HOST
SCL
SDA
SDA
To other
Devices
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Figure 32. Serial Control Bus Connection
The third pin is the ID[X] pin. This pin sets one of four possible device addresses. Two different connections are
possible:
•
•
The pin may be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ resistor.
The pin may be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ resistor and pulled down to ground with a
recommended value RID resistor. This creates a voltage divider that sets the other three possible addresses.
See Table 8 for the serializer and Table 9 for the deserializer. Do not tie ID[X] directly to VSS.
Table 8. ID[X] Resistor Value: DS92LV0421 (Serializer)
RESISTOR
RID kΩ(1)
(5% TOL)
ADDRESS
8'b
0 APPENDED (WRITE)
ADDRESS
7'b
0.47
2.7
7b' 110 1001 (h'69)
7b' 110 1010 (h'6A)
7b' 110 1011 (h'6B)
7b' 110 1110 (h'6E)
8b' 1101 0010 (h'D2)
8b' 1101 0100 (h'D4)
8b' 1101 0110 (h'D6)
8b' 1101 1100 (h'DC)
8.2
Open
(1) RID ≠ 0 Ω. Do not connect directly to VSS (GND). This is not a valid address.
Table 9. ID[X] Resistor Value – DS92LV0422 (Deserializer)
RESISTOR
RID kΩ(1)
(5% TOL)
ADDRESS
8'b
0 APPENDED (WRITE)
ADDRESS
7'b
0.47
2.7
7b' 111 0001 (h'71)
7b' 111 0010 (h'72)
7b' 111 0011 (h'73)
7b' 111 0110 (h'76)
8b' 1110 0010 (h'E2)
8b' 1110 0100 (h'E4)
8b' 1110 0110 (h'E6)
8b' 1110 1100 (h'EC)
8.2
Open
(1) RID ≠ 0 Ω. Do not connect directly to VSS (GND). This is not a valid address.
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The serial bus protocol is controlled by START, START-repeated, and STOP phases. A START occurs when
SCL transitions low while SDA is high. A STOP occurs when SDA transitions high while SCL is also high (see
Figure 33).
SDA
SCL
S
P
START condition, or
STOP condition
START repeat condition
Figure 33. START and STOP Conditions
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match the slave address of a device, it Not-acknowledges (NACKs) the master by letting SDA be pulled high.
ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs
after every data byte is successfully received. When the master is reading data, the master ACKs after every
data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a start condition or a repeated start condition. All communication on the bus ends with a stop
condition. A READ is shown in Figure 34 and a WRITE is shown in Figure 35.
NOTE
During initial power-up, a delay of 10 ms is required before the I2C responds.
If the serial bus is not required, the three pins may be left open (NC).
Register Address
Slave Address
Slave Address
Data
a
c
k
a
c
k
a
c
k
a
c
k
A
2
A
1
A
0
A
2
A
1
A
0
0
S
S
1
P
Figure 34. Serial Control Bus: READ
Register Address
Slave Address
Data
a
c
k
a
c
k
a
c
k
A A A
2 1 0
0
S
P
Figure 35. Serial Control Bus: WRITE
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7.4 Device Functional Modes
7.4.1 Serializer and Deserializer Operating Modes and Reverse Compatibility (CONFIG[1:0])
The DS92LV042x chipset is compatible with other single serial lane Channel Link II or FPD-Link II devices.
Configuration modes are provided for reverse compatibility with the DS90C241 or DS90C124 chipset (FPD-Link
II Generation 1) and also the DS90UR241 / DS90UR124 chipset (FPD-Link II Generation 2) by setting the
respective mode with the CONFIG[1:0] pins on the serializer or deserializer as shown in Table 10 and Table 11.
This selection also determines whether the control signal filter feature is enabled or disabled in the normal mode.
This feature may be controlled by external pin or by register.
Table 10. DS92LV0421 Serializer Modes
CONFIG1
CONFIG0
MODE
COMPATIBLE DESERIALIZER DEVICE
DS92LV0422, DS92LV0412,
DS92LV2422, DS92LV2412
L
L
Normal Mode, Control Signal Filter disabled
DS92LV0422, DS92LV0412,
DS92LV2422, DS92LV2412
L
H
Normal Mode, Control Signal Filter enabled
H
H
L
Reverse Compatibility Mode (FPD-Link II, GEN2)
Reverse Compatibility Mode (FPD-Link II, GEN1)
DS90UR124, DS99R124Q-Q1
DS90C124
H
Table 11. DS92LV0422 Deserializer Modes
CONFIG1
CONFIG0
MODE
COMPATIBLE SERIALIZER DEVICE
DS92LV0421, DS92LV0411,
DS92LV2421, DS92LV2411
L
L
Normal Mode, Control Signal Filter disabled
DS92LV0421, DS92LV0411,
DS92LV2421, DS92LV2411
L
H
Normal Mode, Control Signal Filter enabled
H
H
L
Reverse Compatibility Mode (FPD-Link II, GEN2)
Reverse Compatibility Mode (FPD-Link II, GEN1)
DS90UR241, DS99R421
DS90C241
H
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7.5 Register Maps
Table 12. SERIALIZER: Serial Bus Control Registers
ADD
(DEC)
ADD
(HEX)
REGISTER
NAME
DEFAULT
(BIN)
BIT(S)
R/W
R/W
R/W
FUNCTION
Reserved
MAPSEL
DESCRIPTION
7
6
0
Reserved
0: LSB on RXIN3
1: MSB on RXIN3
0
0: Low
1: High
5
4
R/W
R/W
0
0
VODSEL
Reserved
Reserved
00: Normal Mode, Control Signal Filter Disabled
01: Normal Mode, Control Signal Filter Enabled
10: DS90UR124, DS99R124Q-Q1 Reverse-
Compatibility Mode (FPD-Link II, GEN2)
11: DS90C124 Reverse-Compatibility Mode (FPD-
Link II, GEN1)
Serializer
Config 1
0
0
3:2
R/W
00
CONFIG
Note – not the same function as PowerDown (PDB)
0: Normal Mode
1
R/W
0
SLEEP
1: Sleep Mode – Register settings retained.
0: Configurations set from control pins
0
7
R/W
R/W
0
0
REG
1: Configuration set from registers (except I2C_ID)
0: Address from ID[X] Pin
1: Address from Register
REG ID
Serial Bus Device ID, four IDs are:
7b '1101 001 (h'69)
7b '1101 010 (h'6A)
7b '1101 011 (h'6B)
7b '1101 110 (h'6E)
1
1
Device ID
6:0
7:5
R/W
R/W
1101000
ID[X]
All other addresses are reserved.
000: set by external resistor
001: –1 dB
010: –2 dB
De-Emphasis 011: –3.3 dB
000
Setting
100: –5 dB
101: –6.7 dB
110: –9 dB
111: –12 dB
De-Emphasis
Control
2
2
De-Emphasis 0: De-emphasis Enabled
4
R/W
R/W
0
EN
1: De-emphasis Disabled
3:0
0000
Reserved
Reserved
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Table 13. DESERIALIZER: Serial Bus Control Registers
ADD
(DEC)
ADD
(HEX)
REGISTER
NAME
DEFAULT
(BIN)
BIT(S)
R/W
FUNCTION
DESCRIPTION
0: 20 to 65 MHz SSCG Operation
1: 10 to 20 MHz SSCG Operation
7
R/W
0
LFMODE
Channel Link Map Select
0: LSB on TXOUT3±
1: MSB on TXOUT3±
6
R/W
0
MAPSEL
5
4
R/W
R/W
0
0
Reserved
Reserved
Reserved
Reserved
00: Normal Mode, Control Signal Filter Disabled
01: Normal Mode, Control Signal Filter Enabled
10: DS90UR241, DS99R421 Reverse-Compatibility
Mode (FPD-Link II, GEN2)
Deserializer
Config 1
0
0
3:2
R/W
00
CONFIG
11: DS90C241 Reverse-Compatibility Mode (FPD-
Link II, GEN1)
Note – not the same function as PowerDown (PDB)
0: Normal Mode
1
R/W
0
SLEEP
1: Sleep Mode – Register settings retained.
0: Configurations set from control or strap pins
1: Configuration set from registers (except I2C_ID)
0
7
R/W
R/W
0
0
REG Control
REG ID
0: Address from ID[X] Pin
1: Address from Register
Serial Bus Device ID, four IDs are:
7b' 111 0001 (h'71)
7b' 111 0010 (h'72)
7b' 111 0011 (h'73)
7b' 111 0110 (h'76)
1
1
Device ID
6:0
7
R/W
1110000
0
ID[X]
OEN
All other addresses are reserved.
Output Enable Input
See Table 7
R/W
Output Sleep State Select
See Table 7
6
R/W
R/W
0
OSS_SEL
5:4
00
Reserved
Reserved
Differential LVDS Driver Output Voltage Select
0: LVDS VOD is ±250 mV, 500 mVp-p (typ)
1: LVDS VOD is ±400 mV, 800 mVp-p (typ)
3
R/W
0
VODSEL
Deserializer
Features 1
2
2
000: OFF
001: Reserved
010: 25 MHz ± 40%
011: 16.7 MHz ± 40%
100: 12.5 MHz ± 40%
101: 10 MHz ± 40%
110: 8.3 MHz ± 40%
111: 6.3 MHz ± 40%
2:0
R/W
000
OSC_SEL
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Table 13. DESERIALIZER: Serial Bus Control Registers (continued)
ADD
(DEC)
ADD
(HEX)
REGISTER
NAME
DEFAULT
(BIN)
BIT(S)
R/W
FUNCTION
DESCRIPTION
000: ~1.625 dB
001: ~3.25 dB
010: ~4.87 dB
011: ~6.5 dB
100: ~8.125 dB
101: ~9.75 dB
110: ~11.375 dB
111: ~13 dB
7:5
R/W
000
EQ Gain
0: EQ = disabled
1: EQ = enabled
4
3
R/W
R/W
0
0
EQ Enable
Reserved
Reserved
If LFMODE = 0 then:
000: SSCG OFF
Deserializer
Features 2
3
3
001: fdev = ±0.9%, fmod = CLK/2168
010: fdev = ±1.2%, fmod = CLK/2168
011: fdev = ±1.9%, fmod = CLK/2168
100: fdev = ±2.3%, fmod = CLK/2168
101: fdev = ±0.7%, fmod = CLK/1300
110: fdev = ±1.3%, fmod = CLK/1300
111: fdev = ±1.7%, fmod = CLK/1300
If LFMODE = 1, then:
2:0
R/W
000
SSC
001: fdev = ±0.7%, fmod = CLK/625
010: fdev = ±1.3%, fmod = CLK/625
011: fdev = ±1.8%, fmod = CLK/625
100: fdev = ±2.2%, fmod = CLK/625
101: fdev = ±0.7%, fmod = CLK/385
110: fdev = ±1.2%, fmod = CLK/385
111: fdev = ±1.7%, fmod = CLK/385
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Display Application
The DS92LV042x chipset is intended for interface between a host (graphics processor) and a display. It supports
a 24-bit color depth (RGB888) and up to 1024 × 768 display formats. In a RGB888 application, 24 color bits
(R[7:0], G[7:0], and B[7:0]), Pixel Clock (PCLK), and three control bits (VS, HS, and DE) are supported across
the serial link with RXCLKIN rates from 10 to 75 MHz. The chipset may also be used in 18-bit color applications.
In this application, three to six general-purpose signals may also be sent from host to display.
8.1.2 Live Link Insertion
The serializer and deserializer devices support live link or cable hot plug applications. The automatic receiver
lock to random data plug and go hot insertion capability allows the DS92LV0422 to attain lock to the active data
stream during a live insertion event.
8.1.3 Alternate Color or Data Mapping
Color-mapped data pin names are provided to specify a recommended mapping for 24-bit and 18-bit
applications. Seven (7) is assumed to be the MSB, and Zero (0) is assumed to be the LSB. While this is
recommended, it is not required. When connecting to earlier generations of FPD-Link II serializer and deserializer
devices, a color mapping review is recommended to ensure the correct connectivity is obtained. Table 14
provides examples for interfacing between DS92LV0421 and different deserializers. Table 15 provides examples
for interfacing between DS92LV0422 and different serializers.
Table 14. Serializer Alternate Color or Data Mapping
CHANNEL
LINK
RGB (LSB
EXAMPLE)
BIT NUMBER
DS92LV2422
DS90UR124
DS99R124Q-Q1
DS90C124
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
B1
B0
G1
G0
R1
R0
DE
VS
HS
B7
B6
B5
B4
B1
B0
G1
G0
R1
R0
DE
VS
HS
B7
B6
B5
B4
RXIN3
N/A
N/A
N/A
ROUT20
ROUT19
ROUT18
ROUT17
ROUT16
ROUT15
ROUT14
ROUT20
ROUT19
ROUT18
ROUT17
ROUT16
ROUT15
ROUT14
RXIN2
TXOUT2
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Application Information (continued)
Table 14. Serializer Alternate Color or Data Mapping (continued)
CHANNEL
LINK
RGB (LSB
EXAMPLE)
BIT NUMBER
DS92LV2422
DS90UR124
DS99R124Q-Q1
DS90C124
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
B3
B2
G7
G6
G5
G4
G3
G2
R7
R6
R5
R4
R3
R2
B3
B2
G7
G6
G5
G4
G3
G2
R7
R6
R5
R4
R3
R2
ROUT13
ROUT12
ROUT11
ROUT10
ROUT9
ROUT13
ROUT12
ROUT11
ROUT10
ROUT9
RXIN1
TXOUT1
ROUT8
ROUT8
ROUT7
ROUT7
ROUT6
ROUT6
ROUT5
ROUT5
ROUT4
ROUT4
RXIN0
ROUT3
TXOUT0
ROUT3
ROUT2
ROUT2
ROUT1
ROUT1
ROUT0
ROUT0
ROUT23(1)
ROUT22(1)
ROUT21(1)
OS2(1)
OS1(1)
OS0(1)
ROUT23(1)
ROUT22(1)
ROUT21(1)
N/A
N/A
N/A
N/A
DS92LV0421
SETTINGS
MAPSEL = 0
CONFIG[1:0] = 00
CONFIG[1:0] = 10
CONFIG[1:0] = 11
(1) These bits are not supported by the DS92LV0421.
Table 15. Deserializer Alternate Color or Data Mapping
CHANNEL
LINK
RGB (LSB
EXAMPLE)
BIT NUMBER
DS92LV2421
DS90UR241
DS99R421
DS90C241
Bit 26
Bit 25
Bit 24
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
B1
B1
B0
G1
G0
R1
R0
DE
VS
HS
B7
B6
B5
B4
B3
B2
G7
G6
G5
G4
G3
B0
G1
TXOUT3
N/A
N/A
N/A
G0
R1
R0
DE
VS
DIN20
DIN19
DIN18
DIN17
DIN16
DIN15
DIN14
DIN13
DIN12
DIN11
DIN10
DIN9
DIN20
DIN19
DIN18
DIN17
DIN16
DIN15
DIN14
DIN13
DIN12
DIN11
DIN10
DIN9
HS
B7
TXOUT2
RXIN2
B6
B5
B4
B3
B2
G7
TXOUT1
G6
RXIN1
G5
Bit 8
G4
DIN8
DIN8
Bit 7
G3
DIN7
DIN7
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Table 15. Deserializer Alternate Color or Data Mapping (continued)
CHANNEL
LINK
RGB (LSB
EXAMPLE)
BIT NUMBER
DS92LV2421
DS90UR241
DS99R421
DS90C241
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
G2
R7
R6
R5
R4
R3
R2
G2
R7
R6
R5
R4
R3
R2
DIN6
DIN5
DIN6
DIN5
DIN4
DIN4
TXOUT0
DIN3
RXIN0
DIN3
DIN2
DIN2
DIN1
DIN1
DIN0
DIN0
DIN23(1)
DIN22(1)
DIN21(1)
OS2(1)
OS1(1)
OS0(1)
DIN23(1)
DIN22(1)
DIN21(1)
N/A
N/A
N/A
N/A
DS92LV0422
SETTINGS
MAPSEL = 0
CONFIG[1:0] = 00
CONFIG[1:0] = 10
CONFIG[1:0] = 11
(1) These bits are not supported by the DS92LV0422.
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8.2 Typical Application
8.2.1 DS92LV0421 Typical Connection
Figure 36 shows a typical application of the DS92LV0421 serializer in pin control mode for a 24-bit application.
The LVDS inputs require external 100-Ω differential termination resistors. The CML outputs require 0.1-µF, AC-
coupling capacitors to the line. The line driver includes internal termination. Bypass capacitors are placed near
the power supply pins. At a minimum, four 0.1-µF capacitors and a 4.7-µF capacitor must be used for local
device bypassing. Ferrite beads are placed on the power lines for effective noise suppression. System GPO
(General Purpose Output) signals control the PDB and BISTEN pins. A delay cap is placed on the PDB signal to
delay the enabling of the device until power is stable.
The application assumes connection to the companion deserializer (DS92LV0422), and therefore the
configuration pins CONFIG[1:0] are also both tied low. In this example, the cable is long, and therefore the
VODSEL pin is tied high and a De-Emphasis value is selected by the resistor R1. The interface to the host is
with 1.8-V LVCMOS levels, thus the VDDIO pin is connected also to the 1.8-V rail. The optional serial bus control
is not used in this example, thus the SCL, SDA and ID[X] pins can be left open.
DS92LV0421
1.8V
VDDIO
VDDIO
VDDTX
VDDHS
C10 C8
C9
C11
FB1
C3
C4
FB2
VDDP
VDDL
C12
C5
C6
FB3
FB4
RxCLKIN-
RxCLKIN+
RxIN3-
RxIN3+
VDDRX
Channel Link
Interface
RxIN2-
RxIN2+
C7
FB5
LVDS
100 W Terminations
RxIN1-
RxIN1+
RxIN0-
RxIN0+
C1
C2
Serial
Channel Link II
Interface
DOUT+
DOUT-
1.8V
10k
ID[X]
SCL
SDA
RID
VDDIO
VODSEL
De-Emph
R1
Host
Control
BISTEN
PDB
NOTE:
R
C1-C2 = 0.1 mF (50 WV)
C3-C9 = 0.1 mF
C10-C12 = 4.7 mF
C13 = >10 mF
RES7
RES6
RES5
RES4
RES3
RES2
C13
CONFIG1
CONFIG0
MAPSEL
R = 10 kW
R1 (cable insertion loss specific)
RID (see ID[x] Resistor Value Table)
FB1-FB5: Impedance = 1 kW,
low DC resistance (<1W)
RES1
RES0
DAP (GND)
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Figure 36. DS92LV0421 Typical Connection Diagram
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Typical Application (continued)
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 16 as the input parameters.
Table 16. Design Parameters
PARAMETER
VDDIO
VALUE
1.8 V or 3.3 V
1.8 V
VDDL, VDDP, VDDHS, VDDTX, VDDRX
AC Coupling Capacitor for DOUT±
100 nF
8.2.1.2 Detailed Design Procedure
The DOUT± outputs require 100-nF, AC-coupling capacitors to the line. Channel-Link data input pairs require an
external 100-Ω termination for standard LVDS levels. The power supply filter capacitors are placed near the
power supply pins. A smaller capacitance capacitor must be placed closer to the power supply pins. Adding a
ferrite bead is optional, and if used, TI recommends using a ferrite bead with 1-kΩ impedance and low DC
resistance (less than 1 Ω). The VODSEL pin is tied to VDDIO for long cable applications. The de-emphasis pin
may connect a resistor to Ground (see Table 2). The PDB and BISTEN pins are assumed to be controlled by a
microprocessor. The PDB must remain in a low state until all power supply voltages reach the final voltage. The
CONFIG[1:0] pins are set depending on operating modes and backward compatibility (see Table 10). The
MAPSEL pin sets the mapping scheme (see Figure 23 and Figure 24). The SCL, SDA, and ID[X] pins can be left
open when these serial bus control pins are unused. The RES[7:0] pins and DAP must be tied to Ground.
8.2.1.3 Application Curves
Figure 38. Serializer CML Output Stream,
RXCLKIN = 65 MHz, VODSEL = H
Figure 37. Serializer CML Output Stream,
RXCLKIN = 65 MHz, VODSEL = L
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8.2.2 DS92LV0422 Typical Application
Figure 39 shows a typical application of the DS92LV0422 for a 24-bit application. The CML inputs require 0.1-µF,
AC-coupling capacitors to the line, and the receiver provides internal termination. Bypass capacitors are placed
near the power supply pins. At a minimum, four 0.1-µF capacitors and a 4.7-µF capacitor must be used for local
device bypassing. Ferrite beads are placed on the power lines for effective noise suppression. System GPO
(General Purpose Output) signals control the PDB and BISTEN pins. A delay cap is placed on the PDB signal to
delay the enabling of the device until power is stable.
The application assumes connection to the companion serializer (DS92LV0421), and therefore the configuration
pins CONFIG[1:0] are also both tied low. The interface to the host is with 1.8-V LVCMOS levels, thus the VDDIO
pin is connected also to the 1.8-V rail. The optional serial bus control is not used in this example, thus the SCL,
SDA, and ID[X] pins can be left open.
DS92LV0422
3.3V
1.8V
FB4
FB1
VDDL
VDDTX
C6
C7
C11
C3
C4
C8
C12
C9
VDDL
FB2
VDDIO
FB5
VDDA
VDDA
VDDIO
C13
C10
FB3
VDDP
C5
VDDSC
VDDSC
TxCLKOUT+
TxCLKOUT-
C1
C2
TxOUT3+
TxOUT3-
TxOUT2+
TxOUT2-
TxOUT1+
TxOUT1-
TxOUT0+
TxOUT0-
RIN+
Serial
Channel Link II
Interface
Channel
Link
Interface
RIN-
CMF
C15
BISTEN
PDB
Host
Control
LOCK
PASS
R
C14
1.8V
OEN
OSS_SEL
LFMODE
VODSEL
MAPSEL
10k
RID
ID[X]
SCL
SDA
C1 - C2 = 0.1 mF (50 WV)
C3 œ C10 = 0.1 mF
C11 - C13 = 4.7 mF
C14, C15 = >10 mF
R = 10 kW
RID (See ID[x] Resistor Value Table)
FB1 - FB5: Impedance = 1 kW
Low DC resistance ( <1W)
CONFIG1
CONFIG0
RES
GND
8
SSC[2]
SSC[1]
SSC[0]
DAP (GND)
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Figure 39. DS92LV0422 Typical Connection Diagram
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8.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 17 as the input parameters.
Table 17. Design Parameters
PARAMETER
VDDIO
VALUE
1.8 V or 3.3 V
1.8 V
VDDL, VDDP, VDDSC, VDDA
VDDTX
3.3 V
AC Coupling Capacitor for RIN±
100 nF
8.2.2.2 Detailed Design Procedure
The RIN± inputs require 100-nF, AC-coupling capacitors to the line. The power supply filter capacitors are placed
near the power supply pins. A smaller capacitance capacitor must be placed closer to the power supply pins. The
device has one configuration pin (EQ) called a strap pin, which is pulled down by default. For a high state, use a
10-kΩ resistor pullup to VDDIO. The PDB and BISTEN pins are assumed to be controlled by a microprocessor.
The PDB must remain in a low state until all power supply voltages reach the final voltage. The SCL, SDA, and
ID[X] pins can be left open when these serial bus control pins are unused. The RES pin and DAP must be tied to
Ground.
8.2.2.3 Application Curves
Çime (4 ns/5Lë)
Çime (4 ns/5Lë)
Figure 40. LVDS Parallel Output Data and Clock,
PRBS-7, TXCLKOUT = 75 MHz, VODSEL = L
Figure 41. LVDS Parallel Output Data and Clock,
PRBS-7, TXCLKOUT = 75 MHz, VODSEL = H
9 Power Supply Recommendations
The VDD (VDDn and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. If slower than 1.5 ms,
a capacitor on the PDB pin is required to ensure PDB arrives after all the VDD supplies have settled to the
recommended operating voltage. When the PDB pin is pulled to VDDIO, TI recommends using a 10-kΩ pullup and
a 22-µF cap to Ground to delay the PDB input signal.
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10 Layout
10.1 Layout Guidelines
Circuit board layout and stack-up for the LVDS serializer and deserializer devices must be designed to provide
low-noise power feed to the device. Good layout practice also separates high frequency or high-level inputs and
outputs to minimize unwanted stray noise pickup, feedback, and interference. Power system performance may
be greatly improved by using thin dielectrics (2 to 4 mils) for power or ground sandwiches. This arrangement
provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven
especially effective at high frequencies and makes the value and placement of external bypass capacitors less
critical. External bypass capacitors must include both RF ceramic and tantalum electrolytic types. RF capacitors
may use values in the range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2-µF to 10-µF range.
Voltage rating of the tantalum capacitors must be at least 5x the power supply voltage being used.
Surface-mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, place the smaller value closer to the pin. A large bulk capacitor is recommended at the point of power
entry. This is typically in the 50-µF to 100-µF range and smooths low frequency switching noise. TI recommends
connecting power and ground pins directly to the power and ground planes with bypass capacitors connected to
the plane, with vias on both ends of the capacitor. Connecting power or ground pins to an external bypass
capacitor increases the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four-layer board with a power and ground plane. Place LVCMOS signals away from the CML lines
to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ω are
typically recommended for LVDS interconnects. The closely coupled lines help to ensure that coupled noise
appears as common mode and thus is rejected by the receivers. The tightly coupled lines also radiate less.
10.1.1 WQFN (LLP) Stencil Guidelines
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the LLP (WQFN) package is highly recommended to
improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in Figure 42 and
Figure 43.
Figure 42. No Pullback LLP, Single Row Reference Diagram
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Layout Guidelines (continued)
Table 18. No Pullback LLP Stencil Aperture Summary for DS92LV0421 and DS92LV0422
NUMBER OF
DAP
APERTURE
OPENINGS
PCB I/O
PAD SIZE
(mm)
PCB
PITCH
(mm)
STENCIL I/O
APERTURE
(mm)
STENCIL DAP
APERTURE
(mm)
GAP BETWEEN
DAP APERTURE
(Dim A mm)
PIN
COUNT
MKT
DWG
PCB DAP
SIZE (mm)
DEVICE
DS92LV0421
DS92LV0422
36
48
SQA36A 0.25 × 0.6
SQA48A 0.25 × 0.6
0.5
0.5
4.6 x 4.6
5.1 × 5.1
0.25 × 0.7
0.25 × 0.7
1.0 × 1.0
1.1 × 1.1
16
16
0.2
0.2
Figure 43. 48-Pin WQFN Stencil Example of Via and Opening Placement
Information on the WQFN style package is provided in Leadless Leadframe Package (LLP) Application Report
(SNOA401).
10.1.2 Transmission Media
The serializer and deserializer chipset is intended to be used in a point-to-point configuration through a PCB
trace or through twisted pair cable. The serializer and deserializer provide internal terminations for a clean
signaling environment. The interconnect for LVDS must present a differential impedance of 100 Ω. Use cables
and connectors that have matched differential impedance to minimize impedance discontinuities. Shielded or un-
shielded cables may be used depending upon the noise environment and application requirements.
10.1.3 LVDS Interconnect Guidelines
See AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and AN-905 Transmission
Line RAPIDESIGNER Operation and Applications Guide (SNLA035) for full details.
•
•
Use 100-Ω coupled differential pairs
Use the S, 2S, 3S rule in spacings
–
–
–
S = space between the pair
2S = space between pairs
3S = space to LVCMOS signal
•
•
•
•
•
Minimize the number of vias
Use differential connectors when operating above 500-Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Terminate as close to the Tx outputs and Rx inputs as possible
Additional general guidance can be found in the LVDS Owner's Manual, available in PDF format from the TI
website at: www.ti.com/lvds.
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10.2 Layout Example
The following PCB layout examples are derived from the layout design of the LV04EVK01 Evaluation Module.
These graphics and additional layout description are used to demonstrate both proper routing and proper solder
techniques when designing in the serializer and deserializer pair.
Figure 44. DS92LV0421 Serializer Example Layout
Figure 45. DS92LV0422 Deserializer Example Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
For developmental support, see the following:
Overview for LVDS/M-LVDS/ECL/CML
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
Absolute Maximum Ratings for Soldering (SNOA549)
Leadless Leadframe Package (LLP) Application Report (SNOA401)
AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008)
AN-905 Transmission Line RAPIDESIGNER Operation and Applications Guide (SNLA035)
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 19. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
DS92LV0421
DS92LV0422
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
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11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS92LV0421SQ/NOPB
DS92LV0421SQE/NOPB
DS92LV0421SQX/NOPB
DS92LV0422SQ/NOPB
DS92LV0422SQE/NOPB
DS92LV0422SQX/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
NJK
NJK
NJK
RHS
RHS
RHS
36
36
36
48
48
48
1000 RoHS & Green
250 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
LV0421
SN
SN
SN
SN
SN
LV0421
LV0421
LV0422
LV0422
LV0422
2500 RoHS & Green
1000 RoHS & Green
250
RoHS & Green
2500 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS92LV0421SQ/NOPB
WQFN
NJK
NJK
NJK
RHS
RHS
RHS
36
36
36
48
48
48
1000
250
330.0
178.0
330.0
330.0
178.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
6.3
6.3
6.3
7.3
7.3
7.3
6.3
6.3
6.3
7.3
7.3
7.3
1.5
1.5
1.5
1.3
1.3
1.3
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
DS92LV0421SQE/NOPB WQFN
DS92LV0421SQX/NOPB WQFN
2500
1000
250
DS92LV0422SQ/NOPB
WQFN
DS92LV0422SQE/NOPB WQFN
DS92LV0422SQX/NOPB WQFN
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS92LV0421SQ/NOPB
DS92LV0421SQE/NOPB
DS92LV0421SQX/NOPB
DS92LV0422SQ/NOPB
DS92LV0422SQE/NOPB
DS92LV0422SQX/NOPB
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
NJK
NJK
NJK
RHS
RHS
RHS
36
36
36
48
48
48
1000
250
356.0
208.0
356.0
356.0
208.0
356.0
356.0
191.0
356.0
356.0
191.0
356.0
35.0
35.0
35.0
35.0
35.0
35.0
2500
1000
250
2500
Pack Materials-Page 2
MECHANICAL DATA
NJK0036A
SQA36A (Rev A)
www.ti.com
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