DS92LV1224_15 [TI]
30-66 MHz 10 Bit Bus LVDS Deserializer;
| 型号： | DS92LV1224_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 30-66 MHz 10 Bit Bus LVDS Deserializer |
| 文件： | 总23页 (文件大小：1176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS92LV1224
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SNLS189A –APRIL 2005–REVISED APRIL 2013
DS92LV1224 30-66 MHz 10 Bit Bus LVDS Deserializer
Check for Samples: DS92LV1224
1
FEATURES
DESCRIPTION
The DS92LV1224 is a 300 to 660 Mb/s deserializer
for high-speed unidirectional serial data transmission
over FR-4 printed circuit board backplanes and
balanced copper cables. It receives the Bus LVDS
serial data stream from a compatible 10–bit serializer,
transforms it back into a 10-bit wide parallel data bus
and recovers parallel clock. This single serial data
stream simplifies PCB design and reduces PCB cost
by narrowing data paths that in turn reduce PCB size
and number of layers. The single serial data stream
also reduces cable size, the number of connectors,
and eliminates clock-to-data and data-to-data skew.
2
•
30–66 MHz Single 1:10 Deserializer with
300–660 Mb/s Throughput
•
Robust Bus LVDS Serial Data Transmission
with Embedded Clock for Exceptional Noise
Immunity and Low EMI
•
Clock Recovery from PLL Lock to Random
Data Patterns
•
•
Ensured Transition Every Data Transfer Cycle
Low Power Consumption < 300 mW (typ)
at 66 MHz
•
Single Differential Pair Eliminates Multi-
Channel Skew
The DS92LV1224 works well with Bus LVDS 10–bit
serializers within its specified frequency operating
range. It features low power consumption, and high
impedance outputs in power down mode.
•
•
•
•
Flow-Through Pinout for Easy PCB Layout
Synchronization Mode and LOCK Indicator
Programmable Edge Trigger on Clock
The DS92LV1224 was designed with the flow-through
pinout and is available in a space saving 28–lead
SSOP package.
High Impedance on Receiver Inputs when
Power is Off
•
Small 28-Lead SSOP Package
Block Diagrams
10-BIT SERIALIZER
DS92LV1224
LVDS
D
D
R
I+
10
10
O+
D
R
OUT
IN
R
I-
O-
TCLK_R/F
TCLK
(30 MHz to 66 MHz)
REFCLK
REN
TIMING and
CONTROL
TIMING and
CONTROL
PLL
DEN
PLL
LOCK
RCLK
(30 MHz to 66 MHz)
SYNC1
SYNC2
CLOCK
RECOVERY
RCLK_R/F
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
DS92LV1224
SNLS189A –APRIL 2005–REVISED APRIL 2013
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Functional Description
The DS92LV1224 is a 10-bit Deserializer device which together with a compatible serializer (i.e. DS92LV1023E)
forms a chipset designed to transmit data over FR-4 printed circuit board backplanes and balanced copper
cables at clock speeds from 30 MHz to 66 MHz.
The chipset has three active states of operation: Initialization, Data Transfer, and Resynchronization; and two
passive states: Powerdown and TRI-STATE.
The following sections describe each operation and passive state.
Initialization
Initialization of both devices must occur before data transmission begins. Initialization refers to synchronization of
the Serializer and Deserializer PLL's to local clocks, which may be the same or separate. Afterwards,
synchronization of the Deserializer to Serializer occurs.
Step 1: When you apply VCC to both Serializer and/or Deserializer, the respective outputs enter TRI-STATE, and
on-chip power-on circuitry disables internal circuitry. When VCC reaches VCCOK (2.5V) the PLL in each device
begins locking to a local clock. For the Serializer, the local clock is the transmit clock (TCLK) provided by the
source ASIC or other device. For the Deserializer, you must apply a local clock to the REFCLK pin.
The Serializer outputs remain in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the
Serializer is now ready to send data or SYNC patterns, depending on the levels of the SYNC1 and SYNC2 inputs
or a data stream. The SYNC pattern sent by the Serializer consists of six ones and six zeros switching at the
input clock rate.
Note that the Deserializer LOCK output will remain high while its PLL locks to the incoming data or to SYNC
patterns on the input.
Step 2: The Deserializer PLL must synchronize to the Serializer to complete initialization. The Deserializer will
lock to non-repetitive data patterns. However, the transmission of SYNC patterns enables the Deserializer to lock
to the Serializer signal within a specified time.
The user's application determines control of the SYNC1 and SYNC 2 pins. One recommendation is a direct
feedback loop from the LOCK pin. Under all circumstances, the Serializer stops sending SYNC patterns after
both SYNC inputs return low.
When the Deserializer detects edge transitions at the Bus LVDS input, it will attempt to lock to the embedded
clock information. When the Deserializer locks to the Bus LVDS clock, the LOCK output will go low. When LOCK
is low, the Deserializer outputs represent incoming Bus LVDS data.
Data Transfer
After initialization, the Serializer will accept data from inputs DIN0–DIN9. The Serializer uses the TCLK input to
latch incoming Data. The TCLK_R/F pin selects which edge the Serializer uses to strobe incoming data.
TCLK_R/F high selects the rising edge for clocking data and low selects the falling edge. If either of the SYNC
inputs is high for 5*TCLK cycles, the data at DIN0-DIN9 is ignored regardless of clock edge.
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After determining which clock edge to use, a start and stop bit, appended internally, frame the data bits in the
register. The start bit is always high and the stop bit is always low. The start and stop bits function as the
embedded clock bits in the serial stream.
The Serializer transmits serialized data and clock bits (10+2 bits) from the serial data output (DO±) at 12 times
the TCLK frequency. For example, if TCLK is 66 MHz, the serial rate is 66 × 12 = 792 Mega-bits-per-second.
Since only 10 bits are from input data, the serial “payload” rate is 10 times the TCLK frequency. For instance, if
TCLK = 66 MHz, the payload data rate is 66 × 10 = 660 Mbps. The data source provides TCLK and must be in
the range of 30 MHz to 66 MHz nominal.
The Serializer outputs (DO±) can drive a point-to-point connection or in limited multi-point or multi-drop
backplanes. The outputs transmit data when the enable pin (DEN) is high, PWRDN = high, and SYNC1 and
SYNC2 are low. When DEN is driven low, the Serializer output pins will enter TRI-STATE.
When the Deserializer synchronizes to the Serializer, the LOCK pin is low. The Deserializer locks to the
embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low. Otherwise
ROUT0–ROUT9 is invalid.
The ROUT0-ROUT9 pins use the RCLK pin as the reference to data. The polarity of the RCLK edge is controlled
by the RCLK_R/F input. See Figure 6.
ROUT(0-9), LOCK and RCLK outputs will drive a maximum of three CMOS input gates (15 pF load) with a 66
MHz clock.
Resynchronization
When the Deserializer PLL locks to the embedded clock edge, the Deserializer LOCK pin asserts a low. If the
Deserializer loses lock, the LOCK pin output will go high and the outputs (including RCLK) will enter TRI-STATE.
The user's system monitors the LOCK pin to detect a loss of synchronization. Upon detection, the system can
arrange to pulse the Serializer SYNC1 or SYNC2 pin to resynchronize. Multiple resynchronization approaches
are possible. One recommendation is to provide a feedback loop using the LOCK pin itself to control the sync
request of the Serializer (SYNC1 or SYNC2). Dual SYNC pins are provided for multiple control in a multi-drop
application. Sending sync patterns for resynchronization is desirable when lock times within a specific time are
critical. However, the Deserializer can lock to random data, which is discussed in the next section.
Random Lock Initialization and Resynchronization
The initialization and resynchronization methods described in their respective sections are the fastest ways to
establish the link between the Serializer and Deserializer. However, the DS92LV1224 can attain lock to a data
stream without requiring the Serializer to send special SYNC patterns. This allows the DS92LV1224 to operate in
“open-loop” applications. Equally important is the Deserializer's ability to support hot insertion into a running
backplane. In the open loop or hot insertion case, we assume the data stream is essentially random. Therefore,
because lock time varies due to data stream characteristics, we cannot possibly predict exact lock time.
However, please see Table 1 for some general random lock times under specific conditions. The primary
constraint on the “random” lock time is the initial phase relation between the incoming data and the REFCLK
when the Deserializer powers up. As described in the next paragraph, the data contained in the data stream can
also affect lock time.
If a specific pattern is repetitive, the Deserializer could enter “false lock” - falsely recognizing the data pattern as
the clocking bits. We refer to such a pattern as a repetitive multi-transition, RMT. This occurs when more than
one Low-High transition takes place in a clock cycle over multiple cycles. This occurs when any bit, except DIN
9, is held at a low state and the adjacent bit is held high, creating a 0-1 transition. In the worst case, the
Deserializer could become locked to the data pattern rather than the clock. Circuitry within the DS92LV1224 can
detect that the possibility of “false lock” exists. The circuitry accomplishes this by detecting more than one
potential position for clocking bits. Upon detection, the circuitry will prevent the LOCK output from becoming
active until the potential “false lock” pattern changes. The false lock detect circuitry expects the data will
eventually change, causing the Deserializer to lose lock to the data pattern and then continue searching for clock
bits in the serial data stream. Graphical representations of RMT are shown in Figure 1. Please note that RMT
only applies to bits DIN0-DIN8.
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Powerdown
When no data transfer occurs, you can use the Powerdown state. The Serializer and Deserializer use the
Powerdown state, a low power sleep mode, to reduce power consumption. The Deserializer enters Powerdown
when you drive PWRDN and REN low. The Serializer enters Powerdown when you drive PWRDN low. In
Powerdown, the PLL stops and the outputs enter TRI-STATE, which disables load current and reduces supply
current to the milliampere range. To exit Powerdown, you must drive the PWRDN pin high.
Before valid data exchanges between the Serializer and Deserializer, you must reinitialize and resynchronize the
devices to each other. Initialization of the Serializer takes 510 TCLK cycles. The Deserializer will initialize and
assert LOCK high until lock to the Bus LVDS clock occurs.
TRI-STATE
The Serializer enters TRI-STATE when the DEN pin is driven low. This puts both driver output pins (DO+ and
DO−) into TRI-STATE. When you drive DEN high, the Serializer returns to the previous state, as long as all other
control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F).
When you drive the REN pin low, the Deserializer enters TRI-STATE. Consequently, the receiver output pins
(ROUT0–ROUT9) and RCLK will enter TRI-STATE. The LOCK output remains active, reflecting the state of the
PLL.
(1)
Table 1.
Random Lock Times for the DS92LV1224
40 MHz
66 MHz
18
Units
μs
Maximum
Mean
26
4.5
0.77
3.0
μs
Minimum
Conditions:
0.43
μs
PRBS 215, VCC = 3.3V
(1) Difference in lock times are due to different starting points in the data pattern with multiple parts.
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Figure 1. RMT Patterns Seen on the Bus LVDS Serial Output
DIN0 Held Low-DIN1 Held High Creates an RMT Pattern
DIN4 Held Low-DIN5 Held High Creates an RMT Pattern
DIN8 Held Low-DIN9 Held High Creates an RMT Pattern
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
−0.3V to +3.9V
+150°C
LVCMOS/LVTTL Input Voltage
LVCMOS/LVTTL Output Voltage
Bus LVDS Receiver Input Voltage
Junction Temperature
Storage Temperature
−65°C to +150°C
+260°C
Lead Temperature (Soldering, 4 seconds)
Maximum Package Power Dissipation Capacity at 25°C Package: 28-Lead SSOP
1.27 W
Package Derating:
10.3 mW/°C above
+25°C
28-Lead SSOP
θja
97°C/W
θjc
27°C/W
HBM (1.5kΩ, 100pF)
>2kV
ESD Rating
MM
> 250V
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply
that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Min
3.0
−40
0
Nom
3.3
Max
3.6
Units
Supply Voltage (VCC
)
V
Operating Free Air Temperature (TA)
Receiver Input Range
+25
+85
2.4
°C
V
Supply Noise Voltage(VCC
)
100 mVP-P
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Electrical Characteristics(1)(2)(3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to pins PWRDN, RCLK_R/ F, REN, REFCLK = inputs; apply to pins
ROUT, RCLK, LOCK = outputs)
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
2.0
VCC
0.8
V
V
GND
VCL
IIN
ICL = −18 mA
−0.62
±1
−1.5
+15
VCC
0.5
V
Input Current
VIN = 0V or 3.6V
IOH = −9 mA
−10
2.2
μA
V
VOH
VOL
IOS
IOZ
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
TRI-STATE Output Current
3.0
IOL = 9 mA
GND
−15
−10
0.25
−47
±0.1
V
VOUT = 0V
−85
+10
mA
μA
PWRDN or REN = 0.8V, VOUT = 0V or VCC
DESERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins RI+ and RI−)
VTH
VTL
Differential Threshold High Voltage
Differential Threshold Low Voltage
+6
−12
±1
+50
mV
mV
μA
VCM = +1.1V
−50
−10
−10
VIN = +2.4V, VCC = 3.6V or 0V
VIN = 0V, VCC = 3.6V or 0V
+15
+10
IIN
Input Current
±0.05
μA
DESERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC)
f = 30 MHz
f = 40 MHz
f = 66 MHz
58
58
90
75
75
mA
mA
mA
Deserializer Supply Current Worst
CL = 15 pF
Case
ICCR
See Figure 2
110
ICCXR
Deserializer Supply Current
Powerdown
PWRDN = 0.8V, REN = 0.8V
0.36
1.0
mA
(1) Typical values are given for VCC = 3.3V and TA = +25°C.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) For the purpose of specifying deserializer PLL performance, tDSR1 and tDSR2 are specified with the REFCLK running and stable, and
with specific conditions for the incoming data stream (SYNCPATs). It is recommended that the derserializer be initialized using either
tDSR1 timing or tDSR2 timing. tDSR1 is the time required for the deserializer to indicate lock upon power-up or when leaving the power-
down mode. Synchronization patterns should be sent to the device before initiating either condition. tDSR2 is the time required to indicate
lock for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change from not receiving data to receiving
synchronization patterns (SYNCPATs).
Deserializer Timing Requirements for REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tRFCP
Parameter
REFCLK Period
Conditions
Min
15.15
30
Typ
T
Max
33.33
70
Units
ns
tRFDC
REFCLK Duty Cycle
50
%
tRFCP
tTCP
/
Ratio of REFCLK to TCLK
95
1
3
105
6
tRFTT
REFCLK Transition Time
ns
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Deserializer Switching Characteristics(1)(2)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbo
l
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
Receiver out Clock
Period
tRCP
tCLH
tCHL
tRCP = tTCP
RCLK
15.15
33.33
ns
Rout(0-9),
LOCK,
RCLK
CMOS/TTL Low-to-High
Transition Time
1.2
4
ns
CL = 15 pF
See Figure 3
CMOS/TTL High-to-Low
Transition Time
1.1
4
ns
ns
ns
ns
ns
ns
ns
ns
All Temp./ All
Freq.
1.75*tRCP+1.25
1.75*tRCP+2.25
1.75*tRCP+2.25
1.75*tRCP+2.75
0.4*tRCP
1.75*tRCP+3.75
1.75*tRCP+3.75
1.75*tRCP+3.75
1.75*tRCP+3.75
0.5*tRCP
1.75*tRCP+6.25
1.75*tRCP+5.25
1.75*tRCP+5.25
1.75*tRCP+4.75
Room Temp./
3.3V/30MHz
Deserializer Delay
See Figure 5
tDD
Room Temp./
3.3V/40MHz
Room Temp./
3.3V/66MHz
RCLK
30MHz
ROUT Data Valid before
RCLK
RCLK
40MHz
tROS
See Figure 6
See Figure 6
0.4*tRCP
0.5*tRCP
RCLK
66MHz
0.38*tRCP
0.5*tRCP
30MHz
40MHz
66MHz
−0.4*tRCP
−0.4*tRCP
−0.38*tRCP
45
−0.5*tRCP
−0.5*tRCP
−0.5*tRCP
50
ns
ns
ns
%
ROUT Data valid after
RCLK
tROH
tRDC
tHZR
tLZR
tZHR
tZLR
RCLK Duty Cycle
55
10
10
10
10
3
HIGH to TRI-STATE Delay
LOW to TRI-STATE Delay
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
2.8
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs
2.8
See Figure 7
Rout(0-9)
4.2
4.2
30MHz
40MHz
66MHz
30MHz
40MHz
66MHz
1.68
Deserializer PLL Lock time
from PWRDWN (with
SYNCPAT)
tDSR1
1.31
3
0.84
3
0.62
1
Deserializer PLL Lock time
from SYNCPAT
tDSR2
tZHLK
tRNM
0.47
1
0.29
0.8
TRI-STATE to HIGH Delay
(power-up)
LOCK
3.7
12
ns
30 MHz
40 MHz
66 MHz
650
450
250
950
730
400
ps
ps
ps
(3)
Deserializer Noise Margin See
(1) tLLHT and tLHLT specifications are Guranteed By Design (GBD) using statistical analysis.
(2) Because the Serializer is in TRI-STATE mode, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
(3) tRNM is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. The
Deserializer Noise Margin is Guaranteed By Design (GBD) using statistical analysis.
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AC Timing Diagrams and Test Circuits
Figure 2. “Worst Case” Deserializer ICC Test Pattern
Figure 3. Deserializer CMOS/TTL Output Load and Transition Times
Figure 4. SYNC Timing Delays
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Figure 5. Deserializer Delay
Timing shown for RCLK_R/F = LOW
tHIGH
Duty Cycle (tRDC) =
tHIGH + tLOW
Figure 6. Deserializer Data Valid Out Times
Figure 7. Deserializer TRI-STATE Test Circuit and Timing
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Figure 8. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays
Figure 9. Deserializer PLL Lock Time from SyncPAT
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SW - Setup and Hold Time (Internal Data Sampling Window)
tDJIT - Serializer Output Bit Position Jitter that results from Jitter on TCLK
tRNM = Receiver Noise Margin Time
Figure 10. Receiver Bus LVDS Input Skew Margin
Deserializer Truth Table(4)(5)(6)
INPUTS
OUTPUTS
PWRDN
REN
H
ROUT [0:9]
LOCK
RCLK
H
H
L
Z
Active
Z
H
L
Z
Active
Z
H
X
Z
H
L
Z
Active
Z
(4) LOCK Active indicates the LOCK output will reflect the state of the Deserializer with regard to the selected data stream.
(5) RCLK Active indicates the RCLK will be running if the Deserializer is locked. The Timing of RCLK with respect to ROUT is determined
by RCLK_R/F
(6) ROUT and RCLK are TRI-STATED when LOCK is asserted High.
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APPLICATION INFORMATION
USING THE SERIALIZER AND DESERIALIZER CHIPSET
The Serializer and Deserializer chipset is an easy to use transmitter and receiver pair that sends 10 bits of
parallel LVTTL data over a serial Bus LVDS link up to 660 Mbps. An on-board PLL serializes the input data and
embeds two clock bits within the data stream. The Deserializer uses a separate reference clock (REFCLK) and
an onboard PLL to extract the clock information from the incoming data stream and then deserialize the data.
The Deserializer monitors the incoming clock information, determines lock status, and asserts the LOCK output
high when loss of lock occurs.
POWER CONSIDERATIONS
An all CMOS design of the Serializer and Deserializer makes them inherently low power devices. In addition, the
constant current source nature of the Bus LVDS outputs minimizes the slope of the speed vs. ICC curve of
conventional CMOS designs.
POWERING UP THE DESERIALIZER
The DS92LV1224 can be powered up at any time by following the proper sequence. The REFCLK input can be
running before the Deserializer powers up, and it must be running in order for the Deserializer to lock to incoming
data. The Deserializer outputs will remain in TRI-STATE until the Deserializer detects data transmission at its
inputs and locks to the incoming data stream.
TRANSMITTING DATA
Once you power up the Serializer and Deserializer, they must be phase locked to each other to transmit data.
Phase locking occurs when the Deserializer locks to incoming data or when the Serializer sends patterns. The
Serializer sends SYNC patterns whenever the SYNC1 or SYNC2 inputs are high. The LOCK output of the
Deserializer remains high until it has locked to the incoming data stream. Connecting the LOCK output of the
Deserializer to one of the SYNC inputs of the Serializer will ensure that enough SYNC patterns are sent to
achieve Deserializer lock.
The Deserializer can also lock to incoming data by simply powering up the device and allowing the “random lock”
circuitry to find and lock to the data stream.
While the Deserializer LOCK output is low, data at the Deserializer outputs (ROUT0-9) is valid, except for the
specific case of loss of lock during transmission which is further discussed in the "Recovering from LOCK Loss"
section below.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still
reliably receive data. Various environmental and systematic factors include:
Serializer: TCLK jitter, VCC noise (noise bandwidth and out-of-band noise)
Media: ISI, Large VCM shifts
Deserializer: VCC noise
RECOVERING FROM LOCK LOSS
In the case where the Deserializer loses lock during data transmission, up to 3 cycles of data that were
previously received can be invalid. This is due to the delay in the lock detection circuit. The lock detect circuit
requires that invalid clock information be received 4 times in a row to indicate loss of lock. Since clock
information has been lost, it is possible that data was also lost during these cycles. Therefore, after the
Deserializer relocks to the incoming data stream and the Deserializer LOCK pin goes low, at least three previous
data cycles should be suspect for bit errors.
The Deserializer can relock to the incoming data stream by making the Serializer resend SYNC patterns, as
described above, or by random locking, which can take more time, depending on the data patterns being
received.
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HOT INSERTION
All the BLVDS devices are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s)
makes contact first, then the VCC pin(s), and then the I/O pins. When removing, the I/O pins should be
unplugged first, then the VCC, then the Ground. Random lock hot insertion is illustrated in Figure 13
PCB CONSIDERATIONS
The Bus LVDS Serializer and Deserializer should be placed as close to the edge connector as possible. In
multiple Deserializer applications, the distance from the Deserializer to the slot connector appears as a stub to
the Serializer driving the backplane traces. Longer stubs lower the impedance of the bus, increase the load on
the Serializer, and lower the threshold margin at the Deserializers. Deserializer devices should be placed much
less than one inch from slot connectors. Because transition times are very fast on the Serializer Bus LVDS
outputs, reducing stub lengths as much as possible is the best method to ensure signal integrity.
TRANSMISSION MEDIA
The Serializer and Deserializer can also be used in point-to-point configuration of a backplane, through a PCB
trace, or through twisted pair cable. In point-to-point configuration, the transmission media need only be
terminated at the receiver end. Please note that in point-to-point configuration, the potential of offsetting the
ground levels of the Serializer vs. the Deserializer must be considered. Also, Bus LVDS provides a +/− 1.2V
common mode range at the receiver inputs.
Failsafe Biasing for the DS92LV1224
The DS92LV1224 has an improved input threshold sensitivity of +/− 50mV versus +/− 100mV for the
DS92LV1210 or DS92LV1212. This allows for greater differential noise margin in the DS92LV1224. However, in
cases where the receiver input is not being actively driven, the increased sensitivity of the DS92LV1224 can
pickup noise as a signal and cause unintentional locking . For example, this can occur when the input cable is
disconnected.
External resistors can be added to the receiver circuit board to prevent noise pick-up. Typically, the non-inverting
receiver input is pulled up and the inverting receiver input is pulled down by high value resistors. the pull-up and
pull-down resistors (R1 and R2) provide a current path through the termination resistor (RL) which biases the
receiver inputs when they are not connected to an active driver. The value of the pull-up and pull-down resistors
should be chosen so that enough current is drawn to provide a +15mV drop across the termination resistor.
Please see Figure 11 for the Failsafe Biasing Setup.
USING TDJIT AND TRNM TO VALIDATE SIGNAL QUALITY
The parameters tDJIT and tRNM can be used to generate an eye pattern mask to validate signal quality in an actual
application or in simulation.
The parameter tDJIT measures the transmitter's ability to place data bits in the ideal position to be sampled by the
receiver. The typical tDJIT parameter of −80 ps indicates that the crossing point of the Tx data is 80 ps ahead of
the ideal crossing point. The tDJIT(min) and tDJIT(max) parameters specify the earliest and latest, respectively, time
that a crossing will occur relative to the ideal position.
The parameter tRNM is calculated by first measuring how much of the ideal bit the receiver needs to ensure
correct sampling. After determining this amount, what remains of the ideal bit that is available for external
sources of noise is called tRNM. It is the offset from tDJIT(min or max) for the test mask within the eye opening.
The vertical limits of the mask are determined by the DS92LV1224 receiver input threshold of +/− 50 mV.
Please refer to the eye mask pattern of Figure 11 for a graphic representation of tDJIT and tRNM
.
14
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SNLS189A –APRIL 2005–REVISED APRIL 2013
Figure 11. Failsafe Biasing Setup
Figure 12. Using tDJIT and tRNM to Generate an Eye Pattern Mask and Validate Signal Quality
Figure 13. Random Lock Hot Insertion
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Pin Diagrams
Figure 14. 28-Lead SSOP
See DB Package
DESERIALIZER PIN DESCRIPTION
Pin Name
ROUT
I/O
O
I
No.
Description
15–19, 24–28
2
Data Output. ±9 mA CMOS level outputs.
RCLK_R/F
Recovered Clock Rising/Falling strobe select. TTL level input. Selects RCLK
active edge for strobing of ROUT data. High selects rising edge. Low selects
falling edge.
RI+
I
I
I
5
6
7
+ Serial Data Input. Non-inverting Bus LVDS differential input.
RI−
− Serial Data Input. Inverting Bus LVDS differential input.
PWRDN
Powerdown. TTL level input. PWRDN driven low shuts down the PLL and TRI-
STATEs outputs putting the device into a low power sleep mode.
LOCK
O
10
LOCK goes low when the Deserializer PLL locks onto the embedded clock
edge. CMOS level output. Totem pole output structure, does not directly
support wire OR connection.
RCLK
REN
O
I
9
8
Recovered Clock. Parallel data rate clock recovered from embedded clock.
Used to strobe ROUT, CMOS level output.
Output Enable. TTL level input. TRI-STATEs ROUT0–ROUT9, LOCK and
RCLK when driven low.
DVCC
DGND
AVCC
I
I
I
I
I
21, 23
14, 20, 22
4, 11
Digital Circuit power supply.
Digital Circuit ground.
Analog power supply (PLL and Analog Circuits).
Analog ground (PLL and Analog Circuits).
Use this pin to supply a REFCLK signal for the internal PLL frequency.
AGND
REFCLK
1, 12, 13
3
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SNLS189A –APRIL 2005–REVISED APRIL 2013
REVISION HISTORY
Changes from Original (April 2013) to Revision A
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 16
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Dec-2017
PACKAGING INFORMATION
Orderable Device
DS92LV1224TMSA
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
LIFEBUY
SSOP
SSOP
SSOP
DB
28
28
28
47
TBD
Call TI
CU SN
CU SN
Call TI
DS92LV1224T
MSA
DS92LV1224TMSA/NOPB
DS92LV1224TMSAX/NOPB
LIFEBUY
LIFEBUY
DB
DB
47
Green (RoHS
& no Sb/Br)
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
DS92LV1224T
MSA
2000
Green (RoHS
& no Sb/Br)
-40 to 85
DS92LV1224T
MSA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Dec-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS92LV1224TMSAX/NOP SSOP
B
DB
28
2000
330.0
16.4
8.4
10.7
2.4
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DB 28
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
DS92LV1224TMSAX/NOP
B
2000
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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