DS92LV2411 [TI]
5MHz 至 50MHz 24 位 Channel Link II 串行器;
| 型号： | DS92LV2411 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 5MHz 至 50MHz 24 位 Channel Link II 串行器 |
| 文件： | 总56页 (文件大小：1135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DS92LV2411, DS92LV2412
SNLS302E –MAY 2010–REVISED FEBRUARY 2015
DS92LV241x 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer
1 Features
3 Description
The DS92LV2411 (Serializer) and DS92LV2412
(Deserializer) chipset translates a parallel 24–bit
LVCMOS data interface into a single high-speed CML
serial interface with embedded clock information. This
single serial stream eliminates skew issues between
clock and data, reduces connector size and
interconnect cost for transferring a 24-bit, or less, bus
over FR-4 printed circuit board backplanes,
differential or coax cables.
1
•
24-Bit Data, 3–Bit Control, 5 to 50 MHz Clock
Application Payloads up to 1.2 Gbps
•
•
AC Coupled Interconnects: STP up to 10 m or
Coax 20+ m
•
•
•
•
1.8 V or 3.3 V Compatible LVCMOS I/O Interface
Integrated Terminations on Ser and Des
AT-SPEED BIST Mode and Reporting Pin
Configurable by Pins or I2C Compatible Serial
Control Bus
In addition to the 24-bit data bus interface, the
DS92LV2411/12 also features a 3-bit control bus for
slow speed signals. This allows implementing video
and display applications with up to 24–bits per pixel
(RGB888).
•
•
•
Power Down Mode Minimizes Power Dissipation
>8 kV HBM ESD Rating
SERIALIZER — DS92LV2411
Programmable
transmit
de-emphasis,
receive
–
Supports Spread Spectrum Clocking (SSC) on
Inputs
equalization, on-chip scrambling and DC balancing
enables long distance transmission over lossy cables
and backplanes. The DS92LV2412 automatically
locks to incoming data without an external reference
clock or special sync patterns, providing easy “plug-
and-go” or “hot plug” operation. EMI is minimized by
the use of low voltage differential signaling, receiver
drive strength control, and spread spectrum clocking
capability.
–
–
–
Data Scrambler for Reduced EMI
DC-Balance Encoder for AC Coupling
Selectable Output VOD and Adjustable De-
emphasis
•
DESERIALIZER — DS92LV2412
–
Random Data Lock; no Reference Clock
Required
The DS92LV2411/12 chipset is programmable though
an I2C interface as well as through Pins. A built-in
AT-SPEED BIST feature validates link integrity and
may be used for system diagnostics.
–
–
–
Adjustable Input Receiver Equalization
LOCK (Real Time Link Status) Reporting Pin
Selectable Spread Spectrum Clock Generation
(SSCG) and Output Slew Rate Control (OS) to
Reduce EMI
The DS92LV2411 is offered in a 48-Pin WQFN and
the DS92LV2412 is offered in a 60-Pin WQFN
package. Both devices operate over the full industrial
temperature range of -40°C to +85°C.
2 Applications
•
•
•
•
•
•
Embedded Video and Display
Medical Imaging
Device Information
PART NUMBER
DS92LV2411
DS92LV2412
PACKAGE
WQFN (48)
WQFN (60)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
9.00 mm × 9.00 mm
Factory Automation
Office Automation — Printer, Scanner
Security and Video Surveillance
General Purpose Data Communication
4 Typical Application Schematic
V
V
DDn
1.8V
V
V
DDIO
DDIO
(1.8Vor3.3V)
DDn
1.8V (1.8Vor3.3V)
DI[7:0]
DI[15:8]
DI[23:16]
CI1
CI2
CI3
DO[7:0]
DO[15:8]
DO[23:16]
CO1
CO2
CO3
Channel Link II
1 Pair /AC Coupled
Graphic
Processor
OR
Video
Imager
OR
24-bit RGB
Display
OR
0.1 PF
0.1 PF
DOUT+
DOUT-
RIN+
RIN-
ASIC/FPGA
CLKIN
CLKOUT
100 ohm STP Cable
ASIC/FPGA
DS92LV2411
Serializer
DS92LV2412
Deserializer
LOCK
PASS
PDB
CMF
PDB
BISTEN
BISTEN
RFB
VODSEL
DeEmph
STRAP pins
not shown
SCL
SDA
ID[x]
SCL
SDA
ID[x]
Optional
Optional
DAP
DAP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS92LV2411, DS92LV2412
SNLS302E –MAY 2010–REVISED FEBRUARY 2015
www.ti.com
Table of Contents
8.1 Overview ................................................................. 22
8.2 Functional Block Diagrams ..................................... 22
8.3 Feature Description................................................. 23
8.4 Device Functional Modes........................................ 34
8.5 Programming........................................................... 34
8.6 Register Maps......................................................... 37
Applications and Implementation ...................... 40
9.1 Application Information............................................ 40
9.2 Typical Applications ................................................ 40
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Typical Application Schematic............................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications....................................................... 10
7.1 Absolute Maximum Ratings .................................... 10
7.2 ESD Ratings............................................................ 10
7.3 Recommended Operating Conditions..................... 10
7.4 Thermal Information................................................ 11
7.5 Serializer DC Electrical Characteristics .................. 11
7.6 Deserializer DC Electrical Characteristics .............. 12
7.7 DC and AC Serial Control Bus Characteristics....... 13
7.8 Recommended Timing For The Serial Control Bus 14
7.9 Recommended Serializer Timing For CLKIN.......... 18
7.10 Serializer Switching Characteristics...................... 19
7.11 Deserializer Switching Characteristics.................. 20
7.12 Typical Characteristics.......................................... 21
Detailed Description ............................................ 22
9
10 Power Supply Recommendations ..................... 44
11 Layout................................................................... 44
11.1 Layout Guidelines ................................................. 44
11.2 Layout Example .................................................... 44
12 Device and Documentation Support ................. 47
12.1 Related Links ........................................................ 47
12.2 Trademarks........................................................... 47
12.3 Electrostatic Discharge Caution............................ 47
12.4 Glossary................................................................ 47
13 Mechanical, Packaging, and Orderable
Information ........................................................... 47
8
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (April 2014) to Revision E
Page
•
•
•
•
Changed "Terminal" terminology back to "Pin" ..................................................................................................................... 1
Added statement about checkerboard pattern from deserializer data output when in BIST mode ..................................... 32
Added note that BISTEN pin must be high and REG = 0 to use BIST mode. .................................................................... 32
Changed deserializer Reg 0x02[6] definition to match correct OSS_SEL behavior ............................................................ 38
Changes from Revision C (April 2013) to Revision D
Page
•
•
•
•
•
•
•
•
•
•
•
Added Handling Ratings and Thermal Characteristics and updated datasheet to new layout. ............................................ 1
Changed Serializer Supply current power down test condition from VDDIO from 13.6V to 3.6V .......................................... 12
Added DC to "Deserializer Electrical Characteristics".......................................................................................................... 12
Changed typical value to 36mA instead of 37mA ............................................................................................................... 12
Changed Test condition of VOUT for determining IOZ ........................................................................................................... 12
Added max value for VIL when using 1.8V I/O LVCMOS .................................................................................................... 12
Changed IOL from 3mA to 1.25mA ..................................................................................................................................... 13
Changed parentheses location of UI equation for clarification ............................................................................................ 20
Added characteristic graphics for serializer CML driver output and deserializer LVCMOS clock output ............................ 21
Added applications graphics of the serializer output with and without de-emphasis .......................................................... 43
Added layout example and stencil diagram graphics........................................................................................................... 44
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 43
2
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Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: DS92LV2411 DS92LV2412
DS92LV2411, DS92LV2412
www.ti.com
SNLS302E –MAY 2010–REVISED FEBRUARY 2015
6 Pin Configuration and Functions
48-Pin WQFN
Package RHS
Top View
DI10
DI11
DI12
DI13
DI14
DI15
DI16
DI17
DI18
DI19
DI20
DI21
VODSEL
De-Emph
VDDTX
PDB
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
DOUT+
DOUT-
RES2
DS92LV2411
TOP VIEW
DAP = GND
VDDHS
RES1
RES0
VDDP
CONFIG[1]
Pin Functions, DS92LV2411 Serializer(1)
PIN
TYPE
DESCRIPTION
NAME
LVCMOS PARALLEL INTERFACE
NO.
CI1
CI2
CI3
5
3
4
I, LVCMOS Control Signal Input
w/ pull-down For Display/Video Application:
CI1 = Data Enable Input
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
I, LVCMOS Control Signal Input
w/ pull-down For Display/Video Application:
CI2 = Horizontal Sync Input
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
I, LVCMOS Control Signal Input
w/ pull-down For Display/Video Application:
CI3 = Vertical Sync Input
CI3 is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed is
130 clock cycle wide.
(1) NOTE: 1 = HIGH, 0 = LOW
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on
the PDB Pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
Copyright © 2010–2015, Texas Instruments Incorporated
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Product Folder Links: DS92LV2411 DS92LV2412
DS92LV2411, DS92LV2412
SNLS302E –MAY 2010–REVISED FEBRUARY 2015
www.ti.com
Pin Functions, DS92LV2411 Serializer(1) (continued)
PIN
TYPE
DESCRIPTION
NAME
CLKIN
NO.
10
I, LVCMOS Clock Input
w/ pull-down Latch/data strobe edge set by RFB Pin.
DI[7:0]
34, 33, 32, 29, I, LVCMOS Parallel Interface Data Input Pins
28, 27, 26, 25 w/ pull-down For 8–bit RED Display: DI7 = R7 – MSB, DI0 = R0 – LSB.
DI[15:8]
DI[23:16]
42, 41, 40, 39, I, LVCMOS Parallel Interface Data Input Pins
38, 37, 36, 35 w/ pull-down For 8–bit GREEN Display: DI15 = G7 – MSB, DI8 = G0 – LSB.
2, 1, 48, 47,
I, LVCMOS Parallel Interface Data Input Pins
46, 45, 44, 43 w/ pull-down For 8–bit BLUE Display: DI23 = B7 – MSB, DI16 = B0 – LSB.
CONTROL AND CONFIGURATION
BISTEN
31
I, LVCMOS BIST Mode — Optional
w/ pull-down BISTEN = 0, BIST is disabled (normal operation)
BISTEN = 1, BIST is enabled
CONFIG[1:
0]
13, 12
I, LVCMOS 00: Control Signal Filter DISABLED. Interfaces with DS92LV2412 or DS92LV0412
w/ pull-down 01: Control Signal Filter ENABLED. Interfaces with DS92LV2412 or DS92LV0412
10: Reverse compatibility mode to interface with the DS90UR124 or DS99R124Q
11: Reverse compatibility mode to interface with the DS90C124
De-Emph
23
I, Analog
w/ pull-up
De-Emphasis Control
De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this Pin to GND or control via register.
See Table 2.
This can also be controlled by I2C register access.
ID[x]
PDB
6
I, Analog
I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 11.
21
I, LVCMOS Power-down Mode Input
w/ pull-down PDB = 1, Ser is enabled (normal operation).
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Ser is powered down
When the Ser is in the power-down state, the driver outputs (DOUT+/-) are both logic high,
the PLL is shutdown, IDD is minimized. Control Registers are RESET.
RES[2:0]
RFB
18, 16, 15
11
I, LVCMOS Reserved - tie LOW
w/ pull-down
I, LVCMOS Clock Input Latch/Data Strobe Edge Select
w/ pull-down RFB = 1, parallel interface data and control signals are latched on the rising clock edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock edge.
This can also be controlled by I2C register access.
SCL
8
9
I, LVCMOS I2C Serial Control Bus Clock Input - Optional
Open Drain SCL requires an external pull-up resistor to 3.3V.
SDA
I/O, LVCMOS I2C Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor 3.3V.
VODSEL
24
I, LVCMOS Differential Driver Output Voltage Select
w/ pull-down VODSEL = 1, CML VOD is ±420 mV, 840 mVp-p (typ) — long cable / De-Emph applications
VODSEL = 0, CML VOD is ±280 mV, 560 mVp-p (typ) — short cable (no De-emph), low
power mode.
This is can also be control by I2C register.
4
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Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: DS92LV2411 DS92LV2412
DS92LV2411, DS92LV2412
www.ti.com
NAME
SNLS302E –MAY 2010–REVISED FEBRUARY 2015
Pin Functions, DS92LV2411 Serializer(1) (continued)
PIN
TYPE
DESCRIPTION
NO.
CHANNEL-LINK II — CML SERIAL INTERFACE
DOUT-
19
O, CML
Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
DOUT+
20
O, CML
Non–Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
POWER AND GROUND
GND
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
VDDHS
VDDIO
VDDL
17
30
7
Power
Power
Power
Power
Power
TX High Speed Logic Power, 1.8 V ±5%
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
Logic Power, 1.8 V ±5%
VDDP
14
22
PLL Power, 1.8 V ±5%
VDDTX
Output Driver Power, 1.8 V ±5%
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Product Folder Links: DS92LV2411 DS92LV2412
DS92LV2411, DS92LV2412
SNLS302E –MAY 2010–REVISED FEBRUARY 2015
www.ti.com
60-Pin WQFN
Package NKB
Top View
NC
RES
NC
46
47
48
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VDDL
VDDIR
RIN+
DO8/OSC_SEL0
DO9/OSC_SEL1
DO10/OSC_SEL2
DO11
49
50
51
52
53
54
55
56
57
58
59
60
RIN-
CMF
ROUT+
ROUT-
VDDCMLO
VDDR
ID[x]
VDDIO
DS92LV2412
TOP VIEW
DO12/EQ0
DO13/EQ1
DO14/EQ2
DO15/EQ3
DO16
DAP = GND
BOLD PIN NAME ± indicates I/O strap
VDDPR
VDDSC
PDB
pin associated with output pin
DO17/RFB
DO18/OSS_SEL
NC
NC
(1)
Pin Functions, DS92LV2412 Deserializer
PIN
TYPE
DESCRIPTION
NAME
NO.
LVCMOS PARALLEL INTERFACE
CLKOUT
5
O, LVCMOS Pixel Clock Output
In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6). Data
strobe edge set by RFB.
CO1
6
O, LVCMOS Control Signal Output
For Display/Video Application:
CO1 = Data Enable Output
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6).
(1) NOTE: 1 = HIGH, 0 = LOW
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on
the PDB Pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
6
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Product Folder Links: DS92LV2411 DS92LV2412
DS92LV2411, DS92LV2412
www.ti.com
SNLS302E –MAY 2010–REVISED FEBRUARY 2015
Pin Functions, DS92LV2412 Deserializer (1) (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
CO2
8
O, LVCMOS Control Signal Output
For Display/Video Application:
CO2 = Horizontal Sync Output
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6).
CO3
7
O, LVCMOS Control Signal Output
For Display/Video Application:
CO3 = Vertical Sync Output
CO3 is different than CO1 and CO2 because it is limited to 1 transition per 130 clock cycles.
Thus, the minimum pulse width allowed is 130 clock cycle wide.
The CONFIG[1:0] Pins have no affect on CO3 signal
In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6).
DO[7:0]
DO[15:8]
DO[23:16]
LOCK
33, 34, 35,
I, STRAP,
Parallel Interface Data Output Pins
36, 37, 39, O, LVCMOS For 8–bit RED Display: DO7 = R7 – MSB, DO0 = R0 – LSB.
40, 41
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 6). These
Pins are inputs during power-up (See STRAP Inputs).
20, 21, 22,
I, STRAP,
Parallel Interface Data Output Pins
23, 25, 26, O, LVCMOS For 8–bit GREEN Display: DO15 = G7 – MSB, DO8 = G0 – LSB.
27, 28
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 6). These
Pins are inputs during power-up (See STRAP Inputs).
9, 10, 11,
I, STRAP,
Parallel Interface Data Input Pins
12, 14, 17, O, LVCMOS For 8–bit BLUE Display: DO23 = B7 – MSB, DO16 = B0 – LSB.
18, 19
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 6). These
Pins are inputs during power-up (See STRAP Inputs).
32
O, LVCMOS LOCK Status Output
LOCK = 1, PLL is Locked, outputs are active LOCK = 0, PLL is unlocked, DO[23:0], CO1,
CO2, CO3 and CLKOUT output states are controlled by OSS_SEL (See Table 6). May be
used as Link Status or to flag when Video Data is active (ON/OFF).
PASS
42
O, LVCMOS PASS Output (BIST Mode)
PASS = 1, error free transmission
PASS = 0, one or more errors were detected in the received payload
Route to test point for monitoring, or leave open if unused.
(2)
CONTROL AND CONFIGURATION — STRAP PINS
CONFIG[1:0]
10 [DO22],
9 [DO23]
STRAP
00: Control Signal Filter DISABLED. Interfaces with DS92LV2411 or DS92LV0411
I, LVCMOS 01: Control Signal Filter ENABLED. Interfaces with DS92LV2411 or DS92LV0411
w/ pull-down 10: Reverse compatibility mode to interface with the DS90UR241 or DS99R241
11: Reverse compatibility mode to interface with the DS90C241
EQ[3:0]
20 [DO15],
21 [DO14],
STRAP
I, LVCMOS (See Table 3).
Receiver Input Equalization
22 [DO13], w/ pull-down This can also be controlled by I2C register access.
23 [DO12]
LF_MODE
12 [DO20]
STRAP
SSCG Low Frequency Mode
I, LVCMOS Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE (X).
w/ pull-down LF_MODE = 1, SSCG in low frequency mode (CLK = 5-20 MHz)
LF_MODE = 0, SSCG in high frequency mode (CLK = 20-50 MHz)
This can also be controlled by I2C register access.
MAP_SEL[1:0]
40[D],
41 [D]
STRAP
Bit mapping reverse compatibility / DS90UR241 Options
I, LVCMOS Pin or Register Control
w/ pull-down Default setting is b'00.
(2) For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP Pins are read upon
power-up and set device configuration. Pin Number listed along with shared data output name in square brackets.
Copyright © 2010–2015, Texas Instruments Incorporated
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Pin Functions, DS92LV2412 Deserializer (1) (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
OP_LOW
42 [PASS]
STRAP
Outputs held LOW when LOCK = 1
I, LVCMOS NOTE: Do not use any other strap options with this strap function enabled
w/ pull-down OP_LOW = 1: all outputs are held LOW during power up until released by programming
OP_LOW release/set register HIGH.
NOTE: Before the device is powered up, the outputs are in TRI-STATE
See Figure 26 and Figure 27
OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default)
This can also be controlled by I2C register access.
OS_CLKOUT
OS_DATA
OSS_SEL
11 [DO21]
14 [DO19]
17 [DO18]
STRAP
Output CLKOUT Slew Select
I, LVCMOS OS_CLKOUT = 1, Increased CLKOUT slew rate
w/ pull-down OS_CLKOUT = 0, Normal CLKOUT slew rate (default)
This can also be controlled by I2C register access.
STRAP
Output DO[23:0], CO1, CO2, CO3 Slew Select
I, LVCMOS OS_DATA = 1, Increased DO slew rate
w/ pull-down OS_DATA = 0, Normal DO slew rate (default)
This can also be controlled by I2C register access.
STRAP
Output Sleep State Select
I, LVCMOS OSS_SEL is used in conjunction with PDB to determine the state of the outputs in Power
w/ pull-down Down (Sleep). (See Table 6).
NOTE: OSS_SEL STRAP CANNOT BE USED IF OP_LOW = 1
This can also be controlled by I2C register access.
RFB
18 [DO17]
STRAP
Clock Output Strobe Edge Select
I, LVCMOS RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
w/ pull-down RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
This can also be controlled by I2C register access.
OSC_SEL[2:0] 26 [DO10],
27 [DO9],
STRAP
Oscillator Selectl
I, LVCMOS (See Table 7 and Table 8).
28 [DO8]
w/ pull-down This can also be controlled by I2C register access.
SSC[3:0]
34 [DO6],
35 [DO5],
36 [DO4],
37 [DO3]
STRAP
Spread Spectrum Clock Generation (SSCG) Range Select
I, LVCMOS (See Table 4 and Table 5).
w/ pull-down This can also be controlled by I2C register access.
CONTROL AND CONFIGURATION
BISTEN
44
I, LVCMOS BIST Enable Input — Optional
w/ pull-down BISTEN = 0, BIST is disabled (normal operation)
BISTEN = 1, BIST is enabled
ID[x]
NC
56
I, Analog
I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See Table 11).
1, 15, 16,
30, 31, 45,
46, 60
Not Connected
Leave Pin open (float)
PDB
59
I, LVCMOS Power Down Mode Input
w/ pull-down PDB = 1, Des is enabled (normal operation).
Refer to “Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Des is in power-down.
When the Des is in the power-down state, the LVCMOS output state is determined by
Table 6. Control Registers are RESET.
RES
SCL
SDA
47
3
I, LVCMOS Reserved - tie LOW
w/ pull-down
I, LVCMOS I2C Serial Control Bus Clock Input - Optional
Open Drain SCL requires an external pull-up resistor to 3.3V.
2
I/O, LVCMOS I2C Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor to 3.3V.
8
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Product Folder Links: DS92LV2411 DS92LV2412
DS92LV2411, DS92LV2412
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NAME
SNLS302E –MAY 2010–REVISED FEBRUARY 2015
Pin Functions, DS92LV2412 Deserializer (1) (continued)
PIN
TYPE
DESCRIPTION
NO.
CHANNEL-LINK II — CML SERIAL INTERFACE
CMF
51
I, Analog
Common-Mode Filter
VCM center-tap is a virtual ground which may be AC coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
RIN+
49
50
52
I, CML
I, CML
O, CML
True Input. The input must be AC Coupled with a 0.1 μF capacitor.
Inverting Input. The input must be AC Coupled with a 0.1 μF capacitor.
RIN-
ROUT+
True Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
ROUT-
53
O, CML
Ground
Inverting Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
POWER AND GROUND(3)
GND
DAP
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connected to the ground plane (GND) with at least 9 vias.
VDDCMLO
VDDIO
VDDIR
VDDL
54
13, 24, 38
48
Power
Power
Power
Power
Power
Power
Power
RX High Speed Logic Power, 1.8 V ± 5%
LVCMOS I/O Power, 1.8 V ± 5% OR 3.3 V ± 10% (VDDIO
)
Input Power, 1.8 V ±5%
29
Logic Power, 1.8 V ±5%
VDDPR
VDDR
57
PLL Power, 1.8 V ±5%
43, 55
4, 58
RX High Speed Logic Power, 1.8 V ±5%
SSCG Power, 1.8 V ±5%
VDDSC
(3) Power must be supplied to all power Pins for normal operation
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7 Specifications
7.1 Absolute Maximum Ratings(1)(2)(3)
MIN
−0.3
−0.3
−0.3
−0.3
−0.3
MAX
2.5
UNIT
V
Supply Voltage – VDDn (1.8 V)
Supply Voltage – VDDIO
LVCMOS I/O Voltage
Receiver Input Voltage
Driver Output Voltage
Junction Temperature
4.0
V
(VDDIO + 0.3)
(VDD + 0.3)
(VDD + 0.3)
+150
V
V
V
°C
°C
Storage Temperature Range (Tstg
)
−65
+150
(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(2) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(3) For soldering specifications, see product folder at www.ti.com and http://www.ti.com/lit/SNOA549
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±8000
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
V(ESD)
Electrostatic discharge
±1000
±250
V
Machine Model (MM)
IEC61000–4–2), RD = 330Ω, CS = 150pF
Air Discharge (DOUT+, DOUT-
Contact Discharge (DOUT+, DOUT-
Air Discharge (RIN+, DIN-
Contact Discharge (RIN+, RIN-
)
±2500
±800
)
V(ESD)
Electrostatic discharge
V
)
±2500
±800
)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible if necessary precautions are taken. Pins listed as DOUT+, DOUT- or RIN+, DIN- may actually have higher
performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible if necessary precautions are taken. Pins listed as DOUT+, DOUT- or RIN+, DIN- may actually have higher
performance.
7.3 Recommended Operating Conditions
MIN
1.71
1.71
TYP
1.8
MAX
1.89
1.89
UNIT
V
Supply Voltage (VDDn
)
LVCMOS Supply Voltage (VDDIO
)
)
1.8
V
OR
LVCMOS Supply Voltage (VDDIO
3.0
−40
5
3.3
3.6
+85
50
V
Operating Free Air Temperature (TA)
Clock Frequency
Supply Noise(1)
+25
°C
MHz
mVP-P
50
(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with
amplitude = 100 mVp-p measured at the device VDDn Pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter
cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the
noise frequency is less than 400 kHz.
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7.4 Thermal Information
RHS(2)
48 PINS
27.1
NKB(3)
60 PINS
24.6
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
RθJC(top)
4.5
2.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Ratings for maximum dissipation capacity (215 mW).
(3) Ratings for maximum dissipation capacity (478 mW).
7.5 Serializer DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
LVCMOS INPUT DC SPECIFICATIONS
VDDIO = 3.0 to 3.6V
2.2
VDDIO
VDDIO
0.8
High Level Input
Voltage
VIH
V
V
0.65*
VDDIO
VDDIO = 1.71 to 1.89V
DI[23:0],
VDDIO = 3.0 to 3.6V
GND
Low Level Input
Voltage
CI1,CI2,CI3, CLKIN,
PDB, VODSEL,
RFB, BISTEN,
CONFIG[1:0]
VIL
0.35*
VDDIO
VDDIO = 1.71 to 1.89V
GND
VDDIO = 3.0 to
3.6V
–15
–15
±1
±1
+15
+15
IIN
Input Current
VIN = 0V or VDDIO
μA
VDDIO = 1.71 to
1.89V
CML DRIVER DC SPECIFICATIONS
VODSEL = 0
VODSEL = 1
VODSEL = 0
±205
±320
±280
±420
560
±355
±520
Differential Output
Voltage
VOD
mV
RL = 100Ω, De-
emph = disabled,
Figure 2
Differential Output
Voltage (DOUT+) –
(DOUT-)
mVp-p
mVp-p
VODp-p
ΔVOD
VOS
VODSEL = 1
840
RL = 100Ω, De-
emph = disabled,
VODSEL = L
1
50
mV
Offset Voltage –
Single-ended At TP A
and B, Figure 1
RL = 100Ω, De-
emph = disabled
VODSEL = 0
VODSEL = 1
0.65
V
V
DOUT+, DOUT-
1.575
Offset Voltage
RL = 100Ω, De-emph = disabled
Unbalance Single-
ended At TP A and B,
Figure 1
ΔVOS
1
mV
DOUT+/- = 0V,
De-emph =
disabled
Output Short Circuit
Current
IOS
VODSEL = 0
–36
100
mA
Internal Output
Termination Resistor
RTO
80
120
Ω
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
(3) Current into device Pins is defined as positive. Current out of a device Pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
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Serializer DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX
UNIT
Serializer Supply
Checker Board
VDD = 1.89V
VDDIO = 1.89V
VDDIO = 3.6V
VDD33 = 1.89V
VDDIO = 1.89V
VDDIO = 3.6V
VDD33 = 1.89V
VDDIO = 1.89V
VDDIO = 3.6V
All VDD Pins
75
3
85
5
mA
mA
mA
mA
mA
mA
µA
IDDT1
Current (includes load
current) RL = 100 Ω,
CLKIN = 50 MHz
Pattern, De-emph
= 3kΩ, VODSEL
= H, Figure 9
VDDIO
IDDIOT1
IDDT2
IDDIOT2
IDDZ
11
65
3
15
Checker Board
Pattern, De-emph
= 6kΩ, VODSEL
= L, Figure 9
All VDD Pins
VDDIO
75
5
11
40
5
15
Serializer Supply
Current Power-down
PDB = 0V , (All
other LVCMOS
Inputs = 0V)
All VDD Pins
VDDIO
1000
10
µA
IDDIOZ
10
20
µA
7.6 Deserializer DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)
(2) (3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX UNIT
3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6V
High Level Input
Voltage
VIH
2.2
VDDIO
V
V
Low Level Input
Voltage
PDB, BISTEN
VIL
GND
–15
0.8
IIN
Input Current
VIN = 0V or VDDIO
±1
+15
μA
V
IOH = −0.5 mA, RDS = L
High Level Output
Voltage
DO[23:0], CO1,
CO2, CO3,
VOH
2.4
VDDIO
V
CLKOUT, LOCK,
PASS
Low Level Output
Voltage
IOL = +0.5 mA, RDS = L
VOL
IOS
IOZ
GND
36
0.4
V
VDDIO = 3.3V, VOUT = 0V,
OS_PCLK/DATA = L/H
CLKOUT
Outputs
Output Short Circuit
Current
mA
μA
VDDIO = 3.3V, VOUT = 0V,
OS_PCLK/DATA = L/H
TRI-STATE Output
Current
PDB = 0V, OSS_SEL = 0V, VOUT = H Outputs
–15
+15
1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89V
High Level Input
Voltage
VIH
1.235
VDDIO
V
Low Level Input
Voltage
PDB, BISTEN
VIL
GND
–15
0.595
+15
V
µA
V
IIN
Input Current
VIN = 0V or VDDIO
±1
High Level Output
Voltage
IOH = −0.5 mA, RDS = L
VDDIO
–
DO[23:0], CO1,
CO2, CO3,
VOH
VDDIO
0.45
CLKOUT, LOCK,
PASS
Low Level Output
Voltage
IOL = +0.5 mA, RDS = L
VOL
GND
0.45
V
VDDIO = 1.8V, VOUT = 0V,
OS_PCLK/DATA = L/H
CLKOUT
Outputs
18
18
mA
mA
Output Short Circuit
Current
IOS
VDDIO = 1.8V, VOUT = 0V,
OS_PCLK/DATA = L/H
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
(3) Current into device Pins is defined as positive. Current out of a device Pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
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Deserializer DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX UNIT
TRI-STATE Output
Current
IOZ
PDB = 0V, OSS_SEL = 0V, VOUT = H Outputs
VCM = +1.2V (Internal VBIAS)
–15
+15
µA
CML RECEIVER DC SPECIFICATIONS
Differential Input
VTH
+50
–50
mV
mV
Threshold High Voltage
Differential Input
VTL
Threshold Low Voltage
RIN+, RIN-
Common Mode
VCM
12
V
µA
Ω
Voltage, Internal VBIAS
IIN
Input Current
VIN = 0V or VDDIO
–15
80
+15
120
Internal Input
Termination Resistor
RTI
RIN+, RIN-
100
LOOP THROUGH CML DRIVER OUTPUT DC SPECIFICATIONS – EQ TEST PORT
Differential Output
Voltage
RL = 100Ω
VOD
VOS
RT
542
1.4
mV
V
ROUT+/-
ROUT+/-
Offset Voltage Single-
ended
RL = 100Ω
Internal Termination
Resistor
80
100
120
Ω
SUPPLY CURRENT
Deserializer
Supply Current
(includes load current) H, CL = 4pF,
Checker Board
Pattern, RDS =
VDD = 1.89V
VDDIO = 1.89V
VDDIO = 3.6V
VDD = 1.89V
VDDIO = 1.89V
VDDIO = 3.6V
All VDD Pins
VDDIO
93
33
62
40
5
110
45
mA
mA
mA
µA
IDD1
IDDIO1
IDDZ
75
CLKOUT = 50 MHz
Figure 9
Deserializer Supply
Current Power Down
PDB = 0V, All
other LVCMOS
Inputs = 0V
All VDD Pins
VDDIO
3000
50
µA
IDDIOZ
10
100
µA
7.7 DC and AC Serial Control Bus Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
Input High Level
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIH
SDA and SCL
SDA and SCL
2.2
VDD 3.3V
V
V
VIL
Input Low Level Voltage
Input Hysteresis
Output Low Voltage(1)
GND
0.8
VHY
VOL
Iin
>50
mV
V
SDA, IOL = 1.25mA, VDDIO = 3.3V
SDA or SCL, Vin = VDDIO or GND
SDA, RPU = X, Cb ≤ 400pF
0
0.4
-15
+15
µA
ns
ns
ns
ns
ns
pF
tR
SDA RiseTime – READ
SDA Fall Time – READ
Set Up Time — READ
Hold Up Time — READ
Input Filter
40
25
tF
tSU;DAT
tHD;DAT
tSP
520
55
50
Cin
Input Capacitance
SDA or SCL
<5
(1) Specification is ensured by characterization and is not tested in production.
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7.8 Recommended Timing For The Serial Control Bus
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
fSCL
SCL Clock Frequency
Standard Mode
Fast Mode
100 kHz
400 kHz
tLOW
SCL Low Period
SCL High Period
Standard Mode
Fast Mode
4.7
1.3
4.0
0.6
4.0
µs
µs
µs
µs
µs
tHIGH
Standard Mode
Fast Mode
tHD;STA
Hold time for a start or a
repeated start condition,
Figure 18
Standard Mode
Fast Mode
0.6
4.7
0.6
µs
µs
µs
tSU:STA
Set Up time for a start or a
repeated start condition,
Figure 18
Standard Mode
Fast Mode
tHD;DAT
tSU;DAT
tSU;STO
tBUF
Data Hold Time,
Figure 18
Standard Mode
Fast Mode
0
0
3.45
0.9
µs
µs
ns
ns
µs
µs
µs
Data Set Up Time,
Figure 18
Standard Mode
Fast Mode
250
100
4.0
0.6
4.7
Set Up Time for STOP
Condition, Figure 18
Standard Mode
Fast Mode
Bus Free Time
Between STOP and START,
Figure 18
Standard Mode
Fast Mode
1.3
µs
tr
tf
SCL and SDA Rise Time,
Figure 18
Standard Mode
Fast Mode
1000
300
300
300
ns
ns
ns
ns
SCL and SDA Fall Time,
Figure 18
Standard Mode
Fast mode
A
B
A'
C
C
Scope
A
50:ꢀ
50:ꢀ
B
B'
50:ꢀ
50:ꢀ
Figure 1. Serializer Test Circuit
DOUT+
VOD-
VOD+
DOUT-
GND
VOS
VOD+
(DOUT+) - (DOUT+
)
0V
VODp-p
VOD-
Figure 2. Serializer Output Waveforms
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+VOD
0V
80%
20%
(DOUT+) - (DOUT-)
-VOD
t
t
LHLT
LLHT
Figure 3. Serializer Output Transition Times
t
t
TCIL
t
TCIH
TCP
V
DDIO
CLKIN
w/ RFB = L
80%
20%
1/2 V
DDIO
GND
tCLKT
tCLKT
V
DDIO
V
V
IHmin
ILmax
DI[23:0],
CI1,CI2,CI3
GND
t
t
DIH
DIS
Figure 4. Serializer Input CLKIN Waveform And Set And Hold Times
PDB
1/2 V
DDIO
CLKIN
"X"
active
t
PLD
DOUT
(Diff.)
Driver On
Driver OFF, V
OD
= 0V
Figure 5. Serializer Lock Time
1/2 V
DDIO
PDB
CLKIN
active
"X"
t
XZD
DOUT
(Diff.)
active
Driver OFF, V
OD
= 0V
Figure 6. Serializer Disable Time
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DIN[23:0],
SYMBOL N
SYMBOL N+1
CI1,CI2,CI3
t
SD
CLKIN
(RFB = L)
START
BIT
STOP START
BIT BIT
STOP
BIT
DOUT
(Diff.)
SYMBOL N-1
SYMBOL N
Figure 7. Serializer Latency Delay
t
t
DJIT
DJIT
VOD (+)
DOUT
(Diff.)
TxOUT_E_O
0V
VOD (-)
t
(1 UI)
BIT
Figure 8. Serializer Output Jitter
V
DDIO
CLKIN/
CLKOUT
w/ RFB = L
GND
V
DDIO
DI/DO (odd),
CI2/CO2, CI3/CO3
GND
V
DDIO
DI/DO (even),
CI1/CO1
GND
Figure 9. Checkerboard Data Pattern
V
DDIO
80%
20%
GND
t
t
CHL
CLH
Figure 10. Deserializer LVCMOS Transition Times
START
BIT
STOP START
BIT BIT
STOP
BIT
RIN
(Diff.)
SYMBOL N
SYMBOL N+1
t
DD
CLKOUT
(RFB = L)
DO[23:0],
SYMBOL N-2
SYMBOL N-1
SYMBOL N
CO1,CO2,CO3
Figure 11. Deserializer Delay – Latency
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1/2 V
PDB
DDIO
RIN
(Diff.)
active
"X"
t
XZR
CLKOUT,
DO[23:0],
CO1,CO2,CO3
PASS, LOCK
active
Z (TRI-STATE)
Figure 12. Deserializer Disable Time (OSS_SEL = 0)
2.0V
PDB
0.8V
RIN
(Diff.)
'RQ¶Wꢀ&DUH
t
DDLT
TRI-STATE
or LOW
LOCK
Z or L
t
RxZ
DO[23:0],
CO1,CO2,CO3
TRI-STATE or LOW or Pulled Up
Z or L or PU
CLKOUT
(RFB = L)
TRI-STATE or LOW
IN LOCK TIME
Z or L
OFF
OFF
ACTIVE
Figure 13. Deserializer PLL Lock Times And PDB Tri-State Delay
V
DDIO
CLKOUT
w/RFB = H
1/2 V
DDIO
GND
V
DDIO
DO[23:0],
CO1,CO2,CO3
1/2 V
t
1/2 V
DDIO
DDIO
GND
t
ROS
ROH
Figure 14. Deserializer Output Data Valid (Setup And Hold) Times With SSCG = Off
V
DDIO
CLKOUT
w/RFB = H
1/2 V
DDIO
GND
DO[23:0],
CO1,CO2,CO3
1/2 V
1/2 V
DDIO
DDIO
V
DDIO
GND
t
t
ROH
ROS
Figure 15. Deserializer Output Data Valid (Setup And Hold) Times With SSCG = On
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Ideal Data
Bit End
Sampling
Window
Ideal Data Bit
Beginning
V
TH
0V
RxIN_TOL
Left
RxIN_TOL
Right
V
TL
Ideal Center Position (t /2)
BIT
t
(1 UI)
BIT
t
RJIT = RxIN_TOL (Left + Right)
Sampling Window = 1 UI - t
RJIT
Figure 16. Receiver Input Jitter Tolerance
BISTEN
1/2 V
DDIO
tPASS
PASS
(w/ errors)
1/2 V
DDIO
Prior BIST Result
Current BIST Test - Toggle on Error
Result Held
Figure 17. BIST Pass Waveform
SDA
SCL
t
BUF
t
t
LOW
t
f
HD;STA
t
r
t
t
SP
t
f
r
t
t
HD;STA
SU;STA
t
SU;STO
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
Figure 18. Serial Control Bus Timing Diagram
7.9 Recommended Serializer Timing For CLKIN
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
5 MHz to 50 MHz, Figure 4
MIN
20
TYP
MAX UNIT
tTCP
Transmit Input CLKIN Period
Transmit Input CLKIN High Time
Transmit Input CLKIN Low Time
CLKIN Input Transition Time
T
0.5T
0.5T
200
0.6T
0.6T
2.4
ns
ns
tTCIH
tTCIL
0.4T
0.4T
0.5
ns
tCLKT
SSCIN
ns
CLKIN Input – Spread Spectrum
at 50 MHz
fmod
fdev
35
kHz
±0.02
fMOD
kHz
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7.10 Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tLHT
Ser Output Low-to-High
Transition Time, Figure 3
RL = 100Ω, De-emphasis = disabled,
VODSEL = 0
200
ps
RL = 100Ω, De-emphasis = disabled,
VODSEL = 1
200
200
200
ps
ps
ps
ns
ns
tHLT
Ser Output High-to-Low
Transition Time, Figure 3
RL = 100Ω, De-emphasis = disabled,
VODSEL = 0
RL = 100Ω, De-emphasis = disabled,
VODSEL = 1
tDIS
tDIH
tXZD
tPLD
tSD
Input Data - Setup Time,
Figure 4
DI[23:0], CI1, CI2, CI3 to CLKIN
2
2
Input Data - Hold Time,
Figure 4
CLKIN to DI[23:0], CI1, CI2, CI3
Ser Output Active to OFF
Delay, Figure 6
Serializer PLL Lock Time(1)
Figure 5
8
1.4
15
10
ns
ms
ns
UI
UI
UI
,
RL = 100Ω
RL = 100Ω
Serializer Delay - Latency,
Figure 7
144*T
0.28
0.27
0.35
145*T
tDJIT
Ser Output Total Jitter,
Figure 8
RL = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 50 MHz
RL = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 43MHz
RL = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 5MHz
λSTXBW
Serializer Jitter Transfer
Function -3 dB Bandwidth
CLKIN = 50 MHz
CLKIN = 43 MHz
CLKIN = 20 MHz
CLKIN = 5MHz
CLKIN = 50 MHz
CLKIN = 43 MHz
CLKIN = 20 MHz
CLKIN = 5MHz
3
2.3
MHz
MHz
MHz
kHz
dB
1.3
650
0.84
0.83
0.83
0.28
δSTX
Serializer Jitter Transfer
Function Peaking
dB
dB
dB
(1) When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data
transfer require tPLD
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7.11 Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
CLK Output Period
TEST CONDITIONS
tRCP = tTCP
PIN/FREQ.
CLKOUT
MIN
20
TYP
T
MAX UNIT
tRCP
tRDC
200
0.57T
0.65T
0.60T
ns
ns
ns
ns
CLK Output Duty Cycle
SSCG = OFF, 5 – 50MHz
SSCG = ON, 5 – 20 MHz
SSCG = ON, 20 – 50 MHz
0.43T
0.35T
0.40T
0.50T
0.59T
0.53T
tCLH
LVCMOS
VDDIO = 1.8V,
CL = 4pF,
OS_CLKOUT/DATA = L
CLKOUT/DO[23:0],
CO1, CO2, CO3
Low-to-High
Transition Time,
Figure 10
2.1
2.0
ns
ns
ns
ns
T
VDDIO = 3.3V
CL = 4pF,
OS_CLKOUT/DATA = H
tCHL
LVCMOS
VDDIO = 1.8V
CL = 4pF,
OS_CLKOUT/DATA = L
CLKOUT/DO[23:0],
CO1, CO2, CO3
High-to-Low
Transition Time,
Figure 10
1.6
VDDIO = 3.3V
CL = 8 pF,
OS_CLKOUT/DATA = H
1.5
tROS
tROH
tDDLT
Data Valid before
VDDIO = 1.71 to 1.89V or
CLKOUT – Set Up Time, VDDIO = 3.0 to 3.6V
DO[23:0], CO1, CO2,
CO3
0.27
0.4
0.45
0.55
Figure 14
CL = 4pF (lumped load)
Data Valid after
CLKOUT – Hold Time,
Figure 14
VDDIO = 1.71 to 1.89V or
VDDIO = 3.0 to 3.6V
CL = 4pF (lumped load)
DO[23:0], CO1, CO2,
CO3
T
Deserializer Lock Time,
Figure 13
SSC[3:0] = OFF,
See(1)
CLKOUT = 5MHz
3
4
ms
ms
ms
ms
ns
SSC[3:0] = OFF,
See(1)
CLKOUT = 50MHz
CLKOUT = 5MHz
SSC[3:0] = ON,
See(1)
30
SSC[3:0] = ON,
See(1)
CLKOUT = 50MHz
CLKOUT = 5 to 50 MHz
6
tDD
Des Delay - Latency,
Figure 11
SSC[3:0] = ON,
See(2)
139*T
140*T
tDPJ
Des Period Jitter
SSC[3:0] = OFF,
See(3)
CLKOUT = 5MHz
CLKOUT = 10MHz
CLKOUT = 50MHz
CLKOUT = 5MHz
CLKOUT = 10MHz
CLKOUT = 50MHz
jitter freq <2MHz
jitter freq >6MHz
975
500
550
675
375
500
0.9
1700
1000
1250
1150
900
ps
ps
ps
tDCCJ
Des Cycle-to-Cycle Jitter SSC[3:0] = OFF,
See(2)
ps
ps
1150
ps
UI(4)
tIIT
Des Input Jitter
Tolerance, Figure 16
EQ = OFF,
SSCG = OFF,
CLKOUT = 50 MHz
0.5
UI(4)
BIST MODE
tPASS
BIST PASS Valid Time,
BISTEN = 1, Figure 17
1
10
µs
SSCG MODE
fDEV
Spread Spectrum
Clocking Deviation
Frequency
Under typical conditions
Under typical conditions
CLKOUT = 5 to 50 MHz,
SSC[3:0] = ON
±0.005
fMOD
±0.02
fMOD
KHz
kHz
fMOD
Spread Spectrum
Clocking Modulation
Frequency
CLKOUT = 5 to 50 MHz,
SSC[3:0] = ON
8
100
(1) tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active clock.
(2) tDCCJ is the maximum amount of jitter between adjacent clock cycles.
(3) tDPJ is the maximum amount the period is allowed to deviate over many samples.
(4) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / (28*CLK) ). The UI scales with clock frequency.
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7.12 Typical Characteristics
50 MHz TX
Pixel Clock
Input
(2 V/DIV)
CML Serializer
Data
Throughput
(100 mV/DIV)
50 MHz RX
Pixel Clock
Input
(2 V/DIV)
Time (20 ns/DIV)
Time (1 ns/DIV)
Note: On the rising edge of each clock period, the CML driver outputs Note: When both devices are locked and the scope is triggered from
a low Stop bit, high Start bit, and 28 DC-scrambled data bits.
Figure 19. Serializer CML Driver Output with 50 MHz TX
Pixel Clock.
the TX pixel clock, the RX clock is genlocked to the TX pixel clock
and does not drift.
Figure 20. Comparison of Deserializer LVCMOS RX Clock
Output locked to a 50 MHz TX Pixel Clock.
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8 Detailed Description
8.1 Overview
The DS92LV2411 / DS92LV2412 chipset transmits and receives 24-bits of data and 3 control signals over a
single serial CML pair operating at 140 Mbps to 1.4 Gbps. The serial stream also contains an embedded clock,
video control signals and the DC-balance information which enhances signal quality and supports AC coupling.
The Des can attain lock to a data stream without the use of a separate reference clock source, which greatly
simplifies system complexity and overall cost. The Des also synchronizes to the Ser regardless of the data
pattern, delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without
the need of special training patterns or sync characters. The Des recovers the clock and data by extracting the
embedded clock information, validating and then deserializing the incoming data stream providing a parallel
LVCMOS video bus to the display or ASIC/FPGA.
The DS92LV2411 / DS92LV2412 chipset can operate in 24-bit color depth (with DE, HS, VS encoded within the
serial data stream). In 18–bit color applications, the three video control signals maybe sent encoded within the
serial bit stream (restrictions apply) along with six additional general purpose signals.
8.2 Functional Block Diagrams
VODSEL
De-Emph
DI[23:0]
CI1/DE
CI2/HS
CI3/VS
DOUT+
DOUT-
RFB
Pattern
Generator
CLKIN
PLL
CONFIG[1:0]
PDB
Timing and
Control
SCL
SCA
ID[x]
BISTEN
DS92LV2411 ± SERIALIZER
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Functional Block Diagrams (continued)
STRAP INPUT
LF_MODE
OS_CLKOUT
OS_DATA
OSS_SEL
RFB
EQ [3:0]
OSC_SEL [2:0]
SSC [3:0]
CONFIG [1:0]
MAP_SEL [1:0]
SSCG
ROUT+
ROUT-
CMF
DO[23:0]
CO1/DE
CO2/HS
CO3/VS
RIN+
EQ
RIN-
STRAP INPUT
Error
Detector
PASS
BISTEN
PDB
OP_LOW
Clock and
Data
Recovery
CLKOUT
LOCK
Timing and
Control
SCL
SCA
ID[x]
DS92LV2412 ± DESERIALIZER
8.3 Feature Description
8.3.1 Serializer Functional Description
The Ser converts a wide parallel input bus to a single serial output data stream, and also acts as a signal
generator for the chipset Built In Self Test (BIST) mode. The device can be configured via external Pins or
through the optional serial control bus. The Ser features enhance signal quality on the link by supporting: a
selectable VOD level, a selectable de-emphasis signal conditioning and also the Channel Link II data coding that
provides randomization, scrambling, and DC Balancing of the data. The Ser includes multiple features to reduce
EMI associated with display data transmission. This includes the randomization and scrambling of the data and
also the system spread spectrum clock support. The Ser features power saving features with a sleep mode, auto
stop clock feature, and optional LVCMOS (1.8 V) parallel bus compatibility.
8.3.1.1 EMI Reduction Features
8.3.1.1.1 Data Randomization and Scrambling
Channel Link II Ser / Des feature a 3 step encoding process which enables the use of AC coupled interconnects
and also helps to manage EMI. The serializer first passes the parallel data through a scrambler which
randomizes the data. The randomized data is then DC balanced. The DC balanced and randomized data then
goes through a bit shuffling circuit and is transmitted out on the serial line. This encoding process helps to
prevent static data patterns on the serial stream. The resulting frequency content of the serial stream ranges
from the parallel clock frequency to the nyquist rate. For example, if the Ser / Des chip set is operating at a
parallel clock frequency of 50 MHz, the resulting frequency content of serial stream ranges from 50 MHz to 700
MHz ( 50 MHz *28 bits = 1.4 Gbps / 2 = 700 MHz ).
8.3.1.1.2 Ser — Spread Spectrum Compatibility
The Ser CLKIN is capable of tracking spread spectrum clocking (SSC) from a host source. The CLKIN will
accept spread spectrum tracking up to 35 kHz modulation and ±0.5, ±1 or ±2% deviations (center spread). The
maximum conditions for the CLKIN input are: a modulation frequency of 35 kHz and amplitude deviations of ±2%
(4% total).
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Feature Description (continued)
8.3.1.2 Integrated Signal Conditioning Features — Ser
8.3.1.2.1 Ser — VOD Select (VODSEL)
The Ser differential output voltage may be increased by setting the VODSEL Pin High. When VODSEL is Low,
the VOD is at the standard (default) level. When VODSEL is High, the VOD is increased in level. The increased
VOD is useful in extremely high noise environments and also on extra long cable length applications. When
using de-emphasis it is recommended to set VODSEL = H to avoid excessive signal attenuation especially with
the larger de-emphasis settings. This feature may be controlled by the external Pin or by register.
Table 1. Differential Output Voltage
INPUT
EFFECT
VOD
mV
VOD
mVp-p
VODSEL
H
L
±420
±280
840
560
8.3.1.2.2 Ser — De-Emphasis (De-Emph)
The De-Emph Pin controls the amount of de-emphasis beginning one full bit time after a logic transition that the
Ser drives. This is useful to counteract loading effects of long or lossy cables. This Pin should be left open for
standard switching currents (no de-emphasis) or if controlled by register. De-emphasis is selected by connecting
a resistor on this Pin to ground, with R value between 0.5 kΩ to 1 MΩ, or by register setting. When using De-
Emphasis it is recommended to set VODSEL = H.
Table 2. De-Emphasis Resistor Value
RESISTOR VALUE (kΩ)
DE-EMPHASIS SETTING
Open
0.6
Disabled
- 12 dB
- 9 dB
1.0
2.0
- 6 dB
5.0
- 3 dB
0.00
VDD = 1.8V,
= 25oC
T
A
-2.00
-4.00
-6.00
-8.00
-10.00
-12.00
-14.00
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
R VALUE - LOG SCALE (:)
Figure 21. De-Emph vs. R Value
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8.3.1.3 Power Saving Features
8.3.1.3.1 Ser — Power Down Feature (PDB)
The Ser has a PDB input Pin to ENABLE or POWER DOWN the device. This Pin is controlled by the host and is
used to save power, disabling the link when the it is not needed. In the POWER DOWN mode, the high-speed
driver outputs are both pulled to VDD and present a 0V VOD state. Note – in POWER DOWN, the optional Serial
Bus Control Registers are RESET.
8.3.1.3.2 Ser — Stop Clock Feature
The Ser will enter a low power SLEEP state when the CLKIN is stopped. A STOP condition is detected when the
input clock frequency is less than 3 MHz. The clock should be held at a static Low or high state. When the
CLKIN starts again, the Ser will then lock to the valid input clock and then transmits the serial data to the Des.
Note – in STOP CLOCK SLEEP, the optional Serial Bus Control Registers values are RETAINED.
8.3.1.3.3 1.8 V or 3.3 V VDDIO Operation
The Ser parallel bus and Serial Bus Interface can operate with 1.8 V or 3.3 V levels (VDDIO) for host compatibility.
The 1.8 V levels will offer lower noise (EMI) and also a system power savings.
8.3.1.4 Ser — Pixel Clock Edge Select (RFB)
The RFB Pin determines the edge that the data is latched on. If RFB is High, input data is latched on the Rising
edge of the CLKIN. If RFB is Low, input data is latched on the Falling edge of the CLKIN. Ser and Des maybe
set differently. This feature may be controlled by the external Pin or by register.
8.3.1.5 Optional Serial Bus Control
Please see the following section on the optional Serial Bus Control Interface.
8.3.1.6 Optional BIST Mode
Please see the following section on the chipset BIST mode for details.
8.3.2 Deserializer Functional Description
The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal
check for the chipset Built In Self Test (BIST) mode. The device can be configured via external Pins and strap
Pins or through the optional serial control bus. The Des features enhance signal quality on the link with an
integrated equalizer on the serial input and Channel Link II data encoding which provides randomization,
scrambling, and DC balancing of the data. The Des includes multiple features to reduce EMI associated with
data transmission. This includes the randomization and scrambling of the data, the output spread spectrum clock
generation (SSCG) support and output clock and data slew rate select. The Des features power saving features
with a power down mode, and optional LVCMOS (1.8 V) interface compatibility.
8.3.2.1 Integrated Signal Conditioning Features — Des
8.3.2.1.1 Des — Input Equalizer Gain (Eq)
The Des can enable receiver input equalization of the serial stream to increase the eye opening to the Des input.
Note this function cannot be seen at the RxIN+/- input but can be observed at the serial test port (ROUT+/-)
enabled via the Serial Bus control registers. The equalization feature may be controlled by the external Pin or by
register.
Table 3. Receiver Equalization Configuration
INPUTS
EFFECT
EQ3
EQ2
L
EQ1
L
EQ0
H
L
L
L
L
~1.5 dB
~3 dB
L
H
H
H
L
H
~4.5 dB
~6 dB
H
H
H
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Table 3. Receiver Equalization Configuration (continued)
INPUTS
EFFECT
EQ3
H
EQ2
L
EQ1
L
EQ0
H
~7.5 dB
~9 dB
H
L
H
H
H
H
L
H
~10.5 dB
~12 dB
OFF*
H
H
H
H
X
X
X
L
* Default Setting is EQ = Off
8.3.2.2 EMI Reduction Features
8.3.2.2.1 Des — Output Slew Rate Select (OS_CLKOUT/OS_DATA)
The parallel data outputs and clock outputs of the deserializer feature selectable output slew rates. The slew rate
of the CLKOUT Pin is controlled by the strap Pin or register OS_CLKOUT, while the data outputs (DO[23:0] and
CO[3:1]) are controlled by the strap Pin or register OS_DATA. When OS_CLKOUT/DATA = HIGH, the maximum
slew rate is selected. When the OS_CLKOUT/DATA = LOW, the minimum slew rate is selected. Use the higher
slew rate when driving longer traces or a heavier capacitive load.
8.3.2.2.2 Des — Common Mode Filter Pin (CMF) — Optional
The Des provides access to the center tap of the internal termination. A capacitor may be placed on this Pin for
additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 4.7 µF capacitor may be connected to this Pin to Ground.
8.3.2.2.3 Des — SSCG Generation — Optional
The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and
data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2% (4% total) at up
to 100 kHz modulations is available. See Table 4. This feature may be controlled by external STRAP Pins or by
register.
Table 4. SSCG Configuration (LF_MODE = L) — Des Output
SSC[3:0] INPUTS
RESULT
LF_MODE = L (20 - 50 MHz)
SSC3
L
SSC2
L
SSC1
L
SSC0
L
fdev (%)
NA
fmod (kHz)
Disable
L
L
L
H
L
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
L
L
H
H
L
CLK/2168
CLK/1300
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
L
L
H
L
CLK/868
CLK/650
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
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Table 5. SSCG Configuration (Lf_mode = H) — Des Output
SSC[3:0] INPUTS
RESULT
LH_MODE = H (5 - 20 MHz)
SSC3
SSC2
L
SSC1
L
SSC0
L
fdev (%)
NA
fmod (kHz)
L
L
Disable
L
L
H
L
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
L
L
H
H
L
CLK/620
CLK/370
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
L
L
H
L
CLK/258
CLK/192
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
Frequency
fdev(max)
F
F
F
CLKOUT+
CLKOUT
CLKOUT-
fdev(min)
Time
1/fmod
Figure 22. SSCG Waveform
8.3.2.2.4 1.8 V or 3.3 V VDDIO Operation
The Des parallel bus and Serial Bus Interface can operate with 1.8 V or 3.3 V levels (VDDIO) for target host
compatibility. The 1.8 V levels will offer a lower noise (EMI) and also a system power savings.
8.3.2.3 Power Saving Features
8.3.2.3.1 Des — Powerdown Feature (PDB)
The Des has a PDB input Pin to ENABLE or POWER DOWN the device. This Pin can be controlled by the
system to save power, disabling the Des when the display is not needed. An auto detect mode is also available.
In this mode, the PDB Pin is tied High and the Des will enter POWER DOWN when the serial stream stops.
When the serial stream starts up again, the Des will lock to the input stream and assert the LOCK Pin and output
valid data. In POWER DOWN mode, the Data and CLKOUT output states are determined by the OSS_SEL
status. Note – in POWER DOWN, the optional Serial Bus Control Registers are RESET.
8.3.2.3.2 Des — Stop Stream Sleep Feature
The Des will enter a low power SLEEP state when the input serial stream is stopped. A STOP condition is
detected when the embedded clock bits are not present. When the serial stream starts again, the Des will then
lock to the incoming signal and recover the data. Note – in STOP STREAM SLEEP, the optional Serial Bus
Control Registers values are RETAINED.
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8.3.2.4 Des — Clock-Data Recovery Status Flag (Lock) And Output State Select (OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK goes from TRI-STATE to
LOW (depending on the value of the OSS_SEL setting). After the DS92LV2412 completes its lock sequence to
the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial
input is available on the parallel bus and clock outputs. The CLKOUT output is held at its current state at the
change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered clock (or vice versa).
If there is a loss of clock from the input serial stream, LOCK is driven Low and the state of the outputs are based
on the OSS_SEL setting (STRAP Pin configuration or register).
8.3.2.5 Des — Oscillator Output — Optional
The Des provides an optional clock output when the input clock (serial stream) has been lost. This is based on
an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled by the
external Pin or by register. See Table 7 and Table 8.
Table 6. OSS_SEL And PDB Configuration — Des Outputs
INPUTS
PDB
OUTPUTS
SERIAL
INPUT
OSS_SEL
CLKOUT
DO[23:0], CO1,
CO2, CO3
LOCK
PASS
X
L
L
L
H
L
Z
Z
Z
Z
Z
L
Z
Z
L
X
Z
L
Static
Static
Active
H
H
H
L
H
X
Z
Z*
L
L
Active
Active
H
H
*NOTE — If Pin is strapped HIGH the output will be pulled up
Table 7. OSC (Oscillator) Mode — Des Output
INPUTS
OUTPUTS
EMBEDDED CLK
CLKOUT
DO[23:0]/CO1/CO2/CO3
LOCK
PASS
NOTE *
OSC
L
L
H
Output
Present
Toggling
Active
H
H
* NOTE — Absent and OSC_SEL ≠ 000
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PDB
(DES)
RIN
(Diff.)
active serial stream
X
LOCK
H
H
Z
Z
Z
Z
L
L
L
L
L
L
DO[23:0],
CO1,CO2,CO3
CLKOUT*
(DES)
Z
Z
Locking
Active
C0 or C1 Error
In Bit Stream
Active
OFF
OFF
(Loss of LOCK)
CONDITIONS: * RFB = L, and OSS_SEL Strap = L
Figure 23. Des Outputs With Output State Select Low (OSS_SEL = L)
PDB
(DES)
RIN
(Diff.)
active serial stream
X
Z
Z
Z
H
H
LOCK
L
L
Z
Z
Z
DO[23:0],
CO1,CO2,CO3
Z
Z
CLKOUT*
(DES)
C0 or C1 Error
In Bit Stream
OFF
Locking
Active
Active
OFF
(Loss of LOCK)
CONDITIONS: * RFB = L, and OSS_SEL Strap = H
Figure 24. Des Outputs With Output State Select High (OSS_SEL = H)
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Table 8. OSC_SEL (Oscillator) Configuration
OSC_SEL[2:0] INPUTS
CLKOUT OSCILLATOR FREQUENCY
OSC_SEL2
OSC_SEL1
OSC_SEL0
L
L
L
L
L
H
L
Off – Feature Disabled – Default
50 MHz ±40%
25 MHz ±40%
16.7 MHz ±40%
12.5 MHz ±40%
10 MHz ±40%
8.3 MHz ±40%
6.3 MHz ±40%
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
PDB
(DES)
RIN
(Diff.)
active serial stream
X
Z
H
H
LOCK
L
L
Z
Z
L
DO[23:0],
CO1,CO2,CO3
Z
L
CLKOUT*
(DES)
Z
Z
f
f
L
Z
H
H
PASS
L
L
Z
Locking
Active
C0 or C1 Error
In Bit Stream
Active
OFF
OFF
(Loss of LOCK)
CONDITIONS: * RFB = L, OSS_SEL = H , and OSC_SEL not equal to 000.
Figure 25. Des Outputs With Output State High And Clk Output Oscillator Option Enabled
8.3.2.6 Des — OP_LOW — Optional
The OP_LOW feature is used to hold the LVCMOS outputs, except for the LOCK output, at a LOW state. When
the OP_LOW feature is enabled, the LVCMOS outputs will be held at logic LOW while LOCK = LOW. The user
must toggle the OP_LOW Set/Reset register bit to release the outputs to the normal toggling state. Note that the
release of the outputs can only occur when LOCK is HIGH. The OP_LOW strap option is assigned to the PASS
Pin, at Pin location 42.
Restrictions on other straps:
1. Other strap options should not be used in order to keep the data and clock outputs at a true logic LOW state.
Other features should be selected through the I2C register interface.
2. The OSS_SEL feature is not available when OP_LOW is enabled.
Outputs DO[23:0], CO[3:1] and CLKOUT are in TRI-STATE before PDB toggles HIGH because the OP-LOW
strap value has not been recognized until the DS92LV2412 powers up. Figure 26 shows the user controlled
release of the OP_LOW and automatic reset of OP_LOW set on the falling edge of LOCK. Figure 27 shows the
user controlled release of OP_LOW and manual reset of OP_LOW set. Note manual reset of OP_LOW can only
occur when LOCK is HIGH.
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2.0V
PDB
LOCK
OP_ LOW
SET
(Strap pin)
User
User
controlled
controlled
OP_ LOW
RELEASE/SET
(Register)
DO[23:0],
CO3, CO2, CO1
TRI-
STATE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TRI-
STATE
CLKOUT
Figure 26. OP_LOW Auto Set
2.0V
PDB
LOCK
OP_LOW
SET
(Strap pin)
User
User
controlled
controlled
OP_ LOW
RELEASE/SET
(Register)
DO[23:0],
CO3, CO2, CO1
TRI-
STATE
ACTIVE
ACTIVE
TRI-
STATE
CLKOUT
Figure 27. OP_LOW Manual Set/Reset
8.3.2.7 Des — Clock Edge Select (RFB)
The RFB Pin determines the edge that the data is strobed on. If RFB is High, output data is strobed on the
Rising edge of the CLKOUT. If RFB is Low, data is strobed on the Falling edge of the CLKOUT. This allows for
inter-operability with downstream devices. The Des output does not need to use the same edge as the Ser input.
This feature may be controlled by the external Pin or by register.
8.3.2.8 Des — Control Signal Filter — Optional
The deserializer provides an optional Control Signal (C3, C2, C1) filter that monitors the three control signals and
eliminates any pulses or glitches that are 1 or 2 parallel clock periods wide. Control signals must be 3 parallel
clock periods wide (in its HIGH or LOW state, regardless of which state is active). This is set by the CONFIG[1:0]
strap option or by I2C register control.
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8.3.2.9 Des — SSCG Low Frequency Optimization (Lf_mode)
Text to come. This feature may be controlled by the external Pin or by Register.
8.3.2.10 Des — Strap Input Pins
Configuration of the device maybe done via configuration input Pins and the STRAP input Pins, or via the Serial
Control Bus. The STRAP input Pins share select parallel bus output Pins. They are used to load in configuration
values during the initial power up sequence of the device. Only a pull-up on the Pin is required when a HIGH is
desired. By default the pad has an internal pull down, and will bias Low by itself. The recommended value of the
pull up is 10 kΩ to VDDIO; open (NC) for Low, no pull-down is required (internal pull-down). If using the Serial
Control Bus, no pull ups are required.
8.3.3 Built In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is
useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST
mode only a input clock is required along with control to the Ser and Des BISTEN input Pins. The Ser outputs a
test pattern (PRBS7) and drives the link at speed. The Des detects the PRBS7 pattern and monitors it for errors.
A PASS output Pin toggles to flag any payloads that are received with 1 to 24 errors. Upon completion of the
test, the result of the test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS
indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration
of the test is controlled by the pulse width applied to the Des BISTEN Pin. During the BIST duration, the
deserializer data outputs toggle with a checkerboard pattern.
Inter-operability is supported between this Channel Link II device and all Channel Link II generations (Gen 1/2/3).
Note: In order to use BIST mode, the BISTEN Pin must be pulled high and REG = 0. The serializer cannot be
placed in BIST mode if REG = 1, as this will cause the DS92LV2411 to ignore the pin input voltage.
8.3.3.1 Sample BIST Sequence
See Figure 28 for the BIST mode flow diagram.
Step 1: Place the DS92LV2411 Ser in BIST Mode by setting Ser BISTEN = H. For the DS92LV2411 Ser or
DS99R421 Channel Link II Ser BIST Mode is enabled via the BISTEN Pin. A CLKIN is required for BIST. When
the Des detects the BIST mode pattern and command (DCA and DCB code) the data and control signal outputs
are shut off.
Step 2: Place the DS92LV2412 Des in BIST mode by setting the BISTEN = H. The Des is now in the BIST mode
and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS Pin
will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and
counted to determine the payload error rate.
Step 3: To Stop the BIST mode, the Des BISTEN Pin is set Low. The Des stops checking the data and the final
test result is held on the PASS Pin. If the test ran error free, the PASS output will be High. If there was one or
more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the
device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the BISTEN signal.
Step 4: To return the link to normal operation, the Ser BISTEN input is set Low. The Link returns to normal
operation.
Figure 29 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2
shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link
(differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting
the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or Rx Equalization).
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Normal
Step 1: SER in BIST
BIST
Wait
Step 2: Wait, DES in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: SER in Normal
Figure 28. BIST Mode Flow Diagram
8.3.3.2 BER Calculations
It is possible to calculate the approximate Bit Error Rate (BER). The following is required:
•
•
•
Clock Frequency (MHz)
BIST Duration (seconds)
BIST test Result (PASS)
The BER is less than or equal to one over the product of 24 times the CLK rate times the test duration. If we
assume a 50 MHz clock, a 10 minute (600 second) test, and a PASS, the BERT is ≤ 1.39 X 10E-12
The BIST mode runs a check on the data payload bits. The LOCK Pin also provides a link status. It the recovery
of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK Pin will switch Low. The
combination of the LOCK and At-Speed BIST PASS Pin provides a powerful tool for system evaluation and
performance monitoring.
BISTEN
(SER)
BISTEN
(DES)
CLKOUT
(RFB = L)
DO[23:0]
CO1,CO2,CO3
DATA
(internal)
PASS
Prior Result
Prior Result
PASS
FAIL
X = bit error(s)
DATA
(internal)
X
X
X
PASS
BIST
Result
Held
Normal
PRBS
Normal
BIST Test
BIST Duration
Figure 29. BIST Waveforms
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8.4 Device Functional Modes
8.4.1 Data Transfer
The DS92LV2411 / DS92LV2412 chipset will transmit and receive a pixel of data in the following format: C1 and
C0 represent the embedded clock in the serial stream. C1 is always HIGH and C0 is always LOW. The
remaining 26 bit spaces contain the scrambled, encoded and DC-Balanced serial data.
8.4.2 Serializer and Deserializer Operating Modes and Reverse Compatibility (Config[1:0])
The DS92LV2411 / DS92LV2412 chipset is compatible with other single serial lane Channel Link II or FPD-Link II
devices. Configuration modes are provided for reverse compatibility with the DS90C241 / DS90C124 and also
the DS90UR241 / DS90UR124 by setting the respective mode with the CONFIG[1:0] Pins on the Ser or Des as
shown in Table and Table. This selection also determines whether the Control Signal Filter feature is enabled or
disabled in the Normal mode. These configuration modes are selectable the control Pins only.
Table 9. DS92LV2411 Serializer Modes
CONFIG1
CONFIG0
MODE
DES DEVICE
Normal Mode, Control Signal Filter disabled DS92LV2412, DS92LV2412, DS92LV0422,
DS92LV0412
L
L
Normal Mode, Control Signal Filter enabled
DS92LV2412, DS92LV2412, DS92LV0422,
DS92LV0412
L
H
H
H
L
Reverse Compatibility Mode
Reverse Compatibility Mode
DS90UR124, DS99R124
DS90C124
H
Table 10. DS92LV2412 Serializer Modes
CONFIG1
CONFIG0
MODE
SER DEVICE
Normal Mode, Control Signal Filter disabled DS92LV2411, DS92LV2411, DS92LV0421,
DS92LV0411
L
L
Normal Mode, Control Signal Filter enabled
DS92LV2411, DS92LV2411, DS92LV0421,
DS92LV0411
L
H
H
H
L
Reverse Compatibility Mode
Reverse Compatibility Mode
DS90UR241
DS90C241
H
8.4.3 Video Control Signal Filter — Serializer and Deserializer
When operating the devices in Normal Mode, the Control Signals have the following restrictions:
•
•
•
Normal Mode with Control Signal Filter Enabled: Control Signal 1 and Control Signal 2 — Only 2 transitions
per 130 clock cycles are transmitted, the transition pulse must be 3 parallel clocks or longer.
Normal Mode with Control Signal Filter Disabled: Control Signal 1 and Control Signal 2 — Only 2 transitions
per 130 clock cycles are transmitted, no restriction on minimum transition pulse.
Control Signal 3 — Only 1 transition per 130 clock cycles is transmitted , minimum pulse width is 130 clock
cycles.
Control Signals are defined as low frequency signals with limited transition. Glitches of a control signal can cause
a visual error in display applications. This feature allows for the chipset to validate and filter out any high
frequency noise on the control signals. See Figure.
8.5 Programming
8.5.1 Optional Serial Bus Control
The Ser and Des may also be configured by the use of a serial control bus that is I2C protocol compatible. By
default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap Pins. A write of 01'h to
reg_0x00'h will enable/allow configuration by registers; this will override the control/strap Pins. Multiple devices
may share the serial control bus since multiple addresses are supported. See Figure 30.
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Programming (continued)
The serial bus is comprised of three Pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data
Input / Output signal. Both SCL and SDA signals require an external pull up resistor to VDDIO. For most
applications a 4.7 k pull up resistor to VDDIO may be used. The resistor value may be adjusted for capacitive
loading and data rate requirements. The signals are either pulled High, or driven Low.
1.8V
10 k
V
DDIO
ID[X]
4.7k
4.7k
SER
or
R
ID
HOST
SCL
SDA
SCL
SDA
DES
To other
Devices
Figure 30. Serial Control Bus Connection
The third Pin is the ID[X] Pin. This Pin sets one of four possible device addresses. As shown in Figure 30 ,
Table 11 and Table 12 different Resistor values could be used to set different SMBUS addresses.
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SDA transitions Low while SCL is High. A STOP occurs when SDA transition High while SCL is also HIGH. See
Figure 31
SDA
SCL
S
P
STOP condition
START condition, or
START repeat condition
Figure 31. Start and Stop Conditions
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 32 and a WRITE is shown in Figure 33.
If the Serial Bus is not required, the three Pins may be left open (NC).
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Programming (continued)
Table 11. Id[X] Resistor Value – DS92LV2411 Serializer
RESISTOR
RID kΩ
ADDRESS
7'b
ADDRESS
8'b
0 APPENDED
(WRITE)
0.47
2.7
7b' 110 1001 (h'69)
7b' 110 1010 (h'6A)
7b' 110 1011 (h'6B)
7b' 110 1110 (h'6E)
8b' 1101 0010 (h'D2)
8b' 1101 0100 (h'D4)
8b' 1101 0110 (h'D6)
8b' 1101 1100 (h'DC)
8.2
Open
Table 12. Id[X] Resistor Value – DS92LV2412 Deserializer
RESISTOR
RID kΩ
ADDRESS
7'b
ADDRESS
8'b
0 APPENDED
(WRITE)
0.47
2.7
7b' 111 0001 (h'71)
7b' 111 0010 (h'72)
7b' 111 0011 (h'73)
7b' 111 0110 (h'76)
8b' 1110 0010 (h'E2)
8b' 1110 0100 (h'E4)
8b' 1110 0110 (h'E6)
8b' 1110 1100 (h'EC)
8.2
Open
Register Address
Slave Address
Slave Address
Data
a
a
c
k
a
c
k
a
c
k
A
2
A
1
A
0
A
2
A
1
A
0
c
0
S
S
1
P
k
Figure 32. Serial Control Bus — Read
Register Address
Slave Address
Data
a
c
a
c
k
a
c
k
A
2
A
1
A
0
0
S
P
k
Figure 33. Serial Control Bus — Write
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8.6 Register Maps
Table 13. Serializer — Serial Bus Control Registers
ADD ADD
(dec) (hex)
REGISTER
NAME
Bit(s)
R/W
DEFAULT
(bin)
FUNCTION
DESCRIPTION
0
0
Ser Config 1
7
6
5
R/W
R/W
R/W
0
0
0
Reserved
Reserved
Reserved
Reserved
VODSEL
0: Low
1: High
4
R/W
R/W
0
RFB
0: Data latched on Falling edge of CLKIN
1: Data latched on Rising edge of CLKIN
3:2
00
CONFIG
00: Control Signal Filter Disabled
01: Control Signal Filter Enabled
10: Reserved
11: Reserved
1
R/W
0
SLEEP
Note – not the same function as PowerDown
(PDB)
0: normal mode
1: Sleep Mode – Register settings retained.
0
7
R/W
R/W
R/W
0
0
REG
0: Configurations set from control Pins
1: Configuration set from registers (except I2C_ID)
1
2
1
2
Device ID
REG ID
ID[X]
0: Address from ID[X] Pin
1: Address from Register
6:0
1101000
Serial Bus Device ID, Four IDs are:
7b '1101 001 (h'69)
7b '1101 010 (h'6A)
7b '1101 011 (h'6B)
7b '1101 110 (h'6E)
All other addresses are Reserved.
De-Emphasis
Control
7:5
R/W
000
De-E Setting
000: set by external Resistor
001: -1 dB
010: -2 dB
011: -3.3 dB
100: -5 dB
101: -6.7 dB
110: -9 dB
111: -12 dB
4
R/W
R/W
0
De-E EN
0: De-Emphasis Enabled
1: De-Emphasis Disabled
3:0
000
Reserved
Reserved
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Table 14. Deserializer — Serial Bus Control Registers
ADD ADD
(dec) (hex)
REGISTER
NAME
Bit(s)
R/W
R/W
R/W
R/W
R/W
R/W
DEFAULT
(bin)
FUNCTION
LF_MODE
DESCRIPTION
0
0
Des Config 1
7
6
0
0: 20 to 50 MHz SSCG Operation
1: 5 to 20 MHz SSCG Operation
0
OS_CLKOUT
OS_DATA
RFB
0: Normal CLKOUT Slew Rate
1: Increased CLKOUT Slew Rate
5
0
0: Normal DATA Slew Rate
1: Increased DATA Slew Rate
4
0
0: Data strobed on Falling edge of CLKOUT
1: Data strobed on Rising edge of CLKOUT
3:2
00
CONFIG
00: Normal Mode, Control Signal Filter Disabled
01: Normal Mode, Control Signal Filter Enabled
10: Reserved
11: Reserved
1
0
R/W
R/W
0
0
SLEEP
Note – not the same function as PowerDown (PDB)
0: Normal Mode
1: Sleep Mode – Register settings retained.
REG Control
0: Configurations set from control Pins / STRAP
Pins
1: Configurations set from registers (except I2C_ID)
1
2
1
2
Slave ID
7
R/W
R/W
0
0: Address from ID[X] Pin
1: Address from Register
6:0
1110000
ID[X]
Serial Bus Device ID, Four IDs are:
7b '1110 001 (h'71)
7b '1110 010 (h'72)
7b '1110 011 (h'73)
7b '1110 110 (h'76)
All other addresses are Reserved.
Des Features 1
7
6
R/W
R/W
0
0
OP_LOW
OSS_SEL
0: Set outputs state LOW (except LOCK)
1: Release output LOW state, outputs toggling
normally
Note: This register only works during LOCK = 1
Output Sleep State Select
0: CLKOUT, DO[23:0], CO1, CO2, CO3 = L, LOCK
= Normal, PASS = H
1: CLKOUT, DO[23:0], CO1, CO2, CO3 = Tri-State,
LOCK = Normal, PASS = H
5:4
3
R/W
R/W
00
0
Reserved
Reserved
OP_LOW Strap
Bypass
0: Strap will determine whether OP_LOW feature is
ON or OFF
1: Turns OFF OP_LOW feature
2:0
R/W
00
OSC_SEL
000: disable
001: 50 MHz ±40%
010: 25 MHz ±40%
011: 16.7 MHz ±40%
100: 12.5 MHz ±40%
101: 10 MHz ±40%
110: 8.3 MHz ±40%
111: 6.3 MHz ±40%
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Table 14. Deserializer — Serial Bus Control Registers (continued)
ADD ADD
(dec) (hex)
REGISTER
NAME
Bit(s)
R/W
DEFAULT
(bin)
FUNCTION
EQ Gain
DESCRIPTION
3
3
Des Features 2
7:5
R/W
000
000: ~1.625 dB
001: ~3.25 dB
010: ~4.87 dB
011: ~6.5 dB
100: ~8.125 dB
101: ~9.75 dB
110: ~11.375 dB
111: ~13 dB
4
R/W
R/W
0
EQ Enable
SSC
0: EQ = disable
1: EQ = enable
3:0
0000
IF LF_MODE = 0, then:
000: SSCG disable
0001: fdev = ±0.5%, fmod = CLK/2168
0010: fdev = ±1.0%, fmod = CLK/2168
0011: fdev = ±1.5%, fmod = CLK/2168
0100: fdev = ±2.0%, fmod = CLK/2168
0101: fdev = ±0.5%, fmod = CLK/1300
0110: fdev = ±1.0%, fmod = CLK/1300
0111: fdev = ±1.5%, fmod = CLK/1300
1000: fdev = ±2.0%, fmod = CLK/1300
1001: fdev = ±0.5%, fmod = CLK/868
1010: fdev = ±1.0%, fmod = CLK/868
1011: fdev = ±1.5%, fmod = CLK/868
1100: fdev = ±2.0%, fmod = CLK/868
1101: fdev = ±0.5%, fmod = CLK/650
1110: fdev = ±1.0%, fmod = CLK/650
1111: fdev = ±1.5%, fmod = CLK/650
IF LF_MODE = 1, then:
000: SSCG disable
0001: fdev = ±0.5%, fmod = CLK/620
0010: fdev = ±1.0%, fmod = CLK/620
0011: fdev = ±1.5%, fmod = CLK/620
0100: fdev = ±2.0%, fmod = CLK/620
0101: fdev = ±0.5%, fmod = CLK/370
0110: fdev = ±1.0%, fmod = CLK/370
0111: fdev = ±1.5%, fmod = CLK/370
1000: fdev = ±2.0%, fmod = CLK/370
1001: fdev = ±0.5%, fmod = CLK/258
1010: fdev = ±1.0%, fmod = CLK/258
1011: fdev = ±1.5%, fmod = CLK/258
1100: fdev = ±2.0%, fmod = CLK/258
1101: fdev = ±0.5%, fmod = CLK/192
1110: fdev = ±1.0%, fmod = CLK/192
1111: fdev = ±1.5%, fmod = CLK/192
4
4
ROUT Config
7
R/W
R/W
0
Repeater Enable 0: Output ROUT+/- = disable
1: Output ROUT+/- = enable
6:0
0000000
Reserved
Reserved
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9 Applications and Implementation
9.1 Application Information
The DS92LV2411/DS92LV2412 chipset is intended for interface between a host (graphics processor) and a
Display. It supports an 24-bit color depth (RGB888). In a RGB888 application, 24 color bits (D[23:0), Pixel Clock
(CLKIN) and three control bits (C1, C2, C3) are supported across the serial link with CLK rates from 5 to 50 MHz.
The chipset may also be used in 18-bit color applications. In this application three to six general purpose signals
may also be sent from host to display.
The Des is expected to be located close to its target device. The interconnect between the Des and the target
device is typically in the 1 to 3 inch separation range. The input capacitance of the target device is expected to
be in the 5 to 10 pF range. Care should be taken on the CLK output trace as this signal is edge sensitive and
strobes the data. It is also assumed that the fanout of the Des is one. If additional loads need to be driven, a
logic buffer or mux device is recommended.
9.2 Typical Applications
V
V
DDn
1.8V
V
V
DDIO
DDIO
(1.8Vor3.3V)
DDn
1.8V (1.8Vor3.3V)
DI[7:0]
DI[15:8]
DI[23:16]
CI1
CI2
CI3
DO[7:0]
DO[15:8]
DO[23:16]
CO1
CO2
CO3
Channel Link II
1 Pair /AC Coupled
Graphic
Processor
OR
Video
Imager
OR
24-bit RGB
Display
OR
0.1 PF
0.1 PF
DOUT+
DOUT-
RIN+
RIN-
ASIC/FPGA
CLKIN
CLKOUT
100 ohm STP Cable
ASIC/FPGA
DS92LV2411
Serializer
DS92LV2412
Deserializer
LOCK
PASS
PDB
CMF
PDB
BISTEN
BISTEN
RFB
VODSEL
DeEmph
STRAP pins
not shown
SCL
SDA
ID[x]
SCL
SDA
ID[x]
Optional
Optional
DAP
DAP
Figure 34. Typical Application Schematic for DS92LV2411, DS92LV2412 Ser/Des Pair
9.2.1 Design Requirements
For this typical design application, use the following as input parameters.
Table 15. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
1.8 V or 3.3 V
1.8 V
VDDIO
VDDn
AC Coupling Capacitor for DOUT± and RIN±
CLK Frequency
0.1 µF
50 MHz
9.2.2 Detailed Design Procedure
9.2.2.1 Typical Application Connection
Figure 35 shows a typical connection diagram of the DS92LV2411 Ser in Pin control mode for a 24-bit
application. The CML outputs require 0.1 µF AC coupling capacitors to the line. The line driver includes internal
termination. Bypass capacitors are placed near the power supply Pins. At a minimum, four 0.1 µF capacitors and
a 4.7 µF capacitor should be used for local device bypassing. System GPO (General Purpose Output) signals
control the PDB and BISTEN Pins. In this application the RFB Pin is tied Low to latch data on the falling edge of
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the CLKIN. In this example the cable is long, therefore the VODSEL Pin is tied High and a De-Emphasis value is
selected by the resistor R1. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO Pin is
connected also to the 1.8V rail. The optional Serial Bus control is not used in this example, thus the SCL, SDA
and ID[x] Pins are left open. A delay cap is placed on the PDB signal to delay the enabling of the device until
power is stable.
DS92LV2411 (SER)
1.8V
VDDIO
VDDIO
VDDTX
VDDHS
C9
C7
C8
C10
FB1
C3
C4
FB2
FB3
FB4
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
VDDP
VDDL
C11
C5
C6
DI8
DI9
C1
C2
DI10
DI11
DI12
DI13
DI14
DI15
Serial
DOUT+
DOUT-
Channel Link II
Interface
LVCMOS
Parallel
Video
Interface
DI16
DI17
DI18
DI19
DI20
DI21
DI22
DI23
VDDIO
CLKIN
VODSEL
De-Emph
CI1
CI2
CI3
1.8V
R1
LVCMOS
Control
Interface
10k
RID
BISTEN
PDB
ID[X]
SCL
SDA
C12
NOTE:
C1-C2 = 0.1 PF
C3-C8 = 0.1 PF
C9-11 = 4.7 PF
C12 = >10 PF
R1 (cable specific)
RID (see ID[x] Resistor Value Table 12)
FB1-FB4: Impedance = 1 k:,
low DC resistance (<1:)
CONFIG1
CONFIG0
RFB
RES2
RES1
RES0
DAP (GND)
Figure 35. DS92LV2411 Typical Connection Diagram — Pin Control
Figure 36 shows a typical connection diagram of the DS92LV2412 Des in Pin/strap control mode for a 24-bit
application. The CML inputs utilize 0.1 µF coupling capacitors to the line and the receiver provides internal
termination. Bypass capacitors are placed near the power supply Pins. At a minimum, seven 0.1 µF capacitors
and two 4.7 µF capacitors should be used for local device bypassing. System GPO (General Purpose Output)
signals control the PDB and the BISTEN Pins. In this application the RFB Pin is tied Low to strobe the data on
the falling edge of the CLKOUT.
Since the device in the Pin/STRAP mode, four 10 kΩ pull up resistors are used on the parallel output bus to
select the desired device features. CFEN is set to 1 for Normal Mode with Control Signal Filter enabled, this is
accomplished with the STRAP pull-up on DO23. The receiver input equalizer is also enabled and set to provide
7.5 dB of gain, this is accomplished with EQ[3:0] set to 1001'b with STRAP pull ups on DO12 and DO15. To
reduce parallel bus EMI, the SSCG feature is enabled and set to fmod = CLK/2168 and ±1% with SSC[3:0] set to
0010'b and a STRAP pull-up on DO4. The desired features are set with the use of the four pull up resistors.
The interface to the target display is with 3.3V LVCMOS levels, thus the VDDIO Pin is connected to the 3.3 V
rail. The optional Serial Bus Control is not used in this example, thus the SCL, SDA and ID[x] Pins are left open.
A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
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DS92LV2412 (DES)
VDDIO
1.8V
VDDL
VDDIO
VDDIO
VDDIO
C13
C11
C8
C12 C14
C3
C4
C5
VDDSC
VDDPR
VDDR
C9
C10
C15
C6
VDDIR
VDDIO
EXAMPLE:
STRAP
Input
VDDCMLO
C16
C7
Pull-Ups
(10k)
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
C1
C2
Serial
Channel Link II
Interface
RIN+
RIN-
CMF
C17
DO8
DO9
TP_A
TP_B
ROUT+
ROUT-
DO10
DO11
DO12
DO13
DO14
DO15
LVCMOS
Parallel
Video
Host
Control
BISTEN
PDB
Interface
C18
DO16
DO17
DO18
DO19
DO20
DO21
DO22
DO23
1.8V
10k
RID
ID[X]
SCL
SDA
CO1
CO2
CO3
C1 - C2 = 0.1 PF
C3 - C12 = 0.1 PF
C13, C16 = 4.7 PF
C17 = 4.7 PF
NC
8
CLKOUT
RES
DAP (GND)
LOCK
PASS
C18 = >10 PF
RID (see ID[x] Resistor Value Table 13)
FB1-FB4: Impedance = 1 k:,
low DC resistance (<1:)
Figure 36. DS92LV2412 Typical Connection Diagram — Pin Control
9.2.2.2 Power Up Requirements and PDB Pin
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms
then a capacitor on the PDB Pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB Pin is pulled to VDDIO, it is recommended to use a 10 kΩ pull-up
and a 22 uF cap to GND to delay the PDB input signal.
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9.2.2.3 Transmission Media
The Ser/Des chip set is intended to be used in a point-to-point configuration, through a PCB trace, through
twisted pair cable or through 50Ω coaxial cables. The Ser and Des provide internal terminations providing a
clean signaling environment. The interconnect for the differential serial interface should present a differential
impedance of 100Ω. Use cables and connectors that have matched differential impedance to minimize
impedance discontinuities. Shielded or un-shielded cables may be used depending upon the noise environment
and application requirements.
For 50Ω coaxial cable serial interfaces, any unused input or output Pin must be terminated with an 0.1 µF AC
coupling capacitor and a 50Ω resistor to ground. The PCB traces and serial interconnect should have a single
ended impedance of 50Ω.
9.2.2.4 Live Link Insertion
The Ser and Des devices support live pluggable applications. The automatic receiver lock to random data “plug
and go” hot insertion capability allows the DS92LV2412 to attain lock to the active data stream during a live
insertion event.
9.2.2.5 Serial Interconnect Guidelines
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
•
•
Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
–
–
–
S = space between the pair
2S = space between pairs
3S = space to LVCMOS signal
•
•
•
•
•
Minimize the number of Vias
Use differential connectors when operating above 500Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas
Instruments web site at: http://www.ti.com/ww/en/analog/interface/lvds.shtml
9.2.3 Application Curves
CML
Serializer Data
Throughput
CML
Serializer Data
Throughput
(100 mV/DIV)
(100 mV/DIV)
50 MHz TX
Pixel Clock
Input
50 MHz TX
Pixel Clock
Input
(2 V/DIV)
(2 V/DIV)
Time (4 ns/DIV)
Time (4 ns/DIV)
Figure 37. Serializer Output with 50 MHz TX Pixel Clock,
De-emphasis Disabled
Figure 38. Serializer Output with 50 MHz TX Pixel Clock,
De-emphasis Enabled
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10 Power Supply Recommendations
The devices are designed to operate from an input voltage supply of 1.8V. Some devices provide separate power
and ground Pins for different portions of the circuit. This is done to isolate switching noise effects between
different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables
typically provide guidance on which circuit blocks are connected to which power Pin pairs. In some cases, an
external filter may be used to provide clean power to sensitive circuits such as PLLs.
11 Layout
11.1 Layout Guidelines
Circuit board layout and stack-up for the Ser/Des devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply Pin, locate the smaller value closer to the Pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground Pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground Pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground Pins to the planes, reducing
the impedance at high frequency.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the CML
lines to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ohms
are typically recommended for differential interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
Information on the WQFN style package is provided in TI Application Note: AN-1187 (SNOA401).
11.2 Layout Example
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the LLP package is highly recommended to improve
board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:
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Layout Example (continued)
Figure 39. No Pullback LLP, Single Row Reference Diagram
Table 16. No Pullback LLP Stencil Aperture Summary for DS92LV2411 and DS92LV2412
Device
Pin
Count
MKT Dwg PCB I/O
Pad Size
PCB
Pitch
(mm)
PCB DAP
size (mm)
Stencil I/O
Aperture
(mm)
Stencil DAP Number of Gap Between DAP
Aperture
(mm)
DAP
Aperture
Openings
Aperture (Dim A
mm)
(mm)
0.25 x
SQA48A
DS92LV2411
DS92LV2412
48
60
0.5
0.5
5.1 x 5.1
7.2 x 7.2
0.25 x 0.7
0.25 x 0.9
1.1 x 1.1
16
25
0.2
0.3
0.6
0.25 x
SQA60B
1.16 x 1.16
0.8
Figure 40. 48-Pin WQFN Stencil Example of Via and Opening Placement
The following PCB layout examples are derived from the layout design of the DS9LV2411 and DS92LV2412 in
the LV24EVK01 Evaluation Module User's Guide (SNLU006). These graphics and additional layout description
are used to demonstrate both proper routing and proper solder techniques when designing in the Ser/Des pair.
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Figure 41. DS92LV2411 Serializer Example Layout
Figure 42. DS92LV2412 Deserializer Example Layout
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 17. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
DS92LV2411
DS92LV2412
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS92LV2411SQ/NOPB
DS92LV2411SQE/NOPB
DS92LV2411SQX/NOPB
DS92LV2412SQ/NOPB
DS92LV2412SQE/NOPB
DS92LV2412SQX/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RHS
RHS
RHS
NKB
NKB
NKB
48
48
48
60
60
60
1000 RoHS & Green
250 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
LV2411SQ
SN
SN
SN
SN
SN
LV2411SQ
LV2411SQ
LV2412SQ
LV2412SQ
LV2412SQ
2500 RoHS & Green
1000 RoHS & Green
250
RoHS & Green
2000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS92LV2411SQ/NOPB
WQFN
RHS
RHS
RHS
NKB
NKB
NKB
48
48
48
60
60
60
1000
250
330.0
178.0
330.0
330.0
178.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
7.3
7.3
7.3
9.3
9.3
9.3
7.3
7.3
7.3
9.3
9.3
9.3
1.3
1.3
1.3
1.3
1.3
1.3
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
DS92LV2411SQE/NOPB WQFN
DS92LV2411SQX/NOPB WQFN
2500
1000
250
DS92LV2412SQ/NOPB
WQFN
DS92LV2412SQE/NOPB WQFN
DS92LV2412SQX/NOPB WQFN
2000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS92LV2411SQ/NOPB
DS92LV2411SQE/NOPB
DS92LV2411SQX/NOPB
DS92LV2412SQ/NOPB
DS92LV2412SQE/NOPB
DS92LV2412SQX/NOPB
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RHS
RHS
RHS
NKB
NKB
NKB
48
48
48
60
60
60
1000
250
356.0
208.0
356.0
356.0
208.0
356.0
356.0
191.0
356.0
356.0
191.0
356.0
35.0
35.0
35.0
35.0
35.0
35.0
2500
1000
250
2000
Pack Materials-Page 2
PACKAGE OUTLINE
NKB0060B
VQFN - 0.8 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
9.1
8.9
A
B
PIN 1 INDEX AREA
9.1
8.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2X 7
6.3 0.1
SYMM
EXPOSED
THERMAL PAD
(0.1) TYP
16
30
15
31
SYMM
61
2X 7
1
0.3
60X
45
0.2
56X 0.5
60
46
0.1
C A B
0.7
0.5
PIN 1 ID
0.05
60X
4214995/A 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
NKB0060B
VQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
6.3)
SYMM
SEE SOLDER MASK
DETAIL
60X (0.8)
60X (0.25)
46
60
1
45
56X (0.5)
(1.1) TYP
(1.2) TYP
SYMM
(R0.05) TYP
(
0.2) TYP
VIA
61
(0.6) TYP
(8.6)
15
31
30
16
(0.6) TYP
(1.2) TYP
(1.1) TYP
(8.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214995/A 03/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
NKB0060B
VQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
25X ( 1)
(1.2) TYP
46
60X (0.8)
60X (0.25)
60
1
45
56X (0.5)
(R0.05) TYP
(1.2) TYP
(8.6)
61
SYMM
15
31
16
30
SYMM
(8.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 8X
EXPOSED PAD 61
63% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4214995/A 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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