DS92LV3241TVSX/NOPB [TI]
20-85MHz 32 位频道链接 II 串行器 | PAG | 64 | -40 to 85;
| 型号： | DS92LV3241TVSX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 20-85MHz 32 位频道链接 II 串行器 | PAG | 64 | -40 to 85 驱动 线路驱动器或接收器 驱动程序和接口 |
| 文件： | 总31页 (文件大小：1859K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS92LV3241, DS92LV3242
www.ti.com
SNLS314D –SEPTEMBER 2009–REVISED APRIL 2013
DS92LV3241/DS92LV3242 20-85 MHz 32-Bit Channel Link II Serializer / Deserializer
Check for Samples: DS92LV3241, DS92LV3242
1
FEATURES
APPLICATIONS
2
•
Wide Operating Range Embedded Clock
SER/DES
•
Industrial Imaging (Machine-Vision) and
Control
–
–
–
Up to 32-bit Parallel LVCMOS Data
20 to 85 MHz Parallel Clock
•
Security & Surveillance Cameras and
Infrastructure
•
•
Medical imaging
Up to 2.72 Gbps Application Data Paylod
Up to 30 bits per Pixel, VGA to HD Video
Transport and Display
•
•
Selectable Serial LVDS Bus Width
–
–
Dual Lane Mode (20 to 50 MHz)
Quad Lane Mode (40 to 85 MHz)
DESCRIPTION
Simplified Clocking Architecture
The DS92LV3241 (SER) serializes a 32-bit data bus
into 2 or 4 (selectable) embedded clock LVDS serial
channels for a data payload rate up to 2.72 Gbps
over cables such as CATx, or backplanes FR-4
traces. The companion DS92LV3242 (DES)
deserializes the 2 or 4 LVDS serial data channels,
de-skews channel-to-channel delay variations and
converts the LVDS data stream back into a 32-bit
LVCMOS parallel data bus.
–
–
–
No Separate Serial Clock Line
No reference Clock Required
Receiver Locks to Random Data
•
On-Chip Signal Conditioning for Robust Serial
Connectivity
–
–
–
–
–
Transmit Pre-Emphasis
Data Randomization
On-chip data Randomization/Scrambling and DC
balance encoding and selectable serializer Pre-
emphasis ensure a robust, low-EMI transmission over
longer, lossy cables and backplanes. The
Deserializer automatically locks to incoming data
without an external reference clock or special sync
patterns, providing an easy “plug-and-lock” operation.
DC-Balance Encoding
Receive Channel Deskew
Supports up to 10m CAT-5 at 2.7 Gbps
•
•
Integrated LVDS Terminations
Built-in AT-SPEED BIST for End-to-End
System Testing
By embedding the clock in the data payload and
including signal conditioning functions, the Channel-
Link II SerDes devices reduce trace count, eliminate
skew issues, simplify design effort and lower
cable/connector cost for a wide variety of video,
control and imaging applications. A built-in AT-
SPEED BIST feature validates link integrity and may
be used for system diagnostics.
•
AC-Coupled Interconnect for Isolation and
Fault Protection
•
•
•
> 4KV HBM ESD Protection
Space-Saving 64-pin TQFP Package
Full Industrial Temperature Range : -40° to
+85°C
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
DS92LV3241, DS92LV3242
SNLS314D –SEPTEMBER 2009–REVISED APRIL 2013
www.ti.com
Block Diagram
PLL
CDR/PLL
TxCLKIN
TxIN0
RxCLKOUT
RxOUT0
High-Speed Serial Data
100W differential pairs
RxIN0+
TxOUT0+
TxOUT0 -
TxOUT1+
RxIN0 -
RxIN1 +
RxOUT15
RxOUT16
TxIN15
TxIN16
TxOUT1 -
TxOUT2+
RxIN1 -
RxIN2+
RxOUT31
LOCK
TxIN31
TxOUT2 -
TxOUT3+
RxIN2 -
RxIN3 +
BIST
PDB
R_FB
BISTEN
MODE
VSEL
BIST
TxOUT3 -
RxIN3 -
REN
R_FB
PDB
Control
Control
Pre-Emp
PRE
Tx - SERIALIZER
Rx - DESERIALIZER
Mode Diagrams
DS92LV3241
DS92LV3242
TxOUT0P
RxIN0P
D
D
D
D
R
R
R
TxOUT0N
TxOUT1P
RxIN0N
RxIN1P
TxOUT1N
RxIN1N
32
32
TxIN
RxOUT
(LVCMOS Input)
(LVCMOS Output)
MODE = L
(Dual Mode)
R
TxCLKIN
RxCLKOUT
(20 MHz to 50 MHz)
(20 MHz to 50 MHz)
Tx - SERIALIZER
Rx - DESERIALIZER
Figure 1. 'Dual Mode
2
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SNLS314D –SEPTEMBER 2009–REVISED APRIL 2013
DS92LV3241
DS92LV3242
TxOUT0P
RxIN0P
D
R
R
R
TxOUT0N
TxOUT1P
RxIN0N
RxIN1P
D
TxOUT1N
TxOUT2P
RxIN1N
RxIN2P
32
32
TxIN
RxOUT
(LVCMOS Input)
(LVCMOS Output)
D
TxOUT2N
TxOUT3P
RxIN2N
RxIN3P
MODE = H
(Quad Mode)
D
R
TxCLKIN
RxCLKOUT
(40 MHz to 85 MHz)
(40 MHz to 85 MHz)
TxOUT3N
RxIN3N
Tx - SERIALIZER
Rx - DESERIALIZER
Figure 2. Quad Mode
DS92LV3241 Pin Diagram
IOVDD
IOVSS
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
VSS
TxIN14
TxIN15
VDDPLL
VSSPLL
VSSPLL
VDDPLL
TxIN16
TxIN17
TxIN18
TxIN19
TxIN20
TxIN21
TxIN22
TxIN23
TxOUT0+
TxOUT0-
TxOUT1+
TxOUT1-
VDDA
DS92LV3241
VSSA
TxOUT2+
TxOUT2-
TxOUT3+
TxOUT3-
VSEL
PRE
VDD
VSS
Figure 3. DS92LV3241 Pin Diagram- Top View
64-Pin TQFP (PAG Package)
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SNLS314D –SEPTEMBER 2009–REVISED APRIL 2013
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DS92LV3241 Serializer PIN DESCRIPTIONS
Pin #
Pin Name
I/O, Type
Description
LVCMOS PARALLEL INTERFACE PINS
10–8,
5–1,
TxIN[31:29], I, LVCMOS
TxIN[28:24],
Serializer Parallel Interface Data Input Pins.
64–57,
52–51,
48–44.
41–33
TxIN[23:16],
TxIN[15:14],
TxIN[13:9],
TxIN[8:0]
11
TxCLKIN
I, LVCMOS
Serializer Parallel Interface Clock Input Pin. Strobe edge set by R_FB configuration pin.
CONTROL AND CONFIGURATION PINS
12
PDB
I, LVCMOS
Serializer Power Down Bar (ACTIVE LOW)
PDB = L; Device Disabled, Differential serial outputs are put into TRI-STATE stand-by mode,
PLL is shutdown
PDB = H; Device Enabled
15
19
14
20
13
16
MODE
PRE
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
Dual or Quad mode select (ACTIVE H)
MODE = L (default); Dual Mode,
MODE = H; Quad Mode
PRE-emphasis level select pin
PRE = (RPRE > 12kΩ); Imax = [(1.2/R) x 20 x 2], Rmin = 12kΩ.
PRE = H or floating; pre-emphasis is disabled.
R_FB
VSEL
BISTEN
RSVD
Rising/Falling Bar Clock Edge Select
R_FB = H; Rising Edge,
R_FB = L; Falling Edge
VOD (Differential Output Voltage) Llevel Select
VSEL = L; Low Swing,
VSEL = H; High Swing
BIST Enable
BISTEN = L; BIST OFF, (default), normal operating mode.
BISTEN = H; BIST Enabled (ACTIVE HIGH)
Reserved — MUST BE TIED LOW
LVDS SERIAL INTERFACE PINS
22, 24,
28, 30
TxOUT[3:0]+ O, LVDS
Serializer LVDS Non-Inverted Outputs(+)
Serializer LVDS Inverted Outputs(-)
21, 23,
27, 29
TxOUT[3:0]- O, LVDS
POWER / GROUND PINS
7, 18, 32, VDD
42
VDD
GND
Digital Voltage supply, 3.3V
Digital ground
6, 17, 31, VSS
43
53, 56
54, 55
26
VDDPLL
VSSPLL
VDDA
VDD
GND
VDD
GND
VDD
Analog Voltage supply, PLL POWER, 3.3V
Analog ground, PLL GROUND
Analog Voltage supply
25
VSSA
Analog ground
49
IOVDD
Digital IO Voltage supply
Connect to 1.8V typ for 1.8V LVCMOS interface
Connect to 3.3V typ for 3.3V LVCMOS interface
50
IOVSS
GND
Digital IO ground
4
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SNLS314D –SEPTEMBER 2009–REVISED APRIL 2013
DS92LV3242 Pin Diagram
Top View
PDB
REN
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RxOUT12
RxOUT13
RxOUT14
RxOUT15
RxOUT16
VSS
RxIN0+
RxIN0-
RxIN1+
RxIN1-
VDDA
VDD
DS92LV3242
VSSA
RxOUT17
RxOUT18
RxOUT19
RxOUT20
RxOUT21
RxOUT22
RxOUT23
VSS
RxIN2+
RxIN2-
RxIN3+
RxIN3-
VDD
VSS
VSSPLL
VDDPLL
VDD
Figure 4. DS92LV3242 Pin Diagram
64-Pin TQFP (PAG Package)
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SNLS314D –SEPTEMBER 2009–REVISED APRIL 2013
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DS92LV3242 Deserializer PIN DESCRIPTIONS
Pin #
LVCMOS PARALLEL INTERFACE PINS
5–7, RxOUT[31:29], O, LVCMOS Deserializer Parallel Interface Data Output Pins.
Pin Name
I/O, Type
Description
10–14, RxOUT[28:24],
19–25, RxOUT[23:17],
28–32, RxOUT[16:12],
33–39, RxOUT[11:5],
42–46
RxOUT[4:0]
4
RxCLKOUT
O, LVCMOS Deserializer Recovered Clock Output. Parallel data rate clock recovered from the embedded
clock.
3
LOCK
O, LVCMOS LOCK indicates the status of the receiver PLL LOCK = L; deserializer CDR/PLL is not locked,
RxOUT[31:0] and RCLK are TRI-STATED
LOCK = H; deserializer CDR/PLL is locked
CONTROL AND CONFIGURATION PINS
48
50
49
R_FB
REN
PDB
I, LVCMOS
I, LVCMOS
I, LVCMOS
Rising/Falling Bar Clock Edge Select
R_FB = H; RxOUT clocked on rising edge
R_FB = L; RxOUT clocked on falling edge
Deserializer Enable, DES Output Enable Control Input (ACTIVE HIGH)
REN = L; disabled, RxOUT[31:0] and RxCLKOUT TRI-STATED, PLL still operational
REN = H; Enabled (ACTIVE HIGH)
Power Down Bar, Control Input Signal (ACTIVE LOW)
PDB = L; disabled, RxOUT[31:0], RCLK, and LOCK are TRI-STATED in stand-by mode, PLL
is shutdown
PDB = H; Enabled
47
RSVD
I, LVCMOS
Reserved — MUST BE TIED LOW
LVDS SERIAL INTERFACE PINS
51, 53, RxIN[0:3]+
57, 59
I, LVDS
Deserializer LVDS Non-Inverted Inputs(+)
Deserializer LVDS Inverted Inputs(-)
52, 54, RxIN[0:3]-
58, 60
I, LVDS
POWER / GROUND PINS
9, 16,
17, 26,
61
VDD
VDD
GND
Digital Voltage supply, 3.3V
Digital Ground
8, 15,
18, 27,
62
VSS
55
56
VDDA
VDD
GND
VDD
Analog LVDS Voltage supply, POWER, 3.3V
Analog LVDS GROUND
VSSA
1, 40,
64
VDDPLL
Analog Voltage supply PLL VCO POWER, 3.3V
2, 41,
63
VSSPLL
GND
Analog ground, PLL VCO GROUND
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6
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SNLS314D –SEPTEMBER 2009–REVISED APRIL 2013
Absolute Maximum Ratings(1)(2)
Supply Voltage (VDD
)
−0.3V to +4V
−0.3V to (VDD +0.3V)
−0.3V to (VDD +0.3V)
−0.3V to +3.9V
−0.3V to +3.9V
+125°C
LVCMOS Input Voltage
LVCMOS Output Voltage
LVDS Deserializer Input Voltage
LVDS Driver Output Voltage
Junction Temperature
Storage Temperature
−65°C to +150°C
+260°C
Lead Temperature (Soldering, 4 seconds)
Maximum Package Power Dissipation Capacity Package Derating
θJA
1/θJA °C/W above +25°C
35.7 °C/W(3)
θJC
12.6 °C/W
ESD Rating (HBM)
>4 kV
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) 4 Layer JEDEC
Recommended Operating Conditions
Min
3.135
3.135
1.71
−40
20
Nom
3.3
Max
3.465
3.465
1.89
+85
50
Units
V
Supply Voltage (VDD
)
Supply Voltage(IOVDD
(SER ONLY)
)
3.3V I/O Interface
1.8V I/O Interface
3.3
V
1.8
V
Operating Free Air Temperature (TA)
Input Clock Rate
+25
°C
Dual Mode
Quad Mode
MHz
MHz
mVP-P
40
85
Tolerable Supply Noise
100
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Units
Electrical Characteristics(1)(2)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
Low Level Input Voltage
Tx: IOVDD = 1.71V to 1.89V
0.65 x
IOVDD
IOVDD
0.3
+
V
Tx: IOVDD = 3.135V to 3.465V
Rx
2.0
VDD
VIL
Tx: IOVDD = 1.71V to 1.89V
0.35 x
IOVDD
GND
GND
V
Tx: IOVDD = 3.135V to 3.465V
0.8
Rx
VCL
IIN
Input Clamp Voltage
Input Current
ICL = −18 mA
−0.8
−1.5
+10
+10
V
Tx: VIN = 0V or 3.465V(1.89V)
IOVDD = 3.465V(1.89V)
−10
−10
µA
Rx: VIN = 0V or 3.465V
IOH = −2mA (Dual)
IOH = −2mA (Quad)
IOH = −2mA (Dual)
IOH = −2mA (Quad)
VOUT = 0V (Dual)
VOH
VOL
IOS
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
TRI-STATE Output Current
2.4
3.0
VDD
0.5
V
V
GND
0.33
−22
−33
−40
−70
mA
mA
VOUT = 0V (Quad)
IOZ
PDB = 0V,
VOUT = 0V or VDD
−10
+10
μA
SERIALIZER LVDS DC SPECIFICATIONS
VOD
Output Differential Voltage
No pre-emphasis, VSEL = L
(VSEL = H)
350
(629)
440
(850)
525
(1000)
50
mVP-P
ΔVOD
VOS
Output Differential Voltage Unbalance
Offset Voltage
VSEL = L, No pre-emphasis
VSEL = L, No pre-emphasis
VSEL = L, No pre-emphasis
1
1.25
4
mVP-P
V
1.00
1.50
50
ΔVOS
IOS
Offset Voltage Unbalance
Output Short Circuit Current
mV
TxOUT[3:0] = 0V, PDB = VDD
VSEL = L, No pre-emphasis
,
,
−2
−6
−5
−10
±1
mA
TxOUT[3:0] = 0V, PDB = VDD
VSEL = H, No pre-emphasis
IOZ
TRI-STATE Output Current
Output Termination
PDB = 0V,
TxOUT[3:0] = 0V OR VDD
−15
−15
90
+15
+15
130
µA
µA
Ω
PDB = VDD
,
±1
TxOUT[3:0] = 0V OR VDD
RT
Internal differential output termination
between differential pairs
100
SERIALIZER SUPPLY CURRENT (DVDD, PVDD AND AVDD PINS)(3)
IDDTQ
Serializer (Tx) Total Supply Current
Quad Mode
(includes load current)
f = 85 MHz, CHECKER BOARD pattern
MODE = H, VSEL = H, PRE = OFF
150
150
140
140
200
200
195
195
f = 85 MHz, CHECKER BOARD pattern
MODE = H, VSEL = H, RPRE = 12 kΩ
mA
f = 85 MHz, RANDOM pattern
MODE = H, VSEL = H, PRE = OFF
f = 85 MHz, RANDOM pattern
MODE = H, VSEL = H, RPRE = 12 kΩ
(1) Typical values represent most likely parametric norms at VDD = 3.3V, TA = +25°C, and at the Recommended Operating Conditions at
the time of product characterization and are not verified.
(2) Current into a the device is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH, VTL which are differential voltages.
(3) DIGITAL, PLL, AND ANALOG VDDS
8
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SNLS314D –SEPTEMBER 2009–REVISED APRIL 2013
Electrical Characteristics(1)(2) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
IDDTD
Parameter
Conditions
Min
Typ
Max
Units
Serializer (Tx) Total Supply Current
Dual Mode
f= 50 MHz, CHECKER BOARD pattern
MODE = L, VSEL = H, PRE = OFF
120
145
(includes load current)
f= 50 MHz, CHECKER BOARD pattern
MODE = H, VSEL = H, RPRE = 12 kΩ
120
115
115
2
145
135
135
50
mA
f= 50 MHz, RANDOM pattern
MODE = L, VSEL = H, PRE = OFF
f= 50 MHz, RANDOM pattern
MODE = L, VSEL = H, RPRE = 12 kΩ
IDDTZ
Serializer Supply Current
Power-down
TPWDNB = 0V
(All other LVCMOS Inputs = 0V)
µA
DESERIALIZER LVDS DC SPECIFICATIONS
VTH
VTL
RT
Differential Threshold High Voltage
Differential Threshold Low Voltage
Input Termination
VCM = +1.8V
+50
130
mV
mV
−50
Internal differential output termination
between differential pairs
90
100
Ω
IIN
Input Current
VIN = +2.4V, VDD = 3.6V
±100
±100
±250
±250
µA
µA
VIN = 0V, VDD = 3.6V
DESERIALIZER SUPPLY CURRENT (DVDD, PVDD AND AVDD PINS)(4)
IDDR
Deserializer Total Supply Current
(includes load current)
f = 85 MHz, CL = 8 pF,
CHECKER BOARD pattern, Quad Mode
240
190
145
122
265
210
185
140
mA
f = 85 MHz, CL = 8 pF,
RANDOM pattern, Quad Mode
f = 50 MHz, CL = 8 pF,
CHECKER BOARD pattern, Dual Mode
mA
µA
f = 50 MHz, CL = 8 pF,
RANDOM pattern, Dual Mode
IDDRZ
Deserializer Supply Current Power-down PDB = 0V
(All other LVCMOS Inputs = 0V,
RxIN[3:0](P/N) = 0V)
100
(4) DIGITAL, PLL, AND ANALOG VDDS
Serializer Input Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tCIP
Parameter
TxCLKIN Period
Conditions
MODE = L (Dual Mode)
Min
Typ
tCIP
tCIP
Max
50
Units
20
ns
MODE = H (Quad Mode)
20 MHz – 50 MHz
11.76
25
tCIH
TxCLKIN High Time
0.45 x
tCIP
0.55 x
tCIP
0.5 x tCIP
0.5 x tCIP
0.5 x tCIP
0.5 x tCIP
ns
ns
40 MHz – 85 MHz
0.45 x
tCIP
0.55 x
tCIP
tTCIL
TxCLKIN Low Time
20 MHz – 50 MHz
Figure 7
0.45 x
tCIP
0.55 x
tCIP
40 MHz – 85 MHz
0.45 x
tCIP
0.55 x
tCIP
tCIT
TxCLKIN Transition Time
TxCLKIN Jitter
20 MHz – 50 MHz
Figure 6
0.5
0.5
1.2
ns
40 MHz – 85 MHz
1.2
tJIT
±100
psP-P
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Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tLLHT
tLHLT
tSTC
Parameter
Conditions
Min
Typ
350
350
Max
Units
ps
LVDS Low-to-High Transition Time
LVDS High-to-Low Transition Time
TxIN[31:0] Setup to TxCLKIN
No pre-emphasis
Figure 5
ps
IOVDD = 1.71V to 1.89V
Figure 7
0
ns
ns
IOVDD = 3.135V to 3.465V
IOVDD = 1.71V to 1.89V
IOVDD = 3.135V to 3.465V
Figure 9
0
tHTC
TxIN[31:0] Hold from TxCLKIN
Serializer PLL Lock Time
2.5
2.25
tPLD
tLZD
tHZD
tSD
4400 x
tCIP
5000 x
tCIP
ns
ns
ns
Data Output LOW to TRI-STATE
Delay
See(1)
See(1)
5
5
10
10
Data Output TRI-STATE to HIGH
Delay
Serializer Propagation Delay - Latency f = 50 MHz,
R_FB = H,
PRE = OFF,
MODE = L
Figure 8
4.5 tCIP
6.77
+
f = 50 MHz,
R_FB = L,
PRE = OFF,
MODE = L
4.5 tCIP
5.63
+
+
4.5 tCIP
7.09
+
+
+
+
+
4.5 tCIP
9.29
+
f = 20 MHz,
R_FB = H,
PRE = OFF,
MODE = L
4.5 tCIP
6.57
4.5 tCIP
8.74
4.5 tCIP
10.74
+
ns
f = 85MHz,
R_FB = H,
PRE = OFF,
MODE = H
9.0 tCIP
6.99
f = 85MHz,
R_FB = L,
PRE = OFF,
MODE = H
9.0 tCIP
5.97
+
+
9.0 tCIP
7.38
9.0 tCIP
9.64
+
f = 40 MHz,
R_FB = HL,
PRE = OFF,
MODE = H
9.0 tCIP
6.30
9.0 tCIP
8.26
9.0 tCIP
10.49
+
tLVSKD
LVDS Output Skew
LVDS differential output channel-to-
channel skew
30
500
ps
ΛSTXBW
Jitter Transfer Function -3 dB
Bandwidth
Dual Mode
f = 50 MHz
Figure 15
2.8
MHz
dB
Quad Mode
f = 85 MHz
2
δSTX
Serializer Jitter Transfer Function
Peaking
Dual Mode
f = 50 MHz
0.3
0.9
Quad Mode
f = 85 MHz
(1) When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
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Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tROCP
Parameter
Conditions
Min
Typ
Max
Units
Receiver Output Clock Period
tROCP = tCIP
(Dual Mode)
Figure 11
20
tROCP
50
ns
tROCP = tCIP
(Quad Mode)
11.76
45
tROCP
50
25
55
tRODC
tROTR
RxCLKOUT Duty Cycle
%
LVCMOS Low-to-High Transition
Time
CL = 8pF (lumped load)
(Dual Mode)
3.2
ns
Figure 10
tROTF
tROTR
tROTF
tROSC
tROHC
tROSC
tROHC
tHZR
LVCMOS High-to-Low Transition
Time
3.5
2.4
1.9
ns
ns
LVCMOS Low-to-High Transition
Time
CL = 8pF (lumped load)
(Quad Mode)
LVCMOS High-to-Low Transition
Time
ns
RxOUT[31:0] Setup to RxCLKOUT
RxOUT[31:0] Hold to RxCLKOUT
RxOUT[31:0] Setup to RxCLKOUT
RxOUT[31:0] Hold to RxCLKOUT
f = 50 MHz
(Dual Mode)
0.5 x
tROCP
5.6
7.4
3.4
3.4
ns
ns
ns
ns
ns
ns
ns
0.5 x
tROCP
f = 85 MHz
(Quad Mode)
0.5 x
tROCP
0.5 x
tROCP
Data Output High to TRI-STATE
Delay
Figure 13
5
5
5
10
10
10
10
tLZR
Data Output Low to TRI-STATE
Delay
tZHR
Data Output TRI-STATE to High
Delay
tZLR
Data Output TRI-STATE to Low
Delay
5
ns
ns
tRD
Deserializer Propagation Delay –
Latency
f = 20 MHz
(Dual Mode)
Figure 12
5.5 x
tROCP
3.35
+
5.5 x
tROCP
6.00
ns
ns
ns
f = 50 MHz
(Dual Mode)
+
12.0 x
f = 40 MHz
(Quad Mode)
tROCP
7.4
+
12.0 x
f = 85 MHz
(Quad Mode)
tROCP
5.7
+
(1)
tRPLLS
Deserializer PLL Lock Time
20 MHz – 50 MHz
(Dual Mode)
Figure 13
128k x
tROCP
ns
ns
40 MHz – 85 MHz
(Quad Mode)
Figure 13
256k x
tROCP
TOLJIT
tLVSKR
Deserializer Input Jitter Tolerance
0.25
UI
ns
LVDS Differential Input Skew
Tolerance
20 MHz – 85 MHz
Figure 17
0.4 x
tROCP
(1) tRPLLS is the time required by the Deserializer to obtain lock when exiting power-down mode.
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AC Timing Diagrams and Test Circuits
80%
20%
80%
Differential
Signal
Vdiff = 0V
20%
t
t
LHLT
LLHT
Figure 5. Serializer LVDS Transition Times
VDDIO
80%
80%
TxCLKIN
20%
20%
0V
t
t
CIT
CIT
Figure 6. Serializer Input Clock Transition Time
t
CIP
TxCLKIN
t
+ t
CIH
CIL
t
t
HTC
STC
TxIN
Setup
Hold
Figure 7. Serializer Setup/Hold and High/Low Times
SYMBOL N-1
SYMBOL N
SYMBOL N+1
SYMBOL N
+2
TxIN
SYMBOL N+3
TxCLKIN
t
SD
-
3
SYMBOL N-
SYMBOL N 2
SYMBOL N-1
SYMBOL N
SYMBOL N +1
TxOUT
Figure 8. Serializer Propagation Delay
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PDB
TxCLKIN
TxOUT
2.0V
0.8V
t
or
HZD
t
LZD
t
PLD
TRI-STATE
LVDS Output HIGH
LVDS Output Active
TRI-STATE
Figure 9. Serializer PLL Lock Time
V
V
OH
80%
80%
20%
20%
OL
t
t
ROTF
ROTR
Figure 10. Deserializer LVCMOS Output Transition Time
t
ROCP
t
t
t
RODC
RODC
ROHC
RxCLKOUT
V
DD
/2
V
DD
/2
t
ROSC
DataValid
Before
RxCLKOUT RxCLKOUT
DataValid
After
RxOUT [31:0]
V
DD
/2
V
DD
/2
Figure 11. Deserializer Setup and Hold times
-
SYMBOL N
1
SYMBOL N
SYMBOL N+1
SYMBOL N + 2
SYMBOL N +3
RxIN
t
RD
RxCLKOUT
RxOUT
SYMBOL N -3
SYMBOL N - 2
SYMBOL N -1
SYMBOL N
SYMBOL N +1
Figure 12. Deserializer Propagation Delay
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2.0V
PDB
0.8V
t
RPLLS
Don‘t Care
RxIN [1:0]+/-
LOCK
TRI-STATE
TRI-STATE
TRI-STATE
t
or t
LZR
HZR
TRI-STATE
TRI-STATE
RxOUT [31:0]
RxCLKOUT
REN
Figure 13. Deserializer PLL Lock Time and PDB TRI-STATE Delay
500W
V
V
= V /2 for t
DD
or t
LZR
REF
ZLR
or t
V
REF
+
-
= 0V for t
C
L
= 8 pF
REF
ZHR
HZR
REN
VOH
V
/2
DD
V /2
DD
REN
VOL
t
t
ZLR
LZR
VOL + 0.5V
VOH + 0.5V
VOL + 0.5V
VOH - 0.5V
VOL
VOH
t
t
ZHR
HZR
RxOUT [31:0]
Note: C includes instrumentation and fixture capacitance within 6 cm of RxOUT [31:0].
L
Figure 14. Deserializer TRI_STATE Test Circuit and Timing
0
Dual Mode 50 MHz
-3
Quad Mode 85 MHz
-6
-9
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07
FREQUENCY (Hz)
Figure 15. Serializer Jitter Transfer
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TxOUT[3:0]+
32
TxIN
R
T
R
L
TxOUT[3:0]-
TxCLKIN
Figure 16. Serializer VOD Test Circuit Diagram
t
LVSKR
RxIN0
(Master)
RxIN1
RxIN2
RxIN3
1 RxCLKOUT Cycle
RxCLKOUT
Figure 17. LVDS Deserializer Input Skew
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FUNCTIONAL DESCRIPTION
The DS92LV3241 Serializer (SER) and DS92LV3242 Deserializer (DES) chipset is a flexible SER/DES chipset
that translates a 32-bit parallel LVCMOS data bus into a quad (4 pairs) or dual (2 pairs) LVDS serial links with
embedded clock. The DS92LV3241 serializes the 32-bit wide parallel LVCMOS word into four or two high-speed
LVDS serial data streams with embedded clock, scrambles and DC Balances the data to support AC coupling
and enhance signal quality. The DS92LV3242 receives the dual/quad LVDS serial data streams and converts it
back into a 32-bit wide parallel data with a recovered clock. The dual/quad LVDS serial data stream reduces
cable size, the number of connectors, and eases skew concerns.
Parallel clocks between 20 MHz to 85 MHz are supported by the dual or quad operating modes. The modes are
user selectable through a control pin on Serializer. In dual mode, the transmit clock frequency supports 20 MHz
to 50 MHz and in quad mode the transmit clock frequency supports 40 MHz to 85 MHz. In the dual mode
configuration, the embedded clock LVDS serial streams have an effective data payload of 640 Mbps (20MHz x
32-bit) to 1.6 Gbps (50MHz x 32- bit). In the quad mode configuration, the embedded clock LVDS serial streams
have an effective data payload of 1.28 Gbps (40MHz x 32-bit) to 2.72 Gbps (85MHz x 32-bit). The SER/DES
chipset is designed to transmit data over long distances through standard twisted pair (TWP) cables. The
differential inputs and outputs are internally terminated with 100 ohm resistors to provide source and load
termination, minimize stub length, to reduce component count and further minimize board space.
The DES can attain lock to a data stream without the use of a separate reference clock source; greatly
simplifying system complexity and reducing overall cost. The DES synchronizes to the SER regardless of data
pattern, delivering true automatic “plug-and-lock” performance. It will lock to the incoming serial stream without
the need of special training patterns or special sync characters. The DES recovers the clock and data by
extracting the embedded clock information, deskews the serial data channels and then deserializes the data. The
DES also monitors the incoming clock information, determines lock status, and asserts the LOCK output high
when lock occurs. In addition the DES also supports an optional AT-SPEED BIST (Built In Self Test) mode, BIST
error flag, and LOCK status reporting pin. The SER and the DES have a power down control signal to enable
efficient operation in various applications.
DESKEW AND CHANNEL ALIGNMENT
The DES automatically detects dual or quad serial channel mode and provides a clock alignment and deskew
function without the need for any special training patterns. During the locking phase, the embedded clock
information is recovered on all channels and the serial links are internally synchronized, de-skewed, and auto
aligned. The internal CDR circuitry will dynamically compensate for up to 0.4 times the parallel clock period of
per channel phase skew (channel-to-channel) between the recovered clocks of the serial links. This provides
skew phase tolerance from mismatches in interconnect wires such as PCB trace routing, cable pair-to-pair length
differences, and connector imbalances.
DATA TRANSFER
After SER lock is established (SER PLL to TxCLKIN), the inputs TxIN0–TxIN31 are latched into the encoder
block. Data is clocked into the SER by the TxCLKIN input. The edge of TxCLKIN used to strobe the data is
selectable via the R_FB (SER) pin. R_FB (SER) high selects the rising edge for clocking data and low selects
the falling edge. The SER outputs (TxOUT[3:0]+/-) are intended to drive a AC Coupled point-to-point
connections.
The SER latches 32-bit parallel data bus and performs several operations to it. The 32-bit parallel data is
internally encoded and sequentially transmitted over the two high-speed serial LVDS channels. For each serial
channel, the SER transmits 20 bits of information per payload to the DES. In the dual mode, the 32-bit parallel
data is scaled and bit-mapped across two 20-bit data payloads per channel, resulting in a per channel throughput
of 400 Mbps to 1.0 Gbps (20 bits x clock rate). Under quad mode, the internal PLL operates at ½ the input clock
frequency rate. The 32 bits are bit-mapped and sequenced per every 2 cycles at ½ the TxCLKIN frequency
across four channels, resutling in a per channel throughput of 400 Mbps to 850 Mbps (20 bits x clock rate/2). The
chipset supports frequency ranges of 20 MHz to 85 MHz.
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When all of the DES channels obtain lock , the LOCK pin is driven high and synchronously delivers valid data
and recovered clock on the output. The DES locks to the clock, uses it to generate multiple internal data strobes,
and then drives the recovered clock to the RxCLKOUT pin. The recovered clock (RxCLKOUT) is synchronous to
the data on the RxOUT[31:0] pins. While LOCK is high, data on RxOUT[31:0] is valid. Otherwise, RxOUT[31:0] is
invalid. The polarity of the RxCLKOUT edge is controlled by its R_FB (DES) input. RxOUT[31:0], LOCK and
RxCLKOUT outputs will each drive a maximum of 8 pF load. REN controls TRI-STATE for RxOUT0–RxOUT31
and the RxCLKOUT pin on the DES.
RESYNCHRONIZATION
In the absence of data transitions on one of the channels into the DES (e.g. a loss of the link), it will automatically
try to resynchronize and re-establish lock using the standard lock sequence on the master channel (Channel 0).
For example, if the embedded clock is not detected one time in succession on any of the serial links, the LOCK
pin is driven low. The DES then monitors the master channel for lock, once that is obtained, the second channel
is locked and aligned. The logic state of the LOCK signal indicates whether the data on RxOUT is valid; when it
is high, the data is valid. The system may monitor the LOCK pin to determine whether data on the RxOUT is
valid.
POWERDOWN
The Powerdown state is a low power sleep mode that the SER and DES may use to reduce power when no data
is being transferred. The respective PDB pins are used to set each device into power down mode, which reduces
supply current into the µA range. The SER enters Powerdown when the SER PDB pin is driven low. In
Powerdown, the PLL stops and the outputs go into TRI-STATE, disabling load current and reducing current
supply. To exit Powerdown, SER PDB must be driven high. When the SER exits Powerdown, its PLL must lock
to TxCLKIN before it is ready for sending data to the DES. The system must then allow time for the DES to lock
before data can be recovered.
The DES enters Powerdown mode when DES PDB is driven low. In Powerdown mode, the PLL’s stop and the
outputs enter TRI-STATE. To bring the DES block out of the Powerdown state, the system drives DES PDB high.
Both the SER and DES must relock before data can be transferred from Host and received by the Target. The
DES will startup and assert LOCK high when it is locked to the embedded clocks. See also Figure 13.
TRI-STATE
For the SER, TRI-STATE is entered when the SER PDB pin is driven low. This will TRI-STATE the driver output
pins on TxOUT[3:0]+/-. In addition, when MODE=0 (dual mode), the TxOUT[3:2]+/- outputs pins are in TRI-
STATE.
When you drive the REN or DES PDB pin low, the DES output pins (RxOUT[31:0]) and RxCLKOUT will enter
TRI-STATE. The LOCK output remains active, reflecting the state of the PLL. The DES input pins are high
impedance during receiver Powerdown (DES PDB low) and power-off (VDD = 0V). See also Figure 13.
TRANSMIT PARALLEL DATA AND CONTROL INPUTS
The DS92LV3241 operates on a core supply voltage of 3.3V with an optional digital supply voltage for 1.8V, low-
swing, input support. The SER single-ended (32-bit parallel data and control inputs) pins are 1.8V and 3.3V
LVCMOS logic level compatible and is configured through the IOVDD input supply rail. If 1.8V is required, the
IOVDD pin must be connected to a 1.8V supply rail. Also when power is applied to the transmitter, IOVDD pin
must be applied before or simultaneously with other power supply pins (3.3V). If 1.8V input swing is not required,
this pin should be tied to the common 3.3V rail. During normal operation, the voltage level on the IOVDD pins
must not change.
PRE-EMPHASIS
The SER LVDS Line Driver features a Pre-Emphasis function used to compensate for extra long or lossy
transmission media. The same amount of Pre-Emphasis is applied on all of the enabled differential output
channels. Cable drive is enhanced with a user selectable Pre-Emphasis feature that provides additional output
current during transitions to counteract cable loading effects. The transmission distance will be limited by the loss
characteristics and quality of the media.
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To enable the Pre-Emphasis function, the “PRE” pin requires one external resistor (Rpre) to VSS (GND) in order
to set the pre-emphasized current level. Options include:
1. Normal Output (no Pre-emphasis) – Leave the PRE pin open, include an R pad, do not populate.
2. Enhanced Output (Pre-emphasis enabled) – connect a resistor on the PRE pin to Vss.
Values of the Rpre Resistor should be between 12K Ohm and 100K Ohm. Values less than 6K Ohm should not
be used. The amount of Pre-Emphasis for a given media will depend on the transmission distance and Fmax of
the application. In general, too much Pre-Emphasis can cause over or undershoot at the receiver input pins. This
can result in excessive noise, crosstalk, reduced Fmax, and increased power dissipation. For shorter cables or
distances, Pre-Emphasis is typically not be required. Signal quality measurements should be made at the end of
the application cable to confirm the proper amount of Pre-Emphasis for the specific application.
The Pre-Emphasis circuit increases the drive current to I = 48 / (RPRE). For example if RPRE = 15 kOhms, then
the current is increased by an additional 3.2 mA. To calculate the expected increase in VOD, multiply the increase
in current by 50 ohms. So for the case of RPRE = 15 kOhms, the boost to VOD would be 3.2 mA x 50 Ohms = 160
mV. The duration of the current is controlled to one bit by time. If more than one bit value is repeated in the next
cycle(s), the Pre-Emphasis current is turned off (back to the normal output current level) for the next bit(s). To
boost high frequency data and pre-equalize teh data patternreduce ISI (Inter-Symbol Interference) improving the
resulting eye pattern.
VOD SELECT
The SER Line Driver Differential Output Voltage (VOD) magnitude is selectable. Two levels are provided and are
selected by the VSEL pin. When this pin is LOW, normal output levels are obtained. For most application set the
VSEL pin LOW. When this pin is HIGH, the output current is increased to double the VOD level. Use this setting
only for extra long cables or high-loss interconnects.
Table 1. VOD Control
VSEL Pin Setting
LOW
Effect
Small VOD, typ 440 mVP-P
Large VOD, typ 850 mVP-P
HIGH
SERIAL INTERFACE
The serial links between the DS92LV3241 and the DS92LV3242 are intended for a balanced 100 Ohm
interconnects. The links must be configured as an AC coupled interface.
The SER and DES support AC-coupled interconnects through an integrated DC balanced encoding/decoding
scheme. An external AC coupling capacitors must be placed, in series, in the LVDS signal path. The DES input
stage is designed for AC-coupling by providing a built-in AC bias network which sets the internal common mode
voltage (VCM) to +1.8V.
For the high-speed LVDS transmission, small footprint packages should be used for the AC coupling capacitors.
This will help minimize degradation of signal quality due to package parasitics. NPO class 1 or X7R class 2 type
capacitors are recommended. 50 WVDC should be the minimum used for best system-level ESD performance.
The most common used capacitor value for the interface is 100 nF (0.1 uF) capacitor. One set of capacitors may
be used for isolation. Two sets (both ends) may also be used for maximum isolation of both the SER and DES
from cable faults.
The DS92LV3241 and the DS92LV3242 differential I/O’s are internally terminated with 100 Ohm resistance
between the inverting and non-inverting pins and do not require external termination. The internal resistance
value will be between 90 ohm and 130 ohm. The integrated terminations improve signal integrity, reduce stub
lengths, and decrease the external component count resulting in space savings.
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AT-SPEED BIST FEATURE
The DS92LV3241/ DS92LV3242 serial link is equipped with built-in self-test (BIST) capability to support both
system manufacturing and field diagnostics. BIST mode is intended to check the entire high-speed serial
interface at full link-speed without the use of specialized and expensive test equipment. This feature provides a
simple method for a system host to perform diagnostic testing of both SER and DES. The BIST function is easily
configured through the SER BISTEN pin. When the BIST mode is activated, the SER generates a PRBS
(pseudo-random bit sequence) pattern (2^7-1). This pattern traverses each lane to the DES input. The
DS92LV3242 includes an on-chip PRBS pattern verification circuit that checks the data pattern for bit errors and
reports any errors on the data output pins of the DES.
The AT-Speed BIST feature is enabled by setting the BISTEN to High on SER. The BISTEN input must be High
or Low for 4 or more TxCLKIN clock cycles in order to activate or deactivate the BIST mode. An input clock
signal for the Serializer TxCLKIN must also be applied during the entire BIST operation. Once BIST is enabled,
all the Serializer data inputs (TxIN[31:0]) are ignored and the DES outputs (RxOUT[31:0]) are not available. Next,
the internal test pattern generator for each channel starts transmission of the BIST pattern from SER to DES.
The DES BIST mode will be automatically activated by this sequence. A maximum of 128 consecutives clock
symbols on DS92LV3242 DES is needed to detect BIST enable function. The BIST is implemented with
independent transmit and receive paths for the four serial links. Each channel on the DES will be individually
compared against the expected bit sequence of the BIST pattern.
TxCLKIN
PDB (High)
2.0V
BISTEN
0.8V
BIST disabled
BIST enabled
BIST disabled
4 x tCIP
4 x tCIP
Figure 18. BIST Test Enabled/Disabled
Under the BIST mode, the DES parallel outputs on RxOUT[31:0] are multiplexed to represent BIST status
indicators. The pass/fail status of the BIST is represented by a Pass flag along with an Error counter. The Pass
flag output is designated on DES RxOUT0 for Channel 0, and RxOUT8 for Channel 1. The DES's PLL must first
be locked to ensure the Pass status is valid. The output Pass status pin will stay LOW and then transition to High
once 44*10^6 symbols are achieved across each of the respective transmission links. The total time duration of
the test is defined by the following: 44*10^6 x tCIP . After the Pass output flags reach a HIGH state, it will not
drop to LOW even if subsequent bit errors occurred after the BIST duration period. Errors will be reported if the
input test pattern comparison does not match. If an error (miss-compare) occurs, the status bit is latched on
RxOUT[7:1] for Channel 0, and RxOUT[15:9] for Channel 1; reflecting the number of errors detected. Whenever
a data bit contains an error, the Error counter bit output for that corresponding channel goes HIGH. Each counter
for the serial link utilizes a 7-bit counter to store the number of errors detected (0 to 127 max).
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Recovered Pixel Clock
BISTEN
Case 1: No bit errors
Recovered Pixel Data
Channel 0 - RxOUT0
Channel 1 - RxOUT8
Channel 2 œ RxOUT16
Channel 3 œ RxOUT24
BIST PASS
Error counter
Channel 0 - RxOUT[7:1]
Channel 1 - RxOUT[15:9]
Channel 2 - RxOUT[23:17]
Channel 3 - RxOUT[31:25]
0
0
0
Case 2: Bit error(s)
Recovered Pixel Data
B
B B
B
Channel 0 - RxOUT0
Channel 1 - RxOUT8
Channel 2 œ RxOUT16
Channel 3 œ RxOUT24
BIST FAIL
Error counter
Channel 0 - RxOUT[7:1]
Channel 1 - RxOUT[15:9]
Channel 2 - RxOUT[23:17]
Channel 3 - RxOUT[31:25]
0
1
2
3
4
4
Case 3: Bit error(s)
Recovered Pixel Data
B
Channel 0 - RxOUT0
Channel 1 - RxOUT8
Channel 2 œ RxOUT16
Channel 3 œ RxOUT24
Error counter
BIST PASS
Channel 0 - RxOUT[7:1]
Channel 1 - RxOUT[15:9]
Channel 2 - RxOUT[23:17]
Channel 3 - RxOUT[31:25]
0
0
0
BIST Duration
44 x 106 x tCIP
Status
Region
B = Bad Bit
Figure 19. BIST Diagram for Different Bit Error Cases
TYPICAL APPLICATION CONNECTION
Figure 20 shows a typical application of the DS92LV3241 Serializer (SER). The differential outputs utilize 100nF
coupling capacitors to the serial lines. Bypass capacitors are placed near the power supply pins. A system GPO
(General Purpose Output) controls the PDB and BISTEN pins. In this application the R_FB (SER) pin is tied Low
to latch data on the falling edge of the TxCLKIN. In this application the link is short, therefore the VSEL pin is tied
LOW for the standard output swing level. The Pre-emphasis input utilizes a resistor to ground to set the amount
of pre-emphasis desired by the application.
Configuration pins for the typical application are shown for SER:
•
•
•
•
•
•
PDB – Power Down Control Input – Connect to host or tie HIGH (always ON)
BISTEN – Mode Input - tie LOW if BIST mode is not used, or connect to host
VSEL – tie LOW for normal VOD magnitude (application dependant)
MODE – For clock rates between 20 MHz and 50 MHz tie LOW, for 40 MHz to 85 MHz tie HIGH
PRE – Leave open if not required (have a R pad option on PCB)
RSVD1 & RSVD2 – tie LOW
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There are eight power pins for the device. These may be bussed together on a common 3.3V plane (3.3V
LVCMOS I/O interface). If 1.8V input swing level for parallel data and control pins are required, connect the
IOVDD pin to 1.8V. At a minimum, eight 0.1uF capacitors should be used for local bypassing.
3.3V
3.3V
VDDA
VDD
VDD
VDD
VDD
3.3V
VDDPLL
VDDPLL
IOVDD
1.8V or 3.3V
TxCLKIN
VSS
VSS
VSS
VSS
TxIN31
TxIN30
TxIN29
TxIN28
TxIN27
TxIN26
TxIN25
TxIN24
TxIN23
TxIN22
TxIN21
TxIN20
TxIN19
TxIN18
TxIN17
TxIN16
TxIN15
TxIN14
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
VSSPLL
VSSPLL
VSSA
IOVSS
TxOUT0+
TxOUT0-
TxOUT1+
TxOUT1-
TxOUT2+
TxOUT2-
TxOUT3+
TxOUT3-
TxIN8
TxIN7
TxIN6
TxIN5
PRE
TxIN4
opt.
TxIN3
TxIN2
TxIN1
R_FB
VSEL
TxIN0
PDB
BISTEN
MODE
RSVD
Notes:
Caps are 0.1 mF
except Bulk Supply (4.7 mF)
Figure 20. DS92LV3241 Typical Connection Diagram
Figure 21 shows a typical application of the DS92LV3242 Deserializer (DES). The differential inputs utilize 100nF
coupling capacitors in the serial lines. Bypass capacitors are placed near the power supply pins. A system GPO
(General Purpose Output) controls the PDB pin. In this application the R_FB (DES) pin is tied Low to strobe the
data on the falling edge of the RxCLKOUT. The REN signal is not used and is tied High also.
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Configuration pins for the typical application are shown for DES:
•
•
•
PDB – Power Down Control Input – Connect to host or tie HIGH
REN – tie HIGH if not used (used to MUX two DES to one target device)
RSVD – tie LOW
3.3V
3.3V
VDDA
VDD
VDD
3.3V
VDDPLL
VDDPLL
VDDPLL
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
RxCLKOUT
RxOUT31
RxOUT30
RxOUT29
RxOUT28
RxOUT27
RxOUT26
RxOUT25
RxOUT24
RxOUT23
RxOUT22
RxOUT21
RxOUT20
RxOUT19
RxOUT18
RxOUT17
RxOUT16
RxOUT15
RxOUT14
RxOUT13
RxOUT12
RxOUT11
RxOUT10
RxOUT9
RxOUT8
RxOUT7
RxOUT6
RxOUT5
RxOUT4
RxOUT3
RxOUT2
RxOUT1
RxOUT0
VSSPLL
VSSPLL
VSSPLL
VSSA
RxIN0+
RxIN0-
RxIN1+
RxIN1-
RxIN2+
RxIN2-
RxIN3+
RxIN3-
Tied ON
REN
R_FB
RSVD
PDB
LOCK
Notes:
Caps are 0.1 mF
except Bulk Supply (4.7 mF)
Figure 21. DS92LV3242 Typical Connection Diagram
22
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SNLS314D –SEPTEMBER 2009–REVISED APRIL 2013
Applications Information
TRANSMISSION MEDIA
The SER and DES are used in AC-coupled point-to-point configurations, through a PCB trace, or through twisted
pair cables. Interconnect for LVDS typically has a differential impedance of 100 Ohms. Use cables and
connectors that have matched differential impedance to minimize impedance discontinuities. In most applications
that involve cables, the transmission distance will be determined on data rates involved, acceptable bit error rate
and transmission medium.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS SER/DES devices should be designed to provide low-noise
power feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs
to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommended at the point of
power entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with vias on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz range. To provide effective bypassing,
multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of
interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS
lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100
Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled
noise will appear as common mode and thus is rejected by the receivers. The tightly coupled lines will also
radiate less.
PLUG AND GO
The Serializer and Deserializer devices support hot plugging of the serial interconnect. The automatic receiver
lock to random data “plug & go” capability allows the DS92LV3242 to obtain lock to the active data stream during
a live insertion event.
LVDS INTERCONNECT GUIDELINES
For full details, see the Channel-Link PCB and Interconnect Design-In Guidelines (literature number SNLA008)
and the Transmission Line RAPIDESIGNER Operation and Applications Guide (literature number SNLA035).
•
•
Use 100 Ohm coupled differential pairs
Use the S/2S/3S rule in spacings
–
–
S = space between the pair
2S = space between pairs
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www.ti.com
–
3S = space to LVCMOS signal
•
•
•
•
•
Minimize the number of vias
Use differential connectors when operating above 500 Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual (literature number SNLA187), which is
available in PDF format from the TI LVDS & CML Solutions web site.
Typical Performance Characteristics
The waveforms below illustrate the typical performance of the DS92LV3241. The SER was given a PCLK and configured as
described below each picture. In all of the pictures the SER was configured with BISTEN pin set to logic HIGH. Each
waveform was taken by using a high impedance low capacitance differential probe to probe across a 100 ohm differential
termination resistor within one inch of TxOUT0+/-.
Figure 22. Serial Output Quad Mode, 85 MHz, VSEL = H, No
Pre-Emphasis
Figure 23. Serial Output Quad Mode, 85 MHz, VSEL = L, No
Pre-Emphasis
Figure 24. Serial Output Dual Mode, 50 MHz, VSEL = H, No
Pre-Emphasis
Figure 25. Serial Output Dual Mode, 50 MHz, VSEL = L, No
Pre-Emphasis
24
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SNLS314D –SEPTEMBER 2009–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 24
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
DS92LV3241TVS/NOPB
DS92LV3241TVSX/NOPB
DS92LV3242TVS/NOPB
DS92LV3242TVSX/NOPB
ACTIVE
TQFP
TQFP
TQFP
TQFP
PAG
64
64
64
64
160
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
CU SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
DS92LV3241
TVS
ACTIVE
ACTIVE
ACTIVE
PAG
PAG
PAG
1000
160
Green (RoHS
& no Sb/Br)
-40 to 85
DS92LV3241
TVS
Green (RoHS
& no Sb/Br)
-40 to 85
DS92LV3242
TVS
1000
Green (RoHS
& no Sb/Br)
-40 to 85
DS92LV3242
TVS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Nov-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS92LV3241TVSX/NOPB TQFP
DS92LV3242TVSX/NOPB TQFP
PAG
PAG
64
64
1000
1000
330.0
330.0
24.4
24.4
13.0
13.0
13.0
13.0
1.45
1.45
16.0
16.0
24.0
24.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS92LV3241TVSX/NOPB
DS92LV3242TVSX/NOPB
TQFP
TQFP
PAG
PAG
64
64
1000
1000
367.0
367.0
367.0
367.0
45.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
M
0,08
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
11,80
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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