DS92LX2121SQX/NOPB [TI]
10MHz 至 50MHz 直流平衡 Channel Link III 双向控制串行器 | RTA | 40 | -40 to 85;
| 型号： | DS92LX2121SQX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10MHz 至 50MHz 直流平衡 Channel Link III 双向控制串行器 | RTA | 40 | -40 to 85 驱动 线路驱动器或接收器 驱动程序和接口 |
| 文件： | 总42页 (文件大小：1125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS92LX2121, DS92LX2122
www.ti.com
SNLS330I –MAY 2010–REVISED APRIL 2013
DS92LX2121/DS92LX2122 10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control
Serializer and Deserializer
Check for Samples: DS92LX2121, DS92LX2122
1
FEATURES
APPLICATIONS
2
•
General
•
•
Industrial Displays, Touch Screens
Medical Imaging
–
–
–
Up to 1050 Mbits/sec Data Throughput
10 MHz to 50 MHz Input Clock Support
DESCRIPTION
The DS92LX2121/DS92LX2122 chipset offers
Supports 18-bit Color Depth (RGB666 + HS,
VS, DE)
a
Channel Link III interface with a high-speed forward
channel and a full-duplex control channel for data
transmission over a single differential pair. The
DS92LX2121/DS92LX2122 incorporates differential
signaling on both the high-speed and bi-directional
back channel control data paths. The Serializer/
Deserializer pair is targeted for direct connections
between graphics host controller and displays
modules. This chipset is ideally suited for driving
video data to displays requiring 18-bit color depth
(RGB666 + HS, VS, and DE) along with a bi-
directional back channel control bus. The primary
transport converts 21 bit data over a single high-
speed serial stream, along with a separate low
latency bi-directional back channel transport that
accepts control information from an I2C port. Using
TI’s embedded clock technology allows transparent
full-duplex communication over a single differential
pair, carrying asymmetrical bi-directional back
channel control information in both directions. This
single serial stream simplifies transferring a wide data
bus over PCB traces and cable by eliminating the
skew problems between parallel data and clock
paths. This significantly saves system cost by
narrowing data paths that in turn cable width,
connector size and pins.
–
–
–
–
Embedded Clock with DC Balanced Coding
to Support AC-Coupled Interconnects
Capable to Drive up to 10 Meters Shielded
Twisted-Pair
Bi-Directional Control Interface Channel
with I2C Support
I2C Interface for Device Configuration.
Single-Pin ID Addressing
–
–
Up to 4 GPI on DES and GPO on SER
AT-SPEED BIST Diagnosis Feature to
Validate Link Integrity
–
–
Individual Power-Down Controls for both
SER and DES
User-Selectable Clock Edge for Parallel
Data on both SER and DES
–
–
Integrated Termination Resistors
1.8V- or 3.3V-Compatible Parallel Bus
Interface
–
–
–
Single Power Supply at 1.8V
IEC 61000–4–2 ESD Compliant
Temperature Range −40°C to +85°C
•
DESERIALIZER — DS92LX2122
In addition, the Deserializer provides input
equalization to compensate for loss from the media
over longer distances. Internal DC balanced
encoding/decoding is used to support AC-Coupled
interconnects.
–
No Reference Clock Required on
Deserializer
–
–
–
Programmable Receive Equalization
LOCK Output Reporting Pin to Ensure
EMI/EMC Mitigation
A sleep function provides a power-savings mode
when the high speed forward channel and embedded
bi-directional control channel are not needed.
–
–
–
Programmable Spread Spectrum (SSCG)
Outputs
The Serializer is offered in a 40-pin lead in WQFN
and Deserializer is offered in a 48-pin WQFN
packages.
Receiver Output Drive Strength Control
(RDS)
Receiver Staggered Outputs
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
DS92LX2121, DS92LX2122
SNLS330I –MAY 2010–REVISED APRIL 2013
www.ti.com
Typical Application Diagram
Parallel
Data Out
18+3
Parallel
Data In
18+3
Channel Link III
Graphics
Controller,
Camera
Display
Module, Frame
Grabber
4
4
DS92LX2121
DS92LX2122
GPO
GPI
Back Channel
2
2
Serial
Serial
Control Bus
Control Bus
Serializer
Deserializer
Block Diagrams
R
R
T
R
T
R
T
DOUT+
RIN+
T
21
Data [17:0],
Control [2:0]
21
Data [17:0],
Control [2:0]
4
4
GPI[3:0]
GPO[3:0]
DOUT-
RIN-
PCLK
LOCK
PASS
Clock
Gen
PCLK
PLL
Clock
Gen
CDR
Timing
and
Control
PDB
M/S
PDB
Timing
and
Control
BISTEN
M/S
SDA
SCL
SDA
SCL
CAD
CAD
DS92LX2121 - SERIALIZER
DS92LX2122 - DESERIALIZER
Figure 1. Block Diagram
DS92LX2121
Serializer
DS92LX2122
Deserializer
Channel Link III
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
Timing
Controller
--
Display
--
Graphics
Controller
---
Video
Processor
--
PCLK
PLL
PCLK
Frame Grabber
PDB
M/S
Camera
PDB
M/S
Config.
BISTEN
GPI[3:0]
Config.
GPO[3:0]
mC
2
SDA
SCL
SDA
SCL
2
I C
mC
I C
Figure 2. Application Block Diagram
2
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Product Folder Links: DS92LX2121 DS92LX2122
DS92LX2121, DS92LX2122
www.ti.com
SNLS330I –MAY 2010–REVISED APRIL 2013
DS92LX2121 Pin Diagram
Top View
31
32
33
34
35
36
37
38
39
40
20 GPO[1]
19 GPO[0]
18
V
DDIO
DIN[8]
DIN[9]
DAP = GND
V
DDCML
17 DOUT+
16 DOUT-
V
DDD
DIN[10]
DIN[11]
DS92LX2121
(Top View)
15
14
V
V
DDT
DIN[12]
DIN[13]
DIN[14]
DIN[15]
DDPLL
13 PDB
12 M/S
11 RES
Figure 3. Serializer - DS92LX2121
40-Pin WQFN (RTA Package)
DS92LX2121 Serializer PIN DESCRIPTIONS
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
DIN[20:0]
PCLK
5, 4, 3, 2, 1, 40,
39, 38, 37, 36,
35, 33, 32, 30,
29, 28, 27, 26,
25, 24, 23
Inputs, LVCMOS w/ Parallel data inputs.
pull down
6
Input, LVCMOS w/
pull down
Pixel Clock Input Pin. Strobe edge set by TRFB configuration.
GENERAL PURPOSE OUTPUT (GPO)
GPO[3:0] 22, 21, 20, 19 Output, LVCMOS
General-purpose pins individually configured as outputs; which are used to
control and respond to various commands.
SERIAL CONTROL BUS - I2C COMPATIBLE
Input/Output, Open Clock line for the serial control bus communication
Drain SCL requires an external pull-up resistor to VDDIO
SCL
SDA
7
8
.
Input/Output, Open Data line for the serial control bus communication
Drain
SDA requires an external pull-up resistor to VDDIO
.
I2C Mode Select
M/S = L, Master mode (default); device generates and drives the SCL clock
line. Device is connected to a slave peripheral on the bus. (Serializer initially
starts up in Standby mode and is enabled through remote wakeup by the
Deserializer)
Input, LVCMOS w/
pull down
M/S
12
9
M/S = H, Slave; device accepts SCL clock input
Continuous Address Decoder
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID
address (see Serial Control Bus Connection).
CAD
Input, analog
Copyright © 2010–2013, Texas Instruments Incorporated
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SNLS330I –MAY 2010–REVISED APRIL 2013
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DS92LX2121 Serializer PIN DESCRIPTIONS (continued)
Pin Name
Pin No.
I/O, Type
Description
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB = H, Transmitter is enabled and is ON.
PDB = L, Transmitter is in Sleep (Power Down). When the transmitter is in the
SLEEP state, the PLL is shutdown, and IDD is minimized.
Input, LVCMOS w/
pull down
PDB
RES
13
Input, LVCMOS w/
pull down
Reserved. This pin MUST be tied LOW.
10, 11
Channel Link III INTERFACE
DOUT+
17
16
Input/Output, CML
Input/Output, CML
Non-inverting differential output, back-channel input.
Inverting differential output, back-channel input.
DOUT-
Power and Ground
VDDPLL
VDDT
14
15
18
34
31
Power, Analog
Power, Analog
Power, Analog
Power, Digital
Power, Digital
Ground, DAP
PLL Power, 1.8V ±5%
Tx Analog Power, 1.8V ±5%
LVDS & BC Dr Power, 1.8V ±5%
Digital Power, 1.8V ±5%
VDDCML
VDDD
VDDIO
Power for input stage, The single-ended inputs are powered from VDDIO.
DAP must be grounded. Connect to the ground plane (GND) with at least 16
vias.
VSS
DAP
DS92LX2122 Pin Diagram
Top View
PASS
RES
ROUT[4]
ROUT[5]
ROUT[6]
ROUT[7]
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
DAP = GND
RES
V
DDCML
RIN+
V
DDOR2
RIN-
RES
ROUT[8]
ROUT[9]
DS92LX2122
(Top View)
BISTEN
V
DDD
ROUT[10]
ROUT[11]
ROUT[12]
ROUT[13]
V
DDPLL
RES
M/S
CAD
Figure 4. Deserializer - DS92LX2122
48-Pin WQFN (RHS Package)
4
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Product Folder Links: DS92LX2121 DS92LX2122
DS92LX2121, DS92LX2122
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Pin Name
SNLS330I –MAY 2010–REVISED APRIL 2013
DS92LX2122 Deserializer PIN DESCRIPTIONS
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
ROUT[20:0]
5, 6, 8, 9, 10,
11, 12, 13, 14,
15, 16, 18, 19,
21, 22, 23, 24,
25, 26, 27, 28
Outputs, LVCMOS
Parallel data outputs.
Pixel Clock Output Pin.
PCLK
4
Output, LVCMOS
Strobe edge set by RFB configuration. In SLEEP, outputs are controlled by the
OSS_SEL.
General Purpose Input (GPI)
GPI[3:0] 30, 31, 32, 33
General-purpose pins individually configured as inputs; which are used to
control and respond to various commands.
Input/Output, Digital
SERIAL CONTROL BUS - I2C COMPATIBLE
Input/Output, Open
Drain
Clock line for the serial control bus communication
SCL
SDA
2
1
SCL requires an external pull-up resistor to VDDIO
.
Input/Output, Open
Drain
Data line for serial control bus communication
SDA requires an external pull-up resistor to VDDIO
I2C Mode Select
.
M/S = L, Master; device generates and drives the SCL clock line. Device is
connected to slave peripheral on teh bus.
Input, LVCMOS w/
pull up
M/S
47
M/S = H, Slave (default); device accepts SCL clock input and is attached to an
I2C controller master on the bus. Slave mode does not generate the SCL clock,
but uses the clock generated by teh Master for teh data transfer.
Continuous Address Decoder
Input pin to select the Slave Device Address.
CAD
48
Input, analog
Input is connect to external resistor divider to programmable Device ID address
(see Serial Control Bus Connection)
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB = H, Receiver is enabled and is ON.
Input, LVCMOS w/
pull down
PDB
35
PDB = L, Receiver is in Sleep (Power down mode). When the Receiver is in the
SLEEP state, the LVCMOS Outputs are in TRI-STATE, the PLL is shutdown
and IDD is minimized.
LOCK Status Output Pin.
LOCK = H, PLL is Locked, outputs are active
LOCK
RES
34
Output, LVCMOS
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL. May be used as Link Status.
Reserved.
Pin 43: Leave pin open.
Pin 46: This pin MUST be tied LOW.
38, 39, 43, 46
-
Pins 38, 39: Route to test point as differential pair or leave open if unused.
BIST MODE
BIST Enable Pin.
Input, LVCMOS w/
pull down
BISTEN
44
37
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
PASS Output Pin for BIST mode.
PASS = H, ERROR FREE Transmission
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
PASS
Output, LVCOMS
Channel Link III INTERFACE
Non-inverting differential input, back channel output. The interconnect must be
AC coupled with a 0.1μF capacitor.
RIN+
RIN-
41
42
Input/Output, CML
Input/Output, CML
Inverting differential input, back channel output. The interconnect must be AC
coupled with a 0.1 μF capacitor.
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SNLS330I –MAY 2010–REVISED APRIL 2013
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DS92LX2122 Deserializer PIN DESCRIPTIONS (continued)
Pin Name
Pin No.
I/O, Type
Description
POWER AND GROUND
SSCG Power, 1.8V ±5%
Power supply must be connect regardless if SSCG function is in operation
VDDSSCG
3
Digital Power
Digital Power
TTL Output Buffer Power, The single-ended outputs and control input are
powered from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
VDDOR1/2/3
29, 20, 7
VDDD
17
36
40
45
Digital Power
Analog Power
Analog Power
Analog Power
Digital Core Power, 1.8V ±5%
Rx Analog Power, 1.8V ±5%
VDDR
VDDCML
VDDPLL
Bi-directional Channel Driver Power, 1.8V ±5%
PLL Power, 1.8V ±5%
DAP must be grounded. Connect to the ground plane (GND) with at least 16
vias.
VSS
DAP
Ground, DAP
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage ( VDD1V8
)
−0.3V to +2.5V
−0.3V to +4.0V
Supply Voltage (VDD3V3
)
LVCMOS Input Voltage (VDD1V8
LVCMOS Input Voltage (VDD3V3
)
)
−0.3V to +(VDD1V8 + 0.3V)
−0.3V to +(VDD3V3 + 0.3V)
−0.3V to +(VDD + 0.3V)
−0.3V to (VDD1V8 + 0.3V)
−0.3V to (VDD1V8 + 0.3V)
+150°C
LVCMOS Output Voltage (VDD
)
CML Receiver Input Voltage (VDD1V8
)
CML Driver Output Voltage (VDD1V8
Junction Temperature
)
Storage Temperature
−65°C to +150°C
Maximum Package Power Dissipation Capacity
1/θJA °C/W above +25°
Package Derating:
DS92LX2121 40L WQFN
θJA(based on 16 thermal vias)
θJC(based on 16 thermal vias)
DS92LX2122 48L WQFN
30.7 °C/W
6.8 °C/W
θJA(based on 16 thermal vias)
θJC(based on 16 thermal vias)
ESD Rating (IEC61000–4–2)
26.9 °C/W
4.4 °C/W
RD = 330Ω, CS = 150 pF
≥±25 kV
Air Discharge (DOUT+, DOUT-, RIN+, RIN-)
Contact Discharge (DOUT+, DOUT-, RIN+, RIN-)
ESD Rating (HBM)
≥±10 kV
≥±8 kV
For soldering specifications, see the Absolute Maximum Ratings for Soldering Application Report (literature number SNOA549).
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional; the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions
Min
1.71
1.71
3
Nom
1.8
Max
1.89
1.89
3.6
Units
VDD (1.8V)
V
V
V
VDDIO (1.8V Mode)
VDDIO (3.3V Mode)
1.8
3.3
6
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SNLS330I –MAY 2010–REVISED APRIL 2013
Recommended Operating Conditions (continued)
Min
Nom
Max
Units
Supply Noise(1)
VDDn (1.8 V)
VDDIO (1.8 V)
VDDIO (3.3 V)
25
25
50
85
50
mVP-P
mVP-P
mVP-P
°C
Operating Free Air Temperature (TA)
Input Clock Rate
-40
10
25
MHz
(1) Supply noise testing was done with minimum capacitors (as shown on Figures 35, 36) on the PCB. A sinusoidal signal is AC coupled to
the VDDn (1.8V) supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output
of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 1 MHz. The Des on the other hand
shows no error when the noise frequency is less than 750 kHz.
Serializer Electrical Characteristics(1)(2)(3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS 3.3V I/O (TX INPUTS, RX OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
VIL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Current
VIN = 3.0V to 3.6V
VIN = 3.0V to 3.6V
2.0
GND
-20
VIN
0.8
V
V
VIN = 0V or 3.6V
±1
+20
µA
VIN = 3.0V to 3.6V
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
VDDIO = 3.0V to
3.6V
2.4
VDDIO
0.4
V
V
VDDIO = 3.0V to
3.6V
GND
IOH = +4mA
IOS
Output Short Circuit Current
VOUT = 0V
Serializer
GPO Outputs
mA
-24
-39
Deserializer
LVCMOS
Outputs
Register
Address
(OSS_SEL =
0)
RPWDNB = 0V,
VOUT = 0V or VDD
IOZ
TRI-STATE Output Current
-20
+20
µA
LVCMOS DC SPECIFICATIONS 1.8V I/O (TX INPUTS, RX OUTPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)
VIH
VIL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Current
VIN = 1.71V to
1.89V
0.65 VIN
GND
-20
VIN + 0.3
0.35 VIN
+20
V
VIN = 1.71V to
1.89V
VIN = 0V or 1.89V
VIN = 1.71V to
1.89V
±1
µA
VOH
High Level Output Voltage
Low Level Output Voltage
VDDIO = 1.71V to
1.89V
IOH = −4mA
VDDIO - 0.45
GND
VDDIO
0.45
V
V
VOL
VDDIO = 1.71V to
1.89V
IOL = +4 mA
(1) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
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Serializer Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
IOS
Parameter
Conditions
Min
Typ
Max
Units
mA
(4)
Output Short Circuit Current
VOUT = 0V
Serializer
GPO Outputs
-11
Deserializer
LVCMOS
Outputs
-20
±1
IOZ
TRI-STATE Output Current
RPWDNB = 0V,
VOUT = 0V or VDD
Register
Address
(OSS_SEL =
0)
-20
+20
µA
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
RT = 100Ω
(SeeFigure 9)
268
340
1
412
50
|VOD
|
Output Differential Voltage
mV
mV
ΔVOD
Output Differential Voltage Unbalance RL = 100Ω
RL = 100Ω (See
Figure 9)
VDD (MIN) - VOD VDD - VOD VDD (MAX) -
VOS
Output Differential Offset Voltage
V
VOD (MIN)
(MAX)
ΔVOS
Offset Voltage Unbalance
Output Short Circuit Current
RL = 100Ω
1
50
mV
mA
IOS
DOUT+/- = 0V,
PDB = L or H
-27
(4)
RT
Differential Internal Termination
Resistance
Differential across
DOUT+ and
DOUT-
80
100
120
Ω
CML RECEIVER DC SPECIFICATIONS (RIN+, RIN-)
VTH
VTL
VIN
Differential Threshold High Voltage
Differential Threshold Low Voltage
Differential Input Voltage Range
+90
VCM = 1.2V
RIN+ - RIN-
mV
-90
180
-20
mV
µA
Ω
VIN = VDD or 0 V,
VDD = 1.89 V
±1
+20
120
IIN
Input Current
RT
Differential Internal Termination
Resistance
Differential across
RIN+ and RIN-
80
100
SER/DES SUPPLY CURRENT *DIGITAL, PLL,
AND ANALOG VDDS
RT = 100Ω
WORST CASE
pattern (See
Figure 6)
62
55
90
VDDn = 1.89
V
f = 50 MHz
Default
Serializer (Tx)
Total Supply Current Mode (includes
load current)
IDDT
mA
RT = 100Ω
RANDOM pattern
Registers
RT = 100Ω
WORST CASE
pattern (See
Figure 6)
VDDIO = 1.89
V
PCLK = 50
MHz
2
5
Default
Registers
Serializer (Tx)
VDDIO Supply Current (includes load
current)
IDDIOT
mA
VDDIO = 3.6 V
PCLK = 50
MHz
7
15
Default
Registers
IDDTZ
VDD = 1.89 V
370
55
775
125
135
PDB = 0V; All
other LVCMOS
Inputs = 0V
IDDIOTZ
Serializer (Tx) Supply Current Power-
down
VDDIO = 1.89
V
µA
VDDIO = 3.6 V
65
(4) Specification is guaranteed by characterization and is not tested in production.
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Product Folder Links: DS92LX2121 DS92LX2122
DS92LX2121, DS92LX2122
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SNLS330I –MAY 2010–REVISED APRIL 2013
Serializer Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VDDn = 1.89V
CL = 8pF
PCLK = 50
MHz
WORST CASE
Pattern
(See Figure 6)
SSCG[3:0] =
ON
Default
60
96
Deserializer (Rx)
VDDn Supply Current (includes load
current)
IDDR
mA
Registers
VDDn = 1.89V
CL = 8pF
RANDOM Pattern Default
Registers
PCLK = 50
MHz
53
21
IDDIOR
Deserializer (Rx)
VDDIO = 1.89 V
VDDIO Supply Current (includes load CL = 8pF
PCLK = 50
MHz
Default
current)
WORST CASE
32
Pattern
Registers
(See Figure 6)
mA
VDDIO = 3.6 V
CL = 8pF
PCLK = 50
MHz
WORST CASE
Pattern
(See Figure 6)
Default
Registers
49
42
83
PDB = 0V; All
other LVCMOS
Inputs = 0V
VDDn = 1.89
V
400
IDDRZ
Deserializer (Rx) Supply Current
Power-down
VDDIO = 1.89
V
µA
8
40
IDDIORZ
VDDIO = 3.6 V
350
800
Serializer Electrical Characteristics Recommended Serializer Timing for PCLK(1)(2)(3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
10 MHz – 50 MHz
Min
20
Typ
T
Max
100
Units
tTCP
tTCIH
Transmit Clock Period
ns
ns
(4)
Transmit Clock Input High
Time
0.4T
0.5T
0.6T
tTCIL
Transmit Clock Input Low
Time
0.4T
0.5
0.5T
0.6T
3
ns
tCLKT
tOSC
PCLK Input Transition Time
ns
Internal oscillator clock
source
25
MHz
(1) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
(4) Specification is guaranteed by characterization and is not tested in production.
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Serializer Electrical Characteristics Serializer Switching Characteristics(1)(2)(3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tLHT
CML Low-to-High Transition RL = 100Ω (Figure 7)
Time
150
330
ps
tHLT
CML High-to-Low Transition RL = 100Ω
150
330
ps
Time
(Figure 7)
tDIS
tDIH
tPLD
Data Input Setup to PCLK
Data Input Hold from PCLK
Serializer PLL Lock Time
2.0
2.0
ns
ns
Serializer Data Inputs (Figure 13)
RL = 100Ω
1
2
ms
RT = 100Ω
f = 10-50 MHz
Reg Address 0x03h b[0] (TRFB = 1)
(Figure 15)
6.386T +
12
6.386T +
19.7
tSD
Serializer Delay
6.386T + 5
ns
tJIND
Serializer Output
Deterministic Jitter
Serializer output intrinsic deterministic
jitter . Measured (cycle-cycle) with
PRBS-7 test pattern PCLK = 50 MHz
0.13
0.04
UI
UI
tJINR
Serializer Output Random
Jitter
Serializer output intrinsic random jitter
(cycle-cycle). Alternating-1,0 pattern.
PCLK = 50 MHz
Serializer output peak-to-peak jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measured (cycle-cycle) with
PRBS-7 test pattern.
Peak-to-peak Serializer
Output Jitter
tJINT
0.396
UI
PCLK = 50MHz
Serializer Jitter Transfer
Function -3 dB Bandwidth
PCLK = 50 MHz Default Registers
PCLK = 50 MHz Default Registers
PCLK = 50 MHz Default Registers
λSTXBW
δSTX
1.90
MHz
dB
Serializer Jitter Transfer
Function (Peaking
0.944
Serializer Jitter Transfer
Function (Peaking
Frequency)
δSTXf
500
kHz
(1) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
Serializer Electrical Characteristics Deserializer Switching Characteristics(1)(2)(3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tRCP
Parameter
Receiver Output Clock Period
PCLK Duty Cycle
Conditions
tRCP = tTCP
Pin/Freq.
Min
20
Typ
T
Max
100
55
Units
ns
PCLK
PCLK
tPDC
45
50
2.0
%
LVCMOS Low-to-High Transition
Time
VDDIO: 1.71 V to 1.89 V
or 3.0 V to 3.6 V,
1.3
2.8
tCLH
tCHL
Deserializer PCLK
Output
CL = 8pF (lumped load)
Default Registers
ns
1.3
2.0
2.8
LVCMOS High-to-Low Transition
Time
(4)
(Figure 16 )
(1) The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not guaranteed.
(4) Specification is guaranteed by design and is not tested in production.
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Serializer Electrical Characteristics Deserializer Switching Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
LVCMOS Low-to-High Transition
Time
VDDIO: 1.71 V to 1.89 V
or 3.0 V to 3.6 V,
1.6
2.4
3.3
tCLH
Deserializer Data
Outputs
CL = 8pF (lumped load)
Default Registers
ns
1.6
2.4
3.3
LVCMOS High-to-Low Transition
Time
tCHL
tROS
tROH
(4)
(Figure 17)
ROUT Setup Data to PCLK
ROUT Hold Data to PCLK
VDDIO: 1.71 V to 1.89 V
or 3.0 V to 3.6 V, CL =
8pF (lumped load)
0.38
0.5
Deserializer Data
Outputs
T
0.38T
0.5T
Default Registers
Default Registers
Register 0x03h b[0]
(RRFB = 1)
Figure 18
4.571T + 4.571T + 4.571T
tDD
Deserializer Delay
10 MHz - 50 MHz
ns
8
12
+ 16
(5)
tDDLT
tRJIT
Deserializer Data Lock Time
Receiver Input Jitter Tolerance
10 MHz - 50 MHz
(6)(7)50 MHz
10 MHz
10
ms
UI
0.53
300
PCLK
550
250
ps
tDCJ
Deserializer Clock Jitter
Deserializer Period Jitter
SSCG[3:0] = OFF
50 MHz
(8) (9)
120
PCLK
10 MHz
50 MHz
425
320
600
480
tDPJ
SSCG[3:0] = OFF
ps
ps
(10) (9)
PCLK
10 MHz
50 MHz
320
300
500
500
Deserializer Cycle-to-Cycle Clock
Jitter
tDCCJ
SSCG[3:0] = OFF
(11) (9)
Spread Spectrum Clocking
Deviation Frequency
20 MHz - 50 MHz
20 MHz - 50 MHz
±0.5% to
±2.0%
%
fDEV
LVCMOS Output Bus
SSC[3:0] = ON
Figure 20
Spread Spectrum Clocking
Modulation Frequency
9 kHz to
66 kHz
kHz
fMOD
(5) tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK.
(6) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
(7) tRJIT max (0.61UI) is limited by instrumentation and actual tRJIT of in-band jitter at low frequency (<2 MHz) is greater 1 UI.
(8) tDCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
(9) Specification is guaranteed by characterization and is not tested in production.
(10) tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
(11) tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
Bi-Directional Control Bus AC Timing Specifications (SCL, SDA) - I2C Compliant (Figure 5)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RECOMMENDED INPUT TIMING REQUIREMENTS(1)
fSCL
SCL Clock Frequency
SCL Low Period
fSCL = 100 kHz
>0
4.7
4.0
100
kHz
µs
fLOW
fHIGH
SCL High Period
µs
Hold time for a start or a repeated start
condition
tHD:STA
tSU:STA
4.0
4.7
µs
µs
Set Up time for a start or a repeated
start condition
tHD:DAT
tSU:DAT
tSU:STO
tr
Data Hold Time
0
3.45
µs
ns
µs
ns
ns
pF
Data Set Up Time
250
4.0
Set Up Time for STOP Condition,
SCL & SDA Rise Time
SCL & SDA Fall Time
Capacitive load for bus
1000
300
tf
Cb
400
(1) Recommended Input Timing Requirements are input specifications and not tested in production.
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Bi-Directional Control Bus AC Timing Specifications (SCL, SDA) - I2C Compliant
(Figure 5) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SWITCHING CHARACTERISTICS ()
Serializer MODE = 0 – R/W Register
0x05 = 0x40'h
100
100
fSCL
SCL Clock Frequency
SCL Low Period
kHz
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
Serializer MODE = 0 – R/W Register
0x05 = 0x40'h
tLOW
4.7
4.0
μs
μs
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
Serializer MODE = 0 – R/W Register
0x05 = 0x40'h
tHIGH
SCL High Period
Deserializer MODE = 0 – READ
Register 0x06 b[6:4] = 0x00'h
Hold time for a start or a repeated start
condition
Serializer MODE = 0 Register 0x05
= 0x40'h
tHD:STA
4.0
4.7
μs
μs
Set Up time for a start or a repeated
start condition
Serializer MODE = 0 Register 0x05
= 0x40'h
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tf
Data Hold Time
0
3.45
300
μs
μs
μs
μs
Data Set Up Time
250
4.0
Set Up Time for STOP Condition
SCL & SDA Fall Time
Serializer M/S = 0
Serializer M/S = 0
Bus free time between a stop and start
condition
tBUF
4.7
µs
Serializer
1
tTIMEOUT NACK Time out
ms
Deserializer
25
SDA
t
BUF
t
t
LOW
t
f
HD;STA
t
r
t
t
SP
t
f
r
SCL
t
t
HD;STA
SU;STA
t
SU;STO
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
Figure 5. Serial Control Bus Timing
Bi-Directional Control Bus DC Characteristics (SCL, SDA) - I2C Compliant
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIH
VIL
Input High Level
SDA and SCL
SDA and SCL
0.7 x
VDDIO
VDDIO
V
Input Low Level Voltage
0.3 x
VDDIO
GND
V
VHY
IOZ
IIN
Input Hysteresis
>50
±1
mV
µA
µA
pF
TRI-STATE Output Current
Input Current
PDB = 0V VOUT = 0V or VDD
-20
-20
+20
+20
SDA or SCL, Vin = VDDIO or GND
±1
CIN
Input Pin Capacitance
<5
12
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Bi-Directional Control Bus DC Characteristics (SCL, SDA) - I2C Compliant (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VOL
Low Level Output Voltage
SCL and SDA VDDIO = 3.0V IOL = 1.5
mA
0.36
V
SCL and SDA VDDIO = 1.71V IOL = 1
mA
0.36
V
AC Timing Diagrams and Test Circuits
Device Pin Name
Signal Pattern
T
PCLK
ODD D /R
IN OUT
EVEN D /R
IN OUT
Figure 6. “Worst Case” Test Pattern
80%
20%
80%
Vdiff
Vdiff = 0V
20%
t
t
LHT
HLT
Vdiff = (D
+) - (D
-)
OUT
OUT
Figure 7. Serializer CML Output Load and Transition Times
100 nF
D
OUT
+
50W
50W
SCOPE
BW 8 4.0 GHz
Z
Diff
= 100W
100W
D
OUT
-
100 nF
Figure 8. Serializer CML Output Load and Transition Times
D
D
+
OUT
16
R
D /HS/VS
IN
L
-
OUT
PCLK
Figure 9. Serializer VOD DC Diagram
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D
OUT
-
Single Ended
V
V
V
OD-
OD
OD+
V
D
OUT
+
OS
ö
0V
Differential
V
OD+
0V
(D +)-(D )
OUT OUT-
V
OD-
Figure 10. Serializer VOD DC Diagram
RIN+
RIN+
RIN-
VT H
VCM = 1.2V
VTL
VID
VIN
VID
VIN
RIN-
GND
Figure 11. Low-Voltage Differential VTH/VTL Definition Diagram
V
DD
80%
80%
PCLK
20%
20%
0V
t
t
CLKT
CLKT
Figure 12. Serializer Input Clock Transition Times
t
TCP
PCLK
V
/2
V
DDIO
/2
V
/2
DDIO
DDIO
DDIO
t
t
DIH
DIS
V
DIN/HS/VS
Setup
Hold
V
/2
V
/2
DDIO
DDIO
0V
Figure 13. Serializer Setup/Hold Times
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PDB
(3.3V I/O)
2.0V
PCLK
t
PLD
TRI-STATE
TRI-STATE
Output Active
D
±
OUT
Figure 14. Serializer Data Lock Time
SYMBOL N
SYMBOL N+1
SYMBOL N+2
SYMBOL N+3
D /HS/VS
IN
t
SD
PCLK
SYMBOL N-4
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
DOUT+-
Figure 15. Serializer Delay
2.0V
PDB
(3.3V I/O)
t
DDLT
R
IN
±
LOCK
TRI- STATE
Figure 16. Deserializer Data Lock Time
80%
20%
80%
20%
Deserializer
8 pF
lumped
t
t
CHL
CLH
Figure 17. Deserializer LVCMOS Output Load and Transition Times
SYMBOL N
SYMBOL N+1
SYMBOL N+2
SYMBOL N+3
SYMBOL N+4
RIN±
tDD
PCLK
ROUT/
VS/HS
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
SYMBOL N+1
Figure 18. Deserializer Delay
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t
ROS
V
DDIO
ROUT/HS/VS
V
DDIO
/2
V
/2
DDIO
0V
t
ROH
V
DDIO
PCLK
V
/2
DDIO
0V
Figure 19. Deserializer Output Setup/Hold Times
Frequency
FPCLK+
FPCLK
FPCLK-
fdev (max)
fdev
fdev (min)
Time
1 / fmod
Figure 20. Spread Spectrum Clock Output Profile
2
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
1.0E+04
1.0E+05
1.0E+06
1.0E+07
MODULATION FREQUENCY (Hz)
Figure 21. Typical Serializer Jitter Transfer Function Curve at 43 MHz
0.62
0.61
0.60
0.59
0.58
0.57
0.56
0.55
0.54
0.53
0.52
1.0E+06
JITTER FREQUENCY (Hz)
1.0E+04
1.0E+05
1.0E+07
Figure 22. Typical Deserializer Input Jitter Tolerance Curve at 43 MHz
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Table 1. DS92LX2121 Control Registers
Addr
(Hex)
Name
Bits Field
R/W
RW
RW
Default
Description
7-bit address of Serializer; 0x58h
(1011_000X) default
7:1
DEVICE ID
0x58
0
I2C Device ID
0: Device ID is from CAD
0
SER ID
0
0
1: Register I2C Device ID overrides CAD
7:3
RESERVED
Reserved.
Standby mode control. Retains control register data.
Supported only when M/S = 0
2
STANDBY
RW
0
0: Enabled. Low-current Standby mode with wake-up
capability. Suspends all clocks and functions.
1: Disabled. Standby and wake-up disabled
1
2
Reset
DIGITAL
RESET0
0
1: Digital Reset, retained register value
1
0
RW
RW
self clear
0
1: Digital Reset, retains all register values
DIGITAL RESET1
self clear
Reserved
Reserved
7:0
7:6
RESERVED
RESERVED
0x20'h
11'b
Reserved.
Reserved.
Auto VDDIO detect
Allows manual setting of VDDIO by register.
0: Disable
1: Enable (auto detect mode)
VDDIO Control
VDDIO Mode
5
4
VDDIO CONTOL
VDDIO MODE
RW
1
1
VDDIO voltage set
Only used when VDDIOCONTROL = 0
0: 1.8V
1: 3.3V
I2C Pass-Through Mode
0: Disabled
RW
RW
I2C PASS-
THROUGH
I2C Pass-Through
Reserved
3
2
1
0
3
1: Enabled
RESERVED
Reserved.
Switch over to internal 25 MHz oscillator clock in the
absence of PCLK
0: disable
1: enable
PCLK_AUTO
1
PCLK_AUTO
RW
RW
1
Pixel Clock Edge Select:
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
TRFB
0
TRFB
1
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
4
5
Reserved
7:0
7:0
RESERVED
0x80'h
0x40'h
Reserved.
I2C SCL frequency is determined by the following: fSCL
6.25 MHz / Register value (in decimal) 0x40'h = ~100
kHz SCL (default)
=
I2C Bus Rate
I2C BUS RATE
RW
RW
RW
Note: Register values <0x32'h are NOT supported.
Deserializer Device ID = 0x60
(1100_000X) default
7:1
DES DEV ID
0x60'h
6
7
DES ID
0
RESERVED
SLAVE DEV ID
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
Reserved.
7:1
0
0
Slave Device ID. Sets remote slave I2C address.
Slave ID
0
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
8
9
Reserved
Reserved
Reserved
Reserved
7:0
7:0
7:0
7:0
0
0x01'h
A
B
0
0
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Table 1. DS92LX2121 Control Registers (continued)
Addr
(Hex)
Name
Reserved
PCLK Detect
Reserved
Bits Field
R/W
Default
Description
7:3
2
RESERVED
0
0
Reserved.
1: Valid PCLK detected
0: Valid PCLK not detected
PCLK DETECT
RESERVED
R
C
1
Reserved.
Cable Link Detect
Status
0: Cable link not detected
1: Cable link detected
0
LINK DETECT
R
0
D
E
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7:0
7:0
7:0
7:0
7:0
7:0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
GPCR[7]
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
0: LOW
F
10
11
12
GPCR[6]
1: HIGH
GPCR[5]
GPCR[4]
General Purpose
Control Reg
13
7:0
RW
0
GPCR[3]
GPCR[2]
GPCR[1]
GPCR[0]
Table 2. DS92LX2122 Control Registers
Addr
(Hex)
Name
Bits
Field
R/W
RW
RW
Default
0x60h
0
Description
7-bit address of Deserializer;
7:1
DEVICE ID
0x60h
(1100_000X) default
0
I2C Device ID
0: Device ID is from CAD
1: Register I2C Device ID overrides CAD
0
DES ID
7:3
RESERVED
Reserved
Remote Wake-up Select
1: Enable. Generate remote wakeup signal automatically
wake-up the Serializer in Standby mode
0: Disable. Puts the Serializer in Standby mode
2
REM_WAKEUP
RW
0
1
Reset
1: Resets the device to default register values. Does not
affect device I2C Bus or Device ID
1
0
DIGITALRESET0
DIGITALRESET1
RW
RW
0 self clear
0 self clear 1: Digital Reset, retained register value
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Table 2. DS92LX2122 Control Registers (continued)
Addr
(Hex)
Name
Bits
7:6
5
Field
RESERVED
AUTO_CLOCK
R/W
Default
Description
Reserved
Auto Clock
0
0
Reserved.
1: Output PCLK or internal 25 MHz Oscillator clock
0: Only PCLK when valid PCLK present
RW
RW
Output Sleep State Select
0: Outputs = LOW , when LOCK = L
1: Outputs = TRI-STATE, when LOCK = L
OSS Select
4
OSS_SEL
0
SSCG Select
0000: Normal Operation, SSCG OFF
0001: fmod (KHz) PCLK/2168, fdev ±0.50%
0010: fmod (KHz) PCLK/2168, fdev ±1.00%
0011: fmod (KHz) PCLK/2168, fdev ±1.50%
0100: fmod (KHz) PCLK/2168, fdev ±2.00%
0101: fmod (KHz) PCLK/1300, fdev ±0.50%
0110: fmod (KHz) PCLK/1300, fdev ±1.00%
0111: fmod (KHz) PCLK/1300, fdev ±1.50%
1000: fmod (KHz) PCLK/1300, fdev ±2.00%
1001: fmod (KHz) PCLK/868, fdev ±0.50%
1010: fmod (KHz) PCLK/868, fdev ±1.00%
1011: fmod (KHz) PCLK/868, fdev ±1.50%
1100: fmod (KHz) PCLK/868, fdev ±2.00%
1101: fmod (KHz) PCLK/650, fdev ±0.50%
1110: fmod (KHz) PCLK/650, fdev ±1.00%
1111: fmod (KHz) PCLK/650, fdev +/-1.50%
2
SSCG
3:0
SSCG
0
Reserved
7:6
5
RESERVED
11'b
1
Reserved.
Auto voltage control
0: Disable
1: Enable (auto detect mode)
VDDIO Control
VDDIO CONTROL
RW
RW
VDDIO voltage set
Only used when VDDIOCONTROL = 0
VDDIO Mode
4
3
VDDIO MODE
0
1
0: 1.8V
1: 3.3V
I2C Pass-Through Mode
0: Pass-Through Enabled
1: Pass-Through Disabled
I2C PASS-
THROUGH
3
I2C Pass-Through
RW
RW
0: Disable
1: Enable
Auto ACK
Reserved
2
1
AUTO ACK
RESERVED
0
0
Reserved.
Pixel Clock Edge Select
0: Parallel Interface Data is strobed on the Falling Clock
RRFB
0
RRFB
RW
RW
1
Edge
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
EQ Gain
00'h = ~0.0 dB
01'h = ~4.5 dB
03'h = ~6.5 dB
07'h = ~7.5 dB
0F'h = ~8.0 dB
1F'h = ~11.0 dB
3F'h = ~12.5 dB
FF'h = ~14.0 dB
4
5
EQ Control
Reserved
7:0
7:0
EQ
0
0
RESERVED
Reserved.
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Table 2. DS92LX2122 Control Registers (continued)
Addr
(Hex)
Name
Bits
Field
R/W
RW
RW
Default
Description
Reserved
7
RESERVED
Reserved.
Prescales the SCL clock line when reading data byte
from a slave device (MODE = 0)
000 : ~100 kHz SCL (default)
001 : ~125 kHz SCL
SCL Prescale
Remote NACK
6:4
SCL_PRESCALE
0
1
101 : ~11 kHz SCL
110 : ~33 kHz SCL
111 : ~50 kHz SCL
Other values are NOT supported.
Remote NACK Timer Enable In slave mode (MODE = 1)
if bit is set the I2C core will automatically timeout when
no acknowledge condition was detected.
1: Enable
REM_NACK_TIM
ER
6
3
0: Disable
Remote NACK Timeout
000: 2.0 ms
001: 5.2 ms
010: 8.6 ms
REM_NACK_TIME
R
Remote NACK
2:0
7:1
RW
RW
111'b
011: 11.8 ms
100: 14.4 ms
101: 18.4 ms
110: 21.6 ms
111: 25.0 ms
Serializer Device ID = 0x58
(1011_000X) default
SER DEV ID
0x58h
7
SER ID
0
7:1
0
RESERVED
ID[0] INDEX
RESERVED
ID[1] INDEX
RESERVED
ID[2] INDEX
RESERVED
ID[3] INDEX
RESERVED
ID[4] INDEX
RESERVED
ID[5] INDEX
RESERVED
ID[6] INDEX
RESERVED
ID[7] INDEX
RESERVED
ID[0] MATCH
RESERVED
ID[1] MATCH
RESERVED
ID[2] MATCH
RESERVED
ID[3] MATCH
RESERVED
ID[4] MATCH
RESERVED
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
ID[0] Index
RW
Target slave Device ID slv_id1 [7:1]
Reserved.
8
9
7:1
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Target slave Device ID slv_id1 [7:1]
Reserved.
ID[1] Index
ID[2] Index
ID[3] Index
ID[4] Index
ID[5] Index
ID[6] Index
ID[7] Index
ID[0] Match
ID[1] Match
ID[2] Match
ID[3] Match
ID[4] Match
7:1
0
Target slave Device ID slv_id2 [7:1]
Reserved.
A
7:1
0
Target slave Device ID slv_id3 [7:1]
Reserved.
B
7:1
0
Target slave Device ID slv_id4 [7:1]
Reserved.
C
7:1
0
Target slave Device ID slv_id5 [7:1]
Reserved.
D
7:1
0
Target slave Device ID slv_id6 [7:1]
Reserved.
E
7:1
0
Target slave Device ID slv_id7 [7:1]
Reserved.
F
7:1
0
Alias to match Device ID slv_id0 [7:1]
Reserved.
10
11
12
13
14
7:1
0
Alias to match Device ID slv_id1 [7:1]
Reserved.
7:1
0
Alias to match Device ID slv_id2 [7:1]
Reserved.
7:1
0
Alias to match Device ID slv_id3 [7:1]
Reserved.
7:1
0
Alias to match Device ID slv_id4 [7:1]
Reserved.
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Table 2. DS92LX2122 Control Registers (continued)
Addr
(Hex)
Name
Bits
Field
R/W
Default
Description
7:1
0
ID[5] MATCH
RESERVED
ID[6] MATCH
RESERVED
ID[7] MATCH
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RW
0
Alias to match Device ID slv_id5 [7:1]
15
16
17
ID[5] Match
0
Reserved
7:1
0
RW
RW
0
Alias to match Device ID slv_id6 [7:1]
ID[6] Match
ID[7] Match
0
Reserved.
7:1
0
0
Alias to match Device ID slv_id [7:1]
0
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
18
19
1A
1B
Reserved
Reserved
Reserved
Reserved
Reserved
7:0
7:0
7:0
7:0
7:2
0
0x01'h
0
0
0
Signal Detect
Status
0: Active signal not detected
1: Active signal detected
1
0
R
R
0
0
1C
0: CDR/PLL Unlocked
1: CDR/PLL Locked
LOCK Pin Status
1D
1E
1F
20
21
22
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7:0
7:0
7:0
7:0
7:0
7:0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0x17'h
0x07'h
0x01'h
0x01'h
0x01'h
0x01'h
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
GPCR[7]
GPCR[6]
GPCR[5]
GPCR[4]
GPCR[3]
GPCR[2]
GPCR[1]
GPCR[0]
0: LOW
1: HIGH
General Purpose
Control Reg
23
7:00
7:1
RW
0
Reserved
BIST
RESERVED
BIST_EN
0
0
0
0
0
Reserved.
0
BIST Enable
0: Normal operation
1: Bist Enable
24
25
26
RW
R
BIST_ERR
7:0
7:6
5:0
BIST_ERR
Bist Error Counter
11: Enable remote wake up mode
00: Normal operation mode
Other values are NOT supported.
REM_WAKEUP_E
N
RW
RW
Remote Wake
Enable
RESERVED
Reserved
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FUNCTIONAL DESCRIPTION
The DS92LX2121 / DS92LX2122 Channel Link III chipset is intended for camera applications. The Serializer/
Deserializer chipset operates from a 10 MHz to 50 MHz pixel clock frequency. The DS92LX2121 transforms a
21-bit wide parallel LVCMOS data bus along with a bi-directional back channel control bus into a single high-
speed differential pair. The high speed serial bit stream contains an embedded clock and DC-balance information
which enhances signal quality to support AC coupling. The DS92LX2122 receives the single serial data stream
and converts it back into a 21-bit wide parallel data bus together with the back channel data bus.
The control channel function of the DS92LX2121 / DS92LX2122 provides bi-directional communication between
the image sensor and Electronic Control Unit (ECU). The integrated back channel transfers data bi-directionally
over the same differential pair used for video data interface. This interface offers advantages over other chipsets
by eliminating the need for additional wires for programming and control. The back channel bus is controlled via
an I2C port. The bi-directional back channel offers asymmetrical communication and is not dependent on video
blanking intervals.
DISPLAY APPLICATION
The DS92LX2121 / DS92LX2122 chipset is intended for interface between a host (graphics processor, FPGA,
etc.) and a Display. It supports a 21 bit parallel video bus for 18-bit color depth (RGB666) display format. In a
RGB666 configuration, 18 color bits (R [5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits (VS, HS
and DE) are supported across the serial link. The DS92LX2121 Serializer accepts a 21-bit parallel data bus
along with a bi-directional control bus. The parallel data and bi-directional control channel information is
converted into a single differential link. The integrated bi-directional control channel bus supports I2C compatible
operation for controlling auxiliary data transport to and from host processor and display module. The
DS92LX2122 Deserializer extracts the clock/control information from the incoming data stream and reconstructs
the 21-bit data with control channel data.
SERIAL FRAME FORMAT
The DS92LX2121 / DS92LX2122 chipset will transmit and receive a pixel of data in the following format:
I2C
Bit 0 to Bit 20
Figure 23. Serial Bitstream for 28-bit Symbol
The High Speed Forward Channel is a 28-bit symbol composed of 21 bits of data containing video data & control
information transmitted from Serializer to Deserializer. CLK1 and CLK0 represent the embedded clock in the
serial stream. CLK1 is always HIGH and CLK0 is always LOW. This data payload is optimized for signal
transmission over an AC coupled link. Data is randomized, balanced and scrambled.
The bi-directional control channel data is transferred along with the high-speed forward data over the same serial
link. This architecture provides a full duplex low speed forward channel across the serial link together with a high
speed forward channel without the dependence of the video blanking phase.
DESCRIPTION OF BI-DIRECTIONAL CONTROL BUS AND I2C MODES
The I2C compatible interface allows programming of the DS92LX2121, DS92LX2122, or an external remote
device (such as a display) through the bi-directional control channel. Register programming transactions to/from
the DS92LX2121 / DS92LX2122 chipset are employed through the clock (SCL) and data (SDA) lines. These two
signals have open drain I/Os and both lines must be pulled-up to VDDIO by external resistor. Figure 5 shows the
timing relationships of the clock (SCL) and data (SDA) signals. Pull-up resistors or current sources are required
on the SCL and SDA busses to pull them high when they are not being driven low. A logic zero is transmitted by
driving the output low. A logic high is transmitted by releasing the output and allowing it to be pulled-up
externally. The appropriate pull-up resistor values will depend upon the total bus capacitance and operating
speed. The DS92LX2121 / DS92LX2122 I2C bus data rate supports up to 100 kbps according to I2C
specification.
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To start any data transfer, the DS92LX2121 / DS92LX2122 must be configured in the proper I2C mode. Each
device can function as an I2C slave proxy or master proxy depending on the mode determined by M/S pin. The
Ser/Des interface acts as a virtual bridge between the host device and the remote device. When the M/S pin is
set to HIGH, the device is treated as a slave proxy; and acts as a slave on behalf of the remote slave. When
addressing a remote peripheral or Serializer/ Deserializer (not wired directly to the host device), the slave proxy
will forward any byte transactions sent by the host controller to the target device. When M/S pin is set to LOW,
the device will function as a master proxy device, and acts as a master on behalf of the I2C master controller.
Note that the devices must have complementary settings for the M/S configuration. For example, if the Serializer
M/S pin is set to HIGH then the Deserializer M/S pin must be set to LOW and vice-versa.
Bus Activity:
Master
Register
Address
Slave
Address
Data
SDA Line
7-bit Address
P
S
0
A
C
K
A
C
K
A
C
K
Bus Activity:
Slave
Figure 24. Write Byte
N
A
C
K
Bus Activity:
Master
Register
Address
Slave
Address
Slave
Address
S
P
SDA Line
S
7-bit Address
7-bit Address
0
1
A
C
K
A
C
K
A
C
K
Data
Bus Activity:
Slave
Figure 25. Read Byte
ACK
LSB
MSB
N/ACK
SDA
SCL
MSB
LSB
R/W
Direction
7-bit Slave Address
Data Byte
Bit
Acknowledge
*Acknowledge
or Not-ACK
from the Device
8
9
8
9
1
2
6
7
1
2
Repeated for the Lower Data Byte
and Additional Data Transfers
START
STOP
Figure 26. Basic Operation
SDA
SCL
S
P
STOP condition
START condition, or
START repeat condition
Figure 27. START and STOP Conditions
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1.8V
10k
V
DDIO
CAD
4.7k
4.7k
SER
or
R
CAD
HOST
SCL
SDA
SCL
SDA
DES
To other
Devices
Figure 28. Serial Control Bus Connection
SLAVE CLOCK STRETCHING
In order to communicate and synchronize with remote devices on the I2C bus through the bi-directional control
channel, slave clock stretching must be supported by the I2C master controller/host device. The chipset utilizes
bus clock stretching (holding the SCL line low) during data transmission; where the I2C slave pulls the SCL line
low on the 9th clock of every I2C data transfer (before the ACK signal). The slave device will not control the clock
and only stretches it until the remote peripheral has responded; which is typically in the order of 12 μs (typical).
CAD PIN ADDRESS DECODER
The CAD pin is used to decode and set the physical slave address of the Serializer/Deserializer (I2C only) to
allow up to six devices on the bus using only a single pin. The pin sets one of six possible addresses for each
Serializer/Deserializer device. The pin must be pulled to VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor and a
pull down resistor (RID) of the recommended value to set the physical device address. The recommended
maximum resistor tolerance is 0.1% worst case (0.2% total tolerance).
Table 3. DS92LX2121 RID Resistor Values
CAD Values - DS92LX2121 Ser
Resistor RID kΩ
Address 7'b
Address 8'b 0 appended (WRITE)
0
7b' 101 1000 (h'58)
8b' 1011 0000 (h'B0)
GND
2.0k
4.7k
7b' 101 1001 (h'59)
7b' 101 1010 (h'5A)
7b' 101 1011 (h'5B)
7b' 101 1100 (h'5C)
7b' 101 1110 (h'5E)
8b' 1011 0010 (h'B2)
8b' 1011 0100 (h'B4)
8b' 1011 0110 (h'B6)
8b' 1011 1000 (h'B8)
8b' 1011 1100 (h'BC)
8.2k
12.1k
39.0k
Table 4. DS92LX2122 RID Resistor Values
CAD Values - DS92LX2122 Des
Resistor RID kΩ
Address 7'b
Address 8'b 0 appended (WRITE)
0
7b' 110 0000 (h'60)
8b' 1100 0000 (h'C0)
GND
2.0k
4.7k
7b' 110 0001 (h'61)
7b' 110 0010 (h'62)
7b' 110 0011 (h'63)
7b' 110 0100 (h'64)
7b' 110 0110 (h'66)
8b' 1100 0010 (h'C2)
8b' 1100 0100 (h'C4)
8b' 1101 0110 (h'C6)
8b' 1101 1000 (h'C8)
8b' 1100 1100 (h'CC)
8.2k
12.1k
39.0k
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CAMERA MODE OPERATION
In Camera mode, I2C transactions originate from the Deserializer from the host controller. The I2C slave core in
the Deserializer will detect if a transaction is intended for the Serializer or a slave at the Serializer. Commands
are sent over the bi-directional control channel to initiate the transactions. The Serializer will receive the
command and generate an I2C transaction on its local I2C bus. At the same time, the Serializer will capture the
response on the I2C bus and return the response as a command on the forward channel link. The Deserializer
parses the response and passes the appropriate response to the Deserializer I2C bus.
To configure the devices for camera mode operation, set the Serializer M/S pin to LOW and the Deserializer M/S
pin to HIGH. Before initiating any I2C commands, the Deserializer needs to be programmed with the target slave
device addresses and Serializer device address. SER_DEV_ID Register 0x07h sets the Serializer device
address and SLAVE_x_MATCH/SLAVE_x_INDEX registers 0x08h~0x17h set the remote target slave addresses.
The slave address match registers must also be set. In slave mode the address register is compared with the
address byte sent by the I2C master. If the addresses are equal to any of registers values, the I2C slave will
acknowledge the transaction to the I2C master allowing reads or writes to target device.
DISPLAY MODE OPERATION
In Display mode, I2C transactions originate from the controller attached to the Serializer. The I2C slave core in
the Serializer will detect if a transaction targets (local) registers within the Serializer or the (remote) registers
within the Deserializer or a remote slave connected to the I2C master interface of the Deserializer. Commands
are sent over the forward channel link to initiate the transactions. The Deserializer will receive the command and
generate an I2C transaction on its local I2C bus. At the same time, the Deserializer will capture the response on
the I2C bus and return the response as a command on the bi-directional control channel. The Serializer parses
the response and passes the appropriate response to the Serializer I2C bus.
The physical device ID of the I2C slave in the Serializer is determined by the analog voltage on the CAD pin
input. It can be reprogrammed by using the SER_DEV_ID register and setting the bit . The device ID of the
logical I2C slave in the Deserializer is determined by programming the DES ID in the Serializer. The state of the
CAD pin input on the Deserializer is used to set the device ID. The I2C transactions between Ser/ Des will be
bridged between the host to the remote slave.
To configure the devices for display mode operation, set the Serializer M/S pin to HIGH and the Deserializer M/S
pin to LOW. Before initiating any I2C commands, the Serializer needs to be programmed with the target slave
device address and Serializer device address. DES_DEV_ID Register 0x06h sets the Deserializer device
address and SLAVE_DEV_ID register 0x7h sets the remote target slave address. If the I2C slave address
matches any of registers values, the I2C slave will acknowledge the transaction allowing read or write to target
device. Note: In Display mode operation, registers 0x08h~0x17h on Deserializer must be reset to 0x00.
PROGRAMMABLE CONTROLLER
An integrated I2C slave controller is embedded in each of the DS92LX2121 Serializer and DS92LX2122
Deserializer. It must be used to access and program the extra features embedded within the configuration
registers. Refer to Table 1 and Table 2 for details of control registers.
I2C PASS THROUGH
I2C pass-through provides an alternative means to independently address slave devices. The mode enables or
disables I2C bidirectional control channel communication to the remote I2C bus. This option is used to determine
whether or not an I2C instruction is to be transferred over to the remote I2C device. When enabled, the I2C bus
traffic will continue to pass through and will be received by I2C devices downstream. If disabled, I2C commands
will be excluded to the remote I2C device. The pass through function also provides access and communication to
only specific devices on the remote bus. The feature is effective for both Camera mode and Display mode.
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SYNCHRONIZING MULTIPLE LINKS
For applications requiring synchronization across multiple links, it is recommended to utilize the General Purpose
Input/ Output (GPI/GPO) pins to transmit control signals to synchronize slave peripherals together. To
synchronize the peripherals properly, the system controller needs to provide a sync signal output. Note this form
of synchronization timing relationship has a non-deterministic latency. After the control data is reconstructed from
the bi-directional control channel, there will be a time variation of the GPI/GPO signals arriving at the different
target devices (between the parallel links). The maximum latency delta (t1) of the GPI/GPO data transmitted
across multiple links is 25 μs.
Note: The user must verify that the timing variations between the different links are within their system and timing
specifications.
The maximum time (t1) between the rising edge of GPI/GPO (i.e. sync signal) arriving at Camera A and Camera
B is 25 μs.
DES A
GPIO[n] Input
DES B
GPIO[n] Input
SER A
GPIO[n] Output
SER B
GPIO[n] Output
t1
Figure 29. GPIO Delta Latency
GENERAL PURPOSE I/O (GPIO)
The DS92LX2121 / DS92LX2122 has up to 4 GPO and 4 GPI on the Serializer and Deserializer respectively.
The GPI/GPO maximum switching rate is up to 66 kHz for communication between Deserializer GPI to Serializer
GPO.
AT-SPEED BIST (BISTEN, PASS)
An optional AT SPEED Built in Self Test (BIST) feature supports at speed testing of the high-speed serial and
the back-channel link. Control pins allow the system to initiate the test and set the duration. A HIGH on PASS pin
indicates that all payloads received during the test were error free during the BIST duration test. A LOW on this
pin at the conclusion of this test indicates that one or more payloads were detected with errors.
The BIST duration is defined by the width of BISTEN. BIST starts when BISTEN goes HIGH. BIST ends when
BISTEN goes LOW. PASS flag will go HIGH when no errors detected after BIST Duration completes. Any errors
detected after the BIST Duration are not included in PASS logic.
The following diagram shows how to perform system AT SPEED BIST:
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Serializer MODE = 0 and Deserializer MODE = 1
Apply power for Serializer and Deserializer
Normal
Step 1: Enable AT SPEED BIST by placing the
Deserializer in BIST by mode setting BISTEN = H
BIST Wait
Step 4: Place System in
Normal Operating Mode
BISTEN = L
Step 2: Deserializer will setup Serializer and enable BIST
mode through Bidirectional control channel
communication and then reacquire forward channel clock
BIST Start
Step 3: Stop AT SPEED BIST by turning off BIST
mode with BISTEN = L at the Deserializer.
BIST Stop
Figure 30. AT-SPEED BIST System Flow Diagram
Step 1: Place the Deserializer in BIST Mode.
Serializer and Deserializer power supply must be supplied. Set the Serializer M/S pin to LOW and the
Deserializer M/S pin to HIGH. Enable the AT SPEED BIST mode on the Deserializer by setting the BISTEN pin
High. The DS92LX2122 GPIO[1:0] pins are used to select the PCLK frequency of the on-chip oscillator for the
BIST test on high speed data path.
Table 5. Oscillator Frequency Select
Freq Control
Oscillator Range
External PCLK
min (MHz)
typ (MHz)
max (MHz)
00
01
10
11
10
50
Internal
Internal
Internal
50
25
12.5
The Deserializer GPIO[1:0] set to 00 will bypass the on-chip oscillator and an external oscillator to Serializer
PCLK input is required. This allows the user to operate BIST under different frequencies other than the
predefined ranges.
Step 2: Enable AT SPEED BIST by placing the Serializer into BIST mode.
Deserializer will communicate through the back-channel to configure Serializer into BIST mode. Once the BIST
mode is set, the Serializer will initiate BIST transmission to the Deserializer.
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Wait 10 ms for Deserializer to acquire lock and then monitor the LOCK pin transition from LOW to HIGH. At this
point, AT SPEED BIST is operational and the BIST process has begun. The Serializer will start transfer of an
internally generated PRBS data pattern through the high speed serial link. This pattern traverses across the
interconnecting link to the Deserializer. Check the status of the PASS pin; a HIGH indicates a pass, a LOW
indicates a fail. A fail will stay LOW for ½ a clock cycle. If two or more bits fail in a row the PASS pin will toggle ½
clock cycle HIGH and ½ clock cycle low. The user can use the PASS pin to count the number of fails on the high
speed link. In addition, there is a defined SER and DES register that will keep track of the accumulated error
count. The Serializer DS92LX2121 GPIO[0] pin will be assigned as a PASS flag error indicator for the back-
channel link.
Recovered
Pixel Clock
BISTEN
Case 1: No bit errors
Recovered
Pixel Data
Previous
—CRC“ State
PASS
—CRC“ State
—CRC“ State
—CRC“ State
Case 2: Bit error(s)
Recovered
Pixel Data
B
B
B
B
Previous
—CRC“ State
PASS
E
E
E
E
Case 3: Bit error(s) AFTER BIST Duration
Recovered
Pixel Data
B
Previous
PASS
—CRC“ State
B = Bad Pixel
PE = Payload Error
BIST Duration
(when BISTEN=H)
CRC Status
(when BISTEN=L)
Figure 31. BIST Timing Diagram
Step 3: Stop at SPEED BIST by turning off BIST mode in the Deserializer to determine Pass/Fail.
To end BIST, the system must pull BISTEN pin of the Deserializer LOW. The BIST duration is fully defined by
the BISTEN width and thus the Bit Error Rate is determined by how long the system holds BISTEN HIGH.
BIST Duration (s)
fpixel (MHz)
Pixel
x Total Pixels Transmitted = Total Bits Transmitted
BIST Duration (s) x
=
1 Pixel period (ns) x Total Bits
Bit (Pixel) Error Rate
(for passing BIST)
[Total Bits Transmitted] -1
=
[Total Bits Transmitted x Bits/Pixel] -1
=
Figure 32. BIST BER Calculation
For instance, if BISTEN is held HIGH for 1 second and the PCLK is running at 43 MHz with 16 bpp, then the Bit
Error Rate is no better than 1.46E-9.
Step 4: Place system in Normal Operating Mode by disabling BIST at the Serializer.
Once Step 3 is complete, AT SPEED BIST is over and the Deserializer is out of BIST mode. To fully return to
Normal mode, apply Normal input data into the Serializer.
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Any PASS result will remain unless it is changed by a new BIST session or cleared by asserting and releasing
PDB. The default state of PASS after a PDB toggle is HIGH.
It is important to note that AT SPEED BIST will only determine if there is an issue on the link that is not related to
the clock and data recovery of the link (whose status is flagged with LOCK pin).
LVCMOS VDDIO OPTION
1.8V or 3.3V SER Inputs and DES Outputs are user configurable to provide compatibility with 1.8V and 3.3V
system interfaces.
REMOTE WAKE UP (Camera Mode)
After initial power up, the SER is in a low-power Standby mode. The DES (controlled by the host ) 'Remote
Wakeup' register allows the DES side to generate a signal across the link to remotely wakeup the SER. Once the
SER detects the wakeup signal, the SER switches from Standby mode to active mode. In active mode, the SER
locks onto PCLK input (if present), otherwise the on-chip oscillator is used as the input clock source. Note the
host controller should monitor the DES LOCK pin and confirm LOCK = H before performing any I2C
communication across the link.
For Remote Wakeup to function properly:
•
•
•
The chipset needs to be configured in Camera mode: Serializer M/S = 0 and Deserializer M/S = 1
The SER expects remote wake up by default at power on.
Configure the control channel driver of the DES to be in remote wake up mode by setting DES register 0x26
to 0xC0.
•
•
Perform remote wake up on SER by setting DES register 0x01 b[2] to 1.
Return the control channel driver of the DES to the normal operation mode by setting DES register 0x26 to 0.
The SER can also be put into standby mode by programming the DES remote wake up control register 0x01 b[2]
REM_WAKEUP to 0.
POWERDOWN
The SER has a PDB input pin to ENABLE or Powerdown the device. The modes can be controlled by the host
and is used to disable the Link to save power when the remote device is not operational. An auto mode is also
available. In this mode, the PDB pin is tied High and the SER switches over to an internal oscillator when the
PCLK stops or not present. When a PCLK starts again, the SER will then lock to the valid input PCLK and
transmits the data to the DES. In powerdown mode, the high-speed driver outputs are static (HIGH).
The DES has a PDB input pin to ENABLE or Powerdown the device. This pin can be controlled by the system
and is used to disable the DES to save power. An auto mode is also available. In this mode, the PDB pin is tied
High and the DES will enter powerdown when the serial stream stops. When the serial stream starts up again,
the DES will lock to the input stream and assert the LOCK pin and output valid data. In powerdown mode, the
Data and PCLK outputs are set by the OSS_SEL control register.
POWER UP REQUIREMENTS AND PDB PIN
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5
ms then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB pin is pulled to VDDIO, it is recommended to use a 10 kΩ pull-up
and a 22 uF cap to GND to delay the PDB input signal.
SIGNAL QUALITY ENHANCERS
Des - Receiver Input Equalization (EQ)
The receiver inputs provided input equalization filter in order to compensate for loss from the media. The level of
equalization is controlled via register setting.
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EMI REDUCTION
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Des - Receiver Staggered Output
The Receiver staggered outputs allows for outputs to switch in a random distribution of transitions within a
defined window. Outputs transitions are distributed randomly. This minimizes the number of outputs switching
simultaneously and helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall
EMI.
Des Spread Spectrum Clocking Compatibilty
The DS92LX2122 parallel data and clock outputs have programmable SSCG ranges from 70 kHz and +-2% (4%
total) from 20 MHz to 50 MHz. The modulation rate and modulation frequency variation of output spread is
controlled through the SSC control registers.
PIXEL CLOCK EDGE SELECT (TRFB/RRFB)
The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge
that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register
is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the
data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0,
data is strobed on the Falling edge of the PCLK.
PCLK
DIN/
ROUT
TRFB/RRFB: 0
TRFB/RRFB: 1
Figure 33. Programmable PCLK Strobe Select
Applications Information
AC COUPLING
The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme.
External AC coupling capacitors must be placed in series in the Channel Link III signal path as illustrated in
Figure 34.
D
+
OUT
R
+
IN
D
R
D
-
R
IN
-
OUT
Figure 34. AC-Coupled Application
For high-speed Channel Link III transmissions, the smallest available package should be used for the AC
coupling capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s
require a 0.1 μF AC coupling capacitors to the line.
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TYPICAL APPLICATION CONNECTION
Figure 35 shows a typical connection of the DS92LX2121 Serializer.
DS92LX2121 (SER)
1.8V
VDDIO
VDDT
VDDIO
C4
C3
FB2
FB1
C12
C8
C13
C9
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
VDDPLL
VDDCML
VDDD
C10
C11
C5
C6
C7
FB3
FB4
FB5
DIN7
DIN8
DIN9
LVCMOS
Parallel
Bus
DIN10
DIN11
DIN12
DIN13
C1
C2
Serial
Channel
Link III
DOUT+
DOUT-
DIN14
DIN15
DIN16
DIN17
DIN18
Interface
1.8V
DIN19
DIN20
PCLK
10 kW
LVCMOS
Control
Interface
ID[X]
MODE
PDB
RID
GPO[0]
GPO[1]
GPO[2]
GPO[3]
GPO
Control
Interface
NOTE:
C1 - C2 = 0.1 mF (50 WV)
C3 - C9 = 0.1 mF
C10 - C13 = 4.7 mF
C14 - C15 = >100 pF
RPU = 1 kW to 4.7 kW
RID (see ID[x] Resistor Value Table)
FB1 - FB7: Impedance = 1 kW (@ 100 MHz)
low DC resistance (<1W)
VDDIO
RPU
RPU
C15
I2C
Bus
Interface
SCL
SDA
FB6
RES
DAP (GND)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
FB7
C14
Optional
Optional
Figure 35. DS92LX2121 Typical Connection Diagram
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Figure 36 shows a typical connection of the DS92LX2122 Deserializer.
DS92LX2122 (DES)
1.8V
VDDIO
VDDD
VDDIO1
VDDIO2
VDDIO3
FB1
C13
C11
C8
C12 C14
FB6
C3
C4
C5
VDDR
C9
FB2
FB3
FB4
VDDSSCG
VDDPLL
VDDCML
C10
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
C15
C6
C7
FB5
C16
C1
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
ROUT12
ROUT13
Serial
Channel
Link III
RIN+
RIN-
LVCMOS
Parallel
Bus
Interface
C2
ROUT14
ROUT15
ROUT16
ROUT17
ROUT18
ROUT19
ROUT20
TP_A
TP_B
RES_PIN38
RES_PIN39
LVCMOS
Control
Interface
MODE
PDB
PCLK
VDDIO
RPU
GPI[0]
GPI[1]
GPI[2]
GPI[3]
GPI
Control
Interface
RPU
C18
I2C
SCL
SDA
Bus
FB7
LOCK
PASS
Interface
1.8V
FB8
C17
Optional
Optional
NOTE:
C1 - C2 = 0.1 mF (50 WV)
C3 - C12 = 0.1 mF
C13 - C16 = 4.7 mF
C17 - C18 = >100 pF
RPU = 1 kW to 4.7 kW
10 kW
ID[X]
RES_PIN46
DAP (GND)
RID
RID (see ID[x] Resistor Value Table)
FB1 - FB8: Impedance = 1 kW (@ 100 MHz)
low DC resistance (<1W)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Figure 36. DS92LX2122 Typical Connection Diagram
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SNLS330I –MAY 2010–REVISED APRIL 2013
TRANSMISSION MEDIA
The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and
signal quality requirements. The Ser/Des employ internal termination providing a clean signaling environment.
The interconnect for Channel Link III interface should present a differential impedance of 100 Ohms. Use of
cables and connectors that have matched differential impedance will minimize impedance discontinuities.
Shielded or un-shielded cables may be used depending upon the noise environment and application
requirements. The chipset's optimum cable drive performance is achieved at 43 MHz at 10 meters length. The
maximum signaling rate increases as the cable length decreases. Therefore, the chipset supports 50 MHz at
shorter distances. Other cable parameters that may limit the cable's performance boundaries are: cable
attenuation, near-end crosstalk and pair-to-pair skew.
For obtaining optimal performance the system should use:
•
•
•
•
Shielded Twisted Pair (STP) cable
100Ω differential impedance and 24 AWG (or lower AWG) cable
Low skew, impedance matched
Terminate unused conductors
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the Ser/Des devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise
effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In
some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the
differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential
lines of 100 Ohms are typically recommended for differential interconnect. The closely coupled lines help to
ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled
lines will also radiate less.
Information on the LLP style package is provided in the AN-1187 Leadless Leadframe Package (LLP) Application
Report (literature number SNOA401).
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INTERCONNECT GUIDELINES
For full details, see the Channel-Link PCB and Interconnect Design-In Guidelines (literature number SNLA008)
and the Transmission Line RAPIDESIGNER Operation and Applications Guide (literature number SNLA035).
•
•
Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
–
–
–
S = space between the pair
2S = space between pairs
3S = space to LVCMOS signal
•
•
•
•
Minimize the number of Vias
Use differential connectors when operating above 500Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual (literature number SNLA187), which is
available in PDF format from the TI LVDS & CML Solutions web site.
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SNLS330I –MAY 2010–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision H (April 2013) to Revision I
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 34
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
DS92LX2121SQ/NOPB
DS92LX2121SQE/NOPB
DS92LX2121SQX/NOPB
DS92LX2122SQ/NOPB
DS92LX2122SQE/NOPB
DS92LX2122SQX/NOPB
ACTIVE
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RTA
40
40
40
48
48
48
1000
Green (RoHS
& no Sb/Br)
SN
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
LX2121
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
RTA
RTA
RHS
RHS
RHS
250
2500
1000
250
Green (RoHS
& no Sb/Br)
LX2121
LX2121
LX2122
LX2122
LX2122
Green (RoHS
& no Sb/Br)
SN
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
Green (RoHS
& no Sb/Br)
2500
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS92LX2121SQ/NOPB
WQFN
RTA
RTA
RTA
RHS
RHS
RHS
40
40
40
48
48
48
1000
250
330.0
178.0
330.0
330.0
178.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
6.3
6.3
6.3
7.3
7.3
7.3
6.3
6.3
6.3
7.3
7.3
7.3
1.5
1.5
1.5
1.3
1.3
1.3
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
DS92LX2121SQE/NOPB WQFN
DS92LX2121SQX/NOPB WQFN
2500
1000
250
DS92LX2122SQ/NOPB
WQFN
DS92LX2122SQE/NOPB WQFN
DS92LX2122SQX/NOPB WQFN
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS92LX2121SQ/NOPB
DS92LX2121SQE/NOPB
DS92LX2121SQX/NOPB
DS92LX2122SQ/NOPB
DS92LX2122SQE/NOPB
DS92LX2122SQX/NOPB
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RTA
RTA
RTA
RHS
RHS
RHS
40
40
40
48
48
48
1000
250
367.0
213.0
367.0
367.0
213.0
367.0
367.0
191.0
367.0
367.0
191.0
367.0
38.0
55.0
38.0
38.0
55.0
38.0
2500
1000
250
2500
Pack Materials-Page 2
MECHANICAL DATA
RTA0040A
SQA40A (Rev B)
www.ti.com
MECHANICAL DATA
RHS0048A
SQA48A (Rev B)
www.ti.com
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