DS96F173MJ/883 [TI]
EIA-485/EIA-422 四路差分接收器 | NFE | 16 | -55 to 125;
| 型号： | DS96F173MJ/883 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | EIA-485/EIA-422 四路差分接收器 | NFE | 16 | -55 to 125 接口集成电路 |
| 文件： | 总14页 (文件大小：467K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS96F173MQML,DS96F175MQML
DS96F173MQML/DS96F175MQML EIA-485/EIA-422 Quad Differential Receivers
Literature Number: SNOSAS9
April 28, 2011
DS96F173MQML/
DS96F175MQML
EIA-485/EIA-422 Quad Differential Receivers
General Description
Features
The DS96F173 and the DS96F175 are high speed quad dif-
ferential line receivers designed to meet the EIA-485 stan-
dard. The DS96F173 and the DS96F175 offer improved
performance due to the use of L-FAST bipolar technology.
The use of LFAST technology allows the DS96F173 and
DS96F175 to operate at higher speeds while minimizing pow-
er consumption.
Meets EIA-485, EIA-422A, EIA-423A standards
Designed for multipoint bus applications
TRI-STATE outputs
■
■
■
■
■
■
■
■
■
■
Common mode input voltage range: −7V to +12V
Operates from single +5.0V supply
Lower power version
The DS96F173 and the DS96F175 have TRI-STATE® out-
puts and are optimized for balanced multipoint data bus trans-
mission at rates up to 15 Mbps. The receivers feature high
input impedance, input hysteresis for increased noise immu-
nity, and input sensitivity of 200 mV over a common mode
input voltage range of −7V to +12V. The receivers are there-
fore suitable for multipoint applications in noisy environments.
The DS96F173 features an active high and active low Enable,
common to all four receivers. The DS96F175 features sepa-
rate active high Enables for each receiver pair.
Input sensitivity of ±200 mV over common mode range
Input hysteresis of 50 mV typical
High input impedance
DS96F173 and DS96F175 are lead and function
compatible with SN75173/175 or the AM26LS32/MC3486
Ordering Information
NS Part Number
DS96F173ME/883
SMD Part Number
5962-9076602M2A
NS Package Number
Package Description
20LD Leadless Chip Carrier
16LD Ceramic Dip
E20A
J16A
E20A
J16A
DS96F173MJ/883
DS96F175ME/883
DS96F175MJ-QMLV
5962-9076602MEA
5962-9076601M2A
5962-9076601VEA
20LD Leadless Chip Carrier
16LD Ceramic Dip
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2011 National Semiconductor Corporation
201641
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Connection Diagrams
16-Lead Ceramic Dual-In-Line Package (NS Package Number J16A)
DS96F173
DS96F175
20164101
20164102
Top View
Top View
20-Lead Ceramic Leadless Chip Carrier (NS Package Number E20A)
20164112
20164113
Top View
*NC—No Connection
Top View
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2
Logic Diagrams
20164111
20164110
DS96F175
DS96F173
(Each Receiver) DS96F175
Function Tables
Differential Inputs
Enable
Output
(Each Receiver) DS96F173
A–B
E
Y
Differential Inputs
A–B
Enable
Output
H
H
VID ≥ 0.2V
E
E
Y
H
L
L
Z
VID ≤ −0.2V
H
X
H
VID ≥ 0.2V
X
X
H
L
H
L
X
VID ≤ −0.2V
X
L
L
X
H
L
Z
Z
X
X
X
H = High Level
L = Low Level
Z = High Impedance (off)
X = Don't Care
3
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Absolute Maximum Ratings (Note 1)
Storage Temperature Range (TStg
)
−65°C ≤ TA ≤ +175°C
Lead Temperature (Soldering, 60 sec.)
Max. Package Power Dissipation at 25°C (Note 2)
Ceramic DIP (J)
Ceramic Flatpak (W)
Ceramic LCC (E)
300°C
1,500 mW
1,034 mW
1,500 mW
7.0V
Supply Voltage
Input Voltage, A or B Inputs
Differential Input Voltage
Enable Input Voltage
±25V
±25V
7.0V
Low Level Output Current
50 mA
Recommended Operating Conditions
Min
4.50
−7
Max
5.50
+12
+12
−400
16
Units
Supply Voltage (VCC
)
V
V
V
Common Mode Input Voltage (VCM
Differential Input Voltage (VID)
)
−7
Output Current HIGH (IOH
Output Current LOW (IOL
Operating Temperature (TA)
)
μA
mA
°C
)
−55
125
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Static tests at
Temp (°C)
1
2
+25
+125
-55
Static tests at
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling time at
Settling time at
Settling time at
+25
+125
-55
5
6
7
+25
+125
-55
8A
8B
9
+25
+125
-55
10
11
12
13
14
+25
+125
-55
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4
DC Parameters
The following conditions apply, unless otherwise specified. VCC = 5.0V, Outputs Enabled
Sub-
groups
Symbol
ICC
Parameter
Supply Current
Conditions
Notes
(Note 3)
(Note 4)
Min Max
Units
mA
V
VCC = 5.5V, VID = 2V
50
1, 2, 3
VCC = 4.5V, IOH = -400µA,
VID = 0.2V
VOH
VOL
Logical "1" Output Voltage
Logical "0" Output Voltage
2.5
1, 2, 3
VCC = 4.5V, IOL = 8mA,
VID = -0.2V
(Note 4)
0.45
0.20
V
V
1, 2, 3
1, 2, 3
VCC = 4.5V & 5.5V, VCM = 0V, VO
= 2.5V, IO = -400µA
VCC = 4.5V & 5.5V,
VCM = -12V, VO = 2.5V,
IO = -400µA
Differential-Input High Threshold
Voltage
VTH
0.20
V
1, 2, 3
VCC = 4.5V & 5.5V, VCM = 12V,
VO = 2.5V, IO = -400µA
0.20
V
V
1, 2, 3
1, 2, 3
VCC = 4.5V & 5.5V, VCM = 0V, VO
= 0.5V, IO = 16mA
-0.20
VCC = 4.5V & 5.5V,
VCM = -12V, VO = 0.5V,
IO = 16mA
Differential-Input Low Threshold
Voltage
VTL
-0.20
V
1, 2, 3
VCC = 4.5V & 5.5V, VCM = 12V,
VO = 0.5V, IO = 16mA
-0.20
V
1, 2, 3
1, 2, 3
1, 2, 3
VCC = 4.5V, VI = 12V,
Untested Inputs are 0V
VCC = 5.5V, VI = -7V,
Untested Inputs are 0V
VCC = 5.5V, VIH = 2.7V
1.0
mA
mA
II
Input Line Current
-0.8
IIH
IIL
Logical "1" Enable Input Current
Logical "0" Enable Input Current
10
µA
µA
mA
mA
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
VCC = 5.5V, VIL = 0.4V
VCC = 4.5V, VO = 0V
VCC = 5.5V, VO = 0V
VCC = 4.5V, II = -18mA
-100
-85
-85
-1.5
-15
-15
IOS
VIK
Output Short Circuit Current
Enable Input Clamp Voltage
(Note 8)
VCC = 5.5V, VEn = 0.8V,
VO = 0.4V,
-20
20
20
µA
µA
1, 2, 3
1, 2, 3
Outputs disabled
VCC = 5.5V, VEn = 0.8V,
VO = 2.4V,
IOZ
High Impedance Output Current
-20
2.0
Outputs disabled
VIH
VIL
RI
Logical "1" Enable Input Voltage
Logical "0" Enable Input Voltage
Input Resistance
(Note 5)
(Note 6)
V
V
1, 2, 3
1, 2, 3
1, 2, 3
0.8
10
kΩ
5
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AC Parameters
The following conditions apply, unless otherwise specified. VCC = 5.0V
Sub-
groups
Symbol
tPHL
Parameter
Propagation Delay
Conditions
Notes
Min Max
Units
22
30
22
30
16
27
18
27
20
27
30
37
18
30
3.0
8.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2, 3
1
CL = 15pF
CL = 15pF
CL = 15pF
CL = 15pF
CL = 5pF
CL = 20pF
CL = 5pF
tPLH
tPZH
tPZL
Propagation Delay
Propagation Delay
Propagation Delay
2, 3
1
2, 3
1
2, 3
1
(Note 7)
2, 3
1
tPHZ
Propagation Delay
2, 3
1
tPLZ
Propagation Delay
Propagation Delay
2, 3
1
tPW
2
3
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: Above TA = 25°C derate J package 10 mW/°C, W package 6.90 mW/°C, E package 11.11 mW/°C.
Note 3: ICC is tested with outputs disabled (worst case), ICC enabled is guaranteed by this test.
Note 4: VOH & VOL are tested over common mode voltage range of +/−12V via the VTH / VTL tests.
Note 5: Guaranteed by VOL & VOH tests.
Note 6: Guaranteed by IOZ test.
Note 7: Testing at 20pF assures conformance to spec at 5pF.
Note 8: Only one output at a time should be shorted.
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6
Parameter Measurement Information
20164104
20164103
FIGURE 1. tPLH, tPHL (Note 9, Note 10)
20164106
20164105
FIGURE 2. tHZ, tZH (Note 9, Note 10, Note 12, Note 13)
20164108
20164107
FIGURE 3. tZL, tLZ (Note 9, Note 10, Note 12, Note 13)
Note 9: The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, 50% duty cycle, tr ≤ 6.0 ns, tf ≤ 6.0 ns, ZO = 50Ω.
Note 10: CL includes probe and stray capacitance.
Note 11: DS96F173 with active high and active low Enables are shown. DS96F175 has active high Enable only.
Note 12: All diodes are 1N916 or equivalent.
Note 13: To test the active low Enable E of DS96F173, ground E and apply an inverted input waveform to E . DS96F175 has active high enable only.
7
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Typical Application
20164109
FIGURE 4.
Note: The line length should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short as possible
.
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8
Revision History
Released
Revision
Section
Changes
28–Apr-11
A
New Release, Corporate format
2 MDS data sheets converted into one Corp. data
sheet format. MNDS96F173M-X Rev 0A0 &
MNDS96F175M-X Rev 0B0 will be archived.
9
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Ceramic Leadless Chip Carrier (E)
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (J)
NS Package Number J16A
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10
16-Lead Ceramic FlatPak (W)
NS Package Number W16A
11
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