DS96F174MJ/883 [TI]
EIA-485/EIA-422 四路差分驱动器 | NFE | 16 | -55 to 125;![DS96F174MJ/883](http://pdffile.icpdf.com/pdf2/p00207/img/icpdf/5962-9_1171020_icpdf.jpg)
型号: | DS96F174MJ/883 |
厂家: | ![]() |
描述: | EIA-485/EIA-422 四路差分驱动器 | NFE | 16 | -55 to 125 驱动 接口集成电路 线路驱动器或接收器 驱动程序和接口 |
文件: | 总14页 (文件大小:381K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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DS96F172MQML,DS96F174MQML
DS96F172MQML/DS96F174MQML EIA-485/EIA-422 Quad Differential Drivers
Literature Number: SNOSAS8
April 28, 2011
DS96F172MQML/
DS96F174MQML
EIA-485/EIA-422 Quad Differential Drivers
General Description
Features
The DS96F172 and the DS96F174 are high speed quad dif-
ferential line drivers designed to meet EIA-485 Standards.
The DS96F172 and the DS96F174 offer improved perfor-
mance due to the use of L-FAST bipolar technology. The use
of LFAST technology allows the DS96F172 and DS96F174
to operate at higher speeds while minimizing power con-
sumption.
Meets EIA-485 and EIA-422 standards
■
■
■
■
Monotonic differential output switching
TRI-STATE outputs
Designed for multipoint bus transmission
Common mode output voltage range: −7.0V to +12V
Operates from single +5.0V supply
Reduced power consumption
■
■
■
■
■
The DS96F172 and the DS96F174 have TRI-STATE® out-
puts and are optimized for balanced multipoint data bus trans-
mission at rates up to 15 Mbps. The drivers have wide positive
and negative common mode range for multipoint applications
in noisy environments. Positive and negative current-limiting
is provided which protects the drivers from line fault conditions
over a +12V to −7.0V common mode range. A thermal shut-
down feature is also provided. The DS96F172 features an
active high and active low Enable, common to all four drivers.
The DS96F174 features separate active high Enables for
each driver pair.
Thermal shutdown protection
DS96F172 and DS96F174 are lead and function
compatible with the SN75172/174 or the AM26LS31/
MC3487
Ordering Information
NS Part Number
DS96F172ME/883
SMD Part Number
5962-9076501M2A
5962-9076501MEA
5962-9076502M2A
5962-9076502MEA
5962-9076502VEA
NS Package Number
Package Description
20LD Leadless Chip Carrier
16LD Ceramic Dip
E20A
J16A
E20A
J16A
J16A
DS96F172MJ/883
DS96F174ME/883
DS96F174MJ/883
DS96F174MJ-QMLV
20LD Leadless Chip Carrier
16LD Ceramic Dip
16LD Ceramic Dip
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2011 National Semiconductor Corporation
201640
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Connection Diagrams
16-Lead Ceramic Dual-In-Line Package (NS Package Number J16A)
DS96F172
DS96F174
20164001
20164002
Top View
Top View
20-Lead Ceramic Leadless Chip Carrier (NS Package Number E20A)
20164018
20164019
NC = No connection
Top View
Top View
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2
Logic Diagrams
DS96F172
DS96F174
20164014
20164015
DS96F174
Enable
Function Tables
Input
Outputs
DS96F172
A
H
L
E
H
H
L
Y
H
L
Z
L
(Each Driver)
Input
Enable
Outputs
H
Z
A
H
L
E
H
H
X
X
L
E
X
X
L
Y
H
L
Z
L
X
Z
H = High Level
L = Low Level
X = Don't Care
Z = High Impedance (Off)
H
L
H
L
H
L
L
H
Z
X
H
Z
3
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Absolute Maximum Ratings (Note 1)
Storage Temperature Range (TStg
)
−65°C ≤ TA ≤ +175°C
Lead Temperature (Soldering, 60 sec.)
Maximum Package Power Dissipation at 25°C (Note 2)
Ceramic LCC (E)
Ceramic DIP (J)
Ceramic Flatpak (W)
300°C
2,000 mW
1,800 mW
1,000 mW
7.0V
Supply Voltage
Enable Input Voltage
5.5V
Recommended Operating Conditions
Min
4.50
−7.0
Max
5.50
+12.0
−60
Units
V
Supply Voltage (VCC
Common Mode Output Voltage (VOC
Output Current High (IOH
Output Current Low (IOL
Operating Temperature (TA)
)
)
V
)
mA
mA
°C
)
60
−55
+125
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Static tests at
Temp (°C)
1
2
+25
+125
-55
Static tests at
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling time at
Settling time at
Settling time at
+25
+125
-55
5
6
7
+25
+125
-55
8A
8B
9
+25
+125
-55
10
11
12
13
14
+25
+125
-55
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4
DS96F172/DS96F174 Electrical Characteristics
AC/DC Parameters
(Note 5)
The following conditions apply, unless otherwise specified.
DC:
AC:
VCC = 5.5V
VCC = 5.0V
Sub-
groups
Symbol
Parameter
Conditions
Notes
Min Max
Unit
0.8
0.7
V
V
V
V
V
V
V
V
1
VIL
Logical 0 Input Voltage
2, 3
VIH
Logical 1 Input Voltage
Input Clamp Voltage
2.0
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
VIC
I = -18mA
IO = 0mA
-1.5
6.0
VOD1
Differential Output Voltage
1.5
VCC = 4.5V, RL = 54Ω
Figure 1
VOD2
VOD2
Differential Output Voltage
Differential Output Voltage
(Note 3)
(Note 6)
1.2
3
2.0
1, 2, 3
VCC = 4.5V, RL = 100Ω
Figure 1
-200 200
-400 400
mV
mV
1, 2
3
Change In Magnitude of VOD2
ΔVOD1
VCC = 4.5V, RL = 54Ω
VCC = 4.5V, RL = 100Ω
(Note 3,
Note 6)
(Note 6)
-200 200
-400 400
mV
mV
1, 2
3
Change In Magnitude of VOD2
Common Mode Output Voltage
Common Mode Output Voltage
Change in Magnitude of VOC
Change in Magnitude of VOC
ΔVOD2
VOC
(Note 3,
Note 6)
3.0
3.0
V
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
RL = 54Ω
Figure 1
VOC
RL = 100Ω
Figure 1
-200 200
-200 200
mV
mV
ΔVOC
ΔVOC
VCC = 4.5V, RL = 54Ω
Figure 1
(Note 6)
(Note 7)
VCC = 4.5V, RL = 100Ω
Figure 1
IO
Output Current With Power Off VCC = 0V, VO = -7V to 12V
-50
-50
50
50
20
µA
µA
1, 2, 3
1, 2, 3
High Impedance State Output
VO = -7V to 12V
IOZ
Current
IIH
Logical 1 Input Current
Logical 0 Input Current
Supply Current
VI = 2.4V
µA
µA
mA
mA
mA
mA
mA
mA
ns
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
10, 11
9
IIL
VI = 0.4V
-50
ICC
Outputs Enabled
Outputs Disabled
VO = -7V
50
30
ICCX
IOS1
IOS2
IOS3
IOS4
Supply Current
Short Circuit Output Current
Short Circuit Output Current
Short Circuit Output Current
Short Circuit Output Current
(Note 4)
(Note 4)
(Note 4)
(Note 4)
-250
-150
VO = 0V
VO = VCC
150
250
25
16
25
16
10
4
VO = 12V
RL = 27Ω, CL = 15pF
Figure 4
tPLH
Propagation Delay Lo to Hi level
ns
ns
10, 11
9
Propagation Delay Hi to Low
Level
RL = 27Ω, CL = 15pF
Figure 4
tPHL
ns
ns
10, 11
9
RL = 60Ω
SKEW
tLZ
Output to Output Delay Time
ns
Output Disable Time From Low
Level
40
25
ns
10, 11
9
RL = 110Ω, CL = 50pF
Figure 6
ns
5
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Sub-
groups
Symbol
tHZ
Parameter
Conditions
Notes
Min Max
Unit
Output Disable Time From High
Level
80
30
100
40
40
32
30
22
40
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10, 11
RL = 110Ω, CL = 50pF
Figure 5
9
10, 11
9
Output Enable Time to Low Level
RL = 110Ω, CL = 50pF
tZL
tZH
tDD
tTD
Figure 6
Output Enable Time to High Level
10, 11
9
RL = 110Ω, CL = 50pF
Figure 4
10, 11
9
RL = 60Ω, CL = 15pF
Differential Output Delay Time
Figure 3
Differential Output Transition
Time
10, 11
9
RL = 60Ω, CL = 15pF
Figure 3
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: Above TA = 25°C, derate “E” package 13.3, “J” package 12.5, “W” package 7.1 mW/°C
Note 3: −55°C limit exceeds EIA standard RS−485 specification
Note 4: 0.2µF cap is connected between the output and Gnd to reduce oscillation.
Note 5: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are reference to ground unless otherwise specified.
Note 6: Δ|VOD| is the change in magnitude of VOD, that occurs when the input is changed between high and low levels.
Note 7: Δ|VOC| is the change in magnitude of the VOC that occurs when the input is changed between high and low levels.
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6
Parameter Measurement Information
20164013
20164003
FIGURE 2. Differential Output Voltage with
Varying Common Mode Voltage
FIGURE 1. Differential and Common
Mode Output Voltage
20164005
20164004
FIGURE 3. Differential Output Delay and Transition Times
20164006
20164007
FIGURE 4. Propagation Delay Times
7
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20164009
20164008
FIGURE 5. tZH and tHZ
20164011
FI2G01U64R010E 6. tZL, tLZ, tLZL
Note 8: The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, duty cycle = 50%, tr ≤ 5.0 ns, tf ≤ 5.0 ns, ZO = 50Ω.
Note 9: CL includes probe and jig capacitance.
Note 10: DS96F172 with active high and active low Enables is shown. DS96F174 has active high Enable only.
Note 11: To test the active low Enable E of DS96F172 ground E and apply an inverted waveform to E . DS96F174 has active high Enable only.
Note 12: For more information see Application Bulletin, Contact Product Marketing.
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8
Typical Application
20164012
The line length should be terminated at both ends in its characteristic impedance.
Stub lengths off the main line should be kept as short as possible.
9
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Revision History
Released
Revision
Section
Changes
8–Apr-11
A
New Release, Corporate format
2 MDS data sheets converted into one Corp. data
sheet format. MNDS96F172M-X Rev 1A0 &
MNDS96F174M-X Rev 1B0 will be archived.
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10
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Ceramic Leadless Chip Carrier (E)
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (J)
NS Package Number J16A
11
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